* [PATCH v1 06/32] perf vendor events intel: Refresh broadwellde metrics and events
@ 2022-12-15 6:49 Ian Rogers
2022-12-15 6:49 ` [PATCH v1 07/32] perf vendor events intel: Refresh broadwellx " Ian Rogers
2022-12-15 6:49 ` [PATCH v1 08/32] perf vendor events intel: Refresh cascadelakex " Ian Rogers
0 siblings, 2 replies; 3+ messages in thread
From: Ian Rogers @ 2022-12-15 6:49 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the broadwellde metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics vary as tma_false_sharing, MEM_Parallel_Requests and
MEM_Request_Latency are explicitly dropped from having missing events:
https://github.com/captain5050/perfmon/blob/main/scripts/create_perf_json.py#L934
The formulas also differ due to parentheses, use of exponents and
removal of redundant operations like "* 1". The events are unchanged
but unused json values are removed and implicit umasks of 0 are
dropped. This increases consistency across the json files.
mapfile.csv's version number is set to match that in the perfmon
repository.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/broadwellde/bdwde-metrics.json | 143 +++---
.../arch/x86/broadwellde/cache.json | 153 ------
.../arch/x86/broadwellde/floating-point.json | 40 --
.../arch/x86/broadwellde/frontend.json | 56 --
.../arch/x86/broadwellde/memory.json | 86 ----
.../arch/x86/broadwellde/other.json | 8 -
.../arch/x86/broadwellde/pipeline.json | 272 ----------
.../arch/x86/broadwellde/uncore-cache.json | 414 ++-------------
.../arch/x86/broadwellde/uncore-memory.json | 477 +++---------------
.../arch/x86/broadwellde/uncore-other.json | 163 ++----
.../arch/x86/broadwellde/uncore-power.json | 57 ---
.../arch/x86/broadwellde/virtual-memory.json | 76 ---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
13 files changed, 211 insertions(+), 1736 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json
index 5a074cf7c77d..d35d30932b68 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json
@@ -113,7 +113,7 @@
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
"MetricGroup": "TopdownL1;tma_L1_group",
"MetricName": "tma_bad_speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
@@ -121,7 +121,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
"MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
"MetricName": "tma_branch_mispredicts",
"PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS",
@@ -145,7 +145,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound",
"MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
"MetricName": "tma_memory_bound",
"PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
@@ -177,7 +177,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
+ "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
"MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
"MetricName": "tma_lock_latency",
"PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
@@ -217,7 +217,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_l3_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@@ -225,7 +225,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
+ "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS",
"MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_contested_accesses",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -233,7 +233,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
+ "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_data_sharing",
"PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
@@ -241,7 +241,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
+ "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS",
"MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_l3_hit_latency",
"PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
@@ -249,7 +249,7 @@
},
{
"BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+ "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
"MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
"MetricName": "tma_sq_full",
"PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
@@ -257,7 +257,7 @@
},
{
"BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
+ "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
"MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
"MetricName": "tma_dram_bound",
"PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
@@ -289,20 +289,12 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
"MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
"MetricName": "tma_store_latency",
"PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
"ScaleUnit": "100%"
},
- {
- "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
- "MetricExpr": "60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_false_sharing",
- "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "ScaleUnit": "100%"
- },
{
"BriefDescription": "This metric represents rate of split store accesses",
"MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
@@ -337,7 +329,7 @@
},
{
"BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
+ "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
"MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
"MetricName": "tma_ports_utilization",
"PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
@@ -345,7 +337,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_0",
"PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
@@ -353,7 +345,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_1",
"PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL",
@@ -361,7 +353,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_2",
"PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL",
@@ -369,7 +361,7 @@
},
{
"BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
"MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
"MetricName": "tma_ports_utilized_3m",
"PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3",
@@ -377,7 +369,7 @@
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_alu_op_utilization",
"ScaleUnit": "100%"
@@ -433,7 +425,7 @@
},
{
"BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations Sample with: UOPS_DISPATCHED.PORT_7_8",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+ "MetricExpr": "tma_port_4",
"MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
"MetricName": "tma_store_op_utilization",
"ScaleUnit": "100%"
@@ -526,7 +518,7 @@
},
{
"BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
"MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
"MetricName": "tma_microcode_sequencer",
"PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS",
@@ -599,26 +591,26 @@
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
"MetricGroup": "Flops;Ret",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
- "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "FP_Arith_Utilization",
"PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
},
{
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
"MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP"
},
{
"BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
+ "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
"MetricGroup": "SMT",
"MetricName": "CORE_CLKS"
},
@@ -660,13 +652,13 @@
},
{
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
"MetricGroup": "Flops;InsType",
"MetricName": "IpFLOP"
},
{
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
"MetricGroup": "Flops;InsType",
"MetricName": "IpArith",
"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
@@ -719,7 +711,7 @@
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
"MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage"
},
@@ -731,13 +723,13 @@
},
{
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
- "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricGroup": "Bad;BrMispredicts",
"MetricName": "Branch_Misprediction_Cost"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
"MetricGroup": "Mem;MemoryBound;MemoryLat",
"MetricName": "Load_Miss_Real_Latency"
},
@@ -749,68 +741,68 @@
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L1MPKI"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Backend;CacheMisses;Mem",
"MetricName": "L2MPKI"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem;Offcore",
"MetricName": "L2MPKI_All"
},
{
"BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2MPKI_Load"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_All"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L2HPKI_Load"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricGroup": "CacheMisses;Mem",
"MetricName": "L3MPKI"
},
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricConstraint": "NO_NMI_WATCHDOG",
- "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) if #core_wide < 1 else ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CPU_CLK_UNHALTED.THREAD) )",
+ "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * CORE_CLKS)",
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "Page_Walks_Utilization"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW"
},
@@ -840,19 +832,19 @@
},
{
"BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
"MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization"
},
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
"MetricGroup": "Power;Summary",
"MetricName": "Average_Frequency"
},
{
"BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs",
"PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
@@ -865,7 +857,7 @@
},
{
"BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
"MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization"
},
@@ -883,22 +875,10 @@
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",
+ "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1e6 / duration_time / 1e3",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
- {
- "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)",
- "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
- "MetricGroup": "Mem;SoC",
- "MetricName": "MEM_Request_Latency"
- },
- {
- "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",
- "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",
- "MetricGroup": "Mem;SoC",
- "MetricName": "MEM_Parallel_Requests"
- },
{
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
@@ -907,44 +887,51 @@
},
{
"BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "MetricName": "C3_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
"BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
"MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json
index 4b77181b2c53..fcc99fd22b0a 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "L1D data line replacements",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "L1D miss oustandings duration in cycles",
- "Counter": "2",
- "CounterHTOff": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -53,8 +43,6 @@
},
{
"BriefDescription": "Not rejected writebacks that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_DEMAND_RQSTS.WB_HIT",
"PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
@@ -63,8 +51,6 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@@ -73,8 +59,6 @@
},
{
"BriefDescription": "L2 cache lines in E state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",
@@ -83,8 +67,6 @@
},
{
"BriefDescription": "L2 cache lines in I state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",
@@ -93,8 +75,6 @@
},
{
"BriefDescription": "L2 cache lines in S state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.",
@@ -103,8 +83,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100003",
@@ -112,8 +90,6 @@
},
{
"BriefDescription": "L2 code requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "This event counts the total number of L2 code requests.",
@@ -122,8 +98,6 @@
},
{
"BriefDescription": "Demand Data Read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@@ -132,8 +106,6 @@
},
{
"BriefDescription": "Demand requests that miss L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"SampleAfterValue": "200003",
@@ -141,8 +113,6 @@
},
{
"BriefDescription": "Demand requests to L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"SampleAfterValue": "200003",
@@ -150,8 +120,6 @@
},
{
"BriefDescription": "Requests from L2 hardware prefetchers",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.",
@@ -160,8 +128,6 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@@ -170,8 +136,6 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"SampleAfterValue": "200003",
@@ -179,8 +143,6 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"SampleAfterValue": "200003",
@@ -188,8 +150,6 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.",
@@ -198,8 +158,6 @@
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@@ -208,8 +166,6 @@
},
{
"BriefDescription": "L2 prefetch requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_HIT",
"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.",
@@ -218,8 +174,6 @@
},
{
"BriefDescription": "L2 prefetch requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_MISS",
"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.",
@@ -228,8 +182,6 @@
},
{
"BriefDescription": "All requests that miss L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200003",
@@ -237,8 +189,6 @@
},
{
"BriefDescription": "All L2 requests.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200003",
@@ -246,8 +196,6 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200003",
@@ -255,8 +203,6 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200003",
@@ -264,8 +210,6 @@
},
{
"BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_PF",
"PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.",
@@ -274,8 +218,6 @@
},
{
"BriefDescription": "Transactions accessing L2 pipe",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.",
@@ -284,8 +226,6 @@
},
{
"BriefDescription": "L2 cache accesses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.CODE_RD",
"PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.",
@@ -294,8 +234,6 @@
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.",
@@ -304,8 +242,6 @@
},
{
"BriefDescription": "L1D writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L1D_WB",
"PublicDescription": "This event counts L1D writebacks that access L2 cache.",
@@ -314,8 +250,6 @@
},
{
"BriefDescription": "L2 fill requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_FILL",
"PublicDescription": "This event counts L2 fill requests that access L2 cache.",
@@ -324,8 +258,6 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "This event counts L2 writebacks that access L2 cache.",
@@ -334,8 +266,6 @@
},
{
"BriefDescription": "RFO requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.RFO",
"PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
@@ -344,8 +274,6 @@
},
{
"BriefDescription": "Cycles when L1D is locked",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
@@ -354,8 +282,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@@ -364,8 +290,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@@ -374,8 +298,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@@ -387,8 +309,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@@ -400,8 +320,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@@ -413,8 +331,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@@ -425,8 +341,6 @@
"UMask": "0x8"
},
{
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70, BDM100",
"EventCode": "0xD3",
@@ -438,8 +352,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
@@ -450,8 +362,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
@@ -462,8 +372,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
@@ -474,8 +382,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
@@ -486,8 +392,6 @@
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
@@ -498,8 +402,6 @@
},
{
"BriefDescription": "Retired load uops misses in L1 cache as data sources. Uses PEBS.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
@@ -510,8 +412,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM35",
"EventCode": "0xD1",
@@ -523,8 +423,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache misses as data sources. Uses PEBS.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
@@ -535,8 +433,6 @@
},
{
"BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD1",
@@ -548,8 +444,6 @@
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100, BDE70",
"EventCode": "0xD1",
@@ -560,8 +454,6 @@
},
{
"BriefDescription": "All retired load uops. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
@@ -572,12 +464,9 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
"SampleAfterValue": "2000003",
@@ -585,8 +474,6 @@
},
{
"BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM35",
"EventCode": "0xD0",
@@ -598,8 +485,6 @@
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
@@ -610,12 +495,9 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
"SampleAfterValue": "100003",
@@ -623,8 +505,6 @@
},
{
"BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
@@ -635,12 +515,9 @@
},
{
"BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
"SampleAfterValue": "100003",
@@ -648,8 +525,6 @@
},
{
"BriefDescription": "Demand and prefetch data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@@ -658,8 +533,6 @@
},
{
"BriefDescription": "Cacheable and noncachaeble code read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",
@@ -668,8 +541,6 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@@ -678,8 +549,6 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@@ -688,8 +557,6 @@
},
{
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",
@@ -698,8 +565,6 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
@@ -709,8 +574,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
@@ -721,8 +584,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
@@ -733,8 +594,6 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
@@ -745,8 +604,6 @@
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
@@ -756,8 +613,6 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
@@ -767,8 +622,6 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"Errata": "BDM76",
"EventCode": "0x60",
@@ -778,8 +631,6 @@
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
@@ -789,8 +640,6 @@
},
{
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100003",
@@ -798,8 +647,6 @@
},
{
"BriefDescription": "Split locks in SQ",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"PublicDescription": "This event counts the number of split locks in the super queue.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json
index 46cf18490140..0b3f026158e2 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"SampleAfterValue": "2000003",
@@ -19,8 +15,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"SampleAfterValue": "2000003",
@@ -28,8 +22,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"SampleAfterValue": "2000003",
@@ -37,8 +29,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
"SampleAfterValue": "2000006",
@@ -46,8 +36,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.PACKED",
"SampleAfterValue": "2000004",
@@ -55,8 +43,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"SampleAfterValue": "2000003",
@@ -64,8 +50,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000003",
@@ -73,8 +57,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000003",
@@ -82,8 +64,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
"SampleAfterValue": "2000005",
@@ -91,8 +71,6 @@
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
@@ -102,8 +80,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to input values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
@@ -112,8 +88,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
@@ -122,8 +96,6 @@
},
{
"BriefDescription": "Number of X87 assists due to input value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
@@ -132,8 +104,6 @@
},
{
"BriefDescription": "Number of X87 assists due to output value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
@@ -142,8 +112,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -151,8 +119,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -160,8 +126,6 @@
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
@@ -171,8 +135,6 @@
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
@@ -182,8 +144,6 @@
},
{
"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json
index 37ce8034b2ed..d0f6678609ae 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
@@ -30,8 +24,6 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFDATA_STALL",
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
@@ -40,8 +32,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
@@ -50,8 +40,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -72,8 +58,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -83,8 +67,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -94,8 +76,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@@ -105,8 +85,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
@@ -115,8 +93,6 @@
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
@@ -125,8 +101,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -135,8 +109,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@@ -146,8 +118,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -156,8 +126,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@@ -167,8 +135,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@@ -178,8 +144,6 @@
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -190,8 +154,6 @@
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
@@ -200,8 +162,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
@@ -210,8 +170,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -221,8 +179,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
@@ -231,8 +187,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
@@ -241,8 +195,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -252,8 +204,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -263,8 +213,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -274,8 +222,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -284,8 +230,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json
index a3a5cc6dab42..12cc384d7f18 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Number of times HLE abort was triggered (PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
@@ -12,8 +10,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
@@ -42,8 +34,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times HLE caused a fault.",
@@ -52,8 +42,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
@@ -62,8 +50,6 @@
},
{
"BriefDescription": "Number of times HLE commit succeeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.COMMIT",
"PublicDescription": "Number of times HLE commit succeeded.",
@@ -72,8 +58,6 @@
},
{
"BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.START",
"PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
@@ -92,8 +74,6 @@
},
{
"BriefDescription": "Loads with latency value being above 128",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
@@ -102,13 +82,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 128.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 16",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
@@ -117,13 +94,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 16.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 256",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
@@ -132,13 +106,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 256.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 32",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
@@ -147,13 +118,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 32.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 4",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
@@ -162,13 +130,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above four.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 512",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
@@ -177,13 +142,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 512.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 64",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
@@ -192,13 +154,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 64.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Loads with latency value being above 8",
- "Counter": "3",
- "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
@@ -207,13 +166,10 @@
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above eight.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
@@ -222,8 +178,6 @@
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
@@ -232,8 +186,6 @@
},
{
"BriefDescription": "Number of times RTM abort was triggered (PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
@@ -243,8 +195,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@@ -253,8 +203,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
@@ -263,8 +211,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
@@ -273,8 +219,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times a RTM caused a fault.",
@@ -283,8 +227,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
@@ -293,8 +235,6 @@
},
{
"BriefDescription": "Number of times RTM commit succeeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
"PublicDescription": "Number of times RTM commit succeeded.",
@@ -303,8 +243,6 @@
},
{
"BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
"PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
@@ -313,8 +251,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003",
@@ -322,8 +258,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
@@ -332,8 +266,6 @@
},
{
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@@ -342,8 +274,6 @@
},
{
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4",
"PublicDescription": "RTM region detected inside HLE.",
@@ -352,8 +282,6 @@
},
{
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5",
"SampleAfterValue": "2000003",
@@ -361,8 +289,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
@@ -371,8 +297,6 @@
},
{
"BriefDescription": "Number of times a TSX line had a cache conflict",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"PublicDescription": "Number of times a TSX line had a cache conflict.",
@@ -381,8 +305,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@@ -391,8 +313,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@@ -401,8 +321,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@@ -411,8 +329,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@@ -421,8 +337,6 @@
},
{
"BriefDescription": "Number of times we could not allocate Lock Buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"PublicDescription": "Number of times we could not allocate Lock Buffer.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/other.json b/tools/perf/pmu-events/arch/x86/broadwellde/other.json
index 917d145d5227..1c2a5b001949 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/other.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/other.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
@@ -23,8 +19,6 @@
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
@@ -33,8 +27,6 @@
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json
index 85654037b768..9e7d66b07f01 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles when divider is busy executing divide operations",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x14",
"EventName": "ARITH.FPU_DIV_ACTIVE",
"PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Speculative and retired branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Speculative and retired macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "Speculative and retired direct near calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.",
@@ -51,8 +41,6 @@
},
{
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "Speculative and retired indirect return branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.",
@@ -71,8 +57,6 @@
},
{
"BriefDescription": "Not taken macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "This event counts not taken macro-conditional branch instructions.",
@@ -81,8 +65,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.",
@@ -91,8 +73,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.",
@@ -101,8 +81,6 @@
},
{
"BriefDescription": "Taken speculative and retired direct near calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"PublicDescription": "This event counts taken speculative and retired direct near calls.",
@@ -111,8 +89,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.",
@@ -121,8 +97,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.",
@@ -131,8 +105,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.",
@@ -141,8 +113,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PublicDescription": "This event counts all (macro) branch instructions retired.",
@@ -150,8 +120,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDW98",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
@@ -162,8 +130,6 @@
},
{
"BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -173,8 +139,6 @@
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDW98",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
@@ -184,8 +148,6 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -195,8 +157,6 @@
},
{
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"PEBS": "1",
@@ -206,8 +166,6 @@
},
{
"BriefDescription": "Return instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
@@ -217,8 +175,6 @@
},
{
"BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -228,8 +184,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"PublicDescription": "This event counts not taken branch instructions retired.",
@@ -238,8 +192,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.",
@@ -248,8 +200,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -258,8 +208,6 @@
},
{
"BriefDescription": "Mispredicted indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.",
@@ -268,8 +216,6 @@
},
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -278,8 +224,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -288,8 +232,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.",
@@ -298,8 +240,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -307,8 +247,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.",
@@ -317,8 +255,6 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "This event counts all mispredicted macro branch instructions retired.",
@@ -326,8 +262,6 @@
},
{
"BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -337,8 +271,6 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -348,8 +280,6 @@
},
{
"BriefDescription": "number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -359,8 +289,6 @@
},
{
"BriefDescription": "This event counts the number of mispredicted ret instructions retired.(Precise Event)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1",
@@ -370,8 +298,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -379,8 +305,6 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.",
@@ -390,8 +314,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -399,8 +321,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "2000003",
@@ -408,8 +328,6 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
@@ -417,8 +335,6 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
@@ -428,8 +344,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "2000003",
@@ -437,8 +351,6 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
@@ -447,16 +359,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@@ -465,16 +373,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -483,8 +387,6 @@
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -494,8 +396,6 @@
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -504,8 +404,6 @@
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -515,8 +413,6 @@
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -526,8 +422,6 @@
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -536,8 +430,6 @@
},
{
"BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -547,8 +439,6 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -557,8 +447,6 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -568,8 +456,6 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -578,8 +464,6 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -589,8 +473,6 @@
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -600,8 +482,6 @@
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -610,8 +490,6 @@
},
{
"BriefDescription": "Total execution stalls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -620,8 +498,6 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
@@ -630,8 +506,6 @@
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
"SampleAfterValue": "2000003",
@@ -639,8 +513,6 @@
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM61",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
@@ -649,8 +521,6 @@
},
{
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
- "Counter": "1",
- "CounterHTOff": "1",
"Errata": "BDM11, BDM55",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
@@ -661,8 +531,6 @@
},
{
"BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
@@ -671,8 +539,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RAT_STALL_CYCLES",
"PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",
@@ -681,8 +547,6 @@
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -693,8 +557,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -703,8 +565,6 @@
},
{
"BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"SampleAfterValue": "100003",
@@ -712,8 +572,6 @@
},
{
"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",
@@ -722,8 +580,6 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
@@ -732,8 +588,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.HW_PF",
"PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.",
@@ -742,8 +596,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.",
@@ -752,8 +604,6 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@@ -762,8 +612,6 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -772,8 +620,6 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"SampleAfterValue": "2000003",
@@ -781,8 +627,6 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xC3",
@@ -792,8 +636,6 @@
},
{
"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",
@@ -802,8 +644,6 @@
},
{
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV",
"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
@@ -812,8 +652,6 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.",
@@ -822,8 +660,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -831,8 +667,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -840,8 +674,6 @@
},
{
"BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
"SampleAfterValue": "100003",
@@ -849,8 +681,6 @@
},
{
"BriefDescription": "Resource-related stall cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ANY",
"PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -859,8 +689,6 @@
},
{
"BriefDescription": "Cycles stalled due to re-order buffer full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB",
"PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -869,8 +697,6 @@
},
{
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS",
"PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -879,8 +705,6 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -889,8 +713,6 @@
},
{
"BriefDescription": "Count cases of saving new LBR",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.",
@@ -899,8 +721,6 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
@@ -909,8 +729,6 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -921,8 +739,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
@@ -931,8 +747,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
@@ -941,8 +755,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
@@ -951,8 +763,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
@@ -961,8 +771,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
@@ -971,8 +779,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
@@ -981,8 +787,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_6",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
@@ -991,8 +795,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_7",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
@@ -1001,8 +803,6 @@
},
{
"BriefDescription": "Number of uops executed on the core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
"PublicDescription": "Number of uops executed from any thread.",
@@ -1011,8 +811,6 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1021,8 +819,6 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1031,8 +827,6 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1041,8 +835,6 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1051,8 +843,6 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
"Invert": "1",
@@ -1061,8 +851,6 @@
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -1071,8 +859,6 @@
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -1081,8 +867,6 @@
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -1091,8 +875,6 @@
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -1101,8 +883,6 @@
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -1113,8 +893,6 @@
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.THREAD",
"PublicDescription": "Number of uops to be executed per-thread each cycle.",
@@ -1123,8 +901,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
@@ -1134,8 +910,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
"SampleAfterValue": "2000003",
@@ -1143,8 +917,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
@@ -1154,8 +926,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 1.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003",
@@ -1163,8 +933,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
@@ -1174,8 +942,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
@@ -1183,8 +949,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
@@ -1194,8 +958,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003",
@@ -1203,8 +965,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
@@ -1214,8 +974,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 4.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003",
@@ -1223,8 +981,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
@@ -1234,8 +990,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 5.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003",
@@ -1243,8 +997,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
@@ -1254,8 +1006,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 6.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
"SampleAfterValue": "2000003",
@@ -1263,8 +1013,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
@@ -1274,8 +1022,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 7.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
"SampleAfterValue": "2000003",
@@ -1283,8 +1029,6 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",
@@ -1293,8 +1037,6 @@
},
{
"BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.FLAGS_MERGE",
"PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.",
@@ -1303,8 +1045,6 @@
},
{
"BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SINGLE_MUL",
"SampleAfterValue": "2000003",
@@ -1312,8 +1052,6 @@
},
{
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA",
"SampleAfterValue": "2000003",
@@ -1321,8 +1059,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1333,8 +1069,6 @@
},
{
"BriefDescription": "Actually retired uops. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Data_LA": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
@@ -1345,8 +1079,6 @@
},
{
"BriefDescription": "Retirement slots used. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -1356,8 +1088,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1368,8 +1098,6 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "10",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json
index c4d154944ab6..b8c9845308b2 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Bounce Control",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_C_BOUNCE_CONTROL",
"PerPkg": "1",
@@ -9,14 +8,12 @@
},
{
"BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
"EventName": "UNC_C_CLOCKTICKS",
"PerPkg": "1",
"Unit": "CBO"
},
{
"BriefDescription": "Counter 0 Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_C_COUNTER0_OCCUPANCY",
"PerPkg": "1",
@@ -25,7 +22,6 @@
},
{
"BriefDescription": "FaST wire asserted",
- "Counter": "0,1",
"EventCode": "0x9",
"EventName": "UNC_C_FAST_ASSERTED",
"PerPkg": "1",
@@ -34,7 +30,6 @@
},
{
"BriefDescription": "Cache Lookups; Any Request",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.ANY",
"PerPkg": "1",
@@ -44,7 +39,6 @@
},
{
"BriefDescription": "Cache Lookups; Data Read Request",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
@@ -54,7 +48,6 @@
},
{
"BriefDescription": "Cache Lookups; Lookups that Match NID",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.NID",
"PerPkg": "1",
@@ -64,7 +57,6 @@
},
{
"BriefDescription": "Cache Lookups; Any Read Request",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.READ",
"PerPkg": "1",
@@ -74,7 +66,6 @@
},
{
"BriefDescription": "Cache Lookups; External Snoop Request",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
@@ -84,7 +75,6 @@
},
{
"BriefDescription": "Cache Lookups; Write Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_C_LLC_LOOKUP.WRITE",
"PerPkg": "1",
@@ -94,7 +84,6 @@
},
{
"BriefDescription": "Lines Victimized; Lines in E state",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
@@ -104,7 +93,6 @@
},
{
"BriefDescription": "Lines Victimized",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.F_STATE",
"PerPkg": "1",
@@ -114,7 +102,6 @@
},
{
"BriefDescription": "Lines Victimized; Lines in S State",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.I_STATE",
"PerPkg": "1",
@@ -124,7 +111,6 @@
},
{
"BriefDescription": "Lines Victimized",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.MISS",
"PerPkg": "1",
@@ -134,7 +120,6 @@
},
{
"BriefDescription": "Lines Victimized; Lines in M state",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
@@ -144,7 +129,6 @@
},
{
"BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_C_LLC_VICTIMS.NID",
"PerPkg": "1",
@@ -154,7 +138,6 @@
},
{
"BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
"PerPkg": "1",
@@ -164,7 +147,6 @@
},
{
"BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
"PerPkg": "1",
@@ -174,7 +156,6 @@
},
{
"BriefDescription": "Cbo Misc; RFO HitS",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.RFO_HIT_S",
"PerPkg": "1",
@@ -184,7 +165,6 @@
},
{
"BriefDescription": "Cbo Misc; Silent Snoop Eviction",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
@@ -194,7 +174,6 @@
},
{
"BriefDescription": "Cbo Misc",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.STARTED",
"PerPkg": "1",
@@ -204,7 +183,6 @@
},
{
"BriefDescription": "Cbo Misc; Write Combining Aliasing",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_C_MISC.WC_ALIASING",
"PerPkg": "1",
@@ -214,7 +192,6 @@
},
{
"BriefDescription": "LRU Queue; LRU Age 0",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE0",
"PerPkg": "1",
@@ -224,7 +201,6 @@
},
{
"BriefDescription": "LRU Queue; LRU Age 1",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE1",
"PerPkg": "1",
@@ -234,7 +210,6 @@
},
{
"BriefDescription": "LRU Queue; LRU Age 2",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE2",
"PerPkg": "1",
@@ -244,7 +219,6 @@
},
{
"BriefDescription": "LRU Queue; LRU Age 3",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.AGE3",
"PerPkg": "1",
@@ -254,7 +228,6 @@
},
{
"BriefDescription": "LRU Queue; LRU Bits Decremented",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.LRU_DECREMENT",
"PerPkg": "1",
@@ -264,7 +237,6 @@
},
{
"BriefDescription": "LRU Queue; Non-0 Aged Victim",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
"PerPkg": "1",
@@ -274,27 +246,24 @@
},
{
"BriefDescription": "AD Ring In Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
"BriefDescription": "AD Ring In Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "AD Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.CW",
"PerPkg": "1",
@@ -304,7 +273,6 @@
},
{
"BriefDescription": "AD Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
"PerPkg": "1",
@@ -314,7 +282,6 @@
},
{
"BriefDescription": "AD Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
"PerPkg": "1",
@@ -324,7 +291,6 @@
},
{
"BriefDescription": "AD Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.UP_EVEN",
"PerPkg": "1",
@@ -334,7 +300,6 @@
},
{
"BriefDescription": "AD Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_C_RING_AD_USED.UP_ODD",
"PerPkg": "1",
@@ -344,27 +309,24 @@
},
{
"BriefDescription": "AK Ring In Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.CW",
"PerPkg": "1",
@@ -374,7 +336,6 @@
},
{
"BriefDescription": "AK Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
"PerPkg": "1",
@@ -384,7 +345,6 @@
},
{
"BriefDescription": "AK Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
"PerPkg": "1",
@@ -394,7 +354,6 @@
},
{
"BriefDescription": "AK Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.UP_EVEN",
"PerPkg": "1",
@@ -404,7 +363,6 @@
},
{
"BriefDescription": "AK Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.UP_ODD",
"PerPkg": "1",
@@ -414,27 +372,24 @@
},
{
"BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.CW",
"PerPkg": "1",
@@ -444,7 +399,6 @@
},
{
"BriefDescription": "BL Ring in Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
"PerPkg": "1",
@@ -454,7 +408,6 @@
},
{
"BriefDescription": "BL Ring in Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
"PerPkg": "1",
@@ -464,7 +417,6 @@
},
{
"BriefDescription": "BL Ring in Use; Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.UP_EVEN",
"PerPkg": "1",
@@ -474,7 +426,6 @@
},
{
"BriefDescription": "BL Ring in Use; Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.UP_ODD",
"PerPkg": "1",
@@ -484,7 +435,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; AD",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AD",
"PerPkg": "1",
@@ -493,7 +443,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; AK",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AK",
"PerPkg": "1",
@@ -502,7 +451,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; BL",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.BL",
"PerPkg": "1",
@@ -511,7 +459,6 @@
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.IV",
"PerPkg": "1",
@@ -520,37 +467,33 @@
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.ANY",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.DN",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.DOWN",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity",
- "UMask": "0xCC",
+ "UMask": "0xcc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.UP",
"PerPkg": "1",
@@ -560,7 +503,6 @@
},
{
"BriefDescription": "AD",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.AD",
"PerPkg": "1",
@@ -569,7 +511,6 @@
},
{
"BriefDescription": "AK",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.AK",
"PerPkg": "1",
@@ -578,7 +519,6 @@
},
{
"BriefDescription": "BL",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.BL",
"PerPkg": "1",
@@ -587,7 +527,6 @@
},
{
"BriefDescription": "IV",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_C_RING_SINK_STARVED.IV",
"PerPkg": "1",
@@ -596,7 +535,6 @@
},
{
"BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_C_RING_SRC_THRTL",
"PerPkg": "1",
@@ -604,7 +542,6 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
"PerPkg": "1",
@@ -614,7 +551,6 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
"PerPkg": "1",
@@ -624,7 +560,6 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
"PerPkg": "1",
@@ -634,7 +569,6 @@
},
{
"BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
"PerPkg": "1",
@@ -644,7 +578,6 @@
},
{
"BriefDescription": "Ingress Allocations; IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IPQ",
"PerPkg": "1",
@@ -654,7 +587,6 @@
},
{
"BriefDescription": "Ingress Allocations; IRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ",
"PerPkg": "1",
@@ -664,7 +596,6 @@
},
{
"BriefDescription": "Ingress Allocations; IRQ Rejected",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
"PerPkg": "1",
@@ -674,7 +605,6 @@
},
{
"BriefDescription": "Ingress Allocations; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.PRQ",
"PerPkg": "1",
@@ -684,7 +614,6 @@
},
{
"BriefDescription": "Ingress Allocations; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.PRQ_REJ",
"PerPkg": "1",
@@ -694,7 +623,6 @@
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.IPQ",
"PerPkg": "1",
@@ -704,7 +632,6 @@
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.IRQ",
"PerPkg": "1",
@@ -714,7 +641,6 @@
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
"PerPkg": "1",
@@ -724,7 +650,6 @@
},
{
"BriefDescription": "Ingress Internal Starvation Cycles; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_C_RxR_INT_STARVED.PRQ",
"PerPkg": "1",
@@ -734,7 +659,6 @@
},
{
"BriefDescription": "Probe Queue Retries; Address Conflict",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
"PerPkg": "1",
@@ -744,7 +668,6 @@
},
{
"BriefDescription": "Probe Queue Retries; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
"PerPkg": "1",
@@ -754,7 +677,6 @@
},
{
"BriefDescription": "Probe Queue Retries; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
"PerPkg": "1",
@@ -764,7 +686,6 @@
},
{
"BriefDescription": "Probe Queue Retries; No QPI Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
@@ -774,7 +695,6 @@
},
{
"BriefDescription": "Probe Queue Retries; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO",
"PerPkg": "1",
@@ -784,7 +704,6 @@
},
{
"BriefDescription": "Probe Queue Retries; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET",
"PerPkg": "1",
@@ -794,7 +713,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
"PerPkg": "1",
@@ -804,7 +722,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
"PerPkg": "1",
@@ -814,7 +731,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
"PerPkg": "1",
@@ -824,7 +740,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
@@ -834,7 +749,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.NID",
"PerPkg": "1",
@@ -844,7 +758,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
@@ -854,7 +767,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
"PerPkg": "1",
@@ -864,7 +776,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO",
"PerPkg": "1",
@@ -874,7 +785,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO",
"PerPkg": "1",
@@ -884,7 +794,6 @@
},
{
"BriefDescription": "Ingress Request Queue Rejects; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET",
"PerPkg": "1",
@@ -894,7 +803,6 @@
},
{
"BriefDescription": "ISMQ Retries; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
"PerPkg": "1",
@@ -904,7 +812,6 @@
},
{
"BriefDescription": "ISMQ Retries; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
"PerPkg": "1",
@@ -914,7 +821,6 @@
},
{
"BriefDescription": "ISMQ Retries; No IIO Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
@@ -924,7 +830,6 @@
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
"PerPkg": "1",
@@ -934,7 +839,6 @@
},
{
"BriefDescription": "ISMQ Retries; No QPI Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
@@ -944,7 +848,6 @@
},
{
"BriefDescription": "ISMQ Retries; No RTIDs",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
"PerPkg": "1",
@@ -954,7 +857,6 @@
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
"PerPkg": "1",
@@ -964,7 +866,6 @@
},
{
"BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO",
"PerPkg": "1",
@@ -974,7 +875,6 @@
},
{
"BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO",
"PerPkg": "1",
@@ -984,7 +884,6 @@
},
{
"BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET",
"PerPkg": "1",
@@ -1030,7 +929,6 @@
},
{
"BriefDescription": "SBo Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
@@ -1040,7 +938,6 @@
},
{
"BriefDescription": "SBo Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
@@ -1068,7 +965,6 @@
},
{
"BriefDescription": "TOR Inserts; All",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.ALL",
"PerPkg": "1",
@@ -1078,7 +974,6 @@
},
{
"BriefDescription": "TOR Inserts; Evictions",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.EVICTION",
"PerPkg": "1",
@@ -1088,7 +983,6 @@
},
{
"BriefDescription": "TOR Inserts; Local Memory",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.LOCAL",
"PerPkg": "1",
@@ -1098,7 +992,6 @@
},
{
"BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
"PerPkg": "1",
@@ -1108,17 +1001,15 @@
},
{
"BriefDescription": "TOR Inserts; Misses to Local Memory",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.",
- "UMask": "0x2A",
+ "UMask": "0x2a",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
"PerPkg": "1",
@@ -1128,7 +1019,6 @@
},
{
"BriefDescription": "TOR Inserts; Miss Opcode Match",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
"PerPkg": "1",
@@ -1138,17 +1028,15 @@
},
{
"BriefDescription": "TOR Inserts; Misses to Remote Memory",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
- "UMask": "0x8A",
+ "UMask": "0x8a",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
"PerPkg": "1",
@@ -1158,7 +1046,6 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_ALL",
"PerPkg": "1",
@@ -1168,7 +1055,6 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched Evictions",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
"PerPkg": "1",
@@ -1178,17 +1064,15 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched Miss All",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
- "UMask": "0x4A",
+ "UMask": "0x4a",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
"PerPkg": "1",
@@ -1198,7 +1082,6 @@
},
{
"BriefDescription": "TOR Inserts; NID and Opcode Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
"PerPkg": "1",
@@ -1208,7 +1091,6 @@
},
{
"BriefDescription": "TOR Inserts; NID Matched Writebacks",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_WB",
"PerPkg": "1",
@@ -1218,7 +1100,6 @@
},
{
"BriefDescription": "TOR Inserts; Opcode Match",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.OPCODE",
"PerPkg": "1",
@@ -1228,7 +1109,6 @@
},
{
"BriefDescription": "TOR Inserts; Remote Memory",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.REMOTE",
"PerPkg": "1",
@@ -1238,7 +1118,6 @@
},
{
"BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
"PerPkg": "1",
@@ -1248,7 +1127,6 @@
},
{
"BriefDescription": "TOR Inserts; Writebacks",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.WB",
"PerPkg": "1",
@@ -1298,7 +1176,7 @@
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. 'Miss' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO.",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "CBO"
},
{
@@ -1307,7 +1185,7 @@
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
- "UMask": "0x2A",
+ "UMask": "0x2a",
"Unit": "CBO"
},
{
@@ -1334,7 +1212,7 @@
"EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
- "UMask": "0x8A",
+ "UMask": "0x8a",
"Unit": "CBO"
},
{
@@ -1370,7 +1248,7 @@
"EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
"PerPkg": "1",
"PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
- "UMask": "0x4A",
+ "UMask": "0x4a",
"Unit": "CBO"
},
{
@@ -1438,7 +1316,6 @@
},
{
"BriefDescription": "Onto AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.AD",
"PerPkg": "1",
@@ -1447,7 +1324,6 @@
},
{
"BriefDescription": "Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.AK",
"PerPkg": "1",
@@ -1456,7 +1332,6 @@
},
{
"BriefDescription": "Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.BL",
"PerPkg": "1",
@@ -1465,7 +1340,6 @@
},
{
"BriefDescription": "Egress Allocations; AD - Cachebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
"PerPkg": "1",
@@ -1475,7 +1349,6 @@
},
{
"BriefDescription": "Egress Allocations; AD - Corebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CORE",
"PerPkg": "1",
@@ -1485,7 +1358,6 @@
},
{
"BriefDescription": "Egress Allocations; AK - Cachebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
"PerPkg": "1",
@@ -1495,7 +1367,6 @@
},
{
"BriefDescription": "Egress Allocations; AK - Corebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AK_CORE",
"PerPkg": "1",
@@ -1505,7 +1376,6 @@
},
{
"BriefDescription": "Egress Allocations; BL - Cacheno",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
"PerPkg": "1",
@@ -1515,7 +1385,6 @@
},
{
"BriefDescription": "Egress Allocations; BL - Corebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.BL_CORE",
"PerPkg": "1",
@@ -1525,7 +1394,6 @@
},
{
"BriefDescription": "Egress Allocations; IV - Cachebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
"PerPkg": "1",
@@ -1535,7 +1403,6 @@
},
{
"BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.AD_CORE",
"PerPkg": "1",
@@ -1545,7 +1412,6 @@
},
{
"BriefDescription": "Injection Starvation; Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.AK_BOTH",
"PerPkg": "1",
@@ -1555,7 +1421,6 @@
},
{
"BriefDescription": "Injection Starvation; Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.BL_BOTH",
"PerPkg": "1",
@@ -1565,7 +1430,6 @@
},
{
"BriefDescription": "Injection Starvation; Onto IV Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.IV",
"PerPkg": "1",
@@ -1575,7 +1439,6 @@
},
{
"BriefDescription": "BT Cycles Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_H_BT_CYCLES_NE",
"PerPkg": "1",
@@ -1584,7 +1447,6 @@
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
"PerPkg": "1",
@@ -1594,7 +1456,6 @@
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
"PerPkg": "1",
@@ -1604,7 +1465,6 @@
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
"PerPkg": "1",
@@ -1614,7 +1474,6 @@
},
{
"BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
"EventCode": "0x51",
"EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
"PerPkg": "1",
@@ -1624,7 +1483,6 @@
},
{
"BriefDescription": "HA to iMC Bypass; Not Taken",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
"PerPkg": "1",
@@ -1634,7 +1492,6 @@
},
{
"BriefDescription": "HA to iMC Bypass; Taken",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_H_BYPASS_IMC.TAKEN",
"PerPkg": "1",
@@ -1644,7 +1501,6 @@
},
{
"BriefDescription": "uclks",
- "Counter": "0,1,2,3",
"EventName": "UNC_H_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
@@ -1652,7 +1508,6 @@
},
{
"BriefDescription": "Direct2Core Messages Sent",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_H_DIRECT2CORE_COUNT",
"PerPkg": "1",
@@ -1661,7 +1516,6 @@
},
{
"BriefDescription": "Cycles when Direct2Core was Disabled",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
"PerPkg": "1",
@@ -1670,7 +1524,6 @@
},
{
"BriefDescription": "Number of Reads that had Direct2Core Overridden",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
"PerPkg": "1",
@@ -1679,7 +1532,6 @@
},
{
"BriefDescription": "Directory Lat Opt Return",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_H_DIRECTORY_LAT_OPT",
"PerPkg": "1",
@@ -1688,7 +1540,6 @@
},
{
"BriefDescription": "Directory Lookups; Snoop Not Needed",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
"PerPkg": "1",
@@ -1698,7 +1549,6 @@
},
{
"BriefDescription": "Directory Lookups; Snoop Needed",
- "Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
"PerPkg": "1",
@@ -1708,7 +1558,6 @@
},
{
"BriefDescription": "Directory Updates; Any Directory Update",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
@@ -1718,7 +1567,6 @@
},
{
"BriefDescription": "Directory Updates; Directory Clear",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
"PerPkg": "1",
@@ -1728,7 +1576,6 @@
},
{
"BriefDescription": "Directory Updates; Directory Set",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_H_DIRECTORY_UPDATE.SET",
"PerPkg": "1",
@@ -1738,7 +1585,6 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
"PerPkg": "1",
@@ -1747,16 +1593,14 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.ALL",
"PerPkg": "1",
- "UMask": "0xFF",
+ "UMask": "0xff",
"Unit": "HA"
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.ALLOCS",
"PerPkg": "1",
@@ -1765,7 +1609,6 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.EVICTS",
"PerPkg": "1",
@@ -1774,16 +1617,14 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.HOM",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "HA"
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.INVALS",
"PerPkg": "1",
@@ -1792,7 +1633,6 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
"PerPkg": "1",
@@ -1801,7 +1641,6 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.RSP",
"PerPkg": "1",
@@ -1810,7 +1649,6 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
"PerPkg": "1",
@@ -1819,7 +1657,6 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
"PerPkg": "1",
@@ -1828,7 +1665,6 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.RSPFWDS",
"PerPkg": "1",
@@ -1837,7 +1673,6 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
"PerPkg": "1",
@@ -1846,7 +1681,6 @@
},
{
"BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_H_HITME_HIT.WBMTOI",
"PerPkg": "1",
@@ -1855,7 +1689,6 @@
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
"PerPkg": "1",
@@ -1864,25 +1697,22 @@
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
"PerPkg": "1",
- "UMask": "0xFF",
+ "UMask": "0xff",
"Unit": "HA"
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "HA"
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
"PerPkg": "1",
@@ -1891,7 +1721,6 @@
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
"PerPkg": "1",
@@ -1900,7 +1729,6 @@
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
"PerPkg": "1",
@@ -1909,7 +1737,6 @@
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
"PerPkg": "1",
@@ -1918,7 +1745,6 @@
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
"PerPkg": "1",
@@ -1927,7 +1753,6 @@
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
"PerPkg": "1",
@@ -1936,7 +1761,6 @@
},
{
"BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
"PerPkg": "1",
@@ -1945,7 +1769,6 @@
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
"PerPkg": "1",
@@ -1954,16 +1777,14 @@
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.ALL",
"PerPkg": "1",
- "UMask": "0xFF",
+ "UMask": "0xff",
"Unit": "HA"
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
"PerPkg": "1",
@@ -1972,16 +1793,14 @@
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.HOM",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "HA"
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.INVALS",
"PerPkg": "1",
@@ -1990,7 +1809,6 @@
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
"PerPkg": "1",
@@ -1999,7 +1817,6 @@
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.RSP",
"PerPkg": "1",
@@ -2008,7 +1825,6 @@
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
"PerPkg": "1",
@@ -2017,7 +1833,6 @@
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
"PerPkg": "1",
@@ -2026,7 +1841,6 @@
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
"PerPkg": "1",
@@ -2035,7 +1849,6 @@
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
"PerPkg": "1",
@@ -2044,7 +1857,6 @@
},
{
"BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
"PerPkg": "1",
@@ -2053,7 +1865,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
"PerPkg": "1",
@@ -2063,7 +1874,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
"PerPkg": "1",
@@ -2073,7 +1883,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
"PerPkg": "1",
@@ -2083,7 +1892,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
"PerPkg": "1",
@@ -2093,7 +1901,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
"PerPkg": "1",
@@ -2103,7 +1910,6 @@
},
{
"BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
"PerPkg": "1",
@@ -2113,7 +1919,6 @@
},
{
"BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_H_IMC_READS.NORMAL",
"PerPkg": "1",
@@ -2123,7 +1928,6 @@
},
{
"BriefDescription": "Retry Events",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_H_IMC_RETRY",
"PerPkg": "1",
@@ -2131,17 +1935,15 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_H_IMC_WRITES.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "HA"
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_H_IMC_WRITES.FULL",
"PerPkg": "1",
@@ -2151,7 +1953,6 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
"PerPkg": "1",
@@ -2161,7 +1962,6 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_H_IMC_WRITES.PARTIAL",
"PerPkg": "1",
@@ -2171,7 +1971,6 @@
},
{
"BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
"PerPkg": "1",
@@ -2181,7 +1980,6 @@
},
{
"BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
"EventCode": "0x61",
"EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
"PerPkg": "1",
@@ -2190,7 +1988,6 @@
},
{
"BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
"EventCode": "0x61",
"EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
"PerPkg": "1",
@@ -2199,7 +1996,6 @@
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x64",
"EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0",
"PerPkg": "1",
@@ -2209,7 +2005,6 @@
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x64",
"EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1",
"PerPkg": "1",
@@ -2219,7 +2014,6 @@
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
"EventCode": "0x65",
"EventName": "UNC_H_IOT_CTS_HI.CTS2",
"PerPkg": "1",
@@ -2229,7 +2023,6 @@
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
"EventCode": "0x65",
"EventName": "UNC_H_IOT_CTS_HI.CTS3",
"PerPkg": "1",
@@ -2239,7 +2032,6 @@
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x62",
"EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0",
"PerPkg": "1",
@@ -2249,7 +2041,6 @@
},
{
"BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
"EventCode": "0x62",
"EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1",
"PerPkg": "1",
@@ -2259,7 +2050,6 @@
},
{
"BriefDescription": "OSB Snoop Broadcast; Cancelled",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.CANCELLED",
"PerPkg": "1",
@@ -2269,7 +2059,6 @@
},
{
"BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.INVITOE_LOCAL",
"PerPkg": "1",
@@ -2279,7 +2068,6 @@
},
{
"BriefDescription": "OSB Snoop Broadcast; Local Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.READS_LOCAL",
"PerPkg": "1",
@@ -2289,7 +2077,6 @@
},
{
"BriefDescription": "OSB Snoop Broadcast; Reads Local - Useful",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
"PerPkg": "1",
@@ -2299,7 +2086,6 @@
},
{
"BriefDescription": "OSB Snoop Broadcast; Remote",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.REMOTE",
"PerPkg": "1",
@@ -2309,7 +2095,6 @@
},
{
"BriefDescription": "OSB Snoop Broadcast; Remote - Useful",
- "Counter": "0,1,2,3",
"EventCode": "0x53",
"EventName": "UNC_H_OSB.REMOTE_USEFUL",
"PerPkg": "1",
@@ -2319,7 +2104,6 @@
},
{
"BriefDescription": "OSB Early Data Return; All",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.ALL",
"PerPkg": "1",
@@ -2329,7 +2113,6 @@
},
{
"BriefDescription": "OSB Early Data Return; Reads to Local I",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
"PerPkg": "1",
@@ -2339,7 +2122,6 @@
},
{
"BriefDescription": "OSB Early Data Return; Reads to Local S",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
"PerPkg": "1",
@@ -2349,7 +2131,6 @@
},
{
"BriefDescription": "OSB Early Data Return; Reads to Remote I",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
"PerPkg": "1",
@@ -2359,7 +2140,6 @@
},
{
"BriefDescription": "OSB Early Data Return; Reads to Remote S",
- "Counter": "0,1,2,3",
"EventCode": "0x54",
"EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
"PerPkg": "1",
@@ -2369,7 +2149,6 @@
},
{
"BriefDescription": "Read and Write Requests; Local InvItoEs",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
@@ -2379,7 +2158,6 @@
},
{
"BriefDescription": "Read and Write Requests; Remote InvItoEs",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
"PerPkg": "1",
@@ -2389,7 +2167,6 @@
},
{
"BriefDescription": "Read and Write Requests; Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS",
"PerPkg": "1",
@@ -2399,7 +2176,6 @@
},
{
"BriefDescription": "Read and Write Requests; Local Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS_LOCAL",
"PerPkg": "1",
@@ -2409,7 +2185,6 @@
},
{
"BriefDescription": "Read and Write Requests; Remote Reads",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.READS_REMOTE",
"PerPkg": "1",
@@ -2419,17 +2194,15 @@
},
{
"BriefDescription": "Read and Write Requests; Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES",
"PerPkg": "1",
"PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "Read and Write Requests; Local Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
@@ -2439,7 +2212,6 @@
},
{
"BriefDescription": "Read and Write Requests; Remote Writes",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
@@ -2449,17 +2221,15 @@
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
@@ -2469,7 +2239,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
@@ -2479,7 +2248,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CW",
"PerPkg": "1",
@@ -2489,7 +2257,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
@@ -2499,7 +2266,6 @@
},
{
"BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_H_RING_AD_USED.CW_ODD",
"PerPkg": "1",
@@ -2509,27 +2275,24 @@
},
{
"BriefDescription": "HA AK Ring in Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "HA"
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
@@ -2539,7 +2302,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
@@ -2549,7 +2311,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CW",
"PerPkg": "1",
@@ -2559,7 +2320,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
@@ -2569,7 +2329,6 @@
},
{
"BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_H_RING_AK_USED.CW_ODD",
"PerPkg": "1",
@@ -2579,27 +2338,24 @@
},
{
"BriefDescription": "HA BL Ring in Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "HA"
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "HA"
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
@@ -2609,7 +2365,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
@@ -2619,7 +2374,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW",
"PerPkg": "1",
@@ -2629,7 +2383,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
@@ -2639,7 +2392,6 @@
},
{
"BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_H_RING_BL_USED.CW_ODD",
"PerPkg": "1",
@@ -2649,7 +2401,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
@@ -2659,7 +2410,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
@@ -2669,7 +2419,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
@@ -2679,7 +2428,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
@@ -2689,7 +2437,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
@@ -2699,7 +2446,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
@@ -2709,7 +2455,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
@@ -2719,7 +2464,6 @@
},
{
"BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
@@ -2729,7 +2473,6 @@
},
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
@@ -2739,7 +2482,6 @@
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
@@ -2749,7 +2491,6 @@
},
{
"BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
@@ -2759,7 +2500,6 @@
},
{
"BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
@@ -2769,7 +2509,6 @@
},
{
"BriefDescription": "SBo1 Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
@@ -2779,7 +2518,6 @@
},
{
"BriefDescription": "SBo1 Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
@@ -2789,7 +2527,6 @@
},
{
"BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
@@ -2799,7 +2536,6 @@
},
{
"BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
@@ -2809,7 +2545,6 @@
},
{
"BriefDescription": "Data beat the Snoop Responses; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
"PerPkg": "1",
@@ -2819,7 +2554,6 @@
},
{
"BriefDescription": "Data beat the Snoop Responses; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
"PerPkg": "1",
@@ -2829,7 +2563,6 @@
},
{
"BriefDescription": "Cycles with Snoops Outstanding; All Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
"PerPkg": "1",
@@ -2839,7 +2572,6 @@
},
{
"BriefDescription": "Cycles with Snoops Outstanding; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL",
"PerPkg": "1",
@@ -2849,7 +2581,6 @@
},
{
"BriefDescription": "Cycles with Snoops Outstanding; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE",
"PerPkg": "1",
@@ -2859,7 +2590,6 @@
},
{
"BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL",
"PerPkg": "1",
@@ -2869,7 +2599,6 @@
},
{
"BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE",
"PerPkg": "1",
@@ -2879,7 +2608,6 @@
},
{
"BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
"PerPkg": "1",
@@ -2889,7 +2617,6 @@
},
{
"BriefDescription": "Snoop Responses Received; RspI",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPI",
"PerPkg": "1",
@@ -2899,7 +2626,6 @@
},
{
"BriefDescription": "Snoop Responses Received; RspIFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
"PerPkg": "1",
@@ -2909,7 +2635,6 @@
},
{
"BriefDescription": "Snoop Responses Received; RspS",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPS",
"PerPkg": "1",
@@ -2919,7 +2644,6 @@
},
{
"BriefDescription": "Snoop Responses Received; RspSFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
"PerPkg": "1",
@@ -2929,7 +2653,6 @@
},
{
"BriefDescription": "Snoop Responses Received; Rsp*Fwd*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
"PerPkg": "1",
@@ -2939,7 +2662,6 @@
},
{
"BriefDescription": "Snoop Responses Received; Rsp*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_H_SNOOP_RESP.RSP_WB",
"PerPkg": "1",
@@ -2949,7 +2671,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; Other",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
"PerPkg": "1",
@@ -2959,7 +2680,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; RspCnflct",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
"PerPkg": "1",
@@ -2969,7 +2689,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; RspI",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
"PerPkg": "1",
@@ -2979,7 +2698,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; RspIFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
"PerPkg": "1",
@@ -2989,7 +2707,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; RspS",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
"PerPkg": "1",
@@ -2999,7 +2716,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; RspSFwd",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
"PerPkg": "1",
@@ -3009,7 +2725,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
"PerPkg": "1",
@@ -3019,7 +2734,6 @@
},
{
"BriefDescription": "Snoop Responses Received Local; Rsp*WB",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
"PerPkg": "1",
@@ -3029,7 +2743,6 @@
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
@@ -3039,7 +2752,6 @@
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
@@ -3049,7 +2761,6 @@
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
@@ -3059,7 +2770,6 @@
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
@@ -3069,7 +2779,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
"PerPkg": "1",
@@ -3079,7 +2788,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
"PerPkg": "1",
@@ -3089,7 +2797,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
"PerPkg": "1",
@@ -3099,7 +2806,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
"PerPkg": "1",
@@ -3109,7 +2815,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
"PerPkg": "1",
@@ -3119,7 +2824,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
"PerPkg": "1",
@@ -3129,7 +2833,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
"PerPkg": "1",
@@ -3139,7 +2842,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
"PerPkg": "1",
@@ -3149,7 +2851,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
"PerPkg": "1",
@@ -3159,7 +2860,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
"PerPkg": "1",
@@ -3169,7 +2869,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
"PerPkg": "1",
@@ -3179,7 +2878,6 @@
},
{
"BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
"PerPkg": "1",
@@ -3189,7 +2887,6 @@
},
{
"BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
"PerPkg": "1",
@@ -3199,7 +2896,6 @@
},
{
"BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
"PerPkg": "1",
@@ -3209,7 +2905,6 @@
},
{
"BriefDescription": "Tracker Cycles Not Empty; All Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
"PerPkg": "1",
@@ -3219,7 +2914,6 @@
},
{
"BriefDescription": "Tracker Cycles Not Empty; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
"PerPkg": "1",
@@ -3229,7 +2923,6 @@
},
{
"BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
"PerPkg": "1",
@@ -3239,7 +2932,6 @@
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
"PerPkg": "1",
@@ -3249,7 +2941,6 @@
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
"PerPkg": "1",
@@ -3259,7 +2950,6 @@
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
"PerPkg": "1",
@@ -3269,7 +2959,6 @@
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
"PerPkg": "1",
@@ -3279,7 +2968,6 @@
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
"PerPkg": "1",
@@ -3289,7 +2977,6 @@
},
{
"BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
"PerPkg": "1",
@@ -3299,7 +2986,6 @@
},
{
"BriefDescription": "Data Pending Occupancy Accumultor; Local Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
"PerPkg": "1",
@@ -3309,7 +2995,6 @@
},
{
"BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
"PerPkg": "1",
@@ -3319,7 +3004,6 @@
},
{
"BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_H_TxR_AD.HOM",
"PerPkg": "1",
@@ -3329,7 +3013,6 @@
},
{
"BriefDescription": "AD Egress Full; All",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
"PerPkg": "1",
@@ -3339,7 +3022,6 @@
},
{
"BriefDescription": "AD Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
"PerPkg": "1",
@@ -3349,7 +3031,6 @@
},
{
"BriefDescription": "AD Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
"PerPkg": "1",
@@ -3359,7 +3040,6 @@
},
{
"BriefDescription": "AD Egress Not Empty; All",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
"PerPkg": "1",
@@ -3369,7 +3049,6 @@
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
"PerPkg": "1",
@@ -3379,7 +3058,6 @@
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
"PerPkg": "1",
@@ -3389,7 +3067,6 @@
},
{
"BriefDescription": "AD Egress Allocations; All",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.ALL",
"PerPkg": "1",
@@ -3399,7 +3076,6 @@
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
"PerPkg": "1",
@@ -3409,7 +3085,6 @@
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
"PerPkg": "1",
@@ -3419,7 +3094,6 @@
},
{
"BriefDescription": "AK Egress Full; All",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
"PerPkg": "1",
@@ -3429,7 +3103,6 @@
},
{
"BriefDescription": "AK Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
"PerPkg": "1",
@@ -3439,7 +3112,6 @@
},
{
"BriefDescription": "AK Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
"PerPkg": "1",
@@ -3449,7 +3121,6 @@
},
{
"BriefDescription": "AK Egress Not Empty; All",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
"PerPkg": "1",
@@ -3459,7 +3130,6 @@
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
"PerPkg": "1",
@@ -3469,7 +3139,6 @@
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
"PerPkg": "1",
@@ -3479,7 +3148,6 @@
},
{
"BriefDescription": "AK Egress Allocations; All",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_TxR_AK_INSERTS.ALL",
"PerPkg": "1",
@@ -3489,7 +3157,6 @@
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
"PerPkg": "1",
@@ -3499,7 +3166,6 @@
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
"PerPkg": "1",
@@ -3509,7 +3175,6 @@
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CACHE",
"PerPkg": "1",
@@ -3519,7 +3184,6 @@
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_CORE",
"PerPkg": "1",
@@ -3529,7 +3193,6 @@
},
{
"BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_H_TxR_BL.DRS_QPI",
"PerPkg": "1",
@@ -3539,7 +3202,6 @@
},
{
"BriefDescription": "BL Egress Full; All",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
"PerPkg": "1",
@@ -3549,7 +3211,6 @@
},
{
"BriefDescription": "BL Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
"PerPkg": "1",
@@ -3559,7 +3220,6 @@
},
{
"BriefDescription": "BL Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
"PerPkg": "1",
@@ -3569,7 +3229,6 @@
},
{
"BriefDescription": "BL Egress Not Empty; All",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
"PerPkg": "1",
@@ -3579,7 +3238,6 @@
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
"PerPkg": "1",
@@ -3589,7 +3247,6 @@
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
"PerPkg": "1",
@@ -3599,7 +3256,6 @@
},
{
"BriefDescription": "BL Egress Allocations; All",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.ALL",
"PerPkg": "1",
@@ -3609,7 +3265,6 @@
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
"PerPkg": "1",
@@ -3619,7 +3274,6 @@
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
"PerPkg": "1",
@@ -3629,7 +3283,6 @@
},
{
"BriefDescription": "Injection Starvation; For AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_H_TxR_STARVED.AK",
"PerPkg": "1",
@@ -3639,7 +3292,6 @@
},
{
"BriefDescription": "Injection Starvation; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_H_TxR_STARVED.BL",
"PerPkg": "1",
@@ -3649,7 +3301,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
@@ -3659,7 +3310,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
@@ -3669,7 +3319,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
@@ -3679,7 +3328,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
@@ -3689,7 +3337,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
@@ -3699,7 +3346,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
@@ -3709,7 +3355,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
@@ -3719,7 +3364,6 @@
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json
index 83ff0542dbc0..c3f2f6c2ac74 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "DRAM Activate Count; Activate due to Write",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.BYP",
"PerPkg": "1",
@@ -11,7 +10,6 @@
},
{
"BriefDescription": "DRAM Activate Count; Activate due to Read",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.RD",
"PerPkg": "1",
@@ -21,7 +19,6 @@
},
{
"BriefDescription": "DRAM Activate Count; Activate due to Write",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.WR",
"PerPkg": "1",
@@ -31,7 +28,6 @@
},
{
"BriefDescription": "ACT command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.ACT",
"PerPkg": "1",
@@ -40,7 +36,6 @@
},
{
"BriefDescription": "CAS command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.CAS",
"PerPkg": "1",
@@ -49,7 +44,6 @@
},
{
"BriefDescription": "PRE command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.PRE",
"PerPkg": "1",
@@ -58,17 +52,15 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
@@ -78,7 +70,6 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
@@ -88,17 +79,14 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_RMM",
"PerPkg": "1",
- "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
@@ -108,27 +96,23 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD_WMM",
"PerPkg": "1",
- "PublicDescription": "DRAM RD_CAS and WR_CAS Commands",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
"PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR_RMM",
"PerPkg": "1",
@@ -138,7 +122,6 @@
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR_WMM",
"PerPkg": "1",
@@ -148,14 +131,12 @@
},
{
"BriefDescription": "DRAM Clockticks",
- "Counter": "0,1,2,3",
"EventName": "UNC_M_DCLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge All Commands",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
@@ -164,7 +145,6 @@
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
@@ -174,7 +154,6 @@
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
@@ -184,7 +163,6 @@
},
{
"BriefDescription": "ECC Correctable Errors",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
"PerPkg": "1",
@@ -193,7 +171,6 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.ISOCH",
"PerPkg": "1",
@@ -203,7 +180,6 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.PARTIAL",
"PerPkg": "1",
@@ -213,7 +189,6 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Read Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.READ",
"PerPkg": "1",
@@ -223,7 +198,6 @@
},
{
"BriefDescription": "Cycles in a Major Mode; Write Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_M_MAJOR_MODES.WRITE",
"PerPkg": "1",
@@ -233,7 +207,6 @@
},
{
"BriefDescription": "Channel DLLOFF Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
"PerPkg": "1",
@@ -242,7 +215,6 @@
},
{
"BriefDescription": "Channel PPD Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M_POWER_CHANNEL_PPD",
"PerPkg": "1",
@@ -251,7 +223,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
"PerPkg": "1",
@@ -261,7 +232,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
"PerPkg": "1",
@@ -271,7 +241,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
"PerPkg": "1",
@@ -281,7 +250,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
"PerPkg": "1",
@@ -291,7 +259,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
"PerPkg": "1",
@@ -301,7 +268,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
"PerPkg": "1",
@@ -311,7 +277,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
"PerPkg": "1",
@@ -321,7 +286,6 @@
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
"PerPkg": "1",
@@ -331,16 +295,20 @@
},
{
"BriefDescription": "Critical Throttle Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event.",
"Unit": "iMC"
},
+ {
+ "EventCode": "0x42",
+ "EventName": "UNC_M_POWER_PCU_THROTTLING",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Clock-Enabled Self-Refresh",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M_POWER_SELF_REFRESH",
"PerPkg": "1",
@@ -349,7 +317,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
"PerPkg": "1",
@@ -359,7 +326,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
"PerPkg": "1",
@@ -369,7 +335,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
"PerPkg": "1",
@@ -379,7 +344,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
"PerPkg": "1",
@@ -389,7 +353,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
"PerPkg": "1",
@@ -399,7 +362,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
"PerPkg": "1",
@@ -409,7 +371,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
"PerPkg": "1",
@@ -419,7 +380,6 @@
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
"PerPkg": "1",
@@ -429,7 +389,6 @@
},
{
"BriefDescription": "Read Preemption Count; Read over Read Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
"PerPkg": "1",
@@ -439,7 +398,6 @@
},
{
"BriefDescription": "Read Preemption Count; Read over Write Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
"PerPkg": "1",
@@ -449,7 +407,6 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.BYP",
"PerPkg": "1",
@@ -459,7 +416,6 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
"PerPkg": "1",
@@ -469,7 +425,6 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
"PerPkg": "1",
@@ -479,7 +434,6 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to read",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
@@ -489,7 +443,6 @@
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to write",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
@@ -499,7 +452,6 @@
},
{
"BriefDescription": "Read CAS issued with HIGH priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.HIGH",
"PerPkg": "1",
@@ -508,7 +460,6 @@
},
{
"BriefDescription": "Read CAS issued with LOW priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.LOW",
"PerPkg": "1",
@@ -517,7 +468,6 @@
},
{
"BriefDescription": "Read CAS issued with MEDIUM priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.MED",
"PerPkg": "1",
@@ -526,7 +476,6 @@
},
{
"BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.PANIC",
"PerPkg": "1",
@@ -535,7 +484,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
"PerPkg": "1",
@@ -544,7 +492,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK0",
"PerPkg": "1",
@@ -552,7 +499,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK1",
"PerPkg": "1",
@@ -561,61 +507,54 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK2",
"PerPkg": "1",
@@ -624,7 +563,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK3",
"PerPkg": "1",
@@ -633,7 +571,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK4",
"PerPkg": "1",
@@ -642,7 +579,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK5",
"PerPkg": "1",
@@ -651,7 +587,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK6",
"PerPkg": "1",
@@ -660,7 +595,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK7",
"PerPkg": "1",
@@ -669,7 +603,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK8",
"PerPkg": "1",
@@ -678,7 +611,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK9",
"PerPkg": "1",
@@ -687,7 +619,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
"PerPkg": "1",
@@ -696,7 +627,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
"PerPkg": "1",
@@ -705,7 +635,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
"PerPkg": "1",
@@ -714,7 +643,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
"PerPkg": "1",
@@ -723,7 +651,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
"PerPkg": "1",
@@ -732,7 +659,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB1",
"EventName": "UNC_M_RD_CAS_RANK1.BANK0",
"PerPkg": "1",
@@ -740,7 +666,6 @@
},
{
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- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANK9",
"PerPkg": "1",
@@ -1447,7 +1294,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
"PerPkg": "1",
@@ -1456,7 +1302,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
"PerPkg": "1",
@@ -1465,7 +1310,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
"PerPkg": "1",
@@ -1474,7 +1318,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
"PerPkg": "1",
@@ -1483,7 +1326,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
"PerPkg": "1",
@@ -1492,7 +1334,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK0",
"PerPkg": "1",
@@ -1500,7 +1341,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK1",
"PerPkg": "1",
@@ -1509,61 +1349,54 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK2",
"PerPkg": "1",
@@ -1572,7 +1405,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK3",
"PerPkg": "1",
@@ -1581,7 +1413,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK4",
"PerPkg": "1",
@@ -1590,7 +1421,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK5",
"PerPkg": "1",
@@ -1599,7 +1429,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK6",
"PerPkg": "1",
@@ -1608,7 +1437,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK7",
"PerPkg": "1",
@@ -1617,7 +1445,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK8",
"PerPkg": "1",
@@ -1626,7 +1453,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANK9",
"PerPkg": "1",
@@ -1635,7 +1461,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
"PerPkg": "1",
@@ -1644,7 +1469,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
"PerPkg": "1",
@@ -1653,7 +1477,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
"PerPkg": "1",
@@ -1662,7 +1485,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
"PerPkg": "1",
@@ -1671,7 +1493,6 @@
},
{
"BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M_RPQ_CYCLES_NE",
"PerPkg": "1",
@@ -1680,7 +1501,6 @@
},
{
"BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS",
"PerPkg": "1",
@@ -1689,7 +1509,6 @@
},
{
"BriefDescription": "VMSE MXB write buffer occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
"PerPkg": "1",
@@ -1697,7 +1516,6 @@
},
{
"BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M_VMSE_WR_PUSH.RMM",
"PerPkg": "1",
@@ -1706,7 +1524,6 @@
},
{
"BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
"EventName": "UNC_M_VMSE_WR_PUSH.WMM",
"PerPkg": "1",
@@ -1715,7 +1532,6 @@
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
"PerPkg": "1",
@@ -1724,7 +1540,6 @@
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.STARVE",
"PerPkg": "1",
@@ -1733,7 +1548,6 @@
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
"PerPkg": "1",
@@ -1742,7 +1556,6 @@
},
{
"BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_CYCLES_FULL",
"PerPkg": "1",
@@ -1751,7 +1564,6 @@
},
{
"BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M_WPQ_CYCLES_NE",
"PerPkg": "1",
@@ -1760,7 +1572,6 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT",
"PerPkg": "1",
@@ -1769,7 +1580,6 @@
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT",
"PerPkg": "1",
@@ -1778,7 +1588,6 @@
},
{
"BriefDescription": "Not getting the requested Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_M_WRONG_MM",
"PerPkg": "1",
@@ -1786,7 +1595,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
"PerPkg": "1",
@@ -1795,7 +1603,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK0",
"PerPkg": "1",
@@ -1803,7 +1610,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK1",
"PerPkg": "1",
@@ -1812,61 +1618,54 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK2",
"PerPkg": "1",
@@ -1875,7 +1674,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK3",
"PerPkg": "1",
@@ -1884,7 +1682,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK4",
"PerPkg": "1",
@@ -1893,7 +1690,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK5",
"PerPkg": "1",
@@ -1902,7 +1698,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK6",
"PerPkg": "1",
@@ -1911,7 +1706,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK7",
"PerPkg": "1",
@@ -1920,7 +1714,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK8",
"PerPkg": "1",
@@ -1929,7 +1722,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK9",
"PerPkg": "1",
@@ -1938,7 +1730,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
"PerPkg": "1",
@@ -1947,7 +1738,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
"PerPkg": "1",
@@ -1956,7 +1746,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
"PerPkg": "1",
@@ -1965,7 +1754,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANKG3",
"PerPkg": "1",
@@ -1974,7 +1762,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; All Banks",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS",
"PerPkg": "1",
@@ -1983,7 +1770,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK0",
"PerPkg": "1",
@@ -1991,7 +1777,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK1",
"PerPkg": "1",
@@ -2000,61 +1785,54 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 10",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK10",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 11",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK11",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 12",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK12",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 13",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK13",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 14",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK14",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 15",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK15",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK2",
"PerPkg": "1",
@@ -2063,7 +1841,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK3",
"PerPkg": "1",
@@ -2072,7 +1849,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK4",
"PerPkg": "1",
@@ -2081,7 +1857,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK5",
"PerPkg": "1",
@@ -2090,7 +1865,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK6",
"PerPkg": "1",
@@ -2099,7 +1873,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK7",
"PerPkg": "1",
@@ -2108,7 +1881,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK8",
"PerPkg": "1",
@@ -2117,7 +1889,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANK9",
"PerPkg": "1",
@@ -2126,7 +1897,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG0",
"PerPkg": "1",
@@ -2135,7 +1905,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB9",
"EventName": "UNC_M_WR_CAS_RANK1.BANKG1",
"PerPkg": "1",
@@ -2144,7 +1913,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
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"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK6",
"PerPkg": "1",
@@ -2851,7 +2541,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK7",
"PerPkg": "1",
@@ -2860,7 +2549,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK8",
"PerPkg": "1",
@@ -2869,7 +2557,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK9",
"PerPkg": "1",
@@ -2878,7 +2565,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
"PerPkg": "1",
@@ -2887,7 +2573,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
"PerPkg": "1",
@@ -2896,7 +2581,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
"PerPkg": "1",
@@ -2905,7 +2589,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json
index fc7e0867fcc5..753b381b77fe 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "Total Write Cache Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
@@ -11,7 +10,6 @@
},
{
"BriefDescription": "Total Write Cache Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
"PerPkg": "1",
@@ -21,7 +19,6 @@
},
{
"BriefDescription": "Clocks in the IRP",
- "Counter": "0,1",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Number of clocks in the IRP.",
@@ -29,7 +26,6 @@
},
{
"BriefDescription": "Coherent Ops; CLFlush",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
"PerPkg": "1",
@@ -39,7 +35,6 @@
},
{
"BriefDescription": "Coherent Ops; CRd",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.CRD",
"PerPkg": "1",
@@ -49,7 +44,6 @@
},
{
"BriefDescription": "Coherent Ops; DRd",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.DRD",
"PerPkg": "1",
@@ -59,7 +53,6 @@
},
{
"BriefDescription": "Coherent Ops; PCIDCAHin5t",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
"PerPkg": "1",
@@ -69,7 +62,6 @@
},
{
"BriefDescription": "Coherent Ops; PCIRdCur",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
"PerPkg": "1",
@@ -79,7 +71,6 @@
},
{
"BriefDescription": "Coherent Ops; PCIItoM",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCITOM",
"PerPkg": "1",
@@ -89,7 +80,6 @@
},
{
"BriefDescription": "Coherent Ops; RFO",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.RFO",
"PerPkg": "1",
@@ -99,7 +89,6 @@
},
{
"BriefDescription": "Coherent Ops; WbMtoI",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
@@ -109,7 +98,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
"PerPkg": "1",
@@ -118,7 +106,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_RD_INSERT",
"PerPkg": "1",
@@ -127,7 +114,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_WR_INSERT",
"PerPkg": "1",
@@ -136,7 +122,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_REJ",
"PerPkg": "1",
@@ -145,7 +130,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Requests",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_REQ",
"PerPkg": "1",
@@ -154,7 +138,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_XFER",
"PerPkg": "1",
@@ -163,7 +146,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.PF_ACK_HINT",
"PerPkg": "1",
@@ -172,7 +154,6 @@
},
{
"BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.PF_TIMEOUT",
"PerPkg": "1",
@@ -182,7 +163,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Data Throttled",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.DATA_THROTTLE",
"PerPkg": "1",
@@ -192,7 +172,6 @@
},
{
"BriefDescription": "Misc Events - Set 1",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
@@ -201,7 +180,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Received Invalid",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
"PerPkg": "1",
@@ -211,7 +189,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Received Valid",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
"PerPkg": "1",
@@ -221,7 +198,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_E",
"PerPkg": "1",
@@ -231,7 +207,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_I",
"PerPkg": "1",
@@ -241,7 +216,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_M",
"PerPkg": "1",
@@ -251,7 +225,6 @@
},
{
"BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_I_MISC1.SLOW_S",
"PerPkg": "1",
@@ -261,7 +234,6 @@
},
{
"BriefDescription": "AK Ingress Occupancy",
- "Counter": "0,1",
"EventCode": "0xA",
"EventName": "UNC_I_RxR_AK_INSERTS",
"PerPkg": "1",
@@ -269,7 +241,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
@@ -278,7 +249,6 @@
},
{
"BriefDescription": "BL Ingress Occupancy - DRS",
- "Counter": "0,1",
"EventCode": "0x1",
"EventName": "UNC_I_RxR_BL_DRS_INSERTS",
"PerPkg": "1",
@@ -286,7 +256,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x7",
"EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
"PerPkg": "1",
@@ -294,7 +263,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
@@ -303,7 +271,6 @@
},
{
"BriefDescription": "BL Ingress Occupancy - NCB",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_I_RxR_BL_NCB_INSERTS",
"PerPkg": "1",
@@ -311,7 +278,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x8",
"EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
"PerPkg": "1",
@@ -319,7 +285,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
@@ -328,7 +293,6 @@
},
{
"BriefDescription": "BL Ingress Occupancy - NCS",
- "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_I_RxR_BL_NCS_INSERTS",
"PerPkg": "1",
@@ -336,7 +300,6 @@
"Unit": "IRP"
},
{
- "Counter": "0,1",
"EventCode": "0x9",
"EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
"PerPkg": "1",
@@ -345,7 +308,6 @@
},
{
"BriefDescription": "Snoop Responses; Hit E or S",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_ES",
"PerPkg": "1",
@@ -354,7 +316,6 @@
},
{
"BriefDescription": "Snoop Responses; Hit I",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_I",
"PerPkg": "1",
@@ -363,7 +324,6 @@
},
{
"BriefDescription": "Snoop Responses; Hit M",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_M",
"PerPkg": "1",
@@ -372,7 +332,6 @@
},
{
"BriefDescription": "Snoop Responses; Miss",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.MISS",
"PerPkg": "1",
@@ -381,7 +340,6 @@
},
{
"BriefDescription": "Snoop Responses; SnpCode",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPCODE",
"PerPkg": "1",
@@ -390,7 +348,6 @@
},
{
"BriefDescription": "Snoop Responses; SnpData",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPDATA",
"PerPkg": "1",
@@ -399,7 +356,6 @@
},
{
"BriefDescription": "Snoop Responses; SnpInv",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPINV",
"PerPkg": "1",
@@ -408,7 +364,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Atomic",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.ATOMIC",
"PerPkg": "1",
@@ -418,7 +373,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Other",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.OTHER",
"PerPkg": "1",
@@ -428,7 +382,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Read Prefetches",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.RD_PREF",
"PerPkg": "1",
@@ -438,7 +391,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Reads",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.READS",
"PerPkg": "1",
@@ -448,7 +400,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Writes",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
@@ -458,7 +409,6 @@
},
{
"BriefDescription": "Inbound Transaction Count; Write Prefetches",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
@@ -468,7 +418,6 @@
},
{
"BriefDescription": "No AD Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x18",
"EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
"PerPkg": "1",
@@ -477,7 +426,6 @@
},
{
"BriefDescription": "No BL Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x19",
"EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
@@ -486,7 +434,6 @@
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xE",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
"PerPkg": "1",
@@ -495,7 +442,6 @@
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xF",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
"PerPkg": "1",
@@ -504,7 +450,6 @@
},
{
"BriefDescription": "Outbound Request Queue Occupancy",
- "Counter": "0,1",
"EventCode": "0xD",
"EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
"PerPkg": "1",
@@ -513,16 +458,42 @@
},
{
"BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_R2_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
"Unit": "R2PCIe"
},
+ {
+ "EventCode": "0x2D",
+ "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "R2PCIe"
+ },
+ {
+ "EventCode": "0x2D",
+ "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "R2PCIe"
+ },
+ {
+ "EventCode": "0x2D",
+ "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "R2PCIe"
+ },
+ {
+ "EventCode": "0x2D",
+ "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "R2PCIe"
+ },
{
"BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
"PerPkg": "1",
@@ -532,7 +503,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
"PerPkg": "1",
@@ -542,7 +512,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
"PerPkg": "1",
@@ -552,7 +521,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; DRS",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
"PerPkg": "1",
@@ -562,7 +530,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCB",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
"PerPkg": "1",
@@ -572,7 +539,6 @@
},
{
"BriefDescription": "R2PCIe IIO Credits in Use; NCS",
- "Counter": "0,1",
"EventCode": "0x32",
"EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
"PerPkg": "1",
@@ -582,27 +548,24 @@
},
{
"BriefDescription": "R2 AD Ring in Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
@@ -612,7 +575,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
@@ -622,7 +584,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW",
"PerPkg": "1",
@@ -632,7 +593,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
@@ -642,7 +602,6 @@
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW_ODD",
"PerPkg": "1",
@@ -652,7 +611,6 @@
},
{
"BriefDescription": "AK Ingress Bounced; Dn",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_R2_RING_AK_BOUNCES.DN",
"PerPkg": "1",
@@ -662,7 +620,6 @@
},
{
"BriefDescription": "AK Ingress Bounced; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_R2_RING_AK_BOUNCES.UP",
"PerPkg": "1",
@@ -672,27 +629,24 @@
},
{
"BriefDescription": "R2 AK Ring in Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
@@ -702,7 +656,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
@@ -712,7 +665,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW",
"PerPkg": "1",
@@ -722,7 +674,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
@@ -732,7 +683,6 @@
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW_ODD",
"PerPkg": "1",
@@ -742,27 +692,24 @@
},
{
"BriefDescription": "R2 BL Ring in Use; All",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.ALL",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
@@ -772,7 +719,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
@@ -782,7 +728,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW",
"PerPkg": "1",
@@ -792,7 +737,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
@@ -802,7 +746,6 @@
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW_ODD",
"PerPkg": "1",
@@ -812,27 +755,24 @@
},
{
"BriefDescription": "R2 IV Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.ANY",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
- "UMask": "0xF",
+ "UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.CCW",
"PerPkg": "1",
"PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
- "UMask": "0xC",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.CW",
"PerPkg": "1",
@@ -842,7 +782,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCB",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
"PerPkg": "1",
@@ -852,7 +791,6 @@
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCS",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
"PerPkg": "1",
@@ -862,7 +800,6 @@
},
{
"BriefDescription": "Ingress Allocations; NCB",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCB",
"PerPkg": "1",
@@ -872,7 +809,6 @@
},
{
"BriefDescription": "Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCS",
"PerPkg": "1",
@@ -891,7 +827,6 @@
},
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
@@ -901,7 +836,6 @@
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
@@ -929,7 +863,6 @@
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
@@ -939,7 +872,6 @@
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
@@ -949,7 +881,6 @@
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
@@ -959,7 +890,6 @@
},
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
@@ -1023,7 +953,6 @@
},
{
"BriefDescription": "Egress CCW NACK; AD CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_AD",
"PerPkg": "1",
@@ -1033,7 +962,6 @@
},
{
"BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
"PerPkg": "1",
@@ -1043,7 +971,6 @@
},
{
"BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
"PerPkg": "1",
@@ -1053,7 +980,6 @@
},
{
"BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
"PerPkg": "1",
@@ -1063,7 +989,6 @@
},
{
"BriefDescription": "Egress CCW NACK; BL CW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
"PerPkg": "1",
@@ -1073,7 +998,6 @@
},
{
"BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
"PerPkg": "1",
@@ -1083,7 +1007,6 @@
},
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
@@ -1093,7 +1016,6 @@
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.DISABLE",
"PerPkg": "1",
@@ -1103,7 +1025,6 @@
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.ENABLE",
"PerPkg": "1",
@@ -1113,7 +1034,6 @@
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
"PerPkg": "1",
@@ -1123,7 +1043,6 @@
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
"PerPkg": "1",
@@ -1133,7 +1052,6 @@
},
{
"BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
- "Counter": "0,1",
"EventCode": "0x45",
"EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"PerPkg": "1",
@@ -1143,7 +1061,6 @@
},
{
"BriefDescription": "RACU Request",
- "Counter": "0,1",
"EventCode": "0x46",
"EventName": "UNC_U_RACU_REQUESTS",
"PerPkg": "1",
@@ -1152,7 +1069,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.CMC",
"PerPkg": "1",
@@ -1162,7 +1078,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Livelock",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
"PerPkg": "1",
@@ -1172,7 +1087,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; LTError",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LTERROR",
"PerPkg": "1",
@@ -1182,7 +1096,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T0",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
"PerPkg": "1",
@@ -1192,7 +1105,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Monitor T1",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
"PerPkg": "1",
@@ -1202,7 +1114,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Other",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.OTHER",
"PerPkg": "1",
@@ -1212,7 +1123,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Trap",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.TRAP",
"PerPkg": "1",
@@ -1222,7 +1132,6 @@
},
{
"BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.UMC",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json
index c3325dd61202..124b3fe2e0e1 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json
@@ -1,7 +1,6 @@
[
{
"BriefDescription": "pclk Cycles",
- "Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"PublicDescription": "The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
@@ -9,7 +8,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -18,7 +16,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -27,7 +24,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -36,7 +32,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -45,7 +40,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -54,7 +48,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -63,7 +56,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -72,7 +64,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -81,7 +72,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -90,7 +80,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -99,7 +88,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -108,7 +96,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -117,7 +104,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -126,7 +112,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -135,7 +120,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -144,7 +128,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -153,7 +136,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -162,7 +144,6 @@
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -171,7 +152,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS_CORE0",
"PerPkg": "1",
@@ -180,7 +160,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_P_DEMOTIONS_CORE1",
"PerPkg": "1",
@@ -189,7 +168,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_P_DEMOTIONS_CORE10",
"PerPkg": "1",
@@ -198,7 +176,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3B",
"EventName": "UNC_P_DEMOTIONS_CORE11",
"PerPkg": "1",
@@ -207,7 +184,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_P_DEMOTIONS_CORE12",
"PerPkg": "1",
@@ -216,7 +192,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_P_DEMOTIONS_CORE13",
"PerPkg": "1",
@@ -225,7 +200,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_P_DEMOTIONS_CORE14",
"PerPkg": "1",
@@ -234,7 +208,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_P_DEMOTIONS_CORE15",
"PerPkg": "1",
@@ -243,7 +216,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_P_DEMOTIONS_CORE16",
"PerPkg": "1",
@@ -252,7 +224,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_P_DEMOTIONS_CORE17",
"PerPkg": "1",
@@ -261,7 +232,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_P_DEMOTIONS_CORE2",
"PerPkg": "1",
@@ -270,7 +240,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_P_DEMOTIONS_CORE3",
"PerPkg": "1",
@@ -279,7 +248,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_P_DEMOTIONS_CORE4",
"PerPkg": "1",
@@ -288,7 +256,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_P_DEMOTIONS_CORE5",
"PerPkg": "1",
@@ -297,7 +264,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_P_DEMOTIONS_CORE6",
"PerPkg": "1",
@@ -306,7 +272,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_P_DEMOTIONS_CORE7",
"PerPkg": "1",
@@ -315,7 +280,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_P_DEMOTIONS_CORE8",
"PerPkg": "1",
@@ -324,7 +288,6 @@
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_P_DEMOTIONS_CORE9",
"PerPkg": "1",
@@ -333,7 +296,6 @@
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
@@ -342,7 +304,6 @@
},
{
"BriefDescription": "OS Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
"PerPkg": "1",
@@ -351,7 +312,6 @@
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
@@ -360,7 +320,6 @@
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
@@ -369,7 +328,6 @@
},
{
"BriefDescription": "Cycles spent changing Frequency",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
@@ -378,7 +336,6 @@
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
@@ -387,7 +344,6 @@
},
{
"BriefDescription": "Package C State Residency - C0",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
@@ -396,7 +352,6 @@
},
{
"BriefDescription": "Package C State Residency - C1E",
- "Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
"PerPkg": "1",
@@ -405,7 +360,6 @@
},
{
"BriefDescription": "Package C State Residency - C2E",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
@@ -414,7 +368,6 @@
},
{
"BriefDescription": "Package C State Residency - C3",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
@@ -423,7 +376,6 @@
},
{
"BriefDescription": "Package C State Residency - C6",
- "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
@@ -432,7 +384,6 @@
},
{
"BriefDescription": "Package C7 State Residency",
- "Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
"PerPkg": "1",
@@ -441,7 +392,6 @@
},
{
"BriefDescription": "Number of cores in C-State; C0 and C1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
@@ -450,7 +400,6 @@
},
{
"BriefDescription": "Number of cores in C-State; C3",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
@@ -459,7 +408,6 @@
},
{
"BriefDescription": "Number of cores in C-State; C6 and C7",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
@@ -468,7 +416,6 @@
},
{
"BriefDescription": "External Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
@@ -477,7 +424,6 @@
},
{
"BriefDescription": "Internal Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
@@ -486,7 +432,6 @@
},
{
"BriefDescription": "Total Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -494,7 +439,6 @@
"Unit": "PCU"
},
{
- "Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
"PerPkg": "1",
@@ -503,7 +447,6 @@
},
{
"BriefDescription": "VR Hot",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json
index 6a6de8790f25..93621e004d88 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
@@ -12,8 +10,6 @@
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000003",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
"SampleAfterValue": "2000003",
@@ -30,8 +24,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
"SampleAfterValue": "2000003",
@@ -39,8 +31,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
@@ -49,8 +39,6 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
@@ -60,8 +48,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
@@ -71,8 +57,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
@@ -93,8 +75,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
@@ -104,8 +84,6 @@
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@@ -113,8 +91,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003",
@@ -122,8 +98,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003",
@@ -131,8 +105,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
@@ -141,8 +113,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
@@ -152,8 +122,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
@@ -163,8 +131,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
@@ -174,8 +140,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
@@ -185,8 +149,6 @@
},
{
"BriefDescription": "Cycle count for an Extended Page table walk.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
@@ -195,8 +157,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@@ -205,8 +165,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
@@ -216,8 +174,6 @@
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@@ -225,8 +181,6 @@
},
{
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003",
@@ -234,8 +188,6 @@
},
{
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003",
@@ -243,8 +195,6 @@
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
@@ -253,8 +203,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
@@ -264,8 +212,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
@@ -275,8 +221,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
@@ -286,8 +230,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
@@ -297,8 +239,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
@@ -307,8 +247,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
@@ -317,8 +255,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
@@ -327,8 +263,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in Memory.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
@@ -337,8 +271,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
@@ -347,8 +279,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
@@ -357,8 +287,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
@@ -367,8 +295,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
@@ -377,8 +303,6 @@
},
{
"BriefDescription": "STLB flush attempts",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index df47462a125f..8949b58f89be 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -3,7 +3,7 @@ GenuineIntel-6-(97|9A|B7|BA|BF),v1.16,alderlake,core
GenuineIntel-6-BE,v1.16,alderlaken,core
GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core
GenuineIntel-6-(3D|47),v26,broadwell,core
-GenuineIntel-6-56,v23,broadwellde,core
+GenuineIntel-6-56,v7,broadwellde,core
GenuineIntel-6-4F,v19,broadwellx,core
GenuineIntel-6-55-[56789ABCDEF],v1.16,cascadelakex,core
GenuineIntel-6-9[6C],v1.03,elkhartlake,core
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH v1 07/32] perf vendor events intel: Refresh broadwellx metrics and events
2022-12-15 6:49 [PATCH v1 06/32] perf vendor events intel: Refresh broadwellde metrics and events Ian Rogers
@ 2022-12-15 6:49 ` Ian Rogers
2022-12-15 6:49 ` [PATCH v1 08/32] perf vendor events intel: Refresh cascadelakex " Ian Rogers
1 sibling, 0 replies; 3+ messages in thread
From: Ian Rogers @ 2022-12-15 6:49 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the broadwellx metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated with
fixes to uncore events and improved descriptions. The formatting
changes increase consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/broadwellx/bdx-metrics.json | 1703 ++++----
.../pmu-events/arch/x86/broadwellx/cache.json | 191 -
.../arch/x86/broadwellx/floating-point.json | 40 -
.../arch/x86/broadwellx/frontend.json | 56 -
.../arch/x86/broadwellx/memory.json | 143 -
.../pmu-events/arch/x86/broadwellx/other.json | 8 -
.../arch/x86/broadwellx/pipeline.json | 272 --
.../arch/x86/broadwellx/uncore-cache.json | 3740 ++++++++---------
.../x86/broadwellx/uncore-interconnect.json | 1225 +++---
.../arch/x86/broadwellx/uncore-memory.json | 2052 +++++----
.../arch/x86/broadwellx/uncore-other.json | 2410 ++++++-----
.../arch/x86/broadwellx/uncore-power.json | 198 +-
.../arch/x86/broadwellx/virtual-memory.json | 76 -
13 files changed, 5577 insertions(+), 6537 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json
index e89fa536ca03..f5c8f707c692 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json
@@ -1,1206 +1,1189 @@
[
{
- "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
- "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
- "MetricGroup": "PGO;TopdownL1;tma_L1_group",
- "MetricName": "tma_frontend_bound",
- "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+ "MetricExpr": "INST_RETIRED.ANY / CLKS",
+ "MetricGroup": "Ret;Summary",
+ "MetricName": "IPC"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
- "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS",
- "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_latency",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uops Per Instruction",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
+ "MetricGroup": "Pipeline;Ret;Retire",
+ "MetricName": "UPI"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
- "MetricExpr": "ICACHE.IFDATA_STALL / CLKS",
- "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_icache_misses",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW",
+ "MetricName": "UpTB"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
- "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / CLKS",
- "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_itlb_misses",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+ "MetricExpr": "1 / IPC",
+ "MetricGroup": "Mem;Pipeline",
+ "MetricName": "CPI"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
- "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CLKS",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_branch_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "Pipeline",
+ "MetricName": "CLKS"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ",
- "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_mispredicts_resteers",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+ "MetricExpr": "4 * CORE_CLKS",
+ "MetricGroup": "tma_L1_group",
+ "MetricName": "SLOTS"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ",
- "MetricExpr": "MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)",
- "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_clears_resteers",
- "ScaleUnit": "100%"
+ "BriefDescription": "The ratio of Executed- by Issued-Uops",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
+ "MetricGroup": "Cor;Pipeline",
+ "MetricName": "Execute_per_Issue",
+ "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
- "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers",
- "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_unknown_branches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+ "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+ "MetricGroup": "Ret;SMT;tma_L1_group",
+ "MetricName": "CoreIPC"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
- "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
- "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_dsb_switches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Floating Point Operations Per Cycle",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
+ "MetricGroup": "Flops;Ret",
+ "MetricName": "FLOPc"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
- "MetricExpr": "ILD_STALL.LCP / CLKS",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_lcp",
- "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "FP_Arith_Utilization",
+ "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
},
{
- "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
- "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS",
- "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_ms_switches",
- "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
+ "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+ "MetricName": "ILP"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
- "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
- "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_bandwidth",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+ "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
+ "MetricGroup": "SMT",
+ "MetricName": "CORE_CLKS"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
- "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_mite",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
+ "MetricGroup": "InsType",
+ "MetricName": "IpLoad"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
- "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
- "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_dsb",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
+ "MetricGroup": "InsType",
+ "MetricName": "IpStore"
},
{
- "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_bad_speculation",
- "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Branches;Fed;InsType",
+ "MetricName": "IpBranch"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_branch_mispredicts",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "IpCall"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
- "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
- "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_machine_clears",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+ "MetricName": "IpTB"
},
{
- "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
- "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_backend_bound",
- "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch instructions per taken branch. ",
+ "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "BpTkBranch"
},
{
- "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB)) * tma_backend_bound",
- "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_memory_bound",
- "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "IpFLOP"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
- "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l1_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "IpArith",
+ "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
- "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_dtlb_load",
- "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "IpArith_Scalar_SP",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
- "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_store_fwd_blk",
- "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "IpArith_Scalar_DP",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS",
- "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_lock_latency",
- "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX128",
+ "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
- "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_split_loads",
- "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX256",
+ "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
- "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_4k_aliasing",
- "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+ "MetricExpr": "INST_RETIRED.ANY",
+ "MetricGroup": "Summary;tma_L1_group",
+ "MetricName": "Instructions"
},
{
- "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
- "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CLKS",
- "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_fb_full",
- "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
+ "MetricGroup": "Pipeline;Ret",
+ "MetricName": "Retire"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
- "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l2_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
+ "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
+ "MetricName": "Execute"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l3_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+ "MetricGroup": "DSB;Fed;FetchBW",
+ "MetricName": "DSB_Coverage"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_contested_accesses",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "IpMispredict"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
- "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_data_sharing",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
+ "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BrMispredicts",
+ "MetricName": "Branch_Misprediction_Cost"
},
{
- "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
- "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_l3_hit_latency",
- "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)",
+ "MetricGroup": "Mem;MemoryBound;MemoryLat",
+ "MetricName": "Load_Miss_Real_Latency"
},
{
- "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_sq_full",
- "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+ "MetricGroup": "Mem;MemoryBW;MemoryBound",
+ "MetricName": "MLP"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "(1 - (MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS))) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_dram_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L1MPKI"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_bandwidth",
- "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "Backend;CacheMisses;Mem",
+ "MetricName": "L2MPKI"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_latency",
- "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem;Offcore",
+ "MetricName": "L2MPKI_All"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
- "MetricExpr": "200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
- "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_local_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2MPKI_Load"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
- "MetricExpr": "310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CLKS",
- "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
+ "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2HPKI_All"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
- "MetricExpr": "(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + mem_load_uops_retired.hit_lfb / ((MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS) + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CLKS",
- "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_cache",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2HPKI_Load"
},
{
- "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
- "MetricExpr": "RESOURCE_STALLS.SB / CLKS",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_store_bound",
- "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L3MPKI"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 9 * (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES))) + (1 - (MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_store_latency",
- "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
- "ScaleUnit": "100%"
+ "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+ "MetricConstraint": "NO_NMI_WATCHDOG",
+ "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * CORE_CLKS)",
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "Page_Walks_Utilization"
},
{
- "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
- "MetricExpr": "(200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_false_sharing",
- "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents rate of split store accesses",
- "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
- "MetricGroup": "TopdownL4;tma_store_bound_group",
- "MetricName": "tma_split_stores",
- "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
- "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_dtlb_store",
- "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
- "MetricExpr": "tma_backend_bound - tma_memory_bound",
- "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_core_bound",
- "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "L1D_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
- "MetricExpr": "ARITH.FPU_DIV_ACTIVE / CORE_CLKS",
- "MetricGroup": "TopdownL3;tma_core_bound_group",
- "MetricName": "tma_divider",
- "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "L2_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if (IPC > 1.8) else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS",
- "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
- "MetricName": "tma_ports_utilization",
- "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "L3_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@) / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if (tma_fetch_latency > 0.1) else 0) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_0",
- "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "0",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "L3_Cache_Access_BW_1T"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_1",
- "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average CPU Utilization",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricGroup": "HPC;Summary",
+ "MetricName": "CPU_Utilization"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_2",
- "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+ "MetricGroup": "Power;Summary",
+ "MetricName": "Average_Frequency"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
- "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_3m",
- "ScaleUnit": "100%"
+ "BriefDescription": "Giga Floating Point Operations Per Second",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "GFLOPs",
+ "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_alu_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+ "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+ "MetricGroup": "Power",
+ "MetricName": "Turbo_Utilization"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
- "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_0",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
+ "MetricGroup": "SMT",
+ "MetricName": "SMT_2T_Utilization"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_1",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_Utilization"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_5",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_CPI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_6",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+ "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+ "MetricName": "DRAM_BW_Use"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_load_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
+ "MetricGroup": "Mem;MemoryLat;SoC",
+ "MetricName": "MEM_Read_Latency"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
- "MetricName": "tma_port_2",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@",
+ "MetricGroup": "Mem;MemoryBW;SoC",
+ "MetricName": "MEM_Parallel_Reads"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
- "MetricName": "tma_port_3",
- "ScaleUnit": "100%"
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "cbox_0@event\\=0x0@",
+ "MetricGroup": "SoC",
+ "MetricName": "Socket_CLKS"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_store_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+ "MetricGroup": "Branches;OS",
+ "MetricName": "IpFarBranch"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
- "MetricName": "tma_port_4",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Sample with: UOPS_DISPATCHED_PORT.PORT_7",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
- "MetricName": "tma_port_7",
- "ScaleUnit": "100%"
+ "BriefDescription": "CPU operating frequency (in GHz)",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+ "MetricName": "cpu_operating_frequency",
+ "ScaleUnit": "1GHz"
+ },
+ {
+ "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+ "MetricName": "cpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_retiring",
- "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS",
- "ScaleUnit": "100%"
+ "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+ "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+ "MetricName": "loads_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
- "MetricExpr": "tma_retiring - tma_heavy_operations",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_light_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
- "ScaleUnit": "100%"
+ "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+ "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+ "MetricName": "stores_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
- "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector",
- "MetricGroup": "HPC;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_fp_arith",
- "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+ "MetricName": "l1d_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
- "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_x87_use",
- "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY",
+ "MetricName": "l1d_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_fp_scalar",
- "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+ "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_fp_vector",
- "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_128b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+ "MetricName": "l2_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_256b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
- "MetricExpr": "tma_microcode_sequencer",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_heavy_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_code_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
- "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
- "MetricName": "tma_microcode_sequencer",
- "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@) / INST_RETIRED.ANY",
+ "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
- "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_assists",
- "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@) / INST_RETIRED.ANY",
+ "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
- "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_cisc",
- "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
+ "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
- "MetricExpr": "INST_RETIRED.ANY / CLKS",
- "MetricGroup": "Ret;Summary",
- "MetricName": "IPC"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
+ "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Uops Per Instruction",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
- "MetricGroup": "Pipeline;Ret;Retire",
- "MetricName": "UPI"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
+ "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW",
- "MetricName": "UpTB"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "itlb_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
- "MetricExpr": "1 / IPC",
- "MetricGroup": "Mem;Pipeline",
- "MetricName": "CPI"
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "itlb_large_page_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "Pipeline",
- "MetricName": "CLKS"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
- "MetricExpr": "4 * CORE_CLKS",
- "MetricGroup": "tma_L1_group",
- "MetricName": "SLOTS"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_store_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "The ratio of Executed- by Issued-Uops",
- "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
- "MetricGroup": "Cor;Pipeline",
- "MetricName": "Execute_per_Issue",
- "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
+ "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)",
+ "MetricName": "numa_reads_addressed_to_local_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
- "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
- "MetricGroup": "Ret;SMT;tma_L1_group",
- "MetricName": "CoreIPC"
+ "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)",
+ "MetricName": "numa_reads_addressed_to_remote_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS",
- "MetricGroup": "Flops;Ret",
- "MetricName": "FLOPc"
+ "BriefDescription": "Uncore operating frequency in GHz",
+ "MetricExpr": "UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time",
+ "MetricName": "uncore_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
- "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
- "MetricGroup": "Cor;Flops;HPC",
- "MetricName": "FP_Arith_Utilization",
- "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
+ "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)",
+ "MetricExpr": "UNC_Q_TxL_FLITS_G0.DATA * 8 / 1e6 / duration_time",
+ "MetricName": "qpi_data_transmit_bw",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
- "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
- "MetricName": "ILP"
+ "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
- "MetricGroup": "SMT",
- "MetricName": "CORE_CLKS"
+ "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
- "MetricGroup": "InsType",
- "MetricName": "IpLoad"
+ "BriefDescription": "DDR memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
- "MetricGroup": "InsType",
- "MetricName": "IpStore"
+ "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+ "MetricExpr": "cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_writes",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Branches;Fed;InsType",
- "MetricName": "IpBranch"
+ "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+ "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ + cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x180\\,filter_tid\\=0x3e@) * 64 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_reads",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "IpCall"
+ "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_decoded_icache",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
- "MetricName": "IpTB"
+ "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MITE_UOPS / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Branch instructions per taken branch. ",
- "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "BpTkBranch"
+ "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MS_UOPS / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
- "MetricGroup": "Flops;InsType",
- "MetricName": "IpFLOP"
+ "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "LSD.UOPS / UOPS_ISSUED.ANY",
+ "MetricName": "percent_uops_delivered_from_loop_stream_detector",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))",
- "MetricGroup": "Flops;InsType",
- "MetricName": "IpArith",
- "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
+ "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+ "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
+ "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_frontend_bound",
+ "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
- "MetricGroup": "Flops;FpScalar;InsType",
- "MetricName": "IpArith_Scalar_SP",
- "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+ "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS",
+ "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_latency",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
- "MetricGroup": "Flops;FpScalar;InsType",
- "MetricName": "IpArith_Scalar_DP",
- "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+ "MetricExpr": "ICACHE.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_icache_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX128",
- "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+ "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_itlb_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX256",
- "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+ "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_branch_resteers",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
- "MetricExpr": "INST_RETIRED.ANY",
- "MetricGroup": "Summary;tma_L1_group",
- "MetricName": "Instructions"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_mispredicts_resteers",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
- "MetricGroup": "Pipeline;Ret",
- "MetricName": "Retire"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ",
+ "MetricExpr": "MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_clears_resteers",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "",
- "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
- "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
- "MetricName": "Execute"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
+ "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers",
+ "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_unknown_branches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / ((IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS))",
- "MetricGroup": "DSB;Fed;FetchBW",
- "MetricName": "DSB_Coverage"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_dsb_switches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BadSpec;BrMispredicts",
- "MetricName": "IpMispredict"
+ "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+ "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_lcp",
+ "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
- "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BrMispredicts",
- "MetricName": "Branch_Misprediction_Cost"
+ "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+ "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_ms_switches",
+ "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb)",
- "MetricGroup": "Mem;MemoryBound;MemoryLat",
- "MetricName": "Load_Miss_Real_Latency"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+ "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
+ "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_bandwidth",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
- "MetricGroup": "Mem;MemoryBW;MemoryBound",
- "MetricName": "MLP"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+ "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_mite",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L1MPKI"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+ "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
+ "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_dsb",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "Backend;CacheMisses;Mem",
- "MetricName": "L2MPKI"
+ "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+ "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_bad_speculation",
+ "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem;Offcore",
- "MetricName": "L2MPKI_All"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_branch_mispredicts",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2MPKI_Load"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+ "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_machine_clears",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2HPKI_All"
+ "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+ "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + UOPS_RETIRED.RETIRE_SLOTS / SLOTS)",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_backend_bound",
+ "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2HPKI_Load"
+ "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound",
+ "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_memory_bound",
+ "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L3MPKI"
+ "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+ "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l1_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
- "MetricConstraint": "NO_NMI_WATCHDOG",
- "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * CORE_CLKS)",
- "MetricGroup": "Mem;MemoryTLB",
- "MetricName": "Page_Walks_Utilization"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+ "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_dtlb_load",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW"
+ "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+ "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_store_fwd_blk",
+ "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW"
+ "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+ "MetricExpr": "min(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_lock_latency",
+ "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW"
+ "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+ "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_split_loads",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "L1D_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
+ "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_4k_aliasing",
+ "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "L2_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+ "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_fb_full",
+ "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "L3_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l2_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "0",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "L3_Cache_Access_BW_1T"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+ "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l3_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
- "MetricGroup": "HPC;Summary",
- "MetricName": "CPU_Utilization"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+ "MetricExpr": "min((60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_contested_accesses",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
- "MetricGroup": "Power;Summary",
- "MetricName": "Average_Frequency"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+ "MetricExpr": "min(43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_data_sharing",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1000000000) / duration_time",
- "MetricGroup": "Cor;Flops;HPC",
- "MetricName": "GFLOPs",
- "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
+ "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+ "MetricExpr": "min(41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_l3_hit_latency",
+ "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average Frequency Utilization relative nominal frequency",
- "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
- "MetricGroup": "Power",
- "MetricName": "Turbo_Utilization"
+ "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+ "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_sq_full",
+ "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
- "MetricGroup": "SMT",
- "MetricName": "SMT_2T_Utilization"
+ "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+ "MetricExpr": "min((1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_dram_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "OS",
- "MetricName": "Kernel_Utilization"
+ "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_bandwidth",
+ "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
- "MetricGroup": "OS",
- "MetricName": "Kernel_CPI"
+ "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_latency",
+ "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
- "MetricGroup": "HPC;Mem;MemoryBW;SoC",
- "MetricName": "DRAM_BW_Use"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+ "MetricExpr": "min(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_local_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "1000000000 * (cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x35\\,umask\\=0x3\\,filter_opc\\=0x182@) / (Socket_CLKS / duration_time)",
- "MetricGroup": "Mem;MemoryLat;SoC",
- "MetricName": "MEM_Read_Latency"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+ "MetricExpr": "min(310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182\\,thresh\\=1@",
- "MetricGroup": "Mem;MemoryBW;SoC",
- "MetricName": "MEM_Parallel_Reads"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+ "MetricExpr": "min((200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_cache",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Socket actual clocks when any core is active on that socket",
- "MetricExpr": "cbox_0@event\\=0x0@",
- "MetricGroup": "SoC",
- "MetricName": "Socket_CLKS"
+ "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+ "MetricExpr": "RESOURCE_STALLS.SB / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_store_bound",
+ "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
- "MetricGroup": "Branches;OS",
- "MetricName": "IpFarBranch"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_store_latency",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+ "MetricExpr": "min((200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_false_sharing",
+ "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "BriefDescription": "This metric represents rate of split store accesses",
+ "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_split_stores",
+ "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+ "MetricExpr": "min((8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_dtlb_store",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+ "MetricExpr": "tma_backend_bound - tma_memory_bound",
+ "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_core_bound",
+ "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+ "MetricExpr": "ARITH.FPU_DIV_ACTIVE / CORE_CLKS",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_divider",
+ "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_ports_utilization",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\=0x1\\,cmask\\=0x1@ / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_0",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore frequency per die [GHZ]",
- "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
- "MetricGroup": "SoC",
- "MetricName": "UNCORE_FREQ"
+ "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_1",
+ "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "CPU operating frequency (in GHz)",
- "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "cpu_operating_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_2",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
- "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "loads_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+ "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_3m",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
- "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "stores_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_alu_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
+ "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_0",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_1",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_5",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_6",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_load_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+ "MetricName": "tma_port_2",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_code_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+ "MetricName": "tma_port_3",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@ ) / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_store_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@ ) / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
+ "MetricExpr": "tma_store_op_utilization",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+ "MetricName": "tma_port_4",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
- "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+ "MetricName": "tma_port_7",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_retiring",
+ "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ ) / ( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+ "MetricExpr": "tma_retiring - UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_light_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
+ "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS + tma_fp_scalar + tma_fp_vector",
+ "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_fp_arith",
+ "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_large_page_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+ "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS",
+ "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_x87_use",
+ "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_load_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_fp_scalar",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_store_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_fp_vector",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_local_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_128b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / ( cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_remote_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_256b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore operating frequency in GHz",
- "MetricExpr": "( UNC_C_CLOCKTICKS / ( #num_cores / #num_packages * #num_packages ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "uncore_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_heavy_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)",
- "MetricExpr": "( UNC_Q_TxL_FLITS_G0.DATA * 8 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "qpi_data_transmit_bw",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+ "MetricExpr": "tma_heavy_operations",
+ "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+ "MetricName": "tma_microcode_sequencer",
+ "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory read bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+ "MetricExpr": "min(100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_assists",
+ "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory write bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+ "MetricExpr": "max(0, tma_heavy_operations - tma_assists)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_cisc",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory bandwidth (MB/sec)",
- "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_total",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C3 residency percent per core",
+ "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C3_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
- "MetricExpr": "( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_writes",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C6 residency percent per core",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
- "MetricExpr": "(( cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ + cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x180\\,filter_tid\\=0x3e@ ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_reads",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C7 residency percent per core",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.DSB_UOPS / UOPS_ISSUED.ANY )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_decoded_icache",
- "ScaleUnit": "1%"
+ "BriefDescription": "C2 residency percent per package",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MITE_UOPS / UOPS_ISSUED.ANY )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
- "ScaleUnit": "1%"
+ "BriefDescription": "C3 residency percent per package",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MS_UOPS / UOPS_ISSUED.ANY )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_microcode_sequencer",
- "ScaleUnit": "1%"
+ "BriefDescription": "C6 residency percent per package",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( LSD.UOPS / UOPS_ISSUED.ANY )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_loop_stream_detector",
- "ScaleUnit": "1%"
+ "BriefDescription": "C7 residency percent per package",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json
index 2efc4c0ee740..6a134928b3f0 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "L1D data line replacements",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "L1D miss oustandings duration in cycles",
- "Counter": "2",
- "CounterHTOff": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -53,8 +43,6 @@
},
{
"BriefDescription": "Not rejected writebacks that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_DEMAND_RQSTS.WB_HIT",
"PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
@@ -63,8 +51,6 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@@ -73,8 +59,6 @@
},
{
"BriefDescription": "L2 cache lines in E state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",
@@ -83,8 +67,6 @@
},
{
"BriefDescription": "L2 cache lines in I state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",
@@ -93,8 +75,6 @@
},
{
"BriefDescription": "L2 cache lines in S state filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.",
@@ -103,8 +83,6 @@
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100003",
@@ -112,8 +90,6 @@
},
{
"BriefDescription": "L2 code requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "This event counts the total number of L2 code requests.",
@@ -122,8 +98,6 @@
},
{
"BriefDescription": "Demand Data Read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@@ -132,8 +106,6 @@
},
{
"BriefDescription": "Demand requests that miss L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"SampleAfterValue": "200003",
@@ -141,8 +113,6 @@
},
{
"BriefDescription": "Demand requests to L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"SampleAfterValue": "200003",
@@ -150,8 +120,6 @@
},
{
"BriefDescription": "Requests from L2 hardware prefetchers",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.",
@@ -160,8 +128,6 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@@ -170,8 +136,6 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"SampleAfterValue": "200003",
@@ -179,8 +143,6 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"SampleAfterValue": "200003",
@@ -188,8 +150,6 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.",
@@ -198,8 +158,6 @@
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@@ -208,8 +166,6 @@
},
{
"BriefDescription": "L2 prefetch requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_HIT",
"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.",
@@ -218,8 +174,6 @@
},
{
"BriefDescription": "L2 prefetch requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_MISS",
"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.",
@@ -228,8 +182,6 @@
},
{
"BriefDescription": "All requests that miss L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200003",
@@ -237,8 +189,6 @@
},
{
"BriefDescription": "All L2 requests.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200003",
@@ -246,8 +196,6 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200003",
@@ -255,8 +203,6 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200003",
@@ -264,8 +210,6 @@
},
{
"BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_PF",
"PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.",
@@ -274,8 +218,6 @@
},
{
"BriefDescription": "Transactions accessing L2 pipe",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.",
@@ -284,8 +226,6 @@
},
{
"BriefDescription": "L2 cache accesses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.CODE_RD",
"PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.",
@@ -294,8 +234,6 @@
},
{
"BriefDescription": "Demand Data Read requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.",
@@ -304,8 +242,6 @@
},
{
"BriefDescription": "L1D writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L1D_WB",
"PublicDescription": "This event counts L1D writebacks that access L2 cache.",
@@ -314,8 +250,6 @@
},
{
"BriefDescription": "L2 fill requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_FILL",
"PublicDescription": "This event counts L2 fill requests that access L2 cache.",
@@ -324,8 +258,6 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "This event counts L2 writebacks that access L2 cache.",
@@ -334,8 +266,6 @@
},
{
"BriefDescription": "RFO requests that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.RFO",
"PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
@@ -344,8 +274,6 @@
},
{
"BriefDescription": "Cycles when L1D is locked",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
@@ -354,8 +282,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@@ -364,8 +290,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
@@ -374,8 +298,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@@ -387,8 +309,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@@ -400,8 +320,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@@ -413,8 +331,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
@@ -426,8 +342,6 @@
},
{
"BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70, BDM100",
"EventCode": "0xD3",
@@ -439,8 +353,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
@@ -451,8 +363,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
@@ -463,8 +373,6 @@
},
{
"BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
@@ -475,8 +383,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
@@ -487,8 +393,6 @@
},
{
"BriefDescription": "Retired load uops with L1 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
@@ -499,8 +403,6 @@
},
{
"BriefDescription": "Retired load uops misses in L1 cache as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
@@ -511,8 +413,6 @@
},
{
"BriefDescription": "Retired load uops with L2 cache hits as data sources.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM35",
"EventCode": "0xD1",
@@ -524,8 +424,6 @@
},
{
"BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
@@ -536,8 +434,6 @@
},
{
"BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD1",
@@ -549,8 +445,6 @@
},
{
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100, BDE70",
"EventCode": "0xD1",
@@ -561,8 +455,6 @@
},
{
"BriefDescription": "All retired load uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
@@ -573,12 +465,9 @@
},
{
"BriefDescription": "All retired store uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
"SampleAfterValue": "2000003",
@@ -586,8 +475,6 @@
},
{
"BriefDescription": "Retired load uops with locked access.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM35",
"EventCode": "0xD0",
@@ -599,8 +486,6 @@
},
{
"BriefDescription": "Retired load uops that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
@@ -611,12 +496,9 @@
},
{
"BriefDescription": "Retired store uops that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
"SampleAfterValue": "100003",
@@ -624,8 +506,6 @@
},
{
"BriefDescription": "Retired load uops that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
@@ -636,12 +516,9 @@
},
{
"BriefDescription": "Retired store uops that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
"SampleAfterValue": "100003",
@@ -649,8 +526,6 @@
},
{
"BriefDescription": "Demand and prefetch data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@@ -659,8 +534,6 @@
},
{
"BriefDescription": "Any memory transaction that reached the SQ.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb0",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
"PublicDescription": "This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on.",
@@ -669,8 +542,6 @@
},
{
"BriefDescription": "Cacheable and noncachaeble code read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",
@@ -679,8 +550,6 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@@ -689,8 +558,6 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@@ -699,8 +566,6 @@
},
{
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",
@@ -709,8 +574,6 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
@@ -720,8 +583,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
@@ -732,8 +593,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
@@ -744,8 +603,6 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"Errata": "BDM76",
"EventCode": "0x60",
@@ -756,8 +613,6 @@
},
{
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
@@ -767,8 +622,6 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
@@ -778,8 +631,6 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"Errata": "BDM76",
"EventCode": "0x60",
@@ -789,8 +640,6 @@
},
{
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM76",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
@@ -800,8 +649,6 @@
},
{
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100003",
@@ -809,152 +656,114 @@
},
{
"BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all requests hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C8FFF",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Split locks in SQ",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"PublicDescription": "This event counts the number of split locks in the super queue.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json
index 93bbc8600321..e4826dc7f797 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
"SampleAfterValue": "2000006",
@@ -50,8 +40,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.PACKED",
"SampleAfterValue": "2000004",
@@ -59,8 +47,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -69,8 +55,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -79,8 +63,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -89,8 +71,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.SINGLE",
"SampleAfterValue": "2000005",
@@ -98,8 +78,6 @@
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
@@ -109,8 +87,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to input values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
@@ -119,8 +95,6 @@
},
{
"BriefDescription": "Number of SIMD FP assists due to Output values",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
@@ -129,8 +103,6 @@
},
{
"BriefDescription": "Number of X87 assists due to input value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
@@ -139,8 +111,6 @@
},
{
"BriefDescription": "Number of X87 assists due to output value.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
@@ -149,8 +119,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -158,8 +126,6 @@
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -167,8 +133,6 @@
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
@@ -178,8 +142,6 @@
},
{
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
@@ -189,8 +151,6 @@
},
{
"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json
index 37ce8034b2ed..d0f6678609ae 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xe6",
"EventName": "BACLEARS.ANY",
"SampleAfterValue": "100003",
@@ -10,8 +8,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@@ -20,8 +16,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.HIT",
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
@@ -30,8 +24,6 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.IFDATA_STALL",
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
@@ -40,8 +32,6 @@
},
{
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE.MISSES",
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
@@ -50,8 +40,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -72,8 +58,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -83,8 +67,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -94,8 +76,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@@ -105,8 +85,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
@@ -115,8 +93,6 @@
},
{
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x79",
"EventName": "IDQ.EMPTY",
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
@@ -125,8 +101,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_ALL_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -135,8 +109,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@@ -146,8 +118,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -156,8 +126,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@@ -167,8 +135,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@@ -178,8 +144,6 @@
},
{
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -190,8 +154,6 @@
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
@@ -200,8 +162,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
@@ -210,8 +170,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -221,8 +179,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
@@ -231,8 +187,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
@@ -241,8 +195,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -252,8 +204,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -263,8 +213,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -274,8 +222,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -284,8 +230,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json
index 545f61f691b9..a7449e5b68dc 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Number of times HLE abort was triggered",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
@@ -12,8 +10,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
@@ -42,8 +34,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times HLE caused a fault.",
@@ -52,8 +42,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
@@ -62,8 +50,6 @@
},
{
"BriefDescription": "Number of times HLE commit succeeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.COMMIT",
"PublicDescription": "Number of times HLE commit succeeded.",
@@ -72,8 +58,6 @@
},
{
"BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.START",
"PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
@@ -92,8 +74,6 @@
},
{
"BriefDescription": "Randomly selected loads with latency value being above 128",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -103,13 +83,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 128.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 16",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -119,13 +96,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 16.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 256",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -135,13 +109,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 256.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 32",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -151,13 +122,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 32.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 4",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -167,13 +135,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above four.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 512",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -183,13 +148,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 512.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 64",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -199,13 +161,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 64.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 8",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -215,13 +174,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above eight.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
@@ -230,8 +186,6 @@
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
@@ -240,236 +194,177 @@
},
{
"BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63BC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87FC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63BC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87FC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all requests miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC08FFF",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of times RTM abort was triggered",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
@@ -479,8 +374,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@@ -489,8 +382,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
@@ -499,8 +390,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
@@ -509,8 +398,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times a RTM caused a fault.",
@@ -519,8 +406,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
@@ -529,8 +414,6 @@
},
{
"BriefDescription": "Number of times RTM commit succeeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
"PublicDescription": "Number of times RTM commit succeeded.",
@@ -539,8 +422,6 @@
},
{
"BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
"PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
@@ -549,8 +430,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003",
@@ -558,8 +437,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
@@ -568,8 +445,6 @@
},
{
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@@ -578,8 +453,6 @@
},
{
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4",
"PublicDescription": "RTM region detected inside HLE.",
@@ -588,8 +461,6 @@
},
{
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5",
"SampleAfterValue": "2000003",
@@ -597,8 +468,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
@@ -607,8 +476,6 @@
},
{
"BriefDescription": "Number of times a TSX line had a cache conflict",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"PublicDescription": "Number of times a TSX line had a cache conflict.",
@@ -617,8 +484,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@@ -627,8 +492,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@@ -637,8 +500,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@@ -647,8 +508,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@@ -657,8 +516,6 @@
},
{
"BriefDescription": "Number of times we could not allocate Lock Buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"PublicDescription": "Number of times we could not allocate Lock Buffer.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/other.json b/tools/perf/pmu-events/arch/x86/broadwellx/other.json
index 917d145d5227..1c2a5b001949 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/other.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/other.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Unhalted core cycles when the thread is in ring 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0",
"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
@@ -23,8 +19,6 @@
},
{
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123",
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
@@ -33,8 +27,6 @@
},
{
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json
index f0f30081d683..75233316640b 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles when divider is busy executing divide operations",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x14",
"EventName": "ARITH.FPU_DIV_ACTIVE",
"PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Speculative and retired branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_BRANCHES",
"PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Speculative and retired macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_CONDITIONAL",
"PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_JMP",
"PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "Speculative and retired direct near calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.",
@@ -51,8 +41,6 @@
},
{
"BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "Speculative and retired indirect return branches.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN",
"PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.",
@@ -71,8 +57,6 @@
},
{
"BriefDescription": "Not taken macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "This event counts not taken macro-conditional branch instructions.",
@@ -81,8 +65,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.",
@@ -91,8 +73,6 @@
},
{
"BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP",
"PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.",
@@ -101,8 +81,6 @@
},
{
"BriefDescription": "Taken speculative and retired direct near calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL",
"PublicDescription": "This event counts taken speculative and retired direct near calls.",
@@ -111,8 +89,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.",
@@ -121,8 +97,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect calls",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.",
@@ -131,8 +105,6 @@
},
{
"BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x88",
"EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN",
"PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.",
@@ -141,8 +113,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"PublicDescription": "This event counts all (macro) branch instructions retired.",
@@ -150,8 +120,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDW98",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
@@ -162,8 +130,6 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -173,8 +139,6 @@
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDW98",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
@@ -184,8 +148,6 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -195,8 +157,6 @@
},
{
"BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL_R3",
"PEBS": "1",
@@ -206,8 +166,6 @@
},
{
"BriefDescription": "Return instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
"PEBS": "1",
@@ -217,8 +175,6 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -228,8 +184,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
"PublicDescription": "This event counts not taken branch instructions retired.",
@@ -238,8 +192,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_BRANCHES",
"PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.",
@@ -248,8 +200,6 @@
},
{
"BriefDescription": "Speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_CONDITIONAL",
"PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -258,8 +208,6 @@
},
{
"BriefDescription": "Mispredicted indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.",
@@ -268,8 +216,6 @@
},
{
"BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL",
"PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -278,8 +224,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted macro conditional branches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL",
"PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.",
@@ -288,8 +232,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET",
"PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.",
@@ -298,8 +240,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect calls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL",
"SampleAfterValue": "200003",
@@ -307,8 +247,6 @@
},
{
"BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x89",
"EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR",
"PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.",
@@ -317,8 +255,6 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "This event counts all mispredicted macro branch instructions retired.",
@@ -326,8 +262,6 @@
},
{
"BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -337,8 +271,6 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -348,8 +280,6 @@
},
{
"BriefDescription": "number of near branch instructions retired that were mispredicted and taken.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -359,8 +289,6 @@
},
{
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1",
@@ -370,8 +298,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0x3c",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "100003",
@@ -379,8 +305,6 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.",
@@ -390,8 +314,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "100003",
@@ -399,8 +321,6 @@
},
{
"BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "100003",
@@ -408,8 +328,6 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
@@ -417,8 +335,6 @@
},
{
"BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
@@ -428,8 +344,6 @@
{
"AnyThread": "1",
"BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "100003",
@@ -437,8 +351,6 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
@@ -447,16 +359,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@@ -465,16 +373,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -483,8 +387,6 @@
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
@@ -494,8 +396,6 @@
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -504,8 +404,6 @@
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING",
@@ -515,8 +413,6 @@
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
@@ -526,8 +422,6 @@
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -536,8 +430,6 @@
},
{
"BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
@@ -547,8 +439,6 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -557,8 +447,6 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "Counter": "2",
- "CounterHTOff": "2",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING",
@@ -568,8 +456,6 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -578,8 +464,6 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING",
@@ -589,8 +473,6 @@
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING",
@@ -600,8 +482,6 @@
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -610,8 +490,6 @@
},
{
"BriefDescription": "Total execution stalls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -620,8 +498,6 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
@@ -630,8 +506,6 @@
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
"SampleAfterValue": "2000003",
@@ -639,8 +513,6 @@
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM61",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
@@ -649,8 +521,6 @@
},
{
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
- "Counter": "1",
- "CounterHTOff": "1",
"Errata": "BDM11, BDM55",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
@@ -661,8 +531,6 @@
},
{
"BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.X87",
"PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
@@ -671,8 +539,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RAT_STALL_CYCLES",
"PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",
@@ -681,8 +547,6 @@
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
@@ -693,8 +557,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
@@ -703,8 +565,6 @@
},
{
"BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"SampleAfterValue": "100003",
@@ -712,8 +572,6 @@
},
{
"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",
@@ -722,8 +580,6 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
@@ -732,8 +588,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.HW_PF",
"PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.",
@@ -742,8 +596,6 @@
},
{
"BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4c",
"EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.",
@@ -752,8 +604,6 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@@ -762,8 +612,6 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -772,8 +620,6 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"SampleAfterValue": "2000003",
@@ -781,8 +627,6 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xC3",
@@ -792,8 +636,6 @@
},
{
"BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.CYCLES",
"PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.",
@@ -802,8 +644,6 @@
},
{
"BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MASKMOV",
"PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
@@ -812,8 +652,6 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.",
@@ -822,8 +660,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -831,8 +667,6 @@
},
{
"BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
@@ -840,8 +674,6 @@
},
{
"BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY_WB_ASSIST",
"SampleAfterValue": "100003",
@@ -849,8 +681,6 @@
},
{
"BriefDescription": "Resource-related stall cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.ANY",
"PublicDescription": "This event counts resource-related stall cycles.",
@@ -859,8 +689,6 @@
},
{
"BriefDescription": "Cycles stalled due to re-order buffer full.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.ROB",
"PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -869,8 +697,6 @@
},
{
"BriefDescription": "Cycles stalled due to no eligible RS entry available.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.RS",
"PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -879,8 +705,6 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
@@ -889,8 +713,6 @@
},
{
"BriefDescription": "Count cases of saving new LBR",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.",
@@ -899,8 +721,6 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
@@ -909,8 +729,6 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -921,8 +739,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
@@ -931,8 +747,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
@@ -941,8 +755,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
@@ -951,8 +763,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
@@ -961,8 +771,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
@@ -971,8 +779,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
@@ -981,8 +787,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_6",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
@@ -991,8 +795,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_7",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
@@ -1001,8 +803,6 @@
},
{
"BriefDescription": "Number of uops executed on the core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
"PublicDescription": "Number of uops executed from any thread.",
@@ -1011,8 +811,6 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -1021,8 +819,6 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -1031,8 +827,6 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -1041,8 +835,6 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -1051,8 +843,6 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xb1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
"Invert": "1",
@@ -1061,8 +851,6 @@
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -1071,8 +859,6 @@
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -1081,8 +867,6 @@
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -1091,8 +875,6 @@
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -1101,8 +883,6 @@
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -1113,8 +893,6 @@
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.THREAD",
"PublicDescription": "Number of uops to be executed per-thread each cycle.",
@@ -1123,8 +901,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
@@ -1134,8 +910,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE",
"SampleAfterValue": "2000003",
@@ -1143,8 +917,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
@@ -1154,8 +926,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 1.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE",
"SampleAfterValue": "2000003",
@@ -1163,8 +933,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
@@ -1174,8 +942,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE",
"SampleAfterValue": "2000003",
@@ -1183,8 +949,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
@@ -1194,8 +958,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 3.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE",
"SampleAfterValue": "2000003",
@@ -1203,8 +965,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
@@ -1214,8 +974,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 4.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE",
"SampleAfterValue": "2000003",
@@ -1223,8 +981,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
@@ -1234,8 +990,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 5.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE",
"SampleAfterValue": "2000003",
@@ -1243,8 +997,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
@@ -1254,8 +1006,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are exectuted in port 6.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE",
"SampleAfterValue": "2000003",
@@ -1263,8 +1013,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7",
"PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
@@ -1274,8 +1022,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles per core when uops are dispatched to port 7.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE",
"SampleAfterValue": "2000003",
@@ -1283,8 +1029,6 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",
@@ -1293,8 +1037,6 @@
},
{
"BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.FLAGS_MERGE",
"PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.",
@@ -1303,8 +1045,6 @@
},
{
"BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SINGLE_MUL",
"SampleAfterValue": "2000003",
@@ -1312,8 +1052,6 @@
},
{
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA",
"SampleAfterValue": "2000003",
@@ -1321,8 +1059,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -1333,8 +1069,6 @@
},
{
"BriefDescription": "Actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.ALL",
"PEBS": "1",
@@ -1344,8 +1078,6 @@
},
{
"BriefDescription": "Retirement slots used.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PEBS": "1",
@@ -1355,8 +1087,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -1367,8 +1097,6 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json
index 449fa723d0aa..746954775437 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json
@@ -1,789 +1,1100 @@
[
{
- "BriefDescription": "Bounce Control",
- "Counter": "0,1,2,3",
- "EventCode": "0xA",
- "EventName": "UNC_C_BOUNCE_CONTROL",
+ "BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.CODE_LLC_PREFETCH",
+ "Filter": "filter_opc=0x191",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
- "EventName": "UNC_C_CLOCKTICKS",
+ "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.DATA_LLC_PREFETCH",
+ "Filter": "filter_opc=0x192",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Counter 0 Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x1F",
- "EventName": "UNC_C_COUNTER0_OCCUPANCY",
+ "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.DATA_READ",
+ "Filter": "filter_opc=0x182",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "FaST wire asserted",
- "Counter": "0,1",
- "EventCode": "0x9",
- "EventName": "UNC_C_FAST_ASSERTED",
+ "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.MMIO_READ",
+ "Filter": "filter_opc=0x187,filter_nc=1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Cache Lookups; Data Read Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+ "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.MMIO_WRITE",
+ "Filter": "filter_opc=0x18f,filter_nc=1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Cache Lookups; Write Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.WRITE",
+ "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE",
+ "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Cache Lookups; External Snoop Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
+ "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.PCIE_READ",
+ "Filter": "filter_opc=0x19e",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.ANY",
- "Filter": "filter_state=0x1",
+ "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.PCIE_WRITE",
+ "Filter": "filter_opc=0x1c8",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
"ScaleUnit": "64Bytes",
- "UMask": "0x11",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Cache Lookups; Lookups that Match NID",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.NID",
+ "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.RFO_LLC_PREFETCH",
+ "Filter": "filter_opc=0x190",
"PerPkg": "1",
- "UMask": "0x41",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Cache Lookups; Any Read Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.READ",
+ "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.UNCACHEABLE",
+ "Filter": "filter_opc=0x187",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "M line evictions from LLC (writebacks to memory)",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+ "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH",
+ "Filter": "filter_opc=0x181",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
"ScaleUnit": "64Bytes",
"UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Lines Victimized; Lines in E state",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
+ "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE",
+ "Filter": "filter_opc=0x180,filter_tid=0x3e",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Lines Victimized; Lines in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
+ "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.PCIE_READ",
+ "Filter": "filter_opc=0x19e",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Lines Victimized",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
+ "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.PCIE_WRITE",
+ "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.NID",
+ "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.STREAMING_FULL",
+ "Filter": "filter_opc=0x18c",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Lines Victimized",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.MISS",
+ "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
+ "Filter": "filter_opc=0x18d",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
+ "BriefDescription": "Bounce Control",
+ "EventCode": "0xA",
+ "EventName": "UNC_C_BOUNCE_CONTROL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "UNC_C_BOUNCE_CONTROL",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc; Write Combining Aliasing",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_C_MISC.WC_ALIASING",
+ "BriefDescription": "Uncore Clocks",
+ "EventName": "UNC_C_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "UNC_C_CLOCKTICKS",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_C_MISC.STARTED",
+ "BriefDescription": "Counter 0 Occupancy",
+ "EventCode": "0x1F",
+ "EventName": "UNC_C_COUNTER0_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc; RFO HitS",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_C_MISC.RFO_HIT_S",
+ "BriefDescription": "FaST wire asserted",
+ "EventCode": "0x9",
+ "EventName": "UNC_C_FAST_ASSERTED",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles either the local distress or incoming distress signals are asserted. Incoming distress includes both up and dn.",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
+ "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.ANY",
+ "Filter": "filter_state=0x1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x11",
"Unit": "CBO"
},
{
- "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
+ "BriefDescription": "Cache Lookups; Data Read Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
+ "BriefDescription": "Cache Lookups; Lookups that Match NID",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.NID",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+ "UMask": "0x41",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.UP_ODD",
+ "BriefDescription": "Cache Lookups; Any Read Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.READ",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions",
+ "UMask": "0x21",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
+ "BriefDescription": "Cache Lookups; External Snoop Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
+ "UMask": "0x9",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
+ "BriefDescription": "Cache Lookups; Write Requests",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.WRITE",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC.",
+ "UMask": "0x5",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; Up",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.UP",
+ "BriefDescription": "Lines Victimized; Lines in E state",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; Down",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.DOWN",
+ "BriefDescription": "Lines Victimized",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
- "BriefDescription": "AD Ring In Use; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_C_RING_AD_USED.ALL",
+ "BriefDescription": "Lines Victimized; Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.I_STATE",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "AK Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
+ "BriefDescription": "Lines Victimized",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.MISS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "AK Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_C_RING_AK_USED.UP_ODD",
+ "BriefDescription": "M line evictions from LLC (writebacks to memory)",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Lines Victimized; Victimized Lines that Match NID",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.NID",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+ "UMask": "0x40",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0",
+ "EventCode": "0x39",
+ "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS",
+ "PerPkg": "1",
+ "PublicDescription": "Miscellaneous events in the Cbo.",
+ "UMask": "0x20",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0",
+ "EventCode": "0x39",
+ "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM",
+ "PerPkg": "1",
+ "PublicDescription": "Miscellaneous events in the Cbo.",
+ "UMask": "0x10",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Cbo Misc; RFO HitS",
+ "EventCode": "0x39",
+ "EventName": "UNC_C_MISC.RFO_HIT_S",
+ "PerPkg": "1",
+ "PublicDescription": "Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state. This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.",
+ "UMask": "0x8",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
+ "EventCode": "0x39",
+ "EventName": "UNC_C_MISC.RSPI_WAS_FSE",
+ "PerPkg": "1",
+ "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Cbo Misc",
+ "EventCode": "0x39",
+ "EventName": "UNC_C_MISC.STARTED",
+ "PerPkg": "1",
+ "PublicDescription": "Miscellaneous events in the Cbo.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Cbo Misc; Write Combining Aliasing",
+ "EventCode": "0x39",
+ "EventName": "UNC_C_MISC.WC_ALIASING",
+ "PerPkg": "1",
+ "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.",
+ "UMask": "0x2",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "LRU Queue; LRU Age 0",
+ "EventCode": "0x3C",
+ "EventName": "UNC_C_QLRU.AGE0",
+ "PerPkg": "1",
+ "PublicDescription": "How often age was set to 0",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "LRU Queue; LRU Age 1",
+ "EventCode": "0x3C",
+ "EventName": "UNC_C_QLRU.AGE1",
+ "PerPkg": "1",
+ "PublicDescription": "How often age was set to 1",
+ "UMask": "0x2",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "LRU Queue; LRU Age 2",
+ "EventCode": "0x3C",
+ "EventName": "UNC_C_QLRU.AGE2",
+ "PerPkg": "1",
+ "PublicDescription": "How often age was set to 2",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "LRU Queue; LRU Age 3",
+ "EventCode": "0x3C",
+ "EventName": "UNC_C_QLRU.AGE3",
+ "PerPkg": "1",
+ "PublicDescription": "How often age was set to 3",
+ "UMask": "0x8",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "LRU Queue; LRU Bits Decremented",
+ "EventCode": "0x3C",
+ "EventName": "UNC_C_QLRU.LRU_DECREMENT",
+ "PerPkg": "1",
+ "PublicDescription": "How often all LRU bits were decremented by 1",
+ "UMask": "0x10",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "LRU Queue; Non-0 Aged Victim",
+ "EventCode": "0x3C",
+ "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
+ "PerPkg": "1",
+ "PublicDescription": "How often we picked a victim that had a non-zero age",
+ "UMask": "0x20",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "AD Ring In Use; All",
+ "EventCode": "0x1B",
+ "EventName": "UNC_C_RING_AD_USED.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xf",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "AD Ring In Use; Down",
+ "EventCode": "0x1B",
+ "EventName": "UNC_C_RING_AD_USED.DOWN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX-- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "AD Ring In Use; Down and Even",
+ "EventCode": "0x1B",
+ "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "AD Ring In Use; Down and Odd",
+ "EventCode": "0x1B",
+ "EventName": "UNC_C_RING_AD_USED.DOWN_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
+ "UMask": "0x8",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "AD Ring In Use; Up",
+ "EventCode": "0x1B",
+ "EventName": "UNC_C_RING_AD_USED.UP",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x3",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "AD Ring In Use; Up and Even",
+ "EventCode": "0x1B",
+ "EventName": "UNC_C_RING_AD_USED.UP_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "AD Ring In Use; Up and Odd",
+ "EventCode": "0x1B",
+ "EventName": "UNC_C_RING_AD_USED.UP_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
"UMask": "0x2",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "AK Ring In Use; All",
+ "EventCode": "0x1C",
+ "EventName": "UNC_C_RING_AK_USED.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xf",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "AK Ring In Use; Down",
+ "EventCode": "0x1C",
+ "EventName": "UNC_C_RING_AK_USED.DOWN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "AK Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
"UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "AK Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_C_RING_AK_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "AK Ring In Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Up and Even",
"EventCode": "0x1C",
- "EventName": "UNC_C_RING_AK_USED.DOWN",
+ "EventName": "UNC_C_RING_AK_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "AK Ring In Use; All",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Up and Odd",
"EventCode": "0x1C",
- "EventName": "UNC_C_RING_AK_USED.ALL",
+ "EventName": "UNC_C_RING_AK_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "BL Ring in Use; Up and Even",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Down",
"EventCode": "0x1D",
- "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
+ "EventName": "UNC_C_RING_BL_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
- "BriefDescription": "BL Ring in Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Down",
"EventCode": "0x1D",
- "EventName": "UNC_C_RING_BL_USED.UP_ODD",
+ "EventName": "UNC_C_RING_BL_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.",
"UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_C_RING_BL_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Up and Even",
"EventCode": "0x1D",
- "EventName": "UNC_C_RING_BL_USED.DOWN",
+ "EventName": "UNC_C_RING_BL_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Up and Odd",
"EventCode": "0x1D",
- "EventName": "UNC_C_RING_BL_USED.ALL",
+ "EventName": "UNC_C_RING_BL_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; AD",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AD",
"PerPkg": "1",
+ "PublicDescription": "UNC_C_RING_BOUNCES.AD",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; AK",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.AK",
"PerPkg": "1",
+ "PublicDescription": "UNC_C_RING_BOUNCES.AK",
"UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; BL",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.BL",
"PerPkg": "1",
+ "PublicDescription": "UNC_C_RING_BOUNCES.BL",
"UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
"EventCode": "0x5",
"EventName": "UNC_C_RING_BOUNCES.IV",
"PerPkg": "1",
+ "PublicDescription": "UNC_C_RING_BOUNCES.IV",
"UMask": "0x10",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.ANY",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0xf",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
- "EventName": "UNC_C_RING_IV_USED.UP",
+ "EventName": "UNC_C_RING_IV_USED.DN",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0xc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_C_RING_IV_USED.DOWN",
"PerPkg": "1",
- "UMask": "0xCC",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity",
+ "UMask": "0xcc",
"Unit": "CBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
- "EventName": "UNC_C_RING_IV_USED.DN",
- "PerPkg": "1",
- "UMask": "0xC",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic",
- "Counter": "0,1,2,3",
- "EventCode": "0x7",
- "EventName": "UNC_C_RING_SRC_THRTL",
+ "EventName": "UNC_C_RING_IV_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
+ "BriefDescription": "AD",
+ "EventCode": "0x6",
+ "EventName": "UNC_C_RING_SINK_STARVED.AD",
"PerPkg": "1",
+ "PublicDescription": "UNC_C_RING_SINK_STARVED.AD",
"UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+ "BriefDescription": "AK",
+ "EventCode": "0x6",
+ "EventName": "UNC_C_RING_SINK_STARVED.AK",
"PerPkg": "1",
+ "PublicDescription": "UNC_C_RING_SINK_STARVED.AK",
"UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
+ "BriefDescription": "BL",
+ "EventCode": "0x6",
+ "EventName": "UNC_C_RING_SINK_STARVED.BL",
"PerPkg": "1",
+ "PublicDescription": "UNC_C_RING_SINK_STARVED.BL",
"UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
+ "BriefDescription": "IV",
+ "EventCode": "0x6",
+ "EventName": "UNC_C_RING_SINK_STARVED.IV",
"PerPkg": "1",
+ "PublicDescription": "UNC_C_RING_SINK_STARVED.IV",
"UMask": "0x8",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Allocations; IRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_C_RxR_INSERTS.IRQ",
+ "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.",
+ "EventCode": "0x7",
+ "EventName": "UNC_C_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "UNC_C_RING_SRC_THRTL",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Allocations; IRQ Rejected",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
- "PerPkg": "1",
- "UMask": "0x2",
+ "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ",
+ "EventCode": "0x12",
+ "EventName": "UNC_C_RxR_EXT_STARVED.IPQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.",
+ "UMask": "0x2",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ",
+ "EventCode": "0x12",
+ "EventName": "UNC_C_RxR_EXT_STARVED.IRQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID",
+ "EventCode": "0x12",
+ "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.",
+ "UMask": "0x8",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ",
+ "EventCode": "0x12",
+ "EventName": "UNC_C_RxR_EXT_STARVED.PRQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Allocations; IPQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.IPQ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x4",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Ingress Allocations; IRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_C_RxR_INSERTS.IRQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Ingress Allocations; IRQ Rejected",
+ "EventCode": "0x13",
+ "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x2",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Ingress Allocations; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.PRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x10",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Allocations; PRQ",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_C_RxR_INSERTS.PRQ_REJ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
"UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "Probe Queue Retries; Any Reject",
- "Counter": "0,1,2,3",
- "EventCode": "0x31",
- "EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
+ "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
+ "EventCode": "0x14",
+ "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
+ "EventCode": "0x14",
+ "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.",
"UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "Probe Queue Retries; No Egress Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x31",
- "EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
+ "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
+ "EventCode": "0x14",
+ "EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.",
+ "UMask": "0x8",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Ingress Internal Starvation Cycles; PRQ",
+ "EventCode": "0x14",
+ "EventName": "UNC_C_RxR_INT_STARVED.PRQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.",
+ "UMask": "0x10",
"Unit": "CBO"
},
{
"BriefDescription": "Probe Queue Retries; Address Conflict",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts. Address conflicts out of the IPQ should be rare. They will generally only occur if two different sockets are sending requests to the same address at the same time. This is a true conflict case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.",
"UMask": "0x4",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Probe Queue Retries; Any Reject",
+ "EventCode": "0x31",
+ "EventName": "UNC_C_RxR_IPQ_RETRY.ANY",
+ "PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject. TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.",
+ "UMask": "0x1",
+ "Unit": "CBO"
+ },
+ {
+ "BriefDescription": "Probe Queue Retries; No Egress Credits",
+ "EventCode": "0x31",
+ "EventName": "UNC_C_RxR_IPQ_RETRY.FULL",
+ "PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full. IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.",
+ "UMask": "0x2",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Probe Queue Retries; No QPI Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.",
"UMask": "0x10",
"Unit": "CBO"
},
{
"BriefDescription": "Probe Queue Retries; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Probe Queue Retries; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET",
"PerPkg": "1",
+ "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
"UMask": "0x40",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
+ "EventCode": "0x32",
+ "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IRQ was retried because of an address match in the TOR. In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo. Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete. This comes up most commonly with prefetches. Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC. Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Ingress Request Queue Rejects; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.ANY",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of IRQ retries that occur. Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons. Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress. The egress is the buffer that queues up for allocating onto the ring. IRQ requests can make use of all four rings and all four Egresses. If any of the queues that a given request needs to make use of are full, the request will be retried.",
"UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Request Queue Rejects; Address Conflict",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
"EventCode": "0x32",
- "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT",
+ "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+ "UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Request Queue Rejects",
"EventCode": "0x32",
- "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
+ "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+ "UMask": "0x40",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; No QPI Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
+ "PublicDescription": "Number of requests rejects because of lack of QPI Ingress credits. These credits are required in order to send transactions to the QPI agent. Please see the QPI_IGR_CREDITS events for more information.",
"UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Ingress Request Queue Rejects",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Ingress Request Queue Rejects; No RTIDs",
"EventCode": "0x32",
- "EventName": "UNC_C_RxR_IRQ_RETRY.NID",
+ "EventName": "UNC_C_RxR_IRQ_RETRY.RTID",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of times that requests from the IRQ were retried because there were no RTIDs available. RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory. If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available. Note that there are multiple RTID pools for the different sockets. There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available. This event does not provide any filtering for this case.",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo.",
"UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "Ingress Request Queue Rejects; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
"UMask": "0x40",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Retries; Any Reject",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.ANY",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject. ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries). ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID. Most ISMQ requests already have an RTID, so eviction retries will be less common here.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Retries; No Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_C_RxR_ISMQ_RETRY.FULL",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring. If any of the Egress queues that a given request needs to make use of are full, the request will be retried.",
"UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "ISMQ Retries; No RTIDs",
- "Counter": "0,1,2,3",
+ "BriefDescription": "ISMQ Retries; No IIO Credits",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.",
+ "UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "ISMQ Retries; No QPI Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "ISMQ Retries",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+ "UMask": "0x40",
"Unit": "CBO"
},
{
- "BriefDescription": "ISMQ Retries; No IIO Credits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "ISMQ Retries; No QPI Credits",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
+ "BriefDescription": "ISMQ Retries; No RTIDs",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs. M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory. If no RTIDs are available, they will be retried.",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Retries",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
- "EventName": "UNC_C_RxR_ISMQ_RETRY.NID",
+ "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.",
+ "UMask": "0x80",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo.",
"UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.",
"UMask": "0x40",
"Unit": "CBO"
},
+ {
+ "BriefDescription": "Ingress Occupancy; IPQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x4",
+ "Unit": "CBO"
+ },
{
"BriefDescription": "Ingress Occupancy; IRQ",
"EventCode": "0x11",
"EventName": "UNC_C_RxR_OCCUPANCY.IRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x1",
"Unit": "CBO"
},
@@ -792,40 +1103,34 @@
"EventCode": "0x11",
"EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x2",
"Unit": "CBO"
},
- {
- "BriefDescription": "Ingress Occupancy; IPQ",
- "EventCode": "0x11",
- "EventName": "UNC_C_RxR_OCCUPANCY.IPQ",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "CBO"
- },
{
"BriefDescription": "Ingress Occupancy; PRQ Rejects",
"EventCode": "0x11",
"EventName": "UNC_C_RxR_OCCUPANCY.PRQ_REJ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x20",
"Unit": "CBO"
},
{
"BriefDescription": "SBo Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "SBo Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.",
"UMask": "0x2",
"Unit": "CBO"
},
@@ -834,6 +1139,7 @@
"EventCode": "0x3E",
"EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.",
"UMask": "0x1",
"Unit": "CBO"
},
@@ -842,411 +1148,288 @@
"EventCode": "0x3E",
"EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.",
"UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Opcode Match",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; All",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.OPCODE",
+ "EventName": "UNC_C_TOR_INSERTS.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
- "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Evictions",
"EventCode": "0x35",
- "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE",
- "Filter": "filter_opc=0x180,filter_tid=0x3e",
+ "EventName": "UNC_C_TOR_INSERTS.EVICTION",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Local Memory",
"EventCode": "0x35",
- "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH",
- "Filter": "filter_opc=0x181",
+ "EventName": "UNC_C_TOR_INSERTS.LOCAL",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by locally HOMed memory.",
+ "UMask": "0x28",
"Unit": "CBO"
},
{
- "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
"EventCode": "0x35",
- "EventName": "LLC_REFERENCES.STREAMING_FULL",
- "Filter": "filter_opc=0x18c",
+ "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.",
+ "UMask": "0x21",
"Unit": "CBO"
},
{
- "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Misses to Local Memory",
"EventCode": "0x35",
- "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
- "Filter": "filter_opc=0x18d",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.",
+ "UMask": "0x2a",
"Unit": "CBO"
},
{
- "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
"EventCode": "0x35",
- "EventName": "LLC_REFERENCES.PCIE_READ",
- "Filter": "filter_opc=0x19e",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.",
+ "UMask": "0x23",
"Unit": "CBO"
},
{
- "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Miss Opcode Match",
"EventCode": "0x35",
- "EventName": "LLC_REFERENCES.PCIE_WRITE",
- "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Evictions",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Misses to Remote Memory",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.EVICTION",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
+ "UMask": "0x8a",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; All",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.ALL",
+ "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.",
+ "UMask": "0x83",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Writebacks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID Matched",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.WB",
+ "EventName": "UNC_C_TOR_INSERTS.NID_ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+ "UMask": "0x48",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Miss Opcode Match",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID Matched Evictions",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE",
+ "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.",
+ "UMask": "0x44",
"Unit": "CBO"
},
{
- "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID Matched Miss All",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.DATA_READ",
- "Filter": "filter_opc=0x182",
+ "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.",
+ "UMask": "0x4a",
"Unit": "CBO"
},
{
- "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
"EventCode": "0x35",
- "EventName": "LLC_MISSES.UNCACHEABLE",
- "Filter": "filter_opc=0x187",
+ "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.MMIO_READ",
- "Filter": "filter_opc=0x187,filter_nc=1",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.MMIO_WRITE",
- "Filter": "filter_opc=0x18f,filter_nc=1",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.RFO_LLC_PREFETCH",
- "Filter": "filter_opc=0x190",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LLC prefetch misses for code reads. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.CODE_LLC_PREFETCH",
- "Filter": "filter_opc=0x191",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.DATA_LLC_PREFETCH",
- "Filter": "filter_opc=0x192",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.PCIE_READ",
- "Filter": "filter_opc=0x19e",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.PCIE_WRITE",
- "Filter": "filter_opc=0x1c8",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE",
- "Filter": "filter_opc=0x1c8,filter_tid=0x3e",
- "PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.",
+ "UMask": "0x43",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Inserts; NID and Opcode Matched",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_OPCODE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.",
"UMask": "0x41",
"Unit": "CBO"
},
- {
- "BriefDescription": "TOR Inserts; NID Matched Evictions",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION",
- "PerPkg": "1",
- "UMask": "0x44",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "TOR Inserts; NID Matched",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_ALL",
- "PerPkg": "1",
- "UMask": "0x48",
- "Unit": "CBO"
- },
{
"BriefDescription": "TOR Inserts; NID Matched Writebacks",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_C_TOR_INSERTS.NID_WB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.",
"UMask": "0x50",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Opcode Match",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE",
+ "EventName": "UNC_C_TOR_INSERTS.OPCODE",
"PerPkg": "1",
- "UMask": "0x43",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; NID Matched Miss All",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Remote Memory",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL",
+ "EventName": "UNC_C_TOR_INSERTS.REMOTE",
"PerPkg": "1",
- "UMask": "0x4A",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by remote caches or remote memory.",
+ "UMask": "0x88",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Misses to Local Memory",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL",
+ "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
"PerPkg": "1",
- "UMask": "0x2A",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.",
+ "UMask": "0x81",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Misses to Remote Memory",
- "Counter": "0,1,2,3",
+ "BriefDescription": "TOR Inserts; Writebacks",
"EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE",
+ "EventName": "UNC_C_TOR_INSERTS.WB",
"PerPkg": "1",
- "UMask": "0x8A",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core.",
+ "UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Local Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.LOCAL",
+ "BriefDescription": "TOR Occupancy; Any",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x28",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.",
+ "UMask": "0x8",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Remote Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.REMOTE",
+ "BriefDescription": "TOR Occupancy; Evictions",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION",
"PerPkg": "1",
- "UMask": "0x88",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).",
+ "UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE",
+ "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ",
+ "Filter": "filter_opc=0x182",
"PerPkg": "1",
- "UMask": "0x23",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
+ "UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE",
+ "BriefDescription": "TOR Occupancy",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
"PerPkg": "1",
- "UMask": "0x83",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+ "UMask": "0x28",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE",
+ "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
"PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.",
"UMask": "0x21",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE",
- "PerPkg": "1",
- "UMask": "0x81",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "TOR Occupancy; Opcode Match",
+ "BriefDescription": "TOR Occupancy; Miss All",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. 'Miss' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO.",
+ "UMask": "0xa",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; Evictions",
+ "BriefDescription": "TOR Occupancy",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+ "UMask": "0x2a",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; Any",
+ "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.ALL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.",
+ "UMask": "0x23",
"Unit": "CBO"
},
{
- "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode",
+ "BriefDescription": "TOR Occupancy; Miss Opcode Match",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ",
- "Filter": "filter_opc=0x182",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
"PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.",
"UMask": "0x3",
"Unit": "CBO"
},
{
- "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch)",
+ "BriefDescription": "TOR Occupancy",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE",
- "Filter": "filter_opc=0x182",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
+ "UMask": "0x8a",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; Miss All",
+ "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.",
+ "UMask": "0x83",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
+ "BriefDescription": "TOR Occupancy; NID Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
"PerPkg": "1",
- "UMask": "0x41",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.",
+ "UMask": "0x48",
"Unit": "CBO"
},
{
@@ -1254,15 +1437,17 @@
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION",
"PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .",
"UMask": "0x44",
"Unit": "CBO"
},
{
"BriefDescription": "TOR Occupancy; NID Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
"PerPkg": "1",
- "UMask": "0x48",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.",
+ "UMask": "0x4a",
"Unit": "CBO"
},
{
@@ -1270,39 +1455,35 @@
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE",
"PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.",
"UMask": "0x43",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy; NID Matched",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL",
- "PerPkg": "1",
- "UMask": "0x4A",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "TOR Occupancy",
+ "BriefDescription": "TOR Occupancy; NID and Opcode Matched",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE",
"PerPkg": "1",
- "UMask": "0x2A",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.",
+ "UMask": "0x41",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy",
+ "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE",
+ "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
"PerPkg": "1",
- "UMask": "0x8A",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.",
+ "UMask": "0x50",
"Unit": "CBO"
},
{
- "BriefDescription": "TOR Occupancy",
+ "BriefDescription": "TOR Occupancy; Opcode Match",
"EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL",
+ "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE",
"PerPkg": "1",
- "UMask": "0x28",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).",
+ "UMask": "0x1",
"Unit": "CBO"
},
{
@@ -1310,38 +1491,16 @@
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)",
"UMask": "0x88",
"Unit": "CBO"
},
- {
- "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE",
- "PerPkg": "1",
- "UMask": "0x23",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE",
- "PerPkg": "1",
- "UMask": "0x83",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE",
- "PerPkg": "1",
- "UMask": "0x21",
- "Unit": "CBO"
- },
{
"BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched",
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE",
"PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.",
"UMask": "0x81",
"Unit": "CBO"
},
@@ -1350,2297 +1509,2110 @@
"EventCode": "0x36",
"EventName": "UNC_C_TOR_OCCUPANCY.WB",
"PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR. This does not include RFO, but actual operations that contain data being sent from the core.",
"UMask": "0x10",
"Unit": "CBO"
},
- {
- "BriefDescription": "TOR Occupancy; NID Matched Writebacks",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB",
- "PerPkg": "1",
- "UMask": "0x50",
- "Unit": "CBO"
- },
{
"BriefDescription": "Onto AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.AD",
"PerPkg": "1",
+ "PublicDescription": "UNC_C_TxR_ADS_USED.AD",
"UMask": "0x1",
"Unit": "CBO"
},
{
"BriefDescription": "Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.AK",
"PerPkg": "1",
+ "PublicDescription": "UNC_C_TxR_ADS_USED.AK",
"UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_C_TxR_ADS_USED.BL",
"PerPkg": "1",
+ "PublicDescription": "UNC_C_TxR_ADS_USED.BL",
"UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "Egress Allocations; AD - Cachebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CACHE",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
"Unit": "CBO"
},
- {
- "BriefDescription": "Egress Allocations; AK - Cachebo",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Egress Allocations; BL - Cacheno",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Egress Allocations; IV - Cachebo",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "CBO"
- },
{
"BriefDescription": "Egress Allocations; AD - Corebo",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_C_TxR_INSERTS.AD_CORE",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
"Unit": "CBO"
},
{
- "BriefDescription": "Egress Allocations; AK - Corebo",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.AK_CORE",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Egress Allocations; BL - Corebo",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Egress Allocations; AK - Cachebo",
"EventCode": "0x2",
- "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LRU Queue; LRU Age 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x3C",
- "EventName": "UNC_C_QLRU.AGE0",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LRU Queue; LRU Age 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x3C",
- "EventName": "UNC_C_QLRU.AGE1",
+ "EventName": "UNC_C_TxR_INSERTS.AK_CACHE",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
"Unit": "CBO"
},
{
- "BriefDescription": "LRU Queue; LRU Age 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x3C",
- "EventName": "UNC_C_QLRU.AGE2",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LRU Queue; LRU Age 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x3C",
- "EventName": "UNC_C_QLRU.AGE3",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LRU Queue; LRU Bits Decremented",
- "Counter": "0,1,2,3",
- "EventCode": "0x3C",
- "EventName": "UNC_C_QLRU.LRU_DECREMENT",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "LRU Queue; Non-0 Aged Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x3C",
- "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO",
+ "BriefDescription": "Egress Allocations; AK - Corebo",
+ "EventCode": "0x2",
+ "EventName": "UNC_C_TxR_INSERTS.AK_CORE",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring. This is commonly used for snoop responses coming from the core and destined for a Cachebo.",
"UMask": "0x20",
"Unit": "CBO"
},
{
- "BriefDescription": "AD",
- "Counter": "0,1,2,3",
- "EventCode": "0x6",
- "EventName": "UNC_C_RING_SINK_STARVED.AD",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "AK",
- "Counter": "0,1,2,3",
- "EventCode": "0x6",
- "EventName": "UNC_C_RING_SINK_STARVED.AK",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x6",
- "EventName": "UNC_C_RING_SINK_STARVED.IV",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "BL",
- "Counter": "0,1,2,3",
- "EventCode": "0x6",
- "EventName": "UNC_C_RING_SINK_STARVED.BL",
+ "BriefDescription": "Egress Allocations; BL - Cacheno",
+ "EventCode": "0x2",
+ "EventName": "UNC_C_TxR_INSERTS.BL_CACHE",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Internal Starvation Cycles; IRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_C_RxR_INT_STARVED.IRQ",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "Ingress Internal Starvation Cycles; IPQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_C_RxR_INT_STARVED.IPQ",
+ "BriefDescription": "Egress Allocations; BL - Corebo",
+ "EventCode": "0x2",
+ "EventName": "UNC_C_TxR_INSERTS.BL_CORE",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_C_RxR_INT_STARVED.ISMQ",
+ "BriefDescription": "Egress Allocations; IV - Cachebo",
+ "EventCode": "0x2",
+ "EventName": "UNC_C_TxR_INSERTS.IV_CACHE",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring. This is commonly used for snoops to the cores.",
"UMask": "0x8",
"Unit": "CBO"
},
{
- "BriefDescription": "Ingress Internal Starvation Cycles; PRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_C_RxR_INT_STARVED.PRQ",
+ "BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
+ "EventCode": "0x3",
+ "EventName": "UNC_C_TxR_STARVED.AD_CORE",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation",
"UMask": "0x10",
"Unit": "CBO"
},
{
"BriefDescription": "Injection Starvation; Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.AK_BOTH",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation",
"UMask": "0x2",
"Unit": "CBO"
},
{
"BriefDescription": "Injection Starvation; Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.BL_BOTH",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation",
"UMask": "0x4",
"Unit": "CBO"
},
{
"BriefDescription": "Injection Starvation; Onto IV Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_C_TxR_STARVED.IV",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation",
"UMask": "0x8",
"Unit": "CBO"
},
- {
- "BriefDescription": "Injection Starvation; Onto AD Ring (to core)",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_C_TxR_STARVED.AD_CORE",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CBO"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; Address & Opcode Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.FILT",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; Address",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.ADDR",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; Opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.OPC",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; AD Opcodes",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.AD",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; BL Opcodes",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.BL",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "HA"
- },
- {
- "BriefDescription": "QPI Address/Opcode Match; AK Opcodes",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_H_ADDR_OPC_MATCH.AK",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "HA"
- },
{
"BriefDescription": "BT Cycles Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
- "EventName": "UNC_H_BT_CYCLES_NE",
- "PerPkg": "1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "HA to iMC Bypass; Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_H_BYPASS_IMC.TAKEN",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "HA to iMC Bypass; Not Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "HA"
- },
- {
- "BriefDescription": "uclks",
- "Counter": "0,1,2,3",
- "EventName": "UNC_H_CLOCKTICKS",
- "PerPkg": "1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Direct2Core Messages Sent",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_H_DIRECT2CORE_COUNT",
- "PerPkg": "1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Cycles when Direct2Core was Disabled",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
- "PerPkg": "1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Number of Reads that had Direct2Core Overridden",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
- "PerPkg": "1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Directory Lat Opt Return",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_H_DIRECTORY_LAT_OPT",
- "PerPkg": "1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Directory Lookups; Snoop Needed",
- "Counter": "0,1,2,3",
- "EventCode": "0xC",
- "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Directory Lookups; Snoop Not Needed",
- "Counter": "0,1,2,3",
- "EventCode": "0xC",
- "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Directory Updates; Directory Set",
- "Counter": "0,1,2,3",
- "EventCode": "0xD",
- "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Directory Updates; Directory Clear",
- "Counter": "0,1,2,3",
- "EventCode": "0xD",
- "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Directory Updates; Any Directory Update",
- "Counter": "0,1,2,3",
- "EventCode": "0xD",
- "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
- "PerPkg": "1",
- "UMask": "0x3",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.WBMTOI",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "HA"
- },
- {
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
+ "EventName": "UNC_H_BT_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT.",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.RSPFWDS",
+ "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.RSP",
+ "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.ALLOCS",
+ "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
"PerPkg": "1",
- "UMask": "0x70",
+ "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.EVICTS",
+ "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
"PerPkg": "1",
- "UMask": "0x42",
+ "PublicDescription": "Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.INVALS",
+ "BriefDescription": "HA to iMC Bypass; Not Taken",
+ "EventCode": "0x14",
+ "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x26",
+ "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.ALL",
+ "BriefDescription": "HA to iMC Bypass; Taken",
+ "EventCode": "0x14",
+ "EventName": "UNC_H_BYPASS_IMC.TAKEN",
"PerPkg": "1",
- "UMask": "0xFF",
+ "PublicDescription": "Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "UNC_H_HITME_HIT.HOM",
+ "BriefDescription": "uclks",
+ "EventName": "UNC_H_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent.",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
- "EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
+ "BriefDescription": "Direct2Core Messages Sent",
+ "EventCode": "0x11",
+ "EventName": "UNC_H_DIRECT2CORE_COUNT",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of Direct2Core messages sent",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
- "Counter": "0,1,2,3",
- "EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
+ "BriefDescription": "Cycles when Direct2Core was Disabled",
+ "EventCode": "0x12",
+ "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of cycles in which Direct2Core was disabled",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
- "EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
+ "BriefDescription": "Number of Reads that had Direct2Core Overridden",
+ "EventCode": "0x13",
+ "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of Reads where Direct2Core overridden",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
- "EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
+ "BriefDescription": "Directory Lat Opt Return",
+ "EventCode": "0x41",
+ "EventName": "UNC_H_DIRECTORY_LAT_OPT",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory returned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
- "EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
+ "BriefDescription": "Directory Lookups; Snoop Not Needed",
+ "EventCode": "0xC",
+ "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
- "EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
+ "BriefDescription": "Directory Lookups; Snoop Needed",
+ "EventCode": "0xC",
+ "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
- "EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
+ "BriefDescription": "Directory Updates; Any Directory Update",
+ "EventCode": "0xD",
+ "EventName": "UNC_H_DIRECTORY_UPDATE.ANY",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.",
+ "UMask": "0x3",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
- "EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
+ "BriefDescription": "Directory Updates; Directory Clear",
+ "EventCode": "0xD",
+ "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory clears. This occurs when snoops were sent and all returned with RspI.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
+ "BriefDescription": "Directory Updates; Directory Set",
+ "EventCode": "0xD",
+ "EventName": "UNC_H_DIRECTORY_UPDATE.SET",
"PerPkg": "1",
- "UMask": "0xFF",
+ "PublicDescription": "Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory sets. This occurs when a remote read transaction requests memory, bringing it to a remote cache.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x72",
- "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is AckCnfltWbI",
+ "EventCode": "0x71",
+ "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "UNC_H_HITME_HIT.ACKCNFLTWBI",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; All Requests",
+ "EventCode": "0x71",
+ "EventName": "UNC_H_HITME_HIT.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "UNC_H_HITME_HIT.ALL",
+ "UMask": "0xff",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
+ "EventCode": "0x71",
+ "EventName": "UNC_H_HITME_HIT.ALLOCS",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "UNC_H_HITME_HIT.ALLOCS",
+ "UMask": "0x70",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocations",
+ "EventCode": "0x71",
+ "EventName": "UNC_H_HITME_HIT.EVICTS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "UNC_H_HITME_HIT.EVICTS",
+ "UMask": "0x42",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Requests",
+ "EventCode": "0x71",
+ "EventName": "UNC_H_HITME_HIT.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "UNC_H_HITME_HIT.HOM",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalidations",
+ "EventCode": "0x71",
+ "EventName": "UNC_H_HITME_HIT.INVALS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "UNC_H_HITME_HIT.INVALS",
+ "UMask": "0x26",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
+ "EventCode": "0x71",
+ "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "UNC_H_HITME_HIT.READ_OR_INVITOE",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
+ "EventCode": "0x71",
+ "EventName": "UNC_H_HITME_HIT.RSP",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "UNC_H_HITME_HIT.RSP",
+ "UMask": "0x80",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.RSP",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
+ "EventCode": "0x71",
+ "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "UNC_H_HITME_HIT.RSPFWDI_LOCAL",
+ "UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
+ "EventCode": "0x71",
+ "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
"PerPkg": "1",
- "UMask": "0x70",
+ "PublicDescription": "UNC_H_HITME_HIT.RSPFWDI_REMOTE",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.INVALS",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is RsSFwd or RspSFwdWb",
+ "EventCode": "0x71",
+ "EventName": "UNC_H_HITME_HIT.RSPFWDS",
"PerPkg": "1",
- "UMask": "0x26",
+ "PublicDescription": "UNC_H_HITME_HIT.RSPFWDS",
+ "UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.ALL",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE or WbMtoS",
+ "EventCode": "0x71",
+ "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S",
"PerPkg": "1",
- "UMask": "0xFF",
+ "PublicDescription": "UNC_H_HITME_HIT.WBMTOE_OR_S",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x70",
- "EventName": "UNC_H_HITME_LOOKUP.HOM",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI",
+ "EventCode": "0x71",
+ "EventName": "UNC_H_HITME_HIT.WBMTOI",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "UNC_H_HITME_HIT.WBMTOI",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is AckCnfltWbI",
+ "EventCode": "0x72",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; All Requests",
+ "EventCode": "0x72",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.ALL",
+ "UMask": "0xff",
"Unit": "HA"
},
{
- "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; HOM Requests",
+ "EventCode": "0x72",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.HOM",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
+ "EventCode": "0x72",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
+ "EventCode": "0x72",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSP",
+ "UMask": "0x80",
"Unit": "HA"
},
{
- "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a local request",
+ "EventCode": "0x72",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL",
"UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_H_IMC_READS.NORMAL",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RspIFwd or RspIFwdWb for a remote request",
+ "EventCode": "0x72",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Retry Events",
- "Counter": "0,1,2,3",
- "EventCode": "0x1E",
- "EventName": "UNC_H_IMC_RETRY",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is RsSFwd or RspSFwdWb",
+ "EventCode": "0x72",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
"PerPkg": "1",
+ "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS",
+ "UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
- "EventCode": "0x1A",
- "EventName": "UNC_H_IMC_WRITES.FULL",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoE or WbMtoS",
+ "EventCode": "0x72",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
- "Counter": "0,1,2,3",
- "EventCode": "0x1A",
- "EventName": "UNC_H_IMC_WRITES.PARTIAL",
+ "BriefDescription": "Accumulates Number of PV bits set on HitMe Cache Hits; op is WbMtoI",
+ "EventCode": "0x72",
+ "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
"PerPkg": "1",
+ "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
- "Counter": "0,1,2,3",
- "EventCode": "0x1A",
- "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is AckCnfltWbI",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
"PerPkg": "1",
+ "PublicDescription": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI",
"UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
- "Counter": "0,1,2,3",
- "EventCode": "0x1A",
- "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; All Requests",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.ALL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "UNC_H_HITME_LOOKUP.ALL",
+ "UMask": "0xff",
"Unit": "HA"
},
{
- "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
- "Counter": "0,1,2,3",
- "EventCode": "0x1A",
- "EventName": "UNC_H_IMC_WRITES.ALL",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; Allocations",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.ALLOCS",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "UNC_H_HITME_LOOKUP.ALLOCS",
+ "UMask": "0x70",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Local Reads",
- "Counter": "0,1,2,3",
- "EventCode": "0x53",
- "EventName": "UNC_H_OSB.READS_LOCAL",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; HOM Requests",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.HOM",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "UNC_H_HITME_LOOKUP.HOM",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
- "Counter": "0,1,2,3",
- "EventCode": "0x53",
- "EventName": "UNC_H_OSB.INVITOE_LOCAL",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; Invalidations",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.INVALS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "UNC_H_HITME_LOOKUP.INVALS",
+ "UMask": "0x26",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Remote",
- "Counter": "0,1,2,3",
- "EventCode": "0x53",
- "EventName": "UNC_H_OSB.REMOTE",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Cancelled",
- "Counter": "0,1,2,3",
- "EventCode": "0x53",
- "EventName": "UNC_H_OSB.CANCELLED",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "UNC_H_HITME_LOOKUP.RSP",
+ "UMask": "0x80",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Reads Local - Useful",
- "Counter": "0,1,2,3",
- "EventCode": "0x53",
- "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a local request",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL",
"UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Snoop Broadcast; Remote - Useful",
- "Counter": "0,1,2,3",
- "EventCode": "0x53",
- "EventName": "UNC_H_OSB.REMOTE_USEFUL",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RspIFwd or RspIFwdWb for a remote request",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
+ "PerPkg": "1",
+ "PublicDescription": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE",
+ "UMask": "0x10",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RsSFwd or RspSFwdWb",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS",
"PerPkg": "1",
+ "PublicDescription": "UNC_H_HITME_LOOKUP.RSPFWDS",
"UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Early Data Return; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x54",
- "EventName": "UNC_H_OSB_EDR.ALL",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE or WbMtoS",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Early Data Return; Reads to Local I",
- "Counter": "0,1,2,3",
- "EventCode": "0x54",
- "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoI",
+ "EventCode": "0x70",
+ "EventName": "UNC_H_HITME_LOOKUP.WBMTOI",
"PerPkg": "1",
+ "PublicDescription": "UNC_H_HITME_LOOKUP.WBMTOI",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Early Data Return; Reads to Remote I",
- "Counter": "0,1,2,3",
- "EventCode": "0x54",
- "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
+ "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 0",
+ "EventCode": "0x22",
+ "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Early Data Return; Reads to Local S",
- "Counter": "0,1,2,3",
- "EventCode": "0x54",
- "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
+ "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI Link 1",
+ "EventCode": "0x22",
+ "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "OSB Early Data Return; Reads to Remote S",
- "Counter": "0,1,2,3",
- "EventCode": "0x54",
- "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
+ "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
+ "EventCode": "0x22",
+ "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
"UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Reads",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.READS",
+ "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 0",
+ "EventCode": "0x22",
+ "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Writes",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.WRITES",
+ "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
+ "EventCode": "0x22",
+ "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Local Reads",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.READS_LOCAL",
+ "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI Link 1",
+ "EventCode": "0x22",
+ "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links.",
+ "UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Remote Reads",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.READS_REMOTE",
+ "BriefDescription": "HA to iMC Normal Priority Reads Issued; Normal Priority",
+ "EventCode": "0x17",
+ "EventName": "UNC_H_IMC_READS.NORMAL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Local Writes",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
+ "BriefDescription": "Retry Events",
+ "EventCode": "0x1E",
+ "EventName": "UNC_H_IMC_RETRY",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "UNC_H_IMC_RETRY",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Remote Writes",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
+ "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes",
+ "EventCode": "0x1A",
+ "EventName": "UNC_H_IMC_WRITES.ALL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Local InvItoEs",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
+ "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
+ "EventCode": "0x1A",
+ "EventName": "UNC_H_IMC_WRITES.FULL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Read and Write Requests; Remote InvItoEs",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
+ "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full Line",
+ "EventCode": "0x1A",
+ "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x3E",
- "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
+ "BriefDescription": "HA to iMC Full Line Writes Issued; Partial Non-ISOCH",
+ "EventCode": "0x1A",
+ "EventName": "UNC_H_IMC_WRITES.PARTIAL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0x3E",
- "EventName": "UNC_H_RING_AD_USED.CW_ODD",
+ "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Partial",
+ "EventCode": "0x1A",
+ "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x3E",
- "EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
+ "BriefDescription": "IOT Backpressure",
+ "EventCode": "0x61",
+ "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "UNC_H_IOT_BACKPRESSURE.HUB",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0x3E",
- "EventName": "UNC_H_RING_AD_USED.CCW_ODD",
+ "BriefDescription": "IOT Backpressure",
+ "EventCode": "0x61",
+ "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "UNC_H_IOT_BACKPRESSURE.SAT",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA AD Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
- "EventCode": "0x3E",
- "EventName": "UNC_H_RING_AD_USED.CW",
+ "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+ "EventCode": "0x64",
+ "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
- "EventCode": "0x3E",
- "EventName": "UNC_H_RING_AD_USED.CCW",
+ "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+ "EventCode": "0x64",
+ "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x3F",
- "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
+ "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+ "EventCode": "0x65",
+ "EventName": "UNC_H_IOT_CTS_HI.CTS2",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0x3F",
- "EventName": "UNC_H_RING_AK_USED.CW_ODD",
+ "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+ "EventCode": "0x65",
+ "EventName": "UNC_H_IOT_CTS_HI.CTS3",
"PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x3F",
- "EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
+ "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+ "EventCode": "0x62",
+ "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0x3F",
- "EventName": "UNC_H_RING_AK_USED.CCW_ODD",
+ "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+ "EventCode": "0x62",
+ "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA AK Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
- "EventCode": "0x3F",
- "EventName": "UNC_H_RING_AK_USED.CW",
+ "BriefDescription": "OSB Snoop Broadcast; Cancelled",
+ "EventCode": "0x53",
+ "EventName": "UNC_H_OSB.CANCELLED",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.; OSB Snoop broadcast cancelled due to D2C or Other. OSB cancel is counted when OSB local read is not allowed even when the transaction in local InItoE. It also counts D2C OSB cancel, but also includes the cases were D2C was not set in the first place for the transaction coming from the ring.",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "HA AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
- "EventCode": "0x3F",
- "EventName": "UNC_H_RING_AK_USED.CCW",
+ "BriefDescription": "OSB Snoop Broadcast; Local InvItoE",
+ "EventCode": "0x53",
+ "EventName": "UNC_H_OSB.INVITOE_LOCAL",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
+ "BriefDescription": "OSB Snoop Broadcast; Local Reads",
+ "EventCode": "0x53",
+ "EventName": "UNC_H_OSB.READS_LOCAL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_H_RING_BL_USED.CW_ODD",
+ "BriefDescription": "OSB Snoop Broadcast; Reads Local - Useful",
+ "EventCode": "0x53",
+ "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
+ "BriefDescription": "OSB Snoop Broadcast; Remote",
+ "EventCode": "0x53",
+ "EventName": "UNC_H_OSB.REMOTE",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_H_RING_BL_USED.CCW_ODD",
+ "BriefDescription": "OSB Snoop Broadcast; Remote - Useful",
+ "EventCode": "0x53",
+ "EventName": "UNC_H_OSB.REMOTE_USEFUL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "HA BL Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_H_RING_BL_USED.CW",
+ "BriefDescription": "OSB Early Data Return; All",
+ "EventCode": "0x54",
+ "EventName": "UNC_H_OSB_EDR.ALL",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_H_RING_BL_USED.CCW",
+ "BriefDescription": "OSB Early Data Return; Reads to Local I",
+ "EventCode": "0x54",
+ "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
+ "BriefDescription": "OSB Early Data Return; Reads to Local S",
+ "EventCode": "0x54",
+ "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
+ "BriefDescription": "OSB Early Data Return; Reads to Remote I",
+ "EventCode": "0x54",
+ "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
+ "BriefDescription": "OSB Early Data Return; Reads to Remote S",
+ "EventCode": "0x54",
+ "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
+ "BriefDescription": "Read and Write Requests; Local InvItoEs",
+ "EventCode": "0x1",
+ "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket.",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x68",
- "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD",
+ "BriefDescription": "Read and Write Requests; Remote InvItoEs",
+ "EventCode": "0x1",
+ "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets.",
+ "UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x68",
- "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL",
+ "BriefDescription": "Read and Write Requests; Reads",
+ "EventCode": "0x1",
+ "EventName": "UNC_H_REQUESTS.READS",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests. This is a good proxy for LLC Read Misses (including RFOs).",
+ "UMask": "0x3",
"Unit": "HA"
},
{
- "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x6A",
- "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
+ "BriefDescription": "Read and Write Requests; Local Reads",
+ "EventCode": "0x1",
+ "EventName": "UNC_H_REQUESTS.READS_LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket. This is a good proxy for LLC Read Misses (including RFOs) from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x6A",
- "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
+ "BriefDescription": "Read and Write Requests; Remote Reads",
+ "EventCode": "0x1",
+ "EventName": "UNC_H_REQUESTS.READS_REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket. This is a good proxy for LLC Read Misses (including RFOs) from the remote socket.",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "SBo1 Credits Acquired; For AD Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x69",
- "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD",
+ "BriefDescription": "Read and Write Requests; Writes",
+ "EventCode": "0x1",
+ "EventName": "UNC_H_REQUESTS.WRITES",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests.",
+ "UMask": "0xc",
"Unit": "HA"
},
{
- "BriefDescription": "SBo1 Credits Acquired; For BL Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x69",
- "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL",
+ "BriefDescription": "Read and Write Requests; Local Writes",
+ "EventCode": "0x1",
+ "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x6B",
- "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
+ "BriefDescription": "Read and Write Requests; Remote Writes",
+ "EventCode": "0x1",
+ "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x6B",
- "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
+ "BriefDescription": "HA AD Ring in Use; Counterclockwise",
+ "EventCode": "0x3E",
+ "EventName": "UNC_H_RING_AD_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "HA"
},
{
- "BriefDescription": "Data beat the Snoop Responses; Local Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0xA",
- "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
+ "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even",
+ "EventCode": "0x3E",
+ "EventName": "UNC_H_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Data beat the Snoop Responses; Remote Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0xA",
- "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
+ "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd",
+ "EventCode": "0x3E",
+ "EventName": "UNC_H_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Cycles with Snoops Outstanding; Local Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x8",
- "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL",
+ "BriefDescription": "HA AD Ring in Use; Clockwise",
+ "EventCode": "0x3E",
+ "EventName": "UNC_H_RING_AD_USED.CW",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0x3",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "HA AD Ring in Use; Clockwise and Even",
+ "EventCode": "0x3E",
+ "EventName": "UNC_H_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Cycles with Snoops Outstanding; Remote Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x8",
- "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE",
+ "BriefDescription": "HA AD Ring in Use; Clockwise and Odd",
+ "EventCode": "0x3E",
+ "EventName": "UNC_H_RING_AD_USED.CW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x8",
- "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
+ "BriefDescription": "HA AK Ring in Use; All",
+ "EventCode": "0x3F",
+ "EventName": "UNC_H_RING_AK_USED.ALL",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x9",
- "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL",
+ "BriefDescription": "HA AK Ring in Use; Counterclockwise",
+ "EventCode": "0x3F",
+ "EventName": "UNC_H_RING_AK_USED.CCW",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x9",
- "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE",
+ "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even",
+ "EventCode": "0x3F",
+ "EventName": "UNC_H_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received; RspI",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSPI",
+ "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd",
+ "EventCode": "0x3F",
+ "EventName": "UNC_H_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Shared line response from remote cache",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSPS",
+ "BriefDescription": "HA AK Ring in Use; Clockwise",
+ "EventCode": "0x3F",
+ "EventName": "UNC_H_RING_AK_USED.CW",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0x3",
"Unit": "HA"
},
{
- "BriefDescription": "M line forwarded from remote cache with no writeback to memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+ "BriefDescription": "HA AK Ring in Use; Clockwise and Even",
+ "EventCode": "0x3F",
+ "EventName": "UNC_H_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Shared line forwarded from remote cache",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+ "BriefDescription": "HA AK Ring in Use; Clockwise and Odd",
+ "EventCode": "0x3F",
+ "EventName": "UNC_H_RING_AK_USED.CW_ODD",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received; Rsp*WB",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
+ "BriefDescription": "HA BL Ring in Use; All",
+ "EventCode": "0x40",
+ "EventName": "UNC_H_RING_BL_USED.ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xf",
"Unit": "HA"
},
{
- "BriefDescription": "M line forwarded from remote cache along with writeback to memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+ "BriefDescription": "HA BL Ring in Use; Counterclockwise",
+ "EventCode": "0x40",
+ "EventName": "UNC_H_RING_BL_USED.CCW",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+ "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even",
+ "EventCode": "0x40",
+ "EventName": "UNC_H_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspI",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
+ "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd",
+ "EventCode": "0x40",
+ "EventName": "UNC_H_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspS",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
+ "BriefDescription": "HA BL Ring in Use; Clockwise",
+ "EventCode": "0x40",
+ "EventName": "UNC_H_RING_BL_USED.CW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0x3",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspIFwd",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
+ "BriefDescription": "HA BL Ring in Use; Clockwise and Even",
+ "EventCode": "0x40",
+ "EventName": "UNC_H_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspSFwd",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
+ "BriefDescription": "HA BL Ring in Use; Clockwise and Odd",
+ "EventCode": "0x40",
+ "EventName": "UNC_H_RING_BL_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
+ "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0",
+ "EventCode": "0x15",
+ "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
+ "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1",
+ "EventCode": "0x15",
+ "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspCnflct",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
+ "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2",
+ "EventCode": "0x15",
+ "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Snoop Responses Received Local; Other",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
+ "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3",
+ "EventCode": "0x15",
+ "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x6C",
- "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
+ "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
+ "EventCode": "0x16",
+ "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x6C",
- "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
+ "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
+ "EventCode": "0x16",
+ "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x6C",
- "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
+ "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
+ "EventCode": "0x16",
+ "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
"UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x6C",
- "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
+ "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
+ "EventCode": "0x16",
+ "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and special requests such as ISOCH reads. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
"UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
+ "BriefDescription": "SBo0 Credits Acquired; For AD Ring",
+ "EventCode": "0x68",
+ "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
+ "BriefDescription": "SBo0 Credits Acquired; For BL Ring",
+ "EventCode": "0x68",
+ "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
+ "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
+ "EventCode": "0x6A",
+ "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
+ "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
+ "EventCode": "0x6A",
+ "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
+ "BriefDescription": "SBo1 Credits Acquired; For AD Ring",
+ "EventCode": "0x69",
+ "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
+ "BriefDescription": "SBo1 Credits Acquired; For BL Ring",
+ "EventCode": "0x69",
+ "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
+ "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
+ "EventCode": "0x6B",
+ "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
+ "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
+ "EventCode": "0x6B",
+ "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
+ "BriefDescription": "Data beat the Snoop Responses; Local Requests",
+ "EventCode": "0xA",
+ "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
+ "BriefDescription": "Data beat the Snoop Responses; Remote Requests",
+ "EventCode": "0xA",
+ "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of reads when the snoop was on the critical path to the data return.; This filter includes only requests coming from remote sockets.",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
+ "BriefDescription": "Cycles with Snoops Outstanding; All Requests",
+ "EventCode": "0x8",
+ "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts cycles when one or more snoops are outstanding.; Tracked for snoops from both local and remote sockets.",
+ "UMask": "0x3",
"Unit": "HA"
},
{
- "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
+ "BriefDescription": "Cycles with Snoops Outstanding; Local Requests",
+ "EventCode": "0x8",
+ "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from the local socket.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
+ "BriefDescription": "Cycles with Snoops Outstanding; Remote Requests",
+ "EventCode": "0x8",
+ "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles when one or more snoops are outstanding.; This filter includes only requests coming from remote sockets.",
+ "UMask": "0x2",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local Requests",
+ "EventCode": "0x9",
+ "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
+ "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remote Requests",
+ "EventCode": "0x9",
+ "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of either the local HA tracker pool that have snoops pending in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if an HT (HomeTracker) entry is available and this occupancy is decremented when all the snoop responses have returned.; This filter includes only requests coming from remote sockets.",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
+ "BriefDescription": "Snoop Responses Received; RSPCNFLCT*",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
+ "UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
+ "BriefDescription": "Snoop Responses Received; RspI",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_SNOOP_RESP.RSPI",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Cycles Not Empty; All Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
+ "BriefDescription": "M line forwarded from remote cache with no writeback to memory",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
+ "BriefDescription": "Shared line response from remote cache",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_SNOOP_RESP.RSPS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
+ "BriefDescription": "Shared line forwarded from remote cache",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currentl copy. This is common for data and code reads that hit in a remote socket in E or F state.",
+ "ScaleUnit": "64Bytes",
"UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
+ "BriefDescription": "M line forwarded from remote cache along with writeback to memory",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x20",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Snoop Responses Received; Rsp*WB",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
"UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
+ "BriefDescription": "Snoop Responses Received Local; Other",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for all other snoop responses.",
+ "UMask": "0x80",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
+ "BriefDescription": "Snoop Responses Received Local; RspCnflct",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT",
"PerPkg": "1",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
"UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
+ "BriefDescription": "Snoop Responses Received Local; RspI",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Data Pending Occupancy Accumultor; Local Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
+ "BriefDescription": "Snoop Responses Received Local; RspIFwd",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
+ "BriefDescription": "Snoop Responses Received Local; RspS",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS",
"PerPkg": "1",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AD Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
+ "BriefDescription": "Snoop Responses Received Local; RspSFwd",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currentl copy. This is common for data and code reads that hit in a remote socket in E or F state.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "AD Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
+ "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+ "UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "AD Egress Full; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
+ "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "AK Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
+ "EventCode": "0x6C",
+ "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "AK Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
+ "EventCode": "0x6C",
+ "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x4",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
+ "EventCode": "0x6C",
+ "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AK Egress Full; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
+ "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
+ "EventCode": "0x6C",
+ "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
- "Counter": "0,1,2,3",
- "EventCode": "0x10",
- "EventName": "UNC_H_TxR_BL.DRS_CACHE",
+ "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 0",
+ "EventCode": "0x1B",
+ "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
- "Counter": "0,1,2,3",
- "EventCode": "0x10",
- "EventName": "UNC_H_TxR_BL.DRS_CORE",
+ "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 1",
+ "EventCode": "0x1B",
+ "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
- "Counter": "0,1,2,3",
- "EventCode": "0x10",
- "EventName": "UNC_H_TxR_BL.DRS_QPI",
+ "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 2",
+ "EventCode": "0x1B",
+ "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2",
"UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "BL Egress Full; Scheduler 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x36",
- "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
+ "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 3",
+ "EventCode": "0x1B",
+ "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "BL Egress Full; Scheduler 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x36",
- "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
+ "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 4",
+ "EventCode": "0x1B",
+ "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "BL Egress Full; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x36",
- "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+ "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 5",
+ "EventCode": "0x1B",
+ "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5",
+ "UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "Injection Starvation; For AK Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x6D",
- "EventName": "UNC_H_TxR_STARVED.AK",
+ "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 6",
+ "EventCode": "0x1B",
+ "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6",
+ "UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "Injection Starvation; For BL Ring",
- "Counter": "0,1,2,3",
- "EventCode": "0x6D",
- "EventName": "UNC_H_TxR_STARVED.BL",
+ "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Region 7",
+ "EventCode": "0x1B",
+ "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7",
+ "UMask": "0x80",
"Unit": "HA"
},
{
- "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
+ "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 10",
+ "EventCode": "0x1C",
+ "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
+ "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 11",
+ "EventCode": "0x1C",
+ "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
+ "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 8",
+ "EventCode": "0x1C",
+ "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
+ "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Region 9",
+ "EventCode": "0x1C",
+ "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for Monroe systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD",
+ "BriefDescription": "Tracker Cycles Full; Cycles Completely Used",
+ "EventCode": "0x2",
+ "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the HA tracker pool (HT) is completely used including reserved HT entries. It will not return valid count when BT is disabled.",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD",
+ "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Used",
+ "EventCode": "0x2",
+ "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is completely used. This can be used with edge detect to identify the number of situations when the pool became fully utilized. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, the system could be starved for RTIDs but not fill up the HA trackers. HA trackers are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Counts the number of cycles when the general purpose (GP) HA tracker pool (HT) is completely used. It will not return valid count when BT is disabled.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD",
+ "BriefDescription": "Tracker Cycles Not Empty; All Requests",
+ "EventCode": "0x3",
+ "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; Requests coming from both local and remote sockets.",
+ "UMask": "0x3",
"Unit": "HA"
},
{
- "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD",
+ "BriefDescription": "Tracker Cycles Not Empty; Local Requests",
+ "EventCode": "0x3",
+ "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from the local socket.",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_H_IOT_BACKPRESSURE.SAT",
+ "BriefDescription": "Tracker Cycles Not Empty; Remote Requests",
+ "EventCode": "0x3",
+ "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles when the local HA tracker pool is not empty. This can be used with edge detect to identify the number of situations when the pool became empty. This should not be confused with RTID credit usage -- which must be tracked inside each cbo individually -- but represents the actual tracker buffer structure. In other words, this buffer could be completely empty, but there may still be credits in use by the CBos. This stat can be used in conjunction with the occupancy accumulation stat in order to calculate average queue occpancy. HA trackers are allocated as soon as a request enters the HA if an HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.; This filter includes only requests coming from remote sockets.",
+ "UMask": "0x2",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests",
+ "EventCode": "0x4",
+ "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+ "UMask": "0x40",
"Unit": "HA"
},
{
- "BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_H_IOT_BACKPRESSURE.HUB",
+ "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests",
+ "EventCode": "0x4",
+ "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+ "UMask": "0x80",
"Unit": "HA"
},
{
- "BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
- "EventCode": "0x64",
- "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0",
+ "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests",
+ "EventCode": "0x4",
+ "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
- "EventCode": "0x64",
- "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1",
+ "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests",
+ "EventCode": "0x4",
+ "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
- "BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
- "EventCode": "0x65",
- "EventName": "UNC_H_IOT_CTS_HI.CTS2",
+ "BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests",
+ "EventCode": "0x4",
+ "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+ "UMask": "0x10",
"Unit": "HA"
},
{
- "BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
- "EventCode": "0x65",
- "EventName": "UNC_H_IOT_CTS_HI.CTS3",
+ "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests",
+ "EventCode": "0x4",
+ "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Accumulates the occupancy of the local HA tracker pool in every cycle. This can be used in conjection with the not empty stat to calculate average queue occupancy or the allocations stat in order to calculate average queue latency. HA trackers are allocated as soon as a request enters the HA if a HT (Home Tracker) entry is available and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring.",
+ "UMask": "0x20",
"Unit": "HA"
},
{
- "BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
- "EventCode": "0x62",
- "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0",
+ "BriefDescription": "Data Pending Occupancy Accumultor; Local Requests",
+ "EventCode": "0x5",
+ "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from the local socket.",
"UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
- "EventCode": "0x62",
- "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1",
+ "BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests",
+ "EventCode": "0x5",
+ "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of transactions that have data from the memory controller until they get scheduled to the Egress. This can be used to calculate the queuing latency for two things. (1) If the system is waiting for snoops, this will increase. (2) If the system can't schedule to the Egress because of either (a) Egress Credits or (b) QPI BL IGR credits for remote requests.; This filter includes only requests coming from remote sockets.",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x16",
- "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+ "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
+ "EventCode": "0xF",
+ "EventName": "UNC_H_TxR_AD.HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of outbound transactions on the AD ring. This can be filtered by the NDR and SNP message classes. See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring. NDR stands for non-data response and is generally used for completions that do not include data. AD NDR is used for transactions to remote sockets.",
+ "UMask": "0x4",
"Unit": "HA"
},
{
- "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x16",
- "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+ "BriefDescription": "AD Egress Full; All",
+ "EventCode": "0x2A",
+ "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "AD Egress Full; Cycles full from both schedulers",
+ "UMask": "0x3",
"Unit": "HA"
},
{
- "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x16",
- "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+ "BriefDescription": "AD Egress Full; Scheduler 0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "AD Egress Full; Filter for cycles full from scheduler bank 0",
+ "UMask": "0x1",
"Unit": "HA"
},
{
- "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x16",
- "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
+ "BriefDescription": "AD Egress Full; Scheduler 1",
+ "EventCode": "0x2A",
+ "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "AD Egress Full; Filter for cycles full from scheduler bank 1",
+ "UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "Outbound NDR Ring Transactions; Non-data Responses",
- "Counter": "0,1,2,3",
- "EventCode": "0xF",
- "EventName": "UNC_H_TxR_AD.HOM",
+ "BriefDescription": "AD Egress Not Empty; All",
+ "EventCode": "0x29",
+ "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "AD Egress Not Empty; Cycles full from both schedulers",
+ "UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AD Egress Not Empty; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL",
+ "BriefDescription": "AD Egress Allocations; All",
+ "EventCode": "0x27",
+ "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Allocations; Allocations from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AD Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_H_TxR_AD_INSERTS.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AD Egress Allocations; Filter for allocations from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AD Egress Allocations; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_H_TxR_AD_INSERTS.ALL",
+ "BriefDescription": "AK Egress Full; All",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "AK Egress Full; Cycles full from both schedulers",
+ "UMask": "0x3",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "AK Egress Full; Scheduler 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0",
+ "PerPkg": "1",
+ "PublicDescription": "AK Egress Full; Filter for cycles full from scheduler bank 0",
+ "UMask": "0x1",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "AK Egress Full; Scheduler 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1",
+ "PerPkg": "1",
+ "PublicDescription": "AK Egress Full; Filter for cycles full from scheduler bank 1",
+ "UMask": "0x2",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "AK Egress Not Empty; All",
+ "EventCode": "0x31",
+ "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Not Empty; Cycles full from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AK Egress Not Empty; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x31",
- "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL",
+ "BriefDescription": "AK Egress Allocations; All",
+ "EventCode": "0x2F",
+ "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Allocations; Allocations from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "AK Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_H_TxR_AK_INSERTS.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "AK Egress Allocations; Filter for allocations from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "AK Egress Allocations; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x2F",
- "EventName": "UNC_H_TxR_AK_INSERTS.ALL",
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
+ "EventCode": "0x10",
+ "EventName": "UNC_H_TxR_BL.DRS_CACHE",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to the cache.",
+ "UMask": "0x1",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
+ "EventCode": "0x10",
+ "EventName": "UNC_H_TxR_BL.DRS_CORE",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent directly to the requesting core.",
+ "UMask": "0x2",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
+ "EventCode": "0x10",
+ "EventName": "UNC_H_TxR_BL.DRS_QPI",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI.",
+ "UMask": "0x4",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "BL Egress Full; All",
+ "EventCode": "0x36",
+ "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "BL Egress Full; Cycles full from both schedulers",
+ "UMask": "0x3",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "BL Egress Full; Scheduler 0",
+ "EventCode": "0x36",
+ "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0",
+ "PerPkg": "1",
+ "PublicDescription": "BL Egress Full; Filter for cycles full from scheduler bank 0",
+ "UMask": "0x1",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "BL Egress Full; Scheduler 1",
+ "EventCode": "0x36",
+ "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1",
+ "PerPkg": "1",
+ "PublicDescription": "BL Egress Full; Filter for cycles full from scheduler bank 1",
+ "UMask": "0x2",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "BL Egress Not Empty; All",
+ "EventCode": "0x35",
+ "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Not Empty; Cycles full from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Not Empty; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "BL Egress Not Empty; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL",
+ "BriefDescription": "BL Egress Allocations; All",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Allocations; Allocations from both schedulers",
"UMask": "0x3",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 0",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED0",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 0",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "BL Egress Allocations; Scheduler 1",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_H_TxR_BL_INSERTS.SCHED1",
"PerPkg": "1",
+ "PublicDescription": "BL Egress Allocations; Filter for allocations from scheduler bank 1",
"UMask": "0x2",
"Unit": "HA"
},
{
- "BriefDescription": "BL Egress Allocations; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_H_TxR_BL_INSERTS.ALL",
+ "BriefDescription": "Injection Starvation; For AK Ring",
+ "EventCode": "0x6D",
+ "EventName": "UNC_H_TxR_STARVED.AK",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "Injection Starvation; For BL Ring",
+ "EventCode": "0x6D",
+ "EventName": "UNC_H_TxR_STARVED.BL",
+ "PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 0",
+ "EventCode": "0x18",
+ "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
+ "UMask": "0x1",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 1",
+ "EventCode": "0x18",
+ "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
+ "UMask": "0x2",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 2",
+ "EventCode": "0x18",
+ "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
+ "UMask": "0x4",
+ "Unit": "HA"
+ },
+ {
+ "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Channel 3",
+ "EventCode": "0x18",
+ "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no regular credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
+ "UMask": "0x8",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 0",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only.",
"UMask": "0x1",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 1",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only.",
"UMask": "0x2",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 2",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only.",
"UMask": "0x4",
"Unit": "HA"
},
{
"BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Channel 3",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when there are no special credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and special requests such as ISOCH writes. This count only tracks the special credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only.",
"UMask": "0x8",
"Unit": "HA"
- },
- {
- "BriefDescription": "HA AK Ring in Use; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x3F",
- "EventName": "UNC_H_RING_AK_USED.ALL",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "HA"
- },
- {
- "BriefDescription": "HA BL Ring in Use; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_H_RING_BL_USED.ALL",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "HA"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json
index cb1916f52607..489a3673323d 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json
@@ -1,1452 +1,1331 @@
[
+ {
+ "BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data",
+ "EventName": "QPI_CTL_BANDWIDTH_TX",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.",
+ "ScaleUnit": "8Bytes",
+ "UMask": "0x4",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data",
+ "EventName": "QPI_DATA_BANDWIDTH_TX",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.",
+ "ScaleUnit": "8Bytes",
+ "UMask": "0x2",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "Number of qfclks",
- "Counter": "0,1,2,3",
"EventCode": "0x14",
"EventName": "UNC_Q_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of clocks in the QPI LL. This clock runs at 1/4th the GT/s speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. BDX does not support dynamic link speeds, so this frequency is fixed.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Count of CTO Events",
- "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_Q_CTO_COUNT",
- "ExtSel": "1",
"PerPkg": "1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
- "PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
"EventCode": "0x13",
- "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
+ "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits. The valid bit was set.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.",
"UMask": "0x8",
"Unit": "QPI LL"
},
+ {
+ "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
+ "EventCode": "0x13",
+ "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.",
+ "UMask": "0x80",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid",
"EventCode": "0x13",
- "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS",
+ "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core tranaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set.",
+ "UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid",
- "Counter": "0,1,2,3",
"EventCode": "0x13",
"EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.",
"UMask": "0x40",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Direct 2 Core Spawning; Spawn Success",
"EventCode": "0x13",
- "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS",
+ "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L1",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_Q_L1_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_Q_RxL0P_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_Q_RxL0_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Bypassed",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_Q_RxL_BYPASSED",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "CRC Errors Detected; LinkInit",
+ "EventCode": "0x3",
+ "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization.",
+ "UMask": "0x1",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
+ "EventCode": "0x3",
+ "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
+ "PerPkg": "1",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; DRS",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.",
"UMask": "0x1",
"Unit": "QPI LL"
},
+ {
+ "BriefDescription": "VN0 Credit Consumed; HOM",
+ "EventCode": "0x1E",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.",
+ "UMask": "0x8",
+ "Unit": "QPI LL"
+ },
{
"BriefDescription": "VN0 Credit Consumed; NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "VN0 Credit Consumed; HOM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VN0 Credit Consumed; NDR",
"EventCode": "0x1E",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN0 Credit Consumed; SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "VN0 Credit Consumed; NDR",
- "Counter": "0,1,2,3",
- "EventCode": "0x1E",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR",
- "ExtSel": "1",
+ "BriefDescription": "VN1 Credit Consumed; DRS",
+ "EventCode": "0x39",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "VN1 Credit Consumed; DRS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VN1 Credit Consumed; HOM",
"EventCode": "0x39",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.",
+ "UMask": "0x8",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; NCB",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; NCS",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "VN1 Credit Consumed; HOM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VN1 Credit Consumed; NDR",
"EventCode": "0x39",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM",
- "ExtSel": "1",
+ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
"BriefDescription": "VN1 Credit Consumed; SNP",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.",
"UMask": "0x10",
"Unit": "QPI LL"
},
- {
- "BriefDescription": "VN1 Credit Consumed; NDR",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "QPI LL"
- },
{
"BriefDescription": "VNA Credit Consumed",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Cycles Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_Q_RxL_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
+ "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0",
+ "EventCode": "0xF",
+ "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; SNP Flits",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
- "ExtSel": "1",
+ "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1",
+ "EventCode": "0xF",
+ "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
- "ExtSel": "1",
+ "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0",
+ "EventCode": "0x12",
+ "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
- "ExtSel": "1",
+ "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1",
+ "EventCode": "0x12",
+ "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; HOM Flits",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.HOM",
- "ExtSel": "1",
+ "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0",
+ "EventCode": "0x10",
+ "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
- "ExtSel": "1",
+ "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1",
+ "EventCode": "0x10",
+ "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
- "ExtSel": "1",
+ "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0",
+ "EventCode": "0x11",
+ "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
- "ExtSel": "1",
+ "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1",
+ "EventCode": "0x11",
+ "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1",
"PerPkg": "1",
- "UMask": "0x18",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
- "ExtSel": "1",
+ "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0",
+ "EventCode": "0x14",
+ "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
- "ExtSel": "1",
+ "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1",
+ "EventCode": "0x14",
+ "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
- "ExtSel": "1",
+ "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0",
+ "EventCode": "0x13",
+ "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
- "ExtSel": "1",
+ "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1",
+ "EventCode": "0x13",
+ "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
- "ExtSel": "1",
+ "BriefDescription": "Flits Received - Group 0; Idle and Null Flits",
+ "EventCode": "0x1",
+ "EventName": "UNC_Q_RxL_FLITS_G0.IDLE",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generall not considered part of the QPI bandwidth.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
- "ExtSel": "1",
+ "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)",
+ "EventCode": "0x2",
+ "EventName": "UNC_Q_RxL_FLITS_G1.DRS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data.",
+ "UMask": "0x18",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Rx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x8",
- "EventName": "UNC_Q_RxL_INSERTS",
+ "BriefDescription": "Flits Received - Group 1; DRS Data Flits",
+ "EventCode": "0x2",
+ "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).",
+ "UMask": "0x8",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9",
- "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0",
- "ExtSel": "1",
+ "BriefDescription": "Flits Received - Group 1; DRS Header Flits",
+ "EventCode": "0x2",
+ "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.",
+ "UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9",
- "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1",
- "ExtSel": "1",
+ "BriefDescription": "Flits Received - Group 1; HOM Flits",
+ "EventCode": "0x2",
+ "EventName": "UNC_Q_RxL_FLITS_G1.HOM",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.",
+ "UMask": "0x6",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0xC",
- "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0",
- "ExtSel": "1",
+ "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits",
+ "EventCode": "0x2",
+ "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.",
+ "UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1",
- "Counter": "0,1,2,3",
- "EventCode": "0xC",
- "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1",
- "ExtSel": "1",
+ "BriefDescription": "Flits Received - Group 1; HOM Request Flits",
+ "EventCode": "0x2",
+ "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0xA",
- "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0",
- "ExtSel": "1",
+ "BriefDescription": "Flits Received - Group 1; SNP Flits",
+ "EventCode": "0x2",
+ "EventName": "UNC_Q_RxL_FLITS_G1.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel.",
+ "UMask": "0x1",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits",
+ "EventCode": "0x3",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NCB",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.",
+ "UMask": "0xc",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits",
+ "EventCode": "0x3",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.",
+ "UMask": "0x4",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits",
+ "EventCode": "0x3",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.",
+ "UMask": "0x8",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits",
+ "EventCode": "0x3",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NCS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers.",
+ "UMask": "0x10",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD",
+ "EventCode": "0x3",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.",
+ "UMask": "0x1",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK",
+ "EventCode": "0x3",
+ "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.",
+ "UMask": "0x2",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Rx Flit Buffer Allocations",
+ "EventCode": "0x8",
+ "EventName": "UNC_Q_RxL_INSERTS",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0",
+ "EventCode": "0x9",
+ "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.",
+ "UMask": "0x1",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1",
+ "EventCode": "0x9",
+ "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.",
+ "UMask": "0x2",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0",
+ "EventCode": "0xC",
+ "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.",
+ "UMask": "0x1",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1",
+ "EventCode": "0xC",
+ "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.",
+ "UMask": "0x2",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0",
+ "EventCode": "0xA",
+ "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_Q_RxL_INSERTS_NCB.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_INSERTS_NCS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_INSERTS_NCS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_Q_RxL_INSERTS_NDR.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_Q_RxL_INSERTS_NDR.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_Q_RxL_INSERTS_SNP.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_Q_RxL_INSERTS_SNP.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - All Packets",
- "Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_Q_RxL_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x15",
"EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x18",
"EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x16",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x17",
"EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x1A",
"EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "RxQ Occupancy - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x19",
"EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Cycles in L0p",
- "Counter": "0,1,2,3",
- "EventCode": "0xD",
- "EventName": "UNC_Q_TxL0P_POWER_CYCLES",
+ "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM",
+ "EventCode": "0x35",
+ "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Cycles in L0",
- "Counter": "0,1,2,3",
- "EventCode": "0xC",
- "EventName": "UNC_Q_TxL0_POWER_CYCLES",
+ "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
+ "EventCode": "0x35",
+ "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
+ "PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x8",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP",
+ "EventCode": "0x35",
+ "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Tx Flit Buffer Bypassed",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_Q_TxL_BYPASSED",
+ "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR",
+ "EventCode": "0x35",
+ "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Tx Flit Buffer Cycles not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0x6",
- "EventName": "UNC_Q_TxL_CYCLES_NE",
+ "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
+ "EventCode": "0x35",
+ "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G0.DATA",
+ "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB",
+ "EventCode": "0x35",
+ "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data",
- "Counter": "0,1,2,3",
- "EventName": "QPI_DATA_BANDWIDTH_TX",
+ "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits",
+ "EventCode": "0x35",
+ "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
"PerPkg": "1",
- "ScaleUnit": "8Bytes",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits. For details on a message class granularity, use the Egress Credit Occupancy events.",
+ "UMask": "0x40",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Stalls Sending to R3QPI on VN0; GV",
+ "EventCode": "0x35",
+ "EventName": "UNC_Q_RxL_STALLS_VN0.GV",
+ "PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.",
+ "UMask": "0x80",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM",
+ "EventCode": "0x3A",
+ "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS",
+ "PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x1",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
+ "EventCode": "0x3A",
+ "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
+ "PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x8",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP",
+ "EventCode": "0x3A",
+ "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
+ "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR",
+ "EventCode": "0x3A",
+ "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data",
- "Counter": "0,1,2,3",
- "EventName": "QPI_CTL_BANDWIDTH_TX",
+ "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
+ "EventCode": "0x3A",
+ "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
"PerPkg": "1",
- "ScaleUnit": "8Bytes",
- "UMask": "0x4",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x20",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
- "ExtSel": "1",
+ "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB",
+ "EventCode": "0x3A",
+ "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP",
+ "PerPkg": "1",
+ "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.",
+ "UMask": "0x10",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Cycles in L0p",
+ "EventCode": "0xD",
+ "EventName": "UNC_Q_TxL0P_POWER_CYCLES",
+ "PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Cycles in L0",
+ "EventCode": "0xC",
+ "EventName": "UNC_Q_TxL0_POWER_CYCLES",
+ "PerPkg": "1",
+ "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Tx Flit Buffer Bypassed",
+ "EventCode": "0x5",
+ "EventName": "UNC_Q_TxL_BYPASSED",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
+ "EventCode": "0x2",
+ "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets.",
+ "UMask": "0x2",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
+ "EventCode": "0x2",
+ "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
- "ExtSel": "1",
+ "BriefDescription": "Tx Flit Buffer Cycles not Empty",
+ "EventCode": "0x6",
+ "EventName": "UNC_Q_TxL_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G0.DATA",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 1; HOM Flits",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.HOM",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
+ "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency.",
+ "UMask": "0x18",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Data Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).",
"UMask": "0x8",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 1; DRS Header Flits",
- "Counter": "0,1,2,3",
"EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.",
"UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)",
- "Counter": "0,1,2,3",
- "EventName": "UNC_Q_TxL_FLITS_G1.DRS",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; HOM Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.HOM",
"PerPkg": "1",
- "UMask": "0x18",
+ "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.",
+ "UMask": "0x6",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
- "ExtSel": "1",
+ "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.",
+ "UMask": "0x4",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.",
+ "UMask": "0x2",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Transferred - Group 1; SNP Flits",
+ "EventName": "UNC_Q_TxL_FLITS_G1.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
"EventCode": "0x1",
- "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
- "ExtSel": "1",
+ "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.",
+ "UMask": "0xc",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not te NCB headers.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
- "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
- "ExtSel": "1",
+ "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.",
+ "UMask": "0x8",
+ "Unit": "QPI LL"
+ },
+ {
+ "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
+ "EventCode": "0x1",
+ "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers.",
+ "UMask": "0x10",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD",
"EventCode": "0x1",
- "EventName": "UNC_Q_TxL_FLITS_G2.NCB",
- "ExtSel": "1",
+ "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.",
+ "UMask": "0x1",
"Unit": "QPI LL"
},
{
- "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK",
"EventCode": "0x1",
- "EventName": "UNC_Q_TxL_FLITS_G2.NCS",
- "ExtSel": "1",
+ "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.",
+ "UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_Q_TxL_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
"Unit": "QPI LL"
},
{
"BriefDescription": "Tx Flit Buffer Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_Q_TxL_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x26",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x27",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO fro Snoop messages on AD.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO fro Snoop messages on AD.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x29",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR",
- "Counter": "0,1,2,3",
"EventCode": "0x25",
"EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN",
- "Counter": "0,1,2,3",
"EventCode": "0x1F",
"EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.",
"UMask": "0x4",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x20",
"EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.",
"UMask": "0x1",
"Unit": "QPI LL"
},
{
"BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.",
"UMask": "0x2",
"Unit": "QPI LL"
},
{
"BriefDescription": "VNA Credits Returned",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_Q_VNA_CREDIT_RETURNS",
- "ExtSel": "1",
"PerPkg": "1",
+ "PublicDescription": "Number of VNA credits returned.",
"Unit": "QPI LL"
},
{
"BriefDescription": "VNA Credits Pending Return - Occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY",
- "ExtSel": "1",
- "PerPkg": "1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "CRC Errors Detected; LinkInit",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0xF",
- "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1",
- "Counter": "0,1,2,3",
- "EventCode": "0xF",
- "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x10",
- "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1",
- "Counter": "0,1,2,3",
- "EventCode": "0x10",
- "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN0; GV",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_Q_RxL_STALLS_VN0.GV",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM",
- "Counter": "0,1,2,3",
- "EventCode": "0x3A",
- "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP",
- "Counter": "0,1,2,3",
- "EventCode": "0x3A",
- "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR",
- "Counter": "0,1,2,3",
- "EventCode": "0x3A",
- "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS",
- "Counter": "0,1,2,3",
- "EventCode": "0x3A",
- "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB",
- "Counter": "0,1,2,3",
- "EventCode": "0x3A",
- "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS",
- "Counter": "0,1,2,3",
- "EventCode": "0x3A",
- "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR",
- "ExtSel": "1",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "QPI LL"
- },
- {
- "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
"Unit": "QPI LL"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json
index 05fab7d2723e..34dfc3cf22ef 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json
@@ -1,335 +1,344 @@
[
{
- "BriefDescription": "DRAM Activate Count; Activate due to Read",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_M_ACT_COUNT.RD",
+ "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
+ "EventCode": "0x4",
+ "EventName": "LLC_MISSES.MEM_READ",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Activate Count; Activate due to Write",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_M_ACT_COUNT.WR",
+ "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
+ "EventCode": "0x4",
+ "EventName": "LLC_MISSES.MEM_WRITE",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Activate Count; Activate due to Write",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.BYP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
"UMask": "0x8",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "DRAM Activate Count; Activate due to Read",
+ "EventCode": "0x1",
+ "EventName": "UNC_M_ACT_COUNT.RD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0x1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "DRAM Activate Count; Activate due to Write",
+ "EventCode": "0x1",
+ "EventName": "UNC_M_ACT_COUNT.WR",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0x2",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "ACT command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.ACT",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_BYP_CMDS.ACT",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "CAS command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.CAS",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_BYP_CMDS.CAS",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "PRE command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
"EventCode": "0xA1",
"EventName": "UNC_M_BYP_CMDS.PRE",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_BYP_CMDS.PRE",
"UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_REG",
+ "EventName": "UNC_M_CAS_COUNT.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel.",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+ "EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills).",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Reads (RD_CAS + Underfills)",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD_CAS (w/ and w/out auto-pre)",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD",
+ "EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. AutoPre is only used in systems that are using closed page policy. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
"EventCode": "0x4",
- "EventName": "LLC_MISSES.MEM_READ",
+ "EventName": "UNC_M_CAS_COUNT.RD_RMM",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill Read Issued",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR_WMM",
+ "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller. This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ. While it is possible for underfills to be issed in both WMM and RMM, this event counts both.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR_RMM",
+ "EventName": "UNC_M_CAS_COUNT.RD_WMM",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (both Modes)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel.",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
"EventCode": "0x4",
- "EventName": "LLC_MISSES.MEM_WRITE",
+ "EventName": "UNC_M_CAS_COUNT.WR_RMM",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0xC",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR_CAS (w/ and w/out auto-pre)",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.ALL",
+ "EventName": "UNC_M_CAS_COUNT.WR_WMM",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in WMM",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_WMM",
+ "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
+ "EventCode": "0xff",
+ "EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS issued in RMM",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_RMM",
+ "BriefDescription": "Clockticks in the Memory Controller using one of the programmable counters",
+ "EventName": "UNC_M_CLOCKTICKS_P",
"PerPkg": "1",
- "UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_M_CLOCKTICKS_P",
- "Counter": "0,1,2,3",
"EventName": "UNC_M_DCLOCKTICKS",
"PerPkg": "1",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge All Commands",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that the precharge all command was sent.",
"Unit": "iMC"
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
- "EventName": "UNC_M_DRAM_REFRESH.PANIC",
+ "EventName": "UNC_M_DRAM_REFRESH.HIGH",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of refreshes issued.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Number of DRAM Refreshes Issued",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
- "EventName": "UNC_M_DRAM_REFRESH.HIGH",
+ "EventName": "UNC_M_DRAM_REFRESH.PANIC",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of refreshes issued.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "ECC Correctable Errors",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.READ",
+ "EventName": "UNC_M_MAJOR_MODES.ISOCH",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time. These major modes are used whenever there is an ISOCH txn in the memory controller. In these mode, only ISOCH transactions are processed.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.WRITE",
+ "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads. Regular reads and writes are blocked and only underfill reads will be processed.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
+ "EventName": "UNC_M_MAJOR_MODES.READ",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
"EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.ISOCH",
+ "EventName": "UNC_M_MAJOR_MODES.WRITE",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads. This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Channel DLLOFF Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
"Unit": "iMC"
},
{
"BriefDescription": "Channel PPD Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x85",
"EventName": "UNC_M_POWER_CHANNEL_PPD",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Critical Throttle Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event.",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_POWER_PCU_THROTTLING",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M_POWER_PCU_THROTTLING",
"PerPkg": "1",
@@ -337,2569 +346,2554 @@
},
{
"BriefDescription": "Clock-Enabled Self-Refresh",
- "Counter": "0,1,2,3",
"EventCode": "0x43",
"EventName": "UNC_M_POWER_SELF_REFRESH",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Read Preemption Count; Read over Read Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read.",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Read Preemption Count; Read over Write Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write.",
"UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
"EventCode": "0x2",
- "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "EventName": "UNC_M_PRE_COUNT.BYP",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring. This does not include implicit precharge commands sent in auto-precharge mode.",
"UMask": "0x2",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "DRAM Precharge commands.; Precharges due to page miss",
+ "EventCode": "0x2",
+ "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses. This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include PRE commands sent as a result of the page close counter expiration.",
+ "UMask": "0x1",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to read",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.RD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to write",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_M_PRE_COUNT.BYP",
+ "BriefDescription": "Read CAS issued with HIGH priority",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "UNC_M_RD_CAS_PRIO.HIGH",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Read CAS issued with LOW priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.LOW",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_RD_CAS_PRIO.LOW",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Read CAS issued with MEDIUM priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.MED",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_RD_CAS_PRIO.MED",
"UMask": "0x2",
"Unit": "iMC"
},
- {
- "BriefDescription": "Read CAS issued with HIGH priority",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "iMC"
- },
{
"BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.PANIC",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_RD_CAS_PRIO.PANIC",
"UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.ALLBANKS",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK0",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
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+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
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- "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG0",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG2",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG3",
"UMask": "0x14",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M_RPQ_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "UNC_M_RPQ_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.",
"Unit": "iMC"
},
{
"BriefDescription": "VMSE MXB write buffer occupancy",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
"EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_VMSE_MXB_WR_OCCUPANCY",
"Unit": "iMC"
},
{
- "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
"EventCode": "0x90",
- "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
+ "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "UNC_M_VMSE_WR_PUSH.RMM",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in RMM",
- "Counter": "0,1,2,3",
+ "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued in WMM",
"EventCode": "0x90",
- "EventName": "UNC_M_VMSE_WR_PUSH.RMM",
+ "EventName": "UNC_M_VMSE_WR_PUSH.WMM",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "UNC_M_VMSE_WR_PUSH.WMM",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WMM_TO_RMM.LOW_THRESH",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.STARVE",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WMM_TO_RMM.STARVE",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M_WPQ_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"Unit": "iMC"
},
{
"BriefDescription": "Not getting the requested Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_M_WRONG_MM",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WRONG_MM",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+ "PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+ "UMask": "0x10",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+ "PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK0",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK1",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK1",
"UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK10",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
+ "PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK14",
+ "UMask": "0xe",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
+ "PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK15",
+ "UMask": "0xf",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK2",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK3",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK3",
"UMask": "0x3",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK4",
+ "PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK4",
+ "UMask": "0x4",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK5",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK5",
"UMask": "0x5",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK6",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK6",
"UMask": "0x6",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK7",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK7",
"UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK8",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK9",
"PerPkg": "1",
- "UMask": "0xA",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
- "Counter": "0,1,2,3",
- "EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
- "PerPkg": "1",
- "UMask": "0xB",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
- "Counter": "0,1,2,3",
- "EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
- "PerPkg": "1",
- "UMask": "0xC",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
- "Counter": "0,1,2,3",
- "EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
- "PerPkg": "1",
- "UMask": "0xD",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
- "Counter": "0,1,2,3",
- "EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
- "PerPkg": "1",
- "UMask": "0xE",
- "Unit": "iMC"
- },
- {
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- "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK11",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK12",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK13",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
"PerPkg": "1",
- "UMask": "0x5",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK14",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
"PerPkg": "1",
- "UMask": "0x6",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK15",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK2",
"PerPkg": "1",
- "UMask": "0x7",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK2",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK3",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK3",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK4",
"PerPkg": "1",
- "UMask": "0xA",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK4",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK5",
"PerPkg": "1",
- "UMask": "0xB",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK5",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK6",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK6",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK7",
"PerPkg": "1",
- "UMask": "0xD",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK7",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK8",
"PerPkg": "1",
- "UMask": "0xE",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK8",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK9",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK9",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG0",
"UMask": "0x11",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG1",
"UMask": "0x12",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG2",
"UMask": "0x13",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
"PerPkg": "1",
+ "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG3",
"UMask": "0x14",
"Unit": "iMC"
- },
- {
- "BriefDescription": "Clockticks in the Memory Controller using one of the programmable counters",
- "Counter": "0,1,2,3",
- "EventName": "UNC_M_CLOCKTICKS_P",
- "PerPkg": "1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
- "Counter": "FIXED",
- "EventCode": "0xff",
- "EventName": "UNC_M_CLOCKTICKS",
- "PerPkg": "1",
- "Unit": "iMC"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json
index 289a726c9ac3..a80d931dc3d5 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json
@@ -1,502 +1,508 @@
[
{
"BriefDescription": "Total Write Cache Occupancy; Any Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.",
"UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Total Write Cache Occupancy; Select Source",
- "Counter": "0,1",
"EventCode": "0x12",
"EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Clocks in the IRP",
- "Counter": "0,1",
"EventName": "UNC_I_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Number of clocks in the IRP.",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; PCIRdCur",
- "Counter": "0,1",
+ "BriefDescription": "Coherent Ops; CLFlush",
"EventCode": "0x13",
- "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+ "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x80",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; CRd",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.CRD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; DRd",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.DRD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; RFO",
- "Counter": "0,1",
+ "BriefDescription": "Coherent Ops; PCIDCAHin5t",
"EventCode": "0x13",
- "EventName": "UNC_I_COHERENT_OPS.RFO",
+ "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x20",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Coherent Ops; PCIRdCur",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; PCIItoM",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.PCITOM",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; PCIDCAHin5t",
- "Counter": "0,1",
+ "BriefDescription": "Coherent Ops; RFO",
"EventCode": "0x13",
- "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
+ "EventName": "UNC_I_COHERENT_OPS.RFO",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "Coherent Ops; WbMtoI",
- "Counter": "0,1",
"EventCode": "0x13",
"EventName": "UNC_I_COHERENT_OPS.WBMTOI",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
"UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "Coherent Ops; CLFlush",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
- "Counter": "0,1",
- "EventCode": "0x14",
- "EventName": "UNC_I_MISC0.FAST_REQ",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
"EventCode": "0x14",
- "EventName": "UNC_I_MISC0.FAST_REJ",
+ "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+ "UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_RD_INSERT",
"PerPkg": "1",
+ "PublicDescription": "UNC_I_MISC0.2ND_RD_INSERT",
"UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.2ND_WR_INSERT",
"PerPkg": "1",
+ "PublicDescription": "UNC_I_MISC0.2ND_WR_INSERT",
"UMask": "0x8",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
"EventCode": "0x14",
- "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+ "EventName": "UNC_I_MISC0.FAST_REJ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "UNC_I_MISC0.FAST_REJ",
+ "UMask": "0x2",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
+ "EventCode": "0x14",
+ "EventName": "UNC_I_MISC0.FAST_REQ",
+ "PerPkg": "1",
+ "PublicDescription": "UNC_I_MISC0.FAST_REQ",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.FAST_XFER",
"PerPkg": "1",
+ "PublicDescription": "UNC_I_MISC0.FAST_XFER",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.PF_ACK_HINT",
"PerPkg": "1",
+ "PublicDescription": "UNC_I_MISC0.PF_ACK_HINT",
"UMask": "0x40",
"Unit": "IRP"
},
{
"BriefDescription": "Misc Events - Set 0; Prefetch TimeOut",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_I_MISC0.PF_TIMEOUT",
"PerPkg": "1",
+ "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch. This happens in the case of a prefetch TimeOut",
"UMask": "0x80",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Data Throttled",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SLOW_I",
+ "EventName": "UNC_I_MISC1.DATA_THROTTLE",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "IRP throttled switch data",
+ "UMask": "0x80",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SLOW_S",
+ "EventName": "UNC_I_MISC1.LOST_FWD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "UNC_I_MISC1.LOST_FWD",
+ "UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Received Invalid",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SLOW_E",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x20",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Received Valid",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SLOW_M",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.LOST_FWD",
+ "EventName": "UNC_I_MISC1.SLOW_E",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Received Invalid",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+ "EventName": "UNC_I_MISC1.SLOW_I",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Received Valid",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+ "EventName": "UNC_I_MISC1.SLOW_M",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
- "BriefDescription": "Misc Events - Set 1; Data Throttled",
- "Counter": "0,1",
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
"EventCode": "0x15",
- "EventName": "UNC_I_MISC1.DATA_THROTTLE",
+ "EventName": "UNC_I_MISC1.SLOW_S",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x2",
"Unit": "IRP"
},
{
"BriefDescription": "AK Ingress Occupancy",
- "Counter": "0,1",
"EventCode": "0xA",
"EventName": "UNC_I_RxR_AK_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
- "Counter": "0,1",
"EventCode": "0x4",
"EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "BL Ingress Occupancy - DRS",
- "Counter": "0,1",
"EventCode": "0x1",
"EventName": "UNC_I_RxR_BL_DRS_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY",
- "Counter": "0,1",
"EventCode": "0x7",
"EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
- "Counter": "0,1",
"EventCode": "0x5",
"EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "BL Ingress Occupancy - NCB",
- "Counter": "0,1",
"EventCode": "0x2",
"EventName": "UNC_I_RxR_BL_NCB_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY",
- "Counter": "0,1",
"EventCode": "0x8",
"EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
- "Counter": "0,1",
"EventCode": "0x6",
"EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "BL Ingress Occupancy - NCS",
- "Counter": "0,1",
"EventCode": "0x3",
"EventName": "UNC_I_RxR_BL_NCS_INSERTS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
"BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY",
- "Counter": "0,1",
"EventCode": "0x9",
"EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.",
"Unit": "IRP"
},
{
- "BriefDescription": "Snoop Responses; Miss",
- "Counter": "0,1",
+ "BriefDescription": "Snoop Responses; Hit E or S",
"EventCode": "0x17",
- "EventName": "UNC_I_SNOOP_RESP.MISS",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "UNC_I_SNOOP_RESP.HIT_ES",
+ "UMask": "0x4",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; Hit I",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.HIT_I",
"PerPkg": "1",
+ "PublicDescription": "UNC_I_SNOOP_RESP.HIT_I",
"UMask": "0x2",
"Unit": "IRP"
},
{
- "BriefDescription": "Snoop Responses; Hit E or S",
- "Counter": "0,1",
+ "BriefDescription": "Snoop Responses; Hit M",
"EventCode": "0x17",
- "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_M",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "UNC_I_SNOOP_RESP.HIT_M",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
- "BriefDescription": "Snoop Responses; Hit M",
- "Counter": "0,1",
+ "BriefDescription": "Snoop Responses; Miss",
"EventCode": "0x17",
- "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+ "EventName": "UNC_I_SNOOP_RESP.MISS",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "UNC_I_SNOOP_RESP.MISS",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; SnpCode",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPCODE",
"PerPkg": "1",
+ "PublicDescription": "UNC_I_SNOOP_RESP.SNPCODE",
"UMask": "0x10",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; SnpData",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPDATA",
"PerPkg": "1",
+ "PublicDescription": "UNC_I_SNOOP_RESP.SNPDATA",
"UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Snoop Responses; SnpInv",
- "Counter": "0,1",
"EventCode": "0x17",
"EventName": "UNC_I_SNOOP_RESP.SNPINV",
"PerPkg": "1",
+ "PublicDescription": "UNC_I_SNOOP_RESP.SNPINV",
"UMask": "0x40",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Reads",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Atomic",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.READS",
+ "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions",
+ "UMask": "0x10",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Writes",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Other",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.WRITES",
+ "EventName": "UNC_I_TRANSACTIONS.OTHER",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.",
+ "UMask": "0x20",
"Unit": "IRP"
},
{
"BriefDescription": "Inbound Transaction Count; Read Prefetches",
- "Counter": "0,1",
"EventCode": "0x16",
"EventName": "UNC_I_TRANSACTIONS.RD_PREF",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.",
"UMask": "0x4",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Write Prefetches",
- "Counter": "0,1",
- "EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "IRP"
- },
- {
- "BriefDescription": "Inbound Transaction Count; Atomic",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Reads",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+ "EventName": "UNC_I_TRANSACTIONS.READS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).",
+ "UMask": "0x1",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Other",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Writes",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.OTHER",
+ "EventName": "UNC_I_TRANSACTIONS.WRITES",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests.",
+ "UMask": "0x2",
"Unit": "IRP"
},
{
- "BriefDescription": "Inbound Transaction Count; Select Source",
- "Counter": "0,1",
+ "BriefDescription": "Inbound Transaction Count; Write Prefetches",
"EventCode": "0x16",
- "EventName": "UNC_I_TRANSACTIONS.ORDERINGQ",
+ "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.",
+ "UMask": "0x8",
"Unit": "IRP"
},
{
"BriefDescription": "No AD Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x18",
"EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "No BL Egress Credit Stalls",
- "Counter": "0,1",
"EventCode": "0x19",
"EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xE",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
"EventCode": "0xF",
"EventName": "UNC_I_TxR_DATA_INSERTS_NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
"Unit": "IRP"
},
{
"BriefDescription": "Outbound Request Queue Occupancy",
- "Counter": "0,1",
"EventCode": "0xD",
"EventName": "UNC_I_TxR_REQUEST_OCCUPANCY",
"PerPkg": "1",
+ "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
"Unit": "IRP"
},
{
"BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_R2_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+ "Unit": "R2PCIe"
+ },
+ {
+ "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+ "EventCode": "0x2D",
+ "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "R2PCIe"
+ },
+ {
+ "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+ "EventCode": "0x2D",
+ "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+ "PerPkg": "1",
+ "UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0",
"PerPkg": "1",
@@ -505,7 +511,6 @@
},
{
"BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1",
"PerPkg": "1",
@@ -513,263 +518,326 @@
"Unit": "R2PCIe"
},
{
- "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
- "Counter": "0,1",
- "EventCode": "0x2D",
- "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0",
+ "BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
+ "EventCode": "0x33",
+ "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
+ "UMask": "0x8",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
- "Counter": "0,1",
- "EventCode": "0x2D",
- "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1",
+ "BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
+ "EventCode": "0x33",
+ "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
+ "UMask": "0x10",
+ "Unit": "R2PCIe"
+ },
+ {
+ "BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
+ "EventCode": "0x33",
+ "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
+ "UMask": "0x20",
+ "Unit": "R2PCIe"
+ },
+ {
+ "BriefDescription": "R2PCIe IIO Credits in Use; DRS",
+ "EventCode": "0x32",
+ "EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2PCIe IIO Credits in Use; NCB",
+ "EventCode": "0x32",
+ "EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.",
+ "UMask": "0x10",
+ "Unit": "R2PCIe"
+ },
+ {
+ "BriefDescription": "R2PCIe IIO Credits in Use; NCS",
+ "EventCode": "0x32",
+ "EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.",
+ "UMask": "0x20",
+ "Unit": "R2PCIe"
+ },
+ {
+ "BriefDescription": "R2 AD Ring in Use; All",
"EventCode": "0x7",
- "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
+ "EventName": "UNC_R2_RING_AD_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xf",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
"EventCode": "0x7",
- "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
+ "EventName": "UNC_R2_RING_AD_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AD Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_R2_RING_AD_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 AD Ring in Use; Clockwise and Even",
"EventCode": "0x7",
- "EventName": "UNC_R2_RING_AD_USED.CCW",
+ "EventName": "UNC_R2_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "AK Ingress Bounced; Up",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_R2_RING_AK_BOUNCES.UP",
+ "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd",
+ "EventCode": "0x7",
+ "EventName": "UNC_R2_RING_AD_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "R2PCIe"
},
{
"BriefDescription": "AK Ingress Bounced; Dn",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_R2_RING_AK_BOUNCES.DN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0x8",
- "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
+ "BriefDescription": "AK Ingress Bounced; Up",
+ "EventCode": "0x12",
+ "EventName": "UNC_R2_RING_AK_BOUNCES.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 AK Ring in Use; All",
"EventCode": "0x8",
- "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
+ "EventName": "UNC_R2_RING_AK_USED.ALL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xf",
+ "Unit": "R2PCIe"
+ },
+ {
+ "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
+ "EventCode": "0x8",
+ "EventName": "UNC_R2_RING_AK_USED.CCW",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 AK Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_R2_RING_AK_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 AK Ring in Use; Clockwise and Even",
"EventCode": "0x8",
- "EventName": "UNC_R2_RING_AK_USED.CCW",
+ "EventName": "UNC_R2_RING_AK_USED.CW_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
+ "Unit": "R2PCIe"
+ },
+ {
+ "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd",
+ "EventCode": "0x8",
+ "EventName": "UNC_R2_RING_AK_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 BL Ring in Use; All",
"EventCode": "0x9",
- "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
+ "EventName": "UNC_R2_RING_BL_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xf",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
"EventCode": "0x9",
- "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
+ "EventName": "UNC_R2_RING_BL_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 BL Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_R2_RING_BL_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 BL Ring in Use; Clockwise and Even",
"EventCode": "0x9",
- "EventName": "UNC_R2_RING_BL_USED.CCW",
+ "EventName": "UNC_R2_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 IV Ring in Use; Clockwise",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd",
+ "EventCode": "0x9",
+ "EventName": "UNC_R2_RING_BL_USED.CW_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
+ "Unit": "R2PCIe"
+ },
+ {
+ "BriefDescription": "R2 IV Ring in Use; Any",
"EventCode": "0xA",
- "EventName": "UNC_R2_RING_IV_USED.CW",
+ "EventName": "UNC_R2_RING_IV_USED.ANY",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0xf",
"Unit": "R2PCIe"
},
{
"BriefDescription": "R2 IV Ring in Use; Counterclockwise",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_R2_RING_IV_USED.CCW",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0xc",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2 IV Ring in Use; Any",
- "Counter": "0,1,2,3",
+ "BriefDescription": "R2 IV Ring in Use; Clockwise",
"EventCode": "0xA",
- "EventName": "UNC_R2_RING_IV_USED.ANY",
+ "EventName": "UNC_R2_RING_IV_USED.CW",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0x3",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCB",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Cycles Not Empty; NCS",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R2_RxR_CYCLES_NE.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Allocations; NCB",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R2_RxR_INSERTS.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R2PCIe"
},
@@ -778,60 +846,79 @@
"EventCode": "0x13",
"EventName": "UNC_R2_RxR_OCCUPANCY.DRS",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
"UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
- "Counter": "0,1",
- "EventCode": "0x2C",
- "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
+ "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
+ "EventCode": "0x2A",
+ "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
- "Counter": "0,1",
- "EventCode": "0x2C",
- "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
+ "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
+ "EventCode": "0x2A",
+ "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R2PCIe"
},
+ {
+ "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
+ "EventCode": "0x2C",
+ "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x1",
+ "Unit": "R2PCIe"
+ },
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x4",
"Unit": "R2PCIe"
},
+ {
+ "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
+ "EventCode": "0x2C",
+ "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x2",
+ "Unit": "R2PCIe"
+ },
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x8",
"Unit": "R2PCIe"
},
@@ -840,6 +927,7 @@
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.AD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue",
"UMask": "0x1",
"Unit": "R2PCIe"
},
@@ -848,6 +936,7 @@
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.AK",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue",
"UMask": "0x2",
"Unit": "R2PCIe"
},
@@ -856,6 +945,7 @@
"EventCode": "0x25",
"EventName": "UNC_R2_TxR_CYCLES_FULL.BL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue",
"UMask": "0x4",
"Unit": "R2PCIe"
},
@@ -864,6 +954,7 @@
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.AD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue",
"UMask": "0x1",
"Unit": "R2PCIe"
},
@@ -872,6 +963,7 @@
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.AK",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue",
"UMask": "0x2",
"Unit": "R2PCIe"
},
@@ -880,954 +972,925 @@
"EventCode": "0x23",
"EventName": "UNC_R2_TxR_CYCLES_NE.BL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress CCW NACK; AD CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_AD",
"PerPkg": "1",
+ "PublicDescription": "AD CounterClockwise Egress Queue",
"UMask": "0x1",
"Unit": "R2PCIe"
},
- {
- "BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
- "EventCode": "0x26",
- "EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "R2PCIe"
- },
{
"BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.DN_AK",
"PerPkg": "1",
+ "PublicDescription": "AK CounterClockwise Egress Queue",
"UMask": "0x4",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; BL CCW",
"EventCode": "0x26",
- "EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
+ "EventName": "UNC_R2_TxR_NACK_CW.DN_BL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "BL CounterClockwise Egress Queue",
+ "UMask": "0x2",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; AK CCW",
"EventCode": "0x26",
- "EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
+ "EventName": "UNC_R2_TxR_NACK_CW.UP_AD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "BL CounterClockwise Egress Queue",
+ "UMask": "0x8",
"Unit": "R2PCIe"
},
{
"BriefDescription": "Egress CCW NACK; BL CW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R2_TxR_NACK_CW.UP_AK",
"PerPkg": "1",
+ "PublicDescription": "AD Clockwise Egress Queue",
"UMask": "0x20",
"Unit": "R2PCIe"
},
{
- "BriefDescription": "R2PCIe IIO Credit Acquired; DRS",
- "Counter": "0,1",
- "EventCode": "0x33",
- "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "R2PCIe"
- },
- {
- "BriefDescription": "R2PCIe IIO Credit Acquired; NCB",
- "Counter": "0,1",
- "EventCode": "0x33",
- "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "R2PCIe"
- },
- {
- "BriefDescription": "R2PCIe IIO Credit Acquired; NCS",
- "Counter": "0,1",
- "EventCode": "0x33",
- "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "R2PCIe"
- },
- {
- "BriefDescription": "R2PCIe IIO Credits in Use; DRS",
- "Counter": "0,1",
- "EventCode": "0x32",
- "EventName": "UNC_R2_IIO_CREDITS_USED.DRS",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "R2PCIe"
- },
- {
- "BriefDescription": "R2PCIe IIO Credits in Use; NCB",
- "Counter": "0,1",
- "EventCode": "0x32",
- "EventName": "UNC_R2_IIO_CREDITS_USED.NCB",
+ "BriefDescription": "Egress CCW NACK; BL CCW",
+ "EventCode": "0x26",
+ "EventName": "UNC_R2_TxR_NACK_CW.UP_BL",
"PerPkg": "1",
+ "PublicDescription": "AD CounterClockwise Egress Queue",
"UMask": "0x10",
"Unit": "R2PCIe"
},
- {
- "BriefDescription": "R2PCIe IIO Credits in Use; NCS",
- "Counter": "0,1",
- "EventCode": "0x32",
- "EventName": "UNC_R2_IIO_CREDITS_USED.NCS",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "R2PCIe"
- },
- {
- "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
- "EventCode": "0x2A",
- "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "R2PCIe"
- },
- {
- "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
- "EventCode": "0x2A",
- "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "R2PCIe"
- },
- {
- "BriefDescription": "R2 AD Ring in Use; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x7",
- "EventName": "UNC_R2_RING_AD_USED.ALL",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "R2PCIe"
- },
- {
- "BriefDescription": "R2 AK Ring in Use; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x8",
- "EventName": "UNC_R2_RING_AK_USED.ALL",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "R2PCIe"
- },
- {
- "BriefDescription": "R2 BL Ring in Use; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x9",
- "EventName": "UNC_R2_RING_BL_USED.ALL",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "R2PCIe"
- },
{
"BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2",
"EventCode": "0x1",
"EventName": "UNC_R3_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13",
+ "UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16",
+ "UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
- "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16",
+ "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x1F",
"EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17",
"UMask": "0x80",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6",
"UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "CBox AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x22",
"EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7",
"UMask": "0x80",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA0",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA1",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "HA/R2 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2D",
"EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
- "EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
+ "BriefDescription": "IOT Backpressure",
+ "EventCode": "0xB",
+ "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "UNC_R3_IOT_BACKPRESSURE.HUB",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
- "EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
+ "BriefDescription": "IOT Backpressure",
+ "EventCode": "0xB",
+ "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "UNC_R3_IOT_BACKPRESSURE.SAT",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
- "EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
+ "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+ "EventCode": "0xD",
+ "EventName": "UNC_R3_IOT_CTS_HI.CTS2",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
- "EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
+ "BriefDescription": "IOT Common Trigger Sequencer - Hi",
+ "EventCode": "0xD",
+ "EventName": "UNC_R3_IOT_CTS_HI.CTS3",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
- "EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
+ "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+ "EventCode": "0xC",
+ "EventName": "UNC_R3_IOT_CTS_LO.CTS0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
+ "UMask": "0x1",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "IOT Common Trigger Sequencer - Lo",
+ "EventCode": "0xC",
+ "EventName": "UNC_R3_IOT_CTS_LO.CTS1",
+ "PerPkg": "1",
+ "PublicDescription": "Debug Mask/Match Tie-Ins",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
- "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages",
+ "UMask": "0x2",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "QPI0 AD Credits Empty",
+ "EventCode": "0x20",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR",
+ "PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages",
+ "UMask": "0x8",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "QPI0 AD Credits Empty",
+ "EventCode": "0x20",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP",
+ "PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages",
+ "UMask": "0x4",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "QPI0 AD Credits Empty",
+ "EventCode": "0x20",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM",
+ "PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x20",
"EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages",
"UMask": "0x40",
"Unit": "R3QPI"
},
{
- "BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
- "EventCode": "0x21",
- "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
+ "BriefDescription": "QPI0 AD Credits Empty",
+ "EventCode": "0x20",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP",
+ "PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages",
+ "UMask": "0x20",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "QPI0 AD Credits Empty",
+ "EventCode": "0x20",
+ "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VNA",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x21",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
+ "EventCode": "0x21",
+ "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
+ "PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages",
+ "UMask": "0x40",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "QPI0 BL Credits Empty",
"EventCode": "0x21",
"EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI0 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x21",
- "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR",
+ "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VNA",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2E",
- "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
+ "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2E",
- "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM",
+ "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages",
+ "UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2E",
"EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 AD Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2E",
- "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR",
+ "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VNA",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages",
+ "UMask": "0x40",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
"EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
"BriefDescription": "QPI1 BL Credits Empty",
- "Counter": "0,1",
"EventCode": "0x2F",
- "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR",
+ "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VNA",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AD Ring in Use; All",
"EventCode": "0x7",
- "EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
+ "EventName": "UNC_R3_RING_AD_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xf",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AD Ring in Use; Counterclockwise",
"EventCode": "0x7",
- "EventName": "UNC_R3_RING_AD_USED.CW_ODD",
+ "EventName": "UNC_R3_RING_AD_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AD Ring in Use; Clockwise",
- "Counter": "0,1,2",
"EventCode": "0x7",
"EventName": "UNC_R3_RING_AD_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AD Ring in Use; Counterclockwise",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AD Ring in Use; Clockwise and Even",
"EventCode": "0x7",
- "EventName": "UNC_R3_RING_AD_USED.CCW",
+ "EventName": "UNC_R3_RING_AD_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd",
+ "EventCode": "0x7",
+ "EventName": "UNC_R3_RING_AD_USED.CW_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "R3 AK Ring in Use; All",
"EventCode": "0x8",
- "EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
+ "EventName": "UNC_R3_RING_AK_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xf",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AK Ring in Use; Counterclockwise",
"EventCode": "0x8",
- "EventName": "UNC_R3_RING_AK_USED.CW_ODD",
+ "EventName": "UNC_R3_RING_AK_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 AK Ring in Use; Clockwise",
- "Counter": "0,1,2",
"EventCode": "0x8",
"EventName": "UNC_R3_RING_AK_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 AK Ring in Use; Counterclockwise",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AK Ring in Use; Clockwise and Even",
"EventCode": "0x8",
- "EventName": "UNC_R3_RING_AK_USED.CCW",
+ "EventName": "UNC_R3_RING_AK_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd",
+ "EventCode": "0x8",
+ "EventName": "UNC_R3_RING_AK_USED.CW_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "R3 BL Ring in Use; All",
"EventCode": "0x9",
- "EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
+ "EventName": "UNC_R3_RING_BL_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xf",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 BL Ring in Use; Counterclockwise",
"EventCode": "0x9",
- "EventName": "UNC_R3_RING_BL_USED.CW_ODD",
+ "EventName": "UNC_R3_RING_BL_USED.CCW",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
+ "UMask": "0xc",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CCW_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 BL Ring in Use; Clockwise",
- "Counter": "0,1,2",
"EventCode": "0x9",
"EventName": "UNC_R3_RING_BL_USED.CW",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.",
"UMask": "0x3",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 BL Ring in Use; Counterclockwise",
- "Counter": "0,1,2",
+ "BriefDescription": "R3 BL Ring in Use; Clockwise and Even",
"EventCode": "0x9",
- "EventName": "UNC_R3_RING_BL_USED.CCW",
+ "EventName": "UNC_R3_RING_BL_USED.CW_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "R3 IV Ring in Use; Clockwise",
- "Counter": "0,1,2",
- "EventCode": "0xA",
- "EventName": "UNC_R3_RING_IV_USED.CW",
+ "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd",
+ "EventCode": "0x9",
+ "EventName": "UNC_R3_RING_BL_USED.CW_ODD",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "R3 IV Ring in Use; Any",
- "Counter": "0,1,2",
"EventCode": "0xA",
"EventName": "UNC_R3_RING_IV_USED.ANY",
"PerPkg": "1",
- "UMask": "0xF",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0xf",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "R3 IV Ring in Use; Clockwise",
+ "EventCode": "0xA",
+ "EventName": "UNC_R3_RING_IV_USED.CW",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.",
+ "UMask": "0x3",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ring Stop Starved; AK",
- "Counter": "0,1,2",
"EventCode": "0xE",
"EventName": "UNC_R3_RING_SINK_STARVED.AK",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the ringstop is in starvation (per ring)",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Cycles Not Empty; HOM",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.HOM",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
"UMask": "0x1",
"Unit": "R3QPI"
},
- {
- "BriefDescription": "Ingress Cycles Not Empty; SNP",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "R3QPI"
- },
{
"BriefDescription": "Ingress Cycles Not Empty; NDR",
- "Counter": "0,1",
"EventCode": "0x10",
"EventName": "UNC_R3_RxR_CYCLES_NE.NDR",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Cycles Not Empty; HOM",
- "Counter": "0,1",
- "EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP",
- "Counter": "0,1",
- "EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP",
+ "BriefDescription": "Ingress Cycles Not Empty; SNP",
+ "EventCode": "0x10",
+ "EventName": "UNC_R3_RxR_CYCLES_NE.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS",
"EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; HOM",
"EventCode": "0x14",
- "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Cycles Not Empty; NCB",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Cycles Not Empty; NCS",
- "Counter": "0,1",
"EventCode": "0x14",
"EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Ingress Allocations; HOM",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_R3_RxR_INSERTS.HOM",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR",
+ "EventCode": "0x14",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Ingress Allocations; SNP",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_R3_RxR_INSERTS.SNP",
+ "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP",
+ "EventCode": "0x14",
+ "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Ingress Allocations; NDR",
- "Counter": "0,1",
+ "BriefDescription": "Ingress Allocations; DRS",
"EventCode": "0x11",
- "EventName": "UNC_R3_RxR_INSERTS.NDR",
+ "EventName": "UNC_R3_RxR_INSERTS.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Ingress Allocations; DRS",
- "Counter": "0,1",
+ "BriefDescription": "Ingress Allocations; HOM",
"EventCode": "0x11",
- "EventName": "UNC_R3_RxR_INSERTS.DRS",
+ "EventName": "UNC_R3_RxR_INSERTS.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Allocations; NCB",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x11",
"EventName": "UNC_R3_RxR_INSERTS.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Allocations; HOM",
- "Counter": "0,1",
- "EventCode": "0x15",
- "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM",
+ "BriefDescription": "Ingress Allocations; NDR",
+ "EventCode": "0x11",
+ "EventName": "UNC_R3_RxR_INSERTS.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Allocations; SNP",
- "Counter": "0,1",
- "EventCode": "0x15",
- "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP",
+ "BriefDescription": "Ingress Allocations; SNP",
+ "EventCode": "0x11",
+ "EventName": "UNC_R3_RxR_INSERTS.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
"UMask": "0x2",
"Unit": "R3QPI"
},
- {
- "BriefDescription": "VN1 Ingress Allocations; NDR",
- "Counter": "0,1",
- "EventCode": "0x15",
- "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "R3QPI"
- },
{
"BriefDescription": "VN1 Ingress Allocations; DRS",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_R3_RxR_INSERTS_VN1.DRS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Allocations; NCB",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Ingress Allocations; HOM",
"EventCode": "0x15",
- "EventName": "UNC_R3_RxR_INSERTS_VN1.NCB",
+ "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue",
+ "UMask": "0x1",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "VN1 Ingress Allocations; NCB",
+ "EventCode": "0x15",
+ "EventName": "UNC_R3_RxR_INSERTS_VN1.NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Ingress Allocations; NCS",
- "Counter": "0,1",
"EventCode": "0x15",
"EventName": "UNC_R3_RxR_INSERTS_VN1.NCS",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM",
- "EventCode": "0x13",
- "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM",
+ "BriefDescription": "VN1 Ingress Allocations; NDR",
+ "EventCode": "0x15",
+ "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP",
- "EventCode": "0x13",
- "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP",
+ "BriefDescription": "VN1 Ingress Allocations; SNP",
+ "EventCode": "0x15",
+ "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR",
+ "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS",
"EventCode": "0x13",
- "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR",
+ "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS",
+ "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM",
"EventCode": "0x13",
- "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS",
+ "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
@@ -1835,6 +1898,7 @@
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue",
"UMask": "0x10",
"Unit": "R3QPI"
},
@@ -1843,1410 +1907,1344 @@
"EventCode": "0x13",
"EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS",
"PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue",
"UMask": "0x20",
"Unit": "R3QPI"
},
+ {
+ "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR",
+ "EventCode": "0x13",
+ "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue",
+ "UMask": "0x4",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP",
+ "EventCode": "0x13",
+ "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue",
+ "UMask": "0x2",
+ "Unit": "R3QPI"
+ },
{
"BriefDescription": "SBo0 Credits Acquired; For AD Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo0 Credits Acquired; For BL Ring",
- "Counter": "0,1",
"EventCode": "0x28",
"EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.",
+ "UMask": "0x2",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
+ "EventCode": "0x2A",
+ "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
+ "UMask": "0x1",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
+ "EventCode": "0x2A",
+ "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL",
+ "PerPkg": "1",
+ "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo1 Credits Acquired; For AD Ring",
- "Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "SBo1 Credits Acquired; For BL Ring",
- "Counter": "0,1",
"EventCode": "0x29",
"EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
- "Counter": "0,1",
- "EventCode": "0x2C",
- "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD",
+ "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
+ "EventCode": "0x2B",
+ "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
- "Counter": "0,1",
- "EventCode": "0x2C",
- "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
+ "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
+ "EventCode": "0x2B",
+ "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.",
"UMask": "0x2",
"Unit": "R3QPI"
},
+ {
+ "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring",
+ "EventCode": "0x2C",
+ "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x1",
+ "Unit": "R3QPI"
+ },
{
"BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x4",
"Unit": "R3QPI"
},
+ {
+ "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring",
+ "EventCode": "0x2C",
+ "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
+ "UMask": "0x2",
+ "Unit": "R3QPI"
+ },
{
"BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring",
- "Counter": "0,1",
"EventCode": "0x2C",
"EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.",
"UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "Egress CCW NACK; AD CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.DN_AD",
"PerPkg": "1",
+ "PublicDescription": "AD CounterClockwise Egress Queue",
"UMask": "0x1",
"Unit": "R3QPI"
},
- {
- "BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
- "EventCode": "0x26",
- "EventName": "UNC_R3_TxR_NACK.DN_BL",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "R3QPI"
- },
{
"BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.DN_AK",
"PerPkg": "1",
+ "PublicDescription": "AK CounterClockwise Egress Queue",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Egress CCW NACK; AK CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; BL CCW",
"EventCode": "0x26",
- "EventName": "UNC_R3_TxR_NACK.UP_AD",
+ "EventName": "UNC_R3_TxR_NACK.DN_BL",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "BL CounterClockwise Egress Queue",
+ "UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "Egress CCW NACK; BL CCW",
- "Counter": "0,1",
+ "BriefDescription": "Egress CCW NACK; AK CCW",
"EventCode": "0x26",
- "EventName": "UNC_R3_TxR_NACK.UP_BL",
+ "EventName": "UNC_R3_TxR_NACK.UP_AD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "BL CounterClockwise Egress Queue",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
"BriefDescription": "Egress CCW NACK; BL CW",
- "Counter": "0,1",
"EventCode": "0x26",
"EventName": "UNC_R3_TxR_NACK.UP_AK",
"PerPkg": "1",
+ "PublicDescription": "AD Clockwise Egress Queue",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
- "Counter": "0,1",
- "EventCode": "0x37",
- "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
- "Counter": "0,1",
- "EventCode": "0x37",
- "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
+ "BriefDescription": "Egress CCW NACK; BL CCW",
+ "EventCode": "0x26",
+ "EventName": "UNC_R3_TxR_NACK.UP_BL",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "AD CounterClockwise Egress Queue",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
"EventCode": "0x37",
- "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
+ "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class",
"EventCode": "0x37",
- "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS",
+ "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x37",
"EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Used; HOM Message Class",
- "Counter": "0,1",
- "EventCode": "0x36",
- "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
+ "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class",
+ "EventCode": "0x37",
+ "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Used; SNP Message Class",
- "Counter": "0,1",
- "EventCode": "0x36",
- "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
+ "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class",
+ "EventCode": "0x37",
+ "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Used; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN0 Credit Used; DRS Message Class",
"EventCode": "0x36",
- "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
+ "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN0 Credit Used; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN0 Credit Used; HOM Message Class",
"EventCode": "0x36",
- "EventName": "UNC_R3_VN0_CREDITS_USED.DRS",
+ "EventName": "UNC_R3_VN0_CREDITS_USED.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Used; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN0 Credit Used; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x36",
"EventName": "UNC_R3_VN0_CREDITS_USED.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
- "Counter": "0,1",
- "EventCode": "0x39",
- "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
+ "BriefDescription": "VN0 Credit Used; NDR Message Class",
+ "EventCode": "0x36",
+ "EventName": "UNC_R3_VN0_CREDITS_USED.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
- "Counter": "0,1",
- "EventCode": "0x39",
- "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
+ "BriefDescription": "VN0 Credit Used; SNP Message Class",
+ "EventCode": "0x36",
+ "EventName": "UNC_R3_VN0_CREDITS_USED.SNP",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
"EventCode": "0x39",
- "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
+ "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class",
"EventCode": "0x39",
- "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS",
+ "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x39",
"EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Used; HOM Message Class",
- "Counter": "0,1",
- "EventCode": "0x38",
- "EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
+ "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class",
+ "EventCode": "0x39",
+ "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Used; SNP Message Class",
- "Counter": "0,1",
- "EventCode": "0x38",
- "EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
+ "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class",
+ "EventCode": "0x39",
+ "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP",
"PerPkg": "1",
+ "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
"UMask": "0x2",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Used; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Credit Used; DRS Message Class",
"EventCode": "0x38",
- "EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
+ "EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VN1 Credit Used; DRS Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VN1 Credit Used; HOM Message Class",
"EventCode": "0x38",
- "EventName": "UNC_R3_VN1_CREDITS_USED.DRS",
+ "EventName": "UNC_R3_VN1_CREDITS_USED.HOM",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Used; NCB Message Class",
- "Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VN1 Credit Used; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x38",
"EventName": "UNC_R3_VN1_CREDITS_USED.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?",
"UMask": "0x20",
"Unit": "R3QPI"
},
+ {
+ "BriefDescription": "VN1 Credit Used; NDR Message Class",
+ "EventCode": "0x38",
+ "EventName": "UNC_R3_VN1_CREDITS_USED.NDR",
+ "PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "R3QPI"
+ },
+ {
+ "BriefDescription": "VN1 Credit Used; SNP Message Class",
+ "EventCode": "0x38",
+ "EventName": "UNC_R3_VN1_CREDITS_USED.SNP",
+ "PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
+ "UMask": "0x2",
+ "Unit": "R3QPI"
+ },
{
"BriefDescription": "VNA credit Acquisitions; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x1",
"Unit": "R3QPI"
},
{
"BriefDescription": "VNA credit Acquisitions; HOM Message Class",
- "Counter": "0,1",
"EventCode": "0x33",
"EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL",
"PerPkg": "1",
+ "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
"UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; HOM Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; DRS Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.",
+ "UMask": "0x8",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; SNP Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; HOM Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "R3QPI"
},
{
- "BriefDescription": "VNA Credit Reject; NDR Message Class",
- "Counter": "0,1",
+ "BriefDescription": "VNA Credit Reject; NCB Message Class",
"EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "VNA Credit Reject; DRS Message Class",
- "Counter": "0,1",
- "EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "VNA Credit Reject; NCB Message Class",
- "Counter": "0,1",
- "EventCode": "0x34",
- "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB",
- "PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x10",
"Unit": "R3QPI"
},
{
"BriefDescription": "VNA Credit Reject; NCS Message Class",
- "Counter": "0,1",
"EventCode": "0x34",
"EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).",
"UMask": "0x20",
"Unit": "R3QPI"
},
{
- "BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
- "EventCode": "0xB",
- "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "IOT Backpressure",
- "Counter": "0,1,2",
- "EventCode": "0xB",
- "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
- "EventCode": "0xD",
- "EventName": "UNC_R3_IOT_CTS_HI.CTS2",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "IOT Common Trigger Sequencer - Hi",
- "Counter": "0,1,2",
- "EventCode": "0xD",
- "EventName": "UNC_R3_IOT_CTS_HI.CTS3",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
- "EventCode": "0xC",
- "EventName": "UNC_R3_IOT_CTS_LO.CTS0",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "IOT Common Trigger Sequencer - Lo",
- "Counter": "0,1,2",
- "EventCode": "0xC",
- "EventName": "UNC_R3_IOT_CTS_LO.CTS1",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "SBo0 Credits Occupancy; For AD Ring",
- "EventCode": "0x2A",
- "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "SBo0 Credits Occupancy; For BL Ring",
- "EventCode": "0x2A",
- "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "SBo1 Credits Occupancy; For AD Ring",
- "EventCode": "0x2B",
- "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD",
+ "BriefDescription": "VNA Credit Reject; NDR Message Class",
+ "EventCode": "0x34",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "R3QPI"
},
{
- "BriefDescription": "SBo1 Credits Occupancy; For BL Ring",
- "EventCode": "0x2B",
- "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL",
+ "BriefDescription": "VNA Credit Reject; SNP Message Class",
+ "EventCode": "0x34",
+ "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP",
"PerPkg": "1",
+ "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.",
"UMask": "0x2",
"Unit": "R3QPI"
},
- {
- "BriefDescription": "R3 AD Ring in Use; All",
- "Counter": "0,1,2",
- "EventCode": "0x7",
- "EventName": "UNC_R3_RING_AD_USED.ALL",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "R3 AK Ring in Use; All",
- "Counter": "0,1,2",
- "EventCode": "0x8",
- "EventName": "UNC_R3_RING_AK_USED.ALL",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "R3QPI"
- },
- {
- "BriefDescription": "R3 BL Ring in Use; All",
- "Counter": "0,1,2",
- "EventCode": "0x9",
- "EventName": "UNC_R3_RING_BL_USED.ALL",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "R3QPI"
- },
{
"BriefDescription": "Bounce Control",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_S_BOUNCE_CONTROL",
"PerPkg": "1",
+ "PublicDescription": "UNC_S_BOUNCE_CONTROL",
"Unit": "SBO"
},
{
"BriefDescription": "Uncore Clocks",
- "Counter": "0,1,2,3",
"EventName": "UNC_S_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "UNC_S_CLOCKTICKS",
"Unit": "SBO"
},
{
"BriefDescription": "FaST wire asserted",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_S_FAST_ASSERTED",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
"Unit": "SBO"
},
{
- "BriefDescription": "AD Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; All",
"EventCode": "0x1B",
- "EventName": "UNC_S_RING_AD_USED.UP_EVEN",
+ "EventName": "UNC_S_RING_AD_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xf",
"Unit": "SBO"
},
{
- "BriefDescription": "AD Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; Down",
"EventCode": "0x1B",
- "EventName": "UNC_S_RING_AD_USED.UP_ODD",
+ "EventName": "UNC_S_RING_AD_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Down and Event",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "AD Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1B",
"EventName": "UNC_S_RING_AD_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "SBO"
},
{
- "BriefDescription": "AD Ring In Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; Up and Even",
"EventCode": "0x1B",
- "EventName": "UNC_S_RING_AD_USED.DOWN",
+ "EventName": "UNC_S_RING_AD_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "AK Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AD Ring In Use; Up and Odd",
+ "EventCode": "0x1B",
+ "EventName": "UNC_S_RING_AD_USED.UP_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
+ "Unit": "SBO"
+ },
+ {
+ "BriefDescription": "AK Ring In Use; All",
"EventCode": "0x1C",
- "EventName": "UNC_S_RING_AK_USED.UP_EVEN",
+ "EventName": "UNC_S_RING_AK_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xf",
"Unit": "SBO"
},
{
- "BriefDescription": "AK Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Down",
"EventCode": "0x1C",
- "EventName": "UNC_S_RING_AK_USED.UP_ODD",
+ "EventName": "UNC_S_RING_AK_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Event",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "AK Ring In Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1C",
"EventName": "UNC_S_RING_AK_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "SBO"
},
{
- "BriefDescription": "AK Ring In Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Up and Even",
"EventCode": "0x1C",
- "EventName": "UNC_S_RING_AK_USED.DOWN",
+ "EventName": "UNC_S_RING_AK_USED.UP_EVEN",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "BL Ring in Use; Up and Even",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AK Ring In Use; Up and Odd",
+ "EventCode": "0x1C",
+ "EventName": "UNC_S_RING_AK_USED.UP_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
+ "Unit": "SBO"
+ },
+ {
+ "BriefDescription": "BL Ring in Use; All",
"EventCode": "0x1D",
- "EventName": "UNC_S_RING_BL_USED.UP_EVEN",
+ "EventName": "UNC_S_RING_BL_USED.ALL",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xf",
"Unit": "SBO"
},
{
- "BriefDescription": "BL Ring in Use; Up and Odd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Down",
"EventCode": "0x1D",
- "EventName": "UNC_S_RING_BL_USED.UP_ODD",
+ "EventName": "UNC_S_RING_BL_USED.DOWN",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0xc",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Event",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_S_RING_BL_USED.DOWN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_S_RING_BL_USED.DOWN_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0x1D",
"EventName": "UNC_S_RING_BL_USED.UP",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x3",
"Unit": "SBO"
},
{
- "BriefDescription": "BL Ring in Use; Down",
- "Counter": "0,1,2,3",
+ "BriefDescription": "BL Ring in Use; Up and Even",
"EventCode": "0x1D",
- "EventName": "UNC_S_RING_BL_USED.DOWN",
+ "EventName": "UNC_S_RING_BL_USED.UP_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.",
+ "UMask": "0x1",
+ "Unit": "SBO"
+ },
+ {
+ "BriefDescription": "BL Ring in Use; Up and Odd",
+ "EventCode": "0x1D",
+ "EventName": "UNC_S_RING_BL_USED.UP_ODD",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Number of LLC responses that bounced on the Ring",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Number of LLC responses that bounced on the Ring.",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.AD_CACHE",
"PerPkg": "1",
+ "PublicDescription": "UNC_S_RING_BOUNCES.AD_CACHE",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.AK_CORE",
"PerPkg": "1",
+ "PublicDescription": "UNC_S_RING_BOUNCES.AK_CORE",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.BL_CORE",
"PerPkg": "1",
+ "PublicDescription": "UNC_S_RING_BOUNCES.BL_CORE",
"UMask": "0x4",
"Unit": "SBO"
},
{
- "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.",
"EventCode": "0x5",
"EventName": "UNC_S_RING_BOUNCES.IV_CORE",
"PerPkg": "1",
+ "PublicDescription": "UNC_S_RING_BOUNCES.IV_CORE",
"UMask": "0x8",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
- "EventName": "UNC_S_RING_IV_USED.UP",
+ "EventName": "UNC_S_RING_IV_USED.DN",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0xc",
"Unit": "SBO"
},
{
"BriefDescription": "BL Ring in Use; Any",
- "Counter": "0,1,2,3",
"EventCode": "0x1E",
- "EventName": "UNC_S_RING_IV_USED.DN",
+ "EventName": "UNC_S_RING_IV_USED.UP",
"PerPkg": "1",
- "UMask": "0xC",
+ "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity",
+ "UMask": "0x3",
"Unit": "SBO"
},
{
- "BriefDescription": "Bypass; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_S_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE",
+ "EventCode": "0x6",
+ "EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Bypass; AD - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_S_RxR_BYPASS.AD_BNC",
+ "BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE",
+ "EventCode": "0x6",
+ "EventName": "UNC_S_RING_SINK_STARVED.AK_CORE",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Bypass; BL - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_S_RxR_BYPASS.BL_CRD",
+ "BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE",
+ "EventCode": "0x6",
+ "EventName": "UNC_S_RING_SINK_STARVED.BL_CORE",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
- "BriefDescription": "Bypass; BL - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_S_RxR_BYPASS.BL_BNC",
+ "BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE",
+ "EventCode": "0x6",
+ "EventName": "UNC_S_RING_SINK_STARVED.IV_CORE",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Bypass; AK",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_S_RxR_BYPASS.AK",
+ "BriefDescription": "Injection Starvation; AD - Bounces",
+ "EventCode": "0x15",
+ "EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Bypass; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_S_RxR_BYPASS.IV",
+ "BriefDescription": "Injection Starvation; AD - Credits",
+ "EventCode": "0x15",
+ "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Allocations; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_S_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "Injection Starvation; BL - Bounces",
+ "EventCode": "0x15",
+ "EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.",
+ "UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Allocations; AD - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_S_RxR_INSERTS.AD_BNC",
+ "BriefDescription": "Injection Starvation; BL - Credits",
+ "EventCode": "0x15",
+ "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Allocations; BL - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_S_RxR_INSERTS.BL_CRD",
+ "BriefDescription": "Bypass; AD - Bounces",
+ "EventCode": "0x12",
+ "EventName": "UNC_S_RxR_BYPASS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Bypass the Sbo Ingress.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Allocations; BL - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_S_RxR_INSERTS.BL_BNC",
+ "BriefDescription": "Bypass; AD - Credits",
+ "EventCode": "0x12",
+ "EventName": "UNC_S_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Bypass the Sbo Ingress.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Allocations; AK",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_S_RxR_INSERTS.AK",
+ "BriefDescription": "Bypass; AK",
+ "EventCode": "0x12",
+ "EventName": "UNC_S_RxR_BYPASS.AK",
"PerPkg": "1",
+ "PublicDescription": "Bypass the Sbo Ingress.",
"UMask": "0x10",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Allocations; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_S_RxR_INSERTS.IV",
+ "BriefDescription": "Bypass; BL - Bounces",
+ "EventCode": "0x12",
+ "EventName": "UNC_S_RxR_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Bypass the Sbo Ingress.",
+ "UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Bypass; BL - Credits",
+ "EventCode": "0x12",
+ "EventName": "UNC_S_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Bypass the Sbo Ingress.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; AD - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC",
+ "BriefDescription": "Bypass; IV",
+ "EventCode": "0x12",
+ "EventName": "UNC_S_RxR_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Bypass the Sbo Ingress.",
+ "UMask": "0x20",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; BL - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Injection Starvation; AD - Bounces",
+ "EventCode": "0x14",
+ "EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; BL - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC",
+ "BriefDescription": "Injection Starvation; AD - Credits",
+ "EventCode": "0x14",
+ "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; AK",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.AK",
+ "BriefDescription": "Injection Starvation; AK",
+ "EventCode": "0x14",
+ "EventName": "UNC_S_RxR_CRD_STARVED.AK",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
"UMask": "0x10",
"Unit": "SBO"
},
{
- "BriefDescription": "Ingress Occupancy; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_S_RxR_OCCUPANCY.IV",
+ "BriefDescription": "Injection Starvation; BL - Bounces",
+ "EventCode": "0x14",
+ "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "UNC_S_TxR_ADS_USED.AD",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_S_TxR_ADS_USED.AD",
+ "BriefDescription": "Injection Starvation; BL - Credits",
+ "EventCode": "0x14",
+ "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
- "BriefDescription": "UNC_S_TxR_ADS_USED.AK",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_S_TxR_ADS_USED.AK",
+ "BriefDescription": "Injection Starvation; IVF Credit",
+ "EventCode": "0x14",
+ "EventName": "UNC_S_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x40",
"Unit": "SBO"
},
{
- "BriefDescription": "UNC_S_TxR_ADS_USED.BL",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_S_TxR_ADS_USED.BL",
+ "BriefDescription": "Injection Starvation; IV",
+ "EventCode": "0x14",
+ "EventName": "UNC_S_RxR_CRD_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.",
+ "UMask": "0x20",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.AD_CRD",
+ "BriefDescription": "Ingress Allocations; AD - Bounces",
+ "EventCode": "0x13",
+ "EventName": "UNC_S_RxR_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; AD - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.AD_BNC",
+ "BriefDescription": "Ingress Allocations; AD - Credits",
+ "EventCode": "0x13",
+ "EventName": "UNC_S_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; BL - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.BL_CRD",
+ "BriefDescription": "Ingress Allocations; AK",
+ "EventCode": "0x13",
+ "EventName": "UNC_S_RxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; BL - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.BL_BNC",
+ "BriefDescription": "Ingress Allocations; BL - Bounces",
+ "EventCode": "0x13",
+ "EventName": "UNC_S_RxR_INSERTS.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; AK",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.AK",
+ "BriefDescription": "Ingress Allocations; BL - Credits",
+ "EventCode": "0x13",
+ "EventName": "UNC_S_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Allocations; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_S_TxR_INSERTS.IV",
+ "BriefDescription": "Ingress Allocations; IV",
+ "EventCode": "0x13",
+ "EventName": "UNC_S_RxR_INSERTS.IV",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.",
"UMask": "0x20",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Ingress Occupancy; AD - Bounces",
+ "EventCode": "0x11",
+ "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; AD - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC",
+ "BriefDescription": "Ingress Occupancy; AD - Credits",
+ "EventCode": "0x11",
+ "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; BL - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Ingress Occupancy; AK",
+ "EventCode": "0x11",
+ "EventName": "UNC_S_RxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; BL - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC",
+ "BriefDescription": "Ingress Occupancy; BL - Bounces",
+ "EventCode": "0x11",
+ "EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; AK",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.AK",
+ "BriefDescription": "Ingress Occupancy; BL - Credits",
+ "EventCode": "0x11",
+ "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
- "BriefDescription": "Egress Occupancy; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_S_TxR_OCCUPANCY.IV",
+ "BriefDescription": "Ingress Occupancy; IV",
+ "EventCode": "0x11",
+ "EventName": "UNC_S_RxR_OCCUPANCY.IV",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.",
"UMask": "0x20",
"Unit": "SBO"
},
{
- "BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE",
- "Counter": "0,1,2,3",
- "EventCode": "0x6",
- "EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE",
+ "BriefDescription": "UNC_S_TxR_ADS_USED.AD",
+ "EventCode": "0x4",
+ "EventName": "UNC_S_TxR_ADS_USED.AD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE",
- "Counter": "0,1,2,3",
- "EventCode": "0x6",
- "EventName": "UNC_S_RING_SINK_STARVED.AK_CORE",
+ "BriefDescription": "UNC_S_TxR_ADS_USED.AK",
+ "EventCode": "0x4",
+ "EventName": "UNC_S_TxR_ADS_USED.AK",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE",
- "Counter": "0,1,2,3",
- "EventCode": "0x6",
- "EventName": "UNC_S_RING_SINK_STARVED.BL_CORE",
+ "BriefDescription": "UNC_S_TxR_ADS_USED.BL",
+ "EventCode": "0x4",
+ "EventName": "UNC_S_TxR_ADS_USED.BL",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "SBO"
},
{
- "BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE",
- "Counter": "0,1,2,3",
- "EventCode": "0x6",
- "EventName": "UNC_S_RING_SINK_STARVED.IV_CORE",
+ "BriefDescription": "Egress Allocations; AD - Bounces",
+ "EventCode": "0x2",
+ "EventName": "UNC_S_TxR_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
+ "UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD",
+ "BriefDescription": "Egress Allocations; AD - Credits",
+ "EventCode": "0x2",
+ "EventName": "UNC_S_TxR_INSERTS.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
"UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; AD - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC",
+ "BriefDescription": "Egress Allocations; AK",
+ "EventCode": "0x2",
+ "EventName": "UNC_S_TxR_INSERTS.AK",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; BL - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD",
+ "BriefDescription": "Egress Allocations; BL - Bounces",
+ "EventCode": "0x2",
+ "EventName": "UNC_S_TxR_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
+ "UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; BL - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC",
+ "BriefDescription": "Egress Allocations; BL - Credits",
+ "EventCode": "0x2",
+ "EventName": "UNC_S_TxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; AD - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD",
+ "BriefDescription": "Egress Allocations; IV",
+ "EventCode": "0x2",
+ "EventName": "UNC_S_TxR_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.",
+ "UMask": "0x20",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; AD - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC",
+ "BriefDescription": "Egress Occupancy; AD - Bounces",
+ "EventCode": "0x1",
+ "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
"UMask": "0x2",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; BL - Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD",
+ "BriefDescription": "Egress Occupancy; AD - Credits",
+ "EventCode": "0x1",
+ "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
+ "UMask": "0x1",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; BL - Bounces",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC",
+ "BriefDescription": "Egress Occupancy; AK",
+ "EventCode": "0x1",
+ "EventName": "UNC_S_TxR_OCCUPANCY.AK",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
+ "UMask": "0x10",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; AK",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.AK",
+ "BriefDescription": "Egress Occupancy; BL - Bounces",
+ "EventCode": "0x1",
+ "EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
+ "UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.IV",
+ "BriefDescription": "Egress Occupancy; BL - Credits",
+ "EventCode": "0x1",
+ "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
+ "UMask": "0x4",
"Unit": "SBO"
},
{
- "BriefDescription": "Injection Starvation; IVF Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_S_RxR_CRD_STARVED.IFV",
+ "BriefDescription": "Egress Occupancy; IV",
+ "EventCode": "0x1",
+ "EventName": "UNC_S_TxR_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.",
+ "UMask": "0x20",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto AD Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.AD",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x1",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto AK Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.AK",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x2",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto BL Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.BL",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x4",
"Unit": "SBO"
},
{
"BriefDescription": "Injection Starvation; Onto IV Ring",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_S_TxR_STARVED.IV",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.",
"UMask": "0x8",
"Unit": "SBO"
},
{
- "BriefDescription": "AD Ring In Use; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_S_RING_AD_USED.ALL",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "SBO"
- },
- {
- "BriefDescription": "AK Ring In Use; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_S_RING_AK_USED.ALL",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "SBO"
- },
- {
- "BriefDescription": "BL Ring in Use; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x1D",
- "EventName": "UNC_S_RING_BL_USED.ALL",
+ "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
+ "EventCode": "0xff",
+ "EventName": "UNC_U_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0xF",
- "Unit": "SBO"
+ "Unit": "UBOX"
},
{
"BriefDescription": "VLW Received",
- "Counter": "0,1",
"EventCode": "0x42",
"EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
+ "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
"UMask": "0x8",
"Unit": "UBOX"
},
{
- "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
- "Counter": "0,1",
- "EventCode": "0x45",
- "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UBOX"
- },
- {
- "BriefDescription": "RACU Request",
- "Counter": "0,1",
- "EventCode": "0x46",
- "EventName": "UNC_U_RACU_REQUESTS",
+ "BriefDescription": "Filter Match",
+ "EventCode": "0x41",
+ "EventName": "UNC_U_FILTER_MATCH.DISABLE",
"PerPkg": "1",
+ "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+ "UMask": "0x2",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.ENABLE",
"PerPkg": "1",
+ "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
"UMask": "0x1",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
- "EventName": "UNC_U_FILTER_MATCH.DISABLE",
+ "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
+ "UMask": "0x8",
"Unit": "UBOX"
},
{
"BriefDescription": "Filter Match",
- "Counter": "0,1",
"EventCode": "0x41",
"EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE",
"PerPkg": "1",
+ "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.",
"UMask": "0x4",
"Unit": "UBOX"
},
{
- "BriefDescription": "Filter Match",
- "Counter": "0,1",
- "EventCode": "0x41",
- "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE",
+ "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
+ "EventCode": "0x45",
+ "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "PHOLD cycles. Filter from source CoreID.",
+ "UMask": "0x1",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Monitor T0",
- "Counter": "0,1",
- "EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
+ "BriefDescription": "RACU Request",
+ "EventCode": "0x46",
+ "EventName": "UNC_U_RACU_REQUESTS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Number outstanding register requests within message channel tracker",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Monitor T1",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
+ "EventName": "UNC_U_U2C_EVENTS.CMC",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+ "UMask": "0x10",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; Livelock",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LIVELOCK",
"PerPkg": "1",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
"UMask": "0x4",
"Unit": "UBOX"
},
{
"BriefDescription": "Monitor Sent to T0; LTError",
- "Counter": "0,1",
"EventCode": "0x43",
"EventName": "UNC_U_U2C_EVENTS.LTERROR",
"PerPkg": "1",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
"UMask": "0x8",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Correctable Machine Check",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Monitor T0",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.CMC",
+ "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+ "UMask": "0x1",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Monitor T1",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.UMC",
+ "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core",
+ "UMask": "0x2",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Trap",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Other",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.TRAP",
+ "EventName": "UNC_U_U2C_EVENTS.OTHER",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI",
+ "UMask": "0x80",
"Unit": "UBOX"
},
{
- "BriefDescription": "Monitor Sent to T0; Other",
- "Counter": "0,1",
+ "BriefDescription": "Monitor Sent to T0; Trap",
"EventCode": "0x43",
- "EventName": "UNC_U_U2C_EVENTS.OTHER",
+ "EventName": "UNC_U_U2C_EVENTS.TRAP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+ "UMask": "0x40",
"Unit": "UBOX"
},
{
- "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
- "Counter": "FIXED",
- "EventCode": "0xff",
- "EventName": "UNC_U_CLOCKTICKS",
+ "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check",
+ "EventCode": "0x43",
+ "EventName": "UNC_U_U2C_EVENTS.UMC",
"PerPkg": "1",
+ "PublicDescription": "Events coming from Uncore can be sent to one or all cores",
+ "UMask": "0x20",
"Unit": "UBOX"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json
index 3ffb70ff573d..e682eedf644a 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json
@@ -1,457 +1,457 @@
[
{
"BriefDescription": "pclk Cycles",
- "Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6A",
"EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6B",
"EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6C",
"EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions. There is one event per core.",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS_CORE0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_P_DEMOTIONS_CORE1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_P_DEMOTIONS_CORE10",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3B",
"EventName": "UNC_P_DEMOTIONS_CORE11",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_P_DEMOTIONS_CORE12",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_P_DEMOTIONS_CORE13",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_P_DEMOTIONS_CORE14",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_P_DEMOTIONS_CORE15",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_P_DEMOTIONS_CORE16",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_P_DEMOTIONS_CORE17",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_P_DEMOTIONS_CORE2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_P_DEMOTIONS_CORE3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_P_DEMOTIONS_CORE4",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_P_DEMOTIONS_CORE5",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_P_DEMOTIONS_CORE6",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_P_DEMOTIONS_CORE7",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_P_DEMOTIONS_CORE8",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
- "Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_P_DEMOTIONS_CORE9",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times when a configurable cores had a C-state demotion",
"Unit": "PCU"
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
"Unit": "PCU"
},
{
"BriefDescription": "OS Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the OS is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU"
},
{
- "BriefDescription": "Number of cores in C-State; C0 and C1",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
+ "BriefDescription": "Package C State Residency - C0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
- "BriefDescription": "Number of cores in C-State; C3",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
+ "BriefDescription": "Package C State Residency - C1E",
+ "EventCode": "0x4E",
+ "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C1E. This event can be used in conjunction with edge detect to count C1E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
- "BriefDescription": "Number of cores in C-State; C6 and C7",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
+ "BriefDescription": "Package C State Residency - C2E",
+ "EventCode": "0x2B",
+ "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
- "BriefDescription": "External Prochot",
- "Counter": "0,1,2,3",
- "EventCode": "0xA",
- "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
+ "BriefDescription": "Package C State Residency - C3",
+ "EventCode": "0x2C",
+ "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
- "BriefDescription": "Internal Prochot",
- "Counter": "0,1,2,3",
- "EventCode": "0x9",
- "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
+ "BriefDescription": "Package C State Residency - C6",
+ "EventCode": "0x2D",
+ "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
- "BriefDescription": "Total Core C State Transition Cycles",
- "Counter": "0,1,2,3",
- "EventCode": "0x72",
- "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
+ "BriefDescription": "Package C7 State Residency",
+ "EventCode": "0x2E",
+ "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C7. This event can be used in conjunction with edge detect to count C7 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
- "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
- "Counter": "0,1,2,3",
- "EventCode": "0x79",
- "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
+ "BriefDescription": "Number of cores in C-State; C0 and C1",
+ "EventCode": "0x80",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
- "BriefDescription": "VR Hot",
- "Counter": "0,1,2,3",
- "EventCode": "0x42",
- "EventName": "UNC_P_VR_HOT_CYCLES",
+ "BriefDescription": "Number of cores in C-State; C3",
+ "EventCode": "0x80",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
- "BriefDescription": "Package C State Residency - C0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
+ "BriefDescription": "Number of cores in C-State; C6 and C7",
+ "EventCode": "0x80",
+ "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
- "BriefDescription": "Package C State Residency - C2E",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
+ "BriefDescription": "External Prochot",
+ "EventCode": "0xA",
+ "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
- "BriefDescription": "Package C State Residency - C3",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
+ "BriefDescription": "Internal Prochot",
+ "EventCode": "0x9",
+ "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
- "BriefDescription": "Package C State Residency - C6",
- "Counter": "0,1,2,3",
- "EventCode": "0x2D",
- "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
+ "BriefDescription": "Total Core C State Transition Cycles",
+ "EventCode": "0x72",
+ "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
- "BriefDescription": "Package C7 State Residency",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
+ "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
+ "EventCode": "0x79",
+ "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
"PerPkg": "1",
+ "PublicDescription": "Ring GV with same final and initial frequency",
"Unit": "PCU"
},
{
- "BriefDescription": "Package C State Residency - C1E",
- "Counter": "0,1,2,3",
- "EventCode": "0x4E",
- "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
+ "BriefDescription": "VR Hot",
+ "EventCode": "0x42",
+ "EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "UNC_P_VR_HOT_CYCLES",
"Unit": "PCU"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json
index 6a6de8790f25..93621e004d88 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
@@ -12,8 +10,6 @@
},
{
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000003",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
"SampleAfterValue": "2000003",
@@ -30,8 +24,6 @@
},
{
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
"SampleAfterValue": "2000003",
@@ -39,8 +31,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
@@ -49,8 +39,6 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
@@ -60,8 +48,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
@@ -71,8 +57,6 @@
},
{
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
@@ -93,8 +75,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
@@ -104,8 +84,6 @@
},
{
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@@ -113,8 +91,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003",
@@ -122,8 +98,6 @@
},
{
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003",
@@ -131,8 +105,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
@@ -141,8 +113,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
@@ -152,8 +122,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
@@ -163,8 +131,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
@@ -174,8 +140,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
@@ -185,8 +149,6 @@
},
{
"BriefDescription": "Cycle count for an Extended Page table walk.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
@@ -195,8 +157,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@@ -205,8 +165,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
@@ -216,8 +174,6 @@
},
{
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@@ -225,8 +181,6 @@
},
{
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003",
@@ -234,8 +188,6 @@
},
{
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003",
@@ -243,8 +195,6 @@
},
{
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
@@ -253,8 +203,6 @@
},
{
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
@@ -264,8 +212,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
@@ -275,8 +221,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
@@ -286,8 +230,6 @@
},
{
"BriefDescription": "Cycles when PMH is busy with page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_DURATION",
@@ -297,8 +239,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
@@ -307,8 +247,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
@@ -317,8 +255,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
@@ -327,8 +263,6 @@
},
{
"BriefDescription": "Number of DTLB page walker hits in Memory.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
@@ -337,8 +271,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
@@ -347,8 +279,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L2.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
@@ -357,8 +287,6 @@
},
{
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
@@ -367,8 +295,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
@@ -377,8 +303,6 @@
},
{
"BriefDescription": "STLB flush attempts",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
--
2.39.0.314.g84b9a713c41-goog
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH v1 08/32] perf vendor events intel: Refresh cascadelakex metrics and events
2022-12-15 6:49 [PATCH v1 06/32] perf vendor events intel: Refresh broadwellde metrics and events Ian Rogers
2022-12-15 6:49 ` [PATCH v1 07/32] perf vendor events intel: Refresh broadwellx " Ian Rogers
@ 2022-12-15 6:49 ` Ian Rogers
1 sibling, 0 replies; 3+ messages in thread
From: Ian Rogers @ 2022-12-15 6:49 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Adrian Hunter, Kan Liang, Xing Zhengjun, linux-perf-users,
linux-kernel
Cc: John Garry, Stephane Eranian, Perry Taylor, Caleb Biggers, Ian Rogers
Update the cascadelakex metrics and events using the new tooling from:
https://github.com/intel/perfmon
The metrics are unchanged but the formulas differ due to parentheses,
use of exponents and removal of redundant operations like "* 1". The
order of metrics varies as TMA metrics are first converted and then
removed if perfmon versions are found. The events are updated with
fixes to uncore events and improved descriptions. The formatting
changes increase consistency across the json files.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/cascadelakex/cache.json | 3644 --
.../arch/x86/cascadelakex/clx-metrics.json | 2217 +-
.../arch/x86/cascadelakex/floating-point.json | 24 -
.../arch/x86/cascadelakex/frontend.json | 109 -
.../arch/x86/cascadelakex/memory.json | 2194 --
.../arch/x86/cascadelakex/other.json | 490 -
.../arch/x86/cascadelakex/pipeline.json | 194 -
.../arch/x86/cascadelakex/uncore-memory.json | 3185 +-
.../arch/x86/cascadelakex/uncore-other.json | 29444 +++++++++-------
.../arch/x86/cascadelakex/uncore-power.json | 45 +-
.../arch/x86/cascadelakex/virtual-memory.json | 56 -
11 files changed, 18897 insertions(+), 22705 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json
index 716c1b507496..1070ad317ec9 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "L1D data line replacements",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
"PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "L1D miss outstandings duration in cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
@@ -43,8 +35,6 @@
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
@@ -53,8 +43,6 @@
},
{
"BriefDescription": "L2 cache lines filling L2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
@@ -63,8 +51,6 @@
},
{
"BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.NON_SILENT",
"PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines can be either in modified state or clean state. Modified lines may either be written back to L3 or directly written to memory and not allocated in L3. Clean lines may either be allocated in L3 or dropped.",
@@ -73,8 +59,6 @@
},
{
"BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared state. A non-threaded event.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.SILENT",
"SampleAfterValue": "200003",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.USELESS_HWPF",
"SampleAfterValue": "200003",
@@ -91,8 +73,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Deprecated": "1",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.USELESS_PREF",
@@ -101,8 +81,6 @@
},
{
"BriefDescription": "L2 code requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_CODE_RD",
"PublicDescription": "Counts the total number of L2 code requests.",
@@ -111,8 +89,6 @@
},
{
"BriefDescription": "Demand Data Read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
@@ -121,8 +97,6 @@
},
{
"BriefDescription": "Demand requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"PublicDescription": "Demand requests that miss L2 cache.",
@@ -131,8 +105,6 @@
},
{
"BriefDescription": "Demand requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"PublicDescription": "Demand requests to L2 cache.",
@@ -141,8 +113,6 @@
},
{
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.",
@@ -151,8 +121,6 @@
},
{
"BriefDescription": "RFO requests to L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
@@ -161,8 +129,6 @@
},
{
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_HIT",
"PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
@@ -171,8 +137,6 @@
},
{
"BriefDescription": "L2 cache misses when fetching instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS",
"PublicDescription": "Counts L2 cache misses when fetching instructions.",
@@ -181,8 +145,6 @@
},
{
"BriefDescription": "Demand Data Read requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
@@ -191,8 +153,6 @@
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
@@ -201,8 +161,6 @@
},
{
"BriefDescription": "All requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS",
"PublicDescription": "All requests that miss L2 cache.",
@@ -211,8 +169,6 @@
},
{
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_HIT",
"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.",
@@ -221,8 +177,6 @@
},
{
"BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.PF_MISS",
"PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.",
@@ -231,8 +185,6 @@
},
{
"BriefDescription": "All L2 requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"PublicDescription": "All L2 requests.",
@@ -241,8 +193,6 @@
},
{
"BriefDescription": "RFO requests that hit L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
@@ -251,8 +201,6 @@
},
{
"BriefDescription": "RFO requests that miss L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
@@ -261,8 +209,6 @@
},
{
"BriefDescription": "L2 writebacks that access L2 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "Counts L2 writebacks that access L2 cache.",
@@ -271,8 +217,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests missed L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL057",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS",
@@ -282,8 +226,6 @@
},
{
"BriefDescription": "Core-originated cacheable demand requests that refer to L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL057",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
@@ -293,8 +235,6 @@
},
{
"BriefDescription": "All retired load instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.ALL_LOADS",
@@ -304,24 +244,18 @@
},
{
"BriefDescription": "All retired store instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.ALL_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"SampleAfterValue": "2000003",
"UMask": "0x82"
},
{
"BriefDescription": "All retired memory instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.ANY",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "Counts all retired memory instructions - loads and stores.",
"SampleAfterValue": "2000003",
@@ -329,8 +263,6 @@
},
{
"BriefDescription": "Retired load instructions with locked access.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.LOCK_LOADS",
@@ -340,8 +272,6 @@
},
{
"BriefDescription": "Retired load instructions that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
@@ -352,12 +282,9 @@
},
{
"BriefDescription": "Retired store instructions that split across a cacheline boundary.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.SPLIT_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
"SampleAfterValue": "100003",
@@ -365,8 +292,6 @@
},
{
"BriefDescription": "Retired load instructions that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
@@ -377,12 +302,9 @@
},
{
"BriefDescription": "Retired store instructions that miss the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
- "L1_Hit_Indication": "1",
"PEBS": "1",
"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
"SampleAfterValue": "100003",
@@ -390,8 +312,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
@@ -402,8 +322,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
@@ -414,8 +332,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
@@ -425,8 +341,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
@@ -437,8 +351,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
@@ -449,8 +361,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
@@ -460,8 +370,6 @@
},
{
"BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
@@ -471,8 +379,6 @@
},
{
"BriefDescription": "Retired load instructions whose data sources was remote HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
@@ -483,10 +389,7 @@
},
{
"BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches. Precise event.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
- "ELLC": "1",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM",
"PEBS": "1",
@@ -496,8 +399,6 @@
},
{
"BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD4",
"EventName": "MEM_LOAD_MISC_RETIRED.UC",
@@ -507,8 +408,6 @@
},
{
"BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.FB_HIT",
@@ -519,8 +418,6 @@
},
{
"BriefDescription": "Retired load instructions with L1 cache hits as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L1_HIT",
@@ -531,8 +428,6 @@
},
{
"BriefDescription": "Retired load instructions missed L1 cache as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L1_MISS",
@@ -543,8 +438,6 @@
},
{
"BriefDescription": "Retired load instructions with L2 cache hits as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L2_HIT",
@@ -555,8 +448,6 @@
},
{
"BriefDescription": "Retired load instructions missed L2 cache as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L2_MISS",
@@ -567,8 +458,6 @@
},
{
"BriefDescription": "Retired load instructions with L3 cache hits as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L3_HIT",
@@ -579,8 +468,6 @@
},
{
"BriefDescription": "Retired load instructions missed L3 cache as data sources",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.L3_MISS",
@@ -591,10 +478,7 @@
},
{
"BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches. Precise event.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
- "ELLC": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_RETIRED.LOCAL_PMM",
"PEBS": "1",
@@ -604,6056 +488,4542 @@
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F800807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10000807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8000807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4000807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F802007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8002007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4002007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1002007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2002007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x802007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F800407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10000407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8000407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4000407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F801007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8001007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4001007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1001007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2001007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x801007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Demand and prefetch data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
@@ -6662,8 +5032,6 @@
},
{
"BriefDescription": "Any memory transaction that reached the SQ.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
"PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
@@ -6672,8 +5040,6 @@
},
{
"BriefDescription": "Cacheable and noncachaeble code read requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
@@ -6682,8 +5048,6 @@
},
{
"BriefDescription": "Demand Data Read requests sent to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
@@ -6692,8 +5056,6 @@
},
{
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
@@ -6702,8 +5064,6 @@
},
{
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB2",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.",
@@ -6712,8 +5072,6 @@
},
{
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
@@ -6722,8 +5080,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
@@ -6733,8 +5089,6 @@
},
{
"BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
@@ -6744,8 +5098,6 @@
},
{
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
@@ -6755,8 +5107,6 @@
},
{
"BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
@@ -6766,8 +5116,6 @@
},
{
"BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
"PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
@@ -6776,8 +5124,6 @@
},
{
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.",
@@ -6786,8 +5132,6 @@
},
{
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
@@ -6796,8 +5140,6 @@
},
{
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
@@ -6806,8 +5148,6 @@
},
{
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -6816,8562 +5156,6586 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x107F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C07F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F800807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10000807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8000807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4000807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800807F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F802007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8002007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4002007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1002007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2002007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x802007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F800407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10000407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8000407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4000407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800407F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F801007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8001007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4001007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1001007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2001007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x801007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F804007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F800207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10000207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8000207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4000207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C8000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80088000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80208000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80048000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80108000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.ANY_RESPONSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8007C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2003C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x803C0100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80080100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80200100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80040100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80100100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of cache line split locks sent to uncore.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
@@ -15380,8 +11744,6 @@
},
{
"BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.NTA",
"SampleAfterValue": "2000003",
@@ -15389,8 +11751,6 @@
},
{
"BriefDescription": "Number of PREFETCHW instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
"SampleAfterValue": "2000003",
@@ -15398,8 +11758,6 @@
},
{
"BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T0",
"SampleAfterValue": "2000003",
@@ -15407,8 +11765,6 @@
},
{
"BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x32",
"EventName": "SW_PREFETCH_ACCESS.T1_T2",
"SampleAfterValue": "2000003",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
index 81de1149297d..356cf6603b69 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json
@@ -1,1575 +1,1548 @@
[
{
- "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
- "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
- "MetricGroup": "PGO;TopdownL1;tma_L1_group",
- "MetricName": "tma_frontend_bound",
- "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS",
- "ScaleUnit": "100%"
- },
- {
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
- "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS",
- "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_latency",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
+ "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "Mispredictions"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses",
- "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@) / CLKS",
- "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_icache_misses",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "Memory_Bandwidth"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses",
- "MetricExpr": "ICACHE_64B.IFTAG_STALL / CLKS",
- "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_itlb_misses",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
+ "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound))",
+ "MetricGroup": "Mem;MemoryLat;Offcore",
+ "MetricName": "Memory_Latency"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
- "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_branches",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_branch_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
+ "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))",
+ "MetricGroup": "Mem;MemoryTLB;Offcore",
+ "MetricName": "Memory_Data_TLBs"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_mispredicts_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
+ "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
+ "MetricGroup": "Ret",
+ "MetricName": "Branching_Overhead"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
- "MetricExpr": "(1 - (BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT))) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS",
- "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_clears_resteers",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
+ "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
+ "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
+ "MetricName": "Big_Code"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
- "MetricExpr": "9 * BACLEARS.ANY / CLKS",
- "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group",
- "MetricName": "tma_unknown_branches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
+ "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
+ "MetricGroup": "Fed;FetchBW;Frontend",
+ "MetricName": "Instruction_Fetch_BW"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
- "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS",
- "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_dsb_switches",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
+ "MetricExpr": "INST_RETIRED.ANY / CLKS",
+ "MetricGroup": "Ret;Summary",
+ "MetricName": "IPC"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
- "MetricExpr": "ILD_STALL.LCP / CLKS",
- "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_lcp",
- "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Uops Per Instruction",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
+ "MetricGroup": "Pipeline;Ret;Retire",
+ "MetricName": "UPI"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
- "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS",
- "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group",
- "MetricName": "tma_ms_switches",
- "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW",
+ "MetricName": "UpTB"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
- "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
- "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group",
- "MetricName": "tma_fetch_bandwidth",
- "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
+ "MetricExpr": "1 / IPC",
+ "MetricGroup": "Mem;Pipeline",
+ "MetricName": "CPI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
- "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_mite",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "Pipeline",
+ "MetricName": "CLKS"
},
{
- "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
- "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / CORE_CLKS",
- "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group",
- "MetricName": "tma_decoder0_alone",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
+ "MetricExpr": "4 * CORE_CLKS",
+ "MetricGroup": "tma_L1_group",
+ "MetricName": "SLOTS"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
- "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
- "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group",
- "MetricName": "tma_dsb",
- "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
- "ScaleUnit": "100%"
+ "BriefDescription": "The ratio of Executed- by Issued-Uops",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
+ "MetricGroup": "Cor;Pipeline",
+ "MetricName": "Execute_per_Issue",
+ "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
},
{
- "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
- "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_bad_speculation",
- "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
+ "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
+ "MetricGroup": "Ret;SMT;tma_L1_group",
+ "MetricName": "CoreIPC"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
- "MetricExpr": "(BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * tma_bad_speculation",
- "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_branch_mispredicts",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
- "ScaleUnit": "100%"
+ "BriefDescription": "Floating Point Operations Per Cycle",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
+ "MetricGroup": "Flops;Ret",
+ "MetricName": "FLOPc"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
- "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
- "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group",
- "MetricName": "tma_machine_clears",
- "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "FP_Arith_Utilization",
+ "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
},
{
- "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
- "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * ((INT_MISC.RECOVERY_CYCLES_ANY / 2) if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_backend_bound",
- "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
+ "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
+ "MetricName": "ILP"
},
{
- "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * tma_backend_bound",
- "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_memory_bound",
- "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
+ "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)",
+ "MetricGroup": "Cor;SMT",
+ "MetricName": "Core_Bound_Likely"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
- "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l1_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
+ "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))",
+ "MetricGroup": "SMT",
+ "MetricName": "CORE_CLKS"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
- "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_dtlb_load",
- "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
+ "MetricGroup": "InsType",
+ "MetricName": "IpLoad"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
- "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
- "MetricName": "tma_load_stlb_hit",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
+ "MetricGroup": "InsType",
+ "MetricName": "IpStore"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group",
- "MetricName": "tma_load_stlb_miss",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Branches;Fed;InsType",
+ "MetricName": "IpBranch"
},
{
- "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
- "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_store_fwd_blk",
- "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "IpCall"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
- "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS",
- "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_lock_latency",
- "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instruction per taken branch",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
+ "MetricName": "IpTB"
},
{
- "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary",
- "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_split_loads",
- "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch instructions per taken branch. ",
+ "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
+ "MetricGroup": "Branches;Fed;PGO",
+ "MetricName": "BpTkBranch"
},
{
- "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
- "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS",
- "MetricGroup": "TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_4k_aliasing",
- "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "IpFLOP"
},
{
- "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
- "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CLKS",
- "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group",
- "MetricName": "tma_fb_full",
- "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
+ "MetricGroup": "Flops;InsType",
+ "MetricName": "IpArith",
+ "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
- "MetricExpr": "((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / ((MEM_LOAD_RETIRED.L2_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@)) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l2_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "IpArith_Scalar_SP",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
- "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CLKS",
- "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_l3_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
+ "MetricGroup": "Flops;FpScalar;InsType",
+ "MetricName": "IpArith_Scalar_DP",
+ "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
- "MetricExpr": "((44 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) + (44 * Average_Frequency) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_contested_accesses",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX128",
+ "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
- "MetricExpr": "(44 * Average_Frequency) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD)))) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_data_sharing",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX256",
+ "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
- "MetricExpr": "(17 * Average_Frequency) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_l3_hit_latency",
- "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
+ "MetricGroup": "Flops;FpVector;InsType",
+ "MetricName": "IpArith_AVX512",
+ "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
- "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
- "MetricExpr": "((OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2) if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group",
- "MetricName": "tma_sq_full",
- "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
+ "MetricGroup": "Prefetches",
+ "MetricName": "IpSWPF"
},
{
- "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
- "MetricExpr": "((CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound) - tma_pmm_bound)",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_dram_bound",
- "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
+ "MetricExpr": "INST_RETIRED.ANY",
+ "MetricGroup": "Summary;tma_L1_group",
+ "MetricName": "Instructions"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS",
- "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_bandwidth",
- "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
+ "MetricGroup": "Pipeline;Ret",
+ "MetricName": "Retire"
},
{
- "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
- "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group",
- "MetricName": "tma_mem_latency",
- "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
- "ScaleUnit": "100%"
+ "BriefDescription": "",
+ "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
+ "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
+ "MetricName": "Execute"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
- "MetricExpr": "(59.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Server;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_local_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of Uops issued by front-end when it issued something",
+ "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
+ "MetricGroup": "Fed;FetchBW",
+ "MetricName": "Fetch_UpC"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
- "MetricExpr": "(127 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_dram",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
+ "MetricGroup": "DSB;Fed;FetchBW",
+ "MetricName": "DSB_Coverage"
},
{
- "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
- "MetricExpr": "((89.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (89.5 * Average_Frequency) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CLKS",
- "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group",
- "MetricName": "tma_remote_cache",
- "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT",
+ "MetricGroup": "DSBmiss",
+ "MetricName": "DSB_Switch_Cost"
},
{
- "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
- "MetricExpr": "(((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) / ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 10 * ((MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS) - tma_l2_bound)) if (1000000 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS) else 0)",
- "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_pmm_bound",
- "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
- "ScaleUnit": "100%"
+ "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
+ "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "DSB_Misses"
},
{
- "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
- "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS",
- "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group",
- "MetricName": "tma_store_bound",
- "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
+ "MetricGroup": "DSBmiss;Fed",
+ "MetricName": "IpDSB_Miss_Ret"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
- "MetricExpr": "((L2_RQSTS.RFO_HIT * 11 * (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES))) + (1 - (MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES)) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS",
- "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_store_latency",
- "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
- "ScaleUnit": "100%"
+ "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
+ "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BadSpec;BrMispredicts",
+ "MetricName": "IpMispredict"
},
{
- "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
- "MetricExpr": "((110 * Average_Frequency) * (OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM) + (47.5 * Average_Frequency) * (OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / CLKS",
- "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_false_sharing",
- "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "ScaleUnit": "100%"
+ "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
+ "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;BrMispredicts",
+ "MetricName": "Branch_Misprediction_Cost"
},
{
- "BriefDescription": "This metric represents rate of split store accesses",
- "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS",
- "MetricGroup": "TopdownL4;tma_store_bound_group",
- "MetricName": "tma_split_stores",
- "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are non-taken conditionals",
+ "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches;CodeGen;PGO",
+ "MetricName": "Cond_NT"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
- "MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS",
- "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group",
- "MetricName": "tma_dtlb_store",
- "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are taken conditionals",
+ "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches;CodeGen;PGO",
+ "MetricName": "Cond_TK"
},
{
- "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
- "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
- "MetricName": "tma_store_stlb_hit",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are CALL or RET",
+ "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "CallRet"
},
{
- "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
- "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
- "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group",
- "MetricName": "tma_store_stlb_miss",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
+ "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
+ "MetricGroup": "Bad;Branches",
+ "MetricName": "Jump"
},
{
- "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
- "MetricExpr": "tma_backend_bound - tma_memory_bound",
- "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group",
- "MetricName": "tma_core_bound",
- "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
- "ScaleUnit": "100%"
+ "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
+ "MetricGroup": "Mem;MemoryBound;MemoryLat",
+ "MetricName": "Load_Miss_Real_Latency"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
- "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS",
- "MetricGroup": "TopdownL3;tma_core_bound_group",
- "MetricName": "tma_divider",
- "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE",
- "ScaleUnit": "100%"
+ "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
+ "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
+ "MetricGroup": "Mem;MemoryBW;MemoryBound",
+ "MetricName": "MLP"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
- "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if (ARITH.DIVIDER_ACTIVE < (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY)) else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS",
- "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group",
- "MetricName": "tma_ports_utilization",
- "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L1MPKI"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_0",
- "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L1MPKI_Load"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
- "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / CLKS",
- "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
- "MetricName": "tma_serializing_operation",
- "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "Backend;CacheMisses;Mem",
+ "MetricName": "L2MPKI"
},
{
- "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions",
- "MetricExpr": "40 * ROB_MISC_EVENTS.PAUSE_INST / CLKS",
- "MetricGroup": "TopdownL6;tma_serializing_operation_group",
- "MetricName": "tma_slow_pause",
- "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem;Offcore",
+ "MetricName": "L2MPKI_All"
},
{
- "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
- "MetricExpr": "CLKS * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY",
- "MetricGroup": "TopdownL5;tma_ports_utilized_0_group",
- "MetricName": "tma_mixing_vectors",
- "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2MPKI_Load"
},
{
- "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_1",
- "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
+ "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2HPKI_All"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
- "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_2",
- "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
- "ScaleUnit": "100%"
+ "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
+ "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L2HPKI_Load"
},
{
- "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
- "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / CORE_CLKS",
- "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group",
- "MetricName": "tma_ports_utilized_3m",
- "ScaleUnit": "100%"
+ "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "L3MPKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / (4 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_alu_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
+ "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
+ "MetricGroup": "CacheMisses;Mem",
+ "MetricName": "FB_HPKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
- "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_0",
- "ScaleUnit": "100%"
+ "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
+ "MetricConstraint": "NO_NMI_WATCHDOG",
+ "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * CORE_CLKS)",
+ "MetricGroup": "Mem;MemoryTLB",
+ "MetricName": "Page_Walks_Utilization"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_1",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_5",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_alu_op_utilization_group",
- "MetricName": "tma_port_6",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3",
- "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_load_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "L3_Cache_Access_BW"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
- "MetricName": "tma_port_2",
- "ScaleUnit": "100%"
+ "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
+ "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions",
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "L2_Evictions_Silent_PKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_load_op_utilization_group",
- "MetricName": "tma_port_3",
- "ScaleUnit": "100%"
+ "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
+ "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions",
+ "MetricGroup": "L2Evicts;Mem;Server",
+ "MetricName": "L2_Evictions_NonSilent_PKI"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
- "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group",
- "MetricName": "tma_store_op_utilization",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
+ "MetricExpr": "L1D_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L1D_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
- "MetricName": "tma_port_4",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
+ "MetricExpr": "L2_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L2_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Sample with: UOPS_DISPATCHED_PORT.PORT_7",
- "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
- "MetricGroup": "TopdownL6;tma_store_op_utilization_group",
- "MetricName": "tma_port_7",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "L3_Cache_Fill_BW",
+ "MetricGroup": "Mem;MemoryBW",
+ "MetricName": "L3_Cache_Fill_BW_1T"
},
{
- "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
- "MetricGroup": "TopdownL1;tma_L1_group",
- "MetricName": "tma_retiring",
- "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
+ "MetricExpr": "L3_Cache_Access_BW",
+ "MetricGroup": "Mem;MemoryBW;Offcore",
+ "MetricName": "L3_Cache_Access_BW_1T"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
- "MetricExpr": "tma_retiring - tma_heavy_operations",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_light_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average CPU Utilization",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricGroup": "HPC;Summary",
+ "MetricName": "CPU_Utilization"
},
{
- "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
- "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector",
- "MetricGroup": "HPC;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_fp_arith",
- "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
+ "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time",
+ "MetricGroup": "Power;Summary",
+ "MetricName": "Average_Frequency"
},
{
- "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
- "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
- "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_x87_use",
- "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Giga Floating Point Operations Per Second",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time",
+ "MetricGroup": "Cor;Flops;HPC",
+ "MetricName": "GFLOPs",
+ "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
},
{
- "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_fp_scalar",
- "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average Frequency Utilization relative nominal frequency",
+ "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
+ "MetricGroup": "Power",
+ "MetricName": "Turbo_Utilization"
},
{
- "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group",
- "MetricName": "tma_fp_vector",
- "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
+ "MetricExpr": "(CORE_POWER.LVL0_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS)",
+ "MetricGroup": "Power",
+ "MetricName": "Power_License0_Utilization",
+ "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_128b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
+ "MetricExpr": "(CORE_POWER.LVL1_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS)",
+ "MetricGroup": "Power",
+ "MetricName": "Power_License1_Utilization",
+ "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_256b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
+ "MetricExpr": "(CORE_POWER.LVL2_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS)",
+ "MetricGroup": "Power",
+ "MetricName": "Power_License2_Utilization",
+ "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions."
},
{
- "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
- "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group",
- "MetricName": "tma_fp_vector_512b",
- "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
+ "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)",
+ "MetricGroup": "SMT",
+ "MetricName": "SMT_2T_Utilization"
+ },
+ {
+ "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_Utilization"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
- "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_memory_operations",
- "ScaleUnit": "100%"
+ "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
+ "MetricGroup": "OS",
+ "MetricName": "Kernel_CPI"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
- "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_fused_instructions",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
+ "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time",
+ "MetricGroup": "HPC;Mem;MemoryBW;SoC",
+ "MetricName": "DRAM_BW_Use"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
- "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_non_fused_branches",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)",
+ "MetricGroup": "Mem;MemoryLat;SoC",
+ "MetricName": "MEM_Read_Latency"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
- "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_nop_instructions",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
+ "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@",
+ "MetricGroup": "Mem;MemoryBW;SoC",
+ "MetricName": "MEM_Parallel_Reads"
},
{
- "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
- "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))",
- "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group",
- "MetricName": "tma_other_light_ops",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+ "MetricExpr": "1e9 * (UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS) / imc_0@event\\=0x0@",
+ "MetricGroup": "Mem;MemoryLat;Server;SoC",
+ "MetricName": "MEM_PMM_Read_Latency"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS",
- "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group",
- "MetricName": "tma_heavy_operations",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
+ "MetricExpr": "1e9 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\\=0x0@",
+ "MetricGroup": "Mem;MemoryLat;Server;SoC",
+ "MetricName": "MEM_DRAM_Read_Latency"
},
{
- "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
- "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer",
- "MetricGroup": "TopdownL3;tma_heavy_operations_group",
- "MetricName": "tma_few_uops_instructions",
- "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
+ "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Server;SoC",
+ "MetricName": "PMM_Read_BW"
},
{
- "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
- "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY) * IDQ.MS_UOPS / SLOTS",
- "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group",
- "MetricName": "tma_microcode_sequencer",
- "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
+ "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time",
+ "MetricGroup": "Mem;MemoryBW;Server;SoC",
+ "MetricName": "PMM_Write_BW"
},
{
- "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
- "MetricExpr": "100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / SLOTS",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_assists",
- "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
+ "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e9 / duration_time",
+ "MetricGroup": "IoBW;Mem;Server;SoC",
+ "MetricName": "IO_Write_BW"
},
{
- "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
- "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
- "MetricGroup": "TopdownL4;tma_microcode_sequencer_group",
- "MetricName": "tma_cisc",
- "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
- "ScaleUnit": "100%"
+ "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
+ "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1e9 / duration_time",
+ "MetricGroup": "IoBW;Mem;Server;SoC",
+ "MetricName": "IO_Read_BW"
},
{
- "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
- "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
- "MetricGroup": "Bad;BadSpec;BrMispredicts",
- "MetricName": "Mispredictions"
+ "BriefDescription": "Socket actual clocks when any core is active on that socket",
+ "MetricExpr": "cha_0@event\\=0x0@",
+ "MetricGroup": "SoC",
+ "MetricName": "Socket_CLKS"
},
{
- "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) ",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "Memory_Bandwidth"
+ "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
+ "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
+ "MetricGroup": "Branches;OS",
+ "MetricName": "IpFarBranch"
},
{
- "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + (tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)))",
- "MetricGroup": "Mem;MemoryLat;Offcore",
- "MetricName": "Memory_Latency"
+ "BriefDescription": "Uncore frequency per die [GHZ]",
+ "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9",
+ "MetricGroup": "SoC",
+ "MetricName": "UNCORE_FREQ"
},
{
- "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
- "MetricExpr": "100 * tma_memory_bound * ((tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency))) ",
- "MetricGroup": "Mem;MemoryTLB;Offcore",
- "MetricName": "Memory_Data_TLBs"
+ "BriefDescription": "Percentage of time spent in the active CPU power state C0",
+ "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",
+ "MetricName": "cpu_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)",
- "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)",
- "MetricGroup": "Ret",
- "MetricName": "Branching_Overhead"
+ "BriefDescription": "CPU operating frequency (in GHz)",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time",
+ "MetricName": "cpu_operating_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
- "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
- "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB",
- "MetricName": "Big_Code"
+ "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.",
+ "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY",
+ "MetricName": "cpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks",
- "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code",
- "MetricGroup": "Fed;FetchBW;Frontend",
- "MetricName": "Instruction_Fetch_BW"
+ "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
+ "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
+ "MetricName": "loads_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions Per Cycle (per Logical Processor)",
- "MetricExpr": "INST_RETIRED.ANY / CLKS",
- "MetricGroup": "Ret;Summary",
- "MetricName": "IPC"
+ "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
+ "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
+ "MetricName": "stores_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Uops Per Instruction",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
- "MetricGroup": "Pipeline;Ret;Retire",
- "MetricName": "UPI"
+ "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
+ "MetricName": "l1d_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW",
- "MetricName": "UpTB"
+ "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
+ "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
+ "MetricName": "l1d_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
- "MetricExpr": "1 / IPC",
- "MetricGroup": "Mem;Pipeline",
- "MetricName": "CPI"
+ "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
+ "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "Pipeline",
- "MetricName": "CLKS"
+ "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_hits_per_instr",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
- "MetricExpr": "4 * CORE_CLKS",
- "MetricGroup": "tma_L1_group",
- "MetricName": "SLOTS"
+ "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
+ "MetricName": "l2_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "The ratio of Executed- by Issued-Uops",
- "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
- "MetricGroup": "Cor;Pipeline",
- "MetricName": "Execute_per_Issue",
- "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
+ "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_data_read_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
- "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS",
- "MetricGroup": "Ret;SMT;tma_L1_group",
- "MetricName": "CoreIPC"
+ "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
+ "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
+ "MetricName": "l2_demand_code_mpi",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Floating Point Operations Per Cycle",
- "MetricExpr": "(1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS",
- "MetricGroup": "Flops;Ret",
- "MetricName": "FLOPc"
+ "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12D4043300000000@ / INST_RETIRED.ANY",
+ "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)",
- "MetricExpr": "((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)",
- "MetricGroup": "Cor;Flops;HPC",
- "MetricName": "FP_Arith_Utilization",
- "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)."
+ "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
+ "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12CC023300000000@ / INST_RETIRED.ANY",
+ "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
- "MetricExpr": "UOPS_EXECUTED.THREAD / ((UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)",
- "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
- "MetricName": "ILP"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
+ "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043300000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043300000000@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts",
- "MetricExpr": "(1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0",
- "MetricGroup": "Cor;SMT",
- "MetricName": "Core_Bound_Likely"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
+ "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043200000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
- "MetricExpr": "((CPU_CLK_UNHALTED.THREAD / 2) * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK)) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2) if #SMT_on else CLKS",
- "MetricGroup": "SMT",
- "MetricName": "CORE_CLKS"
+ "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
+ "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043100000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time",
+ "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
+ "ScaleUnit": "1ns"
},
{
- "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS",
- "MetricGroup": "InsType",
- "MetricName": "IpLoad"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "itlb_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES",
- "MetricGroup": "InsType",
- "MetricName": "IpStore"
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions",
+ "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "itlb_large_page_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Branches;Fed;InsType",
- "MetricName": "IpBranch"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "IpCall"
+ "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
+ "MetricName": "dtlb_2mb_large_page_load_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
},
{
- "BriefDescription": "Instruction per taken branch",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
- "MetricName": "IpTB"
+ "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
+ "MetricName": "dtlb_store_mpi",
+ "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
+ "ScaleUnit": "1per_instr"
+ },
+ {
+ "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@)",
+ "MetricName": "numa_reads_addressed_to_local_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Branch instructions per taken branch. ",
- "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
- "MetricGroup": "Branches;Fed;PGO",
- "MetricName": "BpTkBranch"
+ "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
+ "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@)",
+ "MetricName": "numa_reads_addressed_to_remote_dram",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
- "MetricGroup": "Flops;InsType",
- "MetricName": "IpFLOP"
+ "BriefDescription": "Uncore operating frequency in GHz",
+ "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time",
+ "MetricName": "uncore_frequency",
+ "ScaleUnit": "1GHz"
},
{
- "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / ((FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))",
- "MetricGroup": "Flops;InsType",
- "MetricName": "IpArith",
- "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
+ "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
+ "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time",
+ "MetricName": "upi_data_transmit_bw",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
- "MetricGroup": "Flops;FpScalar;InsType",
- "MetricName": "IpArith_Scalar_SP",
- "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "DDR memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
- "MetricGroup": "Flops;FpScalar;InsType",
- "MetricName": "IpArith_Scalar_DP",
- "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "DDR memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX128",
- "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "DDR memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time",
+ "MetricName": "memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX256",
- "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)",
- "MetricGroup": "Flops;FpVector;InsType",
- "MetricName": "IpArith_AVX512",
- "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
+ "MetricExpr": "UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@",
- "MetricGroup": "Prefetches",
- "MetricName": "IpSWPF"
+ "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
+ "MetricExpr": "(UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time",
+ "MetricName": "pmem_memory_bandwidth_total",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST",
- "MetricExpr": "INST_RETIRED.ANY",
- "MetricGroup": "Summary;tma_L1_group",
- "MetricName": "Instructions"
+ "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
+ "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_writes",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
- "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
- "MetricGroup": "Pipeline;Ret",
- "MetricName": "Retire"
+ "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
+ "MetricExpr": "(UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3) * 4 / 1e6 / duration_time",
+ "MetricName": "io_bandwidth_disk_or_network_reads",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "",
- "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
- "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
- "MetricName": "Execute"
+ "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_decoded_icache",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of Uops issued by front-end when it issued something",
- "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@",
- "MetricGroup": "Fed;FetchBW",
- "MetricName": "Fetch_UpC"
+ "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
- "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)",
- "MetricGroup": "DSB;Fed;FetchBW",
- "MetricName": "DSB_Coverage"
+ "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
+ "MetricExpr": "IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)",
+ "MetricName": "percent_uops_delivered_from_microcode_sequencer",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.",
- "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT",
- "MetricGroup": "DSBmiss",
- "MetricName": "DSB_Switch_Cost"
+ "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_local_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.",
- "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))",
- "MetricGroup": "DSBmiss;Fed",
- "MetricName": "DSB_Misses"
+ "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_local_memory_bandwidth_write",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS",
- "MetricGroup": "DSBmiss;Fed",
- "MetricName": "IpDSB_Miss_Ret"
+ "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
+ "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time",
+ "MetricName": "llc_miss_remote_memory_bandwidth_read",
+ "ScaleUnit": "1MB/s"
},
{
- "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
- "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BadSpec;BrMispredicts",
- "MetricName": "IpMispredict"
+ "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
+ "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS",
+ "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_frontend_bound",
+ "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
- "MetricExpr": " (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;BrMispredicts",
- "MetricName": "Branch_Misprediction_Cost"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues",
+ "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS",
+ "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_latency",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are non-taken conditionals",
- "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches;CodeGen;PGO",
- "MetricName": "Cond_NT"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.",
+ "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_icache_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are taken conditionals",
- "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches;CodeGen;PGO",
- "MetricName": "Cond_TK"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.",
+ "MetricExpr": "ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_itlb_misses",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are CALL or RET",
- "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches",
- "MetricName": "CallRet"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
+ "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + tma_unknown_branches",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_branch_resteers",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps",
- "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES",
- "MetricGroup": "Bad;Branches",
- "MetricName": "Jump"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_mispredicts_resteers",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)",
- "MetricGroup": "Mem;MemoryBound;MemoryLat",
- "MetricName": "Load_Miss_Real_Latency"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ",
+ "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_clears_resteers",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
- "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
- "MetricGroup": "Mem;MemoryBW;MemoryBound",
- "MetricName": "MLP"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears",
+ "MetricExpr": "9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group",
+ "MetricName": "tma_unknown_branches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L1MPKI"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines",
+ "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_dsb_switches",
+ "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L1MPKI_Load"
+ "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)",
+ "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_lcp",
+ "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "Backend;CacheMisses;Mem",
- "MetricName": "L2MPKI"
+ "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)",
+ "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group",
+ "MetricName": "tma_ms_switches",
+ "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem;Offcore",
- "MetricName": "L2MPKI_All"
+ "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues",
+ "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
+ "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group",
+ "MetricName": "tma_fetch_bandwidth",
+ "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2MPKI_Load"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)",
+ "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_mite",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
- "MetricExpr": "1000 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2HPKI_All"
+ "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder",
+ "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@) / CORE_CLKS",
+ "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group",
+ "MetricName": "tma_decoder0_alone",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
- "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L2HPKI_Load"
+ "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline",
+ "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2",
+ "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
+ "MetricName": "tma_dsb",
+ "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "L3MPKI"
+ "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
+ "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_bad_speculation",
+ "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)",
- "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY",
- "MetricGroup": "CacheMisses;Mem",
- "MetricName": "FB_HPKI"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
+ "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation",
+ "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_branch_mispredicts",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
- "MetricConstraint": "NO_NMI_WATCHDOG",
- "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * CORE_CLKS)",
- "MetricGroup": "Mem;MemoryTLB",
- "MetricName": "Page_Walks_Utilization"
+ "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears",
+ "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
+ "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group",
+ "MetricName": "tma_machine_clears",
+ "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW"
+ "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
+ "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_backend_bound",
+ "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.",
+ "ScaleUnit": "100%"
},
- {
- "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW"
+ {
+ "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound",
+ "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_memory_bound",
+ "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW"
+ "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache",
+ "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l1_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "L3_Cache_Access_BW"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses",
+ "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_dtlb_load",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)",
- "MetricExpr": "1000 * L2_LINES_OUT.SILENT / Instructions",
- "MetricGroup": "L2Evicts;Mem;Server",
- "MetricName": "L2_Evictions_Silent_PKI"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)",
+ "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+ "MetricName": "tma_load_stlb_hit",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction",
- "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / Instructions",
- "MetricGroup": "L2Evicts;Mem;Server",
- "MetricName": "L2_Evictions_NonSilent_PKI"
+ "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk",
+ "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group",
+ "MetricName": "tma_load_stlb_miss",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
- "MetricExpr": "L1D_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L1D_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores",
+ "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_store_fwd_blk",
+ "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
- "MetricExpr": "L2_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L2_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations",
+ "MetricExpr": "min((12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_lock_latency",
+ "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "L3_Cache_Fill_BW",
- "MetricGroup": "Mem;MemoryBW",
- "MetricName": "L3_Cache_Fill_BW_1T"
+ "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ",
+ "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_split_loads",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
- "MetricExpr": "L3_Cache_Access_BW",
- "MetricGroup": "Mem;MemoryBW;Offcore",
- "MetricName": "L3_Cache_Access_BW_1T"
+ "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset",
+ "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_4k_aliasing",
+ "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average CPU Utilization",
- "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
- "MetricGroup": "HPC;Summary",
- "MetricName": "CPU_Utilization"
+ "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed",
+ "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group",
+ "MetricName": "tma_fb_full",
+ "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
- "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",
- "MetricGroup": "Power;Summary",
- "MetricName": "Average_Frequency"
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads",
+ "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD)",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l2_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Giga Floating Point Operations Per Second",
- "MetricExpr": "((1 * (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1000000000) / duration_time",
- "MetricGroup": "Cor;Flops;HPC",
- "MetricName": "GFLOPs",
- "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
+ "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core",
+ "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_l3_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average Frequency Utilization relative nominal frequency",
- "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC",
- "MetricGroup": "Power",
- "MetricName": "Turbo_Utilization"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses",
+ "MetricExpr": "min(((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) + (47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_contested_accesses",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0",
- "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS",
- "MetricGroup": "Power",
- "MetricName": "Power_License0_Utilization",
- "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes."
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
+ "MetricExpr": "min((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_data_sharing",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1",
- "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS",
- "MetricGroup": "Power",
- "MetricName": "Power_License1_Utilization",
- "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions."
+ "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)",
+ "MetricExpr": "min((20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_l3_hit_latency",
+ "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)",
- "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS",
- "MetricGroup": "Power",
- "MetricName": "Power_License2_Utilization",
- "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions."
+ "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)",
+ "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group",
+ "MetricName": "tma_sq_full",
+ "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
- "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0",
- "MetricGroup": "SMT",
- "MetricName": "SMT_2T_Utilization"
+ "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads",
+ "MetricExpr": "min(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound - min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1), 1)",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_dram_bound",
+ "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
- "MetricGroup": "OS",
- "MetricName": "Kernel_Utilization"
+ "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_bandwidth",
+ "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
- "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
- "MetricGroup": "OS",
- "MetricName": "Kernel_CPI"
+ "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group",
+ "MetricName": "tma_mem_latency",
+ "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
- "MetricExpr": "(64 * (uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@) / 1000000000) / duration_time",
- "MetricGroup": "HPC;Mem;MemoryBW;SoC",
- "MetricName": "DRAM_BW_Use"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory",
+ "MetricExpr": "min((80 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_local_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "1000000000 * (cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433@ / cha@event\\=0x35\\,umask\\=0x21\\,config\\=0x40433@) / (Socket_CLKS / duration_time)",
- "MetricGroup": "Mem;MemoryLat;SoC",
- "MetricName": "MEM_Read_Latency"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory",
+ "MetricExpr": "min((147.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_dram",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
- "MetricExpr": "cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433@ / cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433\\,thresh\\=1@",
- "MetricGroup": "Mem;MemoryBW;SoC",
- "MetricName": "MEM_Parallel_Reads"
+ "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues",
+ "MetricExpr": "min(((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group",
+ "MetricName": "tma_remote_cache",
+ "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
- "MetricExpr": "(1000000000 * (imc@event\\=0xe0\\,umask\\=0x1@ / imc@event\\=0xe3@) / imc_0@event\\=0x0@)",
- "MetricGroup": "Mem;MemoryLat;Server;SoC",
- "MetricName": "MEM_PMM_Read_Latency"
+ "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a",
+ "MetricExpr": "min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1)",
+ "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_pmm_bound",
+ "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches",
- "MetricExpr": "1000000000 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\\=0x0@",
- "MetricGroup": "Mem;MemoryLat;Server;SoC",
- "MetricName": "MEM_DRAM_Read_Latency"
+ "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write",
+ "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group",
+ "MetricName": "tma_store_bound",
+ "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]",
- "MetricExpr": "((64 * imc@event\\=0xe3@ / 1000000000) / duration_time)",
- "MetricGroup": "Mem;MemoryBW;Server;SoC",
- "MetricName": "PMM_Read_BW"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses",
+ "MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_store_latency",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]",
- "MetricExpr": "((64 * imc@event\\=0xe7@ / 1000000000) / duration_time)",
- "MetricGroup": "Mem;MemoryBW;Server;SoC",
- "MetricName": "PMM_Write_BW"
+ "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing",
+ "MetricExpr": "min((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / CPU_CLK_UNHALTED.THREAD, 1)",
+ "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_false_sharing",
+ "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]",
- "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1000000000 / duration_time",
- "MetricGroup": "IoBW;Mem;Server;SoC",
- "MetricName": "IO_Write_BW"
+ "BriefDescription": "This metric represents rate of split store accesses",
+ "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_split_stores",
+ "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]",
- "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1000000000 / duration_time",
- "MetricGroup": "IoBW;Mem;Server;SoC",
- "MetricName": "IO_Read_BW"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses",
+ "MetricExpr": "min((9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS, 1)",
+ "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group",
+ "MetricName": "tma_dtlb_store",
+ "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Socket actual clocks when any core is active on that socket",
- "MetricExpr": "cha_0@event\\=0x0@",
- "MetricGroup": "SoC",
- "MetricName": "Socket_CLKS"
+ "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)",
+ "MetricExpr": "tma_dtlb_store - DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+ "MetricName": "tma_store_stlb_hit",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
- "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
- "MetricGroup": "Branches;OS",
- "MetricName": "IpFarBranch"
+ "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk",
+ "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS",
+ "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group",
+ "MetricName": "tma_store_stlb_miss",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C3 residency percent per core",
- "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C3_Core_Residency"
+ "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck",
+ "MetricExpr": "tma_backend_bound - tma_memory_bound",
+ "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group",
+ "MetricName": "tma_core_bound",
+ "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per core",
- "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Core_Residency"
+ "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active",
+ "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_divider",
+ "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C7 residency percent per core",
- "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C7_Core_Residency"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)",
+ "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD)",
+ "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group",
+ "MetricName": "tma_ports_utilization",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C2 residency percent per package",
- "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C2_Pkg_Residency"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_0",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C3 residency percent per package",
- "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C3_Pkg_Residency"
+ "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations",
+ "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+ "MetricName": "tma_serializing_operation",
+ "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C6 residency percent per package",
- "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C6_Pkg_Residency"
+ "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.",
+ "MetricExpr": "40 * ROB_MISC_EVENTS.PAUSE_INST / CPU_CLK_UNHALTED.THREAD",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group",
+ "MetricName": "tma_slow_pause",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "C7 residency percent per package",
- "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",
- "MetricGroup": "Power",
- "MetricName": "C7_Pkg_Residency"
+ "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued",
+ "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY, 1)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group",
+ "MetricName": "tma_mixing_vectors",
+ "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore frequency per die [GHZ]",
- "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",
- "MetricGroup": "SoC",
- "MetricName": "UNCORE_FREQ"
+ "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_1",
+ "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "CPU operating frequency (in GHz)",
- "MetricExpr": "(( CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "cpu_operating_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)",
+ "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_2",
+ "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions",
- "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "loads_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).",
+ "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / CORE_CLKS",
+ "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group",
+ "MetricName": "tma_ports_utilized_3m",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions",
- "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "stores_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_alu_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS",
+ "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_0",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ",
- "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1d_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_1",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_5",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ",
- "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_hits_per_instr",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group",
+ "MetricName": "tma_port_6",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations",
+ "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_load_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_data_read_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+ "MetricName": "tma_port_2",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions",
- "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "l2_demand_code_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group",
+ "MetricName": "tma_port_3",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12D4043300000000@ / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_data_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS",
+ "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
+ "MetricName": "tma_store_op_utilization",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions",
- "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12CC023300000000@ / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "llc_code_read_mpi_demand_plus_prefetch",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
+ "MetricExpr": "tma_store_op_utilization",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+ "MetricName": "tma_port_4",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds",
- "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043300000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043300000000@ ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)",
+ "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS",
+ "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group",
+ "MetricName": "tma_port_7",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043200000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS",
+ "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group",
+ "MetricName": "tma_retiring",
+ "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds",
- "MetricExpr": "( 1000000000 * ( cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043100000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ ) / ( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) ) ) * duration_time",
- "MetricGroup": "",
- "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests",
- "ScaleUnit": "1ns"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)",
+ "MetricExpr": "tma_retiring - (UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_light_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)",
+ "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + tma_fp_scalar + tma_fp_vector",
+ "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_fp_arith",
+ "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.",
- "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "itlb_large_page_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric serves as an approximation of legacy x87 usage",
+ "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD",
+ "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_x87_use",
+ "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_load_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired",
+ "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_fp_scalar",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.",
- "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_2mb_large_page_load_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+ "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group",
+ "MetricName": "tma_fp_vector",
+ "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.",
- "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY",
- "MetricGroup": "",
- "MetricName": "dtlb_store_mpi",
- "ScaleUnit": "1per_instr"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_128b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_local_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_256b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.",
- "MetricExpr": "100 * cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ / ( cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ )",
- "MetricGroup": "",
- "MetricName": "numa_reads_addressed_to_remote_dram",
- "ScaleUnit": "1%"
+ "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors",
+ "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)",
+ "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group",
+ "MetricName": "tma_fp_vector_512b",
+ "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uncore operating frequency in GHz",
- "MetricExpr": "( UNC_CHA_CLOCKTICKS / ( source_count(UNC_CHA_CLOCKTICKS) * #num_packages ) / 1000000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "uncore_frequency",
- "ScaleUnit": "1GHz"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.",
+ "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_memory_operations",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)",
- "MetricExpr": "( UNC_UPI_TxL_FLITS.ALL_DATA * (64 / 9.0) / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "upi_data_transmit_bw",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions",
+ "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_fused_instructions",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory read bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.RD * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused",
+ "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_non_fused_branches",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory write bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_CAS_COUNT.WR * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions",
+ "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_nop_instructions",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "DDR memory bandwidth (MB/sec)",
- "MetricExpr": "(( UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "memory_bandwidth_total",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting",
+ "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))",
+ "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group",
+ "MetricName": "tma_other_light_ops",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_PMM_RPQ_INSERTS * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "pmem_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences",
+ "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS",
+ "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group",
+ "MetricName": "tma_heavy_operations",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)",
- "MetricExpr": "( UNC_M_PMM_WPQ_INSERTS * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "pmem_memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops",
+ "MetricExpr": "tma_heavy_operations - UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+ "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group",
+ "MetricName": "tma_few_uops_instructions",
+ "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)",
- "MetricExpr": "(( UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS ) * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "pmem_memory_bandwidth_total",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit",
+ "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS",
+ "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group",
+ "MetricName": "tma_microcode_sequencer",
+ "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.",
- "MetricExpr": "(( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_writes",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
+ "MetricExpr": "min(100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / SLOTS, 1)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_assists",
+ "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.",
- "MetricExpr": "(( UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3 ) * 4 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "io_bandwidth_disk_or_network_reads",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
+ "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
+ "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
+ "MetricName": "tma_cisc",
+ "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_decoded_icache",
- "ScaleUnit": "1%"
+ "BriefDescription": "C3 residency percent per core",
+ "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C3_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MITE_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline",
- "ScaleUnit": "1%"
+ "BriefDescription": "C6 residency percent per core",
+ "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue",
- "MetricExpr": "100 * ( IDQ.MS_UOPS / ( IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS ) )",
- "MetricGroup": "",
- "MetricName": "percent_uops_delivered_from_microcode_sequencer",
- "ScaleUnit": "1%"
+ "BriefDescription": "C7 residency percent per core",
+ "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C7_Core_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_local_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C2 residency percent per package",
+ "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C2_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_local_memory_bandwidth_write",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C3 residency percent per package",
+ "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C3_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.",
- "MetricExpr": "( UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1000000) / duration_time",
- "MetricGroup": "",
- "MetricName": "llc_miss_remote_memory_bandwidth_read",
- "ScaleUnit": "1MB/s"
+ "BriefDescription": "C6 residency percent per package",
+ "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C6_Pkg_Residency",
+ "ScaleUnit": "100%"
},
{
- "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit. LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure.",
- "MetricExpr": "100 * ( ( LSD.CYCLES_ACTIVE - LSD.CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else ( CPU_CLK_UNHALTED.THREAD ) ) / 2 )",
- "MetricGroup": "FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group",
- "MetricName": "tma_lsd",
- "ScaleUnit": "1%"
+ "BriefDescription": "C7 residency percent per package",
+ "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
+ "MetricGroup": "Power",
+ "MetricName": "C7_Pkg_Residency",
+ "ScaleUnit": "100%"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json b/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json
index 48bb1b38dde6..1f46e6b33856 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -51,8 +41,6 @@
},
{
"BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
"PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -61,8 +49,6 @@
},
{
"BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -71,8 +57,6 @@
},
{
"BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
@@ -81,8 +65,6 @@
},
{
"BriefDescription": "Intel AVX-512 computational 512-bit packed BFloat16 instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCF",
"EventName": "FP_ARITH_INST_RETIRED2.128BIT_PACKED_BF16",
"PublicDescription": "Counts once for each Intel AVX-512 computational 512-bit packed BFloat16 floating-point instruction retired. Applies to the ZMM based VDPBF16PS instruction. Each count represents 64 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.",
@@ -91,8 +73,6 @@
},
{
"BriefDescription": "Intel AVX-512 computational 128-bit packed BFloat16 instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCF",
"EventName": "FP_ARITH_INST_RETIRED2.256BIT_PACKED_BF16",
"PublicDescription": "Counts once for each Intel AVX-512 computational 128-bit packed BFloat16 floating-point instruction retired. Applies to the XMM based VDPBF16PS instruction. Each count represents 16 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.",
@@ -101,8 +81,6 @@
},
{
"BriefDescription": "Intel AVX-512 computational 256-bit packed BFloat16 instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCF",
"EventName": "FP_ARITH_INST_RETIRED2.512BIT_PACKED_BF16",
"PublicDescription": "Counts once for each Intel AVX-512 computational 256-bit packed BFloat16 floating-point instruction retired. Applies to the YMM based VDPBF16PS instruction. Each count represents 32 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.",
@@ -111,8 +89,6 @@
},
{
"BriefDescription": "Cycles with any input/output SSE or FP assist",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json b/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json
index 8633ee406813..13ccf50db43d 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xE6",
"EventName": "BACLEARS.ANY",
"PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.COUNT",
"PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Retired Instructions who experienced DSB miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
"MSRIndex": "0x3F7",
@@ -40,13 +32,10 @@
"PEBS": "1",
"PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.DSB_MISS",
"MSRIndex": "0x3F7",
@@ -54,13 +43,10 @@
"PEBS": "1",
"PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced iTLB true miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
"MSRIndex": "0x3F7",
@@ -68,39 +54,30 @@
"PEBS": "1",
"PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.L1I_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x12",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.L2_MISS",
"MSRIndex": "0x3F7",
"MSRValue": "0x13",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
"MSRIndex": "0x3F7",
@@ -108,26 +85,20 @@
"PEBS": "2",
"PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
"MSRIndex": "0x3F7",
"MSRValue": "0x408006",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
"MSRIndex": "0x3F7",
@@ -135,39 +106,30 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
"MSRIndex": "0x3F7",
"MSRValue": "0x400206",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
"MSRIndex": "0x3F7",
"MSRValue": "0x410006",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
"MSRIndex": "0x3F7",
@@ -175,39 +137,30 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2",
"MSRIndex": "0x3F7",
"MSRValue": "0x200206",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 3 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3",
"MSRIndex": "0x3F7",
"MSRValue": "0x300206",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
"MSRIndex": "0x3F7",
@@ -215,52 +168,40 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
"MSRIndex": "0x3F7",
"MSRValue": "0x400406",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
"MSRIndex": "0x3F7",
"MSRValue": "0x420006",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
"MSRIndex": "0x3F7",
"MSRValue": "0x404006",
"PEBS": "1",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
"MSRIndex": "0x3F7",
@@ -268,13 +209,10 @@
"PEBS": "1",
"PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC6",
"EventName": "FRONTEND_RETIRED.STLB_MISS",
"MSRIndex": "0x3F7",
@@ -282,13 +220,10 @@
"PEBS": "1",
"PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x80",
"EventName": "ICACHE_16B.IFDATA_STALL",
"PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
@@ -297,8 +232,6 @@
},
{
"BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_HIT",
"SampleAfterValue": "200003",
@@ -306,8 +239,6 @@
},
{
"BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_MISS",
"SampleAfterValue": "200003",
@@ -315,8 +246,6 @@
},
{
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x83",
"EventName": "ICACHE_64B.IFTAG_STALL",
"SampleAfterValue": "200003",
@@ -324,8 +253,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
@@ -335,8 +262,6 @@
},
{
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
@@ -346,8 +271,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering 4 Uops",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
@@ -357,8 +280,6 @@
},
{
"BriefDescription": "Cycles MITE is delivering any Uop",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
@@ -368,8 +289,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
@@ -379,8 +298,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.",
@@ -389,8 +306,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
@@ -400,8 +315,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
@@ -410,8 +323,6 @@
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
@@ -421,8 +332,6 @@
},
{
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
@@ -432,8 +341,6 @@
},
{
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.",
@@ -442,8 +349,6 @@
},
{
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79",
@@ -454,8 +359,6 @@
},
{
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
@@ -464,8 +367,6 @@
},
{
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.",
@@ -474,8 +375,6 @@
},
{
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
@@ -485,8 +384,6 @@
},
{
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
@@ -496,8 +393,6 @@
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
@@ -507,8 +402,6 @@
},
{
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
@@ -518,8 +411,6 @@
},
{
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json b/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json
index 36042010d768..a00ad0aaf1ba 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_EVENTS",
"SampleAfterValue": "2000003",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_MEM",
"SampleAfterValue": "2000003",
@@ -50,8 +40,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
"PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
@@ -60,8 +48,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_TIMER",
"SampleAfterValue": "2000003",
@@ -69,8 +55,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
"SampleAfterValue": "2000003",
@@ -78,8 +62,6 @@
},
{
"BriefDescription": "Number of times an HLE execution successfully committed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.COMMIT",
"PublicDescription": "Number of times HLE commit succeeded.",
@@ -88,8 +70,6 @@
},
{
"BriefDescription": "Number of times an HLE execution started.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC8",
"EventName": "HLE_RETIRED.START",
"PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
@@ -98,8 +78,6 @@
},
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL089",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
@@ -109,8 +87,6 @@
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
@@ -119,13 +95,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
@@ -134,13 +107,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
@@ -149,13 +119,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
@@ -164,13 +131,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
@@ -179,13 +143,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
@@ -194,13 +155,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
@@ -209,13 +167,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"EventCode": "0xcd",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
@@ -224,4213 +179,3160 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS.REMOTE_HITM OCR.ALL_READS.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS.SNOOP_MISS OCR.ALL_READS.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS.SNOOP_NONE OCR.ALL_READS.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F840007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x840007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B8007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F900007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10100007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8100007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4100007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1100007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2100007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x900007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS.REMOTE_HITM OCR.ALL_RFO.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS OCR.ALL_RFO.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE OCR.ALL_RFO.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.ANY_SNOOP OCR.OTHER.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.HITM_OTHER_CORE OCR.OTHER.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC08000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC08000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B808000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Demand Data Read requests who miss L3 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB0",
"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
"PublicDescription": "Demand Data Read requests who miss L3 cache.",
@@ -4439,8 +3341,6 @@
},
{
"BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
@@ -4449,8 +3349,6 @@
},
{
"BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
"SampleAfterValue": "2000003",
@@ -4458,8 +3356,6 @@
},
{
"BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "6",
"EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
@@ -4468,4558 +3364,3506 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC0007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F840007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x840007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B8007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F900007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10100007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8100007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4100007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1100007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2100007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x900007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC08000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC08000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B808000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90008000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBC000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103C000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83C000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x43C000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x13C000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x83FC00100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x23C000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0xBC000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F84000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x404000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x104000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x204000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x84000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63B800100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F90000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1010000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x810000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x410000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x110000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x210000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "This event is deprecated. Refer to new event OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x90000100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
@@ -9029,8 +6873,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_EVENTS",
"PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
@@ -9039,8 +6881,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_MEM",
"PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
@@ -9049,8 +6889,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
"PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
@@ -9059,8 +6897,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_TIMER",
"SampleAfterValue": "2000003",
@@ -9068,8 +6904,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
"PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
@@ -9078,8 +6912,6 @@
},
{
"BriefDescription": "Number of times an RTM execution successfully committed",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.COMMIT",
"PublicDescription": "Number of times RTM commit succeeded.",
@@ -9088,8 +6920,6 @@
},
{
"BriefDescription": "Number of times an RTM execution started.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC9",
"EventName": "RTM_RETIRED.START",
"PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
@@ -9098,8 +6928,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003",
@@ -9107,8 +6935,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
@@ -9117,8 +6943,6 @@
},
{
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@@ -9127,8 +6951,6 @@
},
{
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4",
"PublicDescription": "RTM region detected inside HLE.",
@@ -9137,8 +6959,6 @@
},
{
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5",
"PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
@@ -9147,8 +6967,6 @@
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY",
"SampleAfterValue": "2000003",
@@ -9156,8 +6974,6 @@
},
{
"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"PublicDescription": "Number of times a TSX line had a cache conflict.",
@@ -9166,8 +6982,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@@ -9176,8 +6990,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@@ -9186,8 +6998,6 @@
},
{
"BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@@ -9196,8 +7006,6 @@
},
{
"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@@ -9206,8 +7014,6 @@
},
{
"BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"PublicDescription": "Number of times we could not allocate Lock Buffer.",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json
index 6baa338e72f1..3ab5e91a4c1c 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server michroarchtecture). This includes high current AVX 512-bit instructions.",
@@ -31,8 +25,6 @@
},
{
"BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x28",
"EventName": "CORE_POWER.THROTTLE",
"PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
@@ -41,8 +33,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE",
"SampleAfterValue": "2000003",
@@ -50,8 +40,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM",
"SampleAfterValue": "2000003",
@@ -59,8 +47,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE",
"SampleAfterValue": "2000003",
@@ -68,8 +54,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI",
"SampleAfterValue": "2000003",
@@ -77,8 +61,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE",
"SampleAfterValue": "2000003",
@@ -86,8 +68,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM",
"SampleAfterValue": "2000003",
@@ -95,8 +75,6 @@
},
{
"BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xEF",
"EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE",
"SampleAfterValue": "2000003",
@@ -104,8 +82,6 @@
},
{
"BriefDescription": "Number of hardware interrupts received by the processor.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCB",
"EventName": "HW_INTERRUPTS.RECEIVED",
"PublicDescription": "Counts the number of hardware interruptions received by the processor.",
@@ -114,8 +90,6 @@
},
{
"BriefDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xFE",
"EventName": "IDI_MISC.WB_DOWNGRADE",
"PublicDescription": "Counts number of cache lines that are dropped and not written back to L3 as they are deemed to be less likely to be reused shortly.",
@@ -124,8 +98,6 @@
},
{
"BriefDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xFE",
"EventName": "IDI_MISC.WB_UPGRADE",
"PublicDescription": "Counts number of cache lines that are allocated and written back to L3 with the intention that they are more likely to be reused shortly.",
@@ -134,1849 +106,1387 @@
},
{
"BriefDescription": "OCR.ALL_DATA_RD.ANY_RESPONSE have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020491",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020490",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.ANY_RESPONSE have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020120",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.ANY_RESPONSE have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x107F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F804007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x804007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1004007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F800207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10000207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x8000207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x4000207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x2000207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800207F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.ANY_RESPONSE have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand code reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020004",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts demand data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020001",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x18000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100408000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts any other requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80028000",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020400",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to L2) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020010",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020020",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020080",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80400100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80400100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100400100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F80020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x1000020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x800020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x400020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x100020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x200020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x80020100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
}
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json
index f085b9145952..64e1fe351333 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x14",
"EventName": "ARITH.DIVIDER_ACTIVE",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "All (macro) branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS",
@@ -33,8 +27,6 @@
},
{
"BriefDescription": "Conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
@@ -45,8 +37,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.COND_NTAKEN",
@@ -56,8 +46,6 @@
},
{
"BriefDescription": "Far branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
@@ -68,8 +56,6 @@
},
{
"BriefDescription": "Direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
@@ -80,8 +66,6 @@
},
{
"BriefDescription": "Return instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_RETURN",
@@ -92,8 +76,6 @@
},
{
"BriefDescription": "Taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
@@ -104,8 +86,6 @@
},
{
"BriefDescription": "Not taken branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091",
"EventCode": "0xC4",
"EventName": "BR_INST_RETIRED.NOT_TAKEN",
@@ -115,8 +95,6 @@
},
{
"BriefDescription": "All mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
@@ -124,8 +102,6 @@
},
{
"BriefDescription": "Mispredicted macro branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS",
"PEBS": "2",
@@ -135,8 +111,6 @@
},
{
"BriefDescription": "Mispredicted conditional branch instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"PEBS": "1",
@@ -146,8 +120,6 @@
},
{
"BriefDescription": "Mispredicted direct and indirect near call instructions retired.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"PEBS": "1",
@@ -157,8 +129,6 @@
},
{
"BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS": "1",
@@ -167,8 +137,6 @@
},
{
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC5",
"EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1",
@@ -178,8 +146,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "25003",
@@ -187,8 +153,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK",
"SampleAfterValue": "25003",
@@ -197,8 +161,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "25003",
@@ -206,8 +168,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue": "25003",
@@ -215,8 +175,6 @@
},
{
"BriefDescription": "Reference cycles when the core is not in halt state.",
- "Counter": "Fixed counter 2",
- "CounterHTOff": "Fixed counter 2",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue": "2000003",
@@ -224,8 +182,6 @@
},
{
"BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK",
"SampleAfterValue": "25003",
@@ -234,8 +190,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue": "25003",
@@ -243,8 +197,6 @@
},
{
"BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x3C",
@@ -254,8 +206,6 @@
},
{
"BriefDescription": "Core cycles when the thread is not in halt state",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue": "2000003",
@@ -264,16 +214,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "Fixed counter 1",
- "CounterHTOff": "Fixed counter 1",
"EventName": "CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "Thread cycles when thread is not in halt state",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
@@ -282,16 +228,12 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x3C",
"EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue": "2000003"
},
{
"BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "8",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
@@ -300,8 +242,6 @@
},
{
"BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
@@ -310,8 +250,6 @@
},
{
"BriefDescription": "Cycles while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
@@ -320,8 +258,6 @@
},
{
"BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "12",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
@@ -330,8 +266,6 @@
},
{
"BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "5",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
@@ -340,8 +274,6 @@
},
{
"BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"CounterMask": "20",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
@@ -350,8 +282,6 @@
},
{
"BriefDescription": "Total execution stalls.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA3",
"EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
@@ -360,8 +290,6 @@
},
{
"BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
@@ -370,8 +298,6 @@
},
{
"BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
"PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -380,8 +306,6 @@
},
{
"BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
"PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -390,8 +314,6 @@
},
{
"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
"PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
@@ -400,8 +322,6 @@
},
{
"BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
"SampleAfterValue": "2000003",
@@ -409,8 +329,6 @@
},
{
"BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA6",
"EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
"PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
@@ -419,8 +337,6 @@
},
{
"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x87",
"EventName": "ILD_STALL.LCP",
"PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
@@ -429,8 +345,6 @@
},
{
"BriefDescription": "Instruction decoders utilized in a cycle",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x55",
"EventName": "INST_DECODED.DECODERS",
"PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
@@ -439,8 +353,6 @@
},
{
"BriefDescription": "Instructions retired from execution.",
- "Counter": "Fixed counter 0",
- "CounterHTOff": "Fixed counter 0",
"EventName": "INST_RETIRED.ANY",
"PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
"SampleAfterValue": "2000003",
@@ -448,8 +360,6 @@
},
{
"BriefDescription": "Number of instructions retired. General Counter - architectural event",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.ANY_P",
@@ -458,8 +368,6 @@
},
{
"BriefDescription": "Number of all retired NOP instructions.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.NOP",
@@ -469,8 +377,6 @@
},
{
"BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
- "Counter": "1",
- "CounterHTOff": "1",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
"EventName": "INST_RETIRED.PREC_DIST",
@@ -481,8 +387,6 @@
},
{
"BriefDescription": "Number of cycles using always true condition applied to PEBS instructions retired event.",
- "Counter": "0,2,3",
- "CounterHTOff": "0,2,3",
"CounterMask": "10",
"Errata": "SKL091, SKL044",
"EventCode": "0xC0",
@@ -495,8 +399,6 @@
},
{
"BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
"SampleAfterValue": "2000003",
@@ -504,8 +406,6 @@
},
{
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES",
"PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
@@ -515,8 +415,6 @@
{
"AnyThread": "1",
"BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0D",
"EventName": "INT_MISC.RECOVERY_CYCLES_ANY",
"SampleAfterValue": "2000003",
@@ -524,8 +422,6 @@
},
{
"BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.NO_SR",
"PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
@@ -534,8 +430,6 @@
},
{
"BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x03",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
@@ -544,8 +438,6 @@
},
{
"BriefDescription": "False dependencies in MOB due to partial compare on address.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x07",
"EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
@@ -554,8 +446,6 @@
},
{
"BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4C",
"EventName": "LOAD_HIT_PRE.SW_PF",
"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
@@ -564,8 +454,6 @@
},
{
"BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_4_UOPS",
@@ -575,8 +463,6 @@
},
{
"BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xA8",
"EventName": "LSD.CYCLES_ACTIVE",
@@ -586,8 +472,6 @@
},
{
"BriefDescription": "Number of Uops delivered by the LSD.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA8",
"EventName": "LSD.UOPS",
"PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
@@ -596,8 +480,6 @@
},
{
"BriefDescription": "Number of machine clears (nukes) of any type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0xC3",
@@ -607,8 +489,6 @@
},
{
"BriefDescription": "Self-modifying code (SMC) detected.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
"PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
@@ -617,8 +497,6 @@
},
{
"BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.ANY",
"SampleAfterValue": "100003",
@@ -626,8 +504,6 @@
},
{
"BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x59",
"EventName": "PARTIAL_RAT_STALLS.SCOREBOARD",
"PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.",
@@ -636,8 +512,6 @@
},
{
"BriefDescription": "Resource-related stall cycles",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xa2",
"EventName": "RESOURCE_STALLS.ANY",
"PublicDescription": "Counts resource-related stall cycles.",
@@ -646,8 +520,6 @@
},
{
"BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA2",
"EventName": "RESOURCE_STALLS.SB",
"PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
@@ -656,8 +528,6 @@
},
{
"BriefDescription": "Increments whenever there is an update to the LBR array.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
@@ -666,8 +536,6 @@
},
{
"BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCC",
"EventName": "ROB_MISC_EVENTS.PAUSE_INST",
"SampleAfterValue": "2000003",
@@ -675,8 +543,6 @@
},
{
"BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5E",
"EventName": "RS_EVENTS.EMPTY_CYCLES",
"PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
@@ -685,8 +551,6 @@
},
{
"BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5E",
@@ -698,8 +562,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 0",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_0",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
@@ -708,8 +570,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 1",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_1",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
@@ -718,8 +578,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 2",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_2",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 2.",
@@ -728,8 +586,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_3",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 3.",
@@ -738,8 +594,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 4",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_4",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 4.",
@@ -748,8 +602,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 5",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_5",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
@@ -758,8 +610,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 6",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_6",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
@@ -768,8 +618,6 @@
},
{
"BriefDescription": "Cycles per thread when uops are executed in port 7",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xA1",
"EventName": "UOPS_DISPATCHED_PORT.PORT_7",
"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 7.",
@@ -778,8 +626,6 @@
},
{
"BriefDescription": "Number of uops executed on the core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE",
"PublicDescription": "Number of uops executed from any thread.",
@@ -788,8 +634,6 @@
},
{
"BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
@@ -798,8 +642,6 @@
},
{
"BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
@@ -808,8 +650,6 @@
},
{
"BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
@@ -818,8 +658,6 @@
},
{
"BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
@@ -828,8 +666,6 @@
},
{
"BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE",
@@ -839,8 +675,6 @@
},
{
"BriefDescription": "Cycles where at least 1 uop was executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
@@ -850,8 +684,6 @@
},
{
"BriefDescription": "Cycles where at least 2 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "2",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC",
@@ -861,8 +693,6 @@
},
{
"BriefDescription": "Cycles where at least 3 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "3",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC",
@@ -872,8 +702,6 @@
},
{
"BriefDescription": "Cycles where at least 4 uops were executed per-thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC",
@@ -883,8 +711,6 @@
},
{
"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.STALL_CYCLES",
@@ -895,8 +721,6 @@
},
{
"BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.THREAD",
"PublicDescription": "Number of uops to be executed per-thread each cycle.",
@@ -905,8 +729,6 @@
},
{
"BriefDescription": "Counts the number of x87 uops dispatched.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xB1",
"EventName": "UOPS_EXECUTED.X87",
"PublicDescription": "Counts the number of x87 uops executed.",
@@ -915,8 +737,6 @@
},
{
"BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.ANY",
"PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
@@ -925,8 +745,6 @@
},
{
"BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.SLOW_LEA",
"SampleAfterValue": "2000003",
@@ -934,8 +752,6 @@
},
{
"BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
@@ -946,8 +762,6 @@
},
{
"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x0E",
"EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH",
"PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.",
@@ -956,8 +770,6 @@
},
{
"BriefDescription": "Number of macro-fused uops retired. (non precise)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc2",
"EventName": "UOPS_RETIRED.MACRO_FUSED",
"PublicDescription": "Counts the number of macro-fused uops retired. (non precise)",
@@ -966,8 +778,6 @@
},
{
"BriefDescription": "Retirement slots used.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"PublicDescription": "Counts the retirement slots used.",
@@ -976,8 +786,6 @@
},
{
"BriefDescription": "Cycles without actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
@@ -988,8 +796,6 @@
},
{
"BriefDescription": "Cycles with less than 10 actually retired uops.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json
index 326b674045c6..70a2c0ff8dfd 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json
@@ -1,223 +1,270 @@
[
+ {
+ "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
+ "EventCode": "0x4",
+ "EventName": "LLC_MISSES.MEM_READ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read. This event includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x3",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
+ "EventCode": "0x4",
+ "EventName": "LLC_MISSES.MEM_WRITE",
+ "PerPkg": "1",
+ "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0xc",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "DRAM Activate Count; Activate due to Bypass",
+ "EventCode": "0x1",
+ "EventName": "UNC_M_ACT_COUNT.BYP",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0x8",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "DRAM Activate Count; Activate due to Read",
+ "EventCode": "0x1",
+ "EventName": "UNC_M_ACT_COUNT.RD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
+ "UMask": "0x1",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "DRAM Page Activate commands sent due to a write request",
- "Counter": "0,1,2,3",
"EventCode": "0x1",
"EventName": "UNC_M_ACT_COUNT.WR",
"PerPkg": "1",
+ "PublicDescription": "Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller). Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command.",
"UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_REG",
+ "BriefDescription": "ACT command issued by 2 cycle bypass",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M_BYP_CMDS.ACT",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Underfill Read CAS Commands issued",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
+ "BriefDescription": "CAS command issued by 2 cycle bypass",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M_BYP_CMDS.CAS",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "PRE command issued by 2 cycle bypass",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M_BYP_CMDS.PRE",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "All DRAM CAS Commands issued",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+ "UMask": "0xf",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "All DRAM Read CAS Commands issued (including underfills)",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_M_CAS_COUNT.RD",
"PerPkg": "1",
+ "PublicDescription": "Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read. This event includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
"UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode",
"EventCode": "0x4",
- "EventName": "LLC_MISSES.MEM_READ",
+ "EventName": "UNC_M_CAS_COUNT.RD_ISOCH",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x3",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
- "Counter": "0,1,2,3",
+ "BriefDescription": "All DRAM Read CAS Commands issued (does not include underfills)",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR_WMM",
+ "EventName": "UNC_M_CAS_COUNT.RD_REG",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read. This event only counts regular reads and does not includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM Write CAS commands issued",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR",
+ "EventName": "UNC_M_CAS_COUNT.RD_RMM",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM Underfill Read CAS Commands issued",
"EventCode": "0x4",
- "EventName": "LLC_MISSES.MEM_WRITE",
+ "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0xC",
+ "PublicDescription": "Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads. Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request).",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "All DRAM CAS Commands issued",
- "Counter": "0,1,2,3",
+ "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM",
"EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.ALL",
+ "EventName": "UNC_M_CAS_COUNT.RD_WMM",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "Memory controller clock ticks",
- "Counter": "0,1,2,3",
- "EventName": "UNC_M_CLOCKTICKS",
+ "BriefDescription": "All DRAM Write CAS commands issued",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.WR",
"PerPkg": "1",
+ "PublicDescription": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not.",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode+C37",
- "Counter": "0,1,2,3",
- "EventCode": "0x85",
- "EventName": "UNC_M_POWER_CHANNEL_PPD",
- "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100.",
- "MetricName": "power_channel_ppd %",
+ "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.WR_ISOCH",
"PerPkg": "1",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles Memory is in self refresh power mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x43",
- "EventName": "UNC_M_POWER_SELF_REFRESH",
- "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100.",
- "MetricName": "power_self_refresh %",
+ "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.WR_RMM",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of Opportunistic DRAM Write CAS commands issued on this channel while in Read-Major-Mode.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Pre-charges due to page misses",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode",
+ "EventCode": "0x4",
+ "EventName": "UNC_M_CAS_COUNT.WR_WMM",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Pre-charge for reads",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_M_PRE_COUNT.RD",
+ "BriefDescription": "Memory controller clock ticks",
+ "EventName": "UNC_M_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Counts clockticks of the fixed frequency clock of the memory controller using one of the programmable counters.",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x10",
- "EventName": "UNC_M_RPQ_INSERTS",
+ "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
+ "EventCode": "0xff",
+ "EventName": "UNC_M_CLOCKTICKS_F",
"PerPkg": "1",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M_RPQ_OCCUPANCY",
+ "BriefDescription": "DRAM Precharge All Commands",
+ "EventCode": "0x6",
+ "EventName": "UNC_M_DRAM_PRE_ALL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times that the precharge all command was sent.",
"Unit": "iMC"
},
{
- "BriefDescription": "All hits to Near Memory(DRAM cache) in Memory Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0xD3",
- "EventName": "UNC_M_TAGCHK.HIT",
+ "BriefDescription": "ECC Correctable Errors",
+ "EventCode": "0x9",
+ "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.",
"Unit": "iMC"
},
{
- "BriefDescription": "All Clean line misses to Near Memory(DRAM cache) in Memory Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0xD3",
- "EventName": "UNC_M_TAGCHK.MISS_CLEAN",
+ "BriefDescription": "UNC_M_MAJMODE2.DRAM_CYC",
+ "EventCode": "0xED",
+ "EventName": "UNC_M_MAJMODE2.DRAM_CYC",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "All dirty line misses to Near Memory(DRAM cache) in Memory Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0xD3",
- "EventName": "UNC_M_TAGCHK.MISS_DIRTY",
+ "BriefDescription": "UNC_M_MAJMODE2.DRAM_ENTER",
+ "EventCode": "0xED",
+ "EventName": "UNC_M_MAJMODE2.DRAM_ENTER",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_M_WPQ_INSERTS",
+ "BriefDescription": "UNC_M_MAJMODE2.PMM_CYC",
+ "EventCode": "0xED",
+ "EventName": "UNC_M_MAJMODE2.PMM_CYC",
"PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x81",
- "EventName": "UNC_M_WPQ_OCCUPANCY",
+ "BriefDescription": "UNC_M_MAJMODE2.PMM_ENTER",
+ "EventCode": "0xED",
+ "EventName": "UNC_M_MAJMODE2.PMM_ENTER",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory",
- "Counter": "0,1,2,3",
- "EventCode": "0xE0",
- "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
+ "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
+ "EventCode": "0x7",
+ "EventName": "UNC_M_MAJOR_MODES.ISOCH",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time. These major modes are used whenever there is an ISOCH txn in the memory controller. In these mode, only ISOCH transactions are processed.",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all",
- "Counter": "0,1,2,3",
- "EventCode": "0xE0",
- "EventName": "UNC_M_PMM_READ_LATENCY",
- "MetricExpr": "UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS",
- "MetricName": "UNC_M_PMM_READ_LATENCY",
+ "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
+ "EventCode": "0x7",
+ "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
"PerPkg": "1",
- "ScaleUnit": "6000000000ns",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads. Regular reads and writes are blocked and only underfill reads will be processed.",
+ "UMask": "0x4",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
+ "EventCode": "0x7",
+ "EventName": "UNC_M_MAJOR_MODES.READ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes.",
"UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
- "Counter": "0,1,2,3",
- "EventCode": "0xE3",
- "EventName": "UNC_M_PMM_RPQ_INSERTS",
+ "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
+ "EventCode": "0x7",
+ "EventName": "UNC_M_MAJOR_MODES.WRITE",
"PerPkg": "1",
+ "PublicDescription": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads. This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth.",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m_pmm_rpq_inserts",
- "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M_PMM_BANDWIDTH.READ",
"PerPkg": "1",
@@ -226,7 +273,6 @@
},
{
"BriefDescription": "Intel Optane DC persistent memory bandwidth total (MB/sec). Derived from unc_m_pmm_rpq_inserts",
- "Counter": "0,1,2,3",
"EventCode": "0xE3",
"EventName": "UNC_M_PMM_BANDWIDTH.TOTAL",
"MetricExpr": "UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS",
@@ -235,426 +281,544 @@
"ScaleUnit": "6.103515625E-5MB/sec",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts",
+ "EventCode": "0xE7",
+ "EventName": "UNC_M_PMM_BANDWIDTH.WRITE",
+ "PerPkg": "1",
+ "ScaleUnit": "6.103515625E-5MB/sec",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "All commands for Intel Optane DC persistent memory",
- "Counter": "0,1,2,3",
"EventCode": "0xEA",
"EventName": "UNC_M_PMM_CMD1.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "Misc Commands (error, flow ACKs)",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.MISC",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Misc GNTs",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.MISC_GNT",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Regular reads(RPQ) commands for Intel Optane DC persistent memory",
- "Counter": "0,1,2,3",
"EventCode": "0xEA",
"EventName": "UNC_M_PMM_CMD1.RD",
"PerPkg": "1",
+ "PublicDescription": "All Reads - RPQ or Ufill",
"UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Write commands for Intel Optane DC persistent memory",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RPQ GNTs",
"EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.WR",
+ "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "Underfill read commands for Intel Optane DC persistent memory",
- "Counter": "0,1,2,3",
"EventCode": "0xEA",
"EventName": "UNC_M_PMM_CMD1.UFILL_RD",
"PerPkg": "1",
+ "PublicDescription": "Underfill reads",
"UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
- "Counter": "0,1,2,3",
- "EventCode": "0xE7",
- "EventName": "UNC_M_PMM_WPQ_INSERTS",
+ "BriefDescription": "Underfill GNTs",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS",
"PerPkg": "1",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "Intel Optane DC persistent memory bandwidth write (MB/sec). Derived from unc_m_pmm_wpq_inserts",
- "Counter": "0,1,2,3",
- "EventCode": "0xE7",
- "EventName": "UNC_M_PMM_BANDWIDTH.WRITE",
+ "BriefDescription": "Write commands for Intel Optane DC persistent memory",
+ "EventCode": "0xEA",
+ "EventName": "UNC_M_PMM_CMD1.WR",
"PerPkg": "1",
- "ScaleUnit": "6.103515625E-5MB/sec",
+ "PublicDescription": "Writes",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory",
- "Counter": "0,1,2,3",
- "EventCode": "0xE4",
- "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
+ "BriefDescription": "Expected No data packet (ERID matched NDP encoding)",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.NODATA_EXP",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Activate Count; Activate due to Read",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_M_ACT_COUNT.RD",
+ "BriefDescription": "Unexpected No data packet (ERID matched a Read, but data was a NDP)",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Opportunistic Reads",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.OPP_RD",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Activate Count; Activate due to Bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_M_ACT_COUNT.BYP",
+ "BriefDescription": "PMM ECC Errors",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "PMM ERID detectable parity error",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Read Requests - Slot 0",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "ACT command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M_BYP_CMDS.ACT",
+ "BriefDescription": "Read Requests - Slot 1",
+ "EventCode": "0xEB",
+ "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "PMM Major Mode; Cycles PMM is in Partial Write Major Mode",
+ "EventCode": "0xEC",
+ "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_CYC",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "PMM Major Mode",
+ "EventCode": "0xEC",
+ "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_ENTER",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "PMM Major Mode",
+ "EventCode": "0xEC",
+ "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_EXIT",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "PMM Major Mode; Cycles PMM is in Read Major Mode",
+ "EventCode": "0xEC",
+ "EventName": "UNC_M_PMM_MAJMODE1.RD_CYC",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "CAS command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M_BYP_CMDS.CAS",
+ "BriefDescription": "PMM Major Mode; Cycles PMM is in Write Major Mode",
+ "EventCode": "0xEC",
+ "EventName": "UNC_M_PMM_MAJMODE1.WR_CYC",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "PRE command issued by 2 cycle bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M_BYP_CMDS.PRE",
+ "BriefDescription": "Intel Optane DC persistent memory read latency (ns). Derived from unc_m_pmm_rpq_occupancy.all",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M_PMM_READ_LATENCY",
+ "MetricExpr": "UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS / UNC_M_CLOCKTICKS",
+ "MetricName": "UNC_M_PMM_READ_LATENCY",
"PerPkg": "1",
- "UMask": "0x4",
+ "ScaleUnit": "6000000000ns",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR_RMM",
+ "BriefDescription": "PMM Read Queue Cycles Full",
+ "EventCode": "0xE2",
+ "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL",
"PerPkg": "1",
- "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in WMM",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_WMM",
+ "BriefDescription": "PMM Read Queue Cycles Not Empty",
+ "EventCode": "0xE1",
+ "EventName": "UNC_M_PMM_RPQ_CYCLES_NE",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in RMM",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_RMM",
+ "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
+ "EventCode": "0xE3",
+ "EventName": "UNC_M_PMM_RPQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Read ISOCH Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.RD_ISOCH",
+ "BriefDescription": "Read Pending Queue Occupancy of all read requests for Intel Optane DC persistent memory",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; Read CAS issued in Write ISOCH Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M_CAS_COUNT.WR_ISOCH",
+ "BriefDescription": "PMM Occupancy",
+ "EventCode": "0xE0",
+ "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge All Commands",
- "Counter": "0,1,2,3",
- "EventCode": "0x6",
- "EventName": "UNC_M_DRAM_PRE_ALL",
+ "BriefDescription": "PMM Write Queue Cycles Full",
+ "EventCode": "0xE6",
+ "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL",
"PerPkg": "1",
"Unit": "iMC"
},
{
- "BriefDescription": "ECC Correctable Errors",
- "Counter": "0,1,2,3",
- "EventCode": "0x9",
- "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS",
+ "BriefDescription": "PMM Write Queue Cycles Not Empty",
+ "EventCode": "0xE5",
+ "EventName": "UNC_M_PMM_WPQ_CYCLES_NE",
"PerPkg": "1",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Read Major Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.READ",
+ "BriefDescription": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
+ "EventCode": "0xE7",
+ "EventName": "UNC_M_PMM_WPQ_INSERTS",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory",
+ "EventCode": "0xE4",
+ "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Write Major Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.WRITE",
+ "BriefDescription": "PMM Occupancy",
+ "EventCode": "0xE4",
+ "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Partial Major Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.PARTIAL",
+ "BriefDescription": "PMM Occupancy",
+ "EventCode": "0xE4",
+ "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x7",
- "EventName": "UNC_M_MAJOR_MODES.ISOCH",
+ "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT",
+ "EventCode": "0xE8",
+ "EventName": "UNC_M_PMM_WPQ_PCOMMIT",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT_CYC",
+ "EventCode": "0xE9",
+ "EventName": "UNC_M_PMM_WPQ_PCOMMIT_CYC",
"PerPkg": "1",
- "UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Channel DLLOFF Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x84",
"EventName": "UNC_M_POWER_CHANNEL_DLLOFF",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode+C37",
+ "EventCode": "0x85",
+ "EventName": "UNC_M_POWER_CHANNEL_PPD",
+ "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100",
+ "MetricName": "power_channel_ppd",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of.",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK0",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK2",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK3",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK4",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK5",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK6",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x83",
"EventName": "UNC_M_POWER_CKE_CYCLES.RANK7",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Critical Throttle Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x86",
"EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event.",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_POWER_PCU_THROTTLING",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_M_POWER_PCU_THROTTLING",
"PerPkg": "1",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "Cycles Memory is in self refresh power mode",
+ "EventCode": "0x43",
+ "EventName": "UNC_M_POWER_SELF_REFRESH",
+ "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100",
+ "MetricName": "power_self_refresh",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the iMC (memory controller) is in self-refresh and has a clock. This happens in some ACPI CPU package C-states for the sleep levels. For example, the PCU (Power Control Unit) may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Intel? Dynamic Power Technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x40",
"Unit": "iMC"
},
{
"BriefDescription": "Throttle Cycles for Rank 0; DIMM ID",
- "Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
"UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Read Preemption Count; Read over Read Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read.",
"UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Read Preemption Count; Read over Write Preemption",
- "Counter": "0,1,2,3",
"EventCode": "0x8",
"EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write.",
"UMask": "0x2",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
+ "EventCode": "0x2",
+ "EventName": "UNC_M_PRE_COUNT.BYP",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
+ "UMask": "0x10",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "DRAM Precharge commands.; Precharge due to timer expiration",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring. This does not include implicit precharge commands sent in auto-precharge mode.",
"UMask": "0x2",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "Pre-charges due to page misses",
+ "EventCode": "0x2",
+ "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of explicit DRAM Precharge commands sent on this channel as a result of a DRAM page miss. This does not include the implicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include Precharge commands sent as a result of a page close counter expiration.",
+ "UMask": "0x1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Pre-charge for reads",
+ "EventCode": "0x2",
+ "EventName": "UNC_M_PRE_COUNT.RD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of explicit DRAM Precharge commands issued on a per channel basis due to a read, so as to close the previous DRAM page, before opening the requested page.",
+ "UMask": "0x4",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Pre-charge for writes",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_M_PRE_COUNT.WR",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of DRAM Precharge commands sent on this channel.",
"UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "DRAM Precharge commands.; Precharge due to bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_M_PRE_COUNT.BYP",
+ "BriefDescription": "Read CAS issued with HIGH priority",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Read CAS issued with LOW priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.LOW",
"PerPkg": "1",
@@ -663,7 +827,6 @@
},
{
"BriefDescription": "Read CAS issued with MEDIUM priority",
- "Counter": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UNC_M_RD_CAS_PRIO.MED",
"PerPkg": "1",
@@ -671,26 +834,23 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Read CAS issued with HIGH priority",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
"EventCode": "0xA0",
- "EventName": "UNC_M_RD_CAS_PRIO.HIGH",
+ "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority (starved)",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_M_RD_CAS_PRIO.PANIC",
+ "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK0",
"PerPkg": "1",
@@ -698,7 +858,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANK1",
"PerPkg": "1",
@@ -706,143 +865,119 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
"PerPkg": "1",
- "UMask": "0x3",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
"PerPkg": "1",
- "UMask": "0x5",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
- "PerPkg": "1",
- "UMask": "0x6",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
"PerPkg": "1",
- "UMask": "0x7",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 2",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK2",
"PerPkg": "1",
- "UMask": "0x9",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 3",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK3",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 4",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK4",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 5",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK5",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 6",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK6",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 7",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK7",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 8",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK8",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 0; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 0; Bank 9",
"EventCode": "0xB0",
- "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK0.BANK9",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG0",
"PerPkg": "1",
@@ -851,7 +986,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG1",
"PerPkg": "1",
@@ -860,7 +994,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG2",
"PerPkg": "1",
@@ -869,7 +1002,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB0",
"EventName": "UNC_M_RD_CAS_RANK0.BANKG3",
"PerPkg": "1",
@@ -877,160 +1009,142 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
"PerPkg": "1",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 0",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK0",
"PerPkg": "1",
- "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 1",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK1",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
"PerPkg": "1",
- "UMask": "0x3",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 12",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK12",
"PerPkg": "1",
- "UMask": "0x5",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 13",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK13",
"PerPkg": "1",
- "UMask": "0x6",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
"PerPkg": "1",
- "UMask": "0x7",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 2",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK2",
"PerPkg": "1",
- "UMask": "0x9",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 3",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK3",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 4",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK4",
"PerPkg": "1",
- "UMask": "0xB",
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{
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+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 5",
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+ "EventName": "UNC_M_RD_CAS_RANK1.BANK5",
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+ "UMask": "0x5",
"Unit": "iMC"
},
{
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- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 6",
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+ "EventName": "UNC_M_RD_CAS_RANK1.BANK6",
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+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 7",
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- "EventName": "UNC_M_RD_CAS_RANK1.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK7",
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+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 8",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK8",
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+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 1; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 1; Bank 9",
"EventCode": "0xB1",
- "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK1.BANK9",
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+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks 0-3)",
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"EventName": "UNC_M_RD_CAS_RANK1.BANKG0",
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@@ -1039,7 +1153,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK1.BANKG1",
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@@ -1048,7 +1161,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK1.BANKG2",
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@@ -1057,7 +1169,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK1.BANKG3",
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@@ -1065,160 +1176,142 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; All Banks",
"EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS",
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+ "UMask": "0x10",
"Unit": "iMC"
},
{
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- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 0",
"EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK0",
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- "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 1",
"EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK1",
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+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 10",
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- "EventName": "UNC_M_RD_CAS_RANK2.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK10",
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- "UMask": "0x3",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 4",
- "Counter": "0,1,2,3",
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- "EventName": "UNC_M_RD_CAS_RANK2.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK11",
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- "UMask": "0x4",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 12",
"EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK12",
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- "UMask": "0x5",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 13",
"EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK13",
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- "UMask": "0x6",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 7",
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+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 14",
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- "EventName": "UNC_M_RD_CAS_RANK2.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK14",
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+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 15",
"EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK15",
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- "UMask": "0x8",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 2",
"EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK9",
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+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 10",
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+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 3",
"EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK3",
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+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 11",
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+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 4",
"EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK4",
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- "UMask": "0xB",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 5",
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- "EventName": "UNC_M_RD_CAS_RANK2.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK5",
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- "UMask": "0xC",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 6",
"EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK6",
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- "UMask": "0xD",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 7",
"EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK7",
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- "UMask": "0xE",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 8",
"EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK8",
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- "UMask": "0xF",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 2; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 2; Bank 9",
"EventCode": "0xB2",
- "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK2.BANK9",
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- "UMask": "0x10",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 2; Bank Group 0 (Banks 0-3)",
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"EventCode": "0xB2",
"EventName": "UNC_M_RD_CAS_RANK2.BANKG0",
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@@ -1227,7 +1320,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK2.BANKG1",
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@@ -1236,7 +1328,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK2.BANKG2",
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@@ -1245,16 +1336,22 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK2.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "RD_CAS Access to Rank 3; All Banks",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANK0",
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@@ -1262,7 +1359,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK3.BANK1",
"PerPkg": "1",
@@ -1270,143 +1366,119 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 10",
"EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK10",
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- "UMask": "0x2",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 11",
"EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK11",
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- "UMask": "0x3",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK4",
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- "UMask": "0x4",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 12",
"EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK12",
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- "UMask": "0x5",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 13",
"EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK13",
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- "UMask": "0x6",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 14",
"EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK14",
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+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 15",
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- "EventName": "UNC_M_RD_CAS_RANK3.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK15",
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+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 2",
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- "EventName": "UNC_M_RD_CAS_RANK3.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK2",
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+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 3",
"EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK3",
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- "UMask": "0xA",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 4",
"EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK4",
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- "UMask": "0xB",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 12",
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+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 5",
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- "EventName": "UNC_M_RD_CAS_RANK3.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK5",
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- "UMask": "0xC",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 6",
"EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK6",
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+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 7",
"EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK7",
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- "UMask": "0xE",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 8",
"EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK8",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 3; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 3; Bank 9",
"EventCode": "0xB3",
- "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK3.BANK9",
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- "UMask": "0x10",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANKG0",
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@@ -1415,7 +1487,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks 4-7)",
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"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANKG1",
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@@ -1424,7 +1495,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANKG2",
"PerPkg": "1",
@@ -1433,7 +1503,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks 12-15)",
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"EventCode": "0xB3",
"EventName": "UNC_M_RD_CAS_RANK3.BANKG3",
"PerPkg": "1",
@@ -1441,160 +1510,142 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
"PerPkg": "1",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 0",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK0",
"PerPkg": "1",
- "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 1",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK1",
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- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 10",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK10",
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{
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},
{
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},
{
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},
{
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+ "UMask": "0x4",
"Unit": "iMC"
},
{
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+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 5",
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+ "EventName": "UNC_M_RD_CAS_RANK4.BANK5",
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+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 6",
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+ "EventName": "UNC_M_RD_CAS_RANK4.BANK6",
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+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 7",
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+ "EventName": "UNC_M_RD_CAS_RANK4.BANK7",
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+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 8",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK8",
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+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 4; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 4; Bank 9",
"EventCode": "0xB4",
- "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK4.BANK9",
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+ "UMask": "0x9",
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},
{
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"EventName": "UNC_M_RD_CAS_RANK4.BANKG0",
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@@ -1603,7 +1654,6 @@
},
{
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@@ -1612,7 +1662,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK4.BANKG2",
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@@ -1621,7 +1670,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK4.BANKG3",
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@@ -1629,160 +1677,142 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
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+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 0",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK0",
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- "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 1",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK1",
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+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
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+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
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- "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK11",
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- "UMask": "0x4",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
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- "UMask": "0x5",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
- "Counter": "0,1,2,3",
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- "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
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- "UMask": "0x6",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
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- "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
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+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
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+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
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- "EventName": "UNC_M_RD_CAS_RANK5.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
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+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 2",
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- "EventName": "UNC_M_RD_CAS_RANK5.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK2",
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+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 3",
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- "EventName": "UNC_M_RD_CAS_RANK5.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK3",
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+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 11",
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+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 4",
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+ "EventName": "UNC_M_RD_CAS_RANK5.BANK4",
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+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 5",
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- "EventName": "UNC_M_RD_CAS_RANK5.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK5",
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- "UMask": "0xC",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 6",
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- "EventName": "UNC_M_RD_CAS_RANK5.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK6",
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+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 7",
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- "EventName": "UNC_M_RD_CAS_RANK5.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK7",
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- "UMask": "0xE",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 8",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK8",
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- "UMask": "0xF",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 5; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 5; Bank 9",
"EventCode": "0xB5",
- "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK5.BANK9",
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- "UMask": "0x10",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks 0-3)",
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"EventName": "UNC_M_RD_CAS_RANK5.BANKG0",
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@@ -1791,7 +1821,6 @@
},
{
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@@ -1800,7 +1829,6 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK5.BANKG2",
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@@ -1809,16 +1837,22 @@
},
{
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"EventName": "UNC_M_RD_CAS_RANK5.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
+ "EventCode": "0xB6",
+ "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank 0",
- "Counter": "0,1,2,3",
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"EventName": "UNC_M_RD_CAS_RANK6.BANK0",
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@@ -1826,7 +1860,6 @@
},
{
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@@ -1834,143 +1867,119 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
"EventCode": "0xB6",
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- "Counter": "0,1,2,3",
- "EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
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+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
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- "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK11",
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+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
- "Counter": "0,1,2,3",
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+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
- "Counter": "0,1,2,3",
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+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
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+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
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+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
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+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 3",
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- "EventName": "UNC_M_RD_CAS_RANK6.BANK10",
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- "UMask": "0xA",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 4",
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+ "EventName": "UNC_M_RD_CAS_RANK6.BANK4",
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+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 5",
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- "UMask": "0xC",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 6",
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- "EventName": "UNC_M_RD_CAS_RANK6.BANK13",
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+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 7",
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+ "EventName": "UNC_M_RD_CAS_RANK6.BANK7",
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+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 8",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK8",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 6; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 6; Bank 9",
"EventCode": "0xB6",
- "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK6.BANK9",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG0",
"PerPkg": "1",
@@ -1979,7 +1988,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG1",
"PerPkg": "1",
@@ -1988,7 +1996,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG2",
"PerPkg": "1",
@@ -1997,7 +2004,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB6",
"EventName": "UNC_M_RD_CAS_RANK6.BANKG3",
"PerPkg": "1",
@@ -2005,160 +2011,142 @@
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
+ "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
"PerPkg": "1",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 0",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK0",
"PerPkg": "1",
- "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 1",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK1",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
"PerPkg": "1",
- "UMask": "0x3",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
"PerPkg": "1",
- "UMask": "0x5",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
"PerPkg": "1",
- "UMask": "0x6",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
"PerPkg": "1",
- "UMask": "0x7",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 2",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK2",
"PerPkg": "1",
- "UMask": "0x9",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 3",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK10",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK3",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0x3",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 4",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK11",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK4",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 5",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK12",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK5",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0x5",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 6",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK13",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK6",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0x6",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 14",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 7",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK14",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK7",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0x7",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; Bank 15",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 8",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.BANK15",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK8",
"PerPkg": "1",
- "UMask": "0xF",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "RD_CAS Access to Rank 7; All Banks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "RD_CAS Access to Rank 7; Bank 9",
"EventCode": "0xB7",
- "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS",
+ "EventName": "UNC_M_RD_CAS_RANK7.BANK9",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x9",
"Unit": "iMC"
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG0",
"PerPkg": "1",
@@ -2167,7 +2155,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG1",
"PerPkg": "1",
@@ -2176,7 +2163,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG2",
"PerPkg": "1",
@@ -2185,7 +2171,6 @@
},
{
"BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xB7",
"EventName": "UNC_M_RD_CAS_RANK7.BANKG3",
"PerPkg": "1",
@@ -2194,59 +2179,54 @@
},
{
"BriefDescription": "Read Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "UNC_M_RPQ_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the Read Pending Queue is full. When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead. We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM. This event only tracks non-ISOC queue entries.",
"Unit": "iMC"
},
{
"BriefDescription": "Read Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x11",
"EventName": "UNC_M_RPQ_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses; Read Accepts",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS",
+ "BriefDescription": "Read Pending Queue Allocations",
+ "EventCode": "0x10",
+ "EventName": "UNC_M_RPQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Counts the number of read requests allocated into the Read Pending Queue (RPQ). This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. The requests deallocate after the read CAS command has been issued to DRAM. This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ.",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses; Read Rejects",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS",
+ "BriefDescription": "Read Pending Queue Occupancy",
+ "EventCode": "0x80",
+ "EventName": "UNC_M_RPQ_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Counts the number of entries in the Read Pending Queue (RPQ) at each cycle. This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory.",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses; NM read completions",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Scoreboard Accesses; Write Accepts",
"EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS",
+ "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses; NM write completions",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Scoreboard Accesses; Write Rejects",
"EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS",
+ "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Accesses; FM read completions",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS",
"PerPkg": "1",
@@ -2255,7 +2235,6 @@
},
{
"BriefDescription": "Scoreboard Accesses; FM write completions",
- "Counter": "0,1,2,3",
"EventCode": "0xD2",
"EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS",
"PerPkg": "1",
@@ -2263,26 +2242,39 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses; Write Accepts",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Scoreboard Accesses; Read Accepts",
"EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS",
+ "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Accesses; Write Rejects",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Scoreboard Accesses; Read Rejects",
"EventCode": "0xD2",
- "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS",
+ "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Scoreboard Accesses; NM read completions",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Scoreboard Accesses; NM write completions",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS",
+ "PerPkg": "1",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Alloc",
- "Counter": "0,1,2,3",
"EventCode": "0xD9",
"EventName": "UNC_M_SB_CANARY.ALLOC",
"PerPkg": "1",
@@ -2291,7 +2283,6 @@
},
{
"BriefDescription": "Dealloc",
- "Counter": "0,1,2,3",
"EventCode": "0xD9",
"EventName": "UNC_M_SB_CANARY.DEALLOC",
"PerPkg": "1",
@@ -2299,26 +2290,23 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Reject",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Far Mem Read Starved",
"EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.REJ",
+ "EventName": "UNC_M_SB_CANARY.FMRD_STARVED",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "Valid",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Far Mem Write Starved",
"EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.VLD",
+ "EventName": "UNC_M_SB_CANARY.FMWR_STARVED",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Near Mem Read Starved",
- "Counter": "0,1,2,3",
"EventCode": "0xD9",
"EventName": "UNC_M_SB_CANARY.NMRD_STARVED",
"PerPkg": "1",
@@ -2327,7 +2315,6 @@
},
{
"BriefDescription": "Near Mem Write Starved",
- "Counter": "0,1,2,3",
"EventCode": "0xD9",
"EventName": "UNC_M_SB_CANARY.NMWR_STARVED",
"PerPkg": "1",
@@ -2335,26 +2322,23 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Far Mem Read Starved",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Reject",
"EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.FMRD_STARVED",
+ "EventName": "UNC_M_SB_CANARY.REJ",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Far Mem Write Starved",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Valid",
"EventCode": "0xD9",
- "EventName": "UNC_M_SB_CANARY.FMWR_STARVED",
+ "EventName": "UNC_M_SB_CANARY.VLD",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Cycles Full",
- "Counter": "0,1,2,3",
"EventCode": "0xD1",
"EventName": "UNC_M_SB_CYCLES_FULL",
"PerPkg": "1",
@@ -2362,87 +2346,77 @@
},
{
"BriefDescription": "Scoreboard Cycles Not-Empty",
- "Counter": "0,1,2,3",
"EventCode": "0xD0",
"EventName": "UNC_M_SB_CYCLES_NE",
"PerPkg": "1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts; Reads",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Scoreboard Inserts; Block region reads",
"EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.RDS",
+ "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts; Writes",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Scoreboard Inserts; Block region writes",
"EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.WRS",
+ "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts; Block region reads",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Scoreboard Inserts; Dealloc all commands (for error flows)",
"EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS",
+ "EventName": "UNC_M_SB_INSERTS.DEALLOC",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x40",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts; Block region writes",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Scoreboard Inserts; Patrol inserts",
"EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS",
+ "EventName": "UNC_M_SB_INSERTS.PATROL",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts; Dealloc all commands (for error flows)",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Scoreboard Inserts; Persistent Mem reads",
"EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.DEALLOC",
+ "EventName": "UNC_M_SB_INSERTS.PMM_RDS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Inserts; Patrol inserts",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Scoreboard Inserts; Persistent Mem writes",
"EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.PATROL",
+ "EventName": "UNC_M_SB_INSERTS.PMM_WRS",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Occupancy; Reads",
- "Counter": "0,1,2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.RDS",
+ "BriefDescription": "Scoreboard Inserts; Reads",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.RDS",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "Scoreboard Occupancy; Writes",
- "Counter": "0,1,2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.WRS",
+ "BriefDescription": "Scoreboard Inserts; Writes",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M_SB_INSERTS.WRS",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
{
"BriefDescription": "Scoreboard Occupancy; Block region reads",
- "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS",
"PerPkg": "1",
@@ -2451,7 +2425,6 @@
},
{
"BriefDescription": "Scoreboard Occupancy; Block region writes",
- "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS",
"PerPkg": "1",
@@ -2460,7 +2433,6 @@
},
{
"BriefDescription": "Scoreboard Occupancy; Patrol",
- "Counter": "0,1,2,3",
"EventCode": "0xD5",
"EventName": "UNC_M_SB_OCCUPANCY.PATROL",
"PerPkg": "1",
@@ -2468,26 +2440,55 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Number of Scoreboard Requests Rejected; NM requests rejected due to set conflict",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT",
+ "BriefDescription": "Scoreboard Occupancy; Persistent Mem reads",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Scoreboard Occupancy; Persistent Mem writes",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Scoreboard Occupancy; Reads",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.RDS",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "Scoreboard Occupancy; Writes",
+ "EventCode": "0xD5",
+ "EventName": "UNC_M_SB_OCCUPANCY.WRS",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Number of Scoreboard Requests Rejected; FM requests rejected due to full address conflict",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "Number of Scoreboard Requests Rejected; NM requests rejected due to set conflict",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Number of Scoreboard Requests Rejected; Patrol requests rejected due to set conflict",
- "Counter": "0,1,2,3",
"EventCode": "0xD4",
"EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT",
"PerPkg": "1",
@@ -2495,17 +2496,15 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Near Mem Read - Set",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Far Mem Read - Clear",
"EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_SET",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_CLR",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x20",
"Unit": "iMC"
},
{
"BriefDescription": "Far Mem Read - Set",
- "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M_SB_STRV_ALLOC.FMRD_SET",
"PerPkg": "1",
@@ -2513,17 +2512,15 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Near Mem Write - Set",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Far Mem Write - Clear",
"EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_SET",
+ "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_CLR",
"PerPkg": "1",
- "UMask": "0x4",
+ "UMask": "0x80",
"Unit": "iMC"
},
{
"BriefDescription": "Far Mem Write - Set",
- "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M_SB_STRV_ALLOC.FMWR_SET",
"PerPkg": "1",
@@ -2532,7 +2529,6 @@
},
{
"BriefDescription": "Near Mem Read - Clear",
- "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M_SB_STRV_ALLOC.NMRD_CLR",
"PerPkg": "1",
@@ -2540,17 +2536,15 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Far Mem Read - Clear",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Near Mem Read - Set",
"EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_CLR",
+ "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_SET",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Near Mem Write - Clear",
- "Counter": "0,1,2,3",
"EventCode": "0xD7",
"EventName": "UNC_M_SB_STRV_ALLOC.NMWR_CLR",
"PerPkg": "1",
@@ -2558,35 +2552,39 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Far Mem Write - Clear",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Near Mem Write - Set",
"EventCode": "0xD7",
- "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_CLR",
+ "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_SET",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
- "BriefDescription": "Near Mem Read",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Far Mem Read",
"EventCode": "0xD8",
- "EventName": "UNC_M_SB_STRV_OCC.NMRD",
+ "EventName": "UNC_M_SB_STRV_OCC.FMRD",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x2",
"Unit": "iMC"
},
{
- "BriefDescription": "Far Mem Read",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Far Mem Write",
"EventCode": "0xD8",
- "EventName": "UNC_M_SB_STRV_OCC.FMRD",
+ "EventName": "UNC_M_SB_STRV_OCC.FMWR",
"PerPkg": "1",
- "UMask": "0x2",
+ "UMask": "0x8",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Near Mem Read",
+ "EventCode": "0xD8",
+ "EventName": "UNC_M_SB_STRV_OCC.NMRD",
+ "PerPkg": "1",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
"BriefDescription": "Near Mem Write",
- "Counter": "0,1,2,3",
"EventCode": "0xD8",
"EventName": "UNC_M_SB_STRV_OCC.NMWR",
"PerPkg": "1",
@@ -2594,26 +2592,55 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Far Mem Write",
- "Counter": "0,1,2,3",
- "EventCode": "0xD8",
- "EventName": "UNC_M_SB_STRV_OCC.FMWR",
+ "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.DDR4_CMP",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "iMC"
},
{
"BriefDescription": "UNC_M_SB_TAGGED.NEW",
- "Counter": "0,1,2,3",
"EventCode": "0xDD",
"EventName": "UNC_M_SB_TAGGED.NEW",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "UNC_M_SB_TAGGED.OCC",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.OCC",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.PMM0_CMP",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.PMM1_CMP",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP",
+ "EventCode": "0xDD",
+ "EventName": "UNC_M_SB_TAGGED.PMM2_CMP",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "UNC_M_SB_TAGGED.RD_HIT",
- "Counter": "0,1,2,3",
"EventCode": "0xDD",
"EventName": "UNC_M_SB_TAGGED.RD_HIT",
"PerPkg": "1",
@@ -2622,7 +2649,6 @@
},
{
"BriefDescription": "UNC_M_SB_TAGGED.RD_MISS",
- "Counter": "0,1,2,3",
"EventCode": "0xDD",
"EventName": "UNC_M_SB_TAGGED.RD_MISS",
"PerPkg": "1",
@@ -2630,26 +2656,34 @@
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP",
- "Counter": "0,1,2,3",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.DDR4_CMP",
+ "BriefDescription": "All hits to Near Memory(DRAM cache) in Memory Mode",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M_TAGCHK.HIT",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Tag Check; Hit",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "UNC_M_SB_TAGGED.OCC",
- "Counter": "0,1,2,3",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.OCC",
+ "BriefDescription": "All Clean line misses to Near Memory(DRAM cache) in Memory Mode",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M_TAGCHK.MISS_CLEAN",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Tag Check; Clean",
+ "UMask": "0x2",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "All dirty line misses to Near Memory(DRAM cache) in Memory Mode",
+ "EventCode": "0xD3",
+ "EventName": "UNC_M_TAGCHK.MISS_DIRTY",
+ "PerPkg": "1",
+ "PublicDescription": "Tag Check; Dirty",
+ "UMask": "0x4",
"Unit": "iMC"
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH",
"PerPkg": "1",
@@ -2658,7 +2692,6 @@
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.STARVE",
"PerPkg": "1",
@@ -2667,7 +2700,6 @@
},
{
"BriefDescription": "Transition from WMM to RMM because of low threshold",
- "Counter": "0,1,2,3",
"EventCode": "0xC0",
"EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY",
"PerPkg": "1",
@@ -2676,47 +2708,69 @@
},
{
"BriefDescription": "Write Pending Queue Full Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x22",
"EventName": "UNC_M_WPQ_CYCLES_FULL",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC. This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue Not Empty",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_M_WPQ_CYCLES_NE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Write Pending Queue Allocations",
+ "EventCode": "0x20",
+ "EventName": "UNC_M_WPQ_INSERTS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of writes requests allocated into the Write Pending Queue (WPQ). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller). The write requests deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC.",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Write Pending Queue Occupancy",
+ "EventCode": "0x81",
+ "EventName": "UNC_M_WPQ_OCCUPANCY",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x23",
"EventName": "UNC_M_WPQ_READ_HIT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"Unit": "iMC"
},
{
"BriefDescription": "Write Pending Queue CAM Match",
- "Counter": "0,1,2,3",
"EventCode": "0x24",
"EventName": "UNC_M_WPQ_WRITE_HIT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
"Unit": "iMC"
},
{
"BriefDescription": "Not getting the requested Major Mode",
- "Counter": "0,1,2,3",
"EventCode": "0xC1",
"EventName": "UNC_M_WRONG_MM",
"PerPkg": "1",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; All Banks",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 0",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK0",
"PerPkg": "1",
@@ -2724,16 +2778,62 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 1",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK1",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
+ "PerPkg": "1",
+ "UMask": "0xa",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
+ "PerPkg": "1",
+ "UMask": "0xb",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
+ "PerPkg": "1",
+ "UMask": "0xc",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK13",
+ "PerPkg": "1",
+ "UMask": "0xd",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 14",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK14",
+ "PerPkg": "1",
+ "UMask": "0xe",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank 15",
+ "EventCode": "0xB8",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANK15",
+ "PerPkg": "1",
+ "UMask": "0xf",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK2",
"PerPkg": "1",
@@ -2742,7 +2842,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK3",
"PerPkg": "1",
@@ -2751,7 +2850,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK4",
"PerPkg": "1",
@@ -2760,7 +2858,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK5",
"PerPkg": "1",
@@ -2769,7 +2866,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK6",
"PerPkg": "1",
@@ -2778,7 +2874,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK7",
"PerPkg": "1",
@@ -2787,7 +2882,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK8",
"PerPkg": "1",
@@ -2796,7 +2890,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 0; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xB8",
"EventName": "UNC_M_WR_CAS_RANK0.BANK9",
"PerPkg": "1",
@@ -2804,124 +2897,110 @@
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks 0-3)",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK10",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANKG0",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0x11",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks 4-7)",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK11",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANKG1",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0x12",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks 8-11)",
"EventCode": "0xB8",
- "EventName": "UNC_M_WR_CAS_RANK0.BANK12",
+ "EventName": "UNC_M_WR_CAS_RANK0.BANKG2",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0x13",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 0; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks 12-15)",
"EventCode": "0xB8",
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+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
- "EventCode": "0xBD",
- "EventName": "UNC_M_WR_CAS_RANK5.BANKG3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
+ "EventCode": "0xBE",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
"PerPkg": "1",
- "UMask": "0x14",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
"PerPkg": "1",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK1",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK2",
"PerPkg": "1",
@@ -3870,7 +3844,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK3",
"PerPkg": "1",
@@ -3879,7 +3852,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK4",
"PerPkg": "1",
@@ -3888,7 +3860,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK5",
"PerPkg": "1",
@@ -3897,7 +3868,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK6",
"PerPkg": "1",
@@ -3906,7 +3876,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK7",
"PerPkg": "1",
@@ -3915,7 +3884,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK8",
"PerPkg": "1",
@@ -3924,7 +3892,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 6; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xBE",
"EventName": "UNC_M_WR_CAS_RANK6.BANK9",
"PerPkg": "1",
@@ -3932,124 +3899,110 @@
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 10",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK10",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
"PerPkg": "1",
- "UMask": "0xA",
+ "UMask": "0x11",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 11",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK11",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
"PerPkg": "1",
- "UMask": "0xB",
+ "UMask": "0x12",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 12",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK12",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
"PerPkg": "1",
- "UMask": "0xC",
+ "UMask": "0x13",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 13",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
"EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK13",
+ "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
"PerPkg": "1",
- "UMask": "0xD",
+ "UMask": "0x14",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 14",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK14",
+ "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
"PerPkg": "1",
- "UMask": "0xE",
+ "UMask": "0x10",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank 15",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANK15",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
"PerPkg": "1",
- "UMask": "0xF",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; All Banks",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANKG0",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0xa",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANKG1",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
"PerPkg": "1",
- "UMask": "0x12",
+ "UMask": "0xb",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANKG2",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
"PerPkg": "1",
- "UMask": "0x13",
+ "UMask": "0xc",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
- "EventCode": "0xBE",
- "EventName": "UNC_M_WR_CAS_RANK6.BANKG3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
+ "EventCode": "0xBF",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
"PerPkg": "1",
- "UMask": "0x14",
+ "UMask": "0xd",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK0",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
"PerPkg": "1",
+ "UMask": "0xe",
"Unit": "iMC"
},
{
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
"EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK1",
+ "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0xf",
"Unit": "iMC"
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 2",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK2",
"PerPkg": "1",
@@ -4058,7 +4011,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 3",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK3",
"PerPkg": "1",
@@ -4067,7 +4019,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 4",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK4",
"PerPkg": "1",
@@ -4076,7 +4027,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 5",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK5",
"PerPkg": "1",
@@ -4085,7 +4035,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 6",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK6",
"PerPkg": "1",
@@ -4094,7 +4043,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 7",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK7",
"PerPkg": "1",
@@ -4103,7 +4051,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 8",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK8",
"PerPkg": "1",
@@ -4112,79 +4059,14 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank 9",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANK9",
"PerPkg": "1",
"UMask": "0x9",
"Unit": "iMC"
},
- {
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 10",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK10",
- "PerPkg": "1",
- "UMask": "0xA",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 11",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK11",
- "PerPkg": "1",
- "UMask": "0xB",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 12",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK12",
- "PerPkg": "1",
- "UMask": "0xC",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 13",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK13",
- "PerPkg": "1",
- "UMask": "0xD",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 14",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK14",
- "PerPkg": "1",
- "UMask": "0xE",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 7; Bank 15",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.BANK15",
- "PerPkg": "1",
- "UMask": "0xF",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "WR_CAS Access to Rank 7; All Banks",
- "Counter": "0,1,2,3",
- "EventCode": "0xBF",
- "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "iMC"
- },
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks 0-3)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG0",
"PerPkg": "1",
@@ -4193,7 +4075,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks 4-7)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG1",
"PerPkg": "1",
@@ -4202,7 +4083,6 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks 8-11)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG2",
"PerPkg": "1",
@@ -4211,337 +4091,10 @@
},
{
"BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks 12-15)",
- "Counter": "0,1,2,3",
"EventCode": "0xBF",
"EventName": "UNC_M_WR_CAS_RANK7.BANKG3",
"PerPkg": "1",
"UMask": "0x14",
"Unit": "iMC"
- },
- {
- "BriefDescription": "Clockticks in the Memory Controller using a dedicated 48-bit Fixed Counter",
- "Counter": "FIXED",
- "EventCode": "0xff",
- "EventName": "UNC_M_CLOCKTICKS_F",
- "PerPkg": "1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0xE0",
- "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM Read Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0xE1",
- "EventName": "UNC_M_PMM_RPQ_CYCLES_NE",
- "PerPkg": "1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM Read Queue Cycles Full",
- "Counter": "0,1,2,3",
- "EventCode": "0xE2",
- "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL",
- "PerPkg": "1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "RPQ GNTs",
- "Counter": "0,1,2,3",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Underfill GNTs",
- "Counter": "0,1,2,3",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Misc GNTs",
- "Counter": "0,1,2,3",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.MISC_GNT",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Misc Commands (error, flow ACKs)",
- "Counter": "0,1,2,3",
- "EventCode": "0xEA",
- "EventName": "UNC_M_PMM_CMD1.MISC",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Opportunistic Reads",
- "Counter": "0,1,2,3",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.OPP_RD",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Expected No data packet (ERID matched NDP encoding)",
- "Counter": "0,1,2,3",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.NODATA_EXP",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Unexpected No data packet (ERID matched a Read, but data was a NDP)",
- "Counter": "0,1,2,3",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Read Requests - Slot 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Read Requests - Slot 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM ECC Errors",
- "Counter": "0,1,2,3",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM ERID detectable parity error",
- "Counter": "0,1,2,3",
- "EventCode": "0xEB",
- "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM Major Mode; Cycles PMM is in Read Major Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0xEC",
- "EventName": "UNC_M_PMM_MAJMODE1.RD_CYC",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM Major Mode; Cycles PMM is in Partial Write Major Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0xEC",
- "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_CYC",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM Major Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0xEC",
- "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_ENTER",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM Major Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0xEC",
- "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_EXIT",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "UNC_M_MAJMODE2.DRAM_CYC",
- "Counter": "0,1,2,3",
- "EventCode": "0xED",
- "EventName": "UNC_M_MAJMODE2.DRAM_CYC",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "UNC_M_MAJMODE2.DRAM_ENTER",
- "Counter": "0,1,2,3",
- "EventCode": "0xED",
- "EventName": "UNC_M_MAJMODE2.DRAM_ENTER",
- "PerPkg": "1",
- "UMask": "0x8",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "UNC_M_MAJMODE2.PMM_ENTER",
- "Counter": "0,1,2,3",
- "EventCode": "0xED",
- "EventName": "UNC_M_MAJMODE2.PMM_ENTER",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM Write Queue Cycles Full",
- "Counter": "0,1,2,3",
- "EventCode": "0xE6",
- "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL",
- "PerPkg": "1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM Write Queue Cycles Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0xE5",
- "EventName": "UNC_M_PMM_WPQ_CYCLES_NE",
- "PerPkg": "1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0xE4",
- "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0xE4",
- "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT",
- "Counter": "0,1,2,3",
- "EventCode": "0xE8",
- "EventName": "UNC_M_PMM_WPQ_PCOMMIT",
- "PerPkg": "1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT_CYC",
- "Counter": "0,1,2,3",
- "EventCode": "0xE9",
- "EventName": "UNC_M_PMM_WPQ_PCOMMIT_CYC",
- "PerPkg": "1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "PMM Major Mode; Cycles PMM is in Write Major Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0xEC",
- "EventName": "UNC_M_PMM_MAJMODE1.WR_CYC",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "UNC_M_MAJMODE2.PMM_CYC",
- "Counter": "0,1,2,3",
- "EventCode": "0xED",
- "EventName": "UNC_M_MAJMODE2.PMM_CYC",
- "PerPkg": "1",
- "UMask": "0x1",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP",
- "Counter": "0,1,2,3",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.PMM0_CMP",
- "PerPkg": "1",
- "UMask": "0x10",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP",
- "Counter": "0,1,2,3",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.PMM1_CMP",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP",
- "Counter": "0,1,2,3",
- "EventCode": "0xDD",
- "EventName": "UNC_M_SB_TAGGED.PMM2_CMP",
- "PerPkg": "1",
- "UMask": "0x40",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Scoreboard Inserts; Persistent Mem writes",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.PMM_WRS",
- "PerPkg": "1",
- "UMask": "0x08",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Scoreboard Occupancy; Persistent Mem writes",
- "Counter": "0,1,2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS",
- "PerPkg": "1",
- "UMask": "0x08",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Scoreboard Occupancy; Persistent Mem reads",
- "Counter": "0,1,2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "iMC"
- },
- {
- "BriefDescription": "Scoreboard Inserts; Persistent Mem reads",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M_SB_INSERTS.PMM_RDS",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "iMC"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json
index e10530c21ef8..6b49e6e91045 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json
@@ -1,8010 +1,7928 @@
[
{
- "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+ "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.MMIO_READ",
+ "Filter": "config1=0x40040e33",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages sent direct to core (bypassing the CHA)",
- "Counter": "0,1,2,3",
- "EventCode": "0x23",
- "EventName": "UNC_M2M_DIRECT2CORE_TAKEN",
+ "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.MMIO_WRITE",
+ "Filter": "config1=0x40041e33",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads in which direct to core transaction were overridden",
- "Counter": "0,1,2,3",
- "EventCode": "0x25",
- "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+ "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
+ "EventCode": "0x83",
+ "EventName": "LLC_MISSES.PCIE_READ",
+ "FCMask": "0x07",
+ "Filter": "ch_mask=0x1f",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+ "MetricName": "LLC_MISSES.PCIE_READ",
"PerPkg": "1",
- "Unit": "M2M"
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "ScaleUnit": "4Bytes",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
- "Counter": "0,1,2,3",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
+ "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
+ "EventCode": "0x83",
+ "EventName": "LLC_MISSES.PCIE_WRITE",
+ "FCMask": "0x07",
+ "Filter": "ch_mask=0x1f",
+ "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+ "MetricName": "LLC_MISSES.PCIE_WRITE",
"PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit onthe main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "ScaleUnit": "4Bytes",
"UMask": "0x1",
- "Unit": "M2M"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
- "Counter": "0,1,2,3",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
+ "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss",
+ "EventCode": "0x35",
+ "EventName": "LLC_MISSES.UNCACHEABLE",
+ "Filter": "config1=0x40e33",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
- "Counter": "0,1,2,3",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
+ "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.STREAMING_FULL",
+ "Filter": "config1=0x41833",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
- "Counter": "0,1,2,3",
- "EventCode": "0x2D",
- "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
+ "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
+ "EventCode": "0x35",
+ "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
+ "Filter": "config1=0x41a33",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "ScaleUnit": "64Bytes",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from I to S",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from I to A",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from S to I",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from S to A",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from A to I",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory update from A to S",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.NORMAL",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Reads to iMC issued",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x4",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Partial Non-Isochronous writes to the iMC",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Writes to iMC issued",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.ALL",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.NI",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Prefecth requests that got turn into a demand request",
- "Counter": "0,1,2,3",
- "EventCode": "0x56",
- "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inserts into the Memory Controller Prefetch Queue",
- "Counter": "0,1,2,3",
- "EventCode": "0x57",
- "EventName": "UNC_M2M_PREFCAM_INSERTS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Ingress (from CMS) Queue Inserts",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_M2M_RxC_AD_INSERTS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Ingress (from CMS) Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Ingress (from CMS) Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_M2M_RxC_BL_INSERTS",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Ingress (from CMS) Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x6",
- "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Egress (to CMS) Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x9",
- "EventName": "UNC_M2M_TxC_AD_INSERTS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Egress (to CMS) Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0xA",
- "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Occupancy; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x16",
- "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles when direct to Intel UPI was disabled",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
+ "EventCode": "0x8A",
+ "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages sent direct to the Intel UPI",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read requests to Intel Optane DC persistent memory issued to the iMC from M2M",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.TO_PMM",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write requests to Intel Optane DC persistent memory issued to the iMC from M2M",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventName": "UNC_C_CLOCKTICKS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x42",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x82",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
- "Counter": "0,1,2,3",
- "EventCode": "0x53",
- "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
- "Counter": "0,1,2,3",
- "EventCode": "0x53",
- "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
- "Counter": "0,1,2,3",
- "EventCode": "0x54",
- "EventName": "UNC_CHA_DIR_UPDATE.HA",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
- "Counter": "0,1,2,3",
- "EventCode": "0x54",
- "EventName": "UNC_CHA_DIR_UPDATE.TOR",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
- "Counter": "0,1,2,3",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x3",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x9",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
+ "EventCode": "0x8E",
+ "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Number of times that an RFO hit in S state",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.RFO_HIT_S",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "read requests from home agent",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x03",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "write requests from home agent",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES",
+ "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
"PerPkg": "1",
- "UMask": "0x0C",
+ "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the intermediate bypass.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "read requests from local home agent",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
+ "BriefDescription": "CHA to iMC Bypass; Not Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "write requests from local home agent",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
+ "BriefDescription": "CHA to iMC Bypass; Taken",
+ "EventCode": "0x57",
+ "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the full bypass.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
+ "BriefDescription": "Uncore cache clock ticks",
+ "EventName": "UNC_CHA_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts clockticks of the clock controlling the uncore caching and home agent (CHA).",
"Unit": "CHA"
},
{
- "BriefDescription": "RspIFwd Snoop Responses Received",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xC0",
+ "EventName": "UNC_CHA_CMS_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "CHA"
},
{
- "BriefDescription": "RspSFwd Snoop Responses Received",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
+ "BriefDescription": "Core PMA Events; C1 State",
+ "EventCode": "0x17",
+ "EventName": "UNC_CHA_CORE_PMA.C1_STATE",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
+ "BriefDescription": "Core PMA Events; C1 Transition",
+ "EventCode": "0x17",
+ "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5C",
- "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
+ "BriefDescription": "Core PMA Events; C6 State",
+ "EventCode": "0x17",
+ "EventName": "UNC_CHA_CORE_PMA.C6_STATE",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.IRQ",
+ "BriefDescription": "Core PMA Events; C6 Transition",
+ "EventCode": "0x17",
+ "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION",
"PerPkg": "1",
- "UMask": "0x31",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.IRQ",
+ "BriefDescription": "Core PMA Events; GV",
+ "EventCode": "0x17",
+ "EventName": "UNC_CHA_CORE_PMA.GV",
"PerPkg": "1",
- "UMask": "0x31",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.REM_ALL",
+ "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
"PerPkg": "1",
- "UMask": "0x30",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0xe2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0xA5",
- "EventName": "UNC_C_FAST_ASSERTED",
+ "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0xe1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; IRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
+ "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0xe4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x42",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy; IRQ",
- "EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
+ "BriefDescription": "Core Cross Snoops Issued; Single Core Requests",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x41",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT",
+ "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS",
+ "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x82",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT",
+ "BriefDescription": "Core Cross Snoops Issued; Single Eviction",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
"PerPkg": "1",
- "UMask": "0x14",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x81",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS",
+ "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE",
"PerPkg": "1",
- "UMask": "0x24",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x84",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT",
+ "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x22",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS",
+ "BriefDescription": "Core Cross Snoops Issued; Single External Snoops",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
"UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Hits from Local IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
+ "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node",
+ "EventCode": "0x33",
+ "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE",
"PerPkg": "1",
- "UMask": "0x14",
+ "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Misses from Local IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
+ "BriefDescription": "Counter 0 Occupancy",
+ "EventCode": "0x1F",
+ "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x24",
+ "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; All from Local iA",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA",
+ "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed",
+ "EventCode": "0x53",
+ "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP",
"PerPkg": "1",
- "UMask": "0x31",
+ "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Hits from Local iA",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
+ "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed",
+ "EventCode": "0x53",
+ "EventName": "UNC_CHA_DIR_LOOKUP.SNP",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
+ "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe",
+ "EventCode": "0x54",
+ "EventName": "UNC_CHA_DIR_UPDATE.HA",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.UNCACHEABLE",
- "Filter": "config1=0x40e33",
+ "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe",
+ "EventCode": "0x54",
+ "EventName": "UNC_CHA_DIR_UPDATE.TOR",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.MMIO_READ",
- "Filter": "config1=0x40040e33",
+ "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
+ "EventCode": "0xAE",
+ "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_MISSES.MMIO_WRITE",
- "Filter": "config1=0x40041e33",
+ "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
+ "EventCode": "0xAE",
+ "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.STREAMING_FULL",
- "Filter": "config1=0x41833",
+ "BriefDescription": "FaST wire asserted; Horizontal",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_FAST_ASSERTED.HORZ",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x21",
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "LLC_REFERENCES.STREAMING_PARTIAL",
- "Filter": "config1=0x41a33",
+ "BriefDescription": "FaST wire asserted; Vertical",
+ "EventCode": "0xA5",
+ "EventName": "UNC_CHA_FAST_ASSERTED.VERT",
"PerPkg": "1",
- "ScaleUnit": "64Bytes",
- "UMask": "0x21",
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; All from Local iA",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
+ "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.EX_RDS",
"PerPkg": "1",
- "UMask": "0x31",
+ "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Hits from Local iA",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Misses from Local iA",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
"PerPkg": "1",
- "UMask": "0x21",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS",
+ "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+ "EventCode": "0x5F",
+ "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "FaST wire asserted; Horizontal",
- "Counter": "0,1,2,3",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_FAST_ASSERTED.HORZ",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*",
+ "EventCode": "0x5E",
+ "EventName": "UNC_CHA_HITME_LOOKUP.READ",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Uncore cache clock ticks",
- "Counter": "0,1,2,3",
- "EventName": "UNC_CHA_CLOCKTICKS",
+ "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
+ "EventCode": "0x5E",
+ "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
"PerPkg": "1",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
- "Counter": "0,1,2,3",
- "EventCode": "0x59",
- "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
+ "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn",
+ "EventCode": "0x60",
+ "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
+ "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*",
+ "EventCode": "0x60",
+ "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Read requests from a remote socket",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
+ "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn",
+ "EventCode": "0x60",
+ "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "RspI Snoop Responses Received",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HtiME$ on Reads without RspFwdI*",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Rsp*WB Snoop Responses Received",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Received RspFwdI* for a local request, but converted HitME$ to SF entry",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "RspCnflct* Snoop Responses Received",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for M-state entries",
- "Counter": "0,1,2,3",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Updated HitME$ on RspFwdI* or local HitM/E received for a remote request",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for E-state entries",
- "Counter": "0,1,2,3",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
+ "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed",
+ "EventCode": "0x61",
+ "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop filter capacity evictions for S-state entries",
- "Counter": "0,1,2,3",
- "EventCode": "0x3D",
- "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
+ "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
+ "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x30",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized; Lines in M state",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
+ "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized; Lines in E state",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
+ "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
+ "EventCode": "0xA7",
+ "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized; Lines in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
+ "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
+ "EventCode": "0xA9",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Lines Victimized; Lines in F State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F",
+ "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
+ "EventCode": "0xA9",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
- "Filter": "config1=0x40433",
+ "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
+ "EventCode": "0xA9",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
- "Filter": "config1=0x40233",
+ "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
+ "EventCode": "0xA9",
+ "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
- "Filter": "config1=0x40033",
+ "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
- "Filter": "config1=0x4b433",
+ "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
- "Filter": "config1=0x4b233",
+ "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO",
- "Filter": "config1=0x4b033",
+ "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
+ "EventCode": "0xAB",
+ "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
- "Filter": "config1=0x40433",
+ "BriefDescription": "Horizontal IV Ring in Use; Left",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
- "Filter": "config1=0x40233",
+ "BriefDescription": "Horizontal IV Ring in Use; Right",
+ "EventCode": "0xAD",
+ "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
- "Filter": "config1=0x40033",
+ "BriefDescription": "Normal priority reads issued to the memory controller from the CHA",
+ "EventCode": "0x59",
+ "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
- "Filter": "config1=0x4b433",
+ "BriefDescription": "HA to iMC Reads Issued; ISOCH",
+ "EventCode": "0x59",
+ "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
- "Filter": "config1=0x4b233",
+ "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO",
- "Filter": "config1=0x4b033",
+ "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
- "Filter": "config1=0x40433",
+ "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
- "Filter": "config1=0x40233",
+ "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
- "Filter": "config1=0x40033",
- "PerPkg": "1",
- "UMask": "0x11",
+ "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory controller 5 only.",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
- "Filter": "config1=0x4b433",
+ "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial",
+ "EventCode": "0x5B",
+ "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
"PerPkg": "1",
- "UMask": "0x11",
+ "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
- "Filter": "config1=0x4b233",
+ "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations",
+ "EventCode": "0x62",
+ "EventName": "UNC_CHA_IODC_ALLOC.INVITOM",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
- "Filter": "config1=0x4b033",
+ "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full",
+ "EventCode": "0x62",
+ "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
- "Filter": "config1=0x40433",
+ "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate",
+ "EventCode": "0x62",
+ "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED",
"PerPkg": "1",
- "UMask": "0x21",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
- "Filter": "config1=0x40233",
+ "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason",
+ "EventCode": "0x63",
+ "EventName": "UNC_CHA_IODC_DEALLOC.ALL",
"PerPkg": "1",
- "UMask": "0x21",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
- "Filter": "config1=0x40033",
+ "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction",
+ "EventCode": "0x63",
+ "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT",
"PerPkg": "1",
- "UMask": "0x21",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
- "Filter": "config1=0x4b433",
+ "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE",
+ "EventCode": "0x63",
+ "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE",
"PerPkg": "1",
- "UMask": "0x21",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
- "Filter": "config1=0x4b233",
+ "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI",
+ "EventCode": "0x63",
+ "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI",
"PerPkg": "1",
- "UMask": "0x21",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
- "Filter": "config1=0x4b033",
+ "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI",
+ "EventCode": "0x63",
+ "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI",
"PerPkg": "1",
- "UMask": "0x21",
+ "PublicDescription": "Moved to Cbo section",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Clockticks of the IIO Traffic Controller",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_IIO_CLOCKTICKS",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.ANY",
"PerPkg": "1",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0",
- "FCMask": "0x7",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x1",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Read transactions",
+ "UMask": "0x3",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1",
- "FCMask": "0x7",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Local",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x1",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
+ "UMask": "0x31",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2",
- "FCMask": "0x7",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Remote",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x1",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
+ "UMask": "0x91",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3",
- "FCMask": "0x7",
+ "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x1",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.",
+ "UMask": "0x9",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
- "Counter": "0,1",
- "Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0",
- "FCMask": "0x7",
+ "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests",
+ "EventCode": "0x34",
+ "EventName": "UNC_CHA_LLC_LOOKUP.WRITE",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x4",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC.",
+ "UMask": "0x5",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1",
- "FCMask": "0x7",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x4",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2",
- "FCMask": "0x7",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x4",
- "Unit": "IIO"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3",
- "FCMask": "0x7",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x4",
- "Unit": "IIO"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Local - All Lines",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2f",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Local - Lines in E State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x22",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Local - Lines in F State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x28",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Local - Lines in M State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Local - Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x24",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
- "PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Remote - All Lines",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x8f",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Remote - Lines in E State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x82",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Remote - Lines in F State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x88",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Remote - Lines in M State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x81",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Remote - Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x84",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Lines in E state",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Lines in F State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Lines in M state",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Lines Victimized; Lines in S State",
+ "EventCode": "0x37",
+ "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Cbo Misc; CV0 Prefetch Miss",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Miscellaneous events in the Cbo.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Cbo Misc; CV0 Prefetch Victim",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Miscellaneous events in the Cbo.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Number of times that an RFO hit in S state.",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.RFO_HIT_S",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "LLC_MISSES.PCIE_WRITE",
- "FCMask": "0x07",
- "Filter": "ch_mask=0x1f",
- "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
- "MetricName": "LLC_MISSES.PCIE_WRITE",
+ "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
- "PortMask": "0x01",
- "ScaleUnit": "4Bytes",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Cbo Misc; Write Combining Aliasing",
+ "EventCode": "0x39",
+ "EventName": "UNC_CHA_MISC.WC_ALIASING",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "OSB Snoop Broadcast",
+ "EventCode": "0x55",
+ "EventName": "UNC_CHA_OSB",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in IODC",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.IODC",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "2LM related events; Counts the number of times CHA saw NM Set conflict in IODC",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "NM evictions due to another read to the same near memory set in the LLC.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "NM evictions due to another read to the same near memory set in the SF.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in TOR",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "No Reject in the CHA due to a pending read to the same near memory set in the TOR.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Memory mode related events; Counts the number of times CHA saw NM Set conflict in TOR and the transaction was rejected",
+ "EventCode": "0x64",
+ "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR_REJECT",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Rejects in the CHA due to a pending read to the same near memory set in the TOR.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 2 only.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "LLC_MISSES.PCIE_READ",
- "FCMask": "0x07",
- "Filter": "ch_mask=0x1f",
- "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
- "MetricName": "LLC_MISSES.PCIE_READ",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3",
"PerPkg": "1",
- "PortMask": "0x01",
- "ScaleUnit": "4Bytes",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 3 only.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 4 only.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 5 only.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 0 only.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1",
+ "EventCode": "0x58",
+ "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 1 only.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Read requests",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .",
+ "UMask": "0x3",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Read requests from a unit on this socket",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS_LOCAL",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Read requests from a remote socket",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.READS_REMOTE",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Write requests",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+ "UMask": "0xc",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Write Requests from a unit on this socket",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Read and Write Requests; Writes Remote",
+ "EventCode": "0x50",
+ "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
+ "EventCode": "0xA1",
+ "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.",
+ "EventCode": "0xA0",
+ "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
+ "EventCode": "0xA3",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Sink Starvation on Vertical Ring; AD",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.",
+ "EventCode": "0xA2",
+ "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xA4",
+ "EventName": "UNC_CHA_RING_SRC_THRTL",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
- "Unit": "IIO"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Ingress (from CMS) Allocations; IPQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Ingress (from CMS) Allocations; IRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IRQ",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "Ingress (from CMS) Allocations; RRQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
- "FCMask": "0x4",
+ "BriefDescription": "Ingress (from CMS) Allocations; WBQ",
+ "EventCode": "0x13",
+ "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x03",
- "Unit": "IIO"
+ "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
- "FCMask": "0x4",
+ "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x03",
- "Unit": "IIO"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
- "FCMask": "0x4",
+ "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x03",
- "Unit": "IIO"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
- "FCMask": "0x4",
+ "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x03",
- "Unit": "IIO"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0",
- "Counter": "2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
- "FCMask": "0x04",
+ "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "IIO"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1",
- "Counter": "2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
- "FCMask": "0x04",
+ "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "IIO"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2",
- "Counter": "2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
- "FCMask": "0x04",
+ "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "IIO"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3",
- "Counter": "2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
- "FCMask": "0x04",
+ "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "IIO"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
- "FCMask": "0x4",
+ "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request",
+ "EventCode": "0x22",
+ "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "PortMask": "0x0f",
- "UMask": "0x03",
- "Unit": "IIO"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
- "Counter": "2,3",
- "EventCode": "0xD5",
- "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
- "FCMask": "0x04",
+ "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x0f",
- "Unit": "IIO"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Total IRP occupancy of inbound read and write requests",
- "Counter": "0,1",
- "EventCode": "0xF",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
+ "BriefDescription": "Ingress Probe Queue Rejects; ANY0",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "IRP"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.RFO",
+ "BriefDescription": "Ingress Probe Queue Rejects; HA",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "IRP"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.PCITOM",
+ "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue",
- "Counter": "0,1",
- "EventCode": "0x18",
- "EventName": "UNC_I_FAF_INSERTS",
+ "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "Unit": "IRP"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Occupancy of the IRP FAF queue",
- "Counter": "0,1",
- "EventCode": "0x19",
- "EventName": "UNC_I_FAF_OCCUPANCY",
+ "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "Unit": "IRP"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Inbound write (fast path) requests received by the IRP",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+ "BriefDescription": "Ingress Probe Queue Rejects; SF Victim",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
"UMask": "0x8",
- "Unit": "IRP"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)",
- "Counter": "0,1,2,3",
- "EventCode": "0x1",
- "EventName": "UNC_UPI_CLOCKTICKS",
+ "BriefDescription": "Ingress Probe Queue Rejects; Victim",
+ "EventCode": "0x23",
+ "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Response packets that go direct to core",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
"UMask": "0x1",
- "Unit": "UPI LL"
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x12",
- "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
"UMask": "0x2",
- "Unit": "UPI LL"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_UPI_L1_POWER_CYCLES",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x25",
- "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
- "Counter": "0,1,2,3",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UPI LL"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
- "Counter": "0,1,2,3",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FLITs received which bypassed the Slot0 Recieve Buffer",
- "Counter": "0,1,2,3",
- "EventCode": "0x31",
- "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "UPI LL"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.NULL",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
+ "EventCode": "0x18",
+ "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FLITs that bypassed the TxL Buffer",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_UPI_TxL_BYPASSED",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid Flits Sent; Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.DATA",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.NULL",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
"UMask": "0x20",
- "Unit": "UPI LL"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Protocol header and credit FLITs received from any slot",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x97",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Protocol header and credit FLITs transmitted across any slot",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x97",
- "Unit": "UPI LL"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Idle FLITs transmitted",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.IDLE",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x47",
- "Unit": "UPI LL"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Null FLITs transmitted from any slot",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
+ "EventCode": "0x19",
+ "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x27",
- "Unit": "UPI LL"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Null FLITs received from any slot",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
+ "BriefDescription": "ISMQ Rejects; AD REQ on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x27",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Valid data FLITs received from any slot",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
+ "BriefDescription": "ISMQ Rejects; AD RSP on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UPI_DATA_BANDWIDTH_TX",
+ "BriefDescription": "ISMQ Rejects; Non UPI AK Request",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "ScaleUnit": "7.11E-06Bytes",
- "UMask": "0xf",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "UPI interconnect send bandwidth for payload",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
+ "BriefDescription": "ISMQ Rejects; BL NCB on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "ScaleUnit": "7.11E-06Bytes",
- "UMask": "0xf",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Response packets that go direct to Intel UPI",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U",
+ "BriefDescription": "ISMQ Rejects; BL NCS on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit",
- "Counter": "0,1,2",
- "EventCode": "0x29",
- "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
+ "BriefDescription": "ISMQ Rejects; BL RSP on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC Bypass; Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN",
+ "BriefDescription": "ISMQ Rejects; BL WB on VN0",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles - at UCLK",
- "Counter": "0,1,2,3",
- "EventName": "UNC_M2M_CLOCKTICKS",
+ "BriefDescription": "ISMQ Rejects; Non UPI IV Request",
+ "EventCode": "0x24",
+ "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit; On Dirty Line in I State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
+ "BriefDescription": "ISMQ Retries; AD REQ on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
"UMask": "0x1",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit; On Dirty Line in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
+ "BriefDescription": "ISMQ Retries; AD RSP on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
"UMask": "0x2",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit; On Dirty Line in L State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
+ "BriefDescription": "ISMQ Retries; Non UPI AK Request",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit; On Dirty Line in A State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
+ "BriefDescription": "ISMQ Retries; BL NCB on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit; On NonDirty Line in I State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
+ "BriefDescription": "ISMQ Retries; BL NCS on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit; On NonDirty Line in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
+ "BriefDescription": "ISMQ Retries; BL RSP on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit; On NonDirty Line in L State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
+ "BriefDescription": "ISMQ Retries; BL WB on VN0",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Hit; On NonDirty Line in A State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
+ "BriefDescription": "ISMQ Retries; Non UPI IV Request",
+ "EventCode": "0x2C",
+ "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
"UMask": "0x80",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss; On Dirty Line in I State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
+ "BriefDescription": "ISMQ Rejects; ANY0",
+ "EventCode": "0x25",
+ "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
"UMask": "0x1",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss; On Dirty Line in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
+ "BriefDescription": "ISMQ Rejects; HA",
+ "EventCode": "0x25",
+ "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
"UMask": "0x2",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss; On Dirty Line in L State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
+ "BriefDescription": "ISMQ Retries; ANY0",
+ "EventCode": "0x2D",
+ "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss; On Dirty Line in A State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
+ "BriefDescription": "ISMQ Retries; HA",
+ "EventCode": "0x2D",
+ "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss; On NonDirty Line in I State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
+ "BriefDescription": "Ingress (from CMS) Occupancy; IPQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss; On NonDirty Line in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
+ "BriefDescription": "Ingress (from CMS) Occupancy; IRQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss; On NonDirty Line in L State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
+ "BriefDescription": "Ingress (from CMS) Occupancy; RRQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Directory Miss; On NonDirty Line in A State",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
+ "BriefDescription": "Ingress (from CMS) Occupancy; WBQ",
+ "EventCode": "0x11",
+ "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
"PerPkg": "1",
+ "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.",
"UMask": "0x80",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC; Critical Priority",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.ISOCH",
+ "BriefDescription": "Other Retries; AD REQ on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+ "PerPkg": "1",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Other Retries; AD RSP on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
"UMask": "0x2",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS",
+ "BriefDescription": "Other Retries; Non UPI AK Request",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
+ "PerPkg": "1",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "Other Retries; BL NCB on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FULL",
+ "BriefDescription": "Other Retries; BL NCS on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2M"
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
+ "BriefDescription": "Other Retries; BL RSP on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
"UMask": "0x4",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
+ "BriefDescription": "Other Retries; BL WB on VN0",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
"PerPkg": "1",
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
"UMask": "0x8",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS",
+ "BriefDescription": "Other Retries; Non UPI IV Request",
+ "EventCode": "0x2E",
+ "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number Packet Header Matches; Mesh Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x4C",
- "EventName": "UNC_M2M_PKT_MATCH.MESH",
+ "BriefDescription": "Other Retries; Allow Snoop",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Number Packet Header Matches; MC Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x4C",
- "EventName": "UNC_M2M_PKT_MATCH.MC",
- "PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Prefetch CAM Cycles Full",
- "Counter": "0,1,2,3",
- "EventCode": "0x53",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL",
- "PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Prefetch CAM Cycles Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0x54",
- "EventName": "UNC_M2M_PREFCAM_CYCLES_NE",
+ "BriefDescription": "Other Retries; ANY0",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Prefetch CAM Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x55",
- "EventName": "UNC_M2M_PREFCAM_OCCUPANCY",
+ "BriefDescription": "Other Retries; HA",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+ "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2M"
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+ "BriefDescription": "Other Retries; LLC Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2M"
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+ "BriefDescription": "Other Retries; PhyAddr Match",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number AD Ingress Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_M2M_TGR_AD_CREDITS",
+ "BriefDescription": "Other Retries; SF Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Number BL Ingress Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x42",
- "EventName": "UNC_M2M_TGR_BL_CREDITS",
+ "BriefDescription": "Other Retries; Victim",
+ "EventCode": "0x2F",
+ "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Full; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
"UMask": "0x1",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Full; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
"UMask": "0x2",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Full; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x45",
- "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Not Empty; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2M"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Not Empty; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Cycles Not Empty; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
"UMask": "0x4",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Inserts; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Inserts; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
+ "EventCode": "0x20",
+ "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Inserts; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x49",
- "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Occupancy; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
"PerPkg": "1",
"UMask": "0x1",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Occupancy; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
"PerPkg": "1",
"UMask": "0x2",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Tracker Occupancy; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x47",
- "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Data Pending Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x48",
- "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
+ "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
+ "EventCode": "0x21",
+ "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Full; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0",
+ "BriefDescription": "Request Queue Retries; AD REQ on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x1",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Full; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1",
+ "BriefDescription": "Request Queue Retries; AD RSP on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x2",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Full; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x4A",
- "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2",
+ "BriefDescription": "Request Queue Retries; Non UPI AK Request",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0",
+ "BriefDescription": "Request Queue Retries; BL NCB on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2M"
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1",
+ "BriefDescription": "Request Queue Retries; BL NCS on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2M"
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x4B",
- "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2",
+ "BriefDescription": "Request Queue Retries; BL RSP on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x4",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Inserts; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0",
+ "BriefDescription": "Request Queue Retries; BL WB on VN0",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "M2M"
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Inserts; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1",
+ "BriefDescription": "Request Queue Retries; Non UPI IV Request",
+ "EventCode": "0x2A",
+ "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "M2M"
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Inserts; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2",
+ "BriefDescription": "Request Queue Retries; Allow Snoop",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Occupancy; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0",
+ "BriefDescription": "Request Queue Retries; ANY0",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
"PerPkg": "1",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x1",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Write Tracker Occupancy; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1",
+ "BriefDescription": "Request Queue Retries; HA",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
"PerPkg": "1",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x2",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Write Tracker Occupancy; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2",
- "PerPkg": "1",
- "UMask": "0x4",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "Request Queue Retries; LLC Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "Request Queue Retries; PhyAddr Match",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "Request Queue Retries; SF Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "Request Queue Retries; Victim",
+ "EventCode": "0x2B",
+ "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
"PerPkg": "1",
+ "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "RRQ Rejects; AD REQ on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "RRQ Rejects; AD RSP on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "RRQ Rejects; Non UPI AK Request",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "RRQ Rejects; BL NCB on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "RRQ Rejects; BL NCS on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "RRQ Rejects; BL RSP on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "RRQ Rejects; BL WB on VN0",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "RRQ Rejects; Non UPI IV Request",
+ "EventCode": "0x26",
+ "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "RRQ Rejects; Allow Snoop",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "RRQ Rejects; ANY0",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "RRQ Rejects; HA",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "RRQ Rejects; LLC Victim",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "RRQ Rejects; PhyAddr Match",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "RRQ Rejects; SF Victim",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "RRQ Rejects; Victim",
+ "EventCode": "0x27",
+ "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "WBQ Rejects; AD REQ on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "WBQ Rejects; AD RSP on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "WBQ Rejects; Non UPI AK Request",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
+ "PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "WBQ Rejects; BL NCB on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "WBQ Rejects; BL NCS on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "WBQ Rejects; BL RSP on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "WBQ Rejects; BL WB on VN0",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "WBQ Rejects; Non UPI IV Request",
+ "EventCode": "0x28",
+ "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "WBQ Rejects; Allow Snoop",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "WBQ Rejects; ANY0",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "WBQ Rejects; HA",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "WBQ Rejects; LLC Victim",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "WBQ Rejects; PhyAddr Match",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "WBQ Rejects; SF Victim",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "WBQ Rejects; Victim",
+ "EventCode": "0x29",
+ "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
"PerPkg": "1",
+ "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+ "EventCode": "0xB4",
+ "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0",
+ "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1",
+ "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2",
+ "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3",
+ "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4",
+ "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5",
+ "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
- "Counter": "0,1,2,3",
- "EventCode": "0xAE",
- "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
- "Counter": "0,1,2,3",
- "EventCode": "0xAE",
- "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal IV Ring in Use; Left",
- "Counter": "0,1,2,3",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Horizontal IV Ring in Use; Right",
- "Counter": "0,1,2,3",
- "EventCode": "0xAD",
- "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
+ "BriefDescription": "Snoop filter capacity evictions for E-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.E_STATE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
+ "BriefDescription": "Snoop filter capacity evictions for M-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.M_STATE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
+ "BriefDescription": "Snoop filter capacity evictions for S-state entries.",
+ "EventCode": "0x3D",
+ "EventName": "UNC_CHA_SF_EVICTION.S_STATE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0xA1",
- "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
+ "BriefDescription": "Snoops Sent; All",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.ALL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of snoops issued by the HA.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
+ "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
+ "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
+ "BriefDescription": "Snoops Sent; Directed snoops for Local Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "EventCode": "0xA0",
- "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
+ "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
+ "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
+ "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests",
+ "EventCode": "0x51",
+ "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
+ "BriefDescription": "RspCnflct* Snoop Responses Received",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
+ "BriefDescription": "Snoop Responses Received; RspFwd",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0xA3",
- "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
+ "BriefDescription": "RspI Snoop Responses Received",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPI",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; AD",
- "Counter": "0,1,2,3",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
+ "BriefDescription": "RspIFwd Snoop Responses Received",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
- "Counter": "0,1,2,3",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
+ "BriefDescription": "Snoop Responses Received : RspS",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Snoop Responses Received : RspS : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
- "Counter": "0,1,2,3",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
+ "BriefDescription": "RspSFwd Snoop Responses Received",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache",
- "Counter": "0,1,2,3",
- "EventCode": "0xA2",
- "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
+ "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "EventCode": "0xA4",
- "EventName": "UNC_M2M_RING_SRC_THRTL",
+ "BriefDescription": "Rsp*WB Snoop Responses Received",
+ "EventCode": "0x5C",
+ "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Ingress (from CMS) Full",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
+ "BriefDescription": "Snoop Responses Received Local; RspCnflct",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.",
+ "UMask": "0x40",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Ingress (from CMS) Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
+ "BriefDescription": "Snoop Responses Received Local; RspFwd",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.",
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Ingress (from CMS) Full",
- "Counter": "0,1,2,3",
- "EventCode": "0x8",
- "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
+ "BriefDescription": "Snoop Responses Received Local; RspI",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Ingress (from CMS) Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0x7",
- "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
+ "BriefDescription": "Snoop Responses Received Local; RspIFwd",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC",
+ "BriefDescription": "Snoop Responses Received Local; RspS",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
+ "BriefDescription": "Snoop Responses Received Local; RspSFwd",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its currentl copy. This is common for data and code reads that hit in a remote socket in E or F state.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC",
+ "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB4",
- "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
+ "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
+ "EventCode": "0x5D",
+ "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB2",
- "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD0",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
- "PerPkg": "1",
- "UMask": "0x80",
- "Unit": "M2M"
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD2",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB3",
- "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD4",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB1",
- "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0xB0",
- "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC",
+ "BriefDescription": "TOR Inserts; All",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ALL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0xff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "BriefDescription": "TOR Inserts; Hits from Local",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x15",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "BriefDescription": "TOR Inserts; All from Local iA and IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests",
+ "UMask": "0x35",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "BriefDescription": "TOR Inserts; Misses from Local",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x25",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "BriefDescription": "TOR Inserts; SF/LLC Evictions",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "BriefDescription": "TOR Inserts; Hit (Not a Miss)",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.HIT",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "BriefDescription": "TOR Inserts; All from Local iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from iA Cores",
+ "UMask": "0x31",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "BriefDescription": "TOR Inserts; Hits from Local iA",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD",
+ "Filter": "config1=0x40233",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD",
+ "Filter": "config1=0x40433",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD",
+ "Filter": "config1=0x4b233",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD",
+ "Filter": "config1=0x4b433",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO",
+ "Filter": "config1=0x4b033",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO",
+ "Filter": "config1=0x40033",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD",
+ "Filter": "config1=0x40233",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD",
+ "Filter": "config1=0x40433",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD",
+ "Filter": "config1=0x4b233",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD",
+ "Filter": "config1=0x4b433",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO",
+ "Filter": "config1=0x4b033",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO",
+ "Filter": "config1=0x40033",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "TOR Inserts; All from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally generated IO traffic",
+ "UMask": "0x34",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "TOR Inserts; Hits from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x14",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "TOR Inserts; Misses from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x24",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "TOR Inserts; ItoM misses from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
+ "Filter": "config1=0x49033",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM request is used by IIO to request a data write without first reading the data for ownership.",
+ "UMask": "0x24",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0xE",
- "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
+ "BriefDescription": "TOR Inserts; RdCur misses from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR",
+ "Filter": "config1=0x43C33",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RdCur requests and miss the LLC. A RdCur request is used by IIO to read data without changing state.",
+ "UMask": "0x24",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Egress (to CMS) Credit Acquired",
- "Counter": "0,1,2,3",
- "EventCode": "0xD",
- "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
+ "BriefDescription": "TOR Inserts; RFO misses from Local IO",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
+ "Filter": "config1=0x40033",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests a cache line to be cached in E state with the intent to modify.",
+ "UMask": "0x24",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Egress (to CMS) Full",
- "Counter": "0,1,2,3",
- "EventCode": "0xC",
- "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
+ "BriefDescription": "TOR Inserts; IPQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AD Egress (to CMS) Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0xB",
- "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x18",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0xF",
- "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS",
"PerPkg": "1",
- "Unit": "M2M"
+ "UMask": "0x28",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x10",
- "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
+ "BriefDescription": "TOR Inserts; IRQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.IRQ",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x37",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_M2M_TxC_AK.NDR",
+ "BriefDescription": "TOR Inserts; Miss",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.MISS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1E",
- "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0",
+ "BriefDescription": "TOR Inserts; PRQ",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.PRQ",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1E",
- "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x30",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1D",
- "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x50",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1D",
- "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x60",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1F",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x90",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1F",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0xa0",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.ALL",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0xff",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
+ "BriefDescription": "TOR Occupancy; All from Local",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely generated requests",
+ "UMask": "0x37",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
+ "BriefDescription": "TOR Occupancy; Hits from Local",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x17",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1A",
- "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0",
+ "BriefDescription": "TOR Occupancy; Misses from Local",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x27",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1A",
- "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1",
+ "BriefDescription": "TOR Occupancy; SF/LLC Evictions",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
+ "BriefDescription": "TOR Occupancy; Hit (Not a Miss)",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
+ "BriefDescription": "TOR Occupancy; All from Local iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally initiated requests from iA Cores",
+ "UMask": "0x31",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Full; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
+ "BriefDescription": "TOR Occupancy; Hits from Local iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD",
+ "Filter": "config1=0x40233",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD",
+ "Filter": "config1=0x40433",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD",
+ "Filter": "config1=0x4b233",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD",
+ "Filter": "config1=0x4b433",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO",
+ "Filter": "config1=0x4b033",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO",
+ "Filter": "config1=0x40033",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
+ "BriefDescription": "TOR Occupancy; Misses from Local iA",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD",
+ "Filter": "config1=0x40233",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1B",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
+ "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD",
+ "Filter": "config1=0x40433",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD",
+ "Filter": "config1=0x4b233",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x1C",
- "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD",
+ "Filter": "config1=0x4b433",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x16",
- "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO",
+ "Filter": "config1=0x4b033",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x16",
- "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1",
+ "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO",
+ "Filter": "config1=0x40033",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC",
+ "BriefDescription": "TOR Occupancy; All from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally generated IO traffic",
+ "UMask": "0x34",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
+ "BriefDescription": "TOR Occupancy; Hits from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x14",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC",
+ "BriefDescription": "TOR Occupancy; Misses from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x24",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC",
+ "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
+ "Filter": "config1=0x49033",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM is used by IIO to request a data write without first reading the data for ownership.",
+ "UMask": "0x24",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
+ "BriefDescription": "TOR Occupancy; RDCUR isses from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR",
+ "Filter": "config1=0x43C33",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RdCur requests that miss the LLC. A RdCur request is used by IIO to read data without changing state.",
+ "UMask": "0x24",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC",
+ "BriefDescription": "TOR Occupancy; RFO misses from Local IO",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
+ "Filter": "config1=0x40033",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests data to be cached in E state with the intent to modify.",
+ "UMask": "0x24",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
+ "BriefDescription": "TOR Occupancy; IPQ",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x18",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS",
+ "PerPkg": "1",
+ "UMask": "0x28",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; IRQ",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ",
+ "PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+ "PerPkg": "1",
+ "UMask": "0x37",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; Miss",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+ "PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "TOR Occupancy; PRQ",
+ "EventCode": "0x36",
+ "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+ "PerPkg": "1",
+ "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
+ "EventCode": "0x9D",
+ "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
+ "EventCode": "0x9F",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x9F",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
- "Counter": "0,1,2,3",
"EventCode": "0x9F",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x9F",
- "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x96",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x97",
- "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x95",
- "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x99",
- "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
- },
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
{
"BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x94",
- "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
- "Counter": "0,1,2,3",
"EventCode": "0x9B",
- "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC",
+ "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9C",
- "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical ADS Used; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x9E",
- "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV",
+ "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x92",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x93",
- "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV",
+ "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Allocations; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x91",
- "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV",
+ "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Vertical Egress NACKs; IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_CHA_TxR_VERT_NACK.IV",
+ "PerPkg": "1",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vert Egress Occupancy; IV",
- "Counter": "0,1,2,3",
"EventCode": "0x90",
- "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV",
+ "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x10",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x20",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
- "Counter": "0,1,2,3",
"EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
+ "EventCode": "0x9A",
+ "EventName": "UNC_CHA_TxR_VERT_STARVED.IV",
+ "PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x2",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits",
+ "EventCode": "0x38",
+ "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x4",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x40",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x80",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x10",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits",
+ "EventCode": "0x3B",
+ "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical AD Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical AD Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical AD Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical AD Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA6",
- "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
+ "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical AK Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA8",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical AK Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA8",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical AK Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xA8",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical AK Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xA8",
- "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
+ "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical BL Ring in Use; Down and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xAA",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical BL Ring in Use; Down and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xAA",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical BL Ring in Use; Up and Even",
- "Counter": "0,1,2,3",
"EventCode": "0xAA",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical BL Ring in Use; Up and Odd",
- "Counter": "0,1,2,3",
"EventCode": "0xAA",
- "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
+ "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical IV Ring in Use; Down",
- "Counter": "0,1,2,3",
"EventCode": "0xAC",
- "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
+ "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
"BriefDescription": "Vertical IV Ring in Use; Up",
- "Counter": "0,1,2,3",
"EventCode": "0xAC",
- "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
+ "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x40",
- "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI",
+ "BriefDescription": "WbPushMtoI; Pushed to LLC",
+ "EventCode": "0x56",
+ "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was able to push WbPushMToI to LLC",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
+ "BriefDescription": "WbPushMtoI; Pushed to Memory",
+ "EventCode": "0x56",
+ "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 2 only.",
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x44",
- "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 3 only.",
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 4 only.",
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_M2M_TxR_VERT_NACK.IV",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 5 only.",
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_M2M_TxR_VERT_STARVED.IV",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 0 only.",
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
+ "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 1 only.",
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
+ "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd F/E",
+ "UMask": "0xe4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x4D",
- "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
+ "BriefDescription": "Core Cross Snoop Responses",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd M",
+ "UMask": "0xf0",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC Bypass; Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
+ "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd F/E",
+ "UMask": "0xe2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC Bypass; Not Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
+ "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd M",
+ "UMask": "0xe8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_M2M_CMS_CLOCKTICKS",
+ "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE",
"PerPkg": "1",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response any to Hit F/S/E",
+ "UMask": "0xe1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0",
+ "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd F/E",
+ "UMask": "0x44",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1",
+ "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd M",
+ "UMask": "0x50",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x4E",
- "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2",
+ "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd F/E",
+ "UMask": "0x42",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FaST wire asserted; Vertical",
- "Counter": "0,1,2,3",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_FAST_ASSERTED.VERT",
+ "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd M",
+ "UMask": "0x48",
+ "Unit": "CHA"
},
{
- "BriefDescription": "FaST wire asserted; Horizontal",
- "Counter": "0,1,2,3",
- "EventCode": "0xA5",
- "EventName": "UNC_M2M_FAST_ASSERTED.HORZ",
+ "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response any to Hit F/S/E",
+ "UMask": "0x41",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0",
+ "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd F/E",
+ "UMask": "0x84",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1",
+ "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd M",
+ "UMask": "0x90",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x43",
- "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2",
+ "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd F/E",
+ "UMask": "0x82",
+ "Unit": "CHA"
},
{
- "BriefDescription": "Clean line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode and regular reads to DRAM in 1LM",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN",
+ "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd M",
+ "UMask": "0x88",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
+ "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response any to Hit F/S/E",
+ "UMask": "0x81",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
+ "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd F/E",
+ "UMask": "0x24",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
+ "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd M",
+ "UMask": "0x30",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
+ "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd F/E",
+ "UMask": "0x22",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
+ "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd M",
+ "UMask": "0x28",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
+ "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE",
+ "EventCode": "0x32",
+ "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE",
"PerPkg": "1",
- "UMask": "0x88",
- "Unit": "M2M"
+ "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response any to Hit F/S/E",
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS",
+ "Deprecated": "1",
+ "EventName": "UNC_C_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x90",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ",
+ "Deprecated": "1",
+ "EventCode": "0xA5",
+ "EventName": "UNC_C_FAST_ASSERTED",
"PerPkg": "1",
- "UMask": "0xA0",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Full; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.ANY",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.DATA_READ",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x3",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.LOCAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x31",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.REMOTE",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x91",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "UMask": "0x9",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE",
+ "Deprecated": "1",
+ "EventCode": "0x34",
+ "EventName": "UNC_C_LLC_LOOKUP.WRITE",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "UMask": "0x5",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Not Empty; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x13",
- "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.E_STATE",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.F_STATE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.LOCAL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x2f",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.M_STATE",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x1",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.REMOTE",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "UMask": "0x80",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
+ "Deprecated": "1",
+ "EventCode": "0x37",
+ "EventName": "UNC_C_LLC_VICTIMS.S_STATE",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL",
+ "Deprecated": "1",
+ "EventCode": "0xA4",
+ "EventName": "UNC_C_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M2M"
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Allocations; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x11",
- "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.EVICT",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "UMask": "0x2",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.HIT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x10",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.IPQ",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x8",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M2M"
+ "UMask": "0x18",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M2M"
+ "UMask": "0x28",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.IRQ",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M2M"
+ "UMask": "0x31",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Occupancy; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x12",
- "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "M2M"
+ "UMask": "0x11",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Sideband",
- "Counter": "0,1,2,3",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x21",
+ "Unit": "CHA"
},
{
- "BriefDescription": "AK Egress (to CMS) Sideband",
- "Counter": "0,1,2,3",
- "EventCode": "0x6B",
- "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.LOC_ALL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x37",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x4F",
- "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.LOC_IA",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x31",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x4F",
- "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.LOC_IO",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
+ "UMask": "0x34",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x4F",
- "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.MISS",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x20",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.PRQ",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M2M"
+ "UMask": "0x4",
+ "Unit": "CHA"
},
{
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN1",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M2M"
- },
- {
- "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M2M"
+ "UMask": "0x14",
+ "Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass; Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.REM_ALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x30",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA to iMC Bypass; Not Taken",
- "Counter": "0,1,2,3",
- "EventCode": "0x57",
- "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x50",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Single External Snoops",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EXT_ONE",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS",
"PerPkg": "1",
- "UMask": "0x21",
+ "UMask": "0x60",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Single Core Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.CORE_ONE",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT",
"PerPkg": "1",
- "UMask": "0x41",
+ "UMask": "0x90",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Single Eviction",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x35",
+ "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS",
"PerPkg": "1",
- "UMask": "0x81",
+ "UMask": "0xa0",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.ANY_ONE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.EVICT",
"PerPkg": "1",
- "UMask": "0xE1",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.HIT",
"PerPkg": "1",
- "UMask": "0x22",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0xE2",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT",
"PerPkg": "1",
- "UMask": "0x24",
+ "UMask": "0x18",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS",
"PerPkg": "1",
- "UMask": "0x44",
+ "UMask": "0x28",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.IRQ",
"PerPkg": "1",
- "UMask": "0x84",
+ "UMask": "0x31",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT",
"PerPkg": "1",
- "UMask": "0xE4",
+ "UMask": "0x11",
"Unit": "CHA"
},
{
- "BriefDescription": "Counter 0 Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x1F",
- "EventName": "UNC_CHA_COUNTER0_OCCUPANCY",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS",
"PerPkg": "1",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*",
- "Counter": "0,1,2,3",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x37",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE",
- "Counter": "0,1,2,3",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.WBMTOE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x31",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
- "Counter": "0,1,2,3",
- "EventCode": "0x5F",
- "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x34",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*",
- "Counter": "0,1,2,3",
- "EventCode": "0x5E",
- "EventName": "UNC_CHA_HITME_LOOKUP.READ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.MISS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS",
- "Counter": "0,1,2,3",
- "EventCode": "0x5E",
- "EventName": "UNC_CHA_HITME_LOOKUP.WRITE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.PRQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x14",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+ "Deprecated": "1",
+ "EventCode": "0x36",
+ "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*",
- "Counter": "0,1,2,3",
- "EventCode": "0x60",
- "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.SHARED",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HtiME$ on Reads without RspFwdI*",
- "Counter": "0,1,2,3",
- "EventCode": "0x61",
- "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0x80",
+ "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "HA to iMC Reads Issued; ISOCH",
- "Counter": "0,1,2,3",
- "EventCode": "0x59",
- "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0x82",
+ "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH",
- "Counter": "0,1,2,3",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0x82",
+ "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line",
- "Counter": "0,1,2,3",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0x82",
+ "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial",
- "Counter": "0,1,2,3",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0x82",
+ "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG",
- "Counter": "0,1,2,3",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0x82",
+ "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG",
- "Counter": "0,1,2,3",
- "EventCode": "0x5B",
- "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0x82",
+ "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x62",
- "EventName": "UNC_CHA_IODC_ALLOC.INVITOM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0x88",
+ "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full",
- "Counter": "0,1,2,3",
- "EventCode": "0x62",
- "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0x88",
+ "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate",
- "Counter": "0,1,2,3",
- "EventCode": "0x62",
- "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0x88",
+ "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE",
- "Counter": "0,1,2,3",
- "EventCode": "0x63",
- "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0x88",
+ "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI",
- "Counter": "0,1,2,3",
- "EventCode": "0x63",
- "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0x88",
+ "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI",
- "Counter": "0,1,2,3",
- "EventCode": "0x63",
- "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0x88",
+ "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction",
- "Counter": "0,1,2,3",
- "EventCode": "0x63",
- "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason",
- "Counter": "0,1,2,3",
- "EventCode": "0x63",
- "EventName": "UNC_CHA_IODC_DEALLOC.ALL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2",
"Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.WRITE",
+ "EventCode": "0x8A",
+ "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x5",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3",
"Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.ANY",
+ "EventCode": "0x8A",
+ "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x11",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4",
"Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.LOCAL",
+ "EventCode": "0x8A",
+ "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x31",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5",
"Deprecated": "1",
- "EventCode": "0x34",
- "EventName": "UNC_C_LLC_LOOKUP.REMOTE",
+ "EventCode": "0x8A",
+ "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x91",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0",
"Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.LOCAL",
+ "EventCode": "0x84",
+ "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x2f",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1",
"Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_C_LLC_VICTIMS.REMOTE",
+ "EventCode": "0x84",
+ "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc; Silent Snoop Eviction",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc; Write Combining Aliasing",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.WC_ALIASING",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc; CV0 Prefetch Victim",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.CV0_PREF_VIC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Cbo Misc; CV0 Prefetch Miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_CHA_MISC.CV0_PREF_MISS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "OSB Snoop Broadcast",
- "Counter": "0,1,2,3",
- "EventCode": "0x55",
- "EventName": "UNC_CHA_OSB",
- "PerPkg": "1",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0",
- "Counter": "0,1,2,3",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0x86",
+ "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1",
- "Counter": "0,1,2,3",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0x86",
+ "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2",
- "Counter": "0,1,2,3",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0x86",
+ "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3",
- "Counter": "0,1,2,3",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0x86",
+ "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4",
- "Counter": "0,1,2,3",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0x86",
+ "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5",
- "Counter": "0,1,2,3",
- "EventCode": "0x58",
- "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0x86",
+ "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "write requests from remote home agent",
- "Counter": "0,1,2,3",
- "EventCode": "0x50",
- "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1",
"Deprecated": "1",
- "EventCode": "0x51",
- "EventName": "UNC_H_SNOOPS_SENT.",
+ "EventCode": "0x8E",
+ "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4",
"Deprecated": "1",
- "EventCode": "0x51",
- "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC",
+ "EventCode": "0x8E",
+ "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5",
"Deprecated": "1",
- "EventCode": "0x51",
- "EventName": "UNC_H_SNOOPS_SENT.BCST_REM",
+ "EventCode": "0x8E",
+ "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0",
"Deprecated": "1",
- "EventCode": "0x51",
- "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC",
+ "EventCode": "0x8C",
+ "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1",
"Deprecated": "1",
- "EventCode": "0x51",
- "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM",
+ "EventCode": "0x8C",
+ "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received : RspS",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR2",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3",
"Deprecated": "1",
- "EventCode": "0x5C",
- "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
+ "EventCode": "0x8C",
+ "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR3",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Snoop Responses Received; RspFwd",
- "Counter": "0,1,2,3",
- "EventCode": "0x5C",
- "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5",
"Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI",
+ "EventCode": "0x8C",
+ "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE",
"Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS",
+ "EventCode": "0x57",
+ "EventName": "UNC_H_BYPASS_CHA_IMC.INTERMEDIATE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN",
"Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD",
+ "EventCode": "0x57",
+ "EventName": "UNC_H_BYPASS_CHA_IMC.NOT_TAKEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.TAKEN",
"Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD",
+ "EventCode": "0x57",
+ "EventName": "UNC_H_BYPASS_CHA_IMC.TAKEN",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS",
"Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB",
+ "EventCode": "0xC0",
+ "EventName": "UNC_H_CLOCK",
"PerPkg": "1",
- "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_STATE",
"Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB",
+ "EventCode": "0x17",
+ "EventName": "UNC_H_CORE_PMA.C1_STATE",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_TRANSITION",
"Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT",
+ "EventCode": "0x17",
+ "EventName": "UNC_H_CORE_PMA.C1_TRANSITION",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_STATE",
"Deprecated": "1",
- "EventCode": "0x5D",
- "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD",
+ "EventCode": "0x17",
+ "EventName": "UNC_H_CORE_PMA.C6_STATE",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_TRANSITION",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.EVICT",
+ "EventCode": "0x17",
+ "EventName": "UNC_H_CORE_PMA.C6_TRANSITION",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.GV",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.PRQ",
+ "EventCode": "0x17",
+ "EventName": "UNC_H_CORE_PMA.GV",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_GTONE",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.IPQ",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.ANY_GTONE",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0xe2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_ONE",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.HIT",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.ANY_ONE",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0xe1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_REMOTE",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.MISS",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.ANY_REMOTE",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0xe4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.EVICT",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.CORE_GTONE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x42",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_ONE",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.PRQ",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.CORE_ONE",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x41",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_REMOTE",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.IPQ",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.CORE_REMOTE",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.HIT",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.EVICT_GTONE",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x82",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_ONE",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.MISS",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.EVICT_ONE",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x81",
"Unit": "CHA"
},
{
- "BriefDescription": "WbPushMtoI; Pushed to LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x56",
- "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.EVICT_REMOTE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x84",
"Unit": "CHA"
},
{
- "BriefDescription": "WbPushMtoI; Pushed to Memory",
- "Counter": "0,1,2,3",
- "EventCode": "0x56",
- "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_GTONE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.EXT_GTONE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x22",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0",
- "Counter": "0,1,2,3",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_ONE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.EXT_ONE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1",
- "Counter": "0,1,2,3",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x33",
+ "EventName": "UNC_H_CORE_SNP.EXT_REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2",
- "Counter": "0,1,2,3",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_COUNTER0_OCCUPANCY",
+ "Deprecated": "1",
+ "EventCode": "0x1F",
+ "EventName": "UNC_H_COUNTER0_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3",
- "Counter": "0,1,2,3",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x53",
+ "EventName": "UNC_H_DIR_LOOKUP.NO_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4",
- "Counter": "0,1,2,3",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP",
+ "Deprecated": "1",
+ "EventCode": "0x53",
+ "EventName": "UNC_H_DIR_LOOKUP.SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5",
- "Counter": "0,1,2,3",
- "EventCode": "0x5A",
- "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA",
+ "Deprecated": "1",
+ "EventCode": "0x54",
+ "EventName": "UNC_H_DIR_UPDATE.HA",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.LOC_IO",
+ "EventCode": "0x54",
+ "EventName": "UNC_H_DIR_UPDATE.TOR",
"PerPkg": "1",
- "UMask": "0x34",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.LOC_IA",
+ "EventCode": "0xAE",
+ "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_DN",
"PerPkg": "1",
- "UMask": "0x31",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.LOC_ALL",
+ "EventCode": "0xAE",
+ "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
- "UMask": "0x37",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO",
+ "EventCode": "0x5F",
+ "EventName": "UNC_H_HITME_HIT.EX_RDS",
"PerPkg": "1",
- "UMask": "0x34",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.SHARED_OWNREQ",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA",
+ "EventCode": "0x5F",
+ "EventName": "UNC_H_HITME_HIT.SHARED_OWNREQ",
"PerPkg": "1",
- "UMask": "0x31",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOE",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL",
+ "EventCode": "0x5F",
+ "EventName": "UNC_H_HITME_HIT.WBMTOE",
"PerPkg": "1",
- "UMask": "0x37",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core PMA Events; C1 State",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_CHA_CORE_PMA.C1_STATE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOI_OR_S",
+ "Deprecated": "1",
+ "EventCode": "0x5F",
+ "EventName": "UNC_H_HITME_HIT.WBMTOI_OR_S",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Core PMA Events; C1 Transition",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.READ",
+ "Deprecated": "1",
+ "EventCode": "0x5E",
+ "EventName": "UNC_H_HITME_LOOKUP.READ",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core PMA Events; C6 State",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_CHA_CORE_PMA.C6_STATE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.WRITE",
+ "Deprecated": "1",
+ "EventCode": "0x5E",
+ "EventName": "UNC_H_HITME_LOOKUP.WRITE",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core PMA Events; C6 Transition",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN",
+ "Deprecated": "1",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_HITME_MISS.NOTSHARED_RDINVOWN",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Core PMA Events; GV",
- "Counter": "0,1,2,3",
- "EventCode": "0x17",
- "EventName": "UNC_CHA_CORE_PMA.GV",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.READ_OR_INV",
+ "Deprecated": "1",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_HITME_MISS.READ_OR_INV",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.SHARED_RDINVOWN",
+ "Deprecated": "1",
+ "EventCode": "0x60",
+ "EventName": "UNC_H_HITME_MISS.SHARED_RDINVOWN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE",
+ "Deprecated": "1",
+ "EventCode": "0x61",
+ "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
+ "Deprecated": "1",
+ "EventCode": "0x61",
+ "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RDINVOWN",
+ "Deprecated": "1",
+ "EventCode": "0x61",
+ "EventName": "UNC_H_HITME_UPDATE.RDINVOWN",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RSPFWDI_REM",
+ "Deprecated": "1",
+ "EventCode": "0x61",
+ "EventName": "UNC_H_HITME_UPDATE.RSPFWDI_REM",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x80",
- "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.SHARED",
+ "Deprecated": "1",
+ "EventCode": "0x61",
+ "EventName": "UNC_H_HITME_UPDATE.SHARED",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA7",
+ "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA7",
+ "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA7",
+ "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA7",
+ "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA9",
+ "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA9",
+ "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA9",
+ "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA9",
+ "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x88",
- "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xAB",
+ "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xAB",
+ "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xAB",
+ "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xAB",
+ "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+ "Deprecated": "1",
+ "EventCode": "0xAD",
+ "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+ "Deprecated": "1",
+ "EventCode": "0xAD",
+ "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x8A",
- "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.NORMAL",
+ "Deprecated": "1",
+ "EventCode": "0x59",
+ "EventName": "UNC_H_IMC_READS_COUNT.NORMAL",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.PRIORITY",
+ "Deprecated": "1",
+ "EventCode": "0x59",
+ "EventName": "UNC_H_IMC_READS_COUNT.PRIORITY",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL",
+ "Deprecated": "1",
+ "EventCode": "0x5B",
+ "EventName": "UNC_H_IMC_WRITES_COUNT.FULL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_MIG",
+ "Deprecated": "1",
+ "EventCode": "0x5B",
+ "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_MIG",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY",
+ "Deprecated": "1",
+ "EventCode": "0x5B",
+ "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_PRIORITY",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL",
+ "Deprecated": "1",
+ "EventCode": "0x5B",
+ "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG",
+ "Deprecated": "1",
+ "EventCode": "0x5B",
+ "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_MIG",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
+ "Deprecated": "1",
+ "EventCode": "0x5B",
+ "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_PRIORITY",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.INVITOM",
+ "Deprecated": "1",
+ "EventCode": "0x62",
+ "EventName": "UNC_H_IODC_ALLOC.INVITOM",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.IODCFULL",
+ "Deprecated": "1",
+ "EventCode": "0x62",
+ "EventName": "UNC_H_IODC_ALLOC.IODCFULL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.OSBGATED",
+ "Deprecated": "1",
+ "EventCode": "0x62",
+ "EventName": "UNC_H_IODC_ALLOC.OSBGATED",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.ALL",
+ "Deprecated": "1",
+ "EventCode": "0x63",
+ "EventName": "UNC_H_IODC_DEALLOC.ALL",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x86",
- "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.SNPOUT",
+ "Deprecated": "1",
+ "EventCode": "0x63",
+ "EventName": "UNC_H_IODC_DEALLOC.SNPOUT",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOE",
+ "Deprecated": "1",
+ "EventCode": "0x63",
+ "EventName": "UNC_H_IODC_DEALLOC.WBMTOE",
"PerPkg": "1",
"UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOI",
+ "Deprecated": "1",
+ "EventCode": "0x63",
+ "EventName": "UNC_H_IODC_DEALLOC.WBMTOI",
"PerPkg": "1",
"UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBPUSHMTOI",
+ "Deprecated": "1",
+ "EventCode": "0x63",
+ "EventName": "UNC_H_IODC_DEALLOC.WBPUSHMTOI",
"PerPkg": "1",
"UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_MISS",
+ "Deprecated": "1",
+ "EventCode": "0x39",
+ "EventName": "UNC_H_MISC.CV0_PREF_MISS",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_VIC",
+ "Deprecated": "1",
+ "EventCode": "0x39",
+ "EventName": "UNC_H_MISC.CV0_PREF_VIC",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x8E",
- "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S",
+ "Deprecated": "1",
+ "EventCode": "0x39",
+ "EventName": "UNC_H_MISC.RFO_HIT_S",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RSPI_WAS_FSE",
+ "Deprecated": "1",
+ "EventCode": "0x39",
+ "EventName": "UNC_H_MISC.RSPI_WAS_FSE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.WC_ALIASING",
+ "Deprecated": "1",
+ "EventCode": "0x39",
+ "EventName": "UNC_H_MISC.WC_ALIASING",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_OSB",
+ "Deprecated": "1",
+ "EventCode": "0x55",
+ "EventName": "UNC_H_OSB",
"PerPkg": "1",
- "UMask": "0x04",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC0_SMI2",
+ "Deprecated": "1",
+ "EventCode": "0x58",
+ "EventName": "UNC_H_READ_NO_CREDITS.EDC0_SMI2",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC1_SMI3",
+ "Deprecated": "1",
+ "EventCode": "0x58",
+ "EventName": "UNC_H_READ_NO_CREDITS.EDC1_SMI3",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0x8C",
- "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC2_SMI4",
+ "Deprecated": "1",
+ "EventCode": "0x58",
+ "EventName": "UNC_H_READ_NO_CREDITS.EDC2_SMI4",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC3_SMI5",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_H_CLOCK",
+ "EventCode": "0x58",
+ "EventName": "UNC_H_READ_NO_CREDITS.EDC3_SMI5",
"PerPkg": "1",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
- "Counter": "0,1,2,3",
- "EventCode": "0xAE",
- "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC0_SMI0",
+ "Deprecated": "1",
+ "EventCode": "0x58",
+ "EventName": "UNC_H_READ_NO_CREDITS.MC0_SMI0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
- "Counter": "0,1,2,3",
- "EventCode": "0xAE",
- "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC1_SMI1",
+ "Deprecated": "1",
+ "EventCode": "0x58",
+ "EventName": "UNC_H_READ_NO_CREDITS.MC1_SMI1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA7",
- "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD",
- "PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN",
- "PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
- "PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA9",
- "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD",
- "PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "read requests from home agent",
+ "Deprecated": "1",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.READS",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x3",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "read requests from local home agent",
+ "Deprecated": "1",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.READS_LOCAL",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "read requests from remote home agent",
+ "Deprecated": "1",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.READS_REMOTE",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAB",
- "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "write requests from home agent",
+ "Deprecated": "1",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.WRITES",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0xc",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal IV Ring in Use; Left",
- "Counter": "0,1,2,3",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "write requests from local home agent",
+ "Deprecated": "1",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Horizontal IV Ring in Use; Right",
- "Counter": "0,1,2,3",
- "EventCode": "0xAD",
- "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "write requests from remote home agent",
+ "Deprecated": "1",
+ "EventCode": "0x50",
+ "EventName": "UNC_H_REQUESTS.WRITES_REMOTE",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AD",
+ "Deprecated": "1",
"EventCode": "0xA1",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD",
+ "EventName": "UNC_H_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AK",
+ "Deprecated": "1",
"EventCode": "0xA1",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK",
+ "EventName": "UNC_H_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.BL",
+ "Deprecated": "1",
"EventCode": "0xA1",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL",
+ "EventName": "UNC_H_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.IV",
+ "Deprecated": "1",
"EventCode": "0xA1",
- "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV",
+ "EventName": "UNC_H_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AD",
+ "Deprecated": "1",
"EventCode": "0xA0",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD",
+ "EventName": "UNC_H_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AK",
+ "Deprecated": "1",
"EventCode": "0xA0",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK",
+ "EventName": "UNC_H_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.BL",
+ "Deprecated": "1",
"EventCode": "0xA0",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL",
+ "EventName": "UNC_H_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.IV",
+ "Deprecated": "1",
"EventCode": "0xA0",
- "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV",
+ "EventName": "UNC_H_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+ "Deprecated": "1",
"EventCode": "0xA3",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD",
+ "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+ "Deprecated": "1",
"EventCode": "0xA3",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK",
+ "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+ "Deprecated": "1",
"EventCode": "0xA3",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+ "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.BL",
+ "Deprecated": "1",
"EventCode": "0xA3",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+ "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.IV",
+ "Deprecated": "1",
"EventCode": "0xA3",
- "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1",
+ "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; AD",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AD",
+ "Deprecated": "1",
"EventCode": "0xA2",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD",
+ "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AK",
+ "Deprecated": "1",
"EventCode": "0xA2",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK",
+ "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.BL",
+ "Deprecated": "1",
"EventCode": "0xA2",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL",
+ "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.IV",
+ "Deprecated": "1",
"EventCode": "0xA2",
- "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV",
+ "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IPQ",
"Deprecated": "1",
- "EventCode": "0xA4",
- "EventName": "UNC_C_RING_SRC_THRTL",
+ "EventCode": "0x13",
+ "EventName": "UNC_H_RxC_INSERTS.IPQ",
"PerPkg": "1",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ",
+ "Deprecated": "1",
"EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ",
+ "EventName": "UNC_H_RxC_INSERTS.IRQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; IPQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ_REJ",
+ "Deprecated": "1",
"EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.IPQ",
+ "EventName": "UNC_H_RxC_INSERTS.IRQ_REJ",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ",
+ "Deprecated": "1",
"EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.PRQ",
+ "EventName": "UNC_H_RxC_INSERTS.PRQ",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; PRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ_REJ",
+ "Deprecated": "1",
"EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ",
+ "EventName": "UNC_H_RxC_INSERTS.PRQ_REJ",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; RRQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.RRQ",
+ "Deprecated": "1",
"EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.RRQ",
+ "EventName": "UNC_H_RxC_INSERTS.RRQ",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Allocations; WBQ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.WBQ",
+ "Deprecated": "1",
"EventCode": "0x13",
- "EventName": "UNC_CHA_RxC_INSERTS.WBQ",
+ "EventName": "UNC_H_RxC_INSERTS.WBQ",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+ "Deprecated": "1",
"EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0",
+ "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0",
+ "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
+ "Deprecated": "1",
"EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
+ "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
+ "Deprecated": "1",
"EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
+ "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0",
+ "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0",
+ "Deprecated": "1",
"EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0",
+ "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
"Deprecated": "1",
"EventCode": "0x23",
- "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x1",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; HA",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0",
+ "Deprecated": "1",
"EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.HA",
+ "Deprecated": "1",
"EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; SF Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+ "Deprecated": "1",
"EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
+ "Deprecated": "1",
"EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.VICTIM",
+ "Deprecated": "1",
"EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH",
+ "EventName": "UNC_H_RxC_IPQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+ "Deprecated": "1",
"EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0",
+ "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0",
+ "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+ "Deprecated": "1",
"EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+ "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
+ "Deprecated": "1",
"EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+ "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0",
+ "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0",
+ "Deprecated": "1",
"EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0",
+ "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x19",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.ALLOW_SNP",
+ "PerPkg": "1",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0",
- "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x19",
"EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0",
@@ -8013,170 +7931,169 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.HA",
+ "Deprecated": "1",
"EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+ "Deprecated": "1",
"EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
+ "Deprecated": "1",
"EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.VICTIM",
+ "Deprecated": "1",
"EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP",
+ "EventName": "UNC_H_RxC_IRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; AD REQ on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+ "Deprecated": "1",
"EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0",
+ "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; AD RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0",
+ "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; BL RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+ "Deprecated": "1",
"EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+ "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; BL WB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+ "Deprecated": "1",
"EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+ "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; BL NCB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0",
+ "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; BL NCS on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0",
+ "Deprecated": "1",
"EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0",
+ "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; AD REQ on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+ "Deprecated": "1",
"EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0",
+ "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; AD RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0",
+ "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; BL RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+ "Deprecated": "1",
"EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+ "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; BL WB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+ "Deprecated": "1",
"EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+ "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; BL NCB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0",
+ "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; BL NCS on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0",
+ "Deprecated": "1",
"EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0",
+ "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
- "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x25",
"EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0",
@@ -8185,17 +8102,16 @@
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Rejects; HA",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.HA",
+ "Deprecated": "1",
"EventCode": "0x25",
- "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA",
+ "EventName": "UNC_H_RxC_ISMQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
- "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x2D",
"EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY",
@@ -8204,95 +8120,115 @@
"Unit": "CHA"
},
{
- "BriefDescription": "ISMQ Retries; HA",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.HA",
+ "Deprecated": "1",
"EventCode": "0x2D",
- "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA",
+ "EventName": "UNC_H_RxC_ISMQ1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy; IPQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IPQ",
+ "Deprecated": "1",
"EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ",
+ "EventName": "UNC_H_RxC_OCCUPANCY.IPQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy; RRQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ",
+ "Deprecated": "1",
"EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ",
+ "EventName": "UNC_H_RxC_OCCUPANCY.IRQ",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.RRQ",
+ "Deprecated": "1",
+ "EventCode": "0x11",
+ "EventName": "UNC_H_RxC_OCCUPANCY.RRQ",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Occupancy; WBQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.WBQ",
+ "Deprecated": "1",
"EventCode": "0x11",
- "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ",
+ "EventName": "UNC_H_RxC_OCCUPANCY.WBQ",
"PerPkg": "1",
"UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; AD REQ on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+ "Deprecated": "1",
"EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0",
+ "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; AD RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0",
+ "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; BL RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+ "Deprecated": "1",
"EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+ "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; BL WB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+ "Deprecated": "1",
"EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+ "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; BL NCB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0",
+ "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; BL NCS on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0",
+ "Deprecated": "1",
"EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0",
+ "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x2F",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.ALLOW_SNP",
+ "PerPkg": "1",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0",
- "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x2F",
"EventName": "UNC_H_RxC_OTHER1_RETRY.ANY",
@@ -8301,125 +8237,124 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; HA",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.HA",
+ "Deprecated": "1",
"EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; LLC Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+ "Deprecated": "1",
"EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; SF Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+ "Deprecated": "1",
"EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; Allow Snoop",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.VICTIM",
+ "Deprecated": "1",
"EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP",
+ "EventName": "UNC_H_RxC_OTHER1_RETRY.VICTIM",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Other Retries; PhyAddr Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x20",
+ "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0",
+ "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+ "Deprecated": "1",
"EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0",
+ "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+ "Deprecated": "1",
"EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+ "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+ "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0",
+ "Deprecated": "1",
"EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0",
+ "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x21",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0",
- "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x21",
"EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0",
@@ -8428,125 +8363,124 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.HA",
+ "Deprecated": "1",
"EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+ "Deprecated": "1",
"EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+ "Deprecated": "1",
"EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.VICTIM",
+ "Deprecated": "1",
"EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP",
+ "EventName": "UNC_H_RxC_PRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x2A",
+ "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; AD REQ on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0",
+ "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; AD RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+ "Deprecated": "1",
"EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0",
+ "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; BL RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+ "Deprecated": "1",
"EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+ "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; BL WB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+ "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; BL NCB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0",
+ "Deprecated": "1",
"EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0",
+ "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; BL NCS on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x2B",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
- "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x2B",
"EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY",
@@ -8555,125 +8489,124 @@
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; HA",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+ "Deprecated": "1",
"EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.HA",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; LLC Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+ "Deprecated": "1",
"EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; SF Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+ "Deprecated": "1",
"EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; Allow Snoop",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM",
+ "Deprecated": "1",
"EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP",
+ "EventName": "UNC_H_RxC_REQ_Q1_RETRY.VICTIM",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Request Queue Retries; PhyAddr Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x26",
+ "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; AD REQ on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0",
+ "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; AD RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
+ "Deprecated": "1",
"EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0",
+ "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; BL RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
+ "Deprecated": "1",
"EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
+ "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; BL WB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
+ "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; BL NCB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0",
+ "Deprecated": "1",
"EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0",
+ "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; BL NCS on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x27",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0",
- "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x27",
"EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0",
@@ -8682,125 +8615,124 @@
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; HA",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.HA",
+ "Deprecated": "1",
"EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; LLC Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+ "Deprecated": "1",
"EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; SF Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
+ "Deprecated": "1",
"EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; Allow Snoop",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.VICTIM",
+ "Deprecated": "1",
"EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP",
+ "EventName": "UNC_H_RxC_RRQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "RRQ Rejects; PhyAddr Match",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
+ "Deprecated": "1",
+ "EventCode": "0x28",
+ "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_REQ_VN0",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; AD REQ on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0",
+ "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; AD RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
+ "Deprecated": "1",
"EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0",
+ "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCB_VN0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; BL RSP on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
+ "Deprecated": "1",
"EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
+ "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCS_VN0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; BL WB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0",
+ "Deprecated": "1",
"EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
+ "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_RSP_VN0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; BL NCB on VN0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0",
+ "Deprecated": "1",
"EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0",
+ "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_WB_VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; BL NCS on VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
+ "Deprecated": "1",
+ "EventCode": "0x29",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.ALLOW_SNP",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0",
- "Counter": "0,1,2,3",
"Deprecated": "1",
"EventCode": "0x29",
"EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0",
@@ -8809,3063 +8741,3161 @@
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; HA",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA",
- "PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "WBQ Rejects; LLC Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.HA",
+ "Deprecated": "1",
"EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.HA",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; SF Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+ "Deprecated": "1",
"EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; Victim",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_VICTIM",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
+ "Deprecated": "1",
"EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.PA_MATCH",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; Allow Snoop",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM",
+ "Deprecated": "1",
"EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.SF_VICTIM",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "WBQ Rejects; PhyAddr Match",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.VICTIM",
+ "Deprecated": "1",
"EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH",
+ "EventName": "UNC_H_RxC_WBQ1_REJECT.VICTIM",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_BNC",
+ "Deprecated": "1",
"EventCode": "0xB4",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC",
+ "EventName": "UNC_H_RxR_BUSY_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+ "Deprecated": "1",
"EventCode": "0xB4",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC",
+ "EventName": "UNC_H_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Credit",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_BNC",
+ "Deprecated": "1",
"EventCode": "0xB4",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD",
+ "EventName": "UNC_H_RxR_BUSY_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Credit",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+ "Deprecated": "1",
"EventCode": "0xB4",
- "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD",
+ "EventName": "UNC_H_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_BNC",
+ "Deprecated": "1",
"EventCode": "0xB2",
- "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC",
+ "EventName": "UNC_H_RxR_BYPASS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_CRD",
+ "Deprecated": "1",
"EventCode": "0xB2",
- "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC",
+ "EventName": "UNC_H_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AK_BNC",
+ "Deprecated": "1",
"EventCode": "0xB2",
- "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC",
+ "EventName": "UNC_H_RxR_BYPASS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_BNC",
+ "Deprecated": "1",
"EventCode": "0xB2",
- "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC",
+ "EventName": "UNC_H_RxR_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_CRD",
+ "Deprecated": "1",
"EventCode": "0xB2",
- "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD",
+ "EventName": "UNC_H_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.IV_BNC",
+ "Deprecated": "1",
"EventCode": "0xB2",
- "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD",
+ "EventName": "UNC_H_RxR_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_BNC",
+ "Deprecated": "1",
"EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC",
+ "EventName": "UNC_H_RxR_CRD_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+ "Deprecated": "1",
"EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC",
+ "EventName": "UNC_H_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AK_BNC",
+ "Deprecated": "1",
"EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC",
+ "EventName": "UNC_H_RxR_CRD_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_BNC",
+ "Deprecated": "1",
"EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC",
+ "EventName": "UNC_H_RxR_CRD_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Credit",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+ "Deprecated": "1",
"EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD",
+ "EventName": "UNC_H_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Credit",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IFV",
+ "Deprecated": "1",
"EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD",
+ "EventName": "UNC_H_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IV_BNC",
+ "Deprecated": "1",
"EventCode": "0xB3",
- "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV",
+ "EventName": "UNC_H_RxR_CRD_STARVED.IV_BNC",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_BNC",
+ "Deprecated": "1",
"EventCode": "0xB1",
- "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC",
+ "EventName": "UNC_H_RxR_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_CRD",
+ "Deprecated": "1",
"EventCode": "0xB1",
- "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC",
+ "EventName": "UNC_H_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AK_BNC",
+ "Deprecated": "1",
"EventCode": "0xB1",
- "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC",
+ "EventName": "UNC_H_RxR_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_BNC",
+ "Deprecated": "1",
"EventCode": "0xB1",
- "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC",
+ "EventName": "UNC_H_RxR_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_CRD",
+ "Deprecated": "1",
"EventCode": "0xB1",
- "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD",
+ "EventName": "UNC_H_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.IV_BNC",
+ "Deprecated": "1",
"EventCode": "0xB1",
- "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD",
+ "EventName": "UNC_H_RxR_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_BNC",
+ "Deprecated": "1",
"EventCode": "0xB0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC",
+ "EventName": "UNC_H_RxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+ "Deprecated": "1",
"EventCode": "0xB0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC",
+ "EventName": "UNC_H_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AK_BNC",
+ "Deprecated": "1",
"EventCode": "0xB0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC",
+ "EventName": "UNC_H_RxR_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_BNC",
+ "Deprecated": "1",
"EventCode": "0xB0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC",
+ "EventName": "UNC_H_RxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+ "Deprecated": "1",
"EventCode": "0xB0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD",
+ "EventName": "UNC_H_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.IV_BNC",
+ "Deprecated": "1",
"EventCode": "0xB0",
- "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD",
+ "EventName": "UNC_H_RxR_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.E_STATE",
+ "Deprecated": "1",
+ "EventCode": "0x3D",
+ "EventName": "UNC_H_SF_EVICTION.E_STATE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.M_STATE",
+ "Deprecated": "1",
+ "EventCode": "0x3D",
+ "EventName": "UNC_H_SF_EVICTION.M_STATE",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.S_STATE",
+ "Deprecated": "1",
+ "EventCode": "0x3D",
+ "EventName": "UNC_H_SF_EVICTION.S_STATE",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD0",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.BCST_REM",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.LOCAL",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.LOCAL",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.REMOTE",
+ "Deprecated": "1",
+ "EventCode": "0x51",
+ "EventName": "UNC_H_SNOOPS_SENT.REMOTE",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD2",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPFWD",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSPFWD",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPI",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSPI",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPS",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSPS",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB",
+ "Deprecated": "1",
+ "EventCode": "0x5C",
+ "EventName": "UNC_H_SNOOP_RESP.RSP_WB",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD4",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x80",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2,3",
- "EventCode": "0xD6",
- "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
+ "Deprecated": "1",
+ "EventCode": "0x5D",
+ "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9D",
- "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x9F",
- "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x96",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "Deprecated": "1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "Deprecated": "1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "Deprecated": "1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x97",
- "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "Deprecated": "1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "Deprecated": "1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "Deprecated": "1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_H_TxR_HORZ_ADS_USED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x95",
- "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x9D",
+ "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9F",
+ "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x9F",
+ "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9F",
+ "EventName": "UNC_H_TxR_HORZ_BYPASS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9F",
+ "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x99",
- "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x9F",
+ "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9F",
+ "EventName": "UNC_H_TxR_HORZ_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x96",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x96",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x96",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AK_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x96",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
- "Counter": "0,1,2,3",
- "EventCode": "0x94",
- "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x96",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x96",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.IV_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x97",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x97",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
- "Counter": "0,1,2,3",
- "EventCode": "0x9B",
- "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x97",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AK_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x97",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x97",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x97",
+ "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.IV_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x95",
+ "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_BNC",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "CHA"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x95",
+ "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x95",
+ "EventName": "UNC_H_TxR_HORZ_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9C",
- "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x95",
+ "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x95",
+ "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x95",
+ "EventName": "UNC_H_TxR_HORZ_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x99",
+ "EventName": "UNC_H_TxR_HORZ_NACK.AD_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_CRD",
"Deprecated": "1",
- "EventCode": "0x9E",
- "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1",
+ "EventCode": "0x99",
+ "EventName": "UNC_H_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x99",
+ "EventName": "UNC_H_TxR_HORZ_NACK.AK_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x99",
+ "EventName": "UNC_H_TxR_HORZ_NACK.BL_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x99",
+ "EventName": "UNC_H_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
"UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x99",
+ "EventName": "UNC_H_TxR_HORZ_NACK.IV_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x94",
+ "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x94",
+ "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC",
"Deprecated": "1",
- "EventCode": "0x92",
- "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0",
+ "EventCode": "0x94",
+ "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x94",
+ "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "Deprecated": "1",
+ "EventCode": "0x94",
+ "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x94",
+ "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AD_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_H_TxR_HORZ_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AK_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_H_TxR_HORZ_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.BL_BNC",
+ "Deprecated": "1",
+ "EventCode": "0x9B",
+ "EventName": "UNC_H_TxR_HORZ_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.IV_BNC",
"Deprecated": "1",
- "EventCode": "0x93",
- "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0",
+ "EventCode": "0x9B",
+ "EventName": "UNC_H_TxR_HORZ_STARVED.IV_BNC",
"PerPkg": "1",
"UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG0",
"Deprecated": "1",
- "EventCode": "0x91",
- "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV",
+ "Deprecated": "1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.IV",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x98",
- "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
+ "Deprecated": "1",
+ "EventCode": "0x92",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0",
"Deprecated": "1",
- "EventCode": "0x90",
- "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG0",
"PerPkg": "1",
- "UMask": "0x8",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV",
+ "Deprecated": "1",
+ "EventCode": "0x93",
+ "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.IV",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG1",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x9A",
- "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV",
+ "Deprecated": "1",
+ "EventCode": "0x91",
+ "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA6",
- "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA8",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.AD_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA8",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.AK_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Down and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xA8",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.AK_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xA8",
- "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.BL_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Up and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.IV",
+ "Deprecated": "1",
+ "EventCode": "0x98",
+ "EventName": "UNC_H_TxR_VERT_NACK.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Down and Even",
- "Counter": "0,1,2,3",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
- "Counter": "0,1,2,3",
- "EventCode": "0xAA",
- "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical IV Ring in Use; Up",
- "Counter": "0,1,2,3",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Vertical IV Ring in Use; Down",
- "Counter": "0,1,2,3",
- "EventCode": "0xAC",
- "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG0",
"PerPkg": "1",
- "UMask": "0x21",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG1",
"PerPkg": "1",
- "UMask": "0x41",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV",
+ "Deprecated": "1",
+ "EventCode": "0x90",
+ "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0",
"PerPkg": "1",
- "UMask": "0x81",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG0",
"PerPkg": "1",
- "UMask": "0xE1",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x22",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x42",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG1",
"PerPkg": "1",
- "UMask": "0x82",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG0",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG0",
"PerPkg": "1",
- "UMask": "0xE2",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG1",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x24",
+ "UMask": "0x40",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.IV",
+ "Deprecated": "1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_H_TxR_VERT_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x44",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA6",
+ "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x84",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA6",
+ "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0xE4",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA6",
+ "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x28",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA6",
+ "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x48",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA8",
+ "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x88",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA8",
+ "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0xE8",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xA8",
+ "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x30",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xA8",
+ "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x50",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN",
+ "Deprecated": "1",
+ "EventCode": "0xAA",
+ "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x90",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "Core Cross Snoop Responses",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD",
+ "Deprecated": "1",
+ "EventCode": "0xAA",
+ "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0xF0",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT",
+ "EventCode": "0xAA",
+ "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x18",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS",
+ "EventCode": "0xAA",
+ "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x28",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.DN",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT",
+ "EventCode": "0xAC",
+ "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x50",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.UP",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS",
+ "EventCode": "0xAC",
+ "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x60",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.LLC",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT",
+ "EventCode": "0x56",
+ "EventName": "UNC_H_WB_PUSH_MTOI.LLC",
"PerPkg": "1",
- "UMask": "0x90",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.MEM",
"Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS",
+ "EventCode": "0x56",
+ "EventName": "UNC_H_WB_PUSH_MTOI.MEM",
"PerPkg": "1",
- "UMask": "0xA0",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT",
+ "EventCode": "0x5A",
+ "EventName": "UNC_H_WRITE_NO_CREDITS.EDC0_SMI2",
"PerPkg": "1",
- "UMask": "0x14",
+ "UMask": "0x4",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS",
+ "EventCode": "0x5A",
+ "EventName": "UNC_H_WRITE_NO_CREDITS.EDC1_SMI3",
"PerPkg": "1",
- "UMask": "0x24",
+ "UMask": "0x8",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT",
+ "EventCode": "0x5A",
+ "EventName": "UNC_H_WRITE_NO_CREDITS.EDC2_SMI4",
"PerPkg": "1",
- "UMask": "0x18",
+ "UMask": "0x10",
"Unit": "CHA"
},
{
- "BriefDescription": "This event is deprecated. ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5",
"Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS",
+ "EventCode": "0x5A",
+ "EventName": "UNC_H_WRITE_NO_CREDITS.EDC3_SMI5",
"PerPkg": "1",
- "UMask": "0x28",
+ "UMask": "0x20",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; All from Local IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0",
+ "Deprecated": "1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_H_WRITE_NO_CREDITS.MC0_SMI0",
"PerPkg": "1",
- "UMask": "0x34",
+ "UMask": "0x1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; All from Local iA and IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1",
+ "Deprecated": "1",
+ "EventCode": "0x5A",
+ "EventName": "UNC_H_WRITE_NO_CREDITS.MC1_SMI1",
"PerPkg": "1",
- "UMask": "0x35",
+ "UMask": "0x2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Hits from Local",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDFE",
"PerPkg": "1",
- "UMask": "0x15",
+ "UMask": "0xe4",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Inserts; Misses from Local",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDM",
"PerPkg": "1",
- "UMask": "0x25",
+ "UMask": "0xf0",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; All from Local IO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDFE",
"PerPkg": "1",
- "UMask": "0x34",
+ "UMask": "0xe2",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Hits from Local IO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDM",
"PerPkg": "1",
- "UMask": "0x14",
+ "UMask": "0xe8",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Misses from Local IO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.ANY_RSP_HITFSE",
"PerPkg": "1",
- "UMask": "0x24",
+ "UMask": "0xe1",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Hits from Local",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDFE",
"PerPkg": "1",
- "UMask": "0x17",
+ "UMask": "0x44",
"Unit": "CHA"
},
{
- "BriefDescription": "TOR Occupancy; Misses from Local",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDM",
"PerPkg": "1",
- "UMask": "0x27",
+ "UMask": "0x50",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDFE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x42",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDM",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x48",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.CORE_RSP_HITFSE",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x41",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDFE",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x84",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDM",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x90",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDFE",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x82",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDM",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x88",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EVICT_RSP_HITFSE",
"PerPkg": "1",
- "UMask": "0x80",
+ "UMask": "0x81",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDFE",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x24",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDM",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x30",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDFE",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x22",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDM",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x28",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE",
+ "Deprecated": "1",
+ "EventCode": "0x32",
+ "EventName": "UNC_H_XSNP_RESP.EXT_RSP_HITFSE",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x21",
"Unit": "CHA"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB",
+ "BriefDescription": "Clockticks of the IIO Traffic Controller",
+ "EventCode": "0x1",
+ "EventName": "UNC_IIO_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PublicDescription": "Counts clockticks of the 1GHz traffic controller clock in the IIO unit.",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits",
- "EventCode": "0x3B",
- "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS",
+ "FCMask": "0x4",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PortMask": "0x0f",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0",
+ "FCMask": "0x4",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1",
+ "FCMask": "0x4",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2",
+ "FCMask": "0x4",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3",
+ "FCMask": "0x4",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "UMask": "0x3",
+ "Unit": "IIO"
},
{
- "BriefDescription": "ISMQ Rejects; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "PCIe Completion Buffer Inserts; Port 0",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "ISMQ Rejects; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "PCIe Completion Buffer Inserts; Port 1",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "ISMQ Retries; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI",
+ "BriefDescription": "PCIe Completion Buffer Inserts; Port 2",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "ISMQ Retries; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x2C",
- "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI",
+ "BriefDescription": "PCIe Completion Buffer Inserts; Port 3",
+ "EventCode": "0xC2",
+ "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Other Retries; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI",
+ "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3",
+ "EventCode": "0xD5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0xf",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Other Retries; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x2E",
- "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI",
+ "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0",
+ "EventCode": "0xD5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1",
+ "EventCode": "0xD5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2",
+ "EventCode": "0xD5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Request Queue Retries; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI",
+ "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3",
+ "EventCode": "0xD5",
+ "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3",
+ "FCMask": "0x04",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Request Queue Retries; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RRQ Rejects; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
"UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "RRQ Rejects; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "WBQ Rejects; Non UPI AK Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
"UMask": "0x40",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "WBQ Rejects; Non UPI IV Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Request Queue Retries; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2B",
- "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoops Sent; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.ALL",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
"UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoops Sent; Directed snoops for Local Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x51",
- "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspI",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspS",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspIFwd",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspSFwd",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses Received Local; Rsp*WB",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspCnflct",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x80",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Snoop Responses Received Local; RspFwd",
- "Counter": "0,1,2,3",
- "EventCode": "0x5D",
- "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
"EventCode": "0xC0",
- "EventName": "UNC_CHA_CMS_CLOCKTICKS",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x03",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.WRITE",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x05",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x09",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Any Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.ANY",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x11",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Local",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL",
+ "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x31",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cache and Snoop Filter Lookups; Remote",
- "Counter": "0,1,2,3",
- "EventCode": "0x34",
- "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE",
+ "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x91",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE",
+ "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE",
+ "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE",
+ "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Lines Victimized; Local - All Lines",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL",
+ "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x2F",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE",
+ "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; IRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IRQ",
+ "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; SF/LLC Evictions",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.EVICT",
+ "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; PRQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.PRQ",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; IPQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IPQ",
+ "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; Hit (Not a Miss)",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.HIT",
+ "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; Miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.MISS",
+ "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL",
+ "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x37",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; All",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.ALL",
+ "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xFF",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT",
+ "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x18",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS",
+ "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x28",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT",
+ "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x50",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS",
+ "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x60",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT",
+ "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x90",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS",
+ "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xA0",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; IRQ",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ",
+ "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; SF/LLC Evictions",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT",
+ "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; PRQ",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ",
+ "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; IPQ",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ",
+ "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; Hit (Not a Miss)",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT",
+ "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
"UMask": "0x10",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; Miss",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS",
+ "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL",
+ "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x37",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.ALL",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL",
+ "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0xFF",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+ "UMask": "0x10",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT",
+ "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x18",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Deprecated": "1",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS",
+ "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x28",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2,3",
- "EventCode": "0xA4",
- "EventName": "UNC_CHA_RING_SRC_THRTL",
+ "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Ingress Probe Queue Rejects; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x23",
- "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0",
+ "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3",
+ "UMask": "0x20",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x19",
- "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0",
+ "BriefDescription": "PCI Express bandwidth reading at IIO, part 0",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "ISMQ Rejects; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x25",
- "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0",
+ "BriefDescription": "PCI Express bandwidth reading at IIO, part 1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "ISMQ Retries; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2D",
- "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0",
+ "BriefDescription": "PCI Express bandwidth reading at IIO, part 2",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Other Retries; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2F",
- "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0",
+ "BriefDescription": "PCI Express bandwidth reading at IIO, part 3",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x21",
- "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0",
+ "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "RRQ Rejects; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x27",
- "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0",
+ "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+ "UMask": "0x4",
+ "Unit": "IIO"
},
{
- "BriefDescription": "WBQ Rejects; ANY0",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0",
+ "BriefDescription": "PCI Express bandwidth writing at IIO, part 0",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit onthe main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
"UMask": "0x1",
- "Unit": "CHA"
+ "Unit": "IIO"
},
{
- "BriefDescription": "CMS Vertical ADS Used; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x9E",
- "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV",
+ "BriefDescription": "PCI Express bandwidth writing at IIO, part 1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x92",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV",
+ "BriefDescription": "PCI Express bandwidth writing at IIO, part 2",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x93",
- "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV",
+ "BriefDescription": "PCI Express bandwidth writing at IIO, part 3",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x91",
- "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV",
+ "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; IV",
- "Counter": "0,1,2,3",
- "EventCode": "0x90",
- "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV",
+ "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
},
{
- "BriefDescription": "FaST wire asserted; Vertical",
- "Counter": "0,1,2,3",
- "EventCode": "0xA5",
- "EventName": "UNC_CHA_FAST_ASSERTED.VERT",
+ "BriefDescription": "Data requested of the CPU; Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL",
+ "BriefDescription": "Data requested of the CPU; Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Lines Victimized; Local - Lines in M State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M",
+ "BriefDescription": "Data requested of the CPU; Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x21",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Lines Victimized; Local - Lines in E State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E",
+ "BriefDescription": "Data requested of the CPU; Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x22",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Lines Victimized; Local - Lines in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S",
- "PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Lines Victimized; Local - Lines in F State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F",
- "PerPkg": "1",
- "UMask": "0x28",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Lines Victimized; Remote - Lines in M State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M",
- "PerPkg": "1",
- "UMask": "0x81",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Lines Victimized; Remote - Lines in E State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E",
- "PerPkg": "1",
- "UMask": "0x82",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Lines Victimized; Remote - Lines in S State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S",
- "PerPkg": "1",
- "UMask": "0x84",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Lines Victimized; Remote - Lines in F State",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F",
- "PerPkg": "1",
- "UMask": "0x88",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "Lines Victimized; Remote - All Lines",
- "Counter": "0,1,2,3",
- "EventCode": "0x37",
- "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL",
- "PerPkg": "1",
- "UMask": "0x8F",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "TOR Occupancy; All from Local",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC",
- "PerPkg": "1",
- "UMask": "0x37",
- "Unit": "CHA"
- },
- {
- "BriefDescription": "TOR Inserts; RdCur misses from Local IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR",
- "Filter": "config1=0x43C33",
- "PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; RFO misses from Local IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO",
- "Filter": "config1=0x40033",
+ "BriefDescription": "Data requested of the CPU; Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Inserts; ItoM misses from Local IO",
- "Counter": "0,1,2,3",
- "EventCode": "0x35",
- "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM",
- "Filter": "config1=0x49033",
+ "BriefDescription": "Data requested of the CPU; Messages",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+ "UMask": "0x40",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM",
- "Filter": "config1=0x49033",
+ "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RDCUR isses from Local IO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR",
- "Filter": "config1=0x43C33",
+ "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "TOR Occupancy; RFO misses from Local IO",
- "EventCode": "0x36",
- "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO",
- "Filter": "config1=0x40033",
+ "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x24",
- "Unit": "CHA"
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in IODC",
- "Counter": "0,1,2,3",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.IODC",
+ "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC",
+ "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "CHA"
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC",
- "Counter": "0,1,2,3",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF",
+ "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "CHA"
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in TOR",
- "Counter": "0,1,2,3",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR",
+ "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "CHA"
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Memory mode related events; Counts the number of times CHA saw NM Set conflict in TOR and the transaction was rejected",
- "Counter": "0,1,2,3",
- "EventCode": "0x64",
- "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR_REJECT",
+ "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "CHA"
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts; Port 0",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0",
- "FCMask": "0x7",
+ "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x04",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts; Port 1",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1",
- "FCMask": "0x7",
+ "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x04",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts; Port 2",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2",
- "FCMask": "0x7",
+ "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x04",
+ "PortMask": "0x10",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "PCIe Completion Buffer Inserts; Port 3",
- "Counter": "0,1,2,3",
- "EventCode": "0xC2",
- "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3",
- "FCMask": "0x7",
+ "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x04",
+ "PortMask": "0x20",
+ "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
"BriefDescription": "Num Link Correctable Errors",
- "Counter": "0,1,2,3",
"EventCode": "0xF",
"EventName": "UNC_IIO_LINK_NUM_CORR_ERR",
"PerPkg": "1",
@@ -11873,7 +11903,6 @@
},
{
"BriefDescription": "Num Link Retries",
- "Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_IIO_LINK_NUM_RETRIES",
"PerPkg": "1",
@@ -11881,7 +11910,6 @@
},
{
"BriefDescription": "Number packets that passed the Mask/Match Filter",
- "Counter": "0,1,2,3",
"EventCode": "0x21",
"EventName": "UNC_IIO_MASK_MATCH",
"PerPkg": "1",
@@ -11889,314 +11917,362 @@
},
{
"BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_IIO_MASK_MATCH_AND.BUS0",
"PerPkg": "1",
+ "PublicDescription": "Asserted if all bits specified by mask match",
"UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus; PCIE bus",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus",
"EventCode": "0x2",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Asserted if all bits specified by mask match",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
"BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1",
"PerPkg": "1",
+ "PublicDescription": "Asserted if all bits specified by mask match",
"UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus",
- "Counter": "0,1,2,3",
+ "BriefDescription": "AND Mask/match for debug bus; PCIE bus",
"EventCode": "0x2",
- "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1",
+ "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Asserted if all bits specified by mask match",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
"BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1",
"PerPkg": "1",
+ "PublicDescription": "Asserted if all bits specified by mask match",
"UMask": "0x10",
"Unit": "IIO"
},
{
"BriefDescription": "AND Mask/match for debug bus",
- "Counter": "0,1,2,3",
"EventCode": "0x2",
"EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1",
"PerPkg": "1",
+ "PublicDescription": "Asserted if all bits specified by mask match",
"UMask": "0x20",
"Unit": "IIO"
},
{
"BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_IIO_MASK_MATCH_OR.BUS0",
"PerPkg": "1",
+ "PublicDescription": "Asserted if any bits specified by mask match",
"UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus; PCIE bus",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus",
"EventCode": "0x3",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Asserted if any bits specified by mask match",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
"BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1",
"PerPkg": "1",
+ "PublicDescription": "Asserted if any bits specified by mask match",
"UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus",
- "Counter": "0,1,2,3",
+ "BriefDescription": "OR Mask/match for debug bus; PCIE bus",
"EventCode": "0x3",
- "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1",
+ "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Asserted if any bits specified by mask match",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
"BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1",
"PerPkg": "1",
+ "PublicDescription": "Asserted if any bits specified by mask match",
"UMask": "0x10",
"Unit": "IIO"
},
{
"BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus)",
- "Counter": "0,1,2,3",
"EventCode": "0x3",
"EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1",
"PerPkg": "1",
+ "PublicDescription": "Asserted if any bits specified by mask match",
"UMask": "0x20",
"Unit": "IIO"
},
{
"BriefDescription": "UNC_IIO_NOTHING",
- "Counter": "0,1,2,3",
"EventName": "UNC_IIO_NOTHING",
"PerPkg": "1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x8",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x8",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x8",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x8",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3",
"Deprecated": "1",
"EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x20",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
+ "Deprecated": "1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
- "Counter": "0,1",
"Deprecated": "1",
"EventCode": "0x83",
"EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0",
@@ -12208,7 +12284,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
- "Counter": "0,1",
"Deprecated": "1",
"EventCode": "0x83",
"EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1",
@@ -12220,7 +12295,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
- "Counter": "0,1",
"Deprecated": "1",
"EventCode": "0x83",
"EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2",
@@ -12232,7 +12306,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
- "Counter": "0,1",
"Deprecated": "1",
"EventCode": "0x83",
"EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3",
@@ -12243,344 +12316,293 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x1",
+ "PortMask": "0x10",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x1",
+ "PortMask": "0x20",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x1",
+ "PortMask": "0x1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x1",
+ "PortMask": "0x2",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x2",
+ "PortMask": "0x4",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x2",
+ "PortMask": "0x8",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x2",
+ "PortMask": "0x10",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x2",
+ "PortMask": "0x20",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x4",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
- "Counter": "2,3",
- "Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0",
- "FCMask": "0x7",
- "PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x8",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
- "Counter": "2,3",
- "Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1",
- "FCMask": "0x7",
- "PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x8",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x8",
+ "PortMask": "0x10",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3",
+ "EventCode": "0x83",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x8",
+ "PortMask": "0x20",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x10",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x10",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x10",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x10",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x20",
+ "PortMask": "0x10",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x20",
+ "PortMask": "0x20",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x20",
+ "PortMask": "0x1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x20",
+ "PortMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x40",
+ "PortMask": "0x4",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x40",
+ "PortMask": "0x8",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x40",
+ "PortMask": "0x10",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
"Deprecated": "1",
"EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x40",
+ "PortMask": "0x20",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
- "Counter": "2,3",
"Deprecated": "1",
"EventCode": "0xC0",
"EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0",
@@ -12592,7 +12614,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
- "Counter": "2,3",
"Deprecated": "1",
"EventCode": "0xC0",
"EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1",
@@ -12604,7 +12625,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
- "Counter": "2,3",
"Deprecated": "1",
"EventCode": "0xC0",
"EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2",
@@ -12616,7 +12636,6 @@
},
{
"BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
- "Counter": "2,3",
"Deprecated": "1",
"EventCode": "0xC0",
"EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3",
@@ -12627,115 +12646,98 @@
"Unit": "IIO"
},
{
- "BriefDescription": "Symbol Times on Link",
- "Counter": "0,1,2,3",
- "EventCode": "0x82",
- "EventName": "UNC_IIO_SYMBOL_TIMES",
- "PerPkg": "1",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x1",
+ "PortMask": "0x10",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x1",
+ "PortMask": "0x20",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x1",
+ "PortMask": "0x1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x1",
+ "PortMask": "0x2",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x2",
+ "PortMask": "0x4",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x2",
+ "PortMask": "0x8",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x2",
+ "PortMask": "0x10",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x2",
+ "PortMask": "0x20",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
@@ -12743,11 +12745,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
@@ -12755,11 +12756,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
@@ -12767,11 +12767,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
@@ -12779,491 +12778,480 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x8",
+ "PortMask": "0x10",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x8",
+ "PortMask": "0x20",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x8",
+ "PortMask": "0x1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x8",
+ "PortMask": "0x2",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x10",
+ "PortMask": "0x4",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x10",
+ "PortMask": "0x8",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x10",
+ "PortMask": "0x10",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x10",
+ "PortMask": "0x20",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x20",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MSG.PART0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x40",
+ "PortMask": "0x10",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MSG.PART1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x40",
+ "PortMask": "0x20",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MSG.PART2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x40",
+ "PortMask": "0x1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MSG.PART3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x40",
+ "PortMask": "0x2",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x1",
+ "PortMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x1",
+ "PortMask": "0x8",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x1",
+ "PortMask": "0x10",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3",
+ "EventCode": "0xC0",
+ "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x1",
+ "PortMask": "0x20",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "Symbol Times on Link",
+ "EventCode": "0x82",
+ "EventName": "UNC_IIO_SYMBOL_TIMES",
+ "PerPkg": "1",
+ "PublicDescription": "Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x4",
+ "PortMask": "0x10",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x4",
+ "PortMask": "0x20",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x4",
+ "PortMask": "0x1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x4",
+ "PortMask": "0x2",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x8",
+ "PortMask": "0x4",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x8",
+ "PortMask": "0x8",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x8",
+ "PortMask": "0x1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x8",
+ "PortMask": "0x2",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x10",
+ "PortMask": "0x4",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x10",
+ "PortMask": "0x8",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x10",
+ "PortMask": "0x10",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x10",
+ "PortMask": "0x20",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
- "UMask": "0x20",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MSG.PART0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x1",
@@ -13271,11 +13259,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MSG.PART1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x2",
@@ -13283,11 +13270,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MSG.PART2",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x4",
@@ -13295,11 +13281,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MSG.PART3",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x8",
@@ -13307,211 +13292,208 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MSG.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x1",
- "UMask": "0x80",
+ "PortMask": "0x10",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.MSG.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x2",
- "UMask": "0x80",
+ "PortMask": "0x20",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x4",
- "UMask": "0x80",
+ "PortMask": "0x1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x8",
- "UMask": "0x80",
+ "PortMask": "0x2",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "VTd Access; Vtd hit",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x1",
+ "PortMask": "0x4",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "VTd Access; context cache miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x2",
+ "PortMask": "0x8",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "VTd Access; L1 miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x4",
+ "PortMask": "0x10",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "VTd Access; L2 miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1",
+ "FCMask": "0x7",
"PerPkg": "1",
+ "PortMask": "0x20",
"UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "VTd Access; L3 miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x10",
+ "PortMask": "0x1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "VTd Access; TLB miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x20",
+ "PortMask": "0x2",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "VTd Access; TLB is full",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x40",
+ "PortMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "VTd Access; TLB miss",
- "Counter": "0,1,2,3",
- "EventCode": "0x41",
- "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3",
+ "FCMask": "0x7",
"PerPkg": "1",
- "UMask": "0x80",
+ "PortMask": "0x8",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "VTd Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_IIO_VTD_OCCUPANCY",
- "PerPkg": "1",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x10",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x4",
+ "PortMask": "0x1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x4",
+ "PortMask": "0x2",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x1",
+ "PortMask": "0x4",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x1",
+ "PortMask": "0x8",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
@@ -13519,11 +13501,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
@@ -13531,107 +13512,109 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x8",
+ "PortMask": "0x1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x8",
+ "PortMask": "0x2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x2",
+ "PortMask": "0x4",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
- "Counter": "0,1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x2",
+ "PortMask": "0x8",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x40",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
+ "PortMask": "0x1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
+ "PortMask": "0x2",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
+ "PortMask": "0x4",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3",
+ "FCMask": "0x7",
+ "PerPkg": "1",
+ "PortMask": "0x8",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
+ "Deprecated": "1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
@@ -13639,11 +13622,10 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
@@ -13651,9304 +13633,12704 @@
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
+ "PortMask": "0x1",
"UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
+ "PortMask": "0x2",
"UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x4",
+ "PortMask": "0x4",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x4",
+ "PortMask": "0x8",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x8",
+ "PortMask": "0x1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x8",
+ "PortMask": "0x2",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x2",
+ "PortMask": "0x4",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
- "Counter": "2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
"Deprecated": "1",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x2",
+ "PortMask": "0x8",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x10",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x4",
+ "PortMask": "0x1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x4",
+ "PortMask": "0x2",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
+ "PortMask": "0x4",
"UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
+ "PortMask": "0x8",
"UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MSG.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.MSG.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x40",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
+ "PortMask": "0x1",
"UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
+ "PortMask": "0x2",
"UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x2",
+ "PortMask": "0x4",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
"Deprecated": "1",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x2",
+ "PortMask": "0x8",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
"Deprecated": "1",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
"Deprecated": "1",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x40",
- "Unit": "IIO"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0",
- "FCMask": "0x7",
- "PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
"Deprecated": "1",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
+ "PortMask": "0x1",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
"Deprecated": "1",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
+ "PortMask": "0x2",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
"Deprecated": "1",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x20",
+ "PortMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
"Deprecated": "1",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3",
"FCMask": "0x7",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x20",
+ "PortMask": "0x8",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
"Deprecated": "1",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
"Deprecated": "1",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1",
+ "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1",
"FCMask": "0x7",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x4",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x1",
+ "PortMask": "0x01",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x1",
+ "PortMask": "0x02",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x8",
+ "PortMask": "0x04",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
+ "FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x8",
+ "PortMask": "0x08",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
+ "FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x2",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
"EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1",
- "FCMask": "0x7",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
+ "FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x2",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x20",
+ "PortMask": "0x10",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x20",
+ "PortMask": "0x20",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x20",
+ "PortMask": "0x01",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x20",
+ "PortMask": "0x02",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
+ "PortMask": "0x04",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
+ "PortMask": "0x08",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
+ "PortMask": "0x10",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
+ "PortMask": "0x20",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x80",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x80",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x80",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x80",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x80",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x40",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x40",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x20",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x20",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x08",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1",
+ "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x08",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0",
+ "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card",
- "Counter": "2,3",
- "EventCode": "0xC0",
- "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1",
+ "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0",
+ "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1",
+ "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x10",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2",
+ "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x10",
+ "PortMask": "0x10",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3",
+ "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x10",
+ "PortMask": "0x20",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0",
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x20",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1",
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x20",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2",
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x20",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3",
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x20",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Messages",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0",
+ "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.",
+ "EventCode": "0xC1",
+ "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x40",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Messages",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1",
+ "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x40",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Messages",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2",
+ "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x40",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Messages",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3",
+ "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x40",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3",
+ "UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0",
+ "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1",
+ "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
"UMask": "0x10",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0",
+ "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
+ "PortMask": "0x01",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card reading from DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1",
+ "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
+ "PortMask": "0x02",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0",
+ "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
+ "PortMask": "0x04",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card writing to DRAM",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1",
+ "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
+ "PortMask": "0x08",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3",
+ "UMask": "0x20",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Messages",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Messages",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
+ "PortMask": "0x04",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1",
+ "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0",
+ "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x10",
- "UMask": "0x02",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)",
- "Counter": "0,1",
- "EventCode": "0x83",
- "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1",
+ "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x20",
- "UMask": "0x02",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+ "UMask": "0x4",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x10",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x10",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x10",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3",
+ "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x10",
+ "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0",
+ "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x20",
+ "PortMask": "0x10",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+ "UMask": "0x1",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1",
+ "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested of the CPU; Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested of the CPU; Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x20",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2",
+ "BriefDescription": "Number Transactions requested of the CPU; Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x20",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3",
+ "BriefDescription": "Number Transactions requested of the CPU; Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x20",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3",
+ "UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0",
+ "BriefDescription": "Number Transactions requested of the CPU; Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x01",
+ "PortMask": "0x10",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
"UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1",
+ "BriefDescription": "Number Transactions requested of the CPU; Messages",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x02",
+ "PortMask": "0x20",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
"UMask": "0x40",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2",
+ "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x01",
+ "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x02",
+ "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x40",
+ "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3",
+ "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x08",
- "UMask": "0x40",
+ "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x8",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0",
+ "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x20",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x01",
- "UMask": "0x80",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1",
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x02",
- "UMask": "0x80",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2",
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2",
"FCMask": "0x07",
"PerPkg": "1",
"PortMask": "0x04",
- "UMask": "0x80",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
"Unit": "IIO"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3",
+ "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x08",
+ "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0",
+ "FCMask": "0x07",
+ "PerPkg": "1",
+ "PortMask": "0x10",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
+ "EventCode": "0x84",
+ "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1",
"FCMask": "0x07",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PortMask": "0x20",
+ "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "VTd Access; context cache miss",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "VTd Access; L1 miss",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "VTd Access; L2 miss",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "VTd Access; L3 miss",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "VTd Access; Vtd hit",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "VTd Access; TLB miss",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "VTd Access; TLB is full",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "VTd Access; TLB miss",
+ "EventCode": "0x41",
+ "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "VTd Occupancy",
+ "EventCode": "0x40",
+ "EventName": "UNC_IIO_VTD_OCCUPANCY",
+ "PerPkg": "1",
+ "Unit": "IIO"
+ },
+ {
+ "BriefDescription": "Total Write Cache Occupancy; Any Source",
+ "EventCode": "0xF",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.",
+ "UMask": "0x1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Total Write Cache Occupancy; Snoops",
+ "EventCode": "0xF",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
+ "PerPkg": "1",
+ "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
+ "UMask": "0x2",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Total IRP occupancy of inbound read and write requests.",
+ "EventCode": "0xF",
+ "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM",
+ "PerPkg": "1",
+ "PublicDescription": "Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy.",
+ "UMask": "0x4",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "IRP Clocks",
+ "EventCode": "0x1",
+ "EventName": "UNC_I_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Coherent Ops; CLFlush",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x80",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Coherent Ops; CRd",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x2",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Coherent Ops; DRd",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.DRD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x4",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Coherent Ops; PCIDCAHin5t",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x20",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Coherent Ops; PCIRdCur",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.PCITOM",
+ "PerPkg": "1",
+ "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.",
+ "UMask": "0x10",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.RFO",
+ "PerPkg": "1",
+ "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.",
+ "UMask": "0x8",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Coherent Ops; WbMtoI",
+ "EventCode": "0x10",
+ "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
+ "UMask": "0x40",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "FAF RF full",
+ "EventCode": "0x17",
+ "EventName": "UNC_I_FAF_FULL",
+ "PerPkg": "1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.",
+ "EventCode": "0x18",
+ "EventName": "UNC_I_FAF_INSERTS",
+ "PerPkg": "1",
+ "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Occupancy of the IRP FAF queue.",
+ "EventCode": "0x19",
+ "EventName": "UNC_I_FAF_OCCUPANCY",
+ "PerPkg": "1",
+ "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "FAF allocation -- sent to ADQ",
+ "EventCode": "0x16",
+ "EventName": "UNC_I_FAF_TRANSACTIONS",
+ "PerPkg": "1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "All Inserts Inbound (p2p + faf + cset)",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.FAST_REJ",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.FAST_REQ",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.FAST_XFER",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.PF_ACK_HINT",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 0",
+ "EventCode": "0x1C",
+ "EventName": "UNC_I_MISC0.UNKNOWN",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 1; Lost Forward",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.LOST_FWD",
+ "PerPkg": "1",
+ "PublicDescription": "Snoop pulled away ownership before a write was committed",
+ "UMask": "0x10",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 1; Received Invalid",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+ "PerPkg": "1",
+ "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x20",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 1; Received Valid",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+ "PerPkg": "1",
+ "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x40",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.SLOW_E",
+ "PerPkg": "1",
+ "PublicDescription": "Secondary received a transfer that did have sufficient MESI state",
+ "UMask": "0x4",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.SLOW_I",
+ "PerPkg": "1",
+ "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.SLOW_M",
+ "PerPkg": "1",
+ "PublicDescription": "Snoop took cacheline ownership before write from data was committed.",
+ "UMask": "0x8",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
+ "EventCode": "0x1D",
+ "EventName": "UNC_I_MISC1.SLOW_S",
+ "PerPkg": "1",
+ "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state",
+ "UMask": "0x2",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "P2P Requests",
+ "EventCode": "0x14",
+ "EventName": "UNC_I_P2P_INSERTS",
+ "PerPkg": "1",
+ "PublicDescription": "P2P requests from the ITC",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "P2P Occupancy",
+ "EventCode": "0x15",
+ "EventName": "UNC_I_P2P_OCCUPANCY",
+ "PerPkg": "1",
+ "PublicDescription": "P2P B & S Queue Occupancy",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "P2P Transactions; P2P completions",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "P2P Transactions; match if local only",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "P2P Transactions; match if local and target matches",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "P2P Transactions; P2P Message",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "P2P Transactions; P2P reads",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "P2P Transactions; Match if remote only",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "P2P Transactions; match if remote and target matches",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "P2P Transactions; P2P Writes",
+ "EventCode": "0x13",
+ "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
+ "PerPkg": "1",
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO",
+ "UMask": "0x7e",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
+ "PerPkg": "1",
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache",
+ "UMask": "0x74",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
+ "PerPkg": "1",
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache",
+ "UMask": "0x72",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
+ "PerPkg": "1",
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache",
+ "UMask": "0x78",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
+ "PerPkg": "1",
+ "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache",
+ "UMask": "0x71",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Snoop Responses; Hit E or S",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Snoop Responses; Hit I",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_I",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Snoop Responses; Hit M",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Snoop Responses; Miss",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.MISS",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Snoop Responses; SnpCode",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Snoop Responses; SnpData",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Snoop Responses; SnpInv",
+ "EventCode": "0x12",
+ "EventName": "UNC_I_SNOOP_RESP.SNPINV",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Inbound Transaction Count; Atomic",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions",
+ "UMask": "0x10",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Inbound Transaction Count; Other",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.OTHER",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.",
+ "UMask": "0x20",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Inbound Transaction Count; Read Prefetches",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.",
+ "UMask": "0x4",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Inbound Transaction Count; Reads",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.READS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).",
+ "UMask": "0x1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Inbound Transaction Count; Writes",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.WRITES",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.",
+ "UMask": "0x2",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Inbound write (fast path) requests received by the IRP.",
+ "EventCode": "0x11",
+ "EventName": "UNC_I_TRANSACTIONS.WR_PREF",
+ "PerPkg": "1",
+ "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.",
+ "UMask": "0x8",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "AK Egress Allocations",
+ "EventCode": "0xB",
+ "EventName": "UNC_I_TxC_AK_INSERTS",
+ "PerPkg": "1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "BL DRS Egress Cycles Full",
+ "EventCode": "0x5",
+ "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
+ "PerPkg": "1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "BL DRS Egress Inserts",
+ "EventCode": "0x2",
+ "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
+ "PerPkg": "1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "BL DRS Egress Occupancy",
+ "EventCode": "0x8",
+ "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
+ "PerPkg": "1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "BL NCB Egress Cycles Full",
+ "EventCode": "0x6",
+ "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
+ "PerPkg": "1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "BL NCB Egress Inserts",
+ "EventCode": "0x3",
+ "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
+ "PerPkg": "1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "BL NCB Egress Occupancy",
+ "EventCode": "0x9",
+ "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
+ "PerPkg": "1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "BL NCS Egress Cycles Full",
+ "EventCode": "0x7",
+ "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
+ "PerPkg": "1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "BL NCS Egress Inserts",
+ "EventCode": "0x4",
+ "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
+ "PerPkg": "1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "BL NCS Egress Occupancy",
+ "EventCode": "0xA",
+ "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
+ "PerPkg": "1",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "No AD Egress Credit Stalls",
+ "EventCode": "0x1A",
+ "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "No BL Egress Credit Stalls",
+ "EventCode": "0x1B",
+ "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Outbound Read Requests",
+ "EventCode": "0xD",
+ "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Outbound Read Requests",
+ "EventCode": "0xE",
+ "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "Outbound Request Queue Occupancy",
+ "EventCode": "0xC",
+ "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
+ "PerPkg": "1",
+ "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
+ "Unit": "IRP"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken",
+ "EventCode": "0x22",
+ "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M to iMC Bypass; Taken",
+ "EventCode": "0x22",
+ "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M to iMC Bypass; Not Taken",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M to iMC Bypass; Taken",
+ "EventCode": "0x21",
+ "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles - at UCLK",
+ "EventName": "UNC_M2M_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xC0",
+ "EventName": "UNC_M2M_CMS_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled",
+ "EventCode": "0x24",
+ "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles when direct to core mode (which bypasses the CHA) was disabled",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Messages sent direct to core (bypassing the CHA)",
+ "EventCode": "0x23",
+ "EventName": "UNC_M2M_DIRECT2CORE_TAKEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when messages were sent direct to core (bypassing the CHA)",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Number of reads in which direct to core transaction were overridden",
+ "EventCode": "0x25",
+ "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE",
+ "PerPkg": "1",
+ "PublicDescription": "Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden",
+ "EventCode": "0x28",
+ "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles when direct to Intel UPI was disabled",
+ "EventCode": "0x27",
+ "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabled",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Messages sent direct to the Intel UPI",
+ "EventCode": "0x26",
+ "EventName": "UNC_M2M_DIRECT2UPI_TAKEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA)",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden",
+ "EventCode": "0x29",
+ "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overridden",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Hit; On NonDirty Line in A State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Hit; On NonDirty Line in I State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Hit; On NonDirty Line in L State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Hit; On NonDirty Line in S State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Hit; On Dirty Line in A State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Hit; On Dirty Line in I State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Hit; On Dirty Line in L State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Hit; On Dirty Line in S State",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Miss; On NonDirty Line in A State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Miss; On NonDirty Line in I State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Miss; On NonDirty Line in L State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Miss; On NonDirty Line in S State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Miss; On Dirty Line in A State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Miss; On Dirty Line in I State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Miss; On Dirty Line in L State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Directory Miss; On Dirty Line in S State",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Multi-socket cacheline Directory update from A to I",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to I (Invalid)",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Multi-socket cacheline Directory update from A to S",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to S (Shared)",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Multi-socket cacheline Directory update from/to Any state",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Multi-socket cacheline Directory update from I to A",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to A (SnoopAll)",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Multi-socket cacheline Directory update from I to S",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to S (Shared)",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Multi-socket cacheline Directory update from S to A",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to A (SnoopAll)",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Multi-socket cacheline Directory update from S to I",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to I (Invalid)",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
+ "EventCode": "0xAE",
+ "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
+ "EventCode": "0xAE",
+ "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "PerPkg": "1",
+ "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "FaST wire asserted; Horizontal",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_FAST_ASSERTED.HORZ",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "FaST wire asserted; Vertical",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M2M_FAST_ASSERTED.VERT",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal IV Ring in Use; Left",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Horizontal IV Ring in Use; Right",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Reads to iMC issued",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority.",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M Reads Issued to iMC; Critical Priority",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.ISOCH",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.NORMAL",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Read requests to Intel Optane DC persistent memory issued to the iMC from M2M",
+ "EventCode": "0x37",
+ "EventName": "UNC_M2M_IMC_READS.TO_PMM",
+ "PerPkg": "1",
+ "PublicDescription": "M2M Reads Issued to iMC; All, regardless of priority.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Writes to iMC issued",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.ALL",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller).",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FULL",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.NI",
+ "PerPkg": "1",
+ "UMask": "0x80",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Partial Non-Isochronous writes to the iMC",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.PARTIAL",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Write requests to Intel Optane DC persistent memory issued to the iMC from M2M",
+ "EventCode": "0x38",
+ "EventName": "UNC_M2M_IMC_WRITES.TO_PMM",
+ "PerPkg": "1",
+ "PublicDescription": "M2M Writes Issued to iMC; All, regardless of priority.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Number Packet Header Matches; MC Match",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M2M_PKT_MATCH.MC",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Number Packet Header Matches; Mesh Match",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M2M_PKT_MATCH.MESH",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 0",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 1",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 2",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0",
+ "EventCode": "0x51",
+ "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1",
+ "EventCode": "0x51",
+ "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2",
+ "EventCode": "0x51",
+ "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Prefetch CAM Cycles Full",
+ "EventCode": "0x53",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Prefetch CAM Cycles Not Empty",
+ "EventCode": "0x54",
+ "EventName": "UNC_M2M_PREFCAM_CYCLES_NE",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Prefecth requests that got turn into a demand request",
+ "EventCode": "0x56",
+ "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefecth queue is made of CAM (Content Addressable Memory)",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Inserts into the Memory Controller Prefetch Queue",
+ "EventCode": "0x57",
+ "EventName": "UNC_M2M_PREFCAM_INSERTS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Prefetch CAM Occupancy",
+ "EventCode": "0x55",
+ "EventName": "UNC_M2M_PREFCAM_OCCUPANCY",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Sink Starvation on Vertical Ring; AD",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M2M_RING_SRC_THRTL",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
+ "Deprecated": "1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
+ "Deprecated": "1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
+ "Deprecated": "1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2",
+ "EventCode": "0x43",
+ "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2",
+ "EventCode": "0x44",
+ "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AD Ingress (from CMS) Full",
+ "EventCode": "0x4",
+ "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AD Ingress (from CMS) Not Empty",
+ "EventCode": "0x3",
+ "EventName": "UNC_M2M_RxC_AD_CYCLES_NE",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AD Ingress (from CMS) Queue Inserts",
+ "EventCode": "0x1",
+ "EventName": "UNC_M2M_RxC_AD_INSERTS",
+ "PerPkg": "1",
+ "PublicDescription": "Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AD Ingress (from CMS) Occupancy",
+ "EventCode": "0x2",
+ "EventName": "UNC_M2M_RxC_AD_OCCUPANCY",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Ingress (from CMS) Full",
+ "EventCode": "0x8",
+ "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Ingress (from CMS) Not Empty",
+ "EventCode": "0x7",
+ "EventName": "UNC_M2M_RxC_BL_CYCLES_NE",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Ingress (from CMS) Allocations",
+ "EventCode": "0x5",
+ "EventName": "UNC_M2M_RxC_BL_INSERTS",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Ingress (from CMS) Occupancy",
+ "EventCode": "0x6",
+ "EventName": "UNC_M2M_RxC_BL_OCCUPANCY",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x80",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Clean line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode and regular reads to DRAM in 1LM",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN",
+ "PerPkg": "1",
+ "PublicDescription": "Tag Hit; Read Hit from NearMem, Clean Line",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY",
+ "PerPkg": "1",
+ "PublicDescription": "Tag Hit; Read Hit from NearMem, Dirty Line",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN",
+ "PerPkg": "1",
+ "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Clean Line",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY",
+ "PerPkg": "1",
+ "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Dirty Line",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Number AD Ingress Credits",
+ "EventCode": "0x41",
+ "EventName": "UNC_M2M_TGR_AD_CREDITS",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Number BL Ingress Credits",
+ "EventCode": "0x42",
+ "EventName": "UNC_M2M_TGR_BL_CREDITS",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Cycles Full; Channel 0",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Cycles Full; Channel 1",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Cycles Full; Channel 2",
+ "EventCode": "0x45",
+ "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Cycles Not Empty; Channel 0",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Cycles Not Empty; Channel 1",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Cycles Not Empty; Channel 2",
+ "EventCode": "0x46",
+ "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Inserts; Channel 0",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Inserts; Channel 1",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Inserts; Channel 2",
+ "EventCode": "0x49",
+ "EventName": "UNC_M2M_TRACKER_INSERTS.CH2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Occupancy; Channel 0",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Occupancy; Channel 1",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Tracker Occupancy; Channel 2",
+ "EventCode": "0x47",
+ "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Data Pending Occupancy",
+ "EventCode": "0x48",
+ "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AD Egress (to CMS) Credit Acquired",
+ "EventCode": "0xD",
+ "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AD Egress (to CMS) Credits Occupancy",
+ "EventCode": "0xE",
+ "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AD Egress (to CMS) Full",
+ "EventCode": "0xC",
+ "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AD Egress (to CMS) Not Empty",
+ "EventCode": "0xB",
+ "EventName": "UNC_M2M_TxC_AD_CYCLES_NE",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AD Egress (to CMS) Allocations",
+ "EventCode": "0x9",
+ "EventName": "UNC_M2M_TxC_AD_INSERTS",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles with No AD Egress (to CMS) Credits",
+ "EventCode": "0xF",
+ "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits",
+ "EventCode": "0x10",
+ "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AD Egress (to CMS) Occupancy",
+ "EventCode": "0xA",
+ "EventName": "UNC_M2M_TxC_AD_OCCUPANCY",
+ "PerPkg": "1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo",
+ "EventCode": "0x39",
+ "EventName": "UNC_M2M_TxC_AK.CRD_CBO",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions",
+ "EventCode": "0x39",
+ "EventName": "UNC_M2M_TxC_AK.NDR",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
+ "EventCode": "0x1E",
+ "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
+ "EventCode": "0x1E",
+ "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Full; All",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL",
+ "PerPkg": "1",
+ "UMask": "0x3",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1",
+ "PerPkg": "1",
+ "UMask": "0x88",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1",
+ "PerPkg": "1",
+ "UMask": "0xa0",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request",
+ "EventCode": "0x14",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1",
+ "PerPkg": "1",
+ "UMask": "0x90",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Not Empty; All",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL",
+ "PerPkg": "1",
+ "UMask": "0x3",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request",
+ "EventCode": "0x13",
+ "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Allocations; All",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x3",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT",
+ "PerPkg": "1",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request",
+ "EventCode": "0x11",
+ "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+ "EventCode": "0x20",
+ "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Occupancy; All",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x3",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP",
+ "PerPkg": "1",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request",
+ "EventCode": "0x12",
+ "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Sideband",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "AK Egress (to CMS) Sideband",
+ "EventCode": "0x6B",
+ "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_CACHE",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_CORE",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI",
+ "EventCode": "0x40",
+ "EventName": "UNC_M2M_TxC_BL.DRS_UPI",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side",
+ "EventCode": "0x19",
+ "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side",
+ "EventCode": "0x1A",
+ "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side",
+ "EventCode": "0x1A",
+ "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Full; All",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL",
+ "PerPkg": "1",
+ "UMask": "0x3",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side",
+ "EventCode": "0x18",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Not Empty; All",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL",
+ "PerPkg": "1",
+ "UMask": "0x3",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side",
+ "EventCode": "0x17",
+ "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Allocations; All",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL",
+ "PerPkg": "1",
+ "UMask": "0x3",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side",
+ "EventCode": "0x15",
+ "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+ "EventCode": "0x1B",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+ "EventCode": "0x1B",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Occupancy; All",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL",
+ "PerPkg": "1",
+ "UMask": "0x3",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side",
+ "EventCode": "0x16",
+ "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "PortMask": "0x20",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
- "Unit": "IIO"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x80",
- "Unit": "IIO"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space",
- "Counter": "0,1,2,3",
- "EventCode": "0xC1",
- "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x01",
- "Unit": "IIO"
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x02",
- "Unit": "IIO"
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x04",
- "Unit": "IIO"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x08",
- "Unit": "IIO"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "PortMask": "0x10",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x10",
- "Unit": "IIO"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x10",
- "Unit": "IIO"
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x20",
- "Unit": "IIO"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Messages",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC",
"PerPkg": "1",
- "PortMask": "0x01",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Messages",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC",
"PerPkg": "1",
- "PortMask": "0x02",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Messages",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC",
"PerPkg": "1",
- "PortMask": "0x04",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Messages",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "PortMask": "0x08",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Messages",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
- "PortMask": "0x10",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Number Transactions requested of the CPU; Messages",
- "Counter": "0,1,2,3",
- "EventCode": "0x84",
- "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1",
- "FCMask": "0x07",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0",
"PerPkg": "1",
- "PortMask": "0x20",
- "UMask": "0x40",
- "Unit": "IIO"
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Total Write Cache Occupancy; Any Source",
- "Counter": "0,1",
- "EventCode": "0xF",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "IRP"
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Total Write Cache Occupancy; Snoops",
- "Counter": "0,1",
- "EventCode": "0xF",
- "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "IRP"
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "IRP Clocks",
- "Counter": "0,1",
- "EventCode": "0x1",
- "EventName": "UNC_I_CLOCKTICKS",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Coherent Ops; PCIRdCur",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x1",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Coherent Ops; CRd",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.CRD",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x2",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Coherent Ops; DRd",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.DRD",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "IRP"
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Coherent Ops; PCIDCAHin5t",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Coherent Ops; WbMtoI",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.WBMTOI",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x40",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Coherent Ops; CLFlush",
- "Counter": "0,1",
- "EventCode": "0x10",
- "EventName": "UNC_I_COHERENT_OPS.CLFLUSH",
+ "BriefDescription": "CMS Vertical ADS Used; IV",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "FAF RF full",
- "Counter": "0,1",
- "EventCode": "0x17",
- "EventName": "UNC_I_FAF_FULL",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "FAF allocation -- sent to ADQ",
- "Counter": "0,1",
- "EventCode": "0x16",
- "EventName": "UNC_I_FAF_TRANSACTIONS",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "All Inserts Inbound (p2p + faf + cset)",
- "Counter": "0,1",
- "EventCode": "0x1E",
- "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "IRP"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)",
- "Counter": "0,1",
- "EventCode": "0x1E",
- "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "IRP"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.FAST_REQ",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "IRP"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.FAST_REJ",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "IRP"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.2ND_RD_INSERT",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
+ "EventCode": "0x92",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "IRP"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "IRP"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.FAST_XFER",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.PF_ACK_HINT",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0",
+ "PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
"UMask": "0x40",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 0",
- "Counter": "0,1",
- "EventCode": "0x1C",
- "EventName": "UNC_I_MISC0.UNKNOWN",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
+ "EventCode": "0x93",
+ "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.SLOW_I",
+ "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
"UMask": "0x1",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.SLOW_S",
+ "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
"UMask": "0x2",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.SLOW_E",
+ "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
"UMask": "0x4",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.SLOW_M",
+ "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "IRP"
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 1; Lost Forward",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.LOST_FWD",
+ "BriefDescription": "CMS Vert Egress Allocations; IV",
+ "EventCode": "0x91",
+ "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 1; Received Invalid",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD",
+ "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Misc Events - Set 1; Received Valid",
- "Counter": "0,1",
- "EventCode": "0x1D",
- "EventName": "UNC_I_MISC1.SEC_RCVD_VLD",
+ "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Requests",
- "Counter": "0,1",
- "EventCode": "0x14",
- "EventName": "UNC_I_P2P_INSERTS",
+ "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Occupancy",
- "Counter": "0,1",
- "EventCode": "0x15",
- "EventName": "UNC_I_P2P_OCCUPANCY",
+ "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Transactions; P2P reads",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.RD",
+ "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "IRP"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Transactions; P2P Writes",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.WR",
+ "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "IRP"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Transactions; P2P Message",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.MSG",
+ "BriefDescription": "CMS Vertical Egress NACKs; IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_M2M_TxR_VERT_NACK.IV",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "IRP"
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Transactions; P2P completions",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL",
+ "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "IRP"
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Transactions; Match if remote only",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.REM",
+ "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
"UMask": "0x10",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Transactions; match if remote and target matches",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH",
+ "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Transactions; match if local only",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.LOC",
+ "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
+ "Unit": "M2M"
},
{
- "BriefDescription": "P2P Transactions; match if local and target matches",
- "Counter": "0,1",
- "EventCode": "0x13",
- "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH",
+ "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "IRP"
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Snoop Responses; Miss",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.MISS",
+ "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "IRP"
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Snoop Responses; Hit I",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_I",
+ "BriefDescription": "CMS Vert Egress Occupancy; IV",
+ "EventCode": "0x90",
+ "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "IRP"
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Snoop Responses; Hit E or S",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_ES",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "IRP"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Snoop Responses; Hit M",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.HIT_M",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "IRP"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Snoop Responses; SnpCode",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPCODE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Snoop Responses; SnpData",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPDATA",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x20",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Snoop Responses; SnpInv",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.SNPINV",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "IRP"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Inbound Transaction Count; Reads",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.READS",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "IRP"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x40",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Inbound Transaction Count; Writes",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.WRITES",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M2M_TxR_VERT_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "IRP"
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Inbound Transaction Count; Read Prefetches",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.RD_PREF",
+ "BriefDescription": "Vertical AD Ring In Use; Down and Even",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x4",
- "Unit": "IRP"
+ "Unit": "M2M"
},
{
- "BriefDescription": "Inbound Transaction Count; Atomic",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.ATOMIC",
+ "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Inbound Transaction Count; Other",
- "Counter": "0,1",
- "EventCode": "0x11",
- "EventName": "UNC_I_TRANSACTIONS.OTHER",
+ "BriefDescription": "Vertical AD Ring In Use; Up and Even",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "No AD Egress Credit Stalls",
- "Counter": "0,1",
- "EventCode": "0x1A",
- "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES",
+ "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "AK Egress Allocations",
- "Counter": "0,1",
- "EventCode": "0xB",
- "EventName": "UNC_I_TxC_AK_INSERTS",
+ "BriefDescription": "Vertical AK Ring In Use; Down and Even",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL DRS Egress Cycles Full",
- "Counter": "0,1",
- "EventCode": "0x5",
- "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL",
+ "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL DRS Egress Inserts",
- "Counter": "0,1",
- "EventCode": "0x2",
- "EventName": "UNC_I_TxC_BL_DRS_INSERTS",
+ "BriefDescription": "Vertical AK Ring In Use; Up and Even",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL DRS Egress Occupancy",
- "Counter": "0,1",
- "EventCode": "0x8",
- "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY",
+ "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL NCB Egress Cycles Full",
- "Counter": "0,1",
- "EventCode": "0x6",
- "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL",
+ "BriefDescription": "Vertical BL Ring in Use; Down and Even",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL NCB Egress Inserts",
- "Counter": "0,1",
- "EventCode": "0x3",
- "EventName": "UNC_I_TxC_BL_NCB_INSERTS",
+ "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL NCB Egress Occupancy",
- "Counter": "0,1",
- "EventCode": "0x9",
- "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY",
+ "BriefDescription": "Vertical BL Ring in Use; Up and Even",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL NCS Egress Cycles Full",
- "Counter": "0,1",
- "EventCode": "0x7",
- "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL",
+ "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL NCS Egress Inserts",
- "Counter": "0,1",
- "EventCode": "0x4",
- "EventName": "UNC_I_TxC_BL_NCS_INSERTS",
+ "BriefDescription": "Vertical IV Ring in Use; Down",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "BL NCS Egress Occupancy",
- "Counter": "0,1",
- "EventCode": "0xA",
- "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY",
+ "BriefDescription": "Vertical IV Ring in Use; Up",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "Unit": "IRP"
+ "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "No BL Egress Credit Stalls",
- "Counter": "0,1",
- "EventCode": "0x1B",
- "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
+ "Deprecated": "1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0",
"PerPkg": "1",
- "Unit": "IRP"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
- "EventCode": "0xD",
- "EventName": "UNC_I_TxS_DATA_INSERTS_NCB",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
+ "Deprecated": "1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1",
"PerPkg": "1",
- "Unit": "IRP"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Outbound Read Requests",
- "Counter": "0,1",
- "EventCode": "0xE",
- "EventName": "UNC_I_TxS_DATA_INSERTS_NCS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
+ "Deprecated": "1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2",
"PerPkg": "1",
- "Unit": "IRP"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Outbound Request Queue Occupancy",
- "Counter": "0,1",
- "EventCode": "0xC",
- "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0",
"PerPkg": "1",
- "Unit": "IRP"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1",
"PerPkg": "1",
- "UMask": "0x72",
- "Unit": "IRP"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2",
"PerPkg": "1",
- "UMask": "0x74",
- "Unit": "IRP"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0",
"PerPkg": "1",
- "UMask": "0x78",
- "Unit": "IRP"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_HIT",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1",
"PerPkg": "1",
- "UMask": "0x7e",
- "Unit": "IRP"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "Responses to snoops of any type that miss the IIO cache",
- "Counter": "0,1",
- "EventCode": "0x12",
- "EventName": "UNC_I_SNOOP_RESP.ALL_MISS",
+ "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2",
"PerPkg": "1",
- "UMask": "0x71",
- "Unit": "IRP"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+ "BriefDescription": "Write Tracker Cycles Full; Channel 0",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0",
"PerPkg": "1",
"UMask": "0x1",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+ "BriefDescription": "Write Tracker Cycles Full; Channel 1",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+ "BriefDescription": "Write Tracker Cycles Full; Channel 2",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+ "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+ "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "M2M"
+ },
+ {
+ "BriefDescription": "Write Tracker Inserts; Channel 0",
+ "EventCode": "0x61",
+ "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0",
"PerPkg": "1",
"UMask": "0x1",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "BriefDescription": "Write Tracker Inserts; Channel 1",
+ "EventCode": "0x61",
+ "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1",
"PerPkg": "1",
"UMask": "0x2",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "BriefDescription": "Write Tracker Inserts; Channel 2",
+ "EventCode": "0x61",
+ "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2",
"PerPkg": "1",
"UMask": "0x4",
- "Unit": "UPI LL"
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+ "BriefDescription": "Write Tracker Occupancy; Channel 0",
+ "EventCode": "0x60",
+ "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
- "Counter": "0,1,2,3",
- "EventCode": "0x14",
- "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+ "BriefDescription": "Write Tracker Occupancy; Channel 1",
+ "EventCode": "0x60",
+ "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
- "Counter": "0,1,2,3",
- "EventCode": "0x16",
- "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+ "BriefDescription": "Write Tracker Occupancy; Channel 2",
+ "EventCode": "0x60",
+ "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
+ "EventCode": "0x80",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
- "Unit": "UPI LL"
- },
- {
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
+ "EventCode": "0x80",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
+ "EventCode": "0x80",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
+ "EventCode": "0x80",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
+ "EventCode": "0x80",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+ "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
+ "EventCode": "0x80",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
- "Counter": "0,1,2,3",
- "EventCode": "0x15",
- "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
+ "EventCode": "0x82",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
- "Counter": "0,1,2,3",
- "EventCode": "0x20",
- "EventName": "UNC_UPI_PHY_INIT_CYCLES",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
+ "EventCode": "0x82",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "L1 Req Nack",
- "Counter": "0,1,2,3",
- "EventCode": "0x23",
- "EventName": "UNC_UPI_POWER_L1_NACK",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
+ "EventCode": "0x82",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "L1 Req (same as L1 Ack)",
- "Counter": "0,1,2,3",
- "EventCode": "0x22",
- "EventName": "UNC_UPI_POWER_L1_REQ",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
+ "EventCode": "0x82",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
+ "EventCode": "0x82",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+ "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
+ "EventCode": "0x82",
+ "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
+ "EventCode": "0x88",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
- "Counter": "0,1,2,3",
- "EventCode": "0x46",
- "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
+ "EventCode": "0x88",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles in L0. Receive side",
- "Counter": "0,1,2,3",
- "EventCode": "0x24",
- "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
+ "EventCode": "0x88",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Consumed",
- "Counter": "0,1,2,3",
- "EventCode": "0x39",
- "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
+ "EventCode": "0x88",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Consumed",
- "Counter": "0,1,2,3",
- "EventCode": "0x3A",
- "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
+ "EventCode": "0x88",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "VNA Credit Consumed",
- "Counter": "0,1,2,3",
- "EventCode": "0x38",
- "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
+ "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
+ "EventCode": "0x88",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Received; Slot 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Received; Slot 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Received; Slot 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Received; Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.DATA",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Received; LLCRD Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Received; LLCTRL",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
+ "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
+ "EventCode": "0x8A",
+ "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
+ "EventCode": "0x84",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
+ "EventCode": "0x84",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
+ "EventCode": "0x84",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2",
+ "PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
+ "EventCode": "0x84",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
+ "EventCode": "0x84",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4",
"PerPkg": "1",
- "UMask": "0x9",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP",
+ "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
+ "EventCode": "0x84",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5",
"PerPkg": "1",
- "UMask": "0xA",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_HDR_MATCH.WB",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
+ "EventCode": "0x86",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
- "UMask": "0xB",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
+ "EventCode": "0x86",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
- "UMask": "0xC",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
+ "EventCode": "0x86",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
- "UMask": "0xD",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets; Slot 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
+ "EventCode": "0x86",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets; Slot 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
+ "EventCode": "0x86",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "RxQ Occupancy - All Packets; Slot 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
+ "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
+ "EventCode": "0x86",
+ "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x1",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x2",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x4",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x8",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x10",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
- "Counter": "0,1,2,3",
- "EventCode": "0x33",
- "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+ "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
+ "EventCode": "0x8E",
+ "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
"UMask": "0x20",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x1",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x2",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x4",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x8",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x10",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+ "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
+ "EventCode": "0x8C",
+ "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
"UMask": "0x20",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+ "BriefDescription": "CBox AD Credits Empty; Requests",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
- "Counter": "0,1,2,3",
- "EventCode": "0x2A",
- "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+ "BriefDescription": "CBox AD Credits Empty; Snoops",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
- "Counter": "0,1,2,3",
- "EventCode": "0x28",
- "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+ "BriefDescription": "CBox AD Credits Empty; VNA Messages",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
- "Counter": "0,1,2,3",
- "EventCode": "0x29",
- "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+ "BriefDescription": "CBox AD Credits Empty; Writebacks",
+ "EventCode": "0x22",
+ "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Cycles in L0. Transmit side",
- "Counter": "0,1,2,3",
- "EventCode": "0x26",
- "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
+ "BriefDescription": "Number of uclks in domain",
+ "EventCode": "0x1",
+ "EventName": "UNC_M3UPI_CLOCKTICKS",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Sent; Slot 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
+ "BriefDescription": "CMS Clockticks",
+ "EventCode": "0xC0",
+ "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
+ "PerPkg": "1",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "D2C Sent",
+ "EventCode": "0x2B",
+ "EventName": "UNC_M3UPI_D2C_SENT",
+ "PerPkg": "1",
+ "PublicDescription": "Count cases BL sends direct to core",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "D2U Sent",
+ "EventCode": "0x2A",
+ "EventName": "UNC_M3UPI_D2U_SENT",
+ "PerPkg": "1",
+ "PublicDescription": "Cases where SMI3 sends D2U command",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
+ "EventCode": "0xAE",
+ "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
+ "EventCode": "0xAE",
+ "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
"PerPkg": "1",
+ "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
"UMask": "0x1",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Sent; Slot 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
+ "BriefDescription": "FaST wire asserted; Horizontal",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
"UMask": "0x2",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Sent; Slot 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
+ "BriefDescription": "FaST wire asserted; Vertical",
+ "EventCode": "0xA5",
+ "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Sent; LLCRD Not Empty",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
+ "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Sent; LLCTRL",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
+ "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR",
+ "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ",
+ "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
+ "EventCode": "0xA7",
+ "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
"UMask": "0x8",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP",
+ "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "UMask": "0x9",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.WB",
+ "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "UMask": "0xC",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB",
+ "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "UMask": "0xE",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS",
+ "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
+ "EventCode": "0xA9",
+ "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "UMask": "0xF",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Tx Flit Buffer Allocations",
- "Counter": "0,1,2,3",
- "EventCode": "0x40",
- "EventName": "UNC_UPI_TxL_INSERTS",
+ "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Tx Flit Buffer Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x42",
- "EventName": "UNC_UPI_TxL_OCCUPANCY",
+ "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
- "Counter": "0,1,2,3",
- "EventCode": "0x45",
- "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+ "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "VNA Credits Pending Return - Occupancy",
- "Counter": "0,1,2,3",
- "EventCode": "0x44",
- "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
+ "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
+ "EventCode": "0xAB",
+ "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD",
"PerPkg": "1",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+ "BriefDescription": "Horizontal IV Ring in Use; Left",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Received; Protocol Header",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
+ "BriefDescription": "Horizontal IV Ring in Use; Right",
+ "EventCode": "0xAD",
+ "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Sent; Protocol Header",
- "Counter": "0,1,2,3",
- "EventCode": "0x2",
- "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
+ "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB",
"PerPkg": "1",
- "UMask": "0x80",
- "Unit": "UPI LL"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+ "BriefDescription": "M2 BL Credits Empty; IIO2",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "UPI LL"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
- "Counter": "0,1,2,3",
- "EventCode": "0x18",
- "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+ "BriefDescription": "M2 BL Credits Empty; IIO3",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "UPI LL"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC",
+ "BriefDescription": "M2 BL Credits Empty; IIO4",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
"PerPkg": "1",
- "UMaskExt": "0x02",
- "Unit": "UPI LL"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.REM",
+ "BriefDescription": "M2 BL Credits Empty; IIO5",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
"PerPkg": "1",
- "UMaskExt": "0x04",
- "Unit": "UPI LL"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR",
+ "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
"PerPkg": "1",
- "UMaskExt": "0x08",
- "Unit": "UPI LL"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR",
+ "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits",
+ "EventCode": "0x23",
+ "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
"PerPkg": "1",
- "UMaskExt": "0x10",
- "Unit": "UPI LL"
+ "PublicDescription": "No vn0 and vna credits available to send to M2",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR",
+ "BriefDescription": "Multi Slot Flit Received; AD - Slot 0",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
"PerPkg": "1",
- "UMaskExt": "0x20",
- "Unit": "UPI LL"
+ "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR",
+ "BriefDescription": "Multi Slot Flit Received; AD - Slot 1",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
"PerPkg": "1",
- "UMaskExt": "0x40",
- "Unit": "UPI LL"
+ "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA",
+ "BriefDescription": "Multi Slot Flit Received; AD - Slot 2",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
"PerPkg": "1",
- "UMask": "0xA",
- "Unit": "UPI LL"
+ "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA",
+ "BriefDescription": "Multi Slot Flit Received; AK - Slot 0",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
"PerPkg": "1",
- "UMask": "0xC",
- "Unit": "UPI LL"
+ "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Valid Flits Received; Idle",
- "Counter": "0,1,2,3",
- "EventCode": "0x3",
- "EventName": "UNC_UPI_RxL_FLITS.IDLE",
+ "BriefDescription": "Multi Slot Flit Received; AK - Slot 2",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
"PerPkg": "1",
- "UMask": "0x47",
- "Unit": "UPI LL"
+ "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
+ "BriefDescription": "Multi Slot Flit Received; BL - Slot 0",
+ "EventCode": "0x3E",
+ "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x0108",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Snoop",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x09",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x0109",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
+ "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
+ "EventCode": "0xA1",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x0A",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD",
"PerPkg": "1",
- "UMask": "0x010A",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK",
"PerPkg": "1",
- "UMask": "0x0C",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
"PerPkg": "1",
- "UMask": "0x010C",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
+ "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.",
+ "EventCode": "0xA0",
+ "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
"PerPkg": "1",
- "UMask": "0x0D",
- "Unit": "UPI LL"
+ "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD",
"PerPkg": "1",
- "UMask": "0x010D",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK",
"PerPkg": "1",
- "UMask": "0x0E",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
"PerPkg": "1",
- "UMask": "0x010E",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
+ "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
+ "EventCode": "0xA3",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
"PerPkg": "1",
- "UMask": "0x010F",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Request",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
+ "BriefDescription": "Sink Starvation on Vertical Ring; AD",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "UPI LL"
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK",
"PerPkg": "1",
- "UMask": "0x108",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL",
"PerPkg": "1",
- "UMask": "0x09",
- "Unit": "UPI LL"
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
+ "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.",
+ "EventCode": "0xA2",
+ "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV",
"PerPkg": "1",
- "UMask": "0x109",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
+ "BriefDescription": "Source Throttle",
+ "EventCode": "0xA4",
+ "EventName": "UNC_M3UPI_RING_SRC_THRTL",
"PerPkg": "1",
- "UMask": "0x0A",
- "Unit": "UPI LL"
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
+ "BriefDescription": "Lost Arb for VN0; REQ on AD",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x10A",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "VN0 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
+ "BriefDescription": "Lost Arb for VN0; RSP on AD",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x0C",
- "Unit": "UPI LL"
+ "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
+ "BriefDescription": "Lost Arb for VN0; SNP on AD",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10C",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "VN0 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
+ "BriefDescription": "Lost Arb for VN0; NCB on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x0D",
- "Unit": "UPI LL"
+ "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
+ "BriefDescription": "Lost Arb for VN0; NCS on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x10D",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+ "BriefDescription": "Lost Arb for VN0; RSP on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x0E",
- "Unit": "UPI LL"
+ "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
+ "BriefDescription": "Lost Arb for VN0; WB on BL",
+ "EventCode": "0x4B",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x10E",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "VN0 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+ "BriefDescription": "Lost Arb for VN1; REQ on AD",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x0F",
- "Unit": "UPI LL"
+ "PublicDescription": "VN1 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
+ "BriefDescription": "Lost Arb for VN1; RSP on AD",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x10F",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
+ "BriefDescription": "Lost Arb for VN1; SNP on AD",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x01AA",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "VN1 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid",
- "Counter": "0,1,2,3",
- "EventCode": "0x5",
- "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
+ "BriefDescription": "Lost Arb for VN1; NCB on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x012A",
- "UMaskExt": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0",
- "Counter": "0,1,2,3",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
+ "BriefDescription": "Lost Arb for VN1; NCS on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "UPI LL"
+ "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1",
- "Counter": "0,1,2,3",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
+ "BriefDescription": "Lost Arb for VN1; RSP on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "UPI LL"
+ "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2",
- "Counter": "0,1,2,3",
- "EventCode": "0x30",
- "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
+ "BriefDescription": "Lost Arb for VN1; WB on BL",
+ "EventCode": "0x4C",
+ "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "UPI LL"
+ "PublicDescription": "VN1 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
+ "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN",
"PerPkg": "1",
- "UMask": "0x1AA",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "AD and BL messages won arbitration concurrently / in parallel",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid",
- "Counter": "0,1,2,3",
- "EventCode": "0x4",
- "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
+ "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
"PerPkg": "1",
- "UMask": "0x12A",
- "UMaskExt": "0x1",
- "Unit": "UPI LL"
+ "PublicDescription": "Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message",
+ "UMask": "0x4",
+ "Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VNA",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
+ "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
+ "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
+ "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
+ "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn0, delaying vn1 win, because vn0 offered parallel ad/bl",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
+ "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1",
+ "EventCode": "0x4D",
+ "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn1, delaying vn0 win, because vn1 offered parallel ad/bl",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
+ "BriefDescription": "Can't Arb for VN0; REQ on AD",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x20",
- "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
+ "BriefDescription": "Can't Arb for VN0; RSP on AD",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
+ "BriefDescription": "Can't Arb for VN0; SNP on AD",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
+ "BriefDescription": "Can't Arb for VN0; NCB on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
+ "BriefDescription": "Can't Arb for VN0; NCS on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS",
"PerPkg": "1",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0",
+ "BriefDescription": "Can't Arb for VN0; RSP on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x1",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1",
+ "BriefDescription": "Can't Arb for VN0; WB on BL",
+ "EventCode": "0x49",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0",
+ "BriefDescription": "Can't Arb for VN1; REQ on AD",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1",
+ "BriefDescription": "Can't Arb for VN1; RSP on AD",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CBox AD Credits Empty; VNA Messages",
- "Counter": "0,1,2",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA",
+ "BriefDescription": "Can't Arb for VN1; SNP on AD",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CBox AD Credits Empty; Writebacks",
- "Counter": "0,1,2",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB",
+ "BriefDescription": "Can't Arb for VN1; NCB on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CBox AD Credits Empty; Requests",
- "Counter": "0,1,2",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ",
+ "BriefDescription": "Can't Arb for VN1; NCS on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CBox AD Credits Empty; Snoops",
- "Counter": "0,1,2",
- "EventCode": "0x22",
- "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP",
+ "BriefDescription": "Can't Arb for VN1; RSP on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of uclks in domain",
- "Counter": "0,1,2",
- "EventCode": "0x1",
- "EventName": "UNC_M3UPI_CLOCKTICKS",
+ "BriefDescription": "Can't Arb for VN1; WB on BL",
+ "EventCode": "0x4A",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB",
"PerPkg": "1",
+ "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "D2U Sent",
- "Counter": "0,1,2",
- "EventCode": "0x2A",
- "EventName": "UNC_M3UPI_D2U_SENT",
+ "BriefDescription": "No Credits to Arb for VN0; REQ on AD",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ",
"PerPkg": "1",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB",
+ "BriefDescription": "No Credits to Arb for VN0; RSP on AD",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; IIO2",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB",
+ "BriefDescription": "No Credits to Arb for VN0; SNP on AD",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; IIO3",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB",
+ "BriefDescription": "No Credits to Arb for VN0; NCB on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; IIO4",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB",
+ "BriefDescription": "No Credits to Arb for VN0; NCS on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; IIO5",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB",
+ "BriefDescription": "No Credits to Arb for VN0; RSP on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS",
+ "BriefDescription": "No Credits to Arb for VN0; WB on BL",
+ "EventCode": "0x47",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits",
- "Counter": "0,1,2",
- "EventCode": "0x23",
- "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL",
+ "BriefDescription": "No Credits to Arb for VN1; REQ on AD",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Multi Slot Flit Received; AD - Slot 0",
- "Counter": "0,1,2",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0",
+ "BriefDescription": "No Credits to Arb for VN1; RSP on AD",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Multi Slot Flit Received; AD - Slot 1",
- "Counter": "0,1,2",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1",
+ "BriefDescription": "No Credits to Arb for VN1; SNP on AD",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Multi Slot Flit Received; AD - Slot 2",
- "Counter": "0,1,2",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2",
+ "BriefDescription": "No Credits to Arb for VN1; NCB on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Multi Slot Flit Received; BL - Slot 0",
- "Counter": "0,1,2",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0",
+ "BriefDescription": "No Credits to Arb for VN1; NCS on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Multi Slot Flit Received; AK - Slot 0",
- "Counter": "0,1,2",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0",
+ "BriefDescription": "No Credits to Arb for VN1; RSP on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Multi Slot Flit Received; AK - Slot 2",
- "Counter": "0,1,2",
- "EventCode": "0x3E",
- "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2",
+ "BriefDescription": "No Credits to Arb for VN1; WB on BL",
+ "EventCode": "0x48",
+ "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
+ "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number ot times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while bl message is in arbitration",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
+ "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number ot times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while pipeline is idle",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
+ "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number ot times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl message in same flit",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
+ "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2",
+ "EventCode": "0x40",
+ "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number ot times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl message in same flit",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
+ "BriefDescription": "VN0 message lost contest for flit; REQ on AD",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
+ "BriefDescription": "VN0 message lost contest for flit; RSP on AD",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
+ "BriefDescription": "VN0 message lost contest for flit; SNP on AD",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for AD; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x30",
- "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
+ "BriefDescription": "VN0 message lost contest for flit; NCB on BL",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
+ "BriefDescription": "VN0 message lost contest for flit; NCS on BL",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
+ "BriefDescription": "VN0 message lost contest for flit; RSP on BL",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
+ "BriefDescription": "VN0 message lost contest for flit; WB on BL",
+ "EventCode": "0x50",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD FlowQ Bypass",
- "Counter": "0,1,2",
- "EventCode": "0x2C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
+ "BriefDescription": "VN1 message lost contest for flit; REQ on AD",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
+ "BriefDescription": "VN1 message lost contest for flit; RSP on AD",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
+ "BriefDescription": "VN1 message lost contest for flit; SNP on AD",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
+ "BriefDescription": "VN1 message lost contest for flit; NCB on BL",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
+ "BriefDescription": "VN1 message lost contest for flit; NCS on BL",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
+ "BriefDescription": "VN1 message lost contest for flit; RSP on BL",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
+ "BriefDescription": "VN1 message lost contest for flit; WB on BL",
+ "EventCode": "0x51",
+ "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
+ "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Indication that at least one packet (flit) is in the bgf (fifo only)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x27",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
+ "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
+ "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb",
+ "EventCode": "0x60",
+ "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "VN0 or VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
+ "BriefDescription": "Credit Occupancy; D2K Credits",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "D2K completion fifo credit occupancy (credits in use), accumulated across all cycles",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
+ "BriefDescription": "Credit Occupancy; Packets in BGF FIFO",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
+ "BriefDescription": "Credit Occupancy; Packets in BGF Path",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
+ "BriefDescription": "Credit Occupancy",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "count of bl messages in pump-1-pending state, in completion fifo only",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
+ "BriefDescription": "Credit Occupancy",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
"PerPkg": "1",
+ "PublicDescription": "count of bl messages in pump-1-pending state, in marker table and in fifo",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2D",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
+ "BriefDescription": "Credit Occupancy; Transmit Credits",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
+ "BriefDescription": "Credit Occupancy; VNA In Use",
+ "EventCode": "0x61",
+ "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages",
- "EventCode": "0x1C",
- "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x34",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
+ "EventCode": "0x43",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x34",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x34",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x34",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x34",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x34",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - New Message; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x33",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - New Message; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x33",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
+ "EventCode": "0x44",
+ "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x33",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB",
+ "BriefDescription": "Data Flit Not Sent; All",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Data flit is ready for transmission but could not be sent",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - New Message; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x33",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ",
+ "BriefDescription": "Data Flit Not Sent; No BGF Credits",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Data flit is ready for transmission but could not be sent",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - New Message; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x33",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP",
+ "BriefDescription": "Data Flit Not Sent; No TxQ Credits",
+ "EventCode": "0x57",
+ "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Data flit is ready for transmission but could not be sent",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x33",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB",
+ "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "generating bl data flit sequence; waiting for data pump 0",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "pump-1-pending logic is at capacity (pending table plus completion fifo at limit)",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "pump-1-pending logic is tracking at least one message",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "pump-1-pending completion fifo is full",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ",
+ "BriefDescription": "Generating BL Data Flit Sequence",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "a bl message finished but is in limbo and moved to pump-1-pending logic",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP",
+ "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1",
+ "EventCode": "0x59",
+ "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "generating bl data flit sequence; waiting for data pump 1",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
+ "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC",
+ "EventCode": "0x5A",
+ "EventName": "UNC_M3UPI_RxC_FLITS_MISC",
"PerPkg": "1",
- "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x32",
- "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
+ "BriefDescription": "Sent Header Flit; One Message",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "One message in flit; VNA or non-VNA flit",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AK Flow Q Inserts",
- "Counter": "0,1,2",
- "EventCode": "0x2F",
- "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
+ "BriefDescription": "Sent Header Flit; One Message in non-VNA",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX",
"PerPkg": "1",
+ "PublicDescription": "One message in flit; non-VNA flit",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "AK Flow Q Occupancy",
- "EventCode": "0x1E",
- "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
+ "BriefDescription": "Sent Header Flit; Two Messages",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS",
"PerPkg": "1",
+ "PublicDescription": "Two messages in flit; VNA flit",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
+ "BriefDescription": "Sent Header Flit; Three Messages",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Three messages in flit; VNA flit",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
+ "BriefDescription": "Sent Header Flit",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN0 NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
+ "BriefDescription": "Sent Header Flit",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN0 NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
+ "BriefDescription": "Sent Header Flit",
+ "EventCode": "0x56",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
+ "BriefDescription": "Slotting BL Message Into Header Flit; All",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
+ "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "BL message requires data flit sequence",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN1 NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
+ "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Waiting for header pump 0",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Failed ARB for BL; VN1 NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x35",
- "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
+ "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Header pump 1 is not required for flit",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
+ "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Header pump 1 is not required for flit but flit transmission delayed",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
+ "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Header pump 1 is not required for flit and not available",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
+ "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1",
+ "EventCode": "0x58",
+ "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Waiting for header pump 1",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
+ "BriefDescription": "Flit Gen - Header 1; Acumullate",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
+ "BriefDescription": "Flit Gen - Header 1; Accumulate Ready",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
+ "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
+ "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x28",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
+ "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting is in run-ahead to start new flit, and message is actually slotted into new flit",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
+ "BriefDescription": "Flit Gen - Header 1; Parallel Ok",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; New header flit construction may proceed in parallel with data flit sequence",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
+ "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit finished assembly in parallel with data flit sequence",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
+ "BriefDescription": "Flit Gen - Header 1; Parallel Message",
+ "EventCode": "0x53",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Events related to Header Flit Generation - Set 1; Message is slotted into header flit in parallel with data flit sequence",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
+ "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate-matching stall injected",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
+ "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message",
+ "EventCode": "0x54",
+ "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate matching stall injected, but no additional message slotted during stall cycle",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
+ "BriefDescription": "Header Not Sent; All",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "header flit is ready for transmission but could not be sent",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
+ "BriefDescription": "Header Not Sent; No BGF Credits",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x2E",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
+ "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available; no additional message slotted into flit",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
+ "BriefDescription": "Header Not Sent; No TxQ Credits",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
+ "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available; no additional message slotted into flit",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
+ "BriefDescription": "Header Not Sent; Sent - One Slot Taken",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only one slot taken (two slots free)",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
+ "BriefDescription": "Header Not Sent; Sent - Three Slots Taken",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with three slots taken (no slots free)",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
+ "BriefDescription": "Header Not Sent; Sent - Two Slots Taken",
+ "EventCode": "0x55",
+ "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only two slots taken (one slots free)",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
+ "BriefDescription": "Message Held; Can't Slot AD",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
+ "BriefDescription": "Message Held; Can't Slot BL",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages",
- "EventCode": "0x1D",
- "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
+ "BriefDescription": "Message Held; Parallel AD Lost",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "some AD message lost contest for slot 0 (logical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1})",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x38",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB",
+ "BriefDescription": "Message Held; Parallel Attempt",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "ad and bl messages attempted to slot into the same flit in parallel",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x38",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB",
+ "BriefDescription": "Message Held; Parallel BL Lost",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "some BL message lost contest for slot 0 (logical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1})",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for BL - New Message; VN0 NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x38",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS",
+ "BriefDescription": "Message Held; Parallel Success",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "ad and bl messages were actually slotted into the same flit in paralle",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for BL - New Message; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x38",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB",
+ "BriefDescription": "Message Held; VN0",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.VN0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x38",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB",
+ "BriefDescription": "Message Held; VN1",
+ "EventCode": "0x52",
+ "EventName": "UNC_M3UPI_RxC_HELD.VN1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for BL - New Message; VN1 NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x38",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL",
+ "EventCode": "0x41",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages",
- "Counter": "0,1,2",
- "EventCode": "0x37",
- "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Used; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Used; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Used; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Used; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Used; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL",
+ "EventCode": "0x42",
+ "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Credit Used; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5C",
- "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 No Credits; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 No Credits; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 No Credits; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 No Credits; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 No Credits; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 No Credits; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5E",
- "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
+ "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL",
+ "EventCode": "0x45",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Used; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Used; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Used; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Used; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Used; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Credit Used; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5D",
- "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 No Credits; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
+ "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL",
+ "EventCode": "0x46",
+ "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 No Credits; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
+ "BriefDescription": "VN0 message can't slot into flit; REQ on AD",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 No Credits; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
+ "BriefDescription": "VN0 message can't slot into flit; RSP on AD",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 No Credits; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
+ "BriefDescription": "VN0 message can't slot into flit; SNP on AD",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 No Credits; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
+ "BriefDescription": "VN0 message can't slot into flit; NCB on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 No Credits; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x5F",
- "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
+ "BriefDescription": "VN0 message can't slot into flit; NCS on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; CHA on VN0",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA",
+ "BriefDescription": "VN0 message can't slot into flit; RSP on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; CHA on VN1",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA",
+ "BriefDescription": "VN0 message can't slot into flit; WB on BL",
+ "EventCode": "0x4E",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE",
+ "BriefDescription": "VN1 message can't slot into flit; REQ on AD",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1",
- "EventCode": "0x3C",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE",
+ "BriefDescription": "VN1 message can't slot into flit; RSP on AD",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Snoop Arbitration; FlowQ Won",
- "Counter": "0,1,2",
- "EventCode": "0x3D",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP",
+ "BriefDescription": "VN1 message can't slot into flit; SNP on AD",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Snoop Arbitration; FlowQ Won",
- "Counter": "0,1,2",
- "EventCode": "0x3D",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP",
+ "BriefDescription": "VN1 message can't slot into flit; NCB on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
- "Counter": "0,1,2",
- "EventCode": "0x3D",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP",
+ "BriefDescription": "VN1 message can't slot into flit; NCS on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
- "Counter": "0,1,2",
- "EventCode": "0x3D",
- "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP",
+ "BriefDescription": "VN1 message can't slot into flit; RSP on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x80",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "VN1 message can't slot into flit; WB on BL",
+ "EventCode": "0x4F",
+ "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x80",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration",
+ "EventCode": "0x62",
+ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x80",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "SMI3 Prefetch Messages; Arrived",
+ "EventCode": "0x62",
+ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x80",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old",
+ "EventCode": "0x62",
+ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x80",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap",
+ "EventCode": "0x62",
+ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP",
"PerPkg": "1",
+ "PublicDescription": "Dropped because it was overwritten by new message while prefetch queue was full",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x80",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "SMI3 Prefetch Messages; Slotted",
+ "EventCode": "0x62",
+ "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x82",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Remote VNA Credits; Any In Use",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "At least one remote vna credit is in use",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x82",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "Remote VNA Credits; Corrected",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of remote vna credits corrected (local return) per cycle",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x82",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Remote VNA Credits; Level < 1",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Remote vna credit level is less than 1 (i.e. no vna credits available)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x82",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "Remote VNA Credits; Level < 4",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x82",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "Remote VNA Credits; Level < 5",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
"PerPkg": "1",
+ "PublicDescription": "Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x82",
- "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5",
- "PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
- },
- {
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x88",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "Remote VNA Credits; Used",
+ "EventCode": "0x5B",
+ "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of remote vna credits consumed per cycle",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x88",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x88",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x88",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x88",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+ "EventCode": "0xB4",
+ "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x88",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x8A",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x8A",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x8A",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x8A",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x8A",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
+ "EventCode": "0xB2",
+ "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of packets bypassing the CMS Ingress",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x8A",
- "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x84",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0",
+ "BriefDescription": "Transgress Injection Starvation; AD - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x84",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1",
+ "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x84",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2",
+ "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x84",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3",
+ "BriefDescription": "Transgress Injection Starvation; BL - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x84",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4",
+ "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x84",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5",
+ "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
+ "EventCode": "0xB3",
+ "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x86",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x86",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x86",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x86",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x86",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x86",
- "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
+ "EventCode": "0xB1",
+ "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0",
- "EventCode": "0x8E",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0",
+ "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC",
"PerPkg": "1",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
"UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1",
- "EventCode": "0x8E",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1",
+ "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x2",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2",
- "EventCode": "0x8E",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2",
+ "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "UMask": "0x4",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3",
- "EventCode": "0x8E",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3",
+ "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x8",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4",
- "EventCode": "0x8E",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4",
+ "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5",
- "EventCode": "0x8E",
- "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5",
+ "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
+ "EventCode": "0xB0",
+ "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0x8C",
- "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0x8C",
- "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0x8C",
- "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0x8C",
- "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0x8C",
- "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0x8C",
- "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5",
+ "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD0",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Clockticks",
- "Counter": "0,1,2",
- "EventCode": "0xC0",
- "EventName": "UNC_M3UPI_CMS_CLOCKTICKS",
- "PerPkg": "1",
- "Unit": "M3UPI"
- },
- {
- "BriefDescription": "Egress Blocking due to Ordering requirements; Up",
- "Counter": "0,1,2",
- "EventCode": "0xAE",
- "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Egress Blocking due to Ordering requirements; Down",
- "Counter": "0,1,2",
- "EventCode": "0xAE",
- "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Left and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Left and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Right and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AD Ring In Use; Right and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA7",
- "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD2",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Left and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA9",
- "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Left and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA9",
- "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Right and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA9",
- "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal AK Ring In Use; Right and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA9",
- "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Left and Even",
- "Counter": "0,1,2",
- "EventCode": "0xAB",
- "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Left and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xAB",
- "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD",
+ "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD4",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Right and Even",
- "Counter": "0,1,2",
- "EventCode": "0xAB",
- "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal BL Ring in Use; Right and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xAB",
- "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal IV Ring in Use; Left",
- "Counter": "0,1,2",
- "EventCode": "0xAD",
- "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Horizontal IV Ring in Use; Right",
- "Counter": "0,1,2",
- "EventCode": "0xAD",
- "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD",
- "Counter": "0,1,2",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK",
- "Counter": "0,1,2",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK",
+ "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
+ "EventCode": "0xD6",
+ "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL",
- "Counter": "0,1,2",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL",
+ "BriefDescription": "Failed ARB for AD; VN0 REQ Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV",
- "Counter": "0,1,2",
- "EventCode": "0xA1",
- "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV",
+ "BriefDescription": "Failed ARB for AD; VN0 RSP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; AD",
- "Counter": "0,1,2",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD",
+ "BriefDescription": "Failed ARB for AD; VN0 SNP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core",
- "Counter": "0,1,2",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK",
+ "BriefDescription": "Failed ARB for AD; VN0 WB Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core",
- "Counter": "0,1,2",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL",
+ "BriefDescription": "Failed ARB for AD; VN1 REQ Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache",
- "Counter": "0,1,2",
- "EventCode": "0xA0",
- "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV",
+ "BriefDescription": "Failed ARB for AD; VN1 RSP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; AD",
- "Counter": "0,1,2",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD",
+ "BriefDescription": "Failed ARB for AD; VN1 SNP Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; AK",
- "Counter": "0,1,2",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK",
+ "BriefDescription": "Failed ARB for AD; VN1 WB Messages",
+ "EventCode": "0x30",
+ "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "AD arb but no win; arb request asserted but not won",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; BL",
- "Counter": "0,1,2",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; IV",
- "Counter": "0,1,2",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0xA3",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; AD",
- "Counter": "0,1,2",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD",
+ "BriefDescription": "AD FlowQ Bypass",
+ "EventCode": "0x2C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core",
- "Counter": "0,1,2",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK",
+ "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core",
- "Counter": "0,1,2",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL",
+ "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache",
- "Counter": "0,1,2",
- "EventCode": "0xA2",
- "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV",
+ "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Source Throttle",
- "Counter": "0,1,2",
- "EventCode": "0xA4",
- "EventName": "UNC_M3UPI_RING_SRC_THRTL",
+ "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ",
+ "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP",
+ "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP",
+ "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP",
+ "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages",
+ "EventCode": "0x27",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the AD Egress queue is Not Empty",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB",
+ "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB",
+ "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN0; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4B",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS",
+ "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ",
+ "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP",
+ "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP",
+ "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP",
+ "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages",
+ "EventCode": "0x2D",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB",
+ "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x10",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB",
+ "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Lost Arb for VN1; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4C",
- "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS",
+ "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0",
+ "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1",
+ "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0",
+ "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1",
+ "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0",
+ "BriefDescription": "Number of Snoop Targets; CHA on VN0",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to CHA",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1",
+ "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn0 Snpf",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win",
- "Counter": "0,1,2",
- "EventCode": "0x4D",
- "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN",
+ "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI0",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ",
+ "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI1",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP",
+ "BriefDescription": "Number of Snoop Targets; CHA on VN1",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to CHA",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP",
+ "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn1 Snpf",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP",
+ "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI0",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB",
+ "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1",
+ "EventCode": "0x3C",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1",
"PerPkg": "1",
+ "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB",
+ "BriefDescription": "Snoop Arbitration; FlowQ Won",
+ "EventCode": "0x3D",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn0",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN0; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x49",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS",
+ "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
+ "EventCode": "0x3D",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn0 SnpF issued when SnpF pending on Vn1",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ",
+ "BriefDescription": "Snoop Arbitration; FlowQ Won",
+ "EventCode": "0x3D",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn1",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP",
+ "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won",
+ "EventCode": "0x3D",
+ "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn1 SnpF issued when SnpF pending on Vn0",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP",
+ "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 REQ Messages",
+ "EventCode": "0x34",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP",
+ "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 SNP Messages",
+ "EventCode": "0x34",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB",
+ "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 WB Messages",
+ "EventCode": "0x34",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB",
+ "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 REQ Messages",
+ "EventCode": "0x34",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Can't Arb for VN1; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4A",
- "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS",
+ "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 SNP Messages",
+ "EventCode": "0x34",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ",
+ "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 WB Messages",
+ "EventCode": "0x34",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP",
+ "BriefDescription": "Speculative ARB for AD - New Message; VN0 REQ Messages",
+ "EventCode": "0x33",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP",
+ "BriefDescription": "Speculative ARB for AD - New Message; VN0 SNP Messages",
+ "EventCode": "0x33",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP",
+ "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB Messages",
+ "EventCode": "0x33",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB",
+ "BriefDescription": "Speculative ARB for AD - New Message; VN1 REQ Messages",
+ "EventCode": "0x33",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ",
"PerPkg": "1",
+ "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB",
+ "BriefDescription": "Speculative ARB for AD - New Message; VN1 SNP Messages",
+ "EventCode": "0x33",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN0; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x47",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS",
+ "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB Messages",
+ "EventCode": "0x33",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ",
"PerPkg": "1",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
+ "PerPkg": "1",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x40",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "No Credits to Arb for VN1; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x48",
- "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS",
+ "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB Messages",
+ "EventCode": "0x32",
+ "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle",
- "Counter": "0,1,2",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE",
+ "BriefDescription": "AK Flow Q Inserts",
+ "EventCode": "0x2F",
+ "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS",
"PerPkg": "1",
- "UMask": "0x01",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb",
- "Counter": "0,1,2",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB",
+ "BriefDescription": "AK Flow Q Occupancy",
+ "EventCode": "0x1E",
+ "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY",
"PerPkg": "1",
- "UMask": "0x02",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1",
- "Counter": "0,1,2",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT",
+ "BriefDescription": "Failed ARB for BL; VN0 NCB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2",
- "Counter": "0,1,2",
- "EventCode": "0x40",
- "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT",
+ "BriefDescription": "Failed ARB for BL; VN0 NCS Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ",
+ "BriefDescription": "Failed ARB for BL; VN0 RSP Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP",
+ "BriefDescription": "Failed ARB for BL; VN0 WB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP",
+ "BriefDescription": "Failed ARB for BL; VN1 NCS Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP",
+ "BriefDescription": "Failed ARB for BL; VN1 NCB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB",
+ "BriefDescription": "Failed ARB for BL; VN1 RSP Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP",
"PerPkg": "1",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB",
+ "BriefDescription": "Failed ARB for BL; VN1 WB Messages",
+ "EventCode": "0x35",
+ "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB",
"PerPkg": "1",
+ "PublicDescription": "BL arb but no win; arb request asserted but not won",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message lost contest for flit; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x50",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS",
+ "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ",
+ "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP",
+ "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP",
+ "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP",
+ "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB",
+ "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB",
+ "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message lost contest for flit; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x51",
- "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS",
+ "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages",
+ "EventCode": "0x28",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of cycles the BL Egress queue is Not Empty",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO",
- "Counter": "0,1,2",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO",
+ "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path",
- "Counter": "0,1,2",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH",
+ "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb",
- "Counter": "0,1,2",
- "EventCode": "0x60",
- "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB",
+ "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy; VNA In Use",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE",
+ "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy; Packets in BGF FIFO",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO",
+ "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy; Packets in BGF Path",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH",
+ "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy; Transmit Credits",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD",
+ "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy; D2K Credits",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD",
+ "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages",
+ "EventCode": "0x2E",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL",
+ "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x20",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Credit Occupancy",
- "Counter": "0,1,2",
- "EventCode": "0x61",
- "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO",
+ "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ",
+ "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP",
+ "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP",
+ "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP",
+ "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB",
+ "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP",
"PerPkg": "1",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB",
+ "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB",
"PerPkg": "1",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x43",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS",
+ "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages",
+ "EventCode": "0x38",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ",
+ "BriefDescription": "Speculative ARB for BL - New Message; VN0 NCS Messages",
+ "EventCode": "0x38",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP",
+ "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages",
+ "EventCode": "0x38",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP",
+ "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB Messages",
+ "EventCode": "0x38",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP",
+ "BriefDescription": "Speculative ARB for BL - New Message; VN1 NCB Messages",
+ "EventCode": "0x38",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB",
+ "BriefDescription": "Speculative ARB for BL - New Message; VN1 RSP Messages",
+ "EventCode": "0x38",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB",
"PerPkg": "1",
+ "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x44",
- "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Data Flit Not Sent; All",
- "Counter": "0,1,2",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Data Flit Not Sent; No BGF Credits",
- "Counter": "0,1,2",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Data Flit Not Sent; No TxQ Credits",
- "Counter": "0,1,2",
- "EventCode": "0x57",
- "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x80",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO",
+ "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages",
+ "EventCode": "0x37",
+ "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY",
+ "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT",
+ "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
"PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0",
+ "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Generating BL Data Flit Sequence",
- "Counter": "0,1,2",
- "EventCode": "0x59",
- "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL",
+ "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC",
- "Counter": "0,1,2",
- "EventCode": "0x5A",
- "EventName": "UNC_M3UPI_RxC_FLITS_MISC",
+ "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
+ "EventCode": "0x9D",
+ "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sent Header Flit; One Message",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG",
+ "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sent Header Flit; Two Messages",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS",
+ "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sent Header Flit; Three Messages",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS",
+ "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Sent Header Flit; One Message in non-VNA",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX",
+ "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; All",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL",
+ "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA",
+ "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
+ "EventCode": "0x9F",
+ "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail",
- "Counter": "0,1,2",
- "EventCode": "0x58",
- "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
"PerPkg": "1",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Acumullate",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
+ "EventCode": "0x96",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Accumulate Ready",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Parallel Ok",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Parallel Message",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG",
+ "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
+ "EventCode": "0x97",
+ "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished",
- "Counter": "0,1,2",
- "EventCode": "0x53",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall",
- "Counter": "0,1,2",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message",
- "Counter": "0,1,2",
- "EventCode": "0x54",
- "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG",
+ "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; All",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL",
+ "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; No BGF Credits",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD",
+ "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; No TxQ Credits",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD",
+ "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
+ "EventCode": "0x95",
+ "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; Sent - One Slot Taken",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN",
+ "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; Sent - Two Slots Taken",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN",
+ "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Header Not Sent; Sent - Three Slots Taken",
- "Counter": "0,1,2",
- "EventCode": "0x55",
- "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN",
+ "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; VN0",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.VN0",
+ "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
+ "EventCode": "0x99",
+ "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; VN1",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.VN1",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; Parallel Attempt",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; Parallel Success",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; Parallel AD Lost",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; Parallel BL Lost",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; Can't Slot AD",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD",
+ "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
+ "EventCode": "0x94",
+ "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Message Held; Can't Slot BL",
- "Counter": "0,1,2",
- "EventCode": "0x52",
- "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP",
+ "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
+ "EventCode": "0x9B",
+ "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x41",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+ "EventCode": "0x9C",
+ "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP",
+ "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB",
+ "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x42",
- "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ",
+ "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP",
+ "BriefDescription": "CMS Vertical ADS Used; IV",
+ "EventCode": "0x9E",
+ "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x45",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
+ "EventCode": "0x92",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x46",
- "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP",
+ "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
+ "EventCode": "0x93",
+ "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP",
+ "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP",
+ "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB",
+ "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB",
+ "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN0 message can't slot into flit; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4E",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS",
+ "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; REQ on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ",
+ "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; SNP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP",
+ "BriefDescription": "CMS Vert Egress Allocations; IV",
+ "EventCode": "0x91",
+ "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; RSP on AD",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP",
+ "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; RSP on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP",
+ "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; WB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB",
+ "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; NCB on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB",
+ "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1",
"PerPkg": "1",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "VN1 message can't slot into flit; NCS on BL",
- "Counter": "0,1,2",
- "EventCode": "0x4F",
- "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS",
+ "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "SMI3 Prefetch Messages; Arrived",
- "Counter": "0,1,2",
- "EventCode": "0x62",
- "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED",
+ "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration",
- "Counter": "0,1,2",
- "EventCode": "0x62",
- "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST",
+ "BriefDescription": "CMS Vertical Egress NACKs; IV",
+ "EventCode": "0x98",
+ "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "SMI3 Prefetch Messages; Slotted",
- "Counter": "0,1,2",
- "EventCode": "0x62",
- "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED",
+ "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old",
- "Counter": "0,1,2",
- "EventCode": "0x62",
- "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD",
+ "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap",
- "Counter": "0,1,2",
- "EventCode": "0x62",
- "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP",
+ "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Remote VNA Credits; Used",
- "Counter": "0,1,2",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED",
+ "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Remote VNA Credits; Corrected",
- "Counter": "0,1,2",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED",
+ "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Remote VNA Credits; Level < 1",
- "Counter": "0,1,2",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1",
+ "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Remote VNA Credits; Level < 4",
- "Counter": "0,1,2",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4",
+ "BriefDescription": "CMS Vert Egress Occupancy; IV",
+ "EventCode": "0x90",
+ "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Remote VNA Credits; Level < 5",
- "Counter": "0,1,2",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Remote VNA Credits; Any In Use",
- "Counter": "0,1,2",
- "EventCode": "0x5B",
- "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1",
"PerPkg": "1",
- "UMask": "0x20",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB4",
- "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1",
"PerPkg": "1",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC",
+ "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
+ "EventCode": "0x9A",
+ "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC",
+ "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC",
+ "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC",
+ "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD",
+ "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Bypass; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB2",
- "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD",
+ "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP",
"PerPkg": "1",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
"UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC",
+ "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC",
+ "BriefDescription": "UPI0 AD Credits Empty; VNA",
+ "EventCode": "0x20",
+ "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "No credits available to send to UPIs on the AD Ring",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC",
+ "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC",
+ "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD",
+ "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD",
+ "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Injection Starvation; IFV - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB3",
- "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV",
+ "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP",
"PerPkg": "1",
- "UMask": "0x80",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC",
+ "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x40",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC",
+ "BriefDescription": "UPI0 BL Credits Empty; VNA",
+ "EventCode": "0x21",
+ "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC",
+ "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit.",
+ "EventCode": "0x29",
+ "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC",
+ "BriefDescription": "Vertical AD Ring In Use; Down and Even",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD",
+ "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Allocations; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB1",
- "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD",
+ "BriefDescription": "Vertical AD Ring In Use; Up and Even",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC",
+ "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
+ "EventCode": "0xA6",
+ "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC",
+ "BriefDescription": "Vertical AK Ring In Use; Down and Even",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC",
+ "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC",
+ "BriefDescription": "Vertical AK Ring In Use; Up and Even",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
+ "PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
+ "Unit": "M3UPI"
+ },
+ {
+ "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
+ "EventCode": "0xA8",
+ "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Vertical BL Ring in Use; Down and Even",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Transgress Ingress Occupancy; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0xB0",
- "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
"PerPkg": "1",
- "UMask": "0x40",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0",
+ "BriefDescription": "Vertical BL Ring in Use; Up and Even",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1",
+ "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
+ "EventCode": "0xAA",
+ "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2",
+ "BriefDescription": "Vertical IV Ring in Use; Down",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3",
+ "BriefDescription": "Vertical IV Ring in Use; Up",
+ "EventCode": "0xAC",
+ "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4",
+ "BriefDescription": "VN0 Credit Used; WB on BL",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0xD0",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5",
+ "BriefDescription": "VN0 Credit Used; NCB on BL",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0",
+ "BriefDescription": "VN0 Credit Used; REQ on AD",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1",
+ "BriefDescription": "VN0 Credit Used; RSP on AD",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2",
+ "BriefDescription": "VN0 Credit Used; SNP on AD",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3",
+ "BriefDescription": "VN0 Credit Used; RSP on BL",
+ "EventCode": "0x5C",
+ "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4",
+ "BriefDescription": "VN0 No Credits; WB on BL",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of Cycles there were no VN0 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0xD2",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5",
+ "BriefDescription": "VN0 No Credits; NCB on BL",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of Cycles there were no VN0 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0",
+ "BriefDescription": "VN0 No Credits; REQ on AD",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of Cycles there were no VN0 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1",
+ "BriefDescription": "VN0 No Credits; RSP on AD",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2",
+ "BriefDescription": "VN0 No Credits; SNP on AD",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of Cycles there were no VN0 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3",
+ "BriefDescription": "VN0 No Credits; RSP on BL",
+ "EventCode": "0x5E",
+ "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4",
+ "BriefDescription": "VN1 Credit Used; WB on BL",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0xD4",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5",
+ "BriefDescription": "VN1 Credit Used; NCB on BL",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0",
- "Counter": "0,1,2",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0",
+ "BriefDescription": "VN1 Credit Used; REQ on AD",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1",
- "Counter": "0,1,2",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1",
+ "BriefDescription": "VN1 Credit Used; RSP on AD",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2",
- "Counter": "0,1,2",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2",
+ "BriefDescription": "VN1 Credit Used; SNP on AD",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3",
- "Counter": "0,1,2",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3",
+ "BriefDescription": "VN1 Credit Used; RSP on BL",
+ "EventCode": "0x5D",
+ "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB",
"PerPkg": "1",
- "UMask": "0x08",
+ "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4",
- "Counter": "0,1,2",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4",
+ "BriefDescription": "VN1 No Credits; WB on BL",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB",
"PerPkg": "1",
+ "PublicDescription": "Number of Cycles there were no VN1 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.",
"UMask": "0x10",
"Unit": "M3UPI"
},
{
- "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5",
- "Counter": "0,1,2",
- "EventCode": "0xD6",
- "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5",
+ "BriefDescription": "VN1 No Credits; NCB on BL",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS",
"PerPkg": "1",
+ "PublicDescription": "Number of Cycles there were no VN1 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.",
"UMask": "0x20",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC",
+ "BriefDescription": "VN1 No Credits; REQ on AD",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ",
"PerPkg": "1",
- "UMask": "0x01",
+ "PublicDescription": "Number of Cycles there were no VN1 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.",
+ "UMask": "0x1",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC",
+ "BriefDescription": "VN1 No Credits; RSP on AD",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP",
"PerPkg": "1",
- "UMask": "0x02",
+ "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x4",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC",
+ "BriefDescription": "VN1 No Credits; SNP on AD",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP",
"PerPkg": "1",
- "UMask": "0x04",
+ "PublicDescription": "Number of Cycles there were no VN1 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.",
+ "UMask": "0x2",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD",
+ "BriefDescription": "VN1 No Credits; RSP on BL",
+ "EventCode": "0x5F",
+ "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB",
"PerPkg": "1",
- "UMask": "0x10",
+ "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).",
+ "UMask": "0x8",
"Unit": "M3UPI"
},
{
- "BriefDescription": "CMS Horizontal ADS Used; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x9D",
- "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI",
+ "Deprecated": "1",
+ "EventCode": "0x40",
+ "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x4",
+ "Unit": "M2M"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9F",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC",
+ "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)",
+ "EventCode": "0x1",
+ "EventName": "UNC_UPI_CLOCKTICKS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9F",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC",
+ "BriefDescription": "Data Response packets that go direct to core",
+ "EventCode": "0x12",
+ "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9F",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U",
+ "Deprecated": "1",
+ "EventCode": "0x12",
+ "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9F",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC",
+ "BriefDescription": "Data Response packets that go direct to Intel UPI",
+ "EventCode": "0x12",
+ "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA .",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x9F",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0",
+ "PerPkg": "1",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
+ },
+ {
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1",
+ "PerPkg": "1",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
+ },
+ {
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2",
+ "PerPkg": "1",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
+ },
+ {
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x9F",
- "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC",
+ "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
+ "EventCode": "0x18",
+ "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC",
+ "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)",
+ "EventCode": "0x21",
+ "EventName": "UNC_UPI_L1_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x96",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC",
+ "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+ "EventCode": "0x14",
+ "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK",
+ "PerPkg": "1",
+ "UMask": "0x10",
+ "Unit": "UPI LL"
+ },
+ {
+ "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
+ "EventCode": "0x16",
+ "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x97",
- "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC",
+ "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
+ "EventCode": "0x15",
+ "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD",
+ "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1",
+ "EventCode": "0x20",
+ "EventName": "UNC_UPI_PHY_INIT_CYCLES",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x95",
- "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD",
+ "BriefDescription": "L1 Req Nack",
+ "EventCode": "0x23",
+ "EventName": "UNC_UPI_POWER_L1_NACK",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC",
+ "BriefDescription": "L1 Req (same as L1 Ack).",
+ "EventCode": "0x22",
+ "EventName": "UNC_UPI_POWER_L1_REQ",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD",
+ "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
+ "EventCode": "0x46",
+ "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x99",
- "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD",
+ "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode",
+ "EventCode": "0x25",
+ "EventName": "UNC_UPI_RxL0P_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts cycles when the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC",
+ "BriefDescription": "Cycles in L0. Receive side.",
+ "EventCode": "0x24",
+ "EventName": "UNC_UPI_RxL0_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCB",
+ "UMask": "0xe",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCB",
+ "UMask": "0x10e",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCS",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCS",
+ "UMask": "0x10f",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit",
- "Counter": "0,1,2",
- "EventCode": "0x94",
- "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Request",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "REQ Message Class",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]",
+ "UMask": "0x108",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x1aa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x12a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce",
- "Counter": "0,1,2",
- "EventCode": "0x9B",
- "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0x10c",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - RSP",
+ "UMask": "0xa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - RSP",
+ "UMask": "0x10a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Snoop",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "SNP Message Class",
+ "UMask": "0x9",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]",
+ "UMask": "0x109",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9C",
- "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0xd",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0",
+ "BriefDescription": "Matches on Receive path of a UPI Port; Writeback",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0x10d",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0",
+ "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0",
+ "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; IV",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV",
+ "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer",
+ "EventCode": "0x31",
+ "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1",
+ "BriefDescription": "VN0 Credit Consumed",
+ "EventCode": "0x39",
+ "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1",
+ "BriefDescription": "VN1 Credit Consumed",
+ "EventCode": "0x3A",
+ "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9E",
- "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1",
+ "BriefDescription": "VNA Credit Consumed",
+ "EventCode": "0x38",
+ "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0",
+ "BriefDescription": "Valid data FLITs received from any slot",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0",
+ "BriefDescription": "Null FLITs received from any slot",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.",
+ "UMask": "0x27",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0",
+ "BriefDescription": "Valid Flits Received; Data",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.DATA",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV",
+ "BriefDescription": "Valid Flits Received; Idle",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.IDLE",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).",
+ "UMask": "0x47",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1",
+ "BriefDescription": "Valid Flits Received; LLCRD Not Empty",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.LLCRD",
"PerPkg": "1",
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1",
+ "BriefDescription": "Valid Flits Received; LLCTRL",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.LLCTRL",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x92",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1",
+ "BriefDescription": "Protocol header and credit FLITs received from any slot",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.NON_DATA",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit.",
+ "UMask": "0x97",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL",
+ "Deprecated": "1",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.NULL",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0",
+ "BriefDescription": "Valid Flits Received; Protocol Header",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.PROTHDR",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR",
+ "Deprecated": "1",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV",
+ "BriefDescription": "Valid Flits Received; Slot 0",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT0",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1",
+ "BriefDescription": "Valid Flits Received; Slot 1",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1",
+ "BriefDescription": "Valid Flits Received; Slot 2",
+ "EventCode": "0x3",
+ "EventName": "UNC_UPI_RxL_FLITS.SLOT2",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x93",
- "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB",
+ "Deprecated": "1",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS",
+ "Deprecated": "1",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0xd",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ",
+ "Deprecated": "1",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA",
+ "Deprecated": "1",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0xa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; IV",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP",
+ "Deprecated": "1",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP",
+ "PerPkg": "1",
+ "UMask": "0x9",
+ "Unit": "UPI LL"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB",
+ "Deprecated": "1",
+ "EventCode": "0x5",
+ "EventName": "UNC_UPI_RxL_HDR_MATCH.WB",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "UMask": "0xb",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1",
+ "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT0",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1",
+ "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT1",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x91",
- "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1",
+ "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2",
+ "EventCode": "0x30",
+ "EventName": "UNC_UPI_RxL_INSERTS.SLOT2",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0",
+ "BriefDescription": "RxQ Occupancy - All Packets; Slot 0",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0",
+ "BriefDescription": "RxQ Occupancy - All Packets; Slot 1",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0",
+ "BriefDescription": "RxQ Occupancy - All Packets; Slot 2",
+ "EventCode": "0x32",
+ "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0",
+ "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
+ "EventCode": "0x33",
+ "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; IV",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY",
"PerPkg": "1",
"UMask": "0x20",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x90",
- "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1",
+ "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
+ "EventCode": "0x2A",
+ "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ",
"PerPkg": "1",
"UMask": "0x10",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1",
+ "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode",
+ "EventCode": "0x27",
+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1",
+ "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
+ "EventCode": "0x28",
+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Up and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN",
+ "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
+ "EventCode": "0x29",
+ "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Up and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD",
+ "BriefDescription": "Cycles in L0. Transmit side.",
+ "EventCode": "0x26",
+ "EventName": "UNC_UPI_TxL0_POWER_CYCLES",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Down and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCB",
+ "UMask": "0xe",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AD Ring In Use; Down and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA6",
- "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCB",
+ "UMask": "0x10e",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Up and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA8",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCS",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Up and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA8",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - NCS",
+ "UMask": "0x10f",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Down and Even",
- "Counter": "0,1,2",
- "EventCode": "0xA8",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Request",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "REQ Message Class",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical AK Ring In Use; Down and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xA8",
- "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]",
+ "UMask": "0x108",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Up and Even",
- "Counter": "0,1,2",
- "EventCode": "0xAA",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "UMask": "0x1aa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Up and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xAA",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "UMask": "0x12a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Down and Even",
- "Counter": "0,1,2",
- "EventCode": "0xAA",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical BL Ring in Use; Down and Odd",
- "Counter": "0,1,2",
- "EventCode": "0xAA",
- "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0x10c",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical IV Ring in Use; Up",
- "Counter": "0,1,2",
- "EventCode": "0xAC",
- "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - RSP",
+ "UMask": "0xa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Vertical IV Ring in Use; Down",
- "Counter": "0,1,2",
- "EventCode": "0xAC",
- "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class - RSP",
+ "UMask": "0x10a",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "D2C Sent",
- "Counter": "0,1,2",
- "EventCode": "0x2B",
- "EventName": "UNC_M3UPI_D2C_SENT",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
"PerPkg": "1",
- "Unit": "M3UPI"
+ "PublicDescription": "SNP Message Class",
+ "UMask": "0x9",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "FaST wire asserted; Vertical",
- "Counter": "0,1,2",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]",
+ "UMask": "0x109",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "FaST wire asserted; Horizontal",
- "Counter": "0,1,2",
- "EventCode": "0xA5",
- "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0xd",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Sent Header Flit",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1",
+ "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "M3UPI"
+ "PublicDescription": "Match Message Class -WB",
+ "UMask": "0x10d",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Sent Header Flit",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2",
+ "BriefDescription": "FLITs that bypassed the TxL Buffer",
+ "EventCode": "0x41",
+ "EventName": "UNC_UPI_TxL_BYPASSED",
"PerPkg": "1",
- "UMask": "0x20",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Sent Header Flit",
- "Counter": "0,1,2",
- "EventCode": "0x56",
- "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3",
+ "BriefDescription": "Valid data FLITs transmitted via any slot",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA",
"PerPkg": "1",
- "UMask": "0x40",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path Interconnect (UPI) slots on this UPI unit.",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress NACKs; IV",
- "Counter": "0,1,2",
- "EventCode": "0x98",
- "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV",
+ "BriefDescription": "Null FLITs transmitted from any slot",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unit.",
+ "UMask": "0x27",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "CMS Vertical Egress Injection Starvation; IV",
- "Counter": "0,1,2",
- "EventCode": "0x9A",
- "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV",
+ "BriefDescription": "Valid Flits Sent; Data",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.DATA",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..",
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VNA",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA",
+ "BriefDescription": "Idle FLITs transmitted",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.IDLE",
"PerPkg": "1",
- "UMask": "0x01",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs.",
+ "UMask": "0x47",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP",
+ "BriefDescription": "Valid Flits Sent; LLCRD Not Empty",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.LLCRD",
"PerPkg": "1",
- "UMask": "0x02",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2",
+ "UMask": "0x10",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB",
+ "BriefDescription": "Valid Flits Sent; LLCTRL",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.LLCTRL",
"PerPkg": "1",
- "UMask": "0x04",
- "Unit": "M3UPI"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.",
+ "UMask": "0x40",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages",
- "Counter": "0,1,2",
- "EventCode": "0x21",
- "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB",
+ "BriefDescription": "Protocol header and credit FLITs transmitted across any slot",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.NON_DATA",
"PerPkg": "1",
- "UMask": "0x08",
- "Unit": "M3UPI"
+ "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit.",
+ "UMask": "0x97",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Message Received; VLW",
- "Counter": "0,1",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL",
+ "Deprecated": "1",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.NULL",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UBOX"
+ "UMask": "0x20",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Message Received; MSI",
- "Counter": "0,1",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+ "BriefDescription": "Valid Flits Sent; Protocol Header",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.PROTHDR",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UBOX"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)",
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Message Received; IPI",
- "Counter": "0,1",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR",
+ "Deprecated": "1",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "UBOX"
+ "UMask": "0x80",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Message Received",
- "Counter": "0,1",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
+ "BriefDescription": "Valid Flits Sent; Slot 0",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT0",
"PerPkg": "1",
- "UMask": "0x8",
- "Unit": "UBOX"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.",
+ "UMask": "0x1",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Message Received",
- "Counter": "0,1",
- "EventCode": "0x42",
- "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+ "BriefDescription": "Valid Flits Sent; Slot 1",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT1",
"PerPkg": "1",
- "UMask": "0x10",
- "Unit": "UBOX"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.",
+ "UMask": "0x2",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "IDI Lock/SplitLock Cycles",
- "Counter": "0,1",
- "EventCode": "0x44",
- "EventName": "UNC_U_LOCK_CYCLES",
+ "BriefDescription": "Valid Flits Sent; Slot 2",
+ "EventCode": "0x2",
+ "EventName": "UNC_UPI_TxL_FLITS.SLOT2",
"PerPkg": "1",
- "Unit": "UBOX"
+ "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.",
+ "UMask": "0x4",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
- "Counter": "0,1",
- "EventCode": "0x45",
- "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UBOX"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
- "Counter": "0,1",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.RDRAND",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR",
"PerPkg": "1",
- "UMask": "0x1",
- "Unit": "UBOX"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
- "Counter": "0,1",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.RDSEED",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC",
"PerPkg": "1",
- "UMask": "0x2",
- "Unit": "UBOX"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
- "Counter": "0,1",
- "EventCode": "0x4C",
- "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB",
+ "Deprecated": "1",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB",
"PerPkg": "1",
- "UMask": "0x4",
- "Unit": "UBOX"
+ "UMask": "0xe",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "RACU Request",
- "Counter": "0,1",
- "EventCode": "0x46",
- "EventName": "UNC_U_RACU_REQUESTS",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS",
+ "Deprecated": "1",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS",
"PerPkg": "1",
- "Unit": "UBOX"
+ "UMask": "0xf",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
- "Counter": "FIXED",
- "EventCode": "0xff",
- "EventName": "UNC_U_CLOCKTICKS",
+ "BriefDescription": "This event is deprecated.",
+ "Deprecated": "1",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR",
"PerPkg": "1",
- "Unit": "UBOX"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0x33",
- "EventName": "UNC_H_CORE_SNP.CORE_GTONE",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.REM",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE",
- "UMask": "0x42",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ",
"Deprecated": "1",
- "EventCode": "0x33",
- "EventName": "UNC_H_CORE_SNP.EVICT_GTONE",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE",
- "UMask": "0x82",
- "Unit": "CHA"
+ "UMask": "0x8",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA",
"Deprecated": "1",
- "EventCode": "0x53",
- "EventName": "UNC_H_DIR_LOOKUP.NO_SNP",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP",
- "UMask": "0x2",
- "Unit": "CHA"
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA",
"Deprecated": "1",
- "EventCode": "0x53",
- "EventName": "UNC_H_DIR_LOOKUP.SNP",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP",
- "UMask": "0x1",
- "Unit": "CHA"
+ "UMask": "0xa",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated.",
"Deprecated": "1",
- "EventCode": "0x54",
- "EventName": "UNC_H_DIR_UPDATE.HA",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA",
- "UMask": "0x1",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP",
"Deprecated": "1",
- "EventCode": "0x54",
- "EventName": "UNC_H_DIR_UPDATE.TOR",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR",
- "UMask": "0x2",
- "Unit": "CHA"
+ "UMask": "0x9",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS",
- "Counter": "0,1,2,3",
+ "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB",
"Deprecated": "1",
- "EventCode": "0x5F",
- "EventName": "UNC_H_HITME_HIT.EX_RDS",
+ "EventCode": "0x4",
+ "EventName": "UNC_UPI_TxL_HDR_MATCH.WB",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS",
- "UMask": "0x1",
- "Unit": "CHA"
+ "UMask": "0xc",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x39",
- "EventName": "UNC_H_MISC.RFO_HIT_S",
+ "BriefDescription": "Tx Flit Buffer Allocations",
+ "EventCode": "0x40",
+ "EventName": "UNC_UPI_TxL_INSERTS",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S",
- "UMask": "0x8",
- "Unit": "CHA"
+ "PublicDescription": "Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x50",
- "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL",
+ "BriefDescription": "Tx Flit Buffer Occupancy",
+ "EventCode": "0x42",
+ "EventName": "UNC_UPI_TxL_OCCUPANCY",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL",
- "UMask": "0x10",
- "Unit": "CHA"
+ "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x50",
- "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE",
+ "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
+ "EventCode": "0x45",
+ "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE",
- "UMask": "0x20",
- "Unit": "CHA"
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x50",
- "EventName": "UNC_H_REQUESTS.READS",
+ "BriefDescription": "VNA Credits Pending Return - Occupancy",
+ "EventCode": "0x44",
+ "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS",
- "UMask": "0x3",
- "Unit": "CHA"
+ "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
+ "Unit": "UPI LL"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x50",
- "EventName": "UNC_H_REQUESTS.READS_LOCAL",
+ "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter",
+ "EventCode": "0xff",
+ "EventName": "UNC_U_CLOCKTICKS",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL",
- "UMask": "0x1",
- "Unit": "CHA"
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x50",
- "EventName": "UNC_H_REQUESTS.WRITES",
+ "BriefDescription": "Message Received",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES",
- "UMask": "0xC",
- "Unit": "CHA"
+ "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.",
+ "UMask": "0x8",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x50",
- "EventName": "UNC_H_REQUESTS.WRITES_LOCAL",
+ "BriefDescription": "Message Received",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.INT_PRIO",
+ "PerPkg": "1",
+ "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.",
+ "UMask": "0x10",
+ "Unit": "UBOX"
+ },
+ {
+ "BriefDescription": "Message Received; IPI",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.IPI_RCVD",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL",
+ "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Inter Processor Interrupts",
"UMask": "0x4",
- "Unit": "CHA"
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x13",
- "EventName": "UNC_H_RxC_INSERTS.IRQ",
+ "BriefDescription": "Message Received; MSI",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.MSI_RCVD",
+ "PerPkg": "1",
+ "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)",
+ "UMask": "0x2",
+ "Unit": "UBOX"
+ },
+ {
+ "BriefDescription": "Message Received; VLW",
+ "EventCode": "0x42",
+ "EventName": "UNC_U_EVENT_MSG.VLW_RCVD",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ",
+ "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.",
"UMask": "0x1",
- "Unit": "CHA"
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x19",
- "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH",
+ "BriefDescription": "IDI Lock/SplitLock Cycles",
+ "EventCode": "0x44",
+ "EventName": "UNC_U_LOCK_CYCLES",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH",
- "UMask": "0x80",
- "Unit": "CHA"
+ "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ",
- "Deprecated": "1",
- "EventCode": "0x11",
- "EventName": "UNC_H_RxC_OCCUPANCY.IRQ",
+ "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK",
+ "EventCode": "0x45",
+ "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ",
+ "PublicDescription": "PHOLD cycles.",
"UMask": "0x1",
- "Unit": "CHA"
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5C",
- "EventName": "UNC_H_SNOOP_RESP.RSPIFWD",
+ "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD",
"UMask": "0x4",
- "Unit": "CHA"
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5C",
- "EventName": "UNC_H_SNOOP_RESP.RSPSFWD",
+ "BriefDescription": "UNC_U_RACU_DRNG.RDRAND",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.RDRAND",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD",
- "UMask": "0x8",
- "Unit": "CHA"
+ "UMask": "0x1",
+ "Unit": "UBOX"
},
{
- "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
- "Counter": "0,1,2,3",
- "Deprecated": "1",
- "EventCode": "0x5C",
- "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB",
+ "BriefDescription": "UNC_U_RACU_DRNG.RDSEED",
+ "EventCode": "0x4C",
+ "EventName": "UNC_U_RACU_DRNG.RDSEED",
"PerPkg": "1",
- "PublicDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB",
- "UMask": "0x20",
- "Unit": "CHA"
+ "UMask": "0x2",
+ "Unit": "UBOX"
+ },
+ {
+ "BriefDescription": "RACU Request",
+ "EventCode": "0x46",
+ "EventName": "UNC_U_RACU_REQUESTS",
+ "PerPkg": "1",
+ "PublicDescription": "Number outstanding register requests within message channel tracker",
+ "Unit": "UBOX"
+ },
+ {
+ "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data",
+ "EventCode": "0x2",
+ "EventName": "UPI_DATA_BANDWIDTH_TX",
+ "PerPkg": "1",
+ "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path Interconnect (UPI) slots on this UPI unit.",
+ "ScaleUnit": "7.11E-06Bytes",
+ "UMask": "0xf",
+ "Unit": "UPI LL"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json
index 64301a600ede..6835e14cd42c 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json
@@ -1,14 +1,13 @@
[
{
"BriefDescription": "pclk Cycles",
- "Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
+ "PublicDescription": "The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",
- "Counter": "0,1,2,3",
"EventCode": "0x60",
"EventName": "UNC_P_CORE_TRANSITION_CYCLES",
"PerPkg": "1",
@@ -16,7 +15,6 @@
},
{
"BriefDescription": "UNC_P_DEMOTIONS",
- "Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS",
"PerPkg": "1",
@@ -24,71 +22,70 @@
},
{
"BriefDescription": "Phase Shed 0 Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x75",
"EventName": "UNC_P_FIVR_PS_PS0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Cycles spent in phase-shedding power state 0",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 1 Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x76",
"EventName": "UNC_P_FIVR_PS_PS1_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Cycles spent in phase-shedding power state 1",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 2 Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x77",
"EventName": "UNC_P_FIVR_PS_PS2_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Cycles spent in phase-shedding power state 2",
"Unit": "PCU"
},
{
"BriefDescription": "Phase Shed 3 Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x78",
"EventName": "UNC_P_FIVR_PS_PS3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Cycles spent in phase-shedding power state 3",
"Unit": "PCU"
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
"Unit": "PCU"
},
{
"BriefDescription": "Power Strongest Upper Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when power is the upper limit on frequency.",
"Unit": "PCU"
},
{
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
- "Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES",
- "Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_MCP_PROCHOT_CYCLES",
"PerPkg": "1",
@@ -96,47 +93,46 @@
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
- "Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
- "Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C2E. This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
- "Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C3. This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
- "Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",
- "Counter": "0,1,2,3",
"EventCode": "0x7",
"EventName": "UNC_P_PMAX_THROTTLED_CYCLES",
"PerPkg": "1",
@@ -144,55 +140,54 @@
},
{
"BriefDescription": "Number of cores in C-State; C0 and C1",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C3",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C6 and C7",
- "Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
+ "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.",
"Unit": "PCU"
},
{
"BriefDescription": "External Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Internal Prochot",
- "Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
"Unit": "PCU"
},
{
"BriefDescription": "Total Core C State Transition Cycles",
- "Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
+ "PublicDescription": "Number of cycles spent performing core C state transitions across all cores.",
"Unit": "PCU"
},
{
"BriefDescription": "VR Hot",
- "Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json
index dd334b416c57..f59405877ae8 100644
--- a/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Load misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@@ -11,8 +9,6 @@
},
{
"BriefDescription": "Loads that miss the DTLB and hit the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
@@ -21,8 +17,6 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -42,8 +34,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data load to a 1G page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -52,8 +42,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -62,8 +50,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data load to a 4K page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -72,8 +58,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake microarchitecture.",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Store misses in all DTLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.",
@@ -92,8 +74,6 @@
},
{
"BriefDescription": "Stores that miss the DTLB and hit the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
@@ -102,8 +82,6 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
@@ -113,8 +91,6 @@
},
{
"BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -123,8 +99,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 1G page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -133,8 +107,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -143,8 +115,6 @@
},
{
"BriefDescription": "Page walk completed due to a demand data store to a 4K page",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
@@ -153,8 +123,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.",
@@ -163,8 +131,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4f",
"EventName": "EPT.WALK_PENDING",
"PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.",
@@ -173,8 +139,6 @@
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
@@ -183,8 +147,6 @@
},
{
"BriefDescription": "Misses at all ITLB levels that cause page walks",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.",
@@ -193,8 +155,6 @@
},
{
"BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003",
@@ -202,8 +162,6 @@
},
{
"BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_ACTIVE",
@@ -213,8 +171,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -223,8 +179,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -233,8 +187,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -243,8 +195,6 @@
},
{
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
@@ -253,8 +203,6 @@
},
{
"BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_PENDING",
"PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.",
@@ -263,8 +211,6 @@
},
{
"BriefDescription": "DTLB flush attempts of the thread-specific entries",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
@@ -273,8 +219,6 @@
},
{
"BriefDescription": "STLB flush attempts",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
--
2.39.0.314.g84b9a713c41-goog
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2022-12-15 6:49 [PATCH v1 06/32] perf vendor events intel: Refresh broadwellde metrics and events Ian Rogers
2022-12-15 6:49 ` [PATCH v1 07/32] perf vendor events intel: Refresh broadwellx " Ian Rogers
2022-12-15 6:49 ` [PATCH v1 08/32] perf vendor events intel: Refresh cascadelakex " Ian Rogers
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