From: Yongqiang Niu <yongqiang.niu@mediatek.com> To: CK Hu <ck.hu@mediatek.com>, Chun-Kuang Hu <chunkuang.hu@kernel.org>, Jassi Brar <jassisinghbrar@gmail.com>, Matthias Brugger <matthias.bgg@gmail.com> Cc: <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, Hsin-Yi Wang <hsinyi@chromium.org>, Yongqiang Niu <yongqiang.niu@mediatek.com> Subject: [PATCH v11, 2/4] mailbox: mtk-cmdq: add gce software ddr enable private data Date: Thu, 15 Dec 2022 15:28:04 +0800 [thread overview] Message-ID: <20221215072806.10224-3-yongqiang.niu@mediatek.com> (raw) In-Reply-To: <20221215072806.10224-1-yongqiang.niu@mediatek.com> if gce work control by software, we need set software enable for MT8186 Soc there is a handshake flow between gce and ddr hardware, if not set ddr enable flag of gce, ddr will fall into idle mode, then gce instructions will not process done. we need set this flag of gce to tell ddr when gce is idle or busy controlled by software flow. 0x48[2:0] means control by software 0x48[18:16] means ddr enable 0x48[2:0] is pre-condition of 0x48[18:16]. if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same time. and only these bits is useful, other bits is useless bits Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/mailbox/mtk-cmdq-mailbox.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index c3cb24f51699..d2363c6b8b7a 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -39,6 +39,7 @@ #define GCE_GCTL_VALUE 0x48 #define GCE_CTRL_BY_SW GENMASK(2, 0) +#define GCE_DDR_EN GENMASK(18, 16) #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 @@ -81,6 +82,7 @@ struct cmdq { bool suspended; u8 shift_pa; bool control_by_sw; + bool sw_ddr_en; u32 gce_num; }; @@ -88,6 +90,7 @@ struct gce_plat { u32 thread_nr; u8 shift; bool control_by_sw; + bool sw_ddr_en; u32 gce_num; }; @@ -127,10 +130,16 @@ static void cmdq_thread_resume(struct cmdq_thread *thread) static void cmdq_init(struct cmdq *cmdq) { int i; + u32 gctl_regval = 0; WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); if (cmdq->control_by_sw) - writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + gctl_regval = GCE_CTRL_BY_SW; + if (cmdq->sw_ddr_en) + gctl_regval |= GCE_DDR_EN; + + if (gctl_regval) + writel(gctl_regval, cmdq->base + GCE_GCTL_VALUE); writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i = 0; i <= CMDQ_MAX_EVENT; i++) @@ -545,6 +554,7 @@ static int cmdq_probe(struct platform_device *pdev) cmdq->thread_nr = plat_data->thread_nr; cmdq->shift_pa = plat_data->shift; cmdq->control_by_sw = plat_data->control_by_sw; + cmdq->sw_ddr_en = plat_data->sw_ddr_en; cmdq->gce_num = plat_data->gce_num; cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Yongqiang Niu <yongqiang.niu@mediatek.com> To: CK Hu <ck.hu@mediatek.com>, Chun-Kuang Hu <chunkuang.hu@kernel.org>, Jassi Brar <jassisinghbrar@gmail.com>, Matthias Brugger <matthias.bgg@gmail.com> Cc: <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-mediatek@lists.infradead.org>, <Project_Global_Chrome_Upstream_Group@mediatek.com>, Hsin-Yi Wang <hsinyi@chromium.org>, Yongqiang Niu <yongqiang.niu@mediatek.com> Subject: [PATCH v11, 2/4] mailbox: mtk-cmdq: add gce software ddr enable private data Date: Thu, 15 Dec 2022 15:28:04 +0800 [thread overview] Message-ID: <20221215072806.10224-3-yongqiang.niu@mediatek.com> (raw) In-Reply-To: <20221215072806.10224-1-yongqiang.niu@mediatek.com> if gce work control by software, we need set software enable for MT8186 Soc there is a handshake flow between gce and ddr hardware, if not set ddr enable flag of gce, ddr will fall into idle mode, then gce instructions will not process done. we need set this flag of gce to tell ddr when gce is idle or busy controlled by software flow. 0x48[2:0] means control by software 0x48[18:16] means ddr enable 0x48[2:0] is pre-condition of 0x48[18:16]. if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same time. and only these bits is useful, other bits is useless bits Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> --- drivers/mailbox/mtk-cmdq-mailbox.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index c3cb24f51699..d2363c6b8b7a 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -39,6 +39,7 @@ #define GCE_GCTL_VALUE 0x48 #define GCE_CTRL_BY_SW GENMASK(2, 0) +#define GCE_DDR_EN GENMASK(18, 16) #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 @@ -81,6 +82,7 @@ struct cmdq { bool suspended; u8 shift_pa; bool control_by_sw; + bool sw_ddr_en; u32 gce_num; }; @@ -88,6 +90,7 @@ struct gce_plat { u32 thread_nr; u8 shift; bool control_by_sw; + bool sw_ddr_en; u32 gce_num; }; @@ -127,10 +130,16 @@ static void cmdq_thread_resume(struct cmdq_thread *thread) static void cmdq_init(struct cmdq *cmdq) { int i; + u32 gctl_regval = 0; WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); if (cmdq->control_by_sw) - writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + gctl_regval = GCE_CTRL_BY_SW; + if (cmdq->sw_ddr_en) + gctl_regval |= GCE_DDR_EN; + + if (gctl_regval) + writel(gctl_regval, cmdq->base + GCE_GCTL_VALUE); writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i = 0; i <= CMDQ_MAX_EVENT; i++) @@ -545,6 +554,7 @@ static int cmdq_probe(struct platform_device *pdev) cmdq->thread_nr = plat_data->thread_nr; cmdq->shift_pa = plat_data->shift; cmdq->control_by_sw = plat_data->control_by_sw; + cmdq->sw_ddr_en = plat_data->sw_ddr_en; cmdq->gce_num = plat_data->gce_num; cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-12-15 7:28 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-15 7:28 [PATCH v11, 0/4] mailbox: mtk-cmdq: add MT8186 support Yongqiang Niu 2022-12-15 7:28 ` Yongqiang Niu 2022-12-15 7:28 ` [PATCH v11, 1/4] mailbox: mtk-cmdq: Use GCE_CTRL_BY_SW definition instead of number Yongqiang Niu 2022-12-15 7:28 ` Yongqiang Niu 2022-12-15 7:28 ` Yongqiang Niu [this message] 2022-12-15 7:28 ` [PATCH v11, 2/4] mailbox: mtk-cmdq: add gce software ddr enable private data Yongqiang Niu 2022-12-15 7:28 ` [PATCH v11, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow Yongqiang Niu 2022-12-15 7:28 ` Yongqiang Niu 2022-12-15 7:28 ` [PATCH v11, 4/4] mailbox: mtk-cmdq: add MT8186 support Yongqiang Niu 2022-12-15 7:28 ` Yongqiang Niu
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