[PATCH v2 0/3] arm64: dts: qcom: sm6125: QUPs, SPI and Seine I2C buses

[PATCH v2 0/3] arm64: dts: qcom: sm6125: QUPs, SPI and Seine I2C buses

[Marijn Suijten]

Introduce Qualcomm Universal Peripheral support on SM6125 and define all
known SPI and I2C Serial Engines.  On Sony Seine PDX201 all I2C buses
with known-connected hardware are enabled for future hardware mapping,
together with the respective GPI DMA 0 and QUP 0.

Changes since v1:
- Un-downstream pinctrl mapping:
  - Remove nested mux {} / config {};
  - Remove useless comments;
  - Remove unreferenced pinctrl states;
- Use qup14 pinctrl function name instead of unknown qup_14;
- Reword commit message;
- Add iommus to QUP nodes now that this series depends on apps_smmu to
  be available;
- Reorder all properties to match other SoCs;
- Reorder/intersperse QUP nodes with GPI DMA nodes to maintain sorting
  by address;
- Reorder SPI nodes to fit in with I2C nodes, restoring sorting by
  address too;
- Use QCOM_GPI_* constants;
- Adhere to 3 instead of 5 dma cells for gpi_dma.

v1: https://lore.kernel.org/all/20221001185628.494884-1-martin.botka@somainline.org/T/#u

Depends on:
- SM6125 APPS SMMU: https://lore.kernel.org/linux-arm-msm/20221216215819.1164973-1-marijn.suijten@somainline.org/T/#u
- SM6125 GPI DMA: https://lore.kernel.org/linux-arm-msm/20221216231528.1268447-1-marijn.suijten@somainline.org/T/#u

Marijn Suijten (2):
  arm64: dts: qcom: sm6125: Add QUPs with SPI and I2C Serial Engines
  arm64: dts: qcom: sm6125-seine: Enable GPI DMA 0, QUP 0 and I2C SEs

Martin Botka (1):
  arm64: dts: qcom: sm6125: Add pin configs for QUP SPI/I2C Serial
    Engines

 .../qcom/sm6125-sony-xperia-seine-pdx201.dts  |  29 +
 arch/arm64/boot/dts/qcom/sm6125.dtsi          | 522 ++++++++++++++++++
 2 files changed, 551 insertions(+)

--
2.39.0

[PATCH v2 1/3] arm64: dts: qcom: sm6125: Add pin configs for QUP SPI/I2C Serial Engines

[Marijn Suijten]

From: Martin Botka <martin.botka@somainline.org>

Add pin setup for SPI/I2C Serial Engines that are supported under the
Qualcomm Universal Peripheral found on SM6125.

Signed-off-by: Martin Botka <martin.botka@somainline.org>
[Un-nest pins, remove duplicate pins= properties, follow new node naming
 conventions, fix qup_14 -> qup14 function typo]
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
---
 arch/arm64/boot/dts/qcom/sm6125.dtsi | 224 +++++++++++++++++++++++++++
 1 file changed, 224 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index abcd634c4f6d..5fc304b2da63 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -426,6 +426,230 @@ data-pins {
 					bias-pull-up;
 				};
 			};
+
+			qup_i2c0_default: qup-i2c0-default-state {
+				pins = "gpio0", "gpio1";
+				function = "qup00";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_i2c0_sleep: qup-i2c0-sleep-state {
+				pins = "gpio0", "gpio1";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c1_default: qup-i2c1-default-state {
+				pins = "gpio4", "gpio5";
+				function = "qup01";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_i2c1_sleep: qup-i2c1-sleep-state {
+				pins = "gpio4", "gpio5";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c2_default: qup-i2c2-default-state {
+				pins = "gpio6", "gpio7";
+				function = "qup02";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_i2c2_sleep: qup-i2c2-sleep-state {
+				pins = "gpio6", "gpio7";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c3_default: qup-i2c3-default-state {
+				pins = "gpio14", "gpio15";
+				function = "qup03";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_i2c3_sleep: qup-i2c3-sleep-state {
+				pins = "gpio14", "gpio15";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c4_default: qup-i2c4-default-state {
+				pins = "gpio16", "gpio17";
+				function = "qup04";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_i2c4_sleep: qup-i2c4-sleep-state {
+				pins = "gpio16", "gpio17";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c5_default: qup-i2c5-default-state {
+				pins = "gpio22", "gpio23";
+				function = "qup10";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_i2c5_sleep: qup-i2c5-sleep-state {
+				pins = "gpio22", "gpio23";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c6_default: qup-i2c6-default-state {
+				pins = "gpio30", "gpio31";
+				function = "qup11";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_i2c6_sleep: qup-i2c6-sleep-state {
+				pins = "gpio30", "gpio31";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c7_default: qup-i2c7-default-state {
+				pins = "gpio28", "gpio29";
+				function = "qup12";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_i2c7_sleep: qup-i2c7-sleep-state {
+				pins = "gpio28", "gpio29";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c8_default: qup-i2c8-default-state {
+				pins = "gpio18", "gpio19";
+				function = "qup13";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_i2c8_sleep: qup-i2c8-sleep-state {
+				pins = "gpio18", "gpio19";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_i2c9_default: qup-i2c9-default-state {
+				pins = "gpio10", "gpio11";
+				function = "qup14";
+				drive-strength = <2>;
+				bias-disable;
+			};
+
+			qup_i2c9_sleep: qup-i2c9-sleep-state {
+				pins = "gpio10", "gpio11";
+				function = "gpio";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
+			qup_spi0_default: qup-spi0-default-state {
+				pins = "gpio0", "gpio1", "gpio2", "gpio3";
+				function = "qup00";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi0_sleep: qup-spi0-sleep-state {
+				pins = "gpio0", "gpio1", "gpio2", "gpio3";
+				function = "gpio";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi2_default: qup-spi2-default-state {
+				pins = "gpio6", "gpio7", "gpio8", "gpio9";
+				function = "qup02";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi2_sleep: qup-spi2-sleep-state {
+				pins = "gpio6", "gpio7", "gpio8", "gpio9";
+				function = "gpio";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi5_default: qup-spi5-default-state {
+				pins = "gpio22", "gpio23", "gpio24", "gpio25";
+				function = "qup10";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi5_sleep: qup-spi5-sleep-state {
+				pins = "gpio22", "gpio23", "gpio24", "gpio25";
+				function = "gpio";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi6_default: qup-spi6-default-state {
+				pins = "gpio30", "gpio31", "gpio32", "gpio33";
+				function = "qup11";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi6_sleep: qup-spi6-sleep-state {
+				pins = "gpio30", "gpio31", "gpio32", "gpio33";
+				function = "gpio";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi8_default: qup-spi8-default-state {
+				pins = "gpio18", "gpio19", "gpio20", "gpio21";
+				function = "qup13";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi8_sleep: qup-spi8-sleep-state {
+				pins = "gpio18", "gpio19", "gpio20", "gpio21";
+				function = "gpio";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi9_default: qup-spi9-default-state {
+				pins = "gpio10", "gpio11", "gpio12", "gpio13";
+				function = "qup14";
+				drive-strength = <6>;
+				bias-disable;
+			};
+
+			qup_spi9_sleep: qup-spi9-sleep-state {
+				pins = "gpio10", "gpio11", "gpio12", "gpio13";
+				function = "gpio";
+				drive-strength = <6>;
+				bias-disable;
+			};
 		};
 
 		gcc: clock-controller@1400000 {
-- 
2.39.0

[PATCH v2 2/3] arm64: dts: qcom: sm6125: Add QUPs with SPI and I2C Serial Engines

[Marijn Suijten]

Add Qualcomm Universal Peripheral nodes with SPI and I2C Serial Engines.
QUP 0 only has two SPIs at index 0 and 2, QUP 1 has four SPIs with a gap
in the middle (ranging from 5-9 with SPI 7 missing).  Both QUPs have 5
I2C Serial Engines.

Signed-off-by: Martin Botka <martin.botka@somainline.org>
[Marijn: Add iommus, reword patch description, reorder all properties,
 sort based on address, use QCOM_GPI_ constants, drop dma cells from 5
 to 3]
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
---
 arch/arm64/boot/dts/qcom/sm6125.dtsi | 298 +++++++++++++++++++++++++++
 1 file changed, 298 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 5fc304b2da63..36ba74b5ad89 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -753,6 +753,138 @@ gpi_dma0: dma-controller@4a00000 {
 			status = "disabled";
 		};
 
+		qupv3_id_0: geniqup@4ac0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x04ac0000 0x2000>;
+			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+			clock-names = "m-ahb", "s-ahb";
+			iommus = <&apps_smmu 0x123 0x0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			status = "disabled";
+
+			i2c0: i2c@4a80000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x04a80000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_i2c0_default>;
+				pinctrl-1 = <&qup_i2c0_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi0: spi@4a80000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x04a80000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi0_default>;
+				pinctrl-1 = <&qup_spi0_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@4a84000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x04a84000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_i2c1_default>;
+				pinctrl-1 = <&qup_i2c1_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@4a88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x04a88000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_i2c2_default>;
+				pinctrl-1 = <&qup_i2c2_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi2: spi@4a88000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x04a88000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi2_default>;
+				pinctrl-1 = <&qup_spi2_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@4a8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x04a8c000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_i2c3_default>;
+				pinctrl-1 = <&qup_i2c3_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@4a90000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x04a90000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_i2c4_default>;
+				pinctrl-1 = <&qup_i2c4_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+		};
+
 		gpi_dma1: dma-controller@4c00000 {
 			compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
 			reg = <0x04c00000 0x60000>;
@@ -771,6 +903,172 @@ gpi_dma1: dma-controller@4c00000 {
 			status = "disabled";
 		};
 
+		qupv3_id_1: geniqup@4cc0000 {
+			compatible = "qcom,geni-se-qup";
+			reg = <0x04cc0000 0x2000>;
+			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+			clock-names = "m-ahb", "s-ahb";
+			iommus = <&apps_smmu 0x143 0x0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			status = "disabled";
+
+			i2c5: i2c@4c80000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x04c80000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_i2c5_default>;
+				pinctrl-1 = <&qup_i2c5_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi5: spi@4c80000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x04c80000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi5_default>;
+				pinctrl-1 = <&qup_spi5_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c6: i2c@4c84000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x04c84000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_i2c6_default>;
+				pinctrl-1 = <&qup_i2c6_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi6: spi@4c84000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x04c84000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi6_default>;
+				pinctrl-1 = <&qup_spi6_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c7: i2c@4c88000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x04c88000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_i2c7_default>;
+				pinctrl-1 = <&qup_i2c7_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c8: i2c@4c8c000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x04c8c000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_i2c8_default>;
+				pinctrl-1 = <&qup_i2c8_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi8: spi@4c8c000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x04c8c000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi8_default>;
+				pinctrl-1 = <&qup_spi8_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			i2c9: i2c@4c90000 {
+				compatible = "qcom,geni-i2c";
+				reg = <0x04c90000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_i2c9_default>;
+				pinctrl-1 = <&qup_i2c9_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
+				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi9: spi@4c90000 {
+				compatible = "qcom,geni-spi";
+				reg = <0x04c90000 0x4000>;
+				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+				clock-names = "se";
+				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-0 = <&qup_spi9_default>;
+				pinctrl-1 = <&qup_spi9_sleep>;
+				pinctrl-names = "default", "sleep";
+				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
+				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
+				dma-names = "tx", "rx";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+		};
+
 		usb3: usb@4ef8800 {
 			compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
 			reg = <0x04ef8800 0x400>;
-- 
2.39.0

[PATCH v2 3/3] arm64: dts: qcom: sm6125-seine: Enable GPI DMA 0, QUP 0 and I2C SEs

[Marijn Suijten]

Enable I2C Serial Engines 1, 2 and 3 which are known to have hardware
connected to them, leaving the rest disabled to save on power.  For
this, only GPI DMA 0 and QUP 0 need to be enabled, as nothing seems to
be connected to Serial Engines on GPU DMA 1 / QUP 1.  Beyond this
downstream only defines a UART console available on Serial Engine 4
which also resides on QUP 0.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
---
 .../qcom/sm6125-sony-xperia-seine-pdx201.dts  | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
index 1b9e40d3d269..b1de85d8f1c8 100644
--- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
+++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
@@ -141,10 +141,35 @@ active-config0 {
 	};
 };
 
+&gpi_dma0 {
+	status = "okay";
+};
+
 &hsusb_phy1 {
 	status = "okay";
 };
 
+&i2c1 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	/* NXP PN553 NFC @ 28 */
+};
+
+&i2c2 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	/* Samsung touchscreen @ 48 */
+};
+
+&i2c3 {
+	clock-frequency = <1000000>;
+	status = "okay";
+
+	/* Cirrus Logic CS35L41 boosted audio amplifier @ 40 */
+};
+
 &pm6125_adc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>;
@@ -246,6 +271,10 @@ &pon_resin {
 	linux,code = <KEY_VOLUMEUP>;
 };
 
+&qupv3_id_0 {
+	status = "okay";
+};
+
 &sdc2_off_state {
 	sd-cd-pins {
 		pins = "gpio98";
-- 
2.39.0

Re: [PATCH v2 2/3] arm64: dts: qcom: sm6125: Add QUPs with SPI and I2C Serial Engines

[Konrad Dybcio]

On 17.12.2022 00:34, Marijn Suijten wrote:
> Add Qualcomm Universal Peripheral nodes with SPI and I2C Serial Engines.
> QUP 0 only has two SPIs at index 0 and 2, QUP 1 has four SPIs with a gap
> in the middle (ranging from 5-9 with SPI 7 missing).  Both QUPs have 5
> I2C Serial Engines.
> 
> Signed-off-by: Martin Botka <martin.botka@somainline.org>
> [Marijn: Add iommus, reword patch description, reorder all properties,
>  sort based on address, use QCOM_GPI_ constants, drop dma cells from 5
>  to 3]
> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
Modulo the comment about 0x0/0 in iommus= (let's hear what
others think):

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm64/boot/dts/qcom/sm6125.dtsi | 298 +++++++++++++++++++++++++++
>  1 file changed, 298 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index 5fc304b2da63..36ba74b5ad89 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -753,6 +753,138 @@ gpi_dma0: dma-controller@4a00000 {
>  			status = "disabled";
>  		};
>  
> +		qupv3_id_0: geniqup@4ac0000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0x04ac0000 0x2000>;
> +			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> +				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> +			clock-names = "m-ahb", "s-ahb";
> +			iommus = <&apps_smmu 0x123 0x0>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			status = "disabled";
> +
> +			i2c0: i2c@4a80000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04a80000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c0_default>;
> +				pinctrl-1 = <&qup_i2c0_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
> +				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			spi0: spi@4a80000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x04a80000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_spi0_default>;
> +				pinctrl-1 = <&qup_spi0_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
> +				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c1: i2c@4a84000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04a84000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c1_default>;
> +				pinctrl-1 = <&qup_i2c1_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
> +				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c2: i2c@4a88000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04a88000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c2_default>;
> +				pinctrl-1 = <&qup_i2c2_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
> +				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			spi2: spi@4a88000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x04a88000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_spi2_default>;
> +				pinctrl-1 = <&qup_spi2_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
> +				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c3: i2c@4a8c000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04a8c000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c3_default>;
> +				pinctrl-1 = <&qup_i2c3_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
> +				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c4: i2c@4a90000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04a90000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c4_default>;
> +				pinctrl-1 = <&qup_i2c4_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
> +				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +		};
> +
>  		gpi_dma1: dma-controller@4c00000 {
>  			compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
>  			reg = <0x04c00000 0x60000>;
> @@ -771,6 +903,172 @@ gpi_dma1: dma-controller@4c00000 {
>  			status = "disabled";
>  		};
>  
> +		qupv3_id_1: geniqup@4cc0000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0x04cc0000 0x2000>;
> +			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> +				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> +			clock-names = "m-ahb", "s-ahb";
> +			iommus = <&apps_smmu 0x143 0x0>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			status = "disabled";
> +
> +			i2c5: i2c@4c80000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04c80000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c5_default>;
> +				pinctrl-1 = <&qup_i2c5_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
> +				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			spi5: spi@4c80000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x04c80000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_spi5_default>;
> +				pinctrl-1 = <&qup_spi5_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
> +				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c6: i2c@4c84000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04c84000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c6_default>;
> +				pinctrl-1 = <&qup_i2c6_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
> +				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			spi6: spi@4c84000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x04c84000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_spi6_default>;
> +				pinctrl-1 = <&qup_spi6_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
> +				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c7: i2c@4c88000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04c88000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c7_default>;
> +				pinctrl-1 = <&qup_i2c7_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
> +				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c8: i2c@4c8c000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04c8c000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c8_default>;
> +				pinctrl-1 = <&qup_i2c8_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
> +				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			spi8: spi@4c8c000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x04c8c000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_spi8_default>;
> +				pinctrl-1 = <&qup_spi8_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
> +				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c9: i2c@4c90000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04c90000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c9_default>;
> +				pinctrl-1 = <&qup_i2c9_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
> +				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			spi9: spi@4c90000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x04c90000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_spi9_default>;
> +				pinctrl-1 = <&qup_spi9_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
> +				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +		};
> +
>  		usb3: usb@4ef8800 {
>  			compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
>  			reg = <0x04ef8800 0x400>;

Re: [PATCH v2 3/3] arm64: dts: qcom: sm6125-seine: Enable GPI DMA 0, QUP 0 and I2C SEs

[Konrad Dybcio]

On 17.12.2022 00:34, Marijn Suijten wrote:
> Enable I2C Serial Engines 1, 2 and 3 which are known to have hardware
> connected to them, leaving the rest disabled to save on power.  For
> this, only GPI DMA 0 and QUP 0 need to be enabled, as nothing seems to
> be connected to Serial Engines on GPU DMA 1 / QUP 1.  Beyond this
> downstream only defines a UART console available on Serial Engine 4
> which also resides on QUP 0.
> 
> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  .../qcom/sm6125-sony-xperia-seine-pdx201.dts  | 29 +++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
> index 1b9e40d3d269..b1de85d8f1c8 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
> +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
> @@ -141,10 +141,35 @@ active-config0 {
>  	};
>  };
>  
> +&gpi_dma0 {
> +	status = "okay";
> +};
> +
>  &hsusb_phy1 {
>  	status = "okay";
>  };
>  
> +&i2c1 {
> +	clock-frequency = <400000>;
> +	status = "okay";
> +
> +	/* NXP PN553 NFC @ 28 */
> +};
> +
> +&i2c2 {
> +	clock-frequency = <400000>;
> +	status = "okay";
> +
> +	/* Samsung touchscreen @ 48 */
> +};
> +
> +&i2c3 {
> +	clock-frequency = <1000000>;
> +	status = "okay";
> +
> +	/* Cirrus Logic CS35L41 boosted audio amplifier @ 40 */
> +};
> +
>  &pm6125_adc {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>;
> @@ -246,6 +271,10 @@ &pon_resin {
>  	linux,code = <KEY_VOLUMEUP>;
>  };
>  
> +&qupv3_id_0 {
> +	status = "okay";
> +};
> +
>  &sdc2_off_state {
>  	sd-cd-pins {
>  		pins = "gpio98";

Re: [PATCH v2 2/3] arm64: dts: qcom: sm6125: Add QUPs with SPI and I2C Serial Engines

[Marijn Suijten]

On 2022-12-17 16:19:21, Konrad Dybcio wrote:
> 
> 
> On 17.12.2022 00:34, Marijn Suijten wrote:
> > Add Qualcomm Universal Peripheral nodes with SPI and I2C Serial Engines.
> > QUP 0 only has two SPIs at index 0 and 2, QUP 1 has four SPIs with a gap
> > in the middle (ranging from 5-9 with SPI 7 missing).  Both QUPs have 5
> > I2C Serial Engines.
> > 
> > Signed-off-by: Martin Botka <martin.botka@somainline.org>
> > [Marijn: Add iommus, reword patch description, reorder all properties,
> >  sort based on address, use QCOM_GPI_ constants, drop dma cells from 5
> >  to 3]
> > Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
> > ---
> Modulo the comment about 0x0/0 in iommus= (let's hear what
> others think):

The vast majority of qcom DTS - and the majority of iommus=<> in sm6125
- uses 0x0, so we'll stick with that.  I'll fix and resend an earlier
patch series that wrongly uses decimal 0.

> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> 
> Konrad
> >  arch/arm64/boot/dts/qcom/sm6125.dtsi | 298 +++++++++++++++++++++++++++
> >  1 file changed, 298 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > index 5fc304b2da63..36ba74b5ad89 100644
> > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > @@ -753,6 +753,138 @@ gpi_dma0: dma-controller@4a00000 {
> >  			status = "disabled";
> >  		};
> >  
> > +		qupv3_id_0: geniqup@4ac0000 {
> > +			compatible = "qcom,geni-se-qup";
> > +			reg = <0x04ac0000 0x2000>;
> > +			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> > +				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> > +			clock-names = "m-ahb", "s-ahb";
> > +			iommus = <&apps_smmu 0x123 0x0>;
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			ranges;
> > +			status = "disabled";
> > +
> > +			i2c0: i2c@4a80000 {
> > +				compatible = "qcom,geni-i2c";
> > +				reg = <0x04a80000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_i2c0_default>;
> > +				pinctrl-1 = <&qup_i2c0_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
> > +				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			spi0: spi@4a80000 {
> > +				compatible = "qcom,geni-spi";
> > +				reg = <0x04a80000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_spi0_default>;
> > +				pinctrl-1 = <&qup_spi0_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
> > +				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			i2c1: i2c@4a84000 {
> > +				compatible = "qcom,geni-i2c";
> > +				reg = <0x04a84000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_i2c1_default>;
> > +				pinctrl-1 = <&qup_i2c1_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
> > +				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			i2c2: i2c@4a88000 {
> > +				compatible = "qcom,geni-i2c";
> > +				reg = <0x04a88000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_i2c2_default>;
> > +				pinctrl-1 = <&qup_i2c2_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
> > +				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			spi2: spi@4a88000 {
> > +				compatible = "qcom,geni-spi";
> > +				reg = <0x04a88000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_spi2_default>;
> > +				pinctrl-1 = <&qup_spi2_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
> > +				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			i2c3: i2c@4a8c000 {
> > +				compatible = "qcom,geni-i2c";
> > +				reg = <0x04a8c000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_i2c3_default>;
> > +				pinctrl-1 = <&qup_i2c3_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
> > +				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			i2c4: i2c@4a90000 {
> > +				compatible = "qcom,geni-i2c";
> > +				reg = <0x04a90000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_i2c4_default>;
> > +				pinctrl-1 = <&qup_i2c4_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
> > +				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +		};
> > +
> >  		gpi_dma1: dma-controller@4c00000 {
> >  			compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
> >  			reg = <0x04c00000 0x60000>;
> > @@ -771,6 +903,172 @@ gpi_dma1: dma-controller@4c00000 {
> >  			status = "disabled";
> >  		};
> >  
> > +		qupv3_id_1: geniqup@4cc0000 {
> > +			compatible = "qcom,geni-se-qup";
> > +			reg = <0x04cc0000 0x2000>;
> > +			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> > +				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> > +			clock-names = "m-ahb", "s-ahb";
> > +			iommus = <&apps_smmu 0x143 0x0>;
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			ranges;
> > +			status = "disabled";
> > +
> > +			i2c5: i2c@4c80000 {
> > +				compatible = "qcom,geni-i2c";
> > +				reg = <0x04c80000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_i2c5_default>;
> > +				pinctrl-1 = <&qup_i2c5_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
> > +				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			spi5: spi@4c80000 {
> > +				compatible = "qcom,geni-spi";
> > +				reg = <0x04c80000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_spi5_default>;
> > +				pinctrl-1 = <&qup_spi5_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
> > +				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			i2c6: i2c@4c84000 {
> > +				compatible = "qcom,geni-i2c";
> > +				reg = <0x04c84000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_i2c6_default>;
> > +				pinctrl-1 = <&qup_i2c6_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
> > +				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			spi6: spi@4c84000 {
> > +				compatible = "qcom,geni-spi";
> > +				reg = <0x04c84000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_spi6_default>;
> > +				pinctrl-1 = <&qup_spi6_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
> > +				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			i2c7: i2c@4c88000 {
> > +				compatible = "qcom,geni-i2c";
> > +				reg = <0x04c88000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_i2c7_default>;
> > +				pinctrl-1 = <&qup_i2c7_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
> > +				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			i2c8: i2c@4c8c000 {
> > +				compatible = "qcom,geni-i2c";
> > +				reg = <0x04c8c000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_i2c8_default>;
> > +				pinctrl-1 = <&qup_i2c8_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
> > +				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			spi8: spi@4c8c000 {
> > +				compatible = "qcom,geni-spi";
> > +				reg = <0x04c8c000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_spi8_default>;
> > +				pinctrl-1 = <&qup_spi8_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
> > +				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			i2c9: i2c@4c90000 {
> > +				compatible = "qcom,geni-i2c";
> > +				reg = <0x04c90000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_i2c9_default>;
> > +				pinctrl-1 = <&qup_i2c9_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
> > +				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +
> > +			spi9: spi@4c90000 {
> > +				compatible = "qcom,geni-spi";
> > +				reg = <0x04c90000 0x4000>;
> > +				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> > +				clock-names = "se";
> > +				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
> > +				pinctrl-0 = <&qup_spi9_default>;
> > +				pinctrl-1 = <&qup_spi9_sleep>;
> > +				pinctrl-names = "default", "sleep";
> > +				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
> > +				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
> > +				dma-names = "tx", "rx";
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +				status = "disabled";
> > +			};
> > +		};
> > +
> >  		usb3: usb@4ef8800 {
> >  			compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
> >  			reg = <0x04ef8800 0x400>;

Re: [PATCH v2 2/3] arm64: dts: qcom: sm6125: Add QUPs with SPI and I2C Serial Engines

[Martin Botka]

On Sat, Dec 17 2022 at 12:34:07 AM +01:00:00, Marijn Suijten 
<marijn.suijten@somainline.org> wrote:
> Add Qualcomm Universal Peripheral nodes with SPI and I2C Serial 
> Engines.
> QUP 0 only has two SPIs at index 0 and 2, QUP 1 has four SPIs with a 
> gap
> in the middle (ranging from 5-9 with SPI 7 missing).  Both QUPs have 5
> I2C Serial Engines.
> 
> Signed-off-by: Martin Botka <martin.botka@somainline.org>
> [Marijn: Add iommus, reword patch description, reorder all properties,
>  sort based on address, use QCOM_GPI_ constants, drop dma cells from 5
>  to 3]
> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
>  arch/arm64/boot/dts/qcom/sm6125.dtsi | 298 
> +++++++++++++++++++++++++++
>  1 file changed, 298 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi 
> b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index 5fc304b2da63..36ba74b5ad89 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -753,6 +753,138 @@ gpi_dma0: dma-controller@4a00000 {
>  			status = "disabled";
>  		};
> 
> +		qupv3_id_0: geniqup@4ac0000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0x04ac0000 0x2000>;
> +			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> +				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> +			clock-names = "m-ahb", "s-ahb";
> +			iommus = <&apps_smmu 0x123 0x0>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			status = "disabled";
> +
> +			i2c0: i2c@4a80000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04a80000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c0_default>;
> +				pinctrl-1 = <&qup_i2c0_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
> +				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			spi0: spi@4a80000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x04a80000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_spi0_default>;
> +				pinctrl-1 = <&qup_spi0_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
> +				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c1: i2c@4a84000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04a84000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c1_default>;
> +				pinctrl-1 = <&qup_i2c1_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
> +				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c2: i2c@4a88000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04a88000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c2_default>;
> +				pinctrl-1 = <&qup_i2c2_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
> +				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			spi2: spi@4a88000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x04a88000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_spi2_default>;
> +				pinctrl-1 = <&qup_spi2_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
> +				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c3: i2c@4a8c000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04a8c000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c3_default>;
> +				pinctrl-1 = <&qup_i2c3_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
> +				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c4: i2c@4a90000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04a90000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c4_default>;
> +				pinctrl-1 = <&qup_i2c4_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
> +				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +		};
> +
>  		gpi_dma1: dma-controller@4c00000 {
>  			compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma";
>  			reg = <0x04c00000 0x60000>;
> @@ -771,6 +903,172 @@ gpi_dma1: dma-controller@4c00000 {
>  			status = "disabled";
>  		};
> 
> +		qupv3_id_1: geniqup@4cc0000 {
> +			compatible = "qcom,geni-se-qup";
> +			reg = <0x04cc0000 0x2000>;
> +			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> +				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> +			clock-names = "m-ahb", "s-ahb";
> +			iommus = <&apps_smmu 0x143 0x0>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			status = "disabled";
> +
> +			i2c5: i2c@4c80000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04c80000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c5_default>;
> +				pinctrl-1 = <&qup_i2c5_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
> +				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			spi5: spi@4c80000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x04c80000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_spi5_default>;
> +				pinctrl-1 = <&qup_spi5_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
> +				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c6: i2c@4c84000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04c84000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c6_default>;
> +				pinctrl-1 = <&qup_i2c6_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
> +				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			spi6: spi@4c84000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x04c84000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_spi6_default>;
> +				pinctrl-1 = <&qup_spi6_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
> +				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c7: i2c@4c88000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04c88000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c7_default>;
> +				pinctrl-1 = <&qup_i2c7_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
> +				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c8: i2c@4c8c000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04c8c000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c8_default>;
> +				pinctrl-1 = <&qup_i2c8_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
> +				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			spi8: spi@4c8c000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x04c8c000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_spi8_default>;
> +				pinctrl-1 = <&qup_spi8_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
> +				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c9: i2c@4c90000 {
> +				compatible = "qcom,geni-i2c";
> +				reg = <0x04c90000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_i2c9_default>;
> +				pinctrl-1 = <&qup_i2c9_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
> +				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			spi9: spi@4c90000 {
> +				compatible = "qcom,geni-spi";
> +				reg = <0x04c90000 0x4000>;
> +				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> +				clock-names = "se";
> +				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
> +				pinctrl-0 = <&qup_spi9_default>;
> +				pinctrl-1 = <&qup_spi9_sleep>;
> +				pinctrl-names = "default", "sleep";
> +				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
> +				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
> +				dma-names = "tx", "rx";
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +		};
> +
>  		usb3: usb@4ef8800 {
>  			compatible = "qcom,sm6125-dwc3", "qcom,dwc3";
>  			reg = <0x04ef8800 0x400>;
> --
> 2.39.0
> 
Reviewed-by: Martin Botka <martin.botka@somainline.org>

-Martin

Re: [PATCH v2 3/3] arm64: dts: qcom: sm6125-seine: Enable GPI DMA 0, QUP 0 and I2C SEs

[Martin Botka]

On Sat, Dec 17 2022 at 12:34:08 AM +01:00:00, Marijn Suijten 
<marijn.suijten@somainline.org> wrote:
> Enable I2C Serial Engines 1, 2 and 3 which are known to have hardware
> connected to them, leaving the rest disabled to save on power.  For
> this, only GPI DMA 0 and QUP 0 need to be enabled, as nothing seems to
> be connected to Serial Engines on GPU DMA 1 / QUP 1.  Beyond this
> downstream only defines a UART console available on Serial Engine 4
> which also resides on QUP 0.
> 
> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
> ---
>  .../qcom/sm6125-sony-xperia-seine-pdx201.dts  | 29 
> +++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git 
> a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts 
> b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
> index 1b9e40d3d269..b1de85d8f1c8 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
> +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts
> @@ -141,10 +141,35 @@ active-config0 {
>  	};
>  };
> 
> +&gpi_dma0 {
> +	status = "okay";
> +};
> +
>  &hsusb_phy1 {
>  	status = "okay";
>  };
> 
> +&i2c1 {
> +	clock-frequency = <400000>;
> +	status = "okay";
> +
> +	/* NXP PN553 NFC @ 28 */
> +};
> +
> +&i2c2 {
> +	clock-frequency = <400000>;
> +	status = "okay";
> +
> +	/* Samsung touchscreen @ 48 */
> +};
> +
> +&i2c3 {
> +	clock-frequency = <1000000>;
> +	status = "okay";
> +
> +	/* Cirrus Logic CS35L41 boosted audio amplifier @ 40 */
> +};
> +
>  &pm6125_adc {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>;
> @@ -246,6 +271,10 @@ &pon_resin {
>  	linux,code = <KEY_VOLUMEUP>;
>  };
> 
> +&qupv3_id_0 {
> +	status = "okay";
> +};
> +
>  &sdc2_off_state {
>  	sd-cd-pins {
>  		pins = "gpio98";
> --
> 2.39.0
> 
Reviewed-by: Martin Botka <martin.botka@somainline.org>

-Martin

Re: [PATCH v2 0/3] arm64: dts: qcom: sm6125: QUPs, SPI and Seine I2C buses

[Bjorn Andersson]

On Sat, Dec 17, 2022 at 12:34:05AM +0100, Marijn Suijten wrote:
> Introduce Qualcomm Universal Peripheral support on SM6125 and define all
> known SPI and I2C Serial Engines.  On Sony Seine PDX201 all I2C buses
> with known-connected hardware are enabled for future hardware mapping,
> together with the respective GPI DMA 0 and QUP 0.
> 
> Changes since v1:
> - Un-downstream pinctrl mapping:
>   - Remove nested mux {} / config {};
>   - Remove useless comments;
>   - Remove unreferenced pinctrl states;
> - Use qup14 pinctrl function name instead of unknown qup_14;
> - Reword commit message;
> - Add iommus to QUP nodes now that this series depends on apps_smmu to
>   be available;
> - Reorder all properties to match other SoCs;
> - Reorder/intersperse QUP nodes with GPI DMA nodes to maintain sorting
>   by address;
> - Reorder SPI nodes to fit in with I2C nodes, restoring sorting by
>   address too;
> - Use QCOM_GPI_* constants;
> - Adhere to 3 instead of 5 dma cells for gpi_dma.
> 
> v1: https://lore.kernel.org/all/20221001185628.494884-1-martin.botka@somainline.org/T/#u
> 
> Depends on:
> - SM6125 APPS SMMU: https://lore.kernel.org/linux-arm-msm/20221216215819.1164973-1-marijn.suijten@somainline.org/T/#u
> - SM6125 GPI DMA: https://lore.kernel.org/linux-arm-msm/20221216231528.1268447-1-marijn.suijten@somainline.org/T/#u

Please, in the future, when you have dependencies between your dts
patches, send them together so I don't need to go on a treasure hunt in
my mailbox to figure out which order to apply things...

Regards,
Bjorn

> 
> Marijn Suijten (2):
>   arm64: dts: qcom: sm6125: Add QUPs with SPI and I2C Serial Engines
>   arm64: dts: qcom: sm6125-seine: Enable GPI DMA 0, QUP 0 and I2C SEs
> 
> Martin Botka (1):
>   arm64: dts: qcom: sm6125: Add pin configs for QUP SPI/I2C Serial
>     Engines
> 
>  .../qcom/sm6125-sony-xperia-seine-pdx201.dts  |  29 +
>  arch/arm64/boot/dts/qcom/sm6125.dtsi          | 522 ++++++++++++++++++
>  2 files changed, 551 insertions(+)
> 
> --
> 2.39.0
> 

Re: [PATCH v2 0/3] arm64: dts: qcom: sm6125: QUPs, SPI and Seine I2C buses

[Marijn Suijten]

On 2022-12-29 11:13:01, Bjorn Andersson wrote:
> On Sat, Dec 17, 2022 at 12:34:05AM +0100, Marijn Suijten wrote:
> > Introduce Qualcomm Universal Peripheral support on SM6125 and define all
> > known SPI and I2C Serial Engines.  On Sony Seine PDX201 all I2C buses
> > with known-connected hardware are enabled for future hardware mapping,
> > together with the respective GPI DMA 0 and QUP 0.
> > 
> > Changes since v1:
> > - Un-downstream pinctrl mapping:
> >   - Remove nested mux {} / config {};
> >   - Remove useless comments;
> >   - Remove unreferenced pinctrl states;
> > - Use qup14 pinctrl function name instead of unknown qup_14;
> > - Reword commit message;
> > - Add iommus to QUP nodes now that this series depends on apps_smmu to
> >   be available;
> > - Reorder all properties to match other SoCs;
> > - Reorder/intersperse QUP nodes with GPI DMA nodes to maintain sorting
> >   by address;
> > - Reorder SPI nodes to fit in with I2C nodes, restoring sorting by
> >   address too;
> > - Use QCOM_GPI_* constants;
> > - Adhere to 3 instead of 5 dma cells for gpi_dma.
> > 
> > v1: https://lore.kernel.org/all/20221001185628.494884-1-martin.botka@somainline.org/T/#u
> > 
> > Depends on:
> > - SM6125 APPS SMMU: https://lore.kernel.org/linux-arm-msm/20221216215819.1164973-1-marijn.suijten@somainline.org/T/#u
> > - SM6125 GPI DMA: https://lore.kernel.org/linux-arm-msm/20221216231528.1268447-1-marijn.suijten@somainline.org/T/#u
> 
> Please, in the future, when you have dependencies between your dts
> patches, send them together so I don't need to go on a treasure hunt in
> my mailbox to figure out which order to apply things...

I was quite confident separating out "unrelated" patches in separate
series was preferred, especially when dependencies are marked explicitly
like this... what changed?

(Aside that, would I then call this a v4+v2+v2?)

- Marijn

Re: [PATCH v2 0/3] arm64: dts: qcom: sm6125: QUPs, SPI and Seine I2C buses

[Bjorn Andersson]

On Sat, 17 Dec 2022 00:34:05 +0100, Marijn Suijten wrote:
> Introduce Qualcomm Universal Peripheral support on SM6125 and define all
> known SPI and I2C Serial Engines.  On Sony Seine PDX201 all I2C buses
> with known-connected hardware are enabled for future hardware mapping,
> together with the respective GPI DMA 0 and QUP 0.
> 
> Changes since v1:
> - Un-downstream pinctrl mapping:
>   - Remove nested mux {} / config {};
>   - Remove useless comments;
>   - Remove unreferenced pinctrl states;
> - Use qup14 pinctrl function name instead of unknown qup_14;
> - Reword commit message;
> - Add iommus to QUP nodes now that this series depends on apps_smmu to
>   be available;
> - Reorder all properties to match other SoCs;
> - Reorder/intersperse QUP nodes with GPI DMA nodes to maintain sorting
>   by address;
> - Reorder SPI nodes to fit in with I2C nodes, restoring sorting by
>   address too;
> - Use QCOM_GPI_* constants;
> - Adhere to 3 instead of 5 dma cells for gpi_dma.
> 
> [...]

Applied, thanks!

[1/3] arm64: dts: qcom: sm6125: Add pin configs for QUP SPI/I2C Serial Engines
      commit: 075a6aef55919b9ed99cf07fe149aa52f80d9056
[2/3] arm64: dts: qcom: sm6125: Add QUPs with SPI and I2C Serial Engines
      commit: 72621d0443eaf4e70adcbcd801301b9dd6eed431
[3/3] arm64: dts: qcom: sm6125-seine: Enable GPI DMA 0, QUP 0 and I2C SEs
      commit: f3b770f7a8b439136c71c24dbfc408a0086c6326

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: [PATCH v2 0/3] arm64: dts: qcom: sm6125: QUPs, SPI and Seine I2C buses

[Marijn Suijten]

On 2022-12-29 18:21:55, Marijn Suijten wrote:
> On 2022-12-29 11:13:01, Bjorn Andersson wrote:
> > On Sat, Dec 17, 2022 at 12:34:05AM +0100, Marijn Suijten wrote:
> > > Introduce Qualcomm Universal Peripheral support on SM6125 and define all
> > > known SPI and I2C Serial Engines.  On Sony Seine PDX201 all I2C buses
> > > with known-connected hardware are enabled for future hardware mapping,
> > > together with the respective GPI DMA 0 and QUP 0.
> > > 
> > > Changes since v1:
> > > - Un-downstream pinctrl mapping:
> > >   - Remove nested mux {} / config {};
> > >   - Remove useless comments;
> > >   - Remove unreferenced pinctrl states;
> > > - Use qup14 pinctrl function name instead of unknown qup_14;
> > > - Reword commit message;
> > > - Add iommus to QUP nodes now that this series depends on apps_smmu to
> > >   be available;
> > > - Reorder all properties to match other SoCs;
> > > - Reorder/intersperse QUP nodes with GPI DMA nodes to maintain sorting
> > >   by address;
> > > - Reorder SPI nodes to fit in with I2C nodes, restoring sorting by
> > >   address too;
> > > - Use QCOM_GPI_* constants;
> > > - Adhere to 3 instead of 5 dma cells for gpi_dma.
> > > 
> > > v1: https://lore.kernel.org/all/20221001185628.494884-1-martin.botka@somainline.org/T/#u
> > > 
> > > Depends on:
> > > - SM6125 APPS SMMU: https://lore.kernel.org/linux-arm-msm/20221216215819.1164973-1-marijn.suijten@somainline.org/T/#u
> > > - SM6125 GPI DMA: https://lore.kernel.org/linux-arm-msm/20221216231528.1268447-1-marijn.suijten@somainline.org/T/#u
> > 
> > Please, in the future, when you have dependencies between your dts
> > patches, send them together so I don't need to go on a treasure hunt in
> > my mailbox to figure out which order to apply things...
> 
> I was quite confident separating out "unrelated" patches in separate
> series was preferred, especially when dependencies are marked explicitly
> like this... what changed?

Perhaps because both dependencies have been resent, and the links for
APPS SMMU v4 and GPI DMA v2 have become obsolete in favour of:

- SM6125 APPS SMMU v5: https://lore.kernel.org/linux-arm-msm/20221222193254.126925-1-marijn.suijten@somainline.org/T/#u
- SM6125 GPI DMA v3: https://lore.kernel.org/linux-arm-msm/20221222194600.139854-1-marijn.suijten@somainline.org/T/#u

- Marijn