* [PATCH 1/3] dt-bindings: phy: qcom,pcie2-phy: convert to YAML format
@ 2022-12-16 23:40 ` Dmitry Baryshkov
0 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-12-16 23:40 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree
Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format
from the text description.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../bindings/phy/qcom,pcie2-phy.yaml | 87 +++++++++++++++++++
.../bindings/phy/qcom-pcie2-phy.txt | 42 ---------
2 files changed, 87 insertions(+), 42 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
new file mode 100644
index 000000000000..497850a5b428
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm PCIe2 PHY controller
+
+maintainers:
+ - Vinod Koul <vkoul@kernel.org>
+
+description:
+ The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
+ platforms.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,qcs404-pcie2-phy
+ - const: qcom,pcie2-phy
+
+ reg:
+ items:
+ - description: PHY register set
+
+ clocks:
+ items:
+ - description: a clock-specifier pair for the "pipe" clock
+
+ "#phy-cells":
+ const: 0
+
+ vdda-vp-supply:
+ description: phandle to low voltage regulator
+
+ vdda-vph-supply:
+ description: phandle to high voltage regulator
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: phy
+ - const: pipe
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - vdda-vp-supply
+ - vdda-vph-supply
+ - resets
+ - reset-names
+ - clock-output-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-qcs404.h>
+ phy@7786000 {
+ compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
+ reg = <0x07786000 0xb8>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
+ <&gcc GCC_PCIE_0_PIPE_ARES>;
+ reset-names = "phy", "pipe";
+
+ vdda-vp-supply = <&vreg_l3_1p05>;
+ vdda-vph-supply = <&vreg_l5_1p8>;
+
+ clock-output-names = "pcie_0_pipe_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+...
+
diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
deleted file mode 100644
index 30064253f290..000000000000
--- a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Qualcomm PCIe2 PHY controller
-=============================
-
-The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
-platforms.
-
-Required properties:
- - compatible: compatible list, should be:
- "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
-
- - reg: offset and length of the PHY register set.
- - #phy-cells: must be 0.
-
- - clocks: a clock-specifier pair for the "pipe" clock
-
- - vdda-vp-supply: phandle to low voltage regulator
- - vdda-vph-supply: phandle to high voltage regulator
-
- - resets: reset-specifier pairs for the "phy" and "pipe" resets
- - reset-names: list of resets, should contain:
- "phy" and "pipe"
-
- - clock-output-names: name of the outgoing clock signal from the PHY PLL
- - #clock-cells: must be 0
-
-Example:
- phy@7786000 {
- compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
- reg = <0x07786000 0xb8>;
-
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
- <&gcc GCC_PCIE_0_PIPE_ARES>;
- reset-names = "phy", "pipe";
-
- vdda-vp-supply = <&vreg_l3_1p05>;
- vdda-vph-supply = <&vreg_l5_1p8>;
-
- clock-output-names = "pcie_0_pipe_clk";
- #clock-cells = <0>;
- #phy-cells = <0>;
- };
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 1/3] dt-bindings: phy: qcom,pcie2-phy: convert to YAML format
@ 2022-12-16 23:40 ` Dmitry Baryshkov
0 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-12-16 23:40 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree
Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format
from the text description.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../bindings/phy/qcom,pcie2-phy.yaml | 87 +++++++++++++++++++
.../bindings/phy/qcom-pcie2-phy.txt | 42 ---------
2 files changed, 87 insertions(+), 42 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
new file mode 100644
index 000000000000..497850a5b428
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm PCIe2 PHY controller
+
+maintainers:
+ - Vinod Koul <vkoul@kernel.org>
+
+description:
+ The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
+ platforms.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,qcs404-pcie2-phy
+ - const: qcom,pcie2-phy
+
+ reg:
+ items:
+ - description: PHY register set
+
+ clocks:
+ items:
+ - description: a clock-specifier pair for the "pipe" clock
+
+ "#phy-cells":
+ const: 0
+
+ vdda-vp-supply:
+ description: phandle to low voltage regulator
+
+ vdda-vph-supply:
+ description: phandle to high voltage regulator
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: phy
+ - const: pipe
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - vdda-vp-supply
+ - vdda-vph-supply
+ - resets
+ - reset-names
+ - clock-output-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-qcs404.h>
+ phy@7786000 {
+ compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
+ reg = <0x07786000 0xb8>;
+
+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+ resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
+ <&gcc GCC_PCIE_0_PIPE_ARES>;
+ reset-names = "phy", "pipe";
+
+ vdda-vp-supply = <&vreg_l3_1p05>;
+ vdda-vph-supply = <&vreg_l5_1p8>;
+
+ clock-output-names = "pcie_0_pipe_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+...
+
diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
deleted file mode 100644
index 30064253f290..000000000000
--- a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Qualcomm PCIe2 PHY controller
-=============================
-
-The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
-platforms.
-
-Required properties:
- - compatible: compatible list, should be:
- "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
-
- - reg: offset and length of the PHY register set.
- - #phy-cells: must be 0.
-
- - clocks: a clock-specifier pair for the "pipe" clock
-
- - vdda-vp-supply: phandle to low voltage regulator
- - vdda-vph-supply: phandle to high voltage regulator
-
- - resets: reset-specifier pairs for the "phy" and "pipe" resets
- - reset-names: list of resets, should contain:
- "phy" and "pipe"
-
- - clock-output-names: name of the outgoing clock signal from the PHY PLL
- - #clock-cells: must be 0
-
-Example:
- phy@7786000 {
- compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
- reg = <0x07786000 0xb8>;
-
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
- <&gcc GCC_PCIE_0_PIPE_ARES>;
- reset-names = "phy", "pipe";
-
- vdda-vp-supply = <&vreg_l3_1p05>;
- vdda-vph-supply = <&vreg_l5_1p8>;
-
- clock-output-names = "pcie_0_pipe_clk";
- #clock-cells = <0>;
- #phy-cells = <0>;
- };
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/3] phy: qualcomm: pcie2: register as clock provider
2022-12-16 23:40 ` Dmitry Baryshkov
@ 2022-12-16 23:40 ` Dmitry Baryshkov
-1 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-12-16 23:40 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree
Register pcie2 PHY as a clock provider to enable using it in the
DT-based clock lookup.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-pcie2.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-pcie2.c b/drivers/phy/qualcomm/phy-qcom-pcie2.c
index 5407e59bb185..11a2bb958681 100644
--- a/drivers/phy/qualcomm/phy-qcom-pcie2.c
+++ b/drivers/phy/qualcomm/phy-qcom-pcie2.c
@@ -243,7 +243,11 @@ static int phy_pipe_clksrc_register(struct qcom_phy *qphy)
fixed->fixed_rate = 250000000;
fixed->hw.init = &init;
- return devm_clk_hw_register(qphy->dev, &fixed->hw);
+ ret = devm_clk_hw_register(qphy->dev, &fixed->hw);
+ if (ret < 0)
+ return ret;
+
+ return devm_of_clk_add_hw_provider(qphy->dev, of_clk_hw_simple_get, &fixed->hw);
}
static int qcom_pcie2_phy_probe(struct platform_device *pdev)
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/3] phy: qualcomm: pcie2: register as clock provider
@ 2022-12-16 23:40 ` Dmitry Baryshkov
0 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-12-16 23:40 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree
Register pcie2 PHY as a clock provider to enable using it in the
DT-based clock lookup.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-pcie2.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-pcie2.c b/drivers/phy/qualcomm/phy-qcom-pcie2.c
index 5407e59bb185..11a2bb958681 100644
--- a/drivers/phy/qualcomm/phy-qcom-pcie2.c
+++ b/drivers/phy/qualcomm/phy-qcom-pcie2.c
@@ -243,7 +243,11 @@ static int phy_pipe_clksrc_register(struct qcom_phy *qphy)
fixed->fixed_rate = 250000000;
fixed->hw.init = &init;
- return devm_clk_hw_register(qphy->dev, &fixed->hw);
+ ret = devm_clk_hw_register(qphy->dev, &fixed->hw);
+ if (ret < 0)
+ return ret;
+
+ return devm_of_clk_add_hw_provider(qphy->dev, of_clk_hw_simple_get, &fixed->hw);
}
static int qcom_pcie2_phy_probe(struct platform_device *pdev)
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: qcs404: register PCIe PHY as a clock provider
2022-12-16 23:40 ` Dmitry Baryshkov
@ 2022-12-16 23:40 ` Dmitry Baryshkov
-1 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-12-16 23:40 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree
Add #clock-cells to the pcie_phy node. It provides a PCIe PIPE clock.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index a5324eecb50a..ffffaa7507cf 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -810,6 +810,7 @@ pcie_phy: phy@7786000 {
reset-names = "phy", "pipe";
clock-output-names = "pcie_0_pipe_clk";
+ #clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
--
2.35.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: qcs404: register PCIe PHY as a clock provider
@ 2022-12-16 23:40 ` Dmitry Baryshkov
0 siblings, 0 replies; 14+ messages in thread
From: Dmitry Baryshkov @ 2022-12-16 23:40 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree
Add #clock-cells to the pcie_phy node. It provides a PCIe PIPE clock.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index a5324eecb50a..ffffaa7507cf 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -810,6 +810,7 @@ pcie_phy: phy@7786000 {
reset-names = "phy", "pipe";
clock-output-names = "pcie_0_pipe_clk";
+ #clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
--
2.35.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] arm64: dts: qcom: qcs404: register PCIe PHY as a clock provider
2022-12-16 23:40 ` Dmitry Baryshkov
@ 2022-12-17 15:01 ` Konrad Dybcio
-1 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2022-12-17 15:01 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree
On 17.12.2022 00:40, Dmitry Baryshkov wrote:
> Add #clock-cells to the pcie_phy node. It provides a PCIe PIPE clock.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index a5324eecb50a..ffffaa7507cf 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -810,6 +810,7 @@ pcie_phy: phy@7786000 {
> reset-names = "phy", "pipe";
>
> clock-output-names = "pcie_0_pipe_clk";
> + #clock-cells = <0>;
> #phy-cells = <0>;
>
> status = "disabled";
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] arm64: dts: qcom: qcs404: register PCIe PHY as a clock provider
@ 2022-12-17 15:01 ` Konrad Dybcio
0 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2022-12-17 15:01 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Vinod Koul,
Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree
On 17.12.2022 00:40, Dmitry Baryshkov wrote:
> Add #clock-cells to the pcie_phy node. It provides a PCIe PIPE clock.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index a5324eecb50a..ffffaa7507cf 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -810,6 +810,7 @@ pcie_phy: phy@7786000 {
> reset-names = "phy", "pipe";
>
> clock-output-names = "pcie_0_pipe_clk";
> + #clock-cells = <0>;
> #phy-cells = <0>;
>
> status = "disabled";
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] dt-bindings: phy: qcom,pcie2-phy: convert to YAML format
2022-12-16 23:40 ` Dmitry Baryshkov
@ 2022-12-19 9:16 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-19 9:16 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski
Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree
On 17/12/2022 00:40, Dmitry Baryshkov wrote:
> Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format
> from the text description.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../bindings/phy/qcom,pcie2-phy.yaml | 87 +++++++++++++++++++
> .../bindings/phy/qcom-pcie2-phy.txt | 42 ---------
> 2 files changed, 87 insertions(+), 42 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
> new file mode 100644
> index 000000000000..497850a5b428
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
> @@ -0,0 +1,87 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm PCIe2 PHY controller
> +
> +maintainers:
> + - Vinod Koul <vkoul@kernel.org>
> +
> +description:
> + The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
> + platforms.
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,qcs404-pcie2-phy
> + - const: qcom,pcie2-phy
> +
> + reg:
> + items:
> + - description: PHY register set
> +
> + clocks:
> + items:
> + - description: a clock-specifier pair for the "pipe" clock
> +
> + "#phy-cells":
> + const: 0
> +
> + vdda-vp-supply:
> + description: phandle to low voltage regulator
Drop "phandle to"
> +
> + vdda-vph-supply:
> + description: phandle to high voltage regulator
Drop "phandle to"
> +
> + resets:
> + maxItems: 2
> +
> + reset-names:
> + items:
> + - const: phy
> + - const: pipe
Blank line
> + "#clock-cells":
> + const: 0
> +
> + clock-output-names:
> + maxItems: 1
Maybe keep both next to "clocks"? And same order in "required:".
> +
> +required:
> + - compatible
> + - reg
> + - "#phy-cells"
> + - clocks
> + - vdda-vp-supply
> + - vdda-vph-supply
> + - resets
> + - reset-names
> + - clock-output-names
> + - "#clock-cells"
> +
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] dt-bindings: phy: qcom,pcie2-phy: convert to YAML format
@ 2022-12-19 9:16 ` Krzysztof Kozlowski
0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-19 9:16 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski
Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree
On 17/12/2022 00:40, Dmitry Baryshkov wrote:
> Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format
> from the text description.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> .../bindings/phy/qcom,pcie2-phy.yaml | 87 +++++++++++++++++++
> .../bindings/phy/qcom-pcie2-phy.txt | 42 ---------
> 2 files changed, 87 insertions(+), 42 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
> new file mode 100644
> index 000000000000..497850a5b428
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,pcie2-phy.yaml
> @@ -0,0 +1,87 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/qcom,pcie2-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm PCIe2 PHY controller
> +
> +maintainers:
> + - Vinod Koul <vkoul@kernel.org>
> +
> +description:
> + The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
> + platforms.
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,qcs404-pcie2-phy
> + - const: qcom,pcie2-phy
> +
> + reg:
> + items:
> + - description: PHY register set
> +
> + clocks:
> + items:
> + - description: a clock-specifier pair for the "pipe" clock
> +
> + "#phy-cells":
> + const: 0
> +
> + vdda-vp-supply:
> + description: phandle to low voltage regulator
Drop "phandle to"
> +
> + vdda-vph-supply:
> + description: phandle to high voltage regulator
Drop "phandle to"
> +
> + resets:
> + maxItems: 2
> +
> + reset-names:
> + items:
> + - const: phy
> + - const: pipe
Blank line
> + "#clock-cells":
> + const: 0
> +
> + clock-output-names:
> + maxItems: 1
Maybe keep both next to "clocks"? And same order in "required:".
> +
> +required:
> + - compatible
> + - reg
> + - "#phy-cells"
> + - clocks
> + - vdda-vp-supply
> + - vdda-vph-supply
> + - resets
> + - reset-names
> + - clock-output-names
> + - "#clock-cells"
> +
Best regards,
Krzysztof
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] arm64: dts: qcom: qcs404: register PCIe PHY as a clock provider
2022-12-16 23:40 ` Dmitry Baryshkov
@ 2022-12-20 10:39 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-20 10:39 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski
Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree
On 17/12/2022 00:40, Dmitry Baryshkov wrote:
> Add #clock-cells to the pcie_phy node. It provides a PCIe PIPE clock.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 +
> 1 file changed, 1 insertion(+)
Something to fix:
Applying: arm64: dts: qcom: qcs404: register PCIe PHY as a clock provider
git/rebase-apply/patch:100: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] arm64: dts: qcom: qcs404: register PCIe PHY as a clock provider
@ 2022-12-20 10:39 ` Krzysztof Kozlowski
0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-20 10:39 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
Krzysztof Kozlowski
Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree
On 17/12/2022 00:40, Dmitry Baryshkov wrote:
> Add #clock-cells to the pcie_phy node. It provides a PCIe PIPE clock.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 +
> 1 file changed, 1 insertion(+)
Something to fix:
Applying: arm64: dts: qcom: qcs404: register PCIe PHY as a clock provider
git/rebase-apply/patch:100: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
Best regards,
Krzysztof
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: (subset) [PATCH 1/3] dt-bindings: phy: qcom,pcie2-phy: convert to YAML format
2022-12-16 23:40 ` Dmitry Baryshkov
@ 2022-12-27 18:03 ` Bjorn Andersson
-1 siblings, 0 replies; 14+ messages in thread
From: Bjorn Andersson @ 2022-12-27 18:03 UTC (permalink / raw)
To: dmitry.baryshkov, robh+dt, kishon, krzysztof.kozlowski+dt, vkoul,
agross, konrad.dybcio
Cc: linux-arm-msm, devicetree, p.zabel, linux-phy
On Sat, 17 Dec 2022 01:40:25 +0200, Dmitry Baryshkov wrote:
> Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format
> from the text description.
>
>
Applied, thanks!
[3/3] arm64: dts: qcom: qcs404: register PCIe PHY as a clock provider
commit: 977e9262c3542e87b513d4dad4c57b2c85e16c8c
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: (subset) [PATCH 1/3] dt-bindings: phy: qcom,pcie2-phy: convert to YAML format
@ 2022-12-27 18:03 ` Bjorn Andersson
0 siblings, 0 replies; 14+ messages in thread
From: Bjorn Andersson @ 2022-12-27 18:03 UTC (permalink / raw)
To: dmitry.baryshkov, robh+dt, kishon, krzysztof.kozlowski+dt, vkoul,
agross, konrad.dybcio
Cc: linux-arm-msm, devicetree, p.zabel, linux-phy
On Sat, 17 Dec 2022 01:40:25 +0200, Dmitry Baryshkov wrote:
> Convert the bindings for the Qualcomm PCIe2 PHY into the YAML format
> from the text description.
>
>
Applied, thanks!
[3/3] arm64: dts: qcom: qcs404: register PCIe PHY as a clock provider
commit: 977e9262c3542e87b513d4dad4c57b2c85e16c8c
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-12-27 18:04 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-16 23:40 [PATCH 1/3] dt-bindings: phy: qcom,pcie2-phy: convert to YAML format Dmitry Baryshkov
2022-12-16 23:40 ` Dmitry Baryshkov
2022-12-16 23:40 ` [PATCH 2/3] phy: qualcomm: pcie2: register as clock provider Dmitry Baryshkov
2022-12-16 23:40 ` Dmitry Baryshkov
2022-12-16 23:40 ` [PATCH 3/3] arm64: dts: qcom: qcs404: register PCIe PHY as a " Dmitry Baryshkov
2022-12-16 23:40 ` Dmitry Baryshkov
2022-12-17 15:01 ` Konrad Dybcio
2022-12-17 15:01 ` Konrad Dybcio
2022-12-20 10:39 ` Krzysztof Kozlowski
2022-12-20 10:39 ` Krzysztof Kozlowski
2022-12-19 9:16 ` [PATCH 1/3] dt-bindings: phy: qcom,pcie2-phy: convert to YAML format Krzysztof Kozlowski
2022-12-19 9:16 ` Krzysztof Kozlowski
2022-12-27 18:03 ` (subset) " Bjorn Andersson
2022-12-27 18:03 ` Bjorn Andersson
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