* [PATCH 1/2] arm: mediatek: add mt8195 SOC support
@ 2022-11-08 3:21 Macpaul Lin
2022-11-08 3:21 ` [PATCH 2/2] board: mediatek: add mt8195 demo board Macpaul Lin
` (5 more replies)
0 siblings, 6 replies; 23+ messages in thread
From: Macpaul Lin @ 2022-11-08 3:21 UTC (permalink / raw)
To: Ryder Lee, Weijie Gao, Chunfeng Yun, Macpaul Lin,
GSS_MTK_Uboot_upstream, William Zhang, Simon Glass,
Philippe Reynes, Fabio Estevam, Marcel Ziswiler, Samuel Holland,
Marek Vasut, Ying-Chun Liu (PaulLiu),
Pali Rohár, Frieder Schrempf, Amjad Ouled-Ameur,
Fabien Parent, u-boot
Cc: Miles Chen, Bear Wang, Pablo Sun, Macpaul Lin
From: Fabien Parent <fparent@baylibre.com>
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
MAINTAINERS | 2 +
arch/arm/dts/mt8195.dtsi | 317 +++++++++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8195/Makefile | 3 +
arch/arm/mach-mediatek/mt8195/init.c | 81 +++++++
6 files changed, 416 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8195.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 1cf99c1393..5528dd28c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -362,8 +362,10 @@ ARM MEDIATEK
M: Ryder Lee <ryder.lee@mediatek.com>
M: Weijie Gao <weijie.gao@mediatek.com>
M: Chunfeng Yun <chunfeng.yun@mediatek.com>
+M: Macpaul Lin <macpaul.lin@mediatek.com>
R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
S: Maintained
+F: arch/arm/dts/mt8195.dtsi
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
F: board/mediatek/
diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
new file mode 100644
index 0000000000..d28b038d57
--- /dev/null
+++ b/arch/arm/dts/mt8195.dtsi
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Ben Ho <ben.ho@mediatek.com>
+ * Erin Lo <erin.lo@mediatek.com>
+ * Fabien Parent <fparent@baylibre.com>
+ * Macpaul Lin <macpaul.lin@mediatek.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x101>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x102>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x103>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+ };
+
+ clk26m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ mmc_source_clk: mmc-source-clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ clock-output-names = "mmc_source_clk";
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8195-wdt",
+ "mediatek,wdt";
+ reg = <0 0x10007000 0 0x100>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c100000 0 0x200000>, /* GICR */
+ <0 0x0c400000 0 0x2000>, /* GICC */
+ <0 0x0c410000 0 0x1000>, /* GICH */
+ <0 0x0c420000 0 0x2000>; /* GICV */
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+ };
+ };
+
+ sysirq: interrupt-controller@c530a80 {
+ compatible = "mediatek,mt8195-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x0c530a80 0 0x50>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8195-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8195-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8195-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@11001100 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,hsuart";
+ reg = <0 0x11001100 0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <26000000>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmc_source_clk>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ u3phy0: usb-phy@11f40000 {
+ compatible = "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e40000 0xe00>;
+ status = "okay";
+
+ u2port0: usb-phy@0 {
+ reg = <0 0x700>;
+ clocks = <&clk26m>,
+ <&clk26m>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&clk26m>,
+ <&clk26m>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ usb: usb@11200000 {
+ compatible ="mediatek,mt8195-mtu3", "mediatek,mtu3";
+ reg = <0 0x11200000 0 0x3e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ ssusb: ssusb@11200000 {
+ compatible = "mediatek,ssusb";
+ reg = <0 0x11200000 0 0x3e00>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
+ status = "disabled";
+ };
+
+ xhci0: xhci@11200000 {
+ compatible = "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
+ status = "disabled";
+ };
+ };
+
+ u3phy3: t-phy@11c50000 {
+ compatible = "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c50000 0x700>;
+ status = "okay";
+
+ u2port3: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ xhci3: xhci3@112b0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112b0000 0 0x1000>,
+ <0 0x112b3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port3 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ usb2-lpm-disable;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 04aa2fd97f..3a2af1cdee 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -67,6 +67,15 @@ config TARGET_MT8183
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
+config TARGET_MT8195
+ bool "MediaTek MT8195 SoC"
+ select ARM64
+ help
+ The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
+ a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
+ SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
+ and LPDDR4 options.
+
config TARGET_MT8512
bool "MediaTek MT8512 M1 Board"
select ARM64
@@ -105,6 +114,7 @@ config SYS_BOARD
default "mt7981" if TARGET_MT7981
default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
+ default "mt8195" if TARGET_MT8195
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518
@@ -122,6 +132,7 @@ config SYS_CONFIG_NAME
default "mt7981" if TARGET_MT7981
default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
+ default "mt8195" if TARGET_MT8195
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518
@@ -134,7 +145,7 @@ config SYS_CONFIG_NAME
config MTK_BROM_HEADER_INFO
string
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
- default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
+ default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8195
default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
default "lk=1" if TARGET_MT7623
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index fc85293f71..fbbb5431d1 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/
obj-$(CONFIG_TARGET_MT7981) += mt7981/
obj-$(CONFIG_TARGET_MT7986) += mt7986/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
+obj-$(CONFIG_TARGET_MT8195) += mt8195/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-mediatek/mt8195/Makefile
new file mode 100644
index 0000000000..886ab7e4eb
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8195/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c
new file mode 100644
index 0000000000..1eb4ade6c5
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8195/init.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Macpaul Lin <macpaul.lin@mediatek.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <asm/system.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+int mtk_pll_early_init(void)
+{
+ return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT8195\n");
+ return 0;
+}
+
+static struct mm_region mt8195_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mt8195_mem_map;
--
2.18.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH 2/2] board: mediatek: add mt8195 demo board
2022-11-08 3:21 [PATCH 1/2] arm: mediatek: add mt8195 SOC support Macpaul Lin
@ 2022-11-08 3:21 ` Macpaul Lin
2022-11-08 7:57 ` [PATCH 1/2] arm: mediatek: add mt8195 SOC support Pali Rohár
` (4 subsequent siblings)
5 siblings, 0 replies; 23+ messages in thread
From: Macpaul Lin @ 2022-11-08 3:21 UTC (permalink / raw)
To: Ryder Lee, Weijie Gao, Chunfeng Yun, Macpaul Lin,
GSS_MTK_Uboot_upstream, William Zhang, Simon Glass,
Philippe Reynes, Fabio Estevam, Marcel Ziswiler, Samuel Holland,
Marek Vasut, Ying-Chun Liu (PaulLiu),
Pali Rohár, Frieder Schrempf, Amjad Ouled-Ameur,
Fabien Parent, u-boot
Cc: Miles Chen, Bear Wang, Pablo Sun, Macpaul Lin
From: Fabien Parent <fparent@baylibre.com>
Add mt8195-demo board support.
This demo purpose board uses MediaTek's MT8195 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
MAINTAINERS | 1 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt8195-demo.dts | 109 ++++++++++++++++++++++++++++
board/mediatek/mt8195/MAINTAINERS | 6 ++
board/mediatek/mt8195/Makefile | 3 +
board/mediatek/mt8195/mt8195_demo.c | 38 ++++++++++
configs/mt8195_demo_defconfig | 89 +++++++++++++++++++++++
include/configs/mt8195.h | 34 +++++++++
8 files changed, 281 insertions(+)
create mode 100644 arch/arm/dts/mt8195-demo.dts
create mode 100644 board/mediatek/mt8195/MAINTAINERS
create mode 100644 board/mediatek/mt8195/Makefile
create mode 100644 board/mediatek/mt8195/mt8195_demo.c
create mode 100644 configs/mt8195_demo_defconfig
create mode 100644 include/configs/mt8195.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 5528dd28c3..5aaeeb02cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -389,6 +389,7 @@ F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
+F: include/configs/mt8195.h
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 791838733c..994f7ebcc0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1271,6 +1271,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7986a-emmc-rfb.dtb \
mt7986b-emmc-rfb.dtb \
mt8183-pumpkin.dtb \
+ mt8195-demo.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
diff --git a/arch/arm/dts/mt8195-demo.dts b/arch/arm/dts/mt8195-demo.dts
new file mode 100644
index 0000000000..bd0952b248
--- /dev/null
+++ b/arch/arm/dts/mt8195-demo.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre SAS.
+ * Author: Macpaul Lin <macpaul.lin@mediatek.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include <config.h>
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 demo board";
+ compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@54600000 {
+ no-map;
+ reg = <0 0x54600000 0x0 0x200000>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&ssusb {
+ mediatek,force-vbus;
+ maximum-speed = "high-speed";
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci3 {
+ status = "okay";
+};
diff --git a/board/mediatek/mt8195/MAINTAINERS b/board/mediatek/mt8195/MAINTAINERS
new file mode 100644
index 0000000000..01fa25115d
--- /dev/null
+++ b/board/mediatek/mt8195/MAINTAINERS
@@ -0,0 +1,6 @@
+MT8195 Demo
+M: Macpaul Lin <macpaul.lin@mediatek.com>
+S: Maintained
+F: board/mediatek/mt8195
+F: include/configs/mt8195.h
+F: configs/mt8195_demo_defconfig
diff --git a/board/mediatek/mt8195/Makefile b/board/mediatek/mt8195/Makefile
new file mode 100644
index 0000000000..7e94a87aea
--- /dev/null
+++ b/board/mediatek/mt8195/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += mt8195_demo.o
diff --git a/board/mediatek/mt8195/mt8195_demo.c b/board/mediatek/mt8195/mt8195_demo.c
new file mode 100644
index 0000000000..b95f5cf28d
--- /dev/null
+++ b/board/mediatek/mt8195/mt8195_demo.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BayLibre SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+#include <asm/io.h>
+
+int board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (CONFIG_IS_ENABLED(USB_GADGET)) {
+ ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
+ if (ret) {
+ pr_err("%s: Cannot find USB device\n", __func__);
+ return ret;
+ }
+ }
+
+ if (CONFIG_IS_ENABLED(USB_ETHER))
+ usb_ether_init();
+
+ printf("Disabling WDT\n");
+ writel(0, 0x10007000);
+
+ printf("Enabling SCP SRAM\n");
+ for (unsigned int val = 0xFFFFFFFF; val != 0U;) {
+ val = val >> 1;
+ writel(val, 0x1072102C);
+ }
+
+ return 0;
+}
diff --git a/configs/mt8195_demo_defconfig b/configs/mt8195_demo_defconfig
new file mode 100644
index 0000000000..5b075b1a27
--- /dev/null
+++ b/configs/mt8195_demo_defconfig
@@ -0,0 +1,89 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=13000000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x0
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="mt8195-demo"
+CONFIG_TARGET_MT8195=y
+CONFIG_DEBUG_UART_BASE=0x11001100
+CONFIG_DEBUG_UART_CLOCK=26000000
+# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x4c000000
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="mt8195-demo"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_MEMORY is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_BLOCK_CACHE is not set
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_ENV_IMPORT_FDT=y
+CONFIG_DEVRES=y
+CONFIG_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x4d000000
+CONFIG_FASTBOOT_BUF_SIZE=0x8000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+# CONFIG_INPUT is not set
+# CONFIG_MMC_QUIRKS is not set
+CONFIG_MMC_MTK=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_BAUDRATE=921600
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_MTK_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_MTU3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d
+CONFIG_USB_GADGET_PRODUCT_NUM=0x201c
+CONFIG_USB_ETHER=y
+CONFIG_WDT=y
+CONFIG_WDT_MTK=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/include/configs/mt8195.h b/include/configs/mt8195.h
new file mode 100644
index 0000000000..22bcf87794
--- /dev/null
+++ b/include/configs/mt8195.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for MT8195 based boards
+ *
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Fabien Parent <macpaul.lin@mediatek.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#ifndef __MT8195_H
+#define __MT8195_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_COM1 0x11002000
+#define CONFIG_SYS_NS16550_CLK 26000000
+
+/* Environment settings */
+#include <config_distro_bootcmd.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
+
+#if !defined(CONFIG_EXTRA_ENV_SETTINGS)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0x40000000\0" \
+ BOOTENV
+#endif
+
+#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support
2022-11-08 3:21 [PATCH 1/2] arm: mediatek: add mt8195 SOC support Macpaul Lin
2022-11-08 3:21 ` [PATCH 2/2] board: mediatek: add mt8195 demo board Macpaul Lin
@ 2022-11-08 7:57 ` Pali Rohár
2022-11-09 7:10 ` Macpaul Lin
2022-11-09 2:07 ` Chunfeng Yun (云春峰)
` (3 subsequent siblings)
5 siblings, 1 reply; 23+ messages in thread
From: Pali Rohár @ 2022-11-08 7:57 UTC (permalink / raw)
To: Macpaul Lin
Cc: Ryder Lee, Weijie Gao, Chunfeng Yun, GSS_MTK_Uboot_upstream,
William Zhang, Simon Glass, Philippe Reynes, Fabio Estevam,
Marcel Ziswiler, Samuel Holland, Marek Vasut,
Ying-Chun Liu (PaulLiu),
Frieder Schrempf, Amjad Ouled-Ameur, Fabien Parent, u-boot,
Miles Chen, Bear Wang, Pablo Sun, Macpaul Lin
Hello! I'm not mediatek maintainer and if this patch series is not
something important for me which should I review then please do not send
me lot of these emails... As I would have time to review stuff which are
important.
On Tuesday 08 November 2022 11:21:48 Macpaul Lin wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
> a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
> and LPDDR4 options.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> ---
> MAINTAINERS | 2 +
> arch/arm/dts/mt8195.dtsi | 317 +++++++++++++++++++++++++
> arch/arm/mach-mediatek/Kconfig | 13 +-
> arch/arm/mach-mediatek/Makefile | 1 +
> arch/arm/mach-mediatek/mt8195/Makefile | 3 +
> arch/arm/mach-mediatek/mt8195/init.c | 81 +++++++
> 6 files changed, 416 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/mt8195.dtsi
> create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
> create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1cf99c1393..5528dd28c3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -362,8 +362,10 @@ ARM MEDIATEK
> M: Ryder Lee <ryder.lee@mediatek.com>
> M: Weijie Gao <weijie.gao@mediatek.com>
> M: Chunfeng Yun <chunfeng.yun@mediatek.com>
> +M: Macpaul Lin <macpaul.lin@mediatek.com>
> R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
> S: Maintained
> +F: arch/arm/dts/mt8195.dtsi
> F: arch/arm/mach-mediatek/
> F: arch/arm/include/asm/arch-mediatek/
> F: board/mediatek/
> diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
> new file mode 100644
> index 0000000000..d28b038d57
> --- /dev/null
> +++ b/arch/arm/dts/mt8195.dtsi
> @@ -0,0 +1,317 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + * Copyright (C) 2022 BayLibre, SAS
> + * Author: Ben Ho <ben.ho@mediatek.com>
> + * Erin Lo <erin.lo@mediatek.com>
> + * Fabien Parent <fparent@baylibre.com>
> + * Macpaul Lin <macpaul.lin@mediatek.com>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
> + compatible = "mediatek,mt8195";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu4>;
> + };
> + core1 {
> + cpu = <&cpu5>;
> + };
> + core2 {
> + cpu = <&cpu6>;
> + };
> + core3 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x000>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x001>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x002>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x003>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x100>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x101>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + cpu6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x102>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + cpu7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x103>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> + };
> +
> + clk26m: oscillator {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "clk26m";
> + };
> +
> + mmc_source_clk: mmc-source-clk{
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <400000000>;
> + clock-output-names = "mmc_source_clk";
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8195-wdt",
> + "mediatek,wdt";
> + reg = <0 0x10007000 0 0x100>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <4>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x40000>, /* GICD */
> + <0 0x0c100000 0 0x200000>, /* GICR */
> + <0 0x0c400000 0 0x2000>, /* GICC */
> + <0 0x0c410000 0 0x1000>, /* GICH */
> + <0 0x0c420000 0 0x2000>; /* GICV */
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> + ppi-partitions {
> + ppi_cluster0: interrupt-partition-0 {
> + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
> + };
> + ppi_cluster1: interrupt-partition-1 {
> + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
> + };
> + };
> + };
> +
> + sysirq: interrupt-controller@c530a80 {
> + compatible = "mediatek,mt8195-sysirq",
> + "mediatek,mt6577-sysirq";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x0c530a80 0 0x50>;
> + };
> +
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt8195-topckgen", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon@10001000 {
> + compatible = "mediatek,mt8195-infracfg", "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + apmixedsys: syscon@1000c000 {
> + compatible = "mediatek,mt8195-apmixedsys", "syscon";
> + reg = <0 0x1000c000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + uart0: serial@11001100 {
> + compatible = "mediatek,mt8195-uart",
> + "mediatek,hsuart";
> + reg = <0 0x11001100 0 0x1000>;
> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <26000000>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8195-mmc",
> + "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11f50000 0 0x1000>;
> + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmc_source_clk>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + u3phy0: usb-phy@11f40000 {
> + compatible = "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11e40000 0xe00>;
> + status = "okay";
> +
> + u2port0: usb-phy@0 {
> + reg = <0 0x700>;
> + clocks = <&clk26m>,
> + <&clk26m>;
> + clock-names = "ref", "da_ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port0: usb-phy@700 {
> + reg = <0x700 0x700>;
> + clocks = <&clk26m>,
> + <&clk26m>;
> + clock-names = "ref", "da_ref";
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> + usb: usb@11200000 {
> + compatible ="mediatek,mt8195-mtu3", "mediatek,mtu3";
> + reg = <0 0x11200000 0 0x3e00>,
> + <0 0x11203e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + phys = <&u2port0 PHY_TYPE_USB2>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + ssusb: ssusb@11200000 {
> + compatible = "mediatek,ssusb";
> + reg = <0 0x11200000 0 0x3e00>;
> + reg-names = "mac";
> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
> + status = "disabled";
> + };
> +
> + xhci0: xhci@11200000 {
> + compatible = "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x1000>;
> + reg-names = "mac";
> + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
> + status = "disabled";
> + };
> + };
> +
> + u3phy3: t-phy@11c50000 {
> + compatible = "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11c50000 0x700>;
> + status = "okay";
> +
> + u2port3: usb-phy@0 {
> + reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> + };
> +
> + xhci3: xhci3@112b0000 {
> + compatible = "mediatek,mt8195-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x112b0000 0 0x1000>,
> + <0 0x112b3e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&u2port3 PHY_TYPE_USB2>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> + usb2-lpm-disable;
> + status = "disabled";
> + };
> + };
> +};
> diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
> index 04aa2fd97f..3a2af1cdee 100644
> --- a/arch/arm/mach-mediatek/Kconfig
> +++ b/arch/arm/mach-mediatek/Kconfig
> @@ -67,6 +67,15 @@ config TARGET_MT8183
> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
> and LPDDR4 options.
>
> +config TARGET_MT8195
> + bool "MediaTek MT8195 SoC"
> + select ARM64
> + help
> + The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
> + a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
> + SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
> + and LPDDR4 options.
> +
> config TARGET_MT8512
> bool "MediaTek MT8512 M1 Board"
> select ARM64
> @@ -105,6 +114,7 @@ config SYS_BOARD
> default "mt7981" if TARGET_MT7981
> default "mt7986" if TARGET_MT7986
> default "mt8183" if TARGET_MT8183
> + default "mt8195" if TARGET_MT8195
> default "mt8512" if TARGET_MT8512
> default "mt8516" if TARGET_MT8516
> default "mt8518" if TARGET_MT8518
> @@ -122,6 +132,7 @@ config SYS_CONFIG_NAME
> default "mt7981" if TARGET_MT7981
> default "mt7986" if TARGET_MT7986
> default "mt8183" if TARGET_MT8183
> + default "mt8195" if TARGET_MT8195
> default "mt8512" if TARGET_MT8512
> default "mt8516" if TARGET_MT8516
> default "mt8518" if TARGET_MT8518
> @@ -134,7 +145,7 @@ config SYS_CONFIG_NAME
> config MTK_BROM_HEADER_INFO
> string
> default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
> - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
> + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8195
> default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
> default "lk=1" if TARGET_MT7623
>
> diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
> index fc85293f71..fbbb5431d1 100644
> --- a/arch/arm/mach-mediatek/Makefile
> +++ b/arch/arm/mach-mediatek/Makefile
> @@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/
> obj-$(CONFIG_TARGET_MT7981) += mt7981/
> obj-$(CONFIG_TARGET_MT7986) += mt7986/
> obj-$(CONFIG_TARGET_MT8183) += mt8183/
> +obj-$(CONFIG_TARGET_MT8195) += mt8195/
> obj-$(CONFIG_TARGET_MT8516) += mt8516/
> obj-$(CONFIG_TARGET_MT8518) += mt8518/
> diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-mediatek/mt8195/Makefile
> new file mode 100644
> index 0000000000..886ab7e4eb
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8195/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-y += init.o
> diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c
> new file mode 100644
> index 0000000000..1eb4ade6c5
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8195/init.c
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + * Copyright (C) 2022 BayLibre, SAS
> + * Author: Macpaul Lin <macpaul.lin@mediatek.com>
> + * Author: Fabien Parent <fparent@baylibre.com>
> + */
> +
> +#include <clk.h>
> +#include <common.h>
> +#include <dm.h>
> +#include <fdtdec.h>
> +#include <ram.h>
> +#include <asm/arch/misc.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/sections.h>
> +#include <asm/system.h>
> +#include <dm/uclass.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + int ret;
> +
> + ret = fdtdec_setup_memory_banksize();
> + if (ret)
> + return ret;
> +
> + return fdtdec_setup_mem_size_base();
> +}
> +
> +int dram_init_banksize(void)
> +{
> + gd->bd->bi_dram[0].start = gd->ram_base;
> + gd->bd->bi_dram[0].size = gd->ram_size;
> +
> + return 0;
> +}
> +
> +int mtk_pll_early_init(void)
> +{
> + return 0;
> +}
> +
> +int mtk_soc_early_init(void)
> +{
> + return 0;
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> + psci_system_reset();
> +}
> +
> +int print_cpuinfo(void)
> +{
> + printf("CPU: MediaTek MT8195\n");
> + return 0;
> +}
> +
> +static struct mm_region mt8195_mem_map[] = {
> + {
> + /* DDR */
> + .virt = 0x40000000UL,
> + .phys = 0x40000000UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
> + }, {
> + .virt = 0x00000000UL,
> + .phys = 0x00000000UL,
> + .size = 0x20000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = mt8195_mem_map;
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support
2022-11-08 3:21 [PATCH 1/2] arm: mediatek: add mt8195 SOC support Macpaul Lin
2022-11-08 3:21 ` [PATCH 2/2] board: mediatek: add mt8195 demo board Macpaul Lin
2022-11-08 7:57 ` [PATCH 1/2] arm: mediatek: add mt8195 SOC support Pali Rohár
@ 2022-11-09 2:07 ` Chunfeng Yun (云春峰)
2022-11-09 7:32 ` Macpaul Lin
2022-11-09 9:50 ` [PATCH v2 " Macpaul Lin
` (2 subsequent siblings)
5 siblings, 1 reply; 23+ messages in thread
From: Chunfeng Yun (云春峰) @ 2022-11-09 2:07 UTC (permalink / raw)
To: fparent, marex, sjg, marcel.ziswiler, aouledameur,
frieder.schrempf, philippe.reynes, u-boot,
Macpaul Lin (林智斌),
GSS_MTK_Uboot_upstream, william.zhang, samuel, festevam,
Weijie Gao (高惟杰),
Ryder Lee, paul.liu
Cc: Miles Chen (陳民樺),
Bear Wang (萩原惟德),
macpaul, Pablo Sun (孫毓翔)
On Tue, 2022-11-08 at 11:21 +0800, Macpaul Lin wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73
> and
> a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and
> hosts,
> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
> and LPDDR4 options.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> ---
> MAINTAINERS | 2 +
> arch/arm/dts/mt8195.dtsi | 317
> +++++++++++++++++++++++++
> arch/arm/mach-mediatek/Kconfig | 13 +-
> arch/arm/mach-mediatek/Makefile | 1 +
> arch/arm/mach-mediatek/mt8195/Makefile | 3 +
> arch/arm/mach-mediatek/mt8195/init.c | 81 +++++++
> 6 files changed, 416 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/mt8195.dtsi
> create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
> create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1cf99c1393..5528dd28c3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -362,8 +362,10 @@ ARM MEDIATEK
> M: Ryder Lee <ryder.lee@mediatek.com>
> M: Weijie Gao <weijie.gao@mediatek.com>
> M: Chunfeng Yun <chunfeng.yun@mediatek.com>
> +M: Macpaul Lin <macpaul.lin@mediatek.com>
> R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
> S: Maintained
> +F: arch/arm/dts/mt8195.dtsi
> F: arch/arm/mach-mediatek/
> F: arch/arm/include/asm/arch-mediatek/
> F: board/mediatek/
> diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
> new file mode 100644
> index 0000000000..d28b038d57
> --- /dev/null
> +++ b/arch/arm/dts/mt8195.dtsi
> @@ -0,0 +1,317 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + * Copyright (C) 2022 BayLibre, SAS
> + * Author: Ben Ho <ben.ho@mediatek.com>
> + * Erin Lo <erin.lo@mediatek.com>
> + * Fabien Parent <fparent@baylibre.com>
> + * Macpaul Lin <macpaul.lin@mediatek.com>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
> + compatible = "mediatek,mt8195";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu4>;
> + };
> + core1 {
> + cpu = <&cpu5>;
> + };
> + core2 {
> + cpu = <&cpu6>;
> + };
> + core3 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x000>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x001>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x002>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x003>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x100>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x101>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + cpu6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x102>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + cpu7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x103>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> + };
> +
> + clk26m: oscillator {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "clk26m";
> + };
> +
> + mmc_source_clk: mmc-source-clk{
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <400000000>;
> + clock-output-names = "mmc_source_clk";
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8195-wdt",
> + "mediatek,wdt";
> + reg = <0 0x10007000 0 0x100>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <4>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x40000>, /* GICD */
> + <0 0x0c100000 0 0x200000>, /* GICR */
> + <0 0x0c400000 0 0x2000>, /* GICC */
> + <0 0x0c410000 0 0x1000>, /* GICH */
> + <0 0x0c420000 0 0x2000>; /* GICV */
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> + ppi-partitions {
> + ppi_cluster0: interrupt-partition-0 {
> + affinity = <&cpu0 &cpu1 &cpu2
> &cpu3>;
> + };
> + ppi_cluster1: interrupt-partition-1 {
> + affinity = <&cpu4 &cpu5 &cpu6
> &cpu7>;
> + };
> + };
> + };
> +
> + sysirq: interrupt-controller@c530a80 {
> + compatible = "mediatek,mt8195-sysirq",
> + "mediatek,mt6577-sysirq";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x0c530a80 0 0x50>;
> + };
> +
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt8195-topckgen",
> "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon@10001000 {
> + compatible = "mediatek,mt8195-infracfg",
> "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + apmixedsys: syscon@1000c000 {
> + compatible = "mediatek,mt8195-apmixedsys",
> "syscon";
> + reg = <0 0x1000c000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + uart0: serial@11001100 {
> + compatible = "mediatek,mt8195-uart",
> + "mediatek,hsuart";
> + reg = <0 0x11001100 0 0x1000>;
> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <26000000>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8195-mmc",
> + "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11f50000 0 0x1000>;
> + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmc_source_clk>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + u3phy0: usb-phy@11f40000 {
change node name as t-phy as u3phy3?
> + compatible = "mediatek,generic-tphy-v2";
prefer to add "mediatek,mt8195-tphy" before generic's
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11e40000 0xe00>;
> + status = "okay";
> +
> + u2port0: usb-phy@0 {
> + reg = <0 0x700>;
> + clocks = <&clk26m>,
> + <&clk26m>;
> + clock-names = "ref", "da_ref";
these two clocks are optional, if sw can't control it, no need add it
here.
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port0: usb-phy@700 {
> + reg = <0x700 0x700>;
> + clocks = <&clk26m>,
> + <&clk26m>;
> + clock-names = "ref", "da_ref";
ditto
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> + usb: usb@11200000 {
> + compatible ="mediatek,mt8195-mtu3",
> "mediatek,mtu3";
> + reg = <0 0x11200000 0 0x3e00>,
> + <0 0x11203e00 0 0x0100>;
> + reg-names = "mac", "ippc";
"mac" can be removed, the driver get it from the first child node
> + phys = <&u2port0 PHY_TYPE_USB2>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + ssusb: ssusb@11200000 {
> + compatible = "mediatek,ssusb";
> + reg = <0 0x11200000 0 0x3e00>;
> + reg-names = "mac";
> + interrupts = <GIC_SPI 128
> IRQ_TYPE_LEVEL_LOW>;
> + status = "disabled";
> + };
> +
> + xhci0: xhci@11200000 {
> + compatible = "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x1000>;
> + reg-names = "mac";
> + interrupts = <GIC_SPI 129
> IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "xhci_ck",
> "ref_ck", "mcu_ck";
> + status = "disabled";
> + };
> + };
> +
> + u3phy3: t-phy@11c50000 {
> + compatible = "mediatek,generic-tphy-v2";
add specific one
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11c50000 0x700>;
> + status = "okay";
> +
> + u2port3: usb-phy@0 {
> + reg = <0x0 0x700>;
> + clocks = <&clk26m>;
> + clock-names = "ref";
> + #phy-cells = <1>;
> + };
> + };
> +
> + xhci3: xhci3@112b0000 {
change node name as xhci? prefer to use the same name
> + compatible = "mediatek,mt8195-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x112b0000 0 0x1000>,
> + <0 0x112b3e00 0 0x0100>;
> + reg-names = "mac", "ippc";
remove "mac"
> + interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&u2port3 PHY_TYPE_USB2>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> + usb2-lpm-disable;
> + status = "disabled";
> + };
> + };
> +};
> diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-
> mediatek/Kconfig
> index 04aa2fd97f..3a2af1cdee 100644
> --- a/arch/arm/mach-mediatek/Kconfig
> +++ b/arch/arm/mach-mediatek/Kconfig
> @@ -67,6 +67,15 @@ config TARGET_MT8183
> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
> LPDDR3
> and LPDDR4 options.
>
> +config TARGET_MT8195
> + bool "MediaTek MT8195 SoC"
> + select ARM64
> + help
> + The MediaTek MT8195 is a ARM64-based SoC with a quad-core
> Cortex-A73 and
> + a quad-core Cortex-A53. It is including UART, SPI, USB3.0
> device and hosts,
> + SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
> LPDDR3
> + and LPDDR4 options.
> +
> config TARGET_MT8512
> bool "MediaTek MT8512 M1 Board"
> select ARM64
> @@ -105,6 +114,7 @@ config SYS_BOARD
> default "mt7981" if TARGET_MT7981
> default "mt7986" if TARGET_MT7986
> default "mt8183" if TARGET_MT8183
> + default "mt8195" if TARGET_MT8195
> default "mt8512" if TARGET_MT8512
> default "mt8516" if TARGET_MT8516
> default "mt8518" if TARGET_MT8518
> @@ -122,6 +132,7 @@ config SYS_CONFIG_NAME
> default "mt7981" if TARGET_MT7981
> default "mt7986" if TARGET_MT7986
> default "mt8183" if TARGET_MT8183
> + default "mt8195" if TARGET_MT8195
> default "mt8512" if TARGET_MT8512
> default "mt8516" if TARGET_MT8516
> default "mt8518" if TARGET_MT8518
> @@ -134,7 +145,7 @@ config SYS_CONFIG_NAME
> config MTK_BROM_HEADER_INFO
> string
> default "media=nor" if TARGET_MT8518 || TARGET_MT8512 ||
> TARGET_MT7629 || TARGET_MT7622
> - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 ||
> TARGET_MT8183
> + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 ||
> TARGET_MT8183 || TARGET_MT8195
> default "media=snand;nandinfo=2k+64" if TARGET_MT7981 ||
> TARGET_MT7986
> default "lk=1" if TARGET_MT7623
>
> diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-
> mediatek/Makefile
> index fc85293f71..fbbb5431d1 100644
> --- a/arch/arm/mach-mediatek/Makefile
> +++ b/arch/arm/mach-mediatek/Makefile
> @@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/
> obj-$(CONFIG_TARGET_MT7981) += mt7981/
> obj-$(CONFIG_TARGET_MT7986) += mt7986/
> obj-$(CONFIG_TARGET_MT8183) += mt8183/
> +obj-$(CONFIG_TARGET_MT8195) += mt8195/
> obj-$(CONFIG_TARGET_MT8516) += mt8516/
> obj-$(CONFIG_TARGET_MT8518) += mt8518/
> diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-
> mediatek/mt8195/Makefile
> new file mode 100644
> index 0000000000..886ab7e4eb
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8195/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-y += init.o
> diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-
> mediatek/mt8195/init.c
> new file mode 100644
> index 0000000000..1eb4ade6c5
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8195/init.c
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + * Copyright (C) 2022 BayLibre, SAS
> + * Author: Macpaul Lin <macpaul.lin@mediatek.com>
> + * Author: Fabien Parent <fparent@baylibre.com>
> + */
> +
> +#include <clk.h>
> +#include <common.h>
> +#include <dm.h>
> +#include <fdtdec.h>
> +#include <ram.h>
> +#include <asm/arch/misc.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/sections.h>
> +#include <asm/system.h>
> +#include <dm/uclass.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + int ret;
> +
> + ret = fdtdec_setup_memory_banksize();
> + if (ret)
> + return ret;
> +
> + return fdtdec_setup_mem_size_base();
> +}
> +
> +int dram_init_banksize(void)
> +{
> + gd->bd->bi_dram[0].start = gd->ram_base;
> + gd->bd->bi_dram[0].size = gd->ram_size;
> +
> + return 0;
> +}
> +
> +int mtk_pll_early_init(void)
> +{
> + return 0;
> +}
> +
> +int mtk_soc_early_init(void)
> +{
> + return 0;
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> + psci_system_reset();
> +}
> +
> +int print_cpuinfo(void)
> +{
> + printf("CPU: MediaTek MT8195\n");
> + return 0;
> +}
> +
> +static struct mm_region mt8195_mem_map[] = {
> + {
> + /* DDR */
> + .virt = 0x40000000UL,
> + .phys = 0x40000000UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> PTE_BLOCK_OUTER_SHARE,
> + }, {
> + .virt = 0x00000000UL,
> + .phys = 0x00000000UL,
> + .size = 0x20000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = mt8195_mem_map;
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support
2022-11-08 7:57 ` [PATCH 1/2] arm: mediatek: add mt8195 SOC support Pali Rohár
@ 2022-11-09 7:10 ` Macpaul Lin
2022-11-09 20:09 ` Pali Rohár
0 siblings, 1 reply; 23+ messages in thread
From: Macpaul Lin @ 2022-11-09 7:10 UTC (permalink / raw)
To: Pali Rohár
Cc: Ryder Lee, Weijie Gao, Chunfeng Yun, GSS_MTK_Uboot_upstream,
William Zhang, Simon Glass, Philippe Reynes, Fabio Estevam,
Marcel Ziswiler, Samuel Holland, Marek Vasut,
Ying-Chun Liu (PaulLiu),
Frieder Schrempf, Amjad Ouled-Ameur, Fabien Parent, u-boot,
Miles Chen, Bear Wang, Pablo Sun, Macpaul Lin
On 11/8/22 15:57, Pali Rohár wrote:
> Hello! I'm not mediatek maintainer and if this patch series is not
> something important for me which should I review then please do not send
> me lot of these emails... As I would have time to review stuff which are
> important.
I'm so sorry for bothering you and other developers.
I've used ./scripts/get_maintainer.pl to check these 2 patches and found
you all in the suggestion list.
Result:
"Pali Rohár" <pali@kernel.org>
(added_lines:16/253=6%,removed_lines:12/76=16%)
I'll remove Pali when I send next version.
Who else don't want to be involved in these reviewing activities of
MediaTek platforms, please let us know.
[deleted]
Thanks!
Macpaul Lin
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support
2022-11-09 2:07 ` Chunfeng Yun (云春峰)
@ 2022-11-09 7:32 ` Macpaul Lin
2022-11-09 9:33 ` Macpaul Lin
0 siblings, 1 reply; 23+ messages in thread
From: Macpaul Lin @ 2022-11-09 7:32 UTC (permalink / raw)
To: Chunfeng Yun (云春峰),
fparent, marex, sjg, marcel.ziswiler, aouledameur,
frieder.schrempf, philippe.reynes, u-boot,
GSS_MTK_Uboot_upstream, william.zhang, samuel, festevam,
Weijie Gao (高惟杰),
Ryder Lee, paul.liu
Cc: Miles Chen (陳民樺),
Bear Wang (萩原惟德),
macpaul, Pablo Sun (孫毓翔)
On 11/9/22 10:07, Chunfeng Yun (云春峰) wrote:
> On Tue, 2022-11-08 at 11:21 +0800, Macpaul Lin wrote:
>> From: Fabien Parent <fparent@baylibre.com>
>>
>> The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73
>> and
>> a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and
>> hosts,
>> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
>> and LPDDR4 options.
>>
>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
>> ---
>> MAINTAINERS | 2 +
>> arch/arm/dts/mt8195.dtsi | 317
>> +++++++++++++++++++++++++
>> arch/arm/mach-mediatek/Kconfig | 13 +-
>> arch/arm/mach-mediatek/Makefile | 1 +
>> arch/arm/mach-mediatek/mt8195/Makefile | 3 +
>> arch/arm/mach-mediatek/mt8195/init.c | 81 +++++++
>> 6 files changed, 416 insertions(+), 1 deletion(-)
>> create mode 100644 arch/arm/dts/mt8195.dtsi
>> create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
>> create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
[deleted]
>> + u3phy0: usb-phy@11f40000 {
> change node name as t-phy as u3phy3?
>
Got it, will fix it in next version.
>> + compatible = "mediatek,generic-tphy-v2";
> prefer to add "mediatek,mt8195-tphy" before generic's
>
Will fix it in next version.
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0 0x11e40000 0xe00>;
>> + status = "okay";
>> +
>> + u2port0: usb-phy@0 {
>> + reg = <0 0x700>;
>> + clocks = <&clk26m>,
>> + <&clk26m>;
>> + clock-names = "ref", "da_ref";
> these two clocks are optional, if sw can't control it, no need add it
> here.
MediaTek's clock driver developer will upstream clock driver when
refactoring
work has been completed. Before clock driver is applied to trunk, we can use
clk26m only.
Will fix it in next version.
>> + #phy-cells = <1>;
>> + status = "okay";
>> + };
>> +
>> + u3port0: usb-phy@700 {
>> + reg = <0x700 0x700>;
>> + clocks = <&clk26m>,
>> + <&clk26m>;
>> + clock-names = "ref", "da_ref";
> ditto
>
Will fix it in next version.
>> + #phy-cells = <1>;
>> + status = "okay";
>> + };
>> + };
>> +
>> + usb: usb@11200000 {
>> + compatible ="mediatek,mt8195-mtu3",
>> "mediatek,mtu3";
>> + reg = <0 0x11200000 0 0x3e00>,
>> + <0 0x11203e00 0 0x0100>;
>> + reg-names = "mac", "ippc";
> "mac" can be removed, the driver get it from the first child node
>
Will fix it in next version.
>> + phys = <&u2port0 PHY_TYPE_USB2>;
>> + clocks = <&clk26m>,
>> + <&clk26m>,
>> + <&clk26m>;
>> + clock-names = "sys_ck", "ref_ck", "mcu_ck";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + status = "disabled";
>> +
>> + ssusb: ssusb@11200000 {
>> + compatible = "mediatek,ssusb";
>> + reg = <0 0x11200000 0 0x3e00>;
>> + reg-names = "mac";
>> + interrupts = <GIC_SPI 128
>> IRQ_TYPE_LEVEL_LOW>;
>> + status = "disabled";
>> + };
>> +
>> + xhci0: xhci@11200000 {
>> + compatible = "mediatek,mtk-xhci";
>> + reg = <0 0x11200000 0 0x1000>;
>> + reg-names = "mac";
>> + interrupts = <GIC_SPI 129
>> IRQ_TYPE_LEVEL_LOW>;
>> + clocks = <&clk26m>,
>> + <&clk26m>,
>> + <&clk26m>,
>> + <&clk26m>;
>> + clock-names = "sys_ck", "xhci_ck",
>> "ref_ck", "mcu_ck";
>> + status = "disabled";
>> + };
>> + };
>> +
>> + u3phy3: t-phy@11c50000 {
>> + compatible = "mediatek,generic-tphy-v2";
> add specific one
>
Will fix it in next version.
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0 0x11c50000 0x700>;
>> + status = "okay";
>> +
>> + u2port3: usb-phy@0 {
>> + reg = <0x0 0x700>;
>> + clocks = <&clk26m>;
>> + clock-names = "ref";
>> + #phy-cells = <1>;
>> + };
>> + };
>> +
>> + xhci3: xhci3@112b0000 {
> change node name as xhci? prefer to use the same name
>
Since there are other board manufacturers will use the
other HOST ports, like xhci1 or xhci2 with USB mass storage
function by their needs.
I'll add these 2 node in dtsi in next version.
>> + compatible = "mediatek,mt8195-xhci",
>> + "mediatek,mtk-xhci";
>> + reg = <0 0x112b0000 0 0x1000>,
>> + <0 0x112b3e00 0 0x0100>;
>> + reg-names = "mac", "ippc";
> remove "mac"
Will fix it in next version.
>> + interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
>> + phys = <&u2port3 PHY_TYPE_USB2>;
>> + clocks = <&clk26m>,
>> + <&clk26m>,
>> + <&clk26m>;
>> + clock-names = "sys_ck", "xhci_ck", "ref_ck";
>> + usb2-lpm-disable;
>> + status = "disabled";
>> + };
>> + };
>> +};
>> diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-
>> mediatek/Kconfig
>> index 04aa2fd97f..3a2af1cdee 100644
>> --- a/arch/arm/mach-mediatek/Kconfig
>> +++ b/arch/arm/mach-mediatek/Kconfig
>> @@ -67,6 +67,15 @@ config TARGET_MT8183
>> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
>> LPDDR3
>> and LPDDR4 options.
>>
>> +config TARGET_MT8195
>> + bool "MediaTek MT8195 SoC"
>> + select ARM64
>> + help
>> + The MediaTek MT8195 is a ARM64-based SoC with a quad-core
>> Cortex-A73 and
>> + a quad-core Cortex-A53. It is including UART, SPI, USB3.0
>> device and hosts,
>> + SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
>> LPDDR3
>> + and LPDDR4 options.
>> +
>> config TARGET_MT8512
>> bool "MediaTek MT8512 M1 Board"
>> select ARM64
>> @@ -105,6 +114,7 @@ config SYS_BOARD
>> default "mt7981" if TARGET_MT7981
>> default "mt7986" if TARGET_MT7986
>> default "mt8183" if TARGET_MT8183
>> + default "mt8195" if TARGET_MT8195
>> default "mt8512" if TARGET_MT8512
>> default "mt8516" if TARGET_MT8516
>> default "mt8518" if TARGET_MT8518
>> @@ -122,6 +132,7 @@ config SYS_CONFIG_NAME
>> default "mt7981" if TARGET_MT7981
>> default "mt7986" if TARGET_MT7986
>> default "mt8183" if TARGET_MT8183
>> + default "mt8195" if TARGET_MT8195
>> default "mt8512" if TARGET_MT8512
>> default "mt8516" if TARGET_MT8516
>> default "mt8518" if TARGET_MT8518
>> @@ -134,7 +145,7 @@ config SYS_CONFIG_NAME
>> config MTK_BROM_HEADER_INFO
>> string
>> default "media=nor" if TARGET_MT8518 || TARGET_MT8512 ||
>> TARGET_MT7629 || TARGET_MT7622
>> - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 ||
>> TARGET_MT8183
>> + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 ||
>> TARGET_MT8183 || TARGET_MT8195
>> default "media=snand;nandinfo=2k+64" if TARGET_MT7981 ||
>> TARGET_MT7986
>> default "lk=1" if TARGET_MT7623
>>
>> diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-
>> mediatek/Makefile
>> index fc85293f71..fbbb5431d1 100644
>> --- a/arch/arm/mach-mediatek/Makefile
>> +++ b/arch/arm/mach-mediatek/Makefile
>> @@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/
>> obj-$(CONFIG_TARGET_MT7981) += mt7981/
>> obj-$(CONFIG_TARGET_MT7986) += mt7986/
>> obj-$(CONFIG_TARGET_MT8183) += mt8183/
>> +obj-$(CONFIG_TARGET_MT8195) += mt8195/
>> obj-$(CONFIG_TARGET_MT8516) += mt8516/
>> obj-$(CONFIG_TARGET_MT8518) += mt8518/
>> diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-
>> mediatek/mt8195/Makefile
>> new file mode 100644
>> index 0000000000..886ab7e4eb
>> --- /dev/null
>> +++ b/arch/arm/mach-mediatek/mt8195/Makefile
>> @@ -0,0 +1,3 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +
>> +obj-y += init.o
>> diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-
>> mediatek/mt8195/init.c
>> new file mode 100644
>> index 0000000000..1eb4ade6c5
>> --- /dev/null
>> +++ b/arch/arm/mach-mediatek/mt8195/init.c
>> @@ -0,0 +1,81 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2022 MediaTek Inc.
>> + * Copyright (C) 2022 BayLibre, SAS
>> + * Author: Macpaul Lin <macpaul.lin@mediatek.com>
>> + * Author: Fabien Parent <fparent@baylibre.com>
>> + */
>> +
>> +#include <clk.h>
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <fdtdec.h>
>> +#include <ram.h>
>> +#include <asm/arch/misc.h>
>> +#include <asm/armv8/mmu.h>
>> +#include <asm/sections.h>
>> +#include <asm/system.h>
>> +#include <dm/uclass.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int dram_init(void)
>> +{
>> + int ret;
>> +
>> + ret = fdtdec_setup_memory_banksize();
>> + if (ret)
>> + return ret;
>> +
>> + return fdtdec_setup_mem_size_base();
>> +}
>> +
>> +int dram_init_banksize(void)
>> +{
>> + gd->bd->bi_dram[0].start = gd->ram_base;
>> + gd->bd->bi_dram[0].size = gd->ram_size;
>> +
>> + return 0;
>> +}
>> +
>> +int mtk_pll_early_init(void)
>> +{
>> + return 0;
>> +}
>> +
>> +int mtk_soc_early_init(void)
>> +{
>> + return 0;
>> +}
>> +
>> +void reset_cpu(ulong addr)
>> +{
>> + psci_system_reset();
>> +}
>> +
>> +int print_cpuinfo(void)
>> +{
>> + printf("CPU: MediaTek MT8195\n");
>> + return 0;
>> +}
>> +
>> +static struct mm_region mt8195_mem_map[] = {
>> + {
>> + /* DDR */
>> + .virt = 0x40000000UL,
>> + .phys = 0x40000000UL,
>> + .size = 0x80000000UL,
>> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
>> PTE_BLOCK_OUTER_SHARE,
>> + }, {
>> + .virt = 0x00000000UL,
>> + .phys = 0x00000000UL,
>> + .size = 0x20000000UL,
>> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
>> + PTE_BLOCK_NON_SHARE |
>> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
>> + }, {
>> + 0,
>> + }
>> +};
>> +
>> +struct mm_region *mem_map = mt8195_mem_map;
Thanks a lot!
Macpaul Lin
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support
2022-11-09 7:32 ` Macpaul Lin
@ 2022-11-09 9:33 ` Macpaul Lin
2022-11-09 13:00 ` Chunfeng Yun (云春峰)
0 siblings, 1 reply; 23+ messages in thread
From: Macpaul Lin @ 2022-11-09 9:33 UTC (permalink / raw)
To: Chunfeng Yun (云春峰),
fparent, marex, sjg, marcel.ziswiler, aouledameur,
frieder.schrempf, philippe.reynes, u-boot,
GSS_MTK_Uboot_upstream, william.zhang, samuel, festevam,
Weijie Gao (高惟杰),
Ryder Lee, paul.liu
Cc: Miles Chen (陳民樺),
Bear Wang (萩原惟德),
macpaul, Pablo Sun (孫毓翔)
On 11/9/22 15:32, Macpaul Lin wrote:
>
> On 11/9/22 10:07, Chunfeng Yun (云春峰) wrote:
>> On Tue, 2022-11-08 at 11:21 +0800, Macpaul Lin wrote:
>>> From: Fabien Parent <fparent@baylibre.com>
>>>
>>> The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73
>>> and
>>> a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and
>>> hosts,
>>> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
>>> and LPDDR4 options.
>>>
>>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>>> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
>>> ---
>>> MAINTAINERS | 2 +
>>> arch/arm/dts/mt8195.dtsi | 317
>>> +++++++++++++++++++++++++
>>> arch/arm/mach-mediatek/Kconfig | 13 +-
>>> arch/arm/mach-mediatek/Makefile | 1 +
>>> arch/arm/mach-mediatek/mt8195/Makefile | 3 +
>>> arch/arm/mach-mediatek/mt8195/init.c | 81 +++++++
>>> 6 files changed, 416 insertions(+), 1 deletion(-)
>>> create mode 100644 arch/arm/dts/mt8195.dtsi
>>> create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
>>> create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
[deleted]
>>> + xhci3: xhci3@112b0000 {
>> change node name as xhci? prefer to use the same name
>>
>
> Since there are other board manufacturers will use the
> other HOST ports, like xhci1 or xhci2 with USB mass storage
> function by their needs.
> I'll add these 2 node in dtsi in next version.
>
>>> + compatible = "mediatek,mt8195-xhci",
>>> + "mediatek,mtk-xhci";
>>> + reg = <0 0x112b0000 0 0x1000>,
>>> + <0 0x112b3e00 0 0x0100>;
>>> + reg-names = "mac", "ippc";
>> remove "mac"
>
> Will fix it in next version.
>
Dear Chunfeng,
Unfortunately, if we remove "mac" register here for HOST only node like
xhci3, the driver will complain about probing fail. Please check the
following log.
=> usb start
starting USB...
Bus xhci3@112b0000: xhci-mtk xhci3@112b0000: failed to get xHCI base address
probe failed, error -6
No working controllers found
I'll add "mac" back to HOST only nodes.
Thanks!
Macpaul Lin
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v2 1/2] arm: mediatek: add mt8195 SOC support
2022-11-08 3:21 [PATCH 1/2] arm: mediatek: add mt8195 SOC support Macpaul Lin
` (2 preceding siblings ...)
2022-11-09 2:07 ` Chunfeng Yun (云春峰)
@ 2022-11-09 9:50 ` Macpaul Lin
2022-11-09 9:50 ` [PATCH v2 2/2] board: mediatek: add mt8195 demo board Macpaul Lin
2022-11-09 13:06 ` [PATCH v2 1/2] arm: mediatek: add mt8195 SOC support Chunfeng Yun (云春峰)
2022-11-10 7:34 ` [PATCH v3 " Macpaul Lin
2022-12-19 6:43 ` [PATCH v4 " Macpaul Lin
5 siblings, 2 replies; 23+ messages in thread
From: Macpaul Lin @ 2022-11-09 9:50 UTC (permalink / raw)
To: Chunfeng Yun, fparent @ baylibre . com, marex @ denx . de,
sjg @ chromium . org, marcel . ziswiler @ toradex . com,
aouledameur @ baylibre . com, frieder . schrempf @ kontron . de,
philippe . reynes @ softathome . com, u-boot @ lists . denx . de,
GSS_MTK_Uboot_upstream, william . zhang @ broadcom . com,
samuel @ sholland . org, festevam @ denx . de, Weijie Gao,
Ryder Lee, paul . liu @ linaro . org
Cc: Miles Chen, Bear Wang, Pablo Sun, Macpaul Lin, Macpaul Lin
From: Fabien Parent <fparent@baylibre.com>
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
MAINTAINERS | 2 +
arch/arm/dts/mt8195.dtsi | 370 +++++++++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8195/Makefile | 3 +
arch/arm/mach-mediatek/mt8195/init.c | 81 ++++++
6 files changed, 469 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8195.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
Changes for v2:
- Correct node name to t-phy for u3phy0.
- Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes.
- remove clock nodes that software cannot controlled in phy nodes.
- Test and add back "mac" for HOST only xhci nodes.
diff --git a/MAINTAINERS b/MAINTAINERS
index 1cf99c1393..5528dd28c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -362,8 +362,10 @@ ARM MEDIATEK
M: Ryder Lee <ryder.lee@mediatek.com>
M: Weijie Gao <weijie.gao@mediatek.com>
M: Chunfeng Yun <chunfeng.yun@mediatek.com>
+M: Macpaul Lin <macpaul.lin@mediatek.com>
R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
S: Maintained
+F: arch/arm/dts/mt8195.dtsi
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
F: board/mediatek/
diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
new file mode 100644
index 0000000000..33282d21d1
--- /dev/null
+++ b/arch/arm/dts/mt8195.dtsi
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Ben Ho <ben.ho@mediatek.com>
+ * Erin Lo <erin.lo@mediatek.com>
+ * Fabien Parent <fparent@baylibre.com>
+ * Macpaul Lin <macpaul.lin@mediatek.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x101>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x102>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x103>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+ };
+
+ clk26m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ mmc_source_clk: mmc-source-clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ clock-output-names = "mmc_source_clk";
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8195-wdt",
+ "mediatek,wdt";
+ reg = <0 0x10007000 0 0x100>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c100000 0 0x200000>, /* GICR */
+ <0 0x0c400000 0 0x2000>, /* GICC */
+ <0 0x0c410000 0 0x1000>, /* GICH */
+ <0 0x0c420000 0 0x2000>; /* GICV */
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+ };
+ };
+
+ sysirq: interrupt-controller@c530a80 {
+ compatible = "mediatek,mt8195-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x0c530a80 0 0x50>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8195-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8195-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8195-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@11001100 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,hsuart";
+ reg = <0 0x11001100 0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <26000000>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmc_source_clk>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ u3phy0: t-phy@11f40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e40000 0xe00>;
+ status = "okay";
+
+ u2port0: usb-phy@0 {
+ reg = <0 0x700>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x700>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ usb: usb@11200000 {
+ compatible ="mediatek,mt8195-mtu3", "mediatek,mtu3";
+ reg = <0 0x11203e00 0 0x0100>;
+ reg-names = "ippc";
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ ssusb: ssusb@11200000 {
+ compatible = "mediatek,ssusb";
+ reg = <0 0x11200000 0 0x3e00>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
+ status = "disabled";
+ };
+
+ xhci0: xhci@11200000 {
+ compatible = "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
+ status = "disabled";
+ };
+ };
+
+ u3phy1: t-phy@11e30000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e30000 0xe00>;
+ status = "disabled";
+
+ u2port1: usb-phy@0 {
+ reg = <0x0 0x700>;
+ #phy-cells = <1>;
+ };
+
+ u3port1: usb-phy@700 {
+ reg = <0x700 0x700>;
+ #phy-cells = <1>;
+ };
+ };
+
+ xhci1: xhci1@11290000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11290000 0 0x1000>,
+ <0 0x11293e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port1 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
+ status = "disabled";
+ };
+
+ u3phy2: t-phy@11c40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c40000 0x700>;
+ status = "disabled";
+
+ u2port2: usb-phy@0 {
+ reg = <0x0 0x700>;
+ #phy-cells = <1>;
+ };
+ };
+
+ xhci2: xhci2@112a0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112a0000 0 0x1000>,
+ <0 0x112a3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ status = "disabled";
+ };
+
+ u3phy3: t-phy@11c50000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c50000 0x700>;
+ status = "okay";
+
+ u2port3: usb-phy@0 {
+ reg = <0x0 0x700>;
+ #phy-cells = <1>;
+ };
+ };
+
+ xhci3: xhci3@112b0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112b0000 0 0x1000>,
+ <0 0x112b3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port3 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ usb2-lpm-disable;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 04aa2fd97f..3a2af1cdee 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -67,6 +67,15 @@ config TARGET_MT8183
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
+config TARGET_MT8195
+ bool "MediaTek MT8195 SoC"
+ select ARM64
+ help
+ The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
+ a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
+ SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
+ and LPDDR4 options.
+
config TARGET_MT8512
bool "MediaTek MT8512 M1 Board"
select ARM64
@@ -105,6 +114,7 @@ config SYS_BOARD
default "mt7981" if TARGET_MT7981
default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
+ default "mt8195" if TARGET_MT8195
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518
@@ -122,6 +132,7 @@ config SYS_CONFIG_NAME
default "mt7981" if TARGET_MT7981
default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
+ default "mt8195" if TARGET_MT8195
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518
@@ -134,7 +145,7 @@ config SYS_CONFIG_NAME
config MTK_BROM_HEADER_INFO
string
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
- default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
+ default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8195
default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
default "lk=1" if TARGET_MT7623
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index fc85293f71..fbbb5431d1 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/
obj-$(CONFIG_TARGET_MT7981) += mt7981/
obj-$(CONFIG_TARGET_MT7986) += mt7986/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
+obj-$(CONFIG_TARGET_MT8195) += mt8195/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-mediatek/mt8195/Makefile
new file mode 100644
index 0000000000..886ab7e4eb
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8195/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c
new file mode 100644
index 0000000000..1eb4ade6c5
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8195/init.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Macpaul Lin <macpaul.lin@mediatek.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <asm/system.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+int mtk_pll_early_init(void)
+{
+ return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT8195\n");
+ return 0;
+}
+
+static struct mm_region mt8195_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mt8195_mem_map;
--
2.18.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v2 2/2] board: mediatek: add mt8195 demo board
2022-11-09 9:50 ` [PATCH v2 " Macpaul Lin
@ 2022-11-09 9:50 ` Macpaul Lin
2022-11-09 13:06 ` [PATCH v2 1/2] arm: mediatek: add mt8195 SOC support Chunfeng Yun (云春峰)
1 sibling, 0 replies; 23+ messages in thread
From: Macpaul Lin @ 2022-11-09 9:50 UTC (permalink / raw)
To: Chunfeng Yun, fparent @ baylibre . com, marex @ denx . de,
sjg @ chromium . org, marcel . ziswiler @ toradex . com,
aouledameur @ baylibre . com, frieder . schrempf @ kontron . de,
philippe . reynes @ softathome . com, u-boot @ lists . denx . de,
GSS_MTK_Uboot_upstream, william . zhang @ broadcom . com,
samuel @ sholland . org, festevam @ denx . de, Weijie Gao,
Ryder Lee, paul . liu @ linaro . org
Cc: Miles Chen, Bear Wang, Pablo Sun, Macpaul Lin, Macpaul Lin
From: Fabien Parent <fparent@baylibre.com>
Add mt8195-demo board support.
This demo purpose board uses MediaTek's MT8195 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
MAINTAINERS | 1 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt8195-demo.dts | 109 ++++++++++++++++++++++++++++
board/mediatek/mt8195/MAINTAINERS | 6 ++
board/mediatek/mt8195/Makefile | 3 +
board/mediatek/mt8195/mt8195_demo.c | 38 ++++++++++
configs/mt8195_demo_defconfig | 89 +++++++++++++++++++++++
include/configs/mt8195.h | 34 +++++++++
8 files changed, 281 insertions(+)
create mode 100644 arch/arm/dts/mt8195-demo.dts
create mode 100644 board/mediatek/mt8195/MAINTAINERS
create mode 100644 board/mediatek/mt8195/Makefile
create mode 100644 board/mediatek/mt8195/mt8195_demo.c
create mode 100644 configs/mt8195_demo_defconfig
create mode 100644 include/configs/mt8195.h
Changes for v2:
- no change.
diff --git a/MAINTAINERS b/MAINTAINERS
index 5528dd28c3..5aaeeb02cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -389,6 +389,7 @@ F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
+F: include/configs/mt8195.h
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 791838733c..994f7ebcc0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1271,6 +1271,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7986a-emmc-rfb.dtb \
mt7986b-emmc-rfb.dtb \
mt8183-pumpkin.dtb \
+ mt8195-demo.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
diff --git a/arch/arm/dts/mt8195-demo.dts b/arch/arm/dts/mt8195-demo.dts
new file mode 100644
index 0000000000..bd0952b248
--- /dev/null
+++ b/arch/arm/dts/mt8195-demo.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre SAS.
+ * Author: Macpaul Lin <macpaul.lin@mediatek.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include <config.h>
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 demo board";
+ compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@54600000 {
+ no-map;
+ reg = <0 0x54600000 0x0 0x200000>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&ssusb {
+ mediatek,force-vbus;
+ maximum-speed = "high-speed";
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci3 {
+ status = "okay";
+};
diff --git a/board/mediatek/mt8195/MAINTAINERS b/board/mediatek/mt8195/MAINTAINERS
new file mode 100644
index 0000000000..01fa25115d
--- /dev/null
+++ b/board/mediatek/mt8195/MAINTAINERS
@@ -0,0 +1,6 @@
+MT8195 Demo
+M: Macpaul Lin <macpaul.lin@mediatek.com>
+S: Maintained
+F: board/mediatek/mt8195
+F: include/configs/mt8195.h
+F: configs/mt8195_demo_defconfig
diff --git a/board/mediatek/mt8195/Makefile b/board/mediatek/mt8195/Makefile
new file mode 100644
index 0000000000..7e94a87aea
--- /dev/null
+++ b/board/mediatek/mt8195/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += mt8195_demo.o
diff --git a/board/mediatek/mt8195/mt8195_demo.c b/board/mediatek/mt8195/mt8195_demo.c
new file mode 100644
index 0000000000..b95f5cf28d
--- /dev/null
+++ b/board/mediatek/mt8195/mt8195_demo.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BayLibre SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+#include <asm/io.h>
+
+int board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (CONFIG_IS_ENABLED(USB_GADGET)) {
+ ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
+ if (ret) {
+ pr_err("%s: Cannot find USB device\n", __func__);
+ return ret;
+ }
+ }
+
+ if (CONFIG_IS_ENABLED(USB_ETHER))
+ usb_ether_init();
+
+ printf("Disabling WDT\n");
+ writel(0, 0x10007000);
+
+ printf("Enabling SCP SRAM\n");
+ for (unsigned int val = 0xFFFFFFFF; val != 0U;) {
+ val = val >> 1;
+ writel(val, 0x1072102C);
+ }
+
+ return 0;
+}
diff --git a/configs/mt8195_demo_defconfig b/configs/mt8195_demo_defconfig
new file mode 100644
index 0000000000..5b075b1a27
--- /dev/null
+++ b/configs/mt8195_demo_defconfig
@@ -0,0 +1,89 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=13000000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x0
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="mt8195-demo"
+CONFIG_TARGET_MT8195=y
+CONFIG_DEBUG_UART_BASE=0x11001100
+CONFIG_DEBUG_UART_CLOCK=26000000
+# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x4c000000
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="mt8195-demo"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_MEMORY is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_BLOCK_CACHE is not set
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_ENV_IMPORT_FDT=y
+CONFIG_DEVRES=y
+CONFIG_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x4d000000
+CONFIG_FASTBOOT_BUF_SIZE=0x8000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+# CONFIG_INPUT is not set
+# CONFIG_MMC_QUIRKS is not set
+CONFIG_MMC_MTK=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_BAUDRATE=921600
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_MTK_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_MTU3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d
+CONFIG_USB_GADGET_PRODUCT_NUM=0x201c
+CONFIG_USB_ETHER=y
+CONFIG_WDT=y
+CONFIG_WDT_MTK=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/include/configs/mt8195.h b/include/configs/mt8195.h
new file mode 100644
index 0000000000..22bcf87794
--- /dev/null
+++ b/include/configs/mt8195.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for MT8195 based boards
+ *
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Fabien Parent <macpaul.lin@mediatek.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#ifndef __MT8195_H
+#define __MT8195_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_COM1 0x11002000
+#define CONFIG_SYS_NS16550_CLK 26000000
+
+/* Environment settings */
+#include <config_distro_bootcmd.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
+
+#if !defined(CONFIG_EXTRA_ENV_SETTINGS)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0x40000000\0" \
+ BOOTENV
+#endif
+
+#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support
2022-11-09 9:33 ` Macpaul Lin
@ 2022-11-09 13:00 ` Chunfeng Yun (云春峰)
0 siblings, 0 replies; 23+ messages in thread
From: Chunfeng Yun (云春峰) @ 2022-11-09 13:00 UTC (permalink / raw)
To: fparent, marex, sjg, marcel.ziswiler, aouledameur,
frieder.schrempf, philippe.reynes, u-boot,
Macpaul Lin (林智斌),
GSS_MTK_Uboot_upstream, william.zhang, samuel, festevam,
Weijie Gao (高惟杰),
Ryder Lee, paul.liu
Cc: Miles Chen (陳民樺),
Bear Wang (萩原惟德),
macpaul, Pablo Sun (孫毓翔)
On Wed, 2022-11-09 at 17:33 +0800, Macpaul Lin wrote:
> On 11/9/22 15:32, Macpaul Lin wrote:
> >
> > On 11/9/22 10:07, Chunfeng Yun (云春峰) wrote:
> > > On Tue, 2022-11-08 at 11:21 +0800, Macpaul Lin wrote:
> > > > From: Fabien Parent <fparent@baylibre.com>
> > > >
> > > > The MediaTek MT8195 is a ARM64-based SoC with a quad-core
> > > > Cortex-A73
> > > > and
> > > > a quad-core Cortex-A53. It is including UART, SPI, USB3.0
> > > > device and
> > > > hosts,
> > > > SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
> > > > LPDDR3
> > > > and LPDDR4 options.
> > > >
> > > > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > > > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> > > > ---
> > > > MAINTAINERS | 2 +
> > > > arch/arm/dts/mt8195.dtsi | 317
> > > > +++++++++++++++++++++++++
> > > > arch/arm/mach-mediatek/Kconfig | 13 +-
> > > > arch/arm/mach-mediatek/Makefile | 1 +
> > > > arch/arm/mach-mediatek/mt8195/Makefile | 3 +
> > > > arch/arm/mach-mediatek/mt8195/init.c | 81 +++++++
> > > > 6 files changed, 416 insertions(+), 1 deletion(-)
> > > > create mode 100644 arch/arm/dts/mt8195.dtsi
> > > > create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
> > > > create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
>
> [deleted]
>
> > > > + xhci3: xhci3@112b0000 {
> > >
> > > change node name as xhci? prefer to use the same name
> > >
> >
> > Since there are other board manufacturers will use the
> > other HOST ports, like xhci1 or xhci2 with USB mass storage
> > function by their needs.
> > I'll add these 2 node in dtsi in next version.
> >
> > > > + compatible = "mediatek,mt8195-xhci",
> > > > + "mediatek,mtk-xhci";
> > > > + reg = <0 0x112b0000 0 0x1000>,
> > > > + <0 0x112b3e00 0 0x0100>;
> > > > + reg-names = "mac", "ippc";
> > >
> > > remove "mac"
> >
> > Will fix it in next version.
> >
>
> Dear Chunfeng,
>
> Unfortunately, if we remove "mac" register here for HOST only node
> like
> xhci3, the driver will complain about probing fail. Please check the
> following log.
My bad, do need it for host only mode, sorry
>
> => usb start
> starting USB...
> Bus xhci3@112b0000: xhci-mtk xhci3@112b0000: failed to get xHCI base
> address
> probe failed, error -6
> No working controllers found
>
> I'll add "mac" back to HOST only nodes.
>
> Thanks!
> Macpaul Lin
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v2 1/2] arm: mediatek: add mt8195 SOC support
2022-11-09 9:50 ` [PATCH v2 " Macpaul Lin
2022-11-09 9:50 ` [PATCH v2 2/2] board: mediatek: add mt8195 demo board Macpaul Lin
@ 2022-11-09 13:06 ` Chunfeng Yun (云春峰)
1 sibling, 0 replies; 23+ messages in thread
From: Chunfeng Yun (云春峰) @ 2022-11-09 13:06 UTC (permalink / raw)
To: fparent, marex, sjg, marcel.ziswiler, aouledameur,
frieder.schrempf, philippe.reynes, u-boot,
Macpaul Lin (林智斌),
GSS_MTK_Uboot_upstream, william.zhang, samuel, festevam,
Weijie Gao (高惟杰),
Ryder Lee, paul.liu
Cc: Miles Chen (陳民樺),
Bear Wang (萩原惟德),
macpaul, Pablo Sun (孫毓翔)
On Wed, 2022-11-09 at 17:50 +0800, Macpaul Lin wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73
> and
> a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and
> hosts,
> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
> and LPDDR4 options.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
>
> ---
> MAINTAINERS | 2 +
> arch/arm/dts/mt8195.dtsi | 370
> +++++++++++++++++++++++++
> arch/arm/mach-mediatek/Kconfig | 13 +-
> arch/arm/mach-mediatek/Makefile | 1 +
> arch/arm/mach-mediatek/mt8195/Makefile | 3 +
> arch/arm/mach-mediatek/mt8195/init.c | 81 ++++++
> 6 files changed, 469 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/mt8195.dtsi
> create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
> create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
>
> Changes for v2:
> - Correct node name to t-phy for u3phy0.
> - Add platform compatible string "mediatek,mt8195-tphy" to all usb
> phy nodes.
> - remove clock nodes that software cannot controlled in phy nodes.
> - Test and add back "mac" for HOST only xhci nodes.
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1cf99c1393..5528dd28c3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -362,8 +362,10 @@ ARM MEDIATEK
> M: Ryder Lee <ryder.lee@mediatek.com>
> M: Weijie Gao <weijie.gao@mediatek.com>
> M: Chunfeng Yun <chunfeng.yun@mediatek.com>
> +M: Macpaul Lin <macpaul.lin@mediatek.com>
> R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
> S: Maintained
> +F: arch/arm/dts/mt8195.dtsi
> F: arch/arm/mach-mediatek/
> F: arch/arm/include/asm/arch-mediatek/
> F: board/mediatek/
> diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
> new file mode 100644
> index 0000000000..33282d21d1
> --- /dev/null
> +++ b/arch/arm/dts/mt8195.dtsi
> @@ -0,0 +1,370 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + * Copyright (C) 2022 BayLibre, SAS
> + * Author: Ben Ho <ben.ho@mediatek.com>
> + * Erin Lo <erin.lo@mediatek.com>
> + * Fabien Parent <fparent@baylibre.com>
> + * Macpaul Lin <macpaul.lin@mediatek.com>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
> + compatible = "mediatek,mt8195";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu4>;
> + };
> + core1 {
> + cpu = <&cpu5>;
> + };
> + core2 {
> + cpu = <&cpu6>;
> + };
> + core3 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x000>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x001>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x002>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x003>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x100>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x101>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + cpu6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x102>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + cpu7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x103>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> + };
> +
> + clk26m: oscillator {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "clk26m";
> + };
> +
> + mmc_source_clk: mmc-source-clk{
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <400000000>;
> + clock-output-names = "mmc_source_clk";
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8195-wdt",
> + "mediatek,wdt";
> + reg = <0 0x10007000 0 0x100>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <4>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x40000>, /* GICD */
> + <0 0x0c100000 0 0x200000>, /* GICR */
> + <0 0x0c400000 0 0x2000>, /* GICC */
> + <0 0x0c410000 0 0x1000>, /* GICH */
> + <0 0x0c420000 0 0x2000>; /* GICV */
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> + ppi-partitions {
> + ppi_cluster0: interrupt-partition-0 {
> + affinity = <&cpu0 &cpu1 &cpu2
> &cpu3>;
> + };
> + ppi_cluster1: interrupt-partition-1 {
> + affinity = <&cpu4 &cpu5 &cpu6
> &cpu7>;
> + };
> + };
> + };
> +
> + sysirq: interrupt-controller@c530a80 {
> + compatible = "mediatek,mt8195-sysirq",
> + "mediatek,mt6577-sysirq";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x0c530a80 0 0x50>;
> + };
> +
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt8195-topckgen",
> "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon@10001000 {
> + compatible = "mediatek,mt8195-infracfg",
> "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + apmixedsys: syscon@1000c000 {
> + compatible = "mediatek,mt8195-apmixedsys",
> "syscon";
> + reg = <0 0x1000c000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + uart0: serial@11001100 {
> + compatible = "mediatek,mt8195-uart",
> + "mediatek,hsuart";
> + reg = <0 0x11001100 0 0x1000>;
> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <26000000>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8195-mmc",
> + "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11f50000 0 0x1000>;
> + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmc_source_clk>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + u3phy0: t-phy@11f40000 {
> + compatible = "mediatek,mt8195-tphy",
> "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11e40000 0xe00>;
> + status = "okay";
> +
> + u2port0: usb-phy@0 {
> + reg = <0 0x700>;
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port0: usb-phy@700 {
> + reg = <0x700 0x700>;
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> + usb: usb@11200000 {
> + compatible ="mediatek,mt8195-mtu3",
> "mediatek,mtu3";
> + reg = <0 0x11203e00 0 0x0100>;
> + reg-names = "ippc";
> + phys = <&u2port0 PHY_TYPE_USB2>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + ssusb: ssusb@11200000 {
> + compatible = "mediatek,ssusb";
> + reg = <0 0x11200000 0 0x3e00>;
> + reg-names = "mac";
> + interrupts = <GIC_SPI 128
> IRQ_TYPE_LEVEL_LOW>;
> + status = "disabled";
> + };
> +
> + xhci0: xhci@11200000 {
> + compatible = "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x1000>;
> + reg-names = "mac";
> + interrupts = <GIC_SPI 129
> IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "xhci_ck",
> "ref_ck", "mcu_ck";
> + status = "disabled";
> + };
> + };
> +
> + u3phy1: t-phy@11e30000 {
> + compatible = "mediatek,mt8195-tphy",
> "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11e30000 0xe00>;
> + status = "disabled";
> +
> + u2port1: usb-phy@0 {
> + reg = <0x0 0x700>;
> + #phy-cells = <1>;
> + };
> +
> + u3port1: usb-phy@700 {
> + reg = <0x700 0x700>;
> + #phy-cells = <1>;
> + };
> + };
> +
> + xhci1: xhci1@11290000 {
Prefer to use 'xchi' as node name, but it's ok to use 'xhci1' as a
label.
> + compatible = "mediatek,mt8195-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x11290000 0 0x1000>,
> + <0 0x11293e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&u2port1 PHY_TYPE_USB2>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck",
> "mcu_ck";
> + status = "disabled";
> + };
> +
> + u3phy2: t-phy@11c40000 {
> + compatible = "mediatek,mt8195-tphy",
> "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11c40000 0x700>;
> + status = "disabled";
> +
> + u2port2: usb-phy@0 {
> + reg = <0x0 0x700>;
> + #phy-cells = <1>;
> + };
> + };
> +
> + xhci2: xhci2@112a0000 {
xhci2: xhci@112a0000
> + compatible = "mediatek,mt8195-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x112a0000 0 0x1000>,
> + <0 0x112a3e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&u2port2 PHY_TYPE_USB2>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> + status = "disabled";
> + };
> +
> + u3phy3: t-phy@11c50000 {
> + compatible = "mediatek,mt8195-tphy",
> "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11c50000 0x700>;
> + status = "okay";
> +
> + u2port3: usb-phy@0 {
> + reg = <0x0 0x700>;
> + #phy-cells = <1>;
> + };
> + };
> +
> + xhci3: xhci3@112b0000 {
xhci3: xhci@112b0000
> + compatible = "mediatek,mt8195-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x112b0000 0 0x1000>,
> + <0 0x112b3e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&u2port3 PHY_TYPE_USB2>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> + usb2-lpm-disable;
> + status = "disabled";
> + };
> + };
> +};
> diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-
> mediatek/Kconfig
> index 04aa2fd97f..3a2af1cdee 100644
> --- a/arch/arm/mach-mediatek/Kconfig
> +++ b/arch/arm/mach-mediatek/Kconfig
> @@ -67,6 +67,15 @@ config TARGET_MT8183
> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
> LPDDR3
> and LPDDR4 options.
>
> +config TARGET_MT8195
> + bool "MediaTek MT8195 SoC"
> + select ARM64
> + help
> + The MediaTek MT8195 is a ARM64-based SoC with a quad-core
> Cortex-A73 and
> + a quad-core Cortex-A53. It is including UART, SPI, USB3.0
> device and hosts,
> + SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
> LPDDR3
> + and LPDDR4 options.
> +
> config TARGET_MT8512
> bool "MediaTek MT8512 M1 Board"
> select ARM64
> @@ -105,6 +114,7 @@ config SYS_BOARD
> default "mt7981" if TARGET_MT7981
> default "mt7986" if TARGET_MT7986
> default "mt8183" if TARGET_MT8183
> + default "mt8195" if TARGET_MT8195
> default "mt8512" if TARGET_MT8512
> default "mt8516" if TARGET_MT8516
> default "mt8518" if TARGET_MT8518
> @@ -122,6 +132,7 @@ config SYS_CONFIG_NAME
> default "mt7981" if TARGET_MT7981
> default "mt7986" if TARGET_MT7986
> default "mt8183" if TARGET_MT8183
> + default "mt8195" if TARGET_MT8195
> default "mt8512" if TARGET_MT8512
> default "mt8516" if TARGET_MT8516
> default "mt8518" if TARGET_MT8518
> @@ -134,7 +145,7 @@ config SYS_CONFIG_NAME
> config MTK_BROM_HEADER_INFO
> string
> default "media=nor" if TARGET_MT8518 || TARGET_MT8512 ||
> TARGET_MT7629 || TARGET_MT7622
> - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 ||
> TARGET_MT8183
> + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 ||
> TARGET_MT8183 || TARGET_MT8195
> default "media=snand;nandinfo=2k+64" if TARGET_MT7981 ||
> TARGET_MT7986
> default "lk=1" if TARGET_MT7623
>
> diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-
> mediatek/Makefile
> index fc85293f71..fbbb5431d1 100644
> --- a/arch/arm/mach-mediatek/Makefile
> +++ b/arch/arm/mach-mediatek/Makefile
> @@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/
> obj-$(CONFIG_TARGET_MT7981) += mt7981/
> obj-$(CONFIG_TARGET_MT7986) += mt7986/
> obj-$(CONFIG_TARGET_MT8183) += mt8183/
> +obj-$(CONFIG_TARGET_MT8195) += mt8195/
> obj-$(CONFIG_TARGET_MT8516) += mt8516/
> obj-$(CONFIG_TARGET_MT8518) += mt8518/
> diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-
> mediatek/mt8195/Makefile
> new file mode 100644
> index 0000000000..886ab7e4eb
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8195/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-y += init.o
> diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-
> mediatek/mt8195/init.c
> new file mode 100644
> index 0000000000..1eb4ade6c5
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8195/init.c
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + * Copyright (C) 2022 BayLibre, SAS
> + * Author: Macpaul Lin <macpaul.lin@mediatek.com>
> + * Author: Fabien Parent <fparent@baylibre.com>
> + */
> +
> +#include <clk.h>
> +#include <common.h>
> +#include <dm.h>
> +#include <fdtdec.h>
> +#include <ram.h>
> +#include <asm/arch/misc.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/sections.h>
> +#include <asm/system.h>
> +#include <dm/uclass.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + int ret;
> +
> + ret = fdtdec_setup_memory_banksize();
> + if (ret)
> + return ret;
> +
> + return fdtdec_setup_mem_size_base();
> +}
> +
> +int dram_init_banksize(void)
> +{
> + gd->bd->bi_dram[0].start = gd->ram_base;
> + gd->bd->bi_dram[0].size = gd->ram_size;
> +
> + return 0;
> +}
> +
> +int mtk_pll_early_init(void)
> +{
> + return 0;
> +}
> +
> +int mtk_soc_early_init(void)
> +{
> + return 0;
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> + psci_system_reset();
> +}
> +
> +int print_cpuinfo(void)
> +{
> + printf("CPU: MediaTek MT8195\n");
> + return 0;
> +}
> +
> +static struct mm_region mt8195_mem_map[] = {
> + {
> + /* DDR */
> + .virt = 0x40000000UL,
> + .phys = 0x40000000UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> PTE_BLOCK_OUTER_SHARE,
> + }, {
> + .virt = 0x00000000UL,
> + .phys = 0x00000000UL,
> + .size = 0x20000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = mt8195_mem_map;
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support
2022-11-09 7:10 ` Macpaul Lin
@ 2022-11-09 20:09 ` Pali Rohár
2022-11-09 21:12 ` Tom Rini
0 siblings, 1 reply; 23+ messages in thread
From: Pali Rohár @ 2022-11-09 20:09 UTC (permalink / raw)
To: Macpaul Lin, Tom Rini; +Cc: u-boot
+ Tom
- all
On Wednesday 09 November 2022 15:10:59 Macpaul Lin wrote:
> On 11/8/22 15:57, Pali Rohár wrote:
> > Hello! I'm not mediatek maintainer and if this patch series is not
> > something important for me which should I review then please do not send
> > me lot of these emails... As I would have time to review stuff which are
> > important.
>
> I'm so sorry for bothering you and other developers.
> I've used ./scripts/get_maintainer.pl to check these 2 patches and found you
> all in the suggestion list.
>
> Result:
> "Pali Rohár" <pali@kernel.org>
> (added_lines:16/253=6%,removed_lines:12/76=16%)
>
> I'll remove Pali when I send next version.
> Who else don't want to be involved in these reviewing activities of MediaTek
> platforms, please let us know.
>
> [deleted]
>
> Thanks!
> Macpaul Lin
I think that this is improper configuration of that get_maintainer.pl
script. As it currently spams tons of people. And it is not really a
good idea to spam people about unrelated stuff. Tom, could you do
something with it?
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support
2022-11-09 20:09 ` Pali Rohár
@ 2022-11-09 21:12 ` Tom Rini
0 siblings, 0 replies; 23+ messages in thread
From: Tom Rini @ 2022-11-09 21:12 UTC (permalink / raw)
To: Pali Rohár; +Cc: Macpaul Lin, u-boot
[-- Attachment #1: Type: text/plain, Size: 1402 bytes --]
On Wed, Nov 09, 2022 at 09:09:28PM +0100, Pali Rohár wrote:
> + Tom
> - all
>
> On Wednesday 09 November 2022 15:10:59 Macpaul Lin wrote:
> > On 11/8/22 15:57, Pali Rohár wrote:
> > > Hello! I'm not mediatek maintainer and if this patch series is not
> > > something important for me which should I review then please do not send
> > > me lot of these emails... As I would have time to review stuff which are
> > > important.
> >
> > I'm so sorry for bothering you and other developers.
> > I've used ./scripts/get_maintainer.pl to check these 2 patches and found you
> > all in the suggestion list.
> >
> > Result:
> > "Pali Rohár" <pali@kernel.org>
> > (added_lines:16/253=6%,removed_lines:12/76=16%)
> >
> > I'll remove Pali when I send next version.
> > Who else don't want to be involved in these reviewing activities of MediaTek
> > platforms, please let us know.
> >
> > [deleted]
> >
> > Thanks!
> > Macpaul Lin
>
> I think that this is improper configuration of that get_maintainer.pl
> script. As it currently spams tons of people. And it is not really a
> good idea to spam people about unrelated stuff. Tom, could you do
> something with it?
I've been waiting for someone to submit a patch to tweak
.get_maintainers.conf based on what I think Sean suggested last time.
But in this case I'm not even sure what file was suggesting you.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 1/2] arm: mediatek: add mt8195 SOC support
2022-11-08 3:21 [PATCH 1/2] arm: mediatek: add mt8195 SOC support Macpaul Lin
` (3 preceding siblings ...)
2022-11-09 9:50 ` [PATCH v2 " Macpaul Lin
@ 2022-11-10 7:34 ` Macpaul Lin
2022-11-10 7:34 ` [PATCH v3 2/2] board: mediatek: add mt8195 demo board Macpaul Lin
2022-11-10 13:50 ` [PATCH v3 1/2] arm: mediatek: add mt8195 SOC support Chunfeng Yun (云春峰)
2022-12-19 6:43 ` [PATCH v4 " Macpaul Lin
5 siblings, 2 replies; 23+ messages in thread
From: Macpaul Lin @ 2022-11-10 7:34 UTC (permalink / raw)
To: Chunfeng Yun, fparent @ baylibre . com, marex @ denx . de,
sjg @ chromium . org, marcel . ziswiler @ toradex . com,
aouledameur @ baylibre . com, frieder . schrempf @ kontron . de,
philippe . reynes @ softathome . com, u-boot @ lists . denx . de,
GSS_MTK_Uboot_upstream, william . zhang @ broadcom . com,
samuel @ sholland . org, festevam @ denx . de, Weijie Gao,
Ryder Lee, paul . liu @ linaro . org
Cc: Miles Chen, Bear Wang, Pablo Sun, Macpaul Lin, Macpaul Lin
From: Fabien Parent <fparent@baylibre.com>
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
MAINTAINERS | 2 +
arch/arm/dts/mt8195.dtsi | 370 +++++++++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8195/Makefile | 3 +
arch/arm/mach-mediatek/mt8195/init.c | 81 ++++++
6 files changed, 469 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8195.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
Changes for v2:
- Correct node name to t-phy for u3phy0.
- Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes.
- remove clock nodes that software cannot controlled in phy nodes.
- Test and add back "mac" for HOST only xhci nodes.
Changes for v3:
- Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".
diff --git a/MAINTAINERS b/MAINTAINERS
index 1cf99c1393..5528dd28c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -362,8 +362,10 @@ ARM MEDIATEK
M: Ryder Lee <ryder.lee@mediatek.com>
M: Weijie Gao <weijie.gao@mediatek.com>
M: Chunfeng Yun <chunfeng.yun@mediatek.com>
+M: Macpaul Lin <macpaul.lin@mediatek.com>
R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
S: Maintained
+F: arch/arm/dts/mt8195.dtsi
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
F: board/mediatek/
diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
new file mode 100644
index 0000000000..33282d21d1
--- /dev/null
+++ b/arch/arm/dts/mt8195.dtsi
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Ben Ho <ben.ho@mediatek.com>
+ * Erin Lo <erin.lo@mediatek.com>
+ * Fabien Parent <fparent@baylibre.com>
+ * Macpaul Lin <macpaul.lin@mediatek.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x101>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x102>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x103>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+ };
+
+ clk26m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ mmc_source_clk: mmc-source-clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ clock-output-names = "mmc_source_clk";
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8195-wdt",
+ "mediatek,wdt";
+ reg = <0 0x10007000 0 0x100>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c100000 0 0x200000>, /* GICR */
+ <0 0x0c400000 0 0x2000>, /* GICC */
+ <0 0x0c410000 0 0x1000>, /* GICH */
+ <0 0x0c420000 0 0x2000>; /* GICV */
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+ };
+ };
+
+ sysirq: interrupt-controller@c530a80 {
+ compatible = "mediatek,mt8195-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x0c530a80 0 0x50>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8195-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8195-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8195-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@11001100 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,hsuart";
+ reg = <0 0x11001100 0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <26000000>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmc_source_clk>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ u3phy0: t-phy@11f40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e40000 0xe00>;
+ status = "okay";
+
+ u2port0: usb-phy@0 {
+ reg = <0 0x700>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x700>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ usb: usb@11200000 {
+ compatible ="mediatek,mt8195-mtu3", "mediatek,mtu3";
+ reg = <0 0x11203e00 0 0x0100>;
+ reg-names = "ippc";
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ ssusb: ssusb@11200000 {
+ compatible = "mediatek,ssusb";
+ reg = <0 0x11200000 0 0x3e00>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
+ status = "disabled";
+ };
+
+ xhci0: xhci@11200000 {
+ compatible = "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
+ status = "disabled";
+ };
+ };
+
+ u3phy1: t-phy@11e30000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e30000 0xe00>;
+ status = "disabled";
+
+ u2port1: usb-phy@0 {
+ reg = <0x0 0x700>;
+ #phy-cells = <1>;
+ };
+
+ u3port1: usb-phy@700 {
+ reg = <0x700 0x700>;
+ #phy-cells = <1>;
+ };
+ };
+
+ xhci1: xhci@11290000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11290000 0 0x1000>,
+ <0 0x11293e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port1 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
+ status = "disabled";
+ };
+
+ u3phy2: t-phy@11c40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c40000 0x700>;
+ status = "disabled";
+
+ u2port2: usb-phy@0 {
+ reg = <0x0 0x700>;
+ #phy-cells = <1>;
+ };
+ };
+
+ xhci2: xhci@112a0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112a0000 0 0x1000>,
+ <0 0x112a3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ status = "disabled";
+ };
+
+ u3phy3: t-phy@11c50000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c50000 0x700>;
+ status = "okay";
+
+ u2port3: usb-phy@0 {
+ reg = <0x0 0x700>;
+ #phy-cells = <1>;
+ };
+ };
+
+ xhci3: xhci@112b0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112b0000 0 0x1000>,
+ <0 0x112b3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port3 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ usb2-lpm-disable;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 04aa2fd97f..3a2af1cdee 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -67,6 +67,15 @@ config TARGET_MT8183
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
+config TARGET_MT8195
+ bool "MediaTek MT8195 SoC"
+ select ARM64
+ help
+ The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
+ a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
+ SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
+ and LPDDR4 options.
+
config TARGET_MT8512
bool "MediaTek MT8512 M1 Board"
select ARM64
@@ -105,6 +114,7 @@ config SYS_BOARD
default "mt7981" if TARGET_MT7981
default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
+ default "mt8195" if TARGET_MT8195
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518
@@ -122,6 +132,7 @@ config SYS_CONFIG_NAME
default "mt7981" if TARGET_MT7981
default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
+ default "mt8195" if TARGET_MT8195
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518
@@ -134,7 +145,7 @@ config SYS_CONFIG_NAME
config MTK_BROM_HEADER_INFO
string
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
- default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
+ default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8195
default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
default "lk=1" if TARGET_MT7623
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index fc85293f71..fbbb5431d1 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/
obj-$(CONFIG_TARGET_MT7981) += mt7981/
obj-$(CONFIG_TARGET_MT7986) += mt7986/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
+obj-$(CONFIG_TARGET_MT8195) += mt8195/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-mediatek/mt8195/Makefile
new file mode 100644
index 0000000000..886ab7e4eb
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8195/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c
new file mode 100644
index 0000000000..1eb4ade6c5
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8195/init.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Macpaul Lin <macpaul.lin@mediatek.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <asm/system.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+int mtk_pll_early_init(void)
+{
+ return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT8195\n");
+ return 0;
+}
+
+static struct mm_region mt8195_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mt8195_mem_map;
--
2.18.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 2/2] board: mediatek: add mt8195 demo board
2022-11-10 7:34 ` [PATCH v3 " Macpaul Lin
@ 2022-11-10 7:34 ` Macpaul Lin
2022-12-12 16:53 ` Tom Rini
2022-11-10 13:50 ` [PATCH v3 1/2] arm: mediatek: add mt8195 SOC support Chunfeng Yun (云春峰)
1 sibling, 1 reply; 23+ messages in thread
From: Macpaul Lin @ 2022-11-10 7:34 UTC (permalink / raw)
To: Chunfeng Yun, fparent @ baylibre . com, marex @ denx . de,
sjg @ chromium . org, marcel . ziswiler @ toradex . com,
aouledameur @ baylibre . com, frieder . schrempf @ kontron . de,
philippe . reynes @ softathome . com, u-boot @ lists . denx . de,
GSS_MTK_Uboot_upstream, william . zhang @ broadcom . com,
samuel @ sholland . org, festevam @ denx . de, Weijie Gao,
Ryder Lee, paul . liu @ linaro . org
Cc: Miles Chen, Bear Wang, Pablo Sun, Macpaul Lin, Macpaul Lin
From: Fabien Parent <fparent@baylibre.com>
Add mt8195-demo board support.
This demo purpose board uses MediaTek's MT8195 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
MAINTAINERS | 1 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt8195-demo.dts | 109 ++++++++++++++++++++++++++++
board/mediatek/mt8195/MAINTAINERS | 6 ++
board/mediatek/mt8195/Makefile | 3 +
board/mediatek/mt8195/mt8195_demo.c | 38 ++++++++++
configs/mt8195_demo_defconfig | 89 +++++++++++++++++++++++
include/configs/mt8195.h | 34 +++++++++
8 files changed, 281 insertions(+)
create mode 100644 arch/arm/dts/mt8195-demo.dts
create mode 100644 board/mediatek/mt8195/MAINTAINERS
create mode 100644 board/mediatek/mt8195/Makefile
create mode 100644 board/mediatek/mt8195/mt8195_demo.c
create mode 100644 configs/mt8195_demo_defconfig
create mode 100644 include/configs/mt8195.h
Changes for v2 and v3:
- no change.
diff --git a/MAINTAINERS b/MAINTAINERS
index 5528dd28c3..5aaeeb02cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -389,6 +389,7 @@ F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
+F: include/configs/mt8195.h
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 791838733c..994f7ebcc0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1271,6 +1271,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7986a-emmc-rfb.dtb \
mt7986b-emmc-rfb.dtb \
mt8183-pumpkin.dtb \
+ mt8195-demo.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
diff --git a/arch/arm/dts/mt8195-demo.dts b/arch/arm/dts/mt8195-demo.dts
new file mode 100644
index 0000000000..bd0952b248
--- /dev/null
+++ b/arch/arm/dts/mt8195-demo.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre SAS.
+ * Author: Macpaul Lin <macpaul.lin@mediatek.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include <config.h>
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 demo board";
+ compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@54600000 {
+ no-map;
+ reg = <0 0x54600000 0x0 0x200000>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&ssusb {
+ mediatek,force-vbus;
+ maximum-speed = "high-speed";
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci3 {
+ status = "okay";
+};
diff --git a/board/mediatek/mt8195/MAINTAINERS b/board/mediatek/mt8195/MAINTAINERS
new file mode 100644
index 0000000000..01fa25115d
--- /dev/null
+++ b/board/mediatek/mt8195/MAINTAINERS
@@ -0,0 +1,6 @@
+MT8195 Demo
+M: Macpaul Lin <macpaul.lin@mediatek.com>
+S: Maintained
+F: board/mediatek/mt8195
+F: include/configs/mt8195.h
+F: configs/mt8195_demo_defconfig
diff --git a/board/mediatek/mt8195/Makefile b/board/mediatek/mt8195/Makefile
new file mode 100644
index 0000000000..7e94a87aea
--- /dev/null
+++ b/board/mediatek/mt8195/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += mt8195_demo.o
diff --git a/board/mediatek/mt8195/mt8195_demo.c b/board/mediatek/mt8195/mt8195_demo.c
new file mode 100644
index 0000000000..b95f5cf28d
--- /dev/null
+++ b/board/mediatek/mt8195/mt8195_demo.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BayLibre SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+#include <asm/io.h>
+
+int board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (CONFIG_IS_ENABLED(USB_GADGET)) {
+ ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
+ if (ret) {
+ pr_err("%s: Cannot find USB device\n", __func__);
+ return ret;
+ }
+ }
+
+ if (CONFIG_IS_ENABLED(USB_ETHER))
+ usb_ether_init();
+
+ printf("Disabling WDT\n");
+ writel(0, 0x10007000);
+
+ printf("Enabling SCP SRAM\n");
+ for (unsigned int val = 0xFFFFFFFF; val != 0U;) {
+ val = val >> 1;
+ writel(val, 0x1072102C);
+ }
+
+ return 0;
+}
diff --git a/configs/mt8195_demo_defconfig b/configs/mt8195_demo_defconfig
new file mode 100644
index 0000000000..5b075b1a27
--- /dev/null
+++ b/configs/mt8195_demo_defconfig
@@ -0,0 +1,89 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=13000000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x0
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="mt8195-demo"
+CONFIG_TARGET_MT8195=y
+CONFIG_DEBUG_UART_BASE=0x11001100
+CONFIG_DEBUG_UART_CLOCK=26000000
+# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x4c000000
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="mt8195-demo"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_MEMORY is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_BLOCK_CACHE is not set
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_ENV_IMPORT_FDT=y
+CONFIG_DEVRES=y
+CONFIG_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x4d000000
+CONFIG_FASTBOOT_BUF_SIZE=0x8000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+# CONFIG_INPUT is not set
+# CONFIG_MMC_QUIRKS is not set
+CONFIG_MMC_MTK=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_BAUDRATE=921600
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_MTK_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_MTU3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d
+CONFIG_USB_GADGET_PRODUCT_NUM=0x201c
+CONFIG_USB_ETHER=y
+CONFIG_WDT=y
+CONFIG_WDT_MTK=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/include/configs/mt8195.h b/include/configs/mt8195.h
new file mode 100644
index 0000000000..22bcf87794
--- /dev/null
+++ b/include/configs/mt8195.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for MT8195 based boards
+ *
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Fabien Parent <macpaul.lin@mediatek.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#ifndef __MT8195_H
+#define __MT8195_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_COM1 0x11002000
+#define CONFIG_SYS_NS16550_CLK 26000000
+
+/* Environment settings */
+#include <config_distro_bootcmd.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
+
+#if !defined(CONFIG_EXTRA_ENV_SETTINGS)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0x40000000\0" \
+ BOOTENV
+#endif
+
+#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v3 1/2] arm: mediatek: add mt8195 SOC support
2022-11-10 7:34 ` [PATCH v3 " Macpaul Lin
2022-11-10 7:34 ` [PATCH v3 2/2] board: mediatek: add mt8195 demo board Macpaul Lin
@ 2022-11-10 13:50 ` Chunfeng Yun (云春峰)
1 sibling, 0 replies; 23+ messages in thread
From: Chunfeng Yun (云春峰) @ 2022-11-10 13:50 UTC (permalink / raw)
To: fparent, marex, sjg, marcel.ziswiler, aouledameur,
frieder.schrempf, philippe.reynes, u-boot,
Macpaul Lin (林智斌),
GSS_MTK_Uboot_upstream, william.zhang, samuel, festevam,
Weijie Gao (高惟杰),
Ryder Lee, paul.liu
Cc: Miles Chen (陳民樺),
Bear Wang (萩原惟德),
macpaul, Pablo Sun (孫毓翔)
On Thu, 2022-11-10 at 15:34 +0800, Macpaul Lin wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73
> and
> a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and
> hosts,
> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
> and LPDDR4 options.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
>
> ---
> MAINTAINERS | 2 +
> arch/arm/dts/mt8195.dtsi | 370
> +++++++++++++++++++++++++
> arch/arm/mach-mediatek/Kconfig | 13 +-
> arch/arm/mach-mediatek/Makefile | 1 +
> arch/arm/mach-mediatek/mt8195/Makefile | 3 +
> arch/arm/mach-mediatek/mt8195/init.c | 81 ++++++
> 6 files changed, 469 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/mt8195.dtsi
> create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
> create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
>
> Changes for v2:
> - Correct node name to t-phy for u3phy0.
> - Add platform compatible string "mediatek,mt8195-tphy" to all usb
> phy nodes.
> - remove clock nodes that software cannot controlled in phy nodes.
> - Test and add back "mac" for HOST only xhci nodes.
>
> Changes for v3:
> - Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1cf99c1393..5528dd28c3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -362,8 +362,10 @@ ARM MEDIATEK
> M: Ryder Lee <ryder.lee@mediatek.com>
> M: Weijie Gao <weijie.gao@mediatek.com>
> M: Chunfeng Yun <chunfeng.yun@mediatek.com>
> +M: Macpaul Lin <macpaul.lin@mediatek.com>
> R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
> S: Maintained
> +F: arch/arm/dts/mt8195.dtsi
> F: arch/arm/mach-mediatek/
> F: arch/arm/include/asm/arch-mediatek/
> F: board/mediatek/
> diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
> new file mode 100644
> index 0000000000..33282d21d1
> --- /dev/null
> +++ b/arch/arm/dts/mt8195.dtsi
> @@ -0,0 +1,370 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + * Copyright (C) 2022 BayLibre, SAS
> + * Author: Ben Ho <ben.ho@mediatek.com>
> + * Erin Lo <erin.lo@mediatek.com>
> + * Fabien Parent <fparent@baylibre.com>
> + * Macpaul Lin <macpaul.lin@mediatek.com>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/phy/phy.h>
> +
> +/ {
> + compatible = "mediatek,mt8195";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu4>;
> + };
> + core1 {
> + cpu = <&cpu5>;
> + };
> + core2 {
> + cpu = <&cpu6>;
> + };
> + core3 {
> + cpu = <&cpu7>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x000>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x001>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x002>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x003>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <741>;
> + };
> +
> + cpu4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x100>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + cpu5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x101>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + cpu6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x102>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> +
> + cpu7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a73";
> + reg = <0x103>;
> + enable-method = "psci";
> + capacity-dmips-mhz = <1024>;
> + };
> + };
> +
> + clk26m: oscillator {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "clk26m";
> + };
> +
> + mmc_source_clk: mmc-source-clk{
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <400000000>;
> + clock-output-names = "mmc_source_clk";
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8195-wdt",
> + "mediatek,wdt";
> + reg = <0 0x10007000 0 0x100>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <4>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x40000>, /* GICD */
> + <0 0x0c100000 0 0x200000>, /* GICR */
> + <0 0x0c400000 0 0x2000>, /* GICC */
> + <0 0x0c410000 0 0x1000>, /* GICH */
> + <0 0x0c420000 0 0x2000>; /* GICV */
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> + ppi-partitions {
> + ppi_cluster0: interrupt-partition-0 {
> + affinity = <&cpu0 &cpu1 &cpu2
> &cpu3>;
> + };
> + ppi_cluster1: interrupt-partition-1 {
> + affinity = <&cpu4 &cpu5 &cpu6
> &cpu7>;
> + };
> + };
> + };
> +
> + sysirq: interrupt-controller@c530a80 {
> + compatible = "mediatek,mt8195-sysirq",
> + "mediatek,mt6577-sysirq";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x0c530a80 0 0x50>;
> + };
> +
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt8195-topckgen",
> "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon@10001000 {
> + compatible = "mediatek,mt8195-infracfg",
> "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + apmixedsys: syscon@1000c000 {
> + compatible = "mediatek,mt8195-apmixedsys",
> "syscon";
> + reg = <0 0x1000c000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + uart0: serial@11001100 {
> + compatible = "mediatek,mt8195-uart",
> + "mediatek,hsuart";
> + reg = <0 0x11001100 0 0x1000>;
> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
> + clock-frequency = <26000000>;
> + clocks = <&clk26m>, <&clk26m>;
> + clock-names = "baud", "bus";
> + status = "disabled";
> + };
> +
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8195-mmc",
> + "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11f50000 0 0x1000>;
> + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmc_source_clk>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + u3phy0: t-phy@11f40000 {
> + compatible = "mediatek,mt8195-tphy",
> "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11e40000 0xe00>;
> + status = "okay";
> +
> + u2port0: usb-phy@0 {
> + reg = <0 0x700>;
> + #phy-cells = <1>;
> + status = "okay";
> + };
> +
> + u3port0: usb-phy@700 {
> + reg = <0x700 0x700>;
> + #phy-cells = <1>;
> + status = "okay";
> + };
> + };
> +
> + usb: usb@11200000 {
> + compatible ="mediatek,mt8195-mtu3",
> "mediatek,mtu3";
> + reg = <0 0x11203e00 0 0x0100>;
> + reg-names = "ippc";
> + phys = <&u2port0 PHY_TYPE_USB2>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + ssusb: ssusb@11200000 {
> + compatible = "mediatek,ssusb";
> + reg = <0 0x11200000 0 0x3e00>;
> + reg-names = "mac";
> + interrupts = <GIC_SPI 128
> IRQ_TYPE_LEVEL_LOW>;
> + status = "disabled";
> + };
> +
> + xhci0: xhci@11200000 {
> + compatible = "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x1000>;
> + reg-names = "mac";
> + interrupts = <GIC_SPI 129
> IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "xhci_ck",
> "ref_ck", "mcu_ck";
> + status = "disabled";
> + };
> + };
> +
> + u3phy1: t-phy@11e30000 {
> + compatible = "mediatek,mt8195-tphy",
> "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11e30000 0xe00>;
> + status = "disabled";
> +
> + u2port1: usb-phy@0 {
> + reg = <0x0 0x700>;
> + #phy-cells = <1>;
> + };
> +
> + u3port1: usb-phy@700 {
> + reg = <0x700 0x700>;
> + #phy-cells = <1>;
> + };
> + };
> +
> + xhci1: xhci@11290000 {
> + compatible = "mediatek,mt8195-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x11290000 0 0x1000>,
> + <0 0x11293e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&u2port1 PHY_TYPE_USB2>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck",
> "mcu_ck";
> + status = "disabled";
> + };
> +
> + u3phy2: t-phy@11c40000 {
> + compatible = "mediatek,mt8195-tphy",
> "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11c40000 0x700>;
> + status = "disabled";
> +
> + u2port2: usb-phy@0 {
> + reg = <0x0 0x700>;
> + #phy-cells = <1>;
> + };
> + };
> +
> + xhci2: xhci@112a0000 {
> + compatible = "mediatek,mt8195-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x112a0000 0 0x1000>,
> + <0 0x112a3e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&u2port2 PHY_TYPE_USB2>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> + status = "disabled";
> + };
> +
> + u3phy3: t-phy@11c50000 {
> + compatible = "mediatek,mt8195-tphy",
> "mediatek,generic-tphy-v2";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x11c50000 0x700>;
> + status = "okay";
> +
> + u2port3: usb-phy@0 {
> + reg = <0x0 0x700>;
> + #phy-cells = <1>;
> + };
> + };
> +
> + xhci3: xhci@112b0000 {
> + compatible = "mediatek,mt8195-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x112b0000 0 0x1000>,
> + <0 0x112b3e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&u2port3 PHY_TYPE_USB2>;
> + clocks = <&clk26m>,
> + <&clk26m>,
> + <&clk26m>;
> + clock-names = "sys_ck", "xhci_ck", "ref_ck";
> + usb2-lpm-disable;
> + status = "disabled";
> + };
> + };
> +};
For usb part:
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Thanks a lot
> diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-
> mediatek/Kconfig
> index 04aa2fd97f..3a2af1cdee 100644
> --- a/arch/arm/mach-mediatek/Kconfig
> +++ b/arch/arm/mach-mediatek/Kconfig
> @@ -67,6 +67,15 @@ config TARGET_MT8183
> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
> LPDDR3
> and LPDDR4 options.
>
> +config TARGET_MT8195
> + bool "MediaTek MT8195 SoC"
> + select ARM64
> + help
> + The MediaTek MT8195 is a ARM64-based SoC with a quad-core
> Cortex-A73 and
> + a quad-core Cortex-A53. It is including UART, SPI, USB3.0
> device and hosts,
> + SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
> LPDDR3
> + and LPDDR4 options.
> +
> config TARGET_MT8512
> bool "MediaTek MT8512 M1 Board"
> select ARM64
> @@ -105,6 +114,7 @@ config SYS_BOARD
> default "mt7981" if TARGET_MT7981
> default "mt7986" if TARGET_MT7986
> default "mt8183" if TARGET_MT8183
> + default "mt8195" if TARGET_MT8195
> default "mt8512" if TARGET_MT8512
> default "mt8516" if TARGET_MT8516
> default "mt8518" if TARGET_MT8518
> @@ -122,6 +132,7 @@ config SYS_CONFIG_NAME
> default "mt7981" if TARGET_MT7981
> default "mt7986" if TARGET_MT7986
> default "mt8183" if TARGET_MT8183
> + default "mt8195" if TARGET_MT8195
> default "mt8512" if TARGET_MT8512
> default "mt8516" if TARGET_MT8516
> default "mt8518" if TARGET_MT8518
> @@ -134,7 +145,7 @@ config SYS_CONFIG_NAME
> config MTK_BROM_HEADER_INFO
> string
> default "media=nor" if TARGET_MT8518 || TARGET_MT8512 ||
> TARGET_MT7629 || TARGET_MT7622
> - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 ||
> TARGET_MT8183
> + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 ||
> TARGET_MT8183 || TARGET_MT8195
> default "media=snand;nandinfo=2k+64" if TARGET_MT7981 ||
> TARGET_MT7986
> default "lk=1" if TARGET_MT7623
>
> diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-
> mediatek/Makefile
> index fc85293f71..fbbb5431d1 100644
> --- a/arch/arm/mach-mediatek/Makefile
> +++ b/arch/arm/mach-mediatek/Makefile
> @@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/
> obj-$(CONFIG_TARGET_MT7981) += mt7981/
> obj-$(CONFIG_TARGET_MT7986) += mt7986/
> obj-$(CONFIG_TARGET_MT8183) += mt8183/
> +obj-$(CONFIG_TARGET_MT8195) += mt8195/
> obj-$(CONFIG_TARGET_MT8516) += mt8516/
> obj-$(CONFIG_TARGET_MT8518) += mt8518/
> diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-
> mediatek/mt8195/Makefile
> new file mode 100644
> index 0000000000..886ab7e4eb
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8195/Makefile
> @@ -0,0 +1,3 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-y += init.o
> diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-
> mediatek/mt8195/init.c
> new file mode 100644
> index 0000000000..1eb4ade6c5
> --- /dev/null
> +++ b/arch/arm/mach-mediatek/mt8195/init.c
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + * Copyright (C) 2022 BayLibre, SAS
> + * Author: Macpaul Lin <macpaul.lin@mediatek.com>
> + * Author: Fabien Parent <fparent@baylibre.com>
> + */
> +
> +#include <clk.h>
> +#include <common.h>
> +#include <dm.h>
> +#include <fdtdec.h>
> +#include <ram.h>
> +#include <asm/arch/misc.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/sections.h>
> +#include <asm/system.h>
> +#include <dm/uclass.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + int ret;
> +
> + ret = fdtdec_setup_memory_banksize();
> + if (ret)
> + return ret;
> +
> + return fdtdec_setup_mem_size_base();
> +}
> +
> +int dram_init_banksize(void)
> +{
> + gd->bd->bi_dram[0].start = gd->ram_base;
> + gd->bd->bi_dram[0].size = gd->ram_size;
> +
> + return 0;
> +}
> +
> +int mtk_pll_early_init(void)
> +{
> + return 0;
> +}
> +
> +int mtk_soc_early_init(void)
> +{
> + return 0;
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> + psci_system_reset();
> +}
> +
> +int print_cpuinfo(void)
> +{
> + printf("CPU: MediaTek MT8195\n");
> + return 0;
> +}
> +
> +static struct mm_region mt8195_mem_map[] = {
> + {
> + /* DDR */
> + .virt = 0x40000000UL,
> + .phys = 0x40000000UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> PTE_BLOCK_OUTER_SHARE,
> + }, {
> + .virt = 0x00000000UL,
> + .phys = 0x00000000UL,
> + .size = 0x20000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = mt8195_mem_map;
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/2] board: mediatek: add mt8195 demo board
2022-11-10 7:34 ` [PATCH v3 2/2] board: mediatek: add mt8195 demo board Macpaul Lin
@ 2022-12-12 16:53 ` Tom Rini
2022-12-12 18:53 ` Tom Rini
0 siblings, 1 reply; 23+ messages in thread
From: Tom Rini @ 2022-12-12 16:53 UTC (permalink / raw)
To: Macpaul Lin
Cc: Chunfeng Yun, fparent @ baylibre . com, marex @ denx . de,
sjg @ chromium . org, marcel . ziswiler @ toradex . com,
aouledameur @ baylibre . com, frieder . schrempf @ kontron . de,
philippe . reynes @ softathome . com, u-boot @ lists . denx . de,
GSS_MTK_Uboot_upstream, william . zhang @ broadcom . com,
samuel @ sholland . org, festevam @ denx . de, Weijie Gao,
Ryder Lee, paul . liu @ linaro . org, Miles Chen, Bear Wang,
Pablo Sun, Macpaul Lin
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On Thu, Nov 10, 2022 at 03:34:53PM +0800, Macpaul Lin wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add mt8195-demo board support.
> This demo purpose board uses MediaTek's MT8195 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
[snip]
> +#include <linux/sizes.h>
> +
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE -4
> +#define CONFIG_SYS_NS16550_MEM32
> +#define CONFIG_SYS_NS16550_COM1 0x11002000
> +#define CONFIG_SYS_NS16550_CLK 26000000
This is unused, I believe. But when trying to build with current next I
get:
Error: Load Address must be set.
Error: Bad parameters for image type
Please rebase on top of current next and repost, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/2] board: mediatek: add mt8195 demo board
2022-12-12 16:53 ` Tom Rini
@ 2022-12-12 18:53 ` Tom Rini
2022-12-12 19:02 ` Tom Rini
0 siblings, 1 reply; 23+ messages in thread
From: Tom Rini @ 2022-12-12 18:53 UTC (permalink / raw)
To: Macpaul Lin
Cc: Chunfeng Yun, fparent @ baylibre . com, marex @ denx . de,
sjg @ chromium . org, marcel . ziswiler @ toradex . com,
aouledameur @ baylibre . com, frieder . schrempf @ kontron . de,
philippe . reynes @ softathome . com, u-boot @ lists . denx . de,
GSS_MTK_Uboot_upstream, william . zhang @ broadcom . com,
samuel @ sholland . org, festevam @ denx . de, Weijie Gao,
Ryder Lee, paul . liu @ linaro . org, Miles Chen, Bear Wang,
Pablo Sun, Macpaul Lin
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On Mon, Dec 12, 2022 at 11:53:04AM -0500, Tom Rini wrote:
> On Thu, Nov 10, 2022 at 03:34:53PM +0800, Macpaul Lin wrote:
>
> > From: Fabien Parent <fparent@baylibre.com>
> >
> > Add mt8195-demo board support.
> > This demo purpose board uses MediaTek's MT8195 SoC.
> >
> > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
> > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> [snip]
> > +#include <linux/sizes.h>
> > +
> > +#define CONFIG_SYS_NS16550_SERIAL
> > +#define CONFIG_SYS_NS16550_REG_SIZE -4
> > +#define CONFIG_SYS_NS16550_MEM32
> > +#define CONFIG_SYS_NS16550_COM1 0x11002000
> > +#define CONFIG_SYS_NS16550_CLK 26000000
>
> This is unused, I believe. But when trying to build with current next I
> get:
> Error: Load Address must be set.
> Error: Bad parameters for image type
>
> Please rebase on top of current next and repost, thanks!
Sorry for the noise, this failed due to another patch that needs to be
reworked instead.
--
Tom
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/2] board: mediatek: add mt8195 demo board
2022-12-12 18:53 ` Tom Rini
@ 2022-12-12 19:02 ` Tom Rini
2022-12-19 3:36 ` Macpaul Lin
0 siblings, 1 reply; 23+ messages in thread
From: Tom Rini @ 2022-12-12 19:02 UTC (permalink / raw)
To: Macpaul Lin
Cc: Chunfeng Yun, fparent @ baylibre . com, marex @ denx . de,
sjg @ chromium . org, marcel . ziswiler @ toradex . com,
aouledameur @ baylibre . com, frieder . schrempf @ kontron . de,
philippe . reynes @ softathome . com, u-boot @ lists . denx . de,
GSS_MTK_Uboot_upstream, william . zhang @ broadcom . com,
samuel @ sholland . org, festevam @ denx . de, Weijie Gao,
Ryder Lee, paul . liu @ linaro . org, Miles Chen, Bear Wang,
Pablo Sun, Macpaul Lin
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On Mon, Dec 12, 2022 at 01:53:05PM -0500, Tom Rini wrote:
> On Mon, Dec 12, 2022 at 11:53:04AM -0500, Tom Rini wrote:
> > On Thu, Nov 10, 2022 at 03:34:53PM +0800, Macpaul Lin wrote:
> >
> > > From: Fabien Parent <fparent@baylibre.com>
> > >
> > > Add mt8195-demo board support.
> > > This demo purpose board uses MediaTek's MT8195 SoC.
> > >
> > > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > > Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
> > > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> > [snip]
> > > +#include <linux/sizes.h>
> > > +
> > > +#define CONFIG_SYS_NS16550_SERIAL
> > > +#define CONFIG_SYS_NS16550_REG_SIZE -4
> > > +#define CONFIG_SYS_NS16550_MEM32
> > > +#define CONFIG_SYS_NS16550_COM1 0x11002000
> > > +#define CONFIG_SYS_NS16550_CLK 26000000
> >
> > This is unused, I believe. But when trying to build with current next I
> > get:
> > Error: Load Address must be set.
> > Error: Bad parameters for image type
> >
> > Please rebase on top of current next and repost, thanks!
>
> Sorry for the noise, this failed due to another patch that needs to be
> reworked instead.
Welp, I should have finished my re-testing. The patch that broke
phycore-rk3288 and I assumed broke this platform too, did not break this
platform, there's still some other problem here.
--
Tom
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^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/2] board: mediatek: add mt8195 demo board
2022-12-12 19:02 ` Tom Rini
@ 2022-12-19 3:36 ` Macpaul Lin
2023-01-02 19:15 ` Tom Rini
0 siblings, 1 reply; 23+ messages in thread
From: Macpaul Lin @ 2022-12-19 3:36 UTC (permalink / raw)
To: Tom Rini
Cc: Chunfeng Yun, fparent @ baylibre . com, marex @ denx . de,
sjg @ chromium . org, marcel . ziswiler @ toradex . com,
aouledameur @ baylibre . com, frieder . schrempf @ kontron . de,
philippe . reynes @ softathome . com, u-boot @ lists . denx . de,
GSS_MTK_Uboot_upstream, william . zhang @ broadcom . com,
samuel @ sholland . org, festevam @ denx . de, Weijie Gao,
Ryder Lee, paul . liu @ linaro . org, Miles Chen, Bear Wang,
Pablo Sun, Macpaul Lin
On 12/13/22 03:02, Tom Rini wrote:
> On Mon, Dec 12, 2022 at 01:53:05PM -0500, Tom Rini wrote:
>> On Mon, Dec 12, 2022 at 11:53:04AM -0500, Tom Rini wrote:
>>> On Thu, Nov 10, 2022 at 03:34:53PM +0800, Macpaul Lin wrote:
>>>
>>>> From: Fabien Parent <fparent@baylibre.com>
>>>>
>>>> Add mt8195-demo board support.
>>>> This demo purpose board uses MediaTek's MT8195 SoC.
>>>>
>>>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>>>> Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
>>>> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
>>> [snip]
>>>> +#include <linux/sizes.h>
>>>> +
>>>> +#define CONFIG_SYS_NS16550_SERIAL
>>>> +#define CONFIG_SYS_NS16550_REG_SIZE -4
>>>> +#define CONFIG_SYS_NS16550_MEM32
>>>> +#define CONFIG_SYS_NS16550_COM1 0x11002000
>>>> +#define CONFIG_SYS_NS16550_CLK 26000000
>>>
>>> This is unused, I believe. But when trying to build with current next I
>>> get:
>>> Error: Load Address must be set.
>>> Error: Bad parameters for image type
>>>
>>> Please rebase on top of current next and repost, thanks!
Thanks for the information, will send patch v4 later.
>>
>> Sorry for the noise, this failed due to another patch that needs to be
>> reworked instead.
>
> Welp, I should have finished my re-testing. The patch that broke
> phycore-rk3288 and I assumed broke this platform too, did not break this
> platform, there's still some other problem here.
>
I've tested it on uboot/next and got the following result.
$ make ARCH=arm phycore-rk3288_defconfig
$ make ARCH=arm
scripts/kconfig/conf --syncconfig Kconfig
UPD include/config.h
CFG u-boot.cfg
GEN include/autoconf.mk
GEN include/autoconf.mk.dep
CFG spl/u-boot.cfg
GEN spl/include/autoconf.mk
UPD include/config/uboot.release
UPD include/generated/version_autogenerated.h
UPD include/generated/timestamp_autogenerated.h
UPD include/generated/dt.h
ENVC include/generated/env.txt
ENVP include/generated/env.in
ENVT include/generated/environment.h
CC lib/asm-offsets.s
cc1: error: bad value (‘generic-armv7-a’) for ‘-mtune=’ switch
cc1: note: valid arguments to ‘-mtune=’ switch are: nocona core2 nehalem
corei7 westmere sandybridge corei7-avx ivybridge core-avx-i haswell
core-avx2 broadwell skylake skylake-avx512 bonnell atom silvermont slm
knl intel x86-64 eden-x2 nano nano-1000 nano-2000 nano-3000 nano-x2
eden-x4 nano-x4 k8 k8-sse3 opteron opteron-sse3 athlon64 athlon64-sse3
athlon-fx amdfam10 barcelona bdver1 bdver2 bdver3 bdver4 znver1 btver1
btver2 generic
scripts/Makefile.build:147: recipe for target 'lib/asm-offsets.s' failed
make[1]: *** [lib/asm-offsets.s] Error 1
Makefile:1932: recipe for target 'prepare0' failed
make: *** [prepare0] Error 2
I'm not sure should I test it on custodian tree: arm/next, too. This
failure seems not related to the 2nd patch of mt8195-demo board.
Thanks
Macpaul Lin
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v4 1/2] arm: mediatek: add mt8195 SOC support
2022-11-08 3:21 [PATCH 1/2] arm: mediatek: add mt8195 SOC support Macpaul Lin
` (4 preceding siblings ...)
2022-11-10 7:34 ` [PATCH v3 " Macpaul Lin
@ 2022-12-19 6:43 ` Macpaul Lin
2022-12-19 6:43 ` [PATCH v4 2/2] board: mediatek: add mt8195 demo board Macpaul Lin
5 siblings, 1 reply; 23+ messages in thread
From: Macpaul Lin @ 2022-12-19 6:43 UTC (permalink / raw)
To: trini, fparent, marex, sjg, marcel.ziswiler, aouledameur,
frieder.schrempf, philippe.reynes, u-boot,
GSS_MTK_Uboot_upstream, william.zhang, samuel, festevam,
Weijie.Gao, Ryder.Lee, paul.liu
Cc: Bear Wang, Pablo Sun, Macpaul Lin, Macpaul Lin, Chunfeng Yun, Sam Shih
From: Fabien Parent <fparent@baylibre.com>
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
MAINTAINERS | 2 +
arch/arm/dts/mt8195.dtsi | 370 +++++++++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8195/Makefile | 3 +
arch/arm/mach-mediatek/mt8195/init.c | 81 ++++++
6 files changed, 469 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8195.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
Changes for v2:
- Correct node name to t-phy for u3phy0.
- Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes.
- remove clock nodes that software cannot controlled in phy nodes.
- Test and add back "mac" for HOST only xhci nodes.
Changes for v3:
- Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".
Changes for v4:
- No change.
diff --git a/MAINTAINERS b/MAINTAINERS
index 75b27bc1cc..f2fe78dfc7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -363,8 +363,10 @@ ARM MEDIATEK
M: Ryder Lee <ryder.lee@mediatek.com>
M: Weijie Gao <weijie.gao@mediatek.com>
M: Chunfeng Yun <chunfeng.yun@mediatek.com>
+M: Macpaul Lin <macpaul.lin@mediatek.com>
R: GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>
S: Maintained
+F: arch/arm/dts/mt8195.dtsi
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
F: board/mediatek/
diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
new file mode 100644
index 0000000000..bb6dead834
--- /dev/null
+++ b/arch/arm/dts/mt8195.dtsi
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Ben Ho <ben.ho@mediatek.com>
+ * Erin Lo <erin.lo@mediatek.com>
+ * Fabien Parent <fparent@baylibre.com>
+ * Macpaul Lin <macpaul.lin@mediatek.com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x101>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x102>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x103>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+ };
+
+ clk26m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ mmc_source_clk: mmc-source-clk{
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <400000000>;
+ clock-output-names = "mmc_source_clk";
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8195-wdt",
+ "mediatek,wdt";
+ reg = <0 0x10007000 0 0x100>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c100000 0 0x200000>, /* GICR */
+ <0 0x0c400000 0 0x2000>, /* GICC */
+ <0 0x0c410000 0 0x1000>, /* GICH */
+ <0 0x0c420000 0 0x2000>; /* GICV */
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+ };
+ };
+
+ sysirq: interrupt-controller@c530a80 {
+ compatible = "mediatek,mt8195-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x0c530a80 0 0x50>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8195-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8195-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8195-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@11001100 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,hsuart";
+ reg = <0 0x11001100 0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clock-frequency = <26000000>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmc_source_clk>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ u3phy0: t-phy@11f40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e40000 0xe00>;
+ status = "okay";
+
+ u2port0: usb-phy@0 {
+ reg = <0 0x700>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x700>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ usb: usb@11200000 {
+ compatible ="mediatek,mt8195-mtu3", "mediatek,mtu3";
+ reg = <0 0x11203e00 0 0x0100>;
+ reg-names = "ippc";
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ ssusb: ssusb@11200000 {
+ compatible = "mediatek,ssusb";
+ reg = <0 0x11200000 0 0x3e00>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
+ status = "disabled";
+ };
+
+ xhci0: xhci@11200000 {
+ compatible = "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
+ status = "disabled";
+ };
+ };
+
+ u3phy1: t-phy@11e30000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e30000 0xe00>;
+ status = "disabled";
+
+ u2port1: usb-phy@0 {
+ reg = <0x0 0x700>;
+ #phy-cells = <1>;
+ };
+
+ u3port1: usb-phy@700 {
+ reg = <0x700 0x700>;
+ #phy-cells = <1>;
+ };
+ };
+
+ xhci1: xhci@11290000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11290000 0 0x1000>,
+ <0 0x11293e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port1 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
+ status = "disabled";
+ };
+
+ u3phy2: t-phy@11c40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c40000 0x700>;
+ status = "disabled";
+
+ u2port2: usb-phy@0 {
+ reg = <0x0 0x700>;
+ #phy-cells = <1>;
+ };
+ };
+
+ xhci2: xhci@112a0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112a0000 0 0x1000>,
+ <0 0x112a3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ status = "disabled";
+ };
+
+ u3phy3: t-phy@11c50000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c50000 0x700>;
+ status = "okay";
+
+ u2port3: usb-phy@0 {
+ reg = <0x0 0x700>;
+ #phy-cells = <1>;
+ };
+ };
+
+ xhci3: xhci@112b0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112b0000 0 0x1000>,
+ <0 0x112b3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&u2port3 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+ <&clk26m>,
+ <&clk26m>;
+ clock-names = "sys_ck", "xhci_ck", "ref_ck";
+ usb2-lpm-disable;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 04aa2fd97f..3a2af1cdee 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -67,6 +67,15 @@ config TARGET_MT8183
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
+config TARGET_MT8195
+ bool "MediaTek MT8195 SoC"
+ select ARM64
+ help
+ The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
+ a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
+ SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
+ and LPDDR4 options.
+
config TARGET_MT8512
bool "MediaTek MT8512 M1 Board"
select ARM64
@@ -105,6 +114,7 @@ config SYS_BOARD
default "mt7981" if TARGET_MT7981
default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
+ default "mt8195" if TARGET_MT8195
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518
@@ -122,6 +132,7 @@ config SYS_CONFIG_NAME
default "mt7981" if TARGET_MT7981
default "mt7986" if TARGET_MT7986
default "mt8183" if TARGET_MT8183
+ default "mt8195" if TARGET_MT8195
default "mt8512" if TARGET_MT8512
default "mt8516" if TARGET_MT8516
default "mt8518" if TARGET_MT8518
@@ -134,7 +145,7 @@ config SYS_CONFIG_NAME
config MTK_BROM_HEADER_INFO
string
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
- default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
+ default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8195
default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986
default "lk=1" if TARGET_MT7623
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index fc85293f71..fbbb5431d1 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/
obj-$(CONFIG_TARGET_MT7981) += mt7981/
obj-$(CONFIG_TARGET_MT7986) += mt7986/
obj-$(CONFIG_TARGET_MT8183) += mt8183/
+obj-$(CONFIG_TARGET_MT8195) += mt8195/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-mediatek/mt8195/Makefile
new file mode 100644
index 0000000000..886ab7e4eb
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8195/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c
new file mode 100644
index 0000000000..1eb4ade6c5
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8195/init.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Macpaul Lin <macpaul.lin@mediatek.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <asm/system.h>
+#include <dm/uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+int mtk_pll_early_init(void)
+{
+ return 0;
+}
+
+int mtk_soc_early_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT8195\n");
+ return 0;
+}
+
+static struct mm_region mt8195_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mt8195_mem_map;
--
2.18.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v4 2/2] board: mediatek: add mt8195 demo board
2022-12-19 6:43 ` [PATCH v4 " Macpaul Lin
@ 2022-12-19 6:43 ` Macpaul Lin
0 siblings, 0 replies; 23+ messages in thread
From: Macpaul Lin @ 2022-12-19 6:43 UTC (permalink / raw)
To: trini, fparent, marex, sjg, marcel.ziswiler, aouledameur,
frieder.schrempf, philippe.reynes, u-boot,
GSS_MTK_Uboot_upstream, william.zhang, samuel, festevam,
Weijie.Gao, Ryder.Lee, paul.liu
Cc: Bear Wang, Pablo Sun, Macpaul Lin, Macpaul Lin, Chunfeng Yun, Sam Shih
From: Fabien Parent <fparent@baylibre.com>
Add mt8195-demo board support.
This demo purpose board uses MediaTek's MT8195 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
---
MAINTAINERS | 1 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt8195-demo.dts | 109 ++++++++++++++++++++++++++++
board/mediatek/mt8195/MAINTAINERS | 6 ++
board/mediatek/mt8195/Makefile | 3 +
board/mediatek/mt8195/mt8195_demo.c | 38 ++++++++++
configs/mt8195_demo_defconfig | 89 +++++++++++++++++++++++
include/configs/mt8195.h | 28 +++++++
8 files changed, 275 insertions(+)
create mode 100644 arch/arm/dts/mt8195-demo.dts
create mode 100644 board/mediatek/mt8195/MAINTAINERS
create mode 100644 board/mediatek/mt8195/Makefile
create mode 100644 board/mediatek/mt8195/mt8195_demo.c
create mode 100644 configs/mt8195_demo_defconfig
create mode 100644 include/configs/mt8195.h
Changes for v2 and v3:
- no change.
Changes for v4:
- Remove CONFIG_SYS_NS16550 related settings in mt8195.h
- Tested with u-boot/next.
diff --git a/MAINTAINERS b/MAINTAINERS
index f2fe78dfc7..3c7db798be 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -390,6 +390,7 @@ F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
+F: include/configs/mt8195.h
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b3baaf4829..5ab10ac3db 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1278,6 +1278,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7986a-emmc-rfb.dtb \
mt7986b-emmc-rfb.dtb \
mt8183-pumpkin.dtb \
+ mt8195-demo.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
diff --git a/arch/arm/dts/mt8195-demo.dts b/arch/arm/dts/mt8195-demo.dts
new file mode 100644
index 0000000000..bd0952b248
--- /dev/null
+++ b/arch/arm/dts/mt8195-demo.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre SAS.
+ * Author: Macpaul Lin <macpaul.lin@mediatek.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include <config.h>
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 demo board";
+ compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@54600000 {
+ no-map;
+ reg = <0 0x54600000 0x0 0x200000>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&ssusb {
+ mediatek,force-vbus;
+ maximum-speed = "high-speed";
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci3 {
+ status = "okay";
+};
diff --git a/board/mediatek/mt8195/MAINTAINERS b/board/mediatek/mt8195/MAINTAINERS
new file mode 100644
index 0000000000..01fa25115d
--- /dev/null
+++ b/board/mediatek/mt8195/MAINTAINERS
@@ -0,0 +1,6 @@
+MT8195 Demo
+M: Macpaul Lin <macpaul.lin@mediatek.com>
+S: Maintained
+F: board/mediatek/mt8195
+F: include/configs/mt8195.h
+F: configs/mt8195_demo_defconfig
diff --git a/board/mediatek/mt8195/Makefile b/board/mediatek/mt8195/Makefile
new file mode 100644
index 0000000000..7e94a87aea
--- /dev/null
+++ b/board/mediatek/mt8195/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += mt8195_demo.o
diff --git a/board/mediatek/mt8195/mt8195_demo.c b/board/mediatek/mt8195/mt8195_demo.c
new file mode 100644
index 0000000000..b95f5cf28d
--- /dev/null
+++ b/board/mediatek/mt8195/mt8195_demo.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 BayLibre SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <net.h>
+#include <asm/io.h>
+
+int board_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (CONFIG_IS_ENABLED(USB_GADGET)) {
+ ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
+ if (ret) {
+ pr_err("%s: Cannot find USB device\n", __func__);
+ return ret;
+ }
+ }
+
+ if (CONFIG_IS_ENABLED(USB_ETHER))
+ usb_ether_init();
+
+ printf("Disabling WDT\n");
+ writel(0, 0x10007000);
+
+ printf("Enabling SCP SRAM\n");
+ for (unsigned int val = 0xFFFFFFFF; val != 0U;) {
+ val = val >> 1;
+ writel(val, 0x1072102C);
+ }
+
+ return 0;
+}
diff --git a/configs/mt8195_demo_defconfig b/configs/mt8195_demo_defconfig
new file mode 100644
index 0000000000..5b075b1a27
--- /dev/null
+++ b/configs/mt8195_demo_defconfig
@@ -0,0 +1,89 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=13000000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x0
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="mt8195-demo"
+CONFIG_TARGET_MT8195=y
+CONFIG_DEBUG_UART_BASE=0x11001100
+CONFIG_DEBUG_UART_CLOCK=26000000
+# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x4c000000
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="mt8195-demo"
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_MEMORY is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_BLOCK_CACHE is not set
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ISO_PARTITION=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_MMC_ENV_PART=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_ENV_IMPORT_FDT=y
+CONFIG_DEVRES=y
+CONFIG_CLK=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x4d000000
+CONFIG_FASTBOOT_BUF_SIZE=0x8000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
+# CONFIG_INPUT is not set
+# CONFIG_MMC_QUIRKS is not set
+CONFIG_MMC_MTK=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_BAUDRATE=921600
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_MTK_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_MTU3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d
+CONFIG_USB_GADGET_PRODUCT_NUM=0x201c
+CONFIG_USB_ETHER=y
+CONFIG_WDT=y
+CONFIG_WDT_MTK=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/include/configs/mt8195.h b/include/configs/mt8195.h
new file mode 100644
index 0000000000..bc067647c0
--- /dev/null
+++ b/include/configs/mt8195.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for MT8195 based boards
+ *
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Fabien Parent <macpaul.lin@mediatek.com>
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#ifndef __MT8195_H
+#define __MT8195_H
+
+#include <linux/sizes.h>
+
+/* Environment settings */
+#include <config_distro_bootcmd.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
+
+#if !defined(CONFIG_EXTRA_ENV_SETTINGS)
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "scriptaddr=0x40000000\0" \
+ BOOTENV
+#endif
+
+#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/2] board: mediatek: add mt8195 demo board
2022-12-19 3:36 ` Macpaul Lin
@ 2023-01-02 19:15 ` Tom Rini
0 siblings, 0 replies; 23+ messages in thread
From: Tom Rini @ 2023-01-02 19:15 UTC (permalink / raw)
To: Macpaul Lin
Cc: Chunfeng Yun, fparent @ baylibre . com, marex @ denx . de,
sjg @ chromium . org, marcel . ziswiler @ toradex . com,
aouledameur @ baylibre . com, frieder . schrempf @ kontron . de,
philippe . reynes @ softathome . com, u-boot @ lists . denx . de,
GSS_MTK_Uboot_upstream, william . zhang @ broadcom . com,
samuel @ sholland . org, festevam @ denx . de, Weijie Gao,
Ryder Lee, paul . liu @ linaro . org, Miles Chen, Bear Wang,
Pablo Sun, Macpaul Lin
[-- Attachment #1: Type: text/plain, Size: 3506 bytes --]
On Mon, Dec 19, 2022 at 11:36:44AM +0800, Macpaul Lin wrote:
> On 12/13/22 03:02, Tom Rini wrote:
> > On Mon, Dec 12, 2022 at 01:53:05PM -0500, Tom Rini wrote:
> > > On Mon, Dec 12, 2022 at 11:53:04AM -0500, Tom Rini wrote:
> > > > On Thu, Nov 10, 2022 at 03:34:53PM +0800, Macpaul Lin wrote:
> > > >
> > > > > From: Fabien Parent <fparent@baylibre.com>
> > > > >
> > > > > Add mt8195-demo board support.
> > > > > This demo purpose board uses MediaTek's MT8195 SoC.
> > > > >
> > > > > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > > > > Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
> > > > > Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
> > > > [snip]
> > > > > +#include <linux/sizes.h>
> > > > > +
> > > > > +#define CONFIG_SYS_NS16550_SERIAL
> > > > > +#define CONFIG_SYS_NS16550_REG_SIZE -4
> > > > > +#define CONFIG_SYS_NS16550_MEM32
> > > > > +#define CONFIG_SYS_NS16550_COM1 0x11002000
> > > > > +#define CONFIG_SYS_NS16550_CLK 26000000
> > > >
> > > > This is unused, I believe. But when trying to build with current next I
> > > > get:
> > > > Error: Load Address must be set.
> > > > Error: Bad parameters for image type
> > > >
> > > > Please rebase on top of current next and repost, thanks!
>
> Thanks for the information, will send patch v4 later.
>
> > >
> > > Sorry for the noise, this failed due to another patch that needs to be
> > > reworked instead.
> >
> > Welp, I should have finished my re-testing. The patch that broke
> > phycore-rk3288 and I assumed broke this platform too, did not break this
> > platform, there's still some other problem here.
> >
>
> I've tested it on uboot/next and got the following result.
>
> $ make ARCH=arm phycore-rk3288_defconfig
> $ make ARCH=arm
> scripts/kconfig/conf --syncconfig Kconfig
> UPD include/config.h
> CFG u-boot.cfg
> GEN include/autoconf.mk
> GEN include/autoconf.mk.dep
> CFG spl/u-boot.cfg
> GEN spl/include/autoconf.mk
> UPD include/config/uboot.release
> UPD include/generated/version_autogenerated.h
> UPD include/generated/timestamp_autogenerated.h
> UPD include/generated/dt.h
> ENVC include/generated/env.txt
> ENVP include/generated/env.in
> ENVT include/generated/environment.h
> CC lib/asm-offsets.s
> cc1: error: bad value (‘generic-armv7-a’) for ‘-mtune=’ switch
> cc1: note: valid arguments to ‘-mtune=’ switch are: nocona core2 nehalem
> corei7 westmere sandybridge corei7-avx ivybridge core-avx-i haswell
> core-avx2 broadwell skylake skylake-avx512 bonnell atom silvermont slm knl
> intel x86-64 eden-x2 nano nano-1000 nano-2000 nano-3000 nano-x2 eden-x4
> nano-x4 k8 k8-sse3 opteron opteron-sse3 athlon64 athlon64-sse3 athlon-fx
> amdfam10 barcelona bdver1 bdver2 bdver3 bdver4 znver1 btver1 btver2 generic
> scripts/Makefile.build:147: recipe for target 'lib/asm-offsets.s' failed
> make[1]: *** [lib/asm-offsets.s] Error 1
> Makefile:1932: recipe for target 'prepare0' failed
> make: *** [prepare0] Error 2
>
>
> I'm not sure should I test it on custodian tree: arm/next, too. This
> failure seems not related to the 2nd patch of mt8195-demo board.
You don't pass ARCH= when building U-Boot, and you didn't set
CROSS_COMPILE to your arm32 compiler, so that's why it failed there. v4
shows the same problem as v3 for me, so please make sure to build and
boot v5, thanks.
--
Tom
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^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2023-01-02 19:15 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-08 3:21 [PATCH 1/2] arm: mediatek: add mt8195 SOC support Macpaul Lin
2022-11-08 3:21 ` [PATCH 2/2] board: mediatek: add mt8195 demo board Macpaul Lin
2022-11-08 7:57 ` [PATCH 1/2] arm: mediatek: add mt8195 SOC support Pali Rohár
2022-11-09 7:10 ` Macpaul Lin
2022-11-09 20:09 ` Pali Rohár
2022-11-09 21:12 ` Tom Rini
2022-11-09 2:07 ` Chunfeng Yun (云春峰)
2022-11-09 7:32 ` Macpaul Lin
2022-11-09 9:33 ` Macpaul Lin
2022-11-09 13:00 ` Chunfeng Yun (云春峰)
2022-11-09 9:50 ` [PATCH v2 " Macpaul Lin
2022-11-09 9:50 ` [PATCH v2 2/2] board: mediatek: add mt8195 demo board Macpaul Lin
2022-11-09 13:06 ` [PATCH v2 1/2] arm: mediatek: add mt8195 SOC support Chunfeng Yun (云春峰)
2022-11-10 7:34 ` [PATCH v3 " Macpaul Lin
2022-11-10 7:34 ` [PATCH v3 2/2] board: mediatek: add mt8195 demo board Macpaul Lin
2022-12-12 16:53 ` Tom Rini
2022-12-12 18:53 ` Tom Rini
2022-12-12 19:02 ` Tom Rini
2022-12-19 3:36 ` Macpaul Lin
2023-01-02 19:15 ` Tom Rini
2022-11-10 13:50 ` [PATCH v3 1/2] arm: mediatek: add mt8195 SOC support Chunfeng Yun (云春峰)
2022-12-19 6:43 ` [PATCH v4 " Macpaul Lin
2022-12-19 6:43 ` [PATCH v4 2/2] board: mediatek: add mt8195 demo board Macpaul Lin
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