* [PATCH v2 01/16] dt-bindings: clock: qcom: gcc-qcs404: add two GDSC entries
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 02/16] dt-bindings: clock: qcom: gcc-qcs404: switch to gcc.yaml Dmitry Baryshkov
` (15 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Krzysztof Kozlowski
On QCS404 platform the Global Clock Controller supports two GDSCs: MDSS
(display) and OXILI (GPU). Add corresponding indices.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
include/dt-bindings/clock/qcom,gcc-qcs404.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
index bc3051543347..126a51898571 100644
--- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -177,4 +177,8 @@
#define GCC_PCIE_0_PIPE_ARES 21
#define GCC_WDSP_RESTART 22
+/* Indexes for GDSCs */
+#define MDSS_GDSC 0
+#define OXILI_GDSC 1
+
#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 02/16] dt-bindings: clock: qcom: gcc-qcs404: switch to gcc.yaml
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 01/16] dt-bindings: clock: qcom: gcc-qcs404: add two GDSC entries Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 03/16] dt-bindings: clock: qcom: gcc-qcs404: define clocks/clock-names for QCS404 Dmitry Baryshkov
` (14 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Krzysztof Kozlowski
Now as the gcc-qcs404 gained support for GDSC and requires using
the #power-domain-cells property, switch the qcom,gcc-qcs404.yaml schema
to use common gcc.yaml.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../bindings/clock/qcom,gcc-qcs404.yaml | 22 +++++--------------
1 file changed, 5 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
index dca5775f79a4..b70901e0d5cf 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
@@ -20,26 +20,13 @@ properties:
compatible:
const: qcom,gcc-qcs404
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
- reg:
- maxItems: 1
-
- protected-clocks:
- description:
- Protected clock specifier list as per common clock binding.
-
required:
- compatible
- - reg
- - '#clock-cells'
- - '#reset-cells'
-additionalProperties: false
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
examples:
- |
@@ -48,5 +35,6 @@ examples:
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
};
...
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 03/16] dt-bindings: clock: qcom: gcc-qcs404: define clocks/clock-names for QCS404
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 01/16] dt-bindings: clock: qcom: gcc-qcs404: add two GDSC entries Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 02/16] dt-bindings: clock: qcom: gcc-qcs404: switch to gcc.yaml Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 04/16] clk: qcom: gcc-qcs404: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
` (13 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Krzysztof Kozlowski
Define clock/clock-names properties of the GCC device node to be used
on QCS404 platform.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../bindings/clock/qcom,gcc-qcs404.yaml | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
index b70901e0d5cf..b2256f81b265 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
@@ -20,6 +20,24 @@ properties:
compatible:
const: qcom,gcc-qcs404
+ clocks:
+ items:
+ - description: XO source
+ - description: Sleep clock source
+ - description: PCIe 0 PIPE clock (optional)
+ - description: DSI phy instance 0 dsi clock
+ - description: DSI phy instance 0 byte clock
+ - description: HDMI phy PLL clock
+
+ clock-names:
+ items:
+ - const: cxo
+ - const: sleep_clk
+ - const: pcie_0_pipe_clk_src
+ - const: dsi0pll
+ - const: dsi0pllbyte
+ - const: hdmi_pll
+
required:
- compatible
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 04/16] clk: qcom: gcc-qcs404: use ARRAY_SIZE instead of specifying num_parents
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (2 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 03/16] dt-bindings: clock: qcom: gcc-qcs404: define clocks/clock-names for QCS404 Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 05/16] clk: qcom: gcc-qcs404: disable gpll[04]_out_aux parents Dmitry Baryshkov
` (12 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data/names/hws easy and errorproof.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-qcs404.c | 86 +++++++++++++++++------------------
1 file changed, 43 insertions(+), 43 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 46d314d69250..f60a0ab42da1 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -440,7 +440,7 @@ static struct clk_rcg2 apss_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src",
.parent_names = gcc_parent_names_ao_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_ao_0),
.flags = CLK_IS_CRITICAL,
.ops = &clk_rcg2_ops,
},
@@ -461,7 +461,7 @@ static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup0_i2c_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -486,7 +486,7 @@ static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup0_spi_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -500,7 +500,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -525,7 +525,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -539,7 +539,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -565,7 +565,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -579,7 +579,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -593,7 +593,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -607,7 +607,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -621,7 +621,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -655,7 +655,7 @@ static struct clk_rcg2 blsp1_uart0_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart0_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -669,7 +669,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -683,7 +683,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -698,7 +698,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -712,7 +712,7 @@ static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup0_i2c_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -726,7 +726,7 @@ static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup0_spi_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -740,7 +740,7 @@ static struct clk_rcg2 blsp2_uart0_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart0_apps_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -753,7 +753,7 @@ static struct clk_rcg2 byte0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
.parent_names = gcc_parent_names_5,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
@@ -776,7 +776,7 @@ static struct clk_rcg2 emac_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "emac_clk_src",
.parent_names = gcc_parent_names_4,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_4),
.ops = &clk_rcg2_ops,
},
};
@@ -797,7 +797,7 @@ static struct clk_rcg2 emac_ptp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "emac_ptp_clk_src",
.parent_names = gcc_parent_names_4,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_4),
.ops = &clk_rcg2_ops,
},
};
@@ -816,7 +816,7 @@ static struct clk_rcg2 esc0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
.parent_names = gcc_parent_names_6,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_6),
.ops = &clk_rcg2_ops,
},
};
@@ -850,7 +850,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
.parent_names = gcc_parent_names_7,
- .num_parents = 6,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_7),
.ops = &clk_rcg2_ops,
},
};
@@ -871,7 +871,7 @@ static struct clk_rcg2 gp1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
.parent_names = gcc_parent_names_2,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_2),
.ops = &clk_rcg2_ops,
},
};
@@ -885,7 +885,7 @@ static struct clk_rcg2 gp2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
.parent_names = gcc_parent_names_2,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_2),
.ops = &clk_rcg2_ops,
},
};
@@ -899,7 +899,7 @@ static struct clk_rcg2 gp3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
.parent_names = gcc_parent_names_2,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_2),
.ops = &clk_rcg2_ops,
},
};
@@ -913,7 +913,7 @@ static struct clk_rcg2 hdmi_app_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_app_clk_src",
.parent_names = gcc_parent_names_1,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_1),
.ops = &clk_rcg2_ops,
},
};
@@ -927,7 +927,7 @@ static struct clk_rcg2 hdmi_pclk_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_pclk_clk_src",
.parent_names = gcc_parent_names_8,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_8),
.ops = &clk_rcg2_ops,
},
};
@@ -954,7 +954,7 @@ static struct clk_rcg2 mdp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
.parent_names = gcc_parent_names_9,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_9),
.ops = &clk_rcg2_ops,
},
};
@@ -973,7 +973,7 @@ static struct clk_rcg2 pcie_0_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_aux_clk_src",
.parent_names = gcc_parent_names_10,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_10),
.ops = &clk_rcg2_ops,
},
};
@@ -994,7 +994,7 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_pipe_clk_src",
.parent_names = gcc_parent_names_11,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_11),
.ops = &clk_rcg2_ops,
},
};
@@ -1007,7 +1007,7 @@ static struct clk_rcg2 pclk0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
.parent_names = gcc_parent_names_12,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_12),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
@@ -1028,7 +1028,7 @@ static struct clk_rcg2 pdm2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -1056,7 +1056,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
.parent_names = gcc_parent_names_13,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_13),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1076,7 +1076,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_ice_core_clk_src",
.parent_names = gcc_parent_names_3,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_3),
.ops = &clk_rcg2_ops,
},
};
@@ -1102,7 +1102,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
.parent_names = gcc_parent_names_14,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_14),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1116,7 +1116,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb20_mock_utmi_clk_src",
.parent_names = gcc_parent_names_1,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_1),
.ops = &clk_rcg2_ops,
},
};
@@ -1138,7 +1138,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
.parent_names = gcc_parent_names_0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_0),
.ops = &clk_rcg2_ops,
},
};
@@ -1152,7 +1152,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
.parent_names = gcc_parent_names_1,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_1),
.ops = &clk_rcg2_ops,
},
};
@@ -1166,7 +1166,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb3_phy_aux_clk_src",
.parent_names = gcc_parent_names_1,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_1),
.ops = &clk_rcg2_ops,
},
};
@@ -1189,7 +1189,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
.parent_names = gcc_parent_names_3,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_3),
.ops = &clk_rcg2_ops,
},
};
@@ -1203,7 +1203,7 @@ static struct clk_rcg2 vsync_clk_src = {
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
.parent_names = gcc_parent_names_15,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_15),
.ops = &clk_rcg2_ops,
},
};
@@ -1225,7 +1225,7 @@ static struct clk_rcg2 cdsp_bimc_clk_src = {
.clkr.hw.init = &(struct clk_init_data) {
.name = "cdsp_bimc_clk_src",
.parent_names = gcc_parent_names_16,
- .num_parents = 4,
+ .num_parents = ARRAY_SIZE(gcc_parent_names_16),
.ops = &clk_rcg2_ops,
},
};
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 05/16] clk: qcom: gcc-qcs404: disable gpll[04]_out_aux parents
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (3 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 04/16] clk: qcom: gcc-qcs404: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 06/16] clk: qcom: gcc-qcs404: fix names of the DSI clocks used as parents Dmitry Baryshkov
` (11 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On the QCS404 platform the driver for the Global Clock Controller
doens't define gpll0_out_aux and gpll4_out_aux clocks, so it's not
possible to use them as parents. Remove entries for these clocks.
Note: backporting this patch to earlier kernels would also require a
previous patch which switches the gcc driver to use ARRAY_SIZE for
parent data arrays.
Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-qcs404.c | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index f60a0ab42da1..507c42d7f753 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -25,11 +25,9 @@ enum {
P_CORE_BI_PLL_TEST_SE,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
- P_GPLL0_OUT_AUX,
P_GPLL0_OUT_MAIN,
P_GPLL1_OUT_MAIN,
P_GPLL3_OUT_MAIN,
- P_GPLL4_OUT_AUX,
P_GPLL4_OUT_MAIN,
P_GPLL6_OUT_AUX,
P_HDMI_PHY_PLL_CLK,
@@ -109,28 +107,24 @@ static const char * const gcc_parent_names_4[] = {
static const struct parent_map gcc_parent_map_5[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
- { P_GPLL0_OUT_AUX, 2 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_5[] = {
"cxo",
"dsi0pll_byteclk_src",
- "gpll0_out_aux",
"core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
- { P_GPLL0_OUT_AUX, 3 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_6[] = {
"cxo",
"dsi0_phy_pll_out_byteclk",
- "gpll0_out_aux",
"core_bi_pll_test_se",
};
@@ -139,7 +133,6 @@ static const struct parent_map gcc_parent_map_7[] = {
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL3_OUT_MAIN, 2 },
{ P_GPLL6_OUT_AUX, 3 },
- { P_GPLL4_OUT_AUX, 4 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
@@ -148,7 +141,6 @@ static const char * const gcc_parent_names_7[] = {
"gpll0_out_main",
"gpll3_out_main",
"gpll6_out_aux",
- "gpll4_out_aux",
"core_bi_pll_test_se",
};
@@ -207,14 +199,12 @@ static const char * const gcc_parent_names_11[] = {
static const struct parent_map gcc_parent_map_12[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
- { P_GPLL0_OUT_AUX, 2 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_12[] = {
"cxo",
"dsi0pll_pclk_src",
- "gpll0_out_aux",
"core_bi_pll_test_se",
};
@@ -237,40 +227,34 @@ static const char * const gcc_parent_names_13[] = {
static const struct parent_map gcc_parent_map_14[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
- { P_GPLL4_OUT_AUX, 2 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_14[] = {
"cxo",
"gpll0_out_main",
- "gpll4_out_aux",
"core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_15[] = {
{ P_XO, 0 },
- { P_GPLL0_OUT_AUX, 2 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_15[] = {
"cxo",
- "gpll0_out_aux",
"core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_16[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
- { P_GPLL0_OUT_AUX, 2 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_16[] = {
"cxo",
"gpll0_out_main",
- "gpll0_out_aux",
"core_bi_pll_test_se",
};
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 06/16] clk: qcom: gcc-qcs404: fix names of the DSI clocks used as parents
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (4 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 05/16] clk: qcom: gcc-qcs404: disable gpll[04]_out_aux parents Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 07/16] clk: qcom: gcc-qcs404: fix the name of the HDMI PLL clock Dmitry Baryshkov
` (10 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
The QCS404 uses 28nm LPM DSI PHY, which registers dsi0pll and
dsi0pllbyte clocks. Fix all DSI PHY clock names used as parents inside
the GCC driver.
Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-qcs404.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 507c42d7f753..67a180d688c3 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -112,7 +112,7 @@ static const struct parent_map gcc_parent_map_5[] = {
static const char * const gcc_parent_names_5[] = {
"cxo",
- "dsi0pll_byteclk_src",
+ "dsi0pllbyte",
"core_bi_pll_test_se",
};
@@ -124,7 +124,7 @@ static const struct parent_map gcc_parent_map_6[] = {
static const char * const gcc_parent_names_6[] = {
"cxo",
- "dsi0_phy_pll_out_byteclk",
+ "dsi0pllbyte",
"core_bi_pll_test_se",
};
@@ -167,7 +167,7 @@ static const struct parent_map gcc_parent_map_9[] = {
static const char * const gcc_parent_names_9[] = {
"cxo",
"gpll0_out_main",
- "dsi0_phy_pll_out_dsiclk",
+ "dsi0pll",
"gpll6_out_aux",
"core_bi_pll_test_se",
};
@@ -204,7 +204,7 @@ static const struct parent_map gcc_parent_map_12[] = {
static const char * const gcc_parent_names_12[] = {
"cxo",
- "dsi0pll_pclk_src",
+ "dsi0pll",
"core_bi_pll_test_se",
};
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 07/16] clk: qcom: gcc-qcs404: fix the name of the HDMI PLL clock
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (5 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 06/16] clk: qcom: gcc-qcs404: fix names of the DSI clocks used as parents Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 08/16] clk: qcom: gcc-qcs404: get rid of the test clock Dmitry Baryshkov
` (9 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
The QCS404 uses 28nm HDMI PHY. The in-kernel driver doesn't provide the
PLL (yet), but the out of tree patches used the name "hdmi_pll" for it.
Other Qualcomm HDMI PHYs use either the name "hdmi_pll" (8960) or
"hdmipll" (8996). Thus change the expected HDMI PLL clock name to
"hdmi_pll".
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-qcs404.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 67a180d688c3..241768da2263 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -152,7 +152,7 @@ static const struct parent_map gcc_parent_map_8[] = {
static const char * const gcc_parent_names_8[] = {
"cxo",
- "hdmi_phy_pll_clk",
+ "hdmi_pll",
"core_bi_pll_test_se",
};
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 08/16] clk: qcom: gcc-qcs404: get rid of the test clock
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (6 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 07/16] clk: qcom: gcc-qcs404: fix the name of the HDMI PLL clock Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 09/16] clk: qcom: gcc-qcs404: move PLL clocks up Dmitry Baryshkov
` (8 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree, Stephen Boyd
The test clock isn't in the bindings and apparently it's not used by
anyone upstream. Remove it.
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-qcs404.c | 34 ----------------------------------
1 file changed, 34 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 241768da2263..e1d1d3a700f7 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -22,7 +22,6 @@
#include "reset.h"
enum {
- P_CORE_BI_PLL_TEST_SE,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_GPLL0_OUT_MAIN,
@@ -39,29 +38,24 @@ enum {
static const struct parent_map gcc_parent_map_0[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_0[] = {
"cxo",
"gpll0_out_main",
- "core_bi_pll_test_se",
};
static const char * const gcc_parent_names_ao_0[] = {
"cxo",
"gpll0_ao_out_main",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_XO, 0 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_1[] = {
"cxo",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_2[] = {
@@ -82,50 +76,42 @@ static const struct parent_map gcc_parent_map_3[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL6_OUT_AUX, 2 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_3[] = {
"cxo",
"gpll0_out_main",
"gpll6_out_aux",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_XO, 0 },
{ P_GPLL1_OUT_MAIN, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_4[] = {
"cxo",
"gpll1_out_main",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_5[] = {
"cxo",
"dsi0pllbyte",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_6[] = {
"cxo",
"dsi0pllbyte",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_7[] = {
@@ -133,7 +119,6 @@ static const struct parent_map gcc_parent_map_7[] = {
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL3_OUT_MAIN, 2 },
{ P_GPLL6_OUT_AUX, 3 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_7[] = {
@@ -141,19 +126,16 @@ static const char * const gcc_parent_names_7[] = {
"gpll0_out_main",
"gpll3_out_main",
"gpll6_out_aux",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_XO, 0 },
{ P_HDMI_PHY_PLL_CLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_8[] = {
"cxo",
"hdmi_pll",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_9[] = {
@@ -161,7 +143,6 @@ static const struct parent_map gcc_parent_map_9[] = {
{ P_GPLL0_OUT_MAIN, 1 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 2 },
{ P_GPLL6_OUT_AUX, 3 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_9[] = {
@@ -169,43 +150,36 @@ static const char * const gcc_parent_names_9[] = {
"gpll0_out_main",
"dsi0pll",
"gpll6_out_aux",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_XO, 0 },
{ P_SLEEP_CLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_10[] = {
"cxo",
"sleep_clk",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_XO, 0 },
{ P_PCIE_0_PIPE_CLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_11[] = {
"cxo",
"pcie_0_pipe_clk",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_12[] = {
"cxo",
"dsi0pll",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_13[] = {
@@ -213,7 +187,6 @@ static const struct parent_map gcc_parent_map_13[] = {
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_MAIN, 2 },
{ P_GPLL6_OUT_AUX, 3 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_13[] = {
@@ -221,41 +194,34 @@ static const char * const gcc_parent_names_13[] = {
"gpll0_out_main",
"gpll4_out_main",
"gpll6_out_aux",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_14[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_14[] = {
"cxo",
"gpll0_out_main",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_15[] = {
{ P_XO, 0 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_15[] = {
"cxo",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_16[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_16[] = {
"cxo",
"gpll0_out_main",
- "core_bi_pll_test_se",
};
static struct clk_fixed_factor cxo = {
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 09/16] clk: qcom: gcc-qcs404: move PLL clocks up
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (7 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 08/16] clk: qcom: gcc-qcs404: get rid of the test clock Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 10/16] clk: qcom: gcc-qcs404: use parent_hws/_data instead of parent_names Dmitry Baryshkov
` (7 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Move PLL clock declarations up, before clock parent tables, so that we
can use pll hw clock fields in the next commit.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-qcs404.c | 298 +++++++++++++++++-----------------
1 file changed, 149 insertions(+), 149 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index e1d1d3a700f7..9b200b378b6b 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -35,6 +35,155 @@ enum {
P_XO,
};
+static struct clk_fixed_factor cxo = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "cxo",
+ .parent_names = (const char *[]){ "xo-board" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll0_sleep_clk_src = {
+ .offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x45008,
+ .enable_mask = BIT(23),
+ .enable_is_inverted = true,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_sleep_clk_src",
+ .parent_names = (const char *[]){ "cxo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gpll0_out_main = {
+ .offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .flags = SUPPORTS_FSM_MODE,
+ .clkr = {
+ .enable_reg = 0x45000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_out_main",
+ .parent_names = (const char *[])
+ { "cxo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gpll0_ao_out_main = {
+ .offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .flags = SUPPORTS_FSM_MODE,
+ .clkr = {
+ .enable_reg = 0x45000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_ao_out_main",
+ .parent_names = (const char *[]){ "cxo" },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL,
+ .ops = &clk_alpha_pll_fixed_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gpll1_out_main = {
+ .offset = 0x20000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x45000,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_out_main",
+ .parent_names = (const char *[]){ "cxo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+/* 930MHz configuration */
+static const struct alpha_pll_config gpll3_config = {
+ .l = 48,
+ .alpha = 0x0,
+ .alpha_en_mask = BIT(24),
+ .post_div_mask = 0xf << 8,
+ .post_div_val = 0x1 << 8,
+ .vco_mask = 0x3 << 20,
+ .main_output_mask = 0x1,
+ .config_ctl_val = 0x4001055b,
+};
+
+static const struct pll_vco gpll3_vco[] = {
+ { 700000000, 1400000000, 0 },
+};
+
+static struct clk_alpha_pll gpll3_out_main = {
+ .offset = 0x22000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .vco_table = gpll3_vco,
+ .num_vco = ARRAY_SIZE(gpll3_vco),
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll3_out_main",
+ .parent_names = (const char *[]){ "cxo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll gpll4_out_main = {
+ .offset = 0x24000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x45000,
+ .enable_mask = BIT(5),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll4_out_main",
+ .parent_names = (const char *[]){ "cxo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_pll gpll6 = {
+ .l_reg = 0x37004,
+ .m_reg = 0x37008,
+ .n_reg = 0x3700C,
+ .config_reg = 0x37014,
+ .mode_reg = 0x37000,
+ .status_reg = 0x3701C,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll6",
+ .parent_names = (const char *[]){ "cxo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap gpll6_out_aux = {
+ .enable_reg = 0x45000,
+ .enable_mask = BIT(7),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll6_out_aux",
+ .parent_names = (const char *[]){ "gpll6" },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
static const struct parent_map gcc_parent_map_0[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
@@ -224,155 +373,6 @@ static const char * const gcc_parent_names_16[] = {
"gpll0_out_main",
};
-static struct clk_fixed_factor cxo = {
- .mult = 1,
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "cxo",
- .parent_names = (const char *[]){ "xo-board" },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-};
-
-static struct clk_alpha_pll gpll0_sleep_clk_src = {
- .offset = 0x21000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr = {
- .enable_reg = 0x45008,
- .enable_mask = BIT(23),
- .enable_is_inverted = true,
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_sleep_clk_src",
- .parent_names = (const char *[]){ "cxo" },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
- },
- },
-};
-
-static struct clk_alpha_pll gpll0_out_main = {
- .offset = 0x21000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .flags = SUPPORTS_FSM_MODE,
- .clkr = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_out_main",
- .parent_names = (const char *[])
- { "cxo" },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
- },
- },
-};
-
-static struct clk_alpha_pll gpll0_ao_out_main = {
- .offset = 0x21000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .flags = SUPPORTS_FSM_MODE,
- .clkr = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_ao_out_main",
- .parent_names = (const char *[]){ "cxo" },
- .num_parents = 1,
- .flags = CLK_IS_CRITICAL,
- .ops = &clk_alpha_pll_fixed_ops,
- },
- },
-};
-
-static struct clk_alpha_pll gpll1_out_main = {
- .offset = 0x20000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gpll1_out_main",
- .parent_names = (const char *[]){ "cxo" },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
- },
- },
-};
-
-/* 930MHz configuration */
-static const struct alpha_pll_config gpll3_config = {
- .l = 48,
- .alpha = 0x0,
- .alpha_en_mask = BIT(24),
- .post_div_mask = 0xf << 8,
- .post_div_val = 0x1 << 8,
- .vco_mask = 0x3 << 20,
- .main_output_mask = 0x1,
- .config_ctl_val = 0x4001055b,
-};
-
-static const struct pll_vco gpll3_vco[] = {
- { 700000000, 1400000000, 0 },
-};
-
-static struct clk_alpha_pll gpll3_out_main = {
- .offset = 0x22000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .vco_table = gpll3_vco,
- .num_vco = ARRAY_SIZE(gpll3_vco),
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "gpll3_out_main",
- .parent_names = (const char *[]){ "cxo" },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
- },
- },
-};
-
-static struct clk_alpha_pll gpll4_out_main = {
- .offset = 0x24000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
- .clkr = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(5),
- .hw.init = &(struct clk_init_data){
- .name = "gpll4_out_main",
- .parent_names = (const char *[]){ "cxo" },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
- },
- },
-};
-
-static struct clk_pll gpll6 = {
- .l_reg = 0x37004,
- .m_reg = 0x37008,
- .n_reg = 0x3700C,
- .config_reg = 0x37014,
- .mode_reg = 0x37000,
- .status_reg = 0x3701C,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll6",
- .parent_names = (const char *[]){ "cxo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap gpll6_out_aux = {
- .enable_reg = 0x45000,
- .enable_mask = BIT(7),
- .hw.init = &(struct clk_init_data){
- .name = "gpll6_out_aux",
- .parent_names = (const char *[]){ "gpll6" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
F(19200000, P_XO, 1, 0, 0),
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 10/16] clk: qcom: gcc-qcs404: use parent_hws/_data instead of parent_names
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (8 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 09/16] clk: qcom: gcc-qcs404: move PLL clocks up Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 11/16] clk: qcom: gcc-qcs404: sort out the cxo clock Dmitry Baryshkov
` (6 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-qcs404.c | 524 ++++++++++++++++++----------------
1 file changed, 275 insertions(+), 249 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 9b200b378b6b..2726a48f2d5c 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -21,6 +21,15 @@
#include "common.h"
#include "reset.h"
+enum {
+ DT_XO,
+ DT_SLEEP_CLK,
+ DT_PCIE_0_PIPE_CLK,
+ DT_DSI0_PHY_PLL_OUT_DSICLK,
+ DT_DSI0_PHY_PLL_OUT_BYTECLK,
+ DT_HDMI_PHY_PLL_CLK,
+};
+
enum {
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
@@ -40,7 +49,9 @@ static struct clk_fixed_factor cxo = {
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "cxo",
- .parent_names = (const char *[]){ "xo-board" },
+ .parent_data = &(const struct clk_parent_data) {
+ .name = "xo-board",
+ },
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
@@ -55,7 +66,9 @@ static struct clk_alpha_pll gpll0_sleep_clk_src = {
.enable_is_inverted = true,
.hw.init = &(struct clk_init_data){
.name = "gpll0_sleep_clk_src",
- .parent_names = (const char *[]){ "cxo" },
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &cxo.hw,
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
@@ -71,8 +84,9 @@ static struct clk_alpha_pll gpll0_out_main = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_out_main",
- .parent_names = (const char *[])
- { "cxo" },
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &cxo.hw,
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
@@ -88,7 +102,9 @@ static struct clk_alpha_pll gpll0_ao_out_main = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_ao_out_main",
- .parent_names = (const char *[]){ "cxo" },
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &cxo.hw,
+ },
.num_parents = 1,
.flags = CLK_IS_CRITICAL,
.ops = &clk_alpha_pll_fixed_ops,
@@ -104,7 +120,9 @@ static struct clk_alpha_pll gpll1_out_main = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1_out_main",
- .parent_names = (const char *[]){ "cxo" },
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &cxo.hw,
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
@@ -135,7 +153,9 @@ static struct clk_alpha_pll gpll3_out_main = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpll3_out_main",
- .parent_names = (const char *[]){ "cxo" },
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &cxo.hw,
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
@@ -150,7 +170,9 @@ static struct clk_alpha_pll gpll4_out_main = {
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll4_out_main",
- .parent_names = (const char *[]){ "cxo" },
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &cxo.hw,
+ },
.num_parents = 1,
.ops = &clk_alpha_pll_ops,
},
@@ -167,7 +189,9 @@ static struct clk_pll gpll6 = {
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6",
- .parent_names = (const char *[]){ "cxo" },
+ .parent_data = &(const struct clk_parent_data) {
+ .hw = &cxo.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -178,7 +202,9 @@ static struct clk_regmap gpll6_out_aux = {
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "gpll6_out_aux",
- .parent_names = (const char *[]){ "gpll6" },
+ .parent_hws = (const struct clk_hw*[]) {
+ &gpll6.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -189,22 +215,22 @@ static const struct parent_map gcc_parent_map_0[] = {
{ P_GPLL0_OUT_MAIN, 1 },
};
-static const char * const gcc_parent_names_0[] = {
- "cxo",
- "gpll0_out_main",
+static const struct clk_parent_data gcc_parent_data_0[] = {
+ { .hw = &cxo.hw },
+ { .hw = &gpll0_out_main.clkr.hw },
};
-static const char * const gcc_parent_names_ao_0[] = {
- "cxo",
- "gpll0_ao_out_main",
+static const struct clk_parent_data gcc_parent_data_ao_0[] = {
+ { .hw = &cxo.hw },
+ { .hw = &gpll0_ao_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_XO, 0 },
};
-static const char * const gcc_parent_names_1[] = {
- "cxo",
+static const struct clk_parent_data gcc_parent_data_1[] = {
+ { .hw = &cxo.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
@@ -214,11 +240,11 @@ static const struct parent_map gcc_parent_map_2[] = {
{ P_SLEEP_CLK, 6 },
};
-static const char * const gcc_parent_names_2[] = {
- "cxo",
- "gpll0_out_main",
- "gpll6_out_aux",
- "sleep_clk",
+static const struct clk_parent_data gcc_parent_data_2[] = {
+ { .hw = &cxo.hw },
+ { .hw = &gpll0_out_main.clkr.hw },
+ { .hw = &gpll6_out_aux.hw },
+ { .index = DT_SLEEP_CLK, .name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_3[] = {
@@ -227,10 +253,10 @@ static const struct parent_map gcc_parent_map_3[] = {
{ P_GPLL6_OUT_AUX, 2 },
};
-static const char * const gcc_parent_names_3[] = {
- "cxo",
- "gpll0_out_main",
- "gpll6_out_aux",
+static const struct clk_parent_data gcc_parent_data_3[] = {
+ { .hw = &cxo.hw },
+ { .hw = &gpll0_out_main.clkr.hw },
+ { .hw = &gpll6_out_aux.hw },
};
static const struct parent_map gcc_parent_map_4[] = {
@@ -238,9 +264,9 @@ static const struct parent_map gcc_parent_map_4[] = {
{ P_GPLL1_OUT_MAIN, 1 },
};
-static const char * const gcc_parent_names_4[] = {
- "cxo",
- "gpll1_out_main",
+static const struct clk_parent_data gcc_parent_data_4[] = {
+ { .hw = &cxo.hw },
+ { .hw = &gpll1_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
@@ -248,9 +274,9 @@ static const struct parent_map gcc_parent_map_5[] = {
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
};
-static const char * const gcc_parent_names_5[] = {
- "cxo",
- "dsi0pllbyte",
+static const struct clk_parent_data gcc_parent_data_5[] = {
+ { .hw = &cxo.hw },
+ { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" },
};
static const struct parent_map gcc_parent_map_6[] = {
@@ -258,9 +284,9 @@ static const struct parent_map gcc_parent_map_6[] = {
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
};
-static const char * const gcc_parent_names_6[] = {
- "cxo",
- "dsi0pllbyte",
+static const struct clk_parent_data gcc_parent_data_6[] = {
+ { .hw = &cxo.hw },
+ { .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" },
};
static const struct parent_map gcc_parent_map_7[] = {
@@ -270,11 +296,11 @@ static const struct parent_map gcc_parent_map_7[] = {
{ P_GPLL6_OUT_AUX, 3 },
};
-static const char * const gcc_parent_names_7[] = {
- "cxo",
- "gpll0_out_main",
- "gpll3_out_main",
- "gpll6_out_aux",
+static const struct clk_parent_data gcc_parent_data_7[] = {
+ { .hw = &cxo.hw },
+ { .hw = &gpll0_out_main.clkr.hw },
+ { .hw = &gpll3_out_main.clkr.hw },
+ { .hw = &gpll6_out_aux.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
@@ -282,9 +308,9 @@ static const struct parent_map gcc_parent_map_8[] = {
{ P_HDMI_PHY_PLL_CLK, 1 },
};
-static const char * const gcc_parent_names_8[] = {
- "cxo",
- "hdmi_pll",
+static const struct clk_parent_data gcc_parent_data_8[] = {
+ { .hw = &cxo.hw },
+ { .index = DT_HDMI_PHY_PLL_CLK, .name = "hdmi_pll" },
};
static const struct parent_map gcc_parent_map_9[] = {
@@ -294,11 +320,11 @@ static const struct parent_map gcc_parent_map_9[] = {
{ P_GPLL6_OUT_AUX, 3 },
};
-static const char * const gcc_parent_names_9[] = {
- "cxo",
- "gpll0_out_main",
- "dsi0pll",
- "gpll6_out_aux",
+static const struct clk_parent_data gcc_parent_data_9[] = {
+ { .hw = &cxo.hw },
+ { .hw = &gpll0_out_main.clkr.hw },
+ { .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" },
+ { .hw = &gpll6_out_aux.hw },
};
static const struct parent_map gcc_parent_map_10[] = {
@@ -306,9 +332,9 @@ static const struct parent_map gcc_parent_map_10[] = {
{ P_SLEEP_CLK, 1 },
};
-static const char * const gcc_parent_names_10[] = {
- "cxo",
- "sleep_clk",
+static const struct clk_parent_data gcc_parent_data_10[] = {
+ { .hw = &cxo.hw },
+ { .index = DT_SLEEP_CLK, .name = "sleep_clk" },
};
static const struct parent_map gcc_parent_map_11[] = {
@@ -316,9 +342,9 @@ static const struct parent_map gcc_parent_map_11[] = {
{ P_PCIE_0_PIPE_CLK, 1 },
};
-static const char * const gcc_parent_names_11[] = {
- "cxo",
- "pcie_0_pipe_clk",
+static const struct clk_parent_data gcc_parent_data_11[] = {
+ { .hw = &cxo.hw },
+ { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
};
static const struct parent_map gcc_parent_map_12[] = {
@@ -326,9 +352,9 @@ static const struct parent_map gcc_parent_map_12[] = {
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
};
-static const char * const gcc_parent_names_12[] = {
- "cxo",
- "dsi0pll",
+static const struct clk_parent_data gcc_parent_data_12[] = {
+ { .hw = &cxo.hw },
+ { .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" },
};
static const struct parent_map gcc_parent_map_13[] = {
@@ -338,11 +364,11 @@ static const struct parent_map gcc_parent_map_13[] = {
{ P_GPLL6_OUT_AUX, 3 },
};
-static const char * const gcc_parent_names_13[] = {
- "cxo",
- "gpll0_out_main",
- "gpll4_out_main",
- "gpll6_out_aux",
+static const struct clk_parent_data gcc_parent_data_13[] = {
+ { .hw = &cxo.hw },
+ { .hw = &gpll0_out_main.clkr.hw },
+ { .hw = &gpll4_out_main.clkr.hw },
+ { .hw = &gpll6_out_aux.hw },
};
static const struct parent_map gcc_parent_map_14[] = {
@@ -350,17 +376,17 @@ static const struct parent_map gcc_parent_map_14[] = {
{ P_GPLL0_OUT_MAIN, 1 },
};
-static const char * const gcc_parent_names_14[] = {
- "cxo",
- "gpll0_out_main",
+static const struct clk_parent_data gcc_parent_data_14[] = {
+ { .hw = &cxo.hw },
+ { .hw = &gpll0_out_main.clkr.hw },
};
static const struct parent_map gcc_parent_map_15[] = {
{ P_XO, 0 },
};
-static const char * const gcc_parent_names_15[] = {
- "cxo",
+static const struct clk_parent_data gcc_parent_data_15[] = {
+ { .hw = &cxo.hw },
};
static const struct parent_map gcc_parent_map_16[] = {
@@ -368,9 +394,9 @@ static const struct parent_map gcc_parent_map_16[] = {
{ P_GPLL0_OUT_MAIN, 1 },
};
-static const char * const gcc_parent_names_16[] = {
- "cxo",
- "gpll0_out_main",
+static const struct clk_parent_data gcc_parent_data_16[] = {
+ { .hw = &cxo.hw },
+ { .hw = &gpll0_out_main.clkr.hw },
};
static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
@@ -389,8 +415,8 @@ static struct clk_rcg2 apss_ahb_clk_src = {
.freq_tbl = ftbl_apss_ahb_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "apss_ahb_clk_src",
- .parent_names = gcc_parent_names_ao_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_ao_0),
+ .parent_data = gcc_parent_data_ao_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_ao_0),
.flags = CLK_IS_CRITICAL,
.ops = &clk_rcg2_ops,
},
@@ -410,8 +436,8 @@ static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = {
.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup0_i2c_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -435,8 +461,8 @@ static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = {
.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup0_spi_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -449,8 +475,8 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_i2c_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -474,8 +500,8 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup1_spi_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -488,8 +514,8 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_i2c_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -514,8 +540,8 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
.freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup2_spi_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -528,8 +554,8 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_i2c_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -542,8 +568,8 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup3_spi_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -556,8 +582,8 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_i2c_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -570,8 +596,8 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_qup4_spi_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -604,8 +630,8 @@ static struct clk_rcg2 blsp1_uart0_apps_clk_src = {
.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart0_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -618,8 +644,8 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart1_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -632,8 +658,8 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart2_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -647,8 +673,8 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp1_uart3_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -661,8 +687,8 @@ static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = {
.freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup0_i2c_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -675,8 +701,8 @@ static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = {
.freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_qup0_spi_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -689,8 +715,8 @@ static struct clk_rcg2 blsp2_uart0_apps_clk_src = {
.freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "blsp2_uart0_apps_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -702,8 +728,8 @@ static struct clk_rcg2 byte0_clk_src = {
.parent_map = gcc_parent_map_5,
.clkr.hw.init = &(struct clk_init_data){
.name = "byte0_clk_src",
- .parent_names = gcc_parent_names_5,
- .num_parents = ARRAY_SIZE(gcc_parent_names_5),
+ .parent_data = gcc_parent_data_5,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_byte2_ops,
},
@@ -725,8 +751,8 @@ static struct clk_rcg2 emac_clk_src = {
.freq_tbl = ftbl_emac_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "emac_clk_src",
- .parent_names = gcc_parent_names_4,
- .num_parents = ARRAY_SIZE(gcc_parent_names_4),
+ .parent_data = gcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
@@ -746,8 +772,8 @@ static struct clk_rcg2 emac_ptp_clk_src = {
.freq_tbl = ftbl_emac_ptp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "emac_ptp_clk_src",
- .parent_names = gcc_parent_names_4,
- .num_parents = ARRAY_SIZE(gcc_parent_names_4),
+ .parent_data = gcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_4),
.ops = &clk_rcg2_ops,
},
};
@@ -765,8 +791,8 @@ static struct clk_rcg2 esc0_clk_src = {
.freq_tbl = ftbl_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "esc0_clk_src",
- .parent_names = gcc_parent_names_6,
- .num_parents = ARRAY_SIZE(gcc_parent_names_6),
+ .parent_data = gcc_parent_data_6,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_6),
.ops = &clk_rcg2_ops,
},
};
@@ -799,8 +825,8 @@ static struct clk_rcg2 gfx3d_clk_src = {
.freq_tbl = ftbl_gfx3d_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gfx3d_clk_src",
- .parent_names = gcc_parent_names_7,
- .num_parents = ARRAY_SIZE(gcc_parent_names_7),
+ .parent_data = gcc_parent_data_7,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
.ops = &clk_rcg2_ops,
},
};
@@ -820,8 +846,8 @@ static struct clk_rcg2 gp1_clk_src = {
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp1_clk_src",
- .parent_names = gcc_parent_names_2,
- .num_parents = ARRAY_SIZE(gcc_parent_names_2),
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
@@ -834,8 +860,8 @@ static struct clk_rcg2 gp2_clk_src = {
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp2_clk_src",
- .parent_names = gcc_parent_names_2,
- .num_parents = ARRAY_SIZE(gcc_parent_names_2),
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
@@ -848,8 +874,8 @@ static struct clk_rcg2 gp3_clk_src = {
.freq_tbl = ftbl_gp1_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "gp3_clk_src",
- .parent_names = gcc_parent_names_2,
- .num_parents = ARRAY_SIZE(gcc_parent_names_2),
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
.ops = &clk_rcg2_ops,
},
};
@@ -862,8 +888,8 @@ static struct clk_rcg2 hdmi_app_clk_src = {
.freq_tbl = ftbl_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_app_clk_src",
- .parent_names = gcc_parent_names_1,
- .num_parents = ARRAY_SIZE(gcc_parent_names_1),
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
@@ -876,8 +902,8 @@ static struct clk_rcg2 hdmi_pclk_clk_src = {
.freq_tbl = ftbl_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "hdmi_pclk_clk_src",
- .parent_names = gcc_parent_names_8,
- .num_parents = ARRAY_SIZE(gcc_parent_names_8),
+ .parent_data = gcc_parent_data_8,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_rcg2_ops,
},
};
@@ -903,8 +929,8 @@ static struct clk_rcg2 mdp_clk_src = {
.freq_tbl = ftbl_mdp_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "mdp_clk_src",
- .parent_names = gcc_parent_names_9,
- .num_parents = ARRAY_SIZE(gcc_parent_names_9),
+ .parent_data = gcc_parent_data_9,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_9),
.ops = &clk_rcg2_ops,
},
};
@@ -922,8 +948,8 @@ static struct clk_rcg2 pcie_0_aux_clk_src = {
.freq_tbl = ftbl_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_aux_clk_src",
- .parent_names = gcc_parent_names_10,
- .num_parents = ARRAY_SIZE(gcc_parent_names_10),
+ .parent_data = gcc_parent_data_10,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_10),
.ops = &clk_rcg2_ops,
},
};
@@ -943,8 +969,8 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = {
.freq_tbl = ftbl_pcie_0_pipe_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pcie_0_pipe_clk_src",
- .parent_names = gcc_parent_names_11,
- .num_parents = ARRAY_SIZE(gcc_parent_names_11),
+ .parent_data = gcc_parent_data_11,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_11),
.ops = &clk_rcg2_ops,
},
};
@@ -956,8 +982,8 @@ static struct clk_rcg2 pclk0_clk_src = {
.parent_map = gcc_parent_map_12,
.clkr.hw.init = &(struct clk_init_data){
.name = "pclk0_clk_src",
- .parent_names = gcc_parent_names_12,
- .num_parents = ARRAY_SIZE(gcc_parent_names_12),
+ .parent_data = gcc_parent_data_12,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_12),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_pixel_ops,
},
@@ -977,8 +1003,8 @@ static struct clk_rcg2 pdm2_clk_src = {
.freq_tbl = ftbl_pdm2_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "pdm2_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -1005,8 +1031,8 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
.freq_tbl = ftbl_sdcc1_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_apps_clk_src",
- .parent_names = gcc_parent_names_13,
- .num_parents = ARRAY_SIZE(gcc_parent_names_13),
+ .parent_data = gcc_parent_data_13,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_13),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1025,8 +1051,8 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc1_ice_core_clk_src",
- .parent_names = gcc_parent_names_3,
- .num_parents = ARRAY_SIZE(gcc_parent_names_3),
+ .parent_data = gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
@@ -1051,8 +1077,8 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
.freq_tbl = ftbl_sdcc2_apps_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "sdcc2_apps_clk_src",
- .parent_names = gcc_parent_names_14,
- .num_parents = ARRAY_SIZE(gcc_parent_names_14),
+ .parent_data = gcc_parent_data_14,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_14),
.ops = &clk_rcg2_floor_ops,
},
};
@@ -1065,8 +1091,8 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
.freq_tbl = ftbl_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb20_mock_utmi_clk_src",
- .parent_names = gcc_parent_names_1,
- .num_parents = ARRAY_SIZE(gcc_parent_names_1),
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
@@ -1087,8 +1113,8 @@ static struct clk_rcg2 usb30_master_clk_src = {
.freq_tbl = ftbl_usb30_master_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_master_clk_src",
- .parent_names = gcc_parent_names_0,
- .num_parents = ARRAY_SIZE(gcc_parent_names_0),
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
.ops = &clk_rcg2_ops,
},
};
@@ -1101,8 +1127,8 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
.freq_tbl = ftbl_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb30_mock_utmi_clk_src",
- .parent_names = gcc_parent_names_1,
- .num_parents = ARRAY_SIZE(gcc_parent_names_1),
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
@@ -1115,8 +1141,8 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
.freq_tbl = ftbl_pcie_0_aux_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb3_phy_aux_clk_src",
- .parent_names = gcc_parent_names_1,
- .num_parents = ARRAY_SIZE(gcc_parent_names_1),
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_rcg2_ops,
},
};
@@ -1138,8 +1164,8 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
.freq_tbl = ftbl_usb_hs_system_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "usb_hs_system_clk_src",
- .parent_names = gcc_parent_names_3,
- .num_parents = ARRAY_SIZE(gcc_parent_names_3),
+ .parent_data = gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
.ops = &clk_rcg2_ops,
},
};
@@ -1152,8 +1178,8 @@ static struct clk_rcg2 vsync_clk_src = {
.freq_tbl = ftbl_esc0_clk_src,
.clkr.hw.init = &(struct clk_init_data){
.name = "vsync_clk_src",
- .parent_names = gcc_parent_names_15,
- .num_parents = ARRAY_SIZE(gcc_parent_names_15),
+ .parent_data = gcc_parent_data_15,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_15),
.ops = &clk_rcg2_ops,
},
};
@@ -1174,8 +1200,8 @@ static struct clk_rcg2 cdsp_bimc_clk_src = {
.freq_tbl = ftbl_cdsp_bimc_clk_src,
.clkr.hw.init = &(struct clk_init_data) {
.name = "cdsp_bimc_clk_src",
- .parent_names = gcc_parent_names_16,
- .num_parents = ARRAY_SIZE(gcc_parent_names_16),
+ .parent_data = gcc_parent_data_16,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_16),
.ops = &clk_rcg2_ops,
},
};
@@ -1188,8 +1214,8 @@ static struct clk_branch gcc_apss_ahb_clk = {
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_apss_ahb_clk",
- .parent_names = (const char *[]){
- "apss_ahb_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &apss_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1220,8 +1246,8 @@ static struct clk_branch gcc_bimc_gfx_clk = {
.hw.init = &(struct clk_init_data){
.name = "gcc_bimc_gfx_clk",
.ops = &clk_branch2_ops,
- .parent_names = (const char *[]){
- "gcc_apss_tcu_clk",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gcc_apss_tcu_clk.clkr.hw,
},
},
@@ -1249,8 +1275,8 @@ static struct clk_branch gcc_bimc_cdsp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data) {
.name = "gcc_bimc_cdsp_clk",
- .parent_names = (const char *[]) {
- "cdsp_bimc_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cdsp_bimc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1319,8 +1345,8 @@ static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup0_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup0_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_qup0_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1337,8 +1363,8 @@ static struct clk_branch gcc_blsp1_qup0_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup0_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup0_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_qup0_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1355,8 +1381,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup1_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1373,8 +1399,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup1_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup1_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_qup1_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1391,8 +1417,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup2_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1409,8 +1435,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup2_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup2_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_qup2_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1427,8 +1453,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup3_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1445,8 +1471,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup3_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup3_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_qup3_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1463,8 +1489,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup4_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_qup4_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1481,8 +1507,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_qup4_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_qup4_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_qup4_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1499,8 +1525,8 @@ static struct clk_branch gcc_blsp1_uart0_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart0_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart0_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_uart0_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1517,8 +1543,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart1_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart1_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_uart1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1535,8 +1561,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart2_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart2_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_uart2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1553,8 +1579,8 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp1_uart3_apps_clk",
- .parent_names = (const char *[]){
- "blsp1_uart3_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp1_uart3_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1584,8 +1610,8 @@ static struct clk_branch gcc_blsp2_qup0_i2c_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup0_i2c_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup0_i2c_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp2_qup0_i2c_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1602,8 +1628,8 @@ static struct clk_branch gcc_blsp2_qup0_spi_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_qup0_spi_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_qup0_spi_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp2_qup0_spi_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1620,8 +1646,8 @@ static struct clk_branch gcc_blsp2_uart0_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_blsp2_uart0_apps_clk",
- .parent_names = (const char *[]){
- "blsp2_uart0_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &blsp2_uart0_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1703,8 +1729,8 @@ static struct clk_branch gcc_eth_ptp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_eth_ptp_clk",
- .parent_names = (const char *[]){
- "emac_ptp_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &emac_ptp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1721,8 +1747,8 @@ static struct clk_branch gcc_eth_rgmii_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_eth_rgmii_clk",
- .parent_names = (const char *[]){
- "emac_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &emac_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1804,8 +1830,8 @@ static struct clk_branch gcc_cdsp_tbu_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data) {
.name = "gcc_cdsp_tbu_clk",
- .parent_names = (const char *[]) {
- "cdsp_bimc_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &cdsp_bimc_clk_src.clkr.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1822,8 +1848,8 @@ static struct clk_branch gcc_gp1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
- .parent_names = (const char *[]){
- "gp1_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1840,8 +1866,8 @@ static struct clk_branch gcc_gp2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
- .parent_names = (const char *[]){
- "gp2_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1858,8 +1884,8 @@ static struct clk_branch gcc_gp3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
- .parent_names = (const char *[]){
- "gp3_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1928,8 +1954,8 @@ static struct clk_branch gcc_mdss_byte0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_byte0_clk",
- .parent_names = (const char *[]){
- "byte0_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &byte0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1946,8 +1972,8 @@ static struct clk_branch gcc_mdss_esc0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_esc0_clk",
- .parent_names = (const char *[]){
- "esc0_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &esc0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1964,8 +1990,8 @@ static struct clk_branch gcc_mdss_hdmi_app_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_hdmi_app_clk",
- .parent_names = (const char *[]){
- "hdmi_app_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &hdmi_app_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -1982,8 +2008,8 @@ static struct clk_branch gcc_mdss_hdmi_pclk_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_hdmi_pclk_clk",
- .parent_names = (const char *[]){
- "hdmi_pclk_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &hdmi_pclk_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2000,8 +2026,8 @@ static struct clk_branch gcc_mdss_mdp_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_mdp_clk",
- .parent_names = (const char *[]){
- "mdp_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &mdp_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2018,8 +2044,8 @@ static struct clk_branch gcc_mdss_pclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_pclk0_clk",
- .parent_names = (const char *[]){
- "pclk0_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &pclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2036,8 +2062,8 @@ static struct clk_branch gcc_mdss_vsync_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_mdss_vsync_clk",
- .parent_names = (const char *[]){
- "vsync_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &vsync_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2067,8 +2093,8 @@ static struct clk_branch gcc_oxili_gfx3d_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_oxili_gfx3d_clk",
- .parent_names = (const char *[]){
- "gfx3d_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &gfx3d_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2085,8 +2111,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
.enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk",
- .parent_names = (const char *[]){
- "pcie_0_aux_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2129,8 +2155,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
.enable_mask = BIT(28),
.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_pipe_clk",
- .parent_names = (const char *[]){
- "pcie_0_pipe_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &pcie_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2188,8 +2214,8 @@ static struct clk_branch gcc_pdm2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
- .parent_names = (const char *[]){
- "pdm2_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2298,8 +2324,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
- .parent_names = (const char *[]){
- "sdcc1_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2316,8 +2342,8 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
- .parent_names = (const char *[]){
- "sdcc1_ice_core_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2360,8 +2386,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
- .parent_names = (const char *[]){
- "sdcc2_apps_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2391,8 +2417,8 @@ static struct clk_branch gcc_sys_noc_usb3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_clk",
- .parent_names = (const char *[]){
- "usb30_master_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch2_ops,
@@ -2421,8 +2447,8 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb20_mock_utmi_clk",
- .parent_names = (const char *[]){
- "usb20_mock_utmi_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &usb20_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2452,8 +2478,8 @@ static struct clk_branch gcc_usb30_master_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_master_clk",
- .parent_names = (const char *[]){
- "usb30_master_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &usb30_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2470,8 +2496,8 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_mock_utmi_clk",
- .parent_names = (const char *[]){
- "usb30_mock_utmi_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &usb30_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2501,8 +2527,8 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_phy_aux_clk",
- .parent_names = (const char *[]){
- "usb3_phy_aux_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &usb3_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@@ -2544,8 +2570,8 @@ static struct clk_branch gcc_usb_hs_system_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb_hs_system_clk",
- .parent_names = (const char *[]){
- "usb_hs_system_clk_src",
+ .parent_hws = (const struct clk_hw*[]) {
+ &usb_hs_system_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 11/16] clk: qcom: gcc-qcs404: sort out the cxo clock
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (9 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 10/16] clk: qcom: gcc-qcs404: use parent_hws/_data instead of parent_names Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 12/16] clk: qcom: gcc-qcs404: add support for GDSCs Dmitry Baryshkov
` (5 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
The GCC driver registers the cxo clock as a thin wrapper around board's
xo_board clock. Nowadays we can use the xo_board directly in all the
clocks that use it. Use the fw_name "cxo" for this clock.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-qcs404.c | 97 +++++++++++++++--------------------
1 file changed, 41 insertions(+), 56 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 2726a48f2d5c..fa2adf242648 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -44,14 +44,21 @@ enum {
P_XO,
};
+static const struct parent_map gcc_parent_map_1[] = {
+ { P_XO, 0 },
+};
+
+static const struct clk_parent_data gcc_parent_data_1[] = {
+ { .index = DT_XO, .name = "xo-board" },
+};
+
static struct clk_fixed_factor cxo = {
.mult = 1,
.div = 1,
.hw.init = &(struct clk_init_data){
.name = "cxo",
- .parent_data = &(const struct clk_parent_data) {
- .name = "xo-board",
- },
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.num_parents = 1,
.ops = &clk_fixed_factor_ops,
},
@@ -66,10 +73,8 @@ static struct clk_alpha_pll gpll0_sleep_clk_src = {
.enable_is_inverted = true,
.hw.init = &(struct clk_init_data){
.name = "gpll0_sleep_clk_src",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &cxo.hw,
- },
- .num_parents = 1,
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_alpha_pll_ops,
},
},
@@ -84,10 +89,8 @@ static struct clk_alpha_pll gpll0_out_main = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_out_main",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &cxo.hw,
- },
- .num_parents = 1,
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_alpha_pll_ops,
},
},
@@ -102,10 +105,8 @@ static struct clk_alpha_pll gpll0_ao_out_main = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gpll0_ao_out_main",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &cxo.hw,
- },
- .num_parents = 1,
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_IS_CRITICAL,
.ops = &clk_alpha_pll_fixed_ops,
},
@@ -120,10 +121,8 @@ static struct clk_alpha_pll gpll1_out_main = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gpll1_out_main",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &cxo.hw,
- },
- .num_parents = 1,
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_alpha_pll_ops,
},
},
@@ -153,10 +152,8 @@ static struct clk_alpha_pll gpll3_out_main = {
.clkr = {
.hw.init = &(struct clk_init_data){
.name = "gpll3_out_main",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &cxo.hw,
- },
- .num_parents = 1,
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_alpha_pll_ops,
},
},
@@ -170,10 +167,8 @@ static struct clk_alpha_pll gpll4_out_main = {
.enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){
.name = "gpll4_out_main",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &cxo.hw,
- },
- .num_parents = 1,
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_alpha_pll_ops,
},
},
@@ -189,10 +184,8 @@ static struct clk_pll gpll6 = {
.status_bit = 17,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll6",
- .parent_data = &(const struct clk_parent_data) {
- .hw = &cxo.hw,
- },
- .num_parents = 1,
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
.ops = &clk_pll_ops,
},
};
@@ -216,23 +209,15 @@ static const struct parent_map gcc_parent_map_0[] = {
};
static const struct clk_parent_data gcc_parent_data_0[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
};
static const struct clk_parent_data gcc_parent_data_ao_0[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_ao_out_main.clkr.hw },
};
-static const struct parent_map gcc_parent_map_1[] = {
- { P_XO, 0 },
-};
-
-static const struct clk_parent_data gcc_parent_data_1[] = {
- { .hw = &cxo.hw },
-};
-
static const struct parent_map gcc_parent_map_2[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
@@ -241,7 +226,7 @@ static const struct parent_map gcc_parent_map_2[] = {
};
static const struct clk_parent_data gcc_parent_data_2[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .hw = &gpll6_out_aux.hw },
{ .index = DT_SLEEP_CLK, .name = "sleep_clk" },
@@ -254,7 +239,7 @@ static const struct parent_map gcc_parent_map_3[] = {
};
static const struct clk_parent_data gcc_parent_data_3[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .hw = &gpll6_out_aux.hw },
};
@@ -265,7 +250,7 @@ static const struct parent_map gcc_parent_map_4[] = {
};
static const struct clk_parent_data gcc_parent_data_4[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll1_out_main.clkr.hw },
};
@@ -275,7 +260,7 @@ static const struct parent_map gcc_parent_map_5[] = {
};
static const struct clk_parent_data gcc_parent_data_5[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" },
};
@@ -285,7 +270,7 @@ static const struct parent_map gcc_parent_map_6[] = {
};
static const struct clk_parent_data gcc_parent_data_6[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK, .name = "dsi0pllbyte" },
};
@@ -297,7 +282,7 @@ static const struct parent_map gcc_parent_map_7[] = {
};
static const struct clk_parent_data gcc_parent_data_7[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .hw = &gpll3_out_main.clkr.hw },
{ .hw = &gpll6_out_aux.hw },
@@ -309,7 +294,7 @@ static const struct parent_map gcc_parent_map_8[] = {
};
static const struct clk_parent_data gcc_parent_data_8[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .index = DT_HDMI_PHY_PLL_CLK, .name = "hdmi_pll" },
};
@@ -321,7 +306,7 @@ static const struct parent_map gcc_parent_map_9[] = {
};
static const struct clk_parent_data gcc_parent_data_9[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" },
{ .hw = &gpll6_out_aux.hw },
@@ -333,7 +318,7 @@ static const struct parent_map gcc_parent_map_10[] = {
};
static const struct clk_parent_data gcc_parent_data_10[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .index = DT_SLEEP_CLK, .name = "sleep_clk" },
};
@@ -343,7 +328,7 @@ static const struct parent_map gcc_parent_map_11[] = {
};
static const struct clk_parent_data gcc_parent_data_11[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
};
@@ -353,7 +338,7 @@ static const struct parent_map gcc_parent_map_12[] = {
};
static const struct clk_parent_data gcc_parent_data_12[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK, .name = "dsi0pll" },
};
@@ -365,7 +350,7 @@ static const struct parent_map gcc_parent_map_13[] = {
};
static const struct clk_parent_data gcc_parent_data_13[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
{ .hw = &gpll4_out_main.clkr.hw },
{ .hw = &gpll6_out_aux.hw },
@@ -377,7 +362,7 @@ static const struct parent_map gcc_parent_map_14[] = {
};
static const struct clk_parent_data gcc_parent_data_14[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
};
@@ -386,7 +371,7 @@ static const struct parent_map gcc_parent_map_15[] = {
};
static const struct clk_parent_data gcc_parent_data_15[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
};
static const struct parent_map gcc_parent_map_16[] = {
@@ -395,7 +380,7 @@ static const struct parent_map gcc_parent_map_16[] = {
};
static const struct clk_parent_data gcc_parent_data_16[] = {
- { .hw = &cxo.hw },
+ { .index = DT_XO, .name = "xo-board" },
{ .hw = &gpll0_out_main.clkr.hw },
};
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 12/16] clk: qcom: gcc-qcs404: add support for GDSCs
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (10 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 11/16] clk: qcom: gcc-qcs404: sort out the cxo clock Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 13/16] arm64: dts: qcom: qcs404: use symbol names for PCIe resets Dmitry Baryshkov
` (4 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Add support for two GDSCs provided by this clock controller.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-qcs404.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index fa2adf242648..5f58dd82d3fe 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -19,6 +19,7 @@
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
+#include "gdsc.h"
#include "reset.h"
enum {
@@ -2591,6 +2592,22 @@ static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
},
};
+static struct gdsc mdss_gdsc = {
+ .gdscr = 0x4d078,
+ .pd = {
+ .name = "mdss",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
+static struct gdsc oxili_gdsc = {
+ .gdscr = 0x5901c,
+ .pd = {
+ .name = "oxili",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+};
+
static struct clk_hw *gcc_qcs404_hws[] = {
&cxo.hw,
};
@@ -2741,6 +2758,11 @@ static struct clk_regmap *gcc_qcs404_clocks[] = {
};
+static struct gdsc *gcc_qcs404_gdscs[] = {
+ [MDSS_GDSC] = &mdss_gdsc,
+ [OXILI_GDSC] = &oxili_gdsc,
+};
+
static const struct qcom_reset_map gcc_qcs404_resets[] = {
[GCC_GENI_IR_BCR] = { 0x0F000 },
[GCC_CDSP_RESTART] = { 0x18000 },
@@ -2783,6 +2805,8 @@ static const struct qcom_cc_desc gcc_qcs404_desc = {
.num_resets = ARRAY_SIZE(gcc_qcs404_resets),
.clk_hws = gcc_qcs404_hws,
.num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws),
+ .gdscs = gcc_qcs404_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_qcs404_gdscs),
};
static const struct of_device_id gcc_qcs404_match_table[] = {
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 13/16] arm64: dts: qcom: qcs404: use symbol names for PCIe resets
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (11 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 12/16] clk: qcom: gcc-qcs404: add support for GDSCs Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 14/16] arm64: dts: qcom: qcs404: add power-domains-cells to gcc node Dmitry Baryshkov
` (3 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
The commit e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") added names
for PCIe resets, but it did not change the existing qcs404.dtsi to use
these names. Do it now and use symbol names to make it easier to check
and modify the dtsi in future.
Fixes: e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index ffffaa7507cf..ffc4b081bb62 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -806,7 +806,7 @@ pcie_phy: phy@7786000 {
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
- <&gcc 21>;
+ <&gcc GCC_PCIE_0_PIPE_ARES>;
reset-names = "phy", "pipe";
clock-output-names = "pcie_0_pipe_clk";
@@ -1337,12 +1337,12 @@ pcie: pci@10000000 {
<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
clock-names = "iface", "aux", "master_bus", "slave_bus";
- resets = <&gcc 18>,
- <&gcc 17>,
- <&gcc 15>,
- <&gcc 19>,
+ resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
+ <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
<&gcc GCC_PCIE_0_BCR>,
- <&gcc 16>;
+ <&gcc GCC_PCIE_0_AHB_ARES>;
reset-names = "axi_m",
"axi_s",
"axi_m_sticky",
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 14/16] arm64: dts: qcom: qcs404: add power-domains-cells to gcc node
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (12 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 13/16] arm64: dts: qcom: qcs404: use symbol names for PCIe resets Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 15/16] arm64: dts: qcom: qcs404: add clocks to the " Dmitry Baryshkov
` (2 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
As gcc now provides two GDSCs, add #power-domain-cells property to the
gcc device node.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index ffc4b081bb62..b72542631337 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -729,6 +729,7 @@ gcc: clock-controller@1800000 {
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
assigned-clock-rates = <19200000>;
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 15/16] arm64: dts: qcom: qcs404: add clocks to the gcc node
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (13 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 14/16] arm64: dts: qcom: qcs404: add power-domains-cells to gcc node Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 16/16] arm64: dts: qcom: qcs404: add xo clock to rpm clock controller Dmitry Baryshkov
2022-12-27 18:04 ` (subset) [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Bjorn Andersson
16 siblings, 0 replies; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Populate the gcc node with the clocks and clock-names properties to
enable DT-based lookups for the parent clocks.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index b72542631337..9206ab13977f 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -731,6 +731,13 @@ gcc: clock-controller@1800000 {
#reset-cells = <1>;
#power-domain-cells = <1>;
+ clocks = <&xo_board>,
+ <&sleep_clk>,
+ <&pcie_phy>,
+ <0>,
+ <0>,
+ <0>;
+
assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
assigned-clock-rates = <19200000>;
};
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v2 16/16] arm64: dts: qcom: qcs404: add xo clock to rpm clock controller
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (14 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 15/16] arm64: dts: qcom: qcs404: add clocks to the " Dmitry Baryshkov
@ 2022-12-26 4:21 ` Dmitry Baryshkov
2022-12-27 11:33 ` Konrad Dybcio
2022-12-27 18:04 ` (subset) [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Bjorn Andersson
16 siblings, 1 reply; 19+ messages in thread
From: Dmitry Baryshkov @ 2022-12-26 4:21 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
Populate the rpm clock controller node with clocks and clock-names
properties.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 9206ab13977f..4721b3139df0 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -230,6 +230,8 @@ rpm_requests: glink-channel {
rpmcc: clock-controller {
compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
#clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
};
rpmpd: power-controller {
--
2.35.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v2 16/16] arm64: dts: qcom: qcs404: add xo clock to rpm clock controller
2022-12-26 4:21 ` [PATCH v2 16/16] arm64: dts: qcom: qcs404: add xo clock to rpm clock controller Dmitry Baryshkov
@ 2022-12-27 11:33 ` Konrad Dybcio
0 siblings, 0 replies; 19+ messages in thread
From: Konrad Dybcio @ 2022-12-27 11:33 UTC (permalink / raw)
To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Stephen Boyd,
Michael Turquette, Rob Herring, Krzysztof Kozlowski, Taniya Das
Cc: linux-arm-msm, linux-clk, devicetree
On 26.12.2022 05:21, Dmitry Baryshkov wrote:
> Populate the rpm clock controller node with clocks and clock-names
> properties.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index 9206ab13977f..4721b3139df0 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -230,6 +230,8 @@ rpm_requests: glink-channel {
> rpmcc: clock-controller {
> compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
> #clock-cells = <1>;
> + clocks = <&xo_board>;
> + clock-names = "xo";
> };
>
> rpmpd: power-controller {
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: (subset) [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
` (15 preceding siblings ...)
2022-12-26 4:21 ` [PATCH v2 16/16] arm64: dts: qcom: qcs404: add xo clock to rpm clock controller Dmitry Baryshkov
@ 2022-12-27 18:04 ` Bjorn Andersson
16 siblings, 0 replies; 19+ messages in thread
From: Bjorn Andersson @ 2022-12-27 18:04 UTC (permalink / raw)
To: dmitry.baryshkov, robh+dt, mturquette, sboyd,
krzysztof.kozlowski+dt, agross, quic_tdas, konrad.dybcio
Cc: linux-clk, linux-arm-msm, devicetree
On Mon, 26 Dec 2022 06:21:38 +0200, Dmitry Baryshkov wrote:
> This patchset reworks and improves the Qualcomm QCS404 global clock
> controller driver and it's platform usage.
>
> It fixes some omissions (MDSS and oxili GDSCs, incorrect clock names,
> direct number usage in the qcs404.dtsi). Then it converts the gcc driver
> to use parent_data/parent_hws where prefereable and finally applies
> these features and fixes to the qcs404.dtsi.
>
> [...]
Applied, thanks!
[13/16] arm64: dts: qcom: qcs404: use symbol names for PCIe resets
commit: 41a37d157a613444c97e8f71a5fb2a21116b70d7
[14/16] arm64: dts: qcom: qcs404: add power-domains-cells to gcc node
commit: 1eb309964e6384eda56c2d2816c3857c0b7c3ea6
[15/16] arm64: dts: qcom: qcs404: add clocks to the gcc node
commit: 3494938a7e9e436be5dc989aecc1c800ecf2dba9
[16/16] arm64: dts: qcom: qcs404: add xo clock to rpm clock controller
commit: f961fd2f6717c34a20a6951dcf9782a29e648f6c
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 19+ messages in thread