[PATCH v2 00/11] LoongArch: Better backtraces

[PATCH v2 00/11] LoongArch: Better backtraces

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Hi,

Here are a bunch of tweaks to the backtrace code, so the Quality of Life
for unfortunate LoongArch kernel devs (including but not limited to,
myself) could be marginally improved by relieving them of having to
mentally decode the register names and CSR bitfields.

Before:

> [   17.879976] $ 0   : 0000000000000000 9000000000cc980c 90000001002cc000 90000001002cfe30
> [   17.887936] $ 4   : 0000000000000010 9000000000f1f770 90000001002cc000 9000000000cc3468
> [   17.895895] $ 8   : 900000010028fd00 0000000000000001 000055558e569190 0000000000000004
> [   17.903853] $12   : 0000000000000000 0000000000000004 9000000001026000 900000000132b2d8
> [   17.911811] $16   : 9000000001026000 000000006674b539 9000000000d51d10 0000000000000001
> [   17.919769] $20   : 0000000000000000 900000000025c27c 0000000000000004 0000000000000002
> [   17.927727] $24   : 900000000102e5b0 900000000102e508 0000000000000000 0000000000000004
> [   17.935686] $28   : 9000000009007840 0000000000000004 0000000000000000 0000000000000004
> [   17.943644] era   : 90000000002215a0 __arch_cpu_idle+0x20/0x24
> [   17.949438] ra    : 9000000000cc980c default_idle_call+0x34/0x5c
> [   17.955406] CSR crmd: 000000b0
> [   17.955408] CSR prmd: 00000004
> [   17.958521] CSR euen: 00000000
> [   17.961635] CSR ecfg: 00071c1c
> [   17.964748] CSR estat: 00001000
> [   17.971062] ExcCode : 0 (SubCode 0)
> [   17.974522] PrId  : 0014c010 (Loongson-64bit)

After:

> [   45.869200]  pc 90000000002215a0 ra 9000000000ce86bc tp 90000001002cc000
> [   45.875858]  sp 90000001002cfe30 a0 0000000000000018 a1 9000000000f41ee0
> [   45.882516]  a2 0000000000000001 a3 000000000000000a a4 90000000098032c0
> [   45.889173]  a5 000000000000001b a6 000000008ea4398a a7 0000000000000004
> [   45.895831]  t0 0000000000000000 t1 0000000000000004 t2 0000000000003c00
> [   45.902488]  t3 0000000000cccccd t4 ffffffffffffffff t5 000000010d1ff6c8
> [   45.909146]  t6 0000000000000000 t7 0000000000000000 t8 000000000000005b
> [   45.915803] r21 0000000a390fa6c0 s9 0000000000000001 s0 0000000000000003
> [   45.922460]  s1 90000000010565c0 s2 9000000001056518 s3 0000000000000000
> [   45.929118]  s4 0000000000000004 s5 0000000000000004 s6 9000000000228194
> [   45.935775]  s7 900000000102e220 s8 9000000100093e58
> [   45.940704]    pc: 90000000002215a0 __arch_cpu_idle+0x20/0x24
> [   45.946412]    ra: 9000000000ce86bc default_idle_call+0x34/0x5c
> [   45.952294]  crmd: 000000b0 (-WE DACM=CC DACF=CC +PG -DA -IE PLV0)
> [   45.958443]  prmd: 00000004 (-PWE +PIE PPLV0)
> [   45.962772]  euen: 00000000 (-BTE -ASXE -SXE -FPE)
> [   45.967532]  ecfg: 00071c1c (VS=7 LIE=2-4,10-12)
> [   45.972119] estat: 00001000 [INT] (EsubCode=0 ECode=0 IS=12)
> [   45.977741]  prid: 0014c010 (Loongson-64bit)

Please review, and let the bikeshedding begin!

Changes in v2:

- rebased and tested on top of next-20221226
- removed the mass symbol renamings per Huacai's suggestion (but the
  output still uses the ISA manual names because users are expected to
  be more familiar with those)

WANG Xuerui (11):
  LoongArch: Clean up the architectural interrupt definitions
  LoongArch: Add exception subcode definitions for the watchpoint
    exception
  LoongArch: Print GPRs with ABI names when showing registers
  LoongArch: Print symbol info for PC and $ra only for kernel-mode
    contexts
  LoongArch: Fix format of CSR lines during show_regs
  LoongArch: Humanize the CRMD line when showing registers
  LoongArch: Humanize the PRMD line when showing registers
  LoongArch: Humanize the EUEN line when showing registers
  LoongArch: Humanize the ECFG line when showing registers
  LoongArch: Humanize the ESTAT line when showing registers
  LoongArch: Use lowercase ISA manual names for BADV and CPUCFG.PRID
    lines in show_regs

 arch/loongarch/include/asm/loongarch.h |  60 ++++---
 arch/loongarch/kernel/irq.c            |   2 +-
 arch/loongarch/kernel/perf_event.c     |   2 +-
 arch/loongarch/kernel/time.c           |   2 +-
 arch/loongarch/kernel/traps.c          | 220 +++++++++++++++++++++----
 5 files changed, 227 insertions(+), 59 deletions(-)

-- 
2.38.1

[PATCH v2 01/11] LoongArch: Clean up the architectural interrupt definitions

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

While interrupts are assigned ECodes `64 + interrupt number`, all
existing use sites of interrupt numbers want the 64 subtracted.
Re-arrange the definitions so that the actual interrupt number is used
everywhere, and make EXCCODE_INT_END inclusive as it is more intuitive
that way.

While at it, document an ISA manual erratum that is confirmed by Huacai
but not yet officially fixed in the official (Chinese) version of the
manual, namely the total number of architectural interrupts should be
(at least) 14 instead of 13. Relevant bitfields and masks have been
adjusted as well.

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/include/asm/loongarch.h | 56 ++++++++++++++++----------
 arch/loongarch/kernel/irq.c            |  2 +-
 arch/loongarch/kernel/perf_event.c     |  2 +-
 arch/loongarch/kernel/time.c           |  2 +-
 arch/loongarch/kernel/traps.c          |  2 +-
 5 files changed, 38 insertions(+), 26 deletions(-)

diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 7f8d57a61c8b..4910969928f0 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -311,8 +311,8 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
 #define  CSR_ECFG_VS_WIDTH		3
 #define  CSR_ECFG_VS			(_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT)
 #define  CSR_ECFG_IM_SHIFT		0
-#define  CSR_ECFG_IM_WIDTH		13
-#define  CSR_ECFG_IM			(_ULCAST_(0x1fff) << CSR_ECFG_IM_SHIFT)
+#define  CSR_ECFG_IM_WIDTH		14
+#define  CSR_ECFG_IM			(_ULCAST_(0x3fff) << CSR_ECFG_IM_SHIFT)
 
 #define LOONGARCH_CSR_ESTAT		0x5	/* Exception status */
 #define  CSR_ESTAT_ESUBCODE_SHIFT	22
@@ -322,8 +322,8 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
 #define  CSR_ESTAT_EXC_WIDTH		6
 #define  CSR_ESTAT_EXC			(_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT)
 #define  CSR_ESTAT_IS_SHIFT		0
-#define  CSR_ESTAT_IS_WIDTH		15
-#define  CSR_ESTAT_IS			(_ULCAST_(0x7fff) << CSR_ESTAT_IS_SHIFT)
+#define  CSR_ESTAT_IS_WIDTH		14
+#define  CSR_ESTAT_IS			(_ULCAST_(0x3fff) << CSR_ESTAT_IS_SHIFT)
 
 #define LOONGARCH_CSR_ERA		0x6	/* ERA */
 
@@ -1087,7 +1087,7 @@ static __always_inline void iocsr_write64(u64 val, u32 reg)
 #define ECFGF_IPI		(_ULCAST_(1) << ECFGB_IPI)
 #define ECFGF(hwirq)		(_ULCAST_(1) << hwirq)
 
-#define ESTATF_IP		0x00001fff
+#define ESTATF_IP		0x00003fff
 
 #define LOONGARCH_IOCSR_FEATURES	0x8
 #define  IOCSRF_TEMP			BIT_ULL(0)
@@ -1415,23 +1415,35 @@ __BUILD_CSR_OP(tlbidx)
 	#define EXCSUBCODE_GCHC		1	/* Hardware caused */
 #define EXCCODE_SE		25	/* Security */
 
-#define EXCCODE_INT_START   64
-#define EXCCODE_SIP0        64
-#define EXCCODE_SIP1        65
-#define EXCCODE_IP0         66
-#define EXCCODE_IP1         67
-#define EXCCODE_IP2         68
-#define EXCCODE_IP3         69
-#define EXCCODE_IP4         70
-#define EXCCODE_IP5         71
-#define EXCCODE_IP6         72
-#define EXCCODE_IP7         73
-#define EXCCODE_PMC         74 /* Performance Counter */
-#define EXCCODE_TIMER       75
-#define EXCCODE_IPI         76
-#define EXCCODE_NMI         77
-#define EXCCODE_INT_END     78
-#define EXCCODE_INT_NUM	    (EXCCODE_INT_END - EXCCODE_INT_START)
+/*
+ * Interrupt numbers
+ *
+ * The LoongArch ISA manual v1.02 says there are 13 interrupts in total (see
+ * the description about CSR.ESTAT, Volume 1, section 7.4.6), namely omitting
+ * the NMI.
+ * Unfortunately in this case the manual is wrong, and the definitions here
+ * shall prevail. In other words, CSR.ECFG.LIE and CSR.ESTAT.IS are 14 bits
+ * wide, instead of 13 as the manual suggests otherwise.
+ */
+#define INT_SWI0	0	/* Software Interrupts */
+#define INT_SWI1	1
+#define INT_HWI0	2	/* Hardware Interrupts */
+#define INT_HWI1	3
+#define INT_HWI2	4
+#define INT_HWI3	5
+#define INT_HWI4	6
+#define INT_HWI5	7
+#define INT_HWI6	8
+#define INT_HWI7	9
+#define INT_PCOV	10	/* Performance Counter Overflow */
+#define INT_TI		11	/* Timer */
+#define INT_IPI		12
+#define INT_NMI		13
+
+/* ExcCodes corresponding to interrupts */
+#define EXCCODE_INT_NUM		(INT_NMI + 1)
+#define EXCCODE_INT_START	64
+#define EXCCODE_INT_END		(EXCCODE_INT_START + EXCCODE_INT_NUM - 1)
 
 /* FPU register names */
 #define LOONGARCH_FCSR0	$r0
diff --git a/arch/loongarch/kernel/irq.c b/arch/loongarch/kernel/irq.c
index 0524bf1169b7..883e5066ae44 100644
--- a/arch/loongarch/kernel/irq.c
+++ b/arch/loongarch/kernel/irq.c
@@ -92,7 +92,7 @@ static int __init get_ipi_irq(void)
 	struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
 
 	if (d)
-		return irq_create_mapping(d, EXCCODE_IPI - EXCCODE_INT_START);
+		return irq_create_mapping(d, INT_IPI);
 
 	return -EINVAL;
 }
diff --git a/arch/loongarch/kernel/perf_event.c b/arch/loongarch/kernel/perf_event.c
index 707bd32e5c4f..ff28f99b47d7 100644
--- a/arch/loongarch/kernel/perf_event.c
+++ b/arch/loongarch/kernel/perf_event.c
@@ -461,7 +461,7 @@ static int get_pmc_irq(void)
 	struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
 
 	if (d)
-		return irq_create_mapping(d, EXCCODE_PMC - EXCCODE_INT_START);
+		return irq_create_mapping(d, INT_PCOV);
 
 	return -EINVAL;
 }
diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c
index a6576dea590c..c76a2a22e8e3 100644
--- a/arch/loongarch/kernel/time.c
+++ b/arch/loongarch/kernel/time.c
@@ -133,7 +133,7 @@ static int get_timer_irq(void)
 	struct irq_domain *d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
 
 	if (d)
-		return irq_create_mapping(d, EXCCODE_TIMER - EXCCODE_INT_START);
+		return irq_create_mapping(d, INT_TI);
 
 	return -EINVAL;
 }
diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 7ea62faeeadb..ee5454bdcc74 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -743,7 +743,7 @@ void __init trap_init(void)
 	long i;
 
 	/* Set interrupt vector handler */
-	for (i = EXCCODE_INT_START; i < EXCCODE_INT_END; i++)
+	for (i = EXCCODE_INT_START; i <= EXCCODE_INT_END; i++)
 		set_handler(i * VECSIZE, handle_vint, VECSIZE);
 
 	set_handler(EXCCODE_ADE * VECSIZE, handle_ade, VECSIZE);
-- 
2.38.1

[PATCH v2 02/11] LoongArch: Add exception subcode definitions for the watchpoint exception

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/include/asm/loongarch.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 4910969928f0..d087acaf206d 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -1405,7 +1405,9 @@ __BUILD_CSR_OP(tlbidx)
 #define EXCCODE_FPE		18	/* Floating Point Exception */
 	#define EXCSUBCODE_FPE		0	/* Floating Point Exception */
 	#define EXCSUBCODE_VFPE		1	/* Vector Exception */
-#define EXCCODE_WATCH		19	/* Watch address reference */
+#define EXCCODE_WATCH		19	/* WatchPoint Exception */
+	#define EXCSUBCODE_WPEF		0	/* ... on instruction Fetch */
+	#define EXCSUBCODE_WPEM		1	/* ... on Memory access */
 #define EXCCODE_BTDIS		20	/* Binary Trans. Disabled */
 #define EXCCODE_BTE		21	/* Binary Trans. Exception */
 #define EXCCODE_PSI		22	/* Guest Privileged Error */
-- 
2.38.1

[PATCH v2 03/11] LoongArch: Print GPRs with ABI names when showing registers

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Print 3 registers per line to fit the entire line within 75 columns even
with timestamp prefixed to each line, to ease future copy-pastes for all.

And show PC (CSR.ERA) in place of $zero, like what arch/riscv does.

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 36 ++++++++++++++++++++++-------------
 1 file changed, 23 insertions(+), 13 deletions(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index ee5454bdcc74..d05a3e14279b 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -161,22 +161,32 @@ static void __show_regs(const struct pt_regs *regs)
 	const int field = 2 * sizeof(unsigned long);
 	unsigned int excsubcode;
 	unsigned int exccode;
-	int i;
 
 	show_regs_print_info(KERN_DEFAULT);
 
-	/*
-	 * Saved main processor registers
-	 */
-	for (i = 0; i < 32; ) {
-		if ((i % 4) == 0)
-			printk("$%2d   :", i);
-		pr_cont(" %0*lx", field, regs->regs[i]);
-
-		i++;
-		if ((i % 4) == 0)
-			pr_cont("\n");
-	}
+	/* Print PC and GPRs, 3 per row to fit output in 75 columns */
+	pr_cont(" pc %0*lx ra %0*lx tp %0*lx\n",
+		field, regs->csr_era, field, regs->regs[1], field, regs->regs[2]);
+	pr_cont(" sp %0*lx a0 %0*lx a1 %0*lx\n",
+		field, regs->regs[3], field, regs->regs[4], field, regs->regs[5]);
+	pr_cont(" a2 %0*lx a3 %0*lx a4 %0*lx\n",
+		field, regs->regs[6], field, regs->regs[7], field, regs->regs[8]);
+	pr_cont(" a5 %0*lx a6 %0*lx a7 %0*lx\n",
+		field, regs->regs[9], field, regs->regs[10], field, regs->regs[11]);
+	pr_cont(" t0 %0*lx t1 %0*lx t2 %0*lx\n",
+		field, regs->regs[12], field, regs->regs[13], field, regs->regs[14]);
+	pr_cont(" t3 %0*lx t4 %0*lx t5 %0*lx\n",
+		field, regs->regs[15], field, regs->regs[16], field, regs->regs[17]);
+	pr_cont(" t6 %0*lx t7 %0*lx t8 %0*lx\n",
+		field, regs->regs[18], field, regs->regs[19], field, regs->regs[20]);
+	pr_cont("r21 %0*lx s9 %0*lx s0 %0*lx\n",
+		field, regs->regs[21], field, regs->regs[22], field, regs->regs[23]);
+	pr_cont(" s1 %0*lx s2 %0*lx s3 %0*lx\n",
+		field, regs->regs[24], field, regs->regs[25], field, regs->regs[26]);
+	pr_cont(" s4 %0*lx s5 %0*lx s6 %0*lx\n",
+		field, regs->regs[27], field, regs->regs[28], field, regs->regs[29]);
+	pr_cont(" s7 %0*lx s8 %0*lx\n",
+		field, regs->regs[30], field, regs->regs[31]);
 
 	/*
 	 * Saved csr registers
-- 
2.38.1

[PATCH v2 04/11] LoongArch: Print symbol info for PC and $ra only for kernel-mode contexts

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Otherwise the addresses wouldn't make sense at all. And show "pc"
instead of "era" for a tiny bit of user friendliness.

While at it, align the "map keys" to maintain right-alignment with the
"estat:" line too.

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index d05a3e14279b..f0720b219006 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -188,14 +188,12 @@ static void __show_regs(const struct pt_regs *regs)
 	pr_cont(" s7 %0*lx s8 %0*lx\n",
 		field, regs->regs[30], field, regs->regs[31]);
 
-	/*
-	 * Saved csr registers
-	 */
-	printk("era   : %0*lx %pS\n", field, regs->csr_era,
-	       (void *) regs->csr_era);
-	printk("ra    : %0*lx %pS\n", field, regs->regs[1],
-	       (void *) regs->regs[1]);
+	if (!user_mode(regs)) {
+		pr_cont("   pc: %0*lx %pS\n", field, regs->csr_era, (void *) regs->csr_era);
+		pr_cont("   ra: %0*lx %pS\n", field, regs->regs[1], (void *) regs->regs[1]);
+	}
 
+	/* Print important CSRs */
 	printk("CSR crmd: %08lx	", regs->csr_crmd);
 	printk("CSR prmd: %08lx	", regs->csr_prmd);
 	printk("CSR euen: %08lx	", regs->csr_euen);
-- 
2.38.1

[PATCH v2 05/11] LoongArch: Fix format of CSR lines during show_regs

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Use lowercase CSR names throughout, and right-align the keys. The "CSR"
part is inferrable from context, hence dropped for more horizontal
space.

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index f0720b219006..68524dea5c8c 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -194,13 +194,11 @@ static void __show_regs(const struct pt_regs *regs)
 	}
 
 	/* Print important CSRs */
-	printk("CSR crmd: %08lx	", regs->csr_crmd);
-	printk("CSR prmd: %08lx	", regs->csr_prmd);
-	printk("CSR euen: %08lx	", regs->csr_euen);
-	printk("CSR ecfg: %08lx	", regs->csr_ecfg);
-	printk("CSR estat: %08lx	", regs->csr_estat);
-
-	pr_cont("\n");
+	pr_cont(" crmd: %08lx\n", regs->csr_crmd);
+	pr_cont(" prmd: %08lx\n", regs->csr_prmd);
+	pr_cont(" euen: %08lx\n", regs->csr_euen);
+	pr_cont(" ecfg: %08lx\n", regs->csr_ecfg);
+	pr_cont("estat: %08lx\n", regs->csr_estat);
 
 	exccode = ((regs->csr_estat) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
 	excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT;
-- 
2.38.1

[PATCH v2 06/11] LoongArch: Humanize the CRMD line when showing registers

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Example output looks like:

[   xx.xxxxxx]  crmd: 000000b0 (-WE DACM=CC DACF=CC +PG -DA -IE PLV0)

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 46 ++++++++++++++++++++++++++++++++++-
 1 file changed, 45 insertions(+), 1 deletion(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 68524dea5c8c..c56d5c12c901 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -3,6 +3,7 @@
  * Author: Huacai Chen <chenhuacai@loongson.cn>
  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
  */
+#include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/bug.h>
 #include <linux/compiler.h>
@@ -156,6 +157,49 @@ static void show_code(unsigned int *pc, bool user)
 	pr_cont("\n");
 }
 
+static void print_bool_fragment(const char *key, unsigned long val, bool first)
+{
+	/* e.g. "+PG", "-DA" */
+	pr_cont("%s%c%s", first ? "" : " ", val ? '+' : '-', key);
+}
+
+static void print_plv_fragment(const char *key, int val)
+{
+	/* e.g. "PLV0", "PPLV3" */
+	pr_cont(" %s%d", key, val);
+}
+
+static void print_memory_type_fragment(const char *key, unsigned long val)
+{
+	/* e.g. "DATM=WUC" */
+	const char *humanized_type = NULL;
+
+	switch (val) {
+	case 0: humanized_type = "SUC"; break;
+	case 1: humanized_type = "CC"; break;
+	case 2: humanized_type = "WUC"; break;
+	}
+
+	if (humanized_type) {
+		pr_cont(" %s=%s", key, humanized_type);
+	} else {
+		pr_cont(" %s=Reserved(%lu)", key, val);
+	}
+}
+
+static void print_crmd(unsigned long x)
+{
+	pr_cont(" crmd: %08lx (", x);
+	print_bool_fragment("WE", FIELD_GET(CSR_CRMD_WE, x), true);
+	print_memory_type_fragment("DACM", FIELD_GET(CSR_CRMD_DACM, x));
+	print_memory_type_fragment("DACF", FIELD_GET(CSR_CRMD_DACF, x));
+	print_bool_fragment("PG", FIELD_GET(CSR_CRMD_PG, x), false);
+	print_bool_fragment("DA", FIELD_GET(CSR_CRMD_DA, x), false);
+	print_bool_fragment("IE", FIELD_GET(CSR_CRMD_IE, x), false);
+	print_plv_fragment("PLV", (int) FIELD_GET(CSR_CRMD_PLV, x));
+	pr_cont(")\n");
+}
+
 static void __show_regs(const struct pt_regs *regs)
 {
 	const int field = 2 * sizeof(unsigned long);
@@ -194,7 +238,7 @@ static void __show_regs(const struct pt_regs *regs)
 	}
 
 	/* Print important CSRs */
-	pr_cont(" crmd: %08lx\n", regs->csr_crmd);
+	print_crmd(regs->csr_crmd);
 	pr_cont(" prmd: %08lx\n", regs->csr_prmd);
 	pr_cont(" euen: %08lx\n", regs->csr_euen);
 	pr_cont(" ecfg: %08lx\n", regs->csr_ecfg);
-- 
2.38.1

[PATCH v2 07/11] LoongArch: Humanize the PRMD line when showing registers

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Example output looks like:

[   xx.xxxxxx]  prmd: 00000004 (-PWE +PIE PPLV0)

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index c56d5c12c901..d1404d8c5a5c 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -200,6 +200,15 @@ static void print_crmd(unsigned long x)
 	pr_cont(")\n");
 }
 
+static void print_prmd(unsigned long x)
+{
+	pr_cont(" prmd: %08lx (", x);
+	print_bool_fragment("PWE", FIELD_GET(CSR_PRMD_PWE, x), true);
+	print_bool_fragment("PIE", FIELD_GET(CSR_PRMD_PIE, x), false);
+	print_plv_fragment("PPLV", (int) FIELD_GET(CSR_PRMD_PPLV, x));
+	pr_cont(")\n");
+}
+
 static void __show_regs(const struct pt_regs *regs)
 {
 	const int field = 2 * sizeof(unsigned long);
@@ -239,7 +248,7 @@ static void __show_regs(const struct pt_regs *regs)
 
 	/* Print important CSRs */
 	print_crmd(regs->csr_crmd);
-	pr_cont(" prmd: %08lx\n", regs->csr_prmd);
+	print_prmd(regs->csr_prmd);
 	pr_cont(" euen: %08lx\n", regs->csr_euen);
 	pr_cont(" ecfg: %08lx\n", regs->csr_ecfg);
 	pr_cont("estat: %08lx\n", regs->csr_estat);
-- 
2.38.1

[PATCH v2 08/11] LoongArch: Humanize the EUEN line when showing registers

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Example output looks like:

[   xx.xxxxxx]  euen: 00000000 (-BTE -ASXE -SXE -FPE)

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index d1404d8c5a5c..a43f95631cea 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -209,6 +209,16 @@ static void print_prmd(unsigned long x)
 	pr_cont(")\n");
 }
 
+static void print_euen(unsigned long x)
+{
+	pr_cont(" euen: %08lx (", x);
+	print_bool_fragment("BTE", FIELD_GET(CSR_EUEN_LBTEN, x), true);
+	print_bool_fragment("ASXE", FIELD_GET(CSR_EUEN_LASXEN, x), false);
+	print_bool_fragment("SXE", FIELD_GET(CSR_EUEN_LSXEN, x), false);
+	print_bool_fragment("FPE", FIELD_GET(CSR_EUEN_FPEN, x), false);
+	pr_cont(")\n");
+}
+
 static void __show_regs(const struct pt_regs *regs)
 {
 	const int field = 2 * sizeof(unsigned long);
@@ -249,7 +259,7 @@ static void __show_regs(const struct pt_regs *regs)
 	/* Print important CSRs */
 	print_crmd(regs->csr_crmd);
 	print_prmd(regs->csr_prmd);
-	pr_cont(" euen: %08lx\n", regs->csr_euen);
+	print_euen(regs->csr_euen);
 	pr_cont(" ecfg: %08lx\n", regs->csr_ecfg);
 	pr_cont("estat: %08lx\n", regs->csr_estat);
 
-- 
2.38.1

[PATCH v2 09/11] LoongArch: Humanize the ECFG line when showing registers

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Example output looks like:

[   xx.xxxxxx]  ecfg: 00071c1c (VS=7 LIE=2-4,10-12)

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index a43f95631cea..2b26e610cc8f 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -187,6 +187,12 @@ static void print_memory_type_fragment(const char *key, unsigned long val)
 	}
 }
 
+static void print_intr_fragment(const char *key, unsigned long val)
+{
+	/* e.g. "LIE=0-1,3,5-7" */
+	pr_cont(" %s=%*pbl", key, EXCCODE_INT_NUM, &val);
+}
+
 static void print_crmd(unsigned long x)
 {
 	pr_cont(" crmd: %08lx (", x);
@@ -219,6 +225,13 @@ static void print_euen(unsigned long x)
 	pr_cont(")\n");
 }
 
+static void print_ecfg(unsigned long x)
+{
+	pr_cont(" ecfg: %08lx (VS=%d", x, (int) FIELD_GET(CSR_ECFG_VS, x));
+	print_intr_fragment("LIE", FIELD_GET(CSR_ECFG_IM, x));
+	pr_cont(")\n");
+}
+
 static void __show_regs(const struct pt_regs *regs)
 {
 	const int field = 2 * sizeof(unsigned long);
@@ -260,7 +273,7 @@ static void __show_regs(const struct pt_regs *regs)
 	print_crmd(regs->csr_crmd);
 	print_prmd(regs->csr_prmd);
 	print_euen(regs->csr_euen);
-	pr_cont(" ecfg: %08lx\n", regs->csr_ecfg);
+	print_ecfg(regs->csr_ecfg);
 	pr_cont("estat: %08lx\n", regs->csr_estat);
 
 	exccode = ((regs->csr_estat) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
-- 
2.38.1

[PATCH v2 10/11] LoongArch: Humanize the ESTAT line when showing registers

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Example output looks like:

[   xx.xxxxxx] estat: 00001000 [INT] (EsubCode=0 ECode=0 IS=12)

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 86 ++++++++++++++++++++++++++++++++---
 1 file changed, 79 insertions(+), 7 deletions(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 2b26e610cc8f..7dcb64ab5de8 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -232,11 +232,87 @@ static void print_ecfg(unsigned long x)
 	pr_cont(")\n");
 }
 
+static const char *humanize_exc_name(unsigned int ecode, unsigned int esubcode)
+{
+	/*
+	 * Right now the kernel source refers to the exceptions using mostly
+	 * MIPS-esque names, but LoongArch users and developers are probably
+	 * more familiar with those in the ISA manual, so we are going to
+	 * print out the latter. Expect much friction between the two sides
+	 * below...
+	 */
+	switch (ecode) {
+	case EXCCODE_RSV: return "INT";
+	case EXCCODE_TLBL: return "PIL";
+	case EXCCODE_TLBS: return "PIS";
+	case EXCCODE_TLBI: return "PIF";
+	case EXCCODE_TLBM: return "PME";
+	case EXCCODE_TLBNR: return "PNR";
+	case EXCCODE_TLBNX: return "PNX";
+	case EXCCODE_TLBPE: return "PPI";
+	case EXCCODE_ADE:
+		switch (esubcode) {
+		case EXSUBCODE_ADEF: return "ADEF";
+		case EXSUBCODE_ADEM: return "ADEM";
+		}
+		break;
+	case EXCCODE_ALE: return "ALE";
+	case EXCCODE_OOB: return "BCE";
+	case EXCCODE_SYS: return "SYS";
+	case EXCCODE_BP: return "BRK";
+	case EXCCODE_INE: return "INE";
+	case EXCCODE_IPE: return "IPE";
+	case EXCCODE_FPDIS: return "FPD";
+	case EXCCODE_LSXDIS: return "SXD";
+	case EXCCODE_LASXDIS: return "ASXD";
+	case EXCCODE_FPE:
+		switch (esubcode) {
+		case EXCSUBCODE_FPE: return "FPE";
+		case EXCSUBCODE_VFPE: return "VFPE";
+		}
+		break;
+	case EXCCODE_WATCH:
+		switch (esubcode) {
+		case EXCSUBCODE_WPEF: return "WPEF";
+		case EXCSUBCODE_WPEM: return "WPEM";
+		}
+		break;
+	case EXCCODE_BTDIS: return "BTD";
+	case EXCCODE_BTE: return "BTE";
+	case EXCCODE_PSI: return "GSPR";
+	case EXCCODE_HYP: return "HVC";
+	case EXCCODE_GCM:
+		switch (esubcode) {
+		case EXCSUBCODE_GCSC: return "GCSC";
+		case EXCSUBCODE_GCHC: return "GCHC";
+		}
+		break;
+	/*
+	 * The manual did not mention the EXCCODE_SE case, but print out it
+	 * nevertheless.
+	 */
+	case EXCCODE_SE: return "SE";
+	}
+
+	return "???";
+}
+
+static void print_estat(unsigned long x)
+{
+	unsigned int ecode = FIELD_GET(CSR_ESTAT_EXC, x);
+	unsigned int esubcode = FIELD_GET(CSR_ESTAT_ESUBCODE, x);
+
+	pr_cont("estat: %08lx [%s] (EsubCode=%d ECode=%d", x,
+		humanize_exc_name(ecode, esubcode), (int) esubcode,
+		(int) ecode);
+	print_intr_fragment("IS", FIELD_GET(CSR_ESTAT_IS, x));
+	pr_cont(")\n");
+}
+
 static void __show_regs(const struct pt_regs *regs)
 {
 	const int field = 2 * sizeof(unsigned long);
-	unsigned int excsubcode;
-	unsigned int exccode;
+	unsigned int exccode = FIELD_GET(CSR_ESTAT_EXC, regs->csr_estat);
 
 	show_regs_print_info(KERN_DEFAULT);
 
@@ -274,11 +350,7 @@ static void __show_regs(const struct pt_regs *regs)
 	print_prmd(regs->csr_prmd);
 	print_euen(regs->csr_euen);
 	print_ecfg(regs->csr_ecfg);
-	pr_cont("estat: %08lx\n", regs->csr_estat);
-
-	exccode = ((regs->csr_estat) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
-	excsubcode = ((regs->csr_estat) & CSR_ESTAT_ESUBCODE) >> CSR_ESTAT_ESUBCODE_SHIFT;
-	printk("ExcCode : %x (SubCode %x)\n", exccode, excsubcode);
+	print_estat(regs->csr_estat);
 
 	if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE)
 		printk("BadVA : %0*lx\n", field, regs->csr_badvaddr);
-- 
2.38.1

[PATCH v2 11/11] LoongArch: Use lowercase ISA manual names for BADV and CPUCFG.PRID lines in show_regs

[WANG Xuerui]

From: WANG Xuerui <git@xen0n.name>

Signed-off-by: WANG Xuerui <git@xen0n.name>
---
 arch/loongarch/kernel/traps.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/loongarch/kernel/traps.c b/arch/loongarch/kernel/traps.c
index 7dcb64ab5de8..48c5247a74a8 100644
--- a/arch/loongarch/kernel/traps.c
+++ b/arch/loongarch/kernel/traps.c
@@ -353,9 +353,9 @@ static void __show_regs(const struct pt_regs *regs)
 	print_estat(regs->csr_estat);
 
 	if (exccode >= EXCCODE_TLBL && exccode <= EXCCODE_ALE)
-		printk("BadVA : %0*lx\n", field, regs->csr_badvaddr);
+		printk(" badv: %0*lx\n", field, regs->csr_badvaddr);
 
-	printk("PrId  : %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
+	printk(" prid: %08x (%s)\n", read_cpucfg(LOONGARCH_CPUCFG0),
 	       cpu_family_string());
 }
 
-- 
2.38.1

Re: [PATCH v2 00/11] LoongArch: Better backtraces

[Huacai Chen]

Hi, Xuerui,

V2 is better than V1 for me, but I still have some concerns.

On Thu, Dec 29, 2022 at 1:33 PM WANG Xuerui <kernel@xen0n.name> wrote:
>
> From: WANG Xuerui <git@xen0n.name>
>
> Hi,
>
> Here are a bunch of tweaks to the backtrace code, so the Quality of Life
> for unfortunate LoongArch kernel devs (including but not limited to,
> myself) could be marginally improved by relieving them of having to
> mentally decode the register names and CSR bitfields.
>
> Before:
>
> > [   17.879976] $ 0   : 0000000000000000 9000000000cc980c 90000001002cc000 90000001002cfe30
> > [   17.887936] $ 4   : 0000000000000010 9000000000f1f770 90000001002cc000 9000000000cc3468
> > [   17.895895] $ 8   : 900000010028fd00 0000000000000001 000055558e569190 0000000000000004
> > [   17.903853] $12   : 0000000000000000 0000000000000004 9000000001026000 900000000132b2d8
> > [   17.911811] $16   : 9000000001026000 000000006674b539 9000000000d51d10 0000000000000001
> > [   17.919769] $20   : 0000000000000000 900000000025c27c 0000000000000004 0000000000000002
> > [   17.927727] $24   : 900000000102e5b0 900000000102e508 0000000000000000 0000000000000004
> > [   17.935686] $28   : 9000000009007840 0000000000000004 0000000000000000 0000000000000004
> > [   17.943644] era   : 90000000002215a0 __arch_cpu_idle+0x20/0x24
> > [   17.949438] ra    : 9000000000cc980c default_idle_call+0x34/0x5c
> > [   17.955406] CSR crmd: 000000b0
> > [   17.955408] CSR prmd: 00000004
> > [   17.958521] CSR euen: 00000000
> > [   17.961635] CSR ecfg: 00071c1c
> > [   17.964748] CSR estat: 00001000
> > [   17.971062] ExcCode : 0 (SubCode 0)
> > [   17.974522] PrId  : 0014c010 (Loongson-64bit)
>
> After:
>
> > [   45.869200]  pc 90000000002215a0 ra 9000000000ce86bc tp 90000001002cc000
Though r0 is always 0 in hardware, but we use pt_regs->regs[0] for
syscall restart flag, is that sometimes useful? And you give the pc
below, which means something duplicated.

> > [   45.875858]  sp 90000001002cfe30 a0 0000000000000018 a1 9000000000f41ee0
> > [   45.882516]  a2 0000000000000001 a3 000000000000000a a4 90000000098032c0
> > [   45.889173]  a5 000000000000001b a6 000000008ea4398a a7 0000000000000004
> > [   45.895831]  t0 0000000000000000 t1 0000000000000004 t2 0000000000003c00
> > [   45.902488]  t3 0000000000cccccd t4 ffffffffffffffff t5 000000010d1ff6c8
> > [   45.909146]  t6 0000000000000000 t7 0000000000000000 t8 000000000000005b
> > [   45.915803] r21 0000000a390fa6c0 s9 0000000000000001 s0 0000000000000003
In kernel we can use u0 here, I think.

> > [   45.922460]  s1 90000000010565c0 s2 9000000001056518 s3 0000000000000000
> > [   45.929118]  s4 0000000000000004 s5 0000000000000004 s6 9000000000228194
> > [   45.935775]  s7 900000000102e220 s8 9000000100093e58
> > [   45.940704]    pc: 90000000002215a0 __arch_cpu_idle+0x20/0x24
I don't know whether pc is equivalant to era in everyone's brain, but
not in mime. :)

Huacai
> > [   45.946412]    ra: 9000000000ce86bc default_idle_call+0x34/0x5c
> > [   45.952294]  crmd: 000000b0 (-WE DACM=CC DACF=CC +PG -DA -IE PLV0)
> > [   45.958443]  prmd: 00000004 (-PWE +PIE PPLV0)
> > [   45.962772]  euen: 00000000 (-BTE -ASXE -SXE -FPE)
> > [   45.967532]  ecfg: 00071c1c (VS=7 LIE=2-4,10-12)
> > [   45.972119] estat: 00001000 [INT] (EsubCode=0 ECode=0 IS=12)
> > [   45.977741]  prid: 0014c010 (Loongson-64bit)
>
> Please review, and let the bikeshedding begin!
>
> Changes in v2:
>
> - rebased and tested on top of next-20221226
> - removed the mass symbol renamings per Huacai's suggestion (but the
>   output still uses the ISA manual names because users are expected to
>   be more familiar with those)
>
> WANG Xuerui (11):
>   LoongArch: Clean up the architectural interrupt definitions
>   LoongArch: Add exception subcode definitions for the watchpoint
>     exception
>   LoongArch: Print GPRs with ABI names when showing registers
>   LoongArch: Print symbol info for PC and $ra only for kernel-mode
>     contexts
>   LoongArch: Fix format of CSR lines during show_regs
>   LoongArch: Humanize the CRMD line when showing registers
>   LoongArch: Humanize the PRMD line when showing registers
>   LoongArch: Humanize the EUEN line when showing registers
>   LoongArch: Humanize the ECFG line when showing registers
>   LoongArch: Humanize the ESTAT line when showing registers
>   LoongArch: Use lowercase ISA manual names for BADV and CPUCFG.PRID
>     lines in show_regs
>
>  arch/loongarch/include/asm/loongarch.h |  60 ++++---
>  arch/loongarch/kernel/irq.c            |   2 +-
>  arch/loongarch/kernel/perf_event.c     |   2 +-
>  arch/loongarch/kernel/time.c           |   2 +-
>  arch/loongarch/kernel/traps.c          | 220 +++++++++++++++++++++----
>  5 files changed, 227 insertions(+), 59 deletions(-)
>
> --
> 2.38.1
>