[PATCH v2 1/7] arm64: dts: qcom: sm8450: add spmi node

[PATCH v2 1/7] arm64: dts: qcom: sm8450: add spmi node

[Konrad Dybcio]

From: Vinod Koul <vkoul@kernel.org>

Add the spmi bus as found in the SM8450 SoC

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
[Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
v1 -> v2:
No changes

 arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 570475040d95..b9b59c5223eb 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2715,6 +2715,28 @@ aoss_qmp: power-controller@c300000 {
 			#clock-cells = <0>;
 		};
 
+		spmi_bus: spmi@c42d000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0 0x0c400000 0 0x00003000>,
+			      <0 0x0c500000 0 0x00400000>,
+			      <0 0x0c440000 0 0x00080000>,
+			      <0 0x0c4c0000 0 0x00010000>,
+			      <0 0x0c42d000 0 0x00010000>;
+			reg-names = "core",
+				    "chnls",
+				    "obsrvr",
+				    "intr",
+				    "cnfg";
+			interrupt-names = "periph_irq";
+			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+			qcom,ee = <0>;
+			qcom,channel = <0>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+		};
+
 		ipcc: mailbox@ed18000 {
 			compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
 			reg = <0 0x0ed18000 0 0x1000>;
-- 
2.39.0

[PATCH v2 2/7] arm64: dts: qcom: sm8450-nagara: Include PMIC DTSIs

[Konrad Dybcio]

Now that SPMI is finally in place, include the DTSIs of PMICs present
on Nagara.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
v1 -> v2:
No changes

 arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
index 45ee922de4e8..e29fb7adc780 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
@@ -5,6 +5,12 @@
 
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "sm8450.dtsi"
+#include "pm8350.dtsi"
+#include "pm8350b.dtsi"
+#include "pm8350c.dtsi"
+#include "pm8450.dtsi"
+#include "pmk8350.dtsi"
+#include "pmr735a.dtsi"
 
 /delete-node/ &adsp_mem;
 /delete-node/ &rmtfs_mem;
-- 
2.39.0

[PATCH v2 3/7] arm64: dts: qcom: sm8450-nagara: Add GPIO line names for PMIC GPIOs

[Konrad Dybcio]

Sony ever so graciously provides GPIO line names in their downstream
kernel (though sometimes they are not 100% accurate and you can judge
that by simply looking at them and with what drivers they are used).

Add these to the PDX223&224 DTSIs to better document the hardware.

Diff between 223 and 224:
pm8350b
< 			  "CAM_PWR_LD_EN",
> 			  "NC",

pm8350c
<			  "RGBC_IR_PWR_EN",
> 			  "NC",

Which is due to different camera power wiring on 223 and lack of a
ToF sensor on 224.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
v1 -> v2:
No changes

 .../qcom/sm8450-sony-xperia-nagara-pdx223.dts | 23 ++++++++++++++++
 .../qcom/sm8450-sony-xperia-nagara-pdx224.dts | 23 ++++++++++++++++
 .../dts/qcom/sm8450-sony-xperia-nagara.dtsi   | 27 +++++++++++++++++++
 3 files changed, 73 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts
index b83500316a81..561cd4f09ab7 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts
@@ -13,6 +13,29 @@ / {
 	compatible = "sony,pdx223", "qcom,sm8450";
 };
 
+&pm8350b_gpios {
+	gpio-line-names = "CAM_PWR_A_CS", /* GPIO_1 */
+			  "NC",
+			  "NC",
+			  "NC",
+			  "SNAPSHOT_N",
+			  "CAM_PWR_LD_EN",
+			  "NC",
+			  "FOCUS_N";
+};
+
+&pm8350c_gpios {
+	gpio-line-names = "FL_STROBE_TRIG_WIDE", /* GPIO_1 */
+			  "FL_STROBE_TRIG_TELE",
+			  "WLC_ID",
+			  "WLC_TXPWR_EN",
+			  "NC",
+			  "RGBC_IR_PWR_EN",
+			  "NC",
+			  "NC",
+			  "WIDEC_PWR_EN";
+};
+
 &tlmm {
 	gpio-line-names = "NC", /* GPIO_0 */
 			  "NC",
diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts
index 13c2fc4bccfc..fc9d74d0f227 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts
@@ -20,6 +20,29 @@ imx563_vdig_vreg: imx563-vdig-regulator {
 	};
 };
 
+&pm8350b_gpios {
+	gpio-line-names = "CAM_PWR_A_CS", /* GPIO_1 */
+			  "NC",
+			  "NC",
+			  "NC",
+			  "SNAPSHOT_N",
+			  "NC",
+			  "NC",
+			  "FOCUS_N";
+};
+
+&pm8350c_gpios {
+	gpio-line-names = "FL_STROBE_TRIG_WIDE", /* GPIO_1 */
+			  "FL_STROBE_TRIG_TELE",
+			  "WLC_ID",
+			  "WLC_TXPWR_EN",
+			  "NC",
+			  "NC", /* RGBCIR uses a PMIC vreg, so it's most likely NC. */
+			  "NC",
+			  "NC",
+			  "WIDEC_PWR_EN";
+};
+
 &tlmm {
 	gpio-line-names = "TELE_SPI_MISO", /* GPIO_0 */
 			  "TELE_SPI_MOSI", /* SONY says NC, but it only makes sense this way.. */
diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
index e29fb7adc780..8e128efcb128 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
@@ -551,6 +551,33 @@ &pcie0_phy {
 	status = "okay";
 };
 
+&pm8350_gpios {
+	gpio-line-names = "ASSIGN1_THERM", /* GPIO_1 */
+			  "LCD_ID",
+			  "SDR_MMW_THERM",
+			  "RF_ID",
+			  "NC",
+			  "VOL_DOWN_N",
+			  "NC",
+			  "NC",
+			  "NC",
+			  "PM8350_OPTION"; /* GPIO_10 */
+};
+
+&pm8450_gpios {
+	gpio-line-names = "FP_LDO_EN", /* GPIO_1 */
+			  "",
+			  "",
+			  "";
+};
+
+&pmk8350_gpios {
+	gpio-line-names = "NC", /* GPIO_1 */
+			  "NC",
+			  "DISP_THERM",
+			  "PMK8350_OPTION";
+};
+
 &remoteproc_adsp {
 	firmware-name = "qcom/sm8350/Sony/nagara/adsp.mbn";
 	status = "okay";
-- 
2.39.0

[PATCH v2 4/7] arm64: dts: qcom: sm8450-nagara: Add GPIO keys

[Konrad Dybcio]

With PMIC GPIOs now available, set up required pin settings and add
gpio-keys.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
v1 -> v2:
- gpio-key,wakeup -> wakeup-source

 .../dts/qcom/sm8450-sony-xperia-nagara.dtsi   | 61 +++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
index 8e128efcb128..0e139921b3e3 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
@@ -27,6 +27,41 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
+	gpio-keys {
+		compatible = "gpio-keys";
+		label = "gpio-keys";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>;
+
+		key-camera-focus {
+			label = "Camera Focus";
+			linux,code = <KEY_CAMERA_FOCUS>;
+			gpios = <&pm8350b_gpios 8 GPIO_ACTIVE_LOW>;
+			debounce-interval = <15>;
+			linux,can-disable;
+			wakeup-source;
+		};
+
+		key-camera-snapshot {
+			label = "Camera Snapshot";
+			linux,code = <KEY_CAMERA>;
+			gpios = <&pm8350b_gpios 5 GPIO_ACTIVE_LOW>;
+			debounce-interval = <15>;
+			linux,can-disable;
+			wakeup-source;
+		};
+
+		key-volume-down {
+			label = "Volume Down";
+			linux,code = <KEY_VOLUMEDOWN>;
+			gpios = <&pm8350_gpios 6 GPIO_ACTIVE_LOW>;
+			debounce-interval = <15>;
+			linux,can-disable;
+			wakeup-source;
+		};
+	};
+
 	reserved-memory {
 		adsp_mem: memory@85700000 {
 			reg = <0x0 0x85700000 0x0 0x2800000>;
@@ -562,6 +597,32 @@ &pm8350_gpios {
 			  "NC",
 			  "NC",
 			  "PM8350_OPTION"; /* GPIO_10 */
+
+	vol_down_n: vol-down-n-state {
+		pins = "gpio6";
+		function = "normal";
+		power-source = <1>;
+		bias-pull-up;
+		input-enable;
+	};
+};
+
+&pm8350b_gpios {
+	snapshot_n: snapshot-n-state {
+		pins = "gpio5";
+		function = "normal";
+		power-source = <0>;
+		bias-pull-up;
+		input-enable;
+	};
+
+	focus_n: focus-n-state {
+		pins = "gpio8";
+		function = "normal";
+		power-source = <0>;
+		bias-pull-up;
+		input-enable;
+	};
 };
 
 &pm8450_gpios {
-- 
2.39.0

[PATCH v2 5/7] arm64: dts: qcom: sm8450-nagara: Set up camera regulators

[Konrad Dybcio]

Set up gpio-controlled fixed regulators for camera on PDX223 and fix
up the existing ones in common and PDX224 trees.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
v1 -> v2:
No changes

 .../qcom/sm8450-sony-xperia-nagara-pdx223.dts | 38 +++++++++++++++++++
 .../qcom/sm8450-sony-xperia-nagara-pdx224.dts | 15 +++++++-
 .../dts/qcom/sm8450-sony-xperia-nagara.dtsi   | 16 +++++++-
 3 files changed, 65 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts
index 561cd4f09ab7..daf2f91f356e 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts
@@ -11,6 +11,26 @@
 / {
 	model = "Sony Xperia 1 IV";
 	compatible = "sony,pdx223", "qcom,sm8450";
+
+	imx316_lvdd_regulator: imx316-lvdd-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "imx316_lvdd_regulator";
+		gpio = <&pm8350b_gpios 6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&cam_pwr_ld_en>;
+	};
+
+	tcs3490_vdd_regulator: rgbcir-vdd-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "tcs3490_vdd_regulator";
+		gpio = <&pm8350c_gpios 6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&rgbc_ir_pwr_en>;
+	};
 };
 
 &pm8350b_gpios {
@@ -22,6 +42,15 @@ &pm8350b_gpios {
 			  "CAM_PWR_LD_EN",
 			  "NC",
 			  "FOCUS_N";
+
+	cam_pwr_ld_en: cam-pwr-ld-en-state {
+		pins = "gpio6";
+		function = "normal";
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+		power-source = <0>;
+		drive-push-pull;
+		output-low;
+	};
 };
 
 &pm8350c_gpios {
@@ -34,6 +63,15 @@ &pm8350c_gpios {
 			  "NC",
 			  "NC",
 			  "WIDEC_PWR_EN";
+
+	rgbc_ir_pwr_en: rgbc-ir-pwr-en-state {
+		pins = "gpio6";
+		function = "normal";
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+		power-source = <1>;
+		drive-push-pull;
+		output-low;
+	};
 };
 
 &tlmm {
diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts
index fc9d74d0f227..dc4de2d3fe48 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts
+++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx224.dts
@@ -12,11 +12,14 @@ / {
 	model = "Sony Xperia 5 IV";
 	compatible = "sony,pdx224", "qcom,sm8450";
 
-	imx563_vdig_vreg: imx563-vdig-regulator {
+	imx563_vdig_regulator: imx563-vdig-regulator {
 		compatible = "regulator-fixed";
-		regulator-name = "imx563_vdig_vreg";
+		regulator-name = "imx563_vdig_regulator";
 		gpio = <&tlmm 22 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&uwidec_pwr_en>;
 	};
 };
 
@@ -254,4 +257,12 @@ &tlmm {
 			  "APPS_I2C_0_SCL",
 			  "CCI_I2C3_SDA",
 			  "CCI_I2C3_SCL";
+
+	uwidec_pwr_en: uwidec-pwr-en-state {
+		pins = "gpio22";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
 };
diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
index 0e139921b3e3..a8c4df2696e3 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
@@ -3,6 +3,7 @@
  * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org>
  */
 
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
 #include "sm8450.dtsi"
 #include "pm8350.dtsi"
@@ -93,11 +94,14 @@ ramoops@ffc00000 {
 	};
 
 	/* Sadly, the voltages for these GPIO regulators are unknown. */
-	imx650_vana_vreg: imx650-vana-regulator {
+	imx650_vana_regulator: imx650-vana-regulator {
 		compatible = "regulator-fixed";
-		regulator-name = "imx650_vana_vreg";
+		regulator-name = "imx650_vana_regulator";
 		gpio = <&tlmm 23 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&telec_pwr_en>;
 	};
 
 	vph_pwr: vph-pwr-regulator {
@@ -703,6 +707,14 @@ ts_int_default: ts-int-default-state {
 		input-enable;
 	};
 
+	telec_pwr_en: telec-pwr-en-state {
+		pins = "gpio23";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
 	sdc2_card_det_n: sd-card-det-n-state {
 		pins = "gpio92";
 		function = "gpio";
-- 
2.39.0

[PATCH v2 6/7] arm64: dts: qcom: sm8450-nagara: Enable PMIC RESIN+PON

[Konrad Dybcio]

Enable the power and volume up buttons, connected to PON and RESIN
respectively.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
v1 -> v2:
No changes

 arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
index a8c4df2696e3..15709d73b264 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
@@ -643,6 +643,15 @@ &pmk8350_gpios {
 			  "PMK8350_OPTION";
 };
 
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEUP>;
+	status = "okay";
+};
+
 &remoteproc_adsp {
 	firmware-name = "qcom/sm8350/Sony/nagara/adsp.mbn";
 	status = "okay";
-- 
2.39.0

[PATCH v2 7/7] arm64: dts: qcom: sm8450-nagara: Configure SLG51000 PMIC

[Konrad Dybcio]

Nagara devices use the Dialog SLG51000 PMIC for powering some camera
sensors. Add the required nodes to support it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
v1 -> v2:
No changes

 .../dts/qcom/sm8450-sony-xperia-nagara.dtsi   | 62 ++++++++++++++++++-
 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
index 15709d73b264..8869495c397e 100644
--- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
@@ -513,7 +513,58 @@ &i2c5 {
 	clock-frequency = <400000>;
 	status = "okay";
 
-	/* Dialog SLG51000 CMIC @ 75 */
+	pmic@75 {
+		compatible = "dlg,slg51000";
+		reg = <0x75>;
+		dlg,cs-gpios = <&pm8350b_gpios 1 GPIO_ACTIVE_HIGH>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&cam_pwr_a_cs>;
+
+		regulators {
+			slg51000_a_ldo1: ldo1 {
+				regulator-name = "slg51000_a_ldo1";
+				regulator-min-microvolt = <2400000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			slg51000_a_ldo2: ldo2 {
+				regulator-name = "slg51000_a_ldo2";
+				regulator-min-microvolt = <2400000>;
+				regulator-max-microvolt = <3300000>;
+			};
+
+			slg51000_a_ldo3: ldo3 {
+				regulator-name = "slg51000_a_ldo3";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3750000>;
+			};
+
+			slg51000_a_ldo4: ldo4 {
+				regulator-name = "slg51000_a_ldo4";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3750000>;
+			};
+
+			slg51000_a_ldo5: ldo5 {
+				regulator-name = "slg51000_a_ldo5";
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1200000>;
+			};
+
+			slg51000_a_ldo6: ldo6 {
+				regulator-name = "slg51000_a_ldo6";
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1200000>;
+			};
+
+			slg51000_a_ldo7: ldo7 {
+				regulator-name = "slg51000_a_ldo7";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3750000>;
+			};
+		};
+	};
 };
 
 &i2c9 {
@@ -612,6 +663,15 @@ vol_down_n: vol-down-n-state {
 };
 
 &pm8350b_gpios {
+	cam_pwr_a_cs: cam-pwr-a-cs-state {
+		pins = "gpio1";
+		function = "normal";
+		qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
+		power-source = <1>;
+		drive-push-pull;
+		output-high;
+	};
+
 	snapshot_n: snapshot-n-state {
 		pins = "gpio5";
 		function = "normal";
-- 
2.39.0

Re: [PATCH v2 1/7] arm64: dts: qcom: sm8450: add spmi node

[Krzysztof Kozlowski]

On 29/12/2022 11:32, Konrad Dybcio wrote:
> From: Vinod Koul <vkoul@kernel.org>
> 
> Add the spmi bus as found in the SM8450 SoC
> 
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> [Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list]
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> v1 -> v2:
> No changes
> 
>  arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 570475040d95..b9b59c5223eb 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -2715,6 +2715,28 @@ aoss_qmp: power-controller@c300000 {
>  			#clock-cells = <0>;
>  		};
>  
> +		spmi_bus: spmi@c42d000 {

Hmm looks different than reg.

> +			compatible = "qcom,spmi-pmic-arb";
> +			reg = <0 0x0c400000 0 0x00003000>,
> +			      <0 0x0c500000 0 0x00400000>,
> +			      <0 0x0c440000 0 0x00080000>,
> +			      <0 0x0c4c0000 0 0x00010000>,
> +			      <0 0x0c42d000 0 0x00010000>;
x

Best regards,
Krzysztof

Re: [PATCH v2 1/7] arm64: dts: qcom: sm8450: add spmi node

[Konrad Dybcio]

On 29.12.2022 11:42, Krzysztof Kozlowski wrote:
> On 29/12/2022 11:32, Konrad Dybcio wrote:
>> From: Vinod Koul <vkoul@kernel.org>
>>
>> Add the spmi bus as found in the SM8450 SoC
>>
>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>> [Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list]
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> v1 -> v2:
>> No changes
>>
>>  arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index 570475040d95..b9b59c5223eb 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -2715,6 +2715,28 @@ aoss_qmp: power-controller@c300000 {
>>  			#clock-cells = <0>;
>>  		};
>>  
>> +		spmi_bus: spmi@c42d000 {
> 
> Hmm looks different than reg.
> 
>> +			compatible = "qcom,spmi-pmic-arb";
>> +			reg = <0 0x0c400000 0 0x00003000>,
>> +			      <0 0x0c500000 0 0x00400000>,
>> +			      <0 0x0c440000 0 0x00080000>,
>> +			      <0 0x0c4c0000 0 0x00010000>,
>> +			      <0 0x0c42d000 0 0x00010000>;
> x
Hm, my guess would be that Vinod chose to put the "cnfg" reg
instead of "core" in the unit address, as 8450 has 2 SPMI bus
hosts and they both share the core reg, so it would have been
impossible to have two spmi@core nodes..

Konrad
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v2 1/7] arm64: dts: qcom: sm8450: add spmi node

[Krzysztof Kozlowski]

On 29/12/2022 11:45, Konrad Dybcio wrote:
> 
> 
> On 29.12.2022 11:42, Krzysztof Kozlowski wrote:
>> On 29/12/2022 11:32, Konrad Dybcio wrote:
>>> From: Vinod Koul <vkoul@kernel.org>
>>>
>>> Add the spmi bus as found in the SM8450 SoC
>>>
>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>> [Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list]
>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> ---
>>> v1 -> v2:
>>> No changes
>>>
>>>  arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++
>>>  1 file changed, 22 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> index 570475040d95..b9b59c5223eb 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>> @@ -2715,6 +2715,28 @@ aoss_qmp: power-controller@c300000 {
>>>  			#clock-cells = <0>;
>>>  		};
>>>  
>>> +		spmi_bus: spmi@c42d000 {
>>
>> Hmm looks different than reg.
>>
>>> +			compatible = "qcom,spmi-pmic-arb";
>>> +			reg = <0 0x0c400000 0 0x00003000>,
>>> +			      <0 0x0c500000 0 0x00400000>,
>>> +			      <0 0x0c440000 0 0x00080000>,
>>> +			      <0 0x0c4c0000 0 0x00010000>,
>>> +			      <0 0x0c42d000 0 0x00010000>;
>> x
> Hm, my guess would be that Vinod chose to put the "cnfg" reg
> instead of "core" in the unit address, as 8450 has 2 SPMI bus
> hosts and they both share the core reg, so it would have been
> impossible to have two spmi@core nodes..

Eh? SM8450 has 2 SPMI hosts both using 0x0c400000? How does that work?
Usually address can be mapped only once.

Where is the second SPMI? I cannot find it in linux-next.


Best regards,
Krzysztof

Re: [PATCH v2 1/7] arm64: dts: qcom: sm8450: add spmi node

[Konrad Dybcio]

On 29.12.2022 11:57, Krzysztof Kozlowski wrote:
> On 29/12/2022 11:45, Konrad Dybcio wrote:
>>
>>
>> On 29.12.2022 11:42, Krzysztof Kozlowski wrote:
>>> On 29/12/2022 11:32, Konrad Dybcio wrote:
>>>> From: Vinod Koul <vkoul@kernel.org>
>>>>
>>>> Add the spmi bus as found in the SM8450 SoC
>>>>
>>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>>> [Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list]
>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>> ---
>>>> v1 -> v2:
>>>> No changes
>>>>
>>>>  arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++
>>>>  1 file changed, 22 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>> index 570475040d95..b9b59c5223eb 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>> @@ -2715,6 +2715,28 @@ aoss_qmp: power-controller@c300000 {
>>>>  			#clock-cells = <0>;
>>>>  		};
>>>>  
>>>> +		spmi_bus: spmi@c42d000 {
>>>
>>> Hmm looks different than reg.
>>>
>>>> +			compatible = "qcom,spmi-pmic-arb";
>>>> +			reg = <0 0x0c400000 0 0x00003000>,
>>>> +			      <0 0x0c500000 0 0x00400000>,
>>>> +			      <0 0x0c440000 0 0x00080000>,
>>>> +			      <0 0x0c4c0000 0 0x00010000>,
>>>> +			      <0 0x0c42d000 0 0x00010000>;
>>> x
>> Hm, my guess would be that Vinod chose to put the "cnfg" reg
>> instead of "core" in the unit address, as 8450 has 2 SPMI bus
>> hosts and they both share the core reg, so it would have been
>> impossible to have two spmi@core nodes..
> 
> Eh? SM8450 has 2 SPMI hosts both using 0x0c400000? How does that work?
> Usually address can be mapped only once.
No idea either!

> 
> Where is the second SPMI? I cannot find it in linux-next.
It's only there on downstream and I'm not sure how useful it is
really, only some debug subdevice is attached to it.. Perhaps
we could ignore its existence for now and I could use the core
reg in unit address for spmi0?

Konrad
> 
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v2 1/7] arm64: dts: qcom: sm8450: add spmi node

[Krzysztof Kozlowski]

On 29/12/2022 12:04, Konrad Dybcio wrote:
> 
> 
> On 29.12.2022 11:57, Krzysztof Kozlowski wrote:
>> On 29/12/2022 11:45, Konrad Dybcio wrote:
>>>
>>>
>>> On 29.12.2022 11:42, Krzysztof Kozlowski wrote:
>>>> On 29/12/2022 11:32, Konrad Dybcio wrote:
>>>>> From: Vinod Koul <vkoul@kernel.org>
>>>>>
>>>>> Add the spmi bus as found in the SM8450 SoC
>>>>>
>>>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
>>>>> [Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list]
>>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>>>> ---
>>>>> v1 -> v2:
>>>>> No changes
>>>>>
>>>>>  arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++
>>>>>  1 file changed, 22 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>>> index 570475040d95..b9b59c5223eb 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>>>>> @@ -2715,6 +2715,28 @@ aoss_qmp: power-controller@c300000 {
>>>>>  			#clock-cells = <0>;
>>>>>  		};
>>>>>  
>>>>> +		spmi_bus: spmi@c42d000 {
>>>>
>>>> Hmm looks different than reg.
>>>>
>>>>> +			compatible = "qcom,spmi-pmic-arb";
>>>>> +			reg = <0 0x0c400000 0 0x00003000>,
>>>>> +			      <0 0x0c500000 0 0x00400000>,
>>>>> +			      <0 0x0c440000 0 0x00080000>,
>>>>> +			      <0 0x0c4c0000 0 0x00010000>,
>>>>> +			      <0 0x0c42d000 0 0x00010000>;
>>>> x
>>> Hm, my guess would be that Vinod chose to put the "cnfg" reg
>>> instead of "core" in the unit address, as 8450 has 2 SPMI bus
>>> hosts and they both share the core reg, so it would have been
>>> impossible to have two spmi@core nodes..
>>
>> Eh? SM8450 has 2 SPMI hosts both using 0x0c400000? How does that work?
>> Usually address can be mapped only once.
> No idea either!
> 
>>
>> Where is the second SPMI? I cannot find it in linux-next.
> It's only there on downstream and I'm not sure how useful it is
> really, only some debug subdevice is attached to it.. Perhaps
> we could ignore its existence for now and I could use the core
> reg in unit address for spmi0?

I see it indeed in downstream. core, chnls and obsrvr IO are the same.
There is quite of debug devices attached.

There is a comment in PMIC arbiter code to use a IO mapping allowing
simultaneous mappings, so this is actually valid.

Anyway, DT expects unit address to match first reg, so if we want to
have second PMIC, we need to change the order of reg entries.

We can ignore this problem till we add second PMIC...

Best regards,
Krzysztof

Re: [PATCH v2 1/7] arm64: dts: qcom: sm8450: add spmi node

[Bjorn Andersson]

On Thu, Dec 29, 2022 at 11:57:58AM +0100, Krzysztof Kozlowski wrote:
> On 29/12/2022 11:45, Konrad Dybcio wrote:
> > 
> > 
> > On 29.12.2022 11:42, Krzysztof Kozlowski wrote:
> >> On 29/12/2022 11:32, Konrad Dybcio wrote:
> >>> From: Vinod Koul <vkoul@kernel.org>
> >>>
> >>> Add the spmi bus as found in the SM8450 SoC
> >>>
> >>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> >>> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> >>> [Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list]
> >>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> >>> ---
> >>> v1 -> v2:
> >>> No changes
> >>>
> >>>  arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++
> >>>  1 file changed, 22 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> >>> index 570475040d95..b9b59c5223eb 100644
> >>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> >>> @@ -2715,6 +2715,28 @@ aoss_qmp: power-controller@c300000 {
> >>>  			#clock-cells = <0>;
> >>>  		};
> >>>  
> >>> +		spmi_bus: spmi@c42d000 {
> >>
> >> Hmm looks different than reg.
> >>
> >>> +			compatible = "qcom,spmi-pmic-arb";
> >>> +			reg = <0 0x0c400000 0 0x00003000>,
> >>> +			      <0 0x0c500000 0 0x00400000>,
> >>> +			      <0 0x0c440000 0 0x00080000>,
> >>> +			      <0 0x0c4c0000 0 0x00010000>,
> >>> +			      <0 0x0c42d000 0 0x00010000>;
> >> x
> > Hm, my guess would be that Vinod chose to put the "cnfg" reg
> > instead of "core" in the unit address, as 8450 has 2 SPMI bus
> > hosts and they both share the core reg, so it would have been
> > impossible to have two spmi@core nodes..
> 
> Eh? SM8450 has 2 SPMI hosts both using 0x0c400000? How does that work?
> Usually address can be mapped only once.
> 

The SPMI controller does something like multi-master. The driver expects
the same region to be mapped multiple times and qcom,channel is used to
select which one each instance should operate on.

Regards,
Bjorn

> Where is the second SPMI? I cannot find it in linux-next.
> 
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH v2 1/7] arm64: dts: qcom: sm8450: add spmi node

[Vinod Koul]

On 29-12-22, 10:12, Bjorn Andersson wrote:
> On Thu, Dec 29, 2022 at 11:57:58AM +0100, Krzysztof Kozlowski wrote:
> > On 29/12/2022 11:45, Konrad Dybcio wrote:
> > > 
> > > 
> > > On 29.12.2022 11:42, Krzysztof Kozlowski wrote:
> > >> On 29/12/2022 11:32, Konrad Dybcio wrote:
> > >>> From: Vinod Koul <vkoul@kernel.org>
> > >>>
> > >>> Add the spmi bus as found in the SM8450 SoC
> > >>>
> > >>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > >>> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> > >>> [Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list]
> > >>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> > >>> ---
> > >>> v1 -> v2:
> > >>> No changes
> > >>>
> > >>>  arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++
> > >>>  1 file changed, 22 insertions(+)
> > >>>
> > >>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > >>> index 570475040d95..b9b59c5223eb 100644
> > >>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > >>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> > >>> @@ -2715,6 +2715,28 @@ aoss_qmp: power-controller@c300000 {
> > >>>  			#clock-cells = <0>;
> > >>>  		};
> > >>>  
> > >>> +		spmi_bus: spmi@c42d000 {
> > >>
> > >> Hmm looks different than reg.
> > >>
> > >>> +			compatible = "qcom,spmi-pmic-arb";
> > >>> +			reg = <0 0x0c400000 0 0x00003000>,
> > >>> +			      <0 0x0c500000 0 0x00400000>,
> > >>> +			      <0 0x0c440000 0 0x00080000>,
> > >>> +			      <0 0x0c4c0000 0 0x00010000>,
> > >>> +			      <0 0x0c42d000 0 0x00010000>;
> > >> x
> > > Hm, my guess would be that Vinod chose to put the "cnfg" reg
> > > instead of "core" in the unit address, as 8450 has 2 SPMI bus
> > > hosts and they both share the core reg, so it would have been
> > > impossible to have two spmi@core nodes..
> > 
> > Eh? SM8450 has 2 SPMI hosts both using 0x0c400000? How does that work?
> > Usually address can be mapped only once.
> > 
> 
> The SPMI controller does something like multi-master. The driver expects
> the same region to be mapped multiple times and qcom,channel is used to
> select which one each instance should operate on.

Right, this one adds same as downstream. I agree in future we should
revisit this and decide how we should model this. For now I am more
inclined to get this piece closed, it been more than a year :-( lets not
make it two!

-- 
~Vinod

Re: [PATCH v2 2/7] arm64: dts: qcom: sm8450-nagara: Include PMIC DTSIs

[Vinod Koul]

On 29-12-22, 11:32, Konrad Dybcio wrote:
> Now that SPMI is finally in place, include the DTSIs of PMICs present
> on Nagara.

I never got to send mine, so thanks for sending

Reviewed-by: Vinod Koul <vkoul@kernel.org>

> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> v1 -> v2:
> No changes
> 
>  arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
> index 45ee922de4e8..e29fb7adc780 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara.dtsi
> @@ -5,6 +5,12 @@
>  
>  #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>  #include "sm8450.dtsi"
> +#include "pm8350.dtsi"
> +#include "pm8350b.dtsi"
> +#include "pm8350c.dtsi"
> +#include "pm8450.dtsi"
> +#include "pmk8350.dtsi"
> +#include "pmr735a.dtsi"
>  
>  /delete-node/ &adsp_mem;
>  /delete-node/ &rmtfs_mem;
> -- 
> 2.39.0

-- 
~Vinod

Re: (subset) [PATCH v2 1/7] arm64: dts: qcom: sm8450: add spmi node

[Bjorn Andersson]

On Thu, 29 Dec 2022 11:32:06 +0100, Konrad Dybcio wrote:
> From: Vinod Koul <vkoul@kernel.org>
> 
> Add the spmi bus as found in the SM8450 SoC
> 
> 

Applied, thanks!

[1/7] arm64: dts: qcom: sm8450: add spmi node
      commit: f891f86e47c3208986b0985ca1fbc94647ba2ad0
[2/7] arm64: dts: qcom: sm8450-nagara: Include PMIC DTSIs
      commit: 25deb75e99bc57a7860cef2688b032d0e2f979dc
[3/7] arm64: dts: qcom: sm8450-nagara: Add GPIO line names for PMIC GPIOs
      commit: 4c5ab70d11ba591e28d4b07e50847084141c2374
[4/7] arm64: dts: qcom: sm8450-nagara: Add GPIO keys
      commit: 7b2557697890a947e178d4dc20848b479e384123
[5/7] arm64: dts: qcom: sm8450-nagara: Set up camera regulators
      commit: 40430a7c485b5463247b28691ad6a4fc5e280235
[6/7] arm64: dts: qcom: sm8450-nagara: Enable PMIC RESIN+PON
      commit: e9090691e48d2ceabec70448ac893637fbf0e27e
[7/7] arm64: dts: qcom: sm8450-nagara: Configure SLG51000 PMIC
      commit: 0d89bfbcd6d4c2691f5d70b8f2938aeb7774e7f6

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>