From: Anup Patel <apatel@ventanamicro.com> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Jones <ajones@ventanamicro.com>, Atish Patra <atishp@atishpatra.org>, Samuel Holland <samuel@sholland.org>, Conor Dooley <conor.dooley@microchip.com>, Anup Patel <anup@brainfault.org>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>, Rob Herring <robh@kernel.org>, Palmer Dabbelt <palmer@rivosinc.com> Subject: [PATCH v6 2/3] dt-bindings: timer: Add bindings for the RISC-V timer device Date: Tue, 3 Jan 2023 19:41:01 +0530 [thread overview] Message-ID: <20230103141102.772228-3-apatel@ventanamicro.com> (raw) In-Reply-To: <20230103141102.772228-1-apatel@ventanamicro.com> We add DT bindings for a separate RISC-V timer DT node which can be used to describe implementation specific behaviour (such as timer interrupt not triggered during non-retentive suspend). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> --- .../bindings/timer/riscv,timer.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/riscv,timer.yaml diff --git a/Documentation/devicetree/bindings/timer/riscv,timer.yaml b/Documentation/devicetree/bindings/timer/riscv,timer.yaml new file mode 100644 index 000000000000..38d67e1a5a79 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/riscv,timer.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/riscv,timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V timer + +maintainers: + - Anup Patel <anup@brainfault.org> + +description: |+ + RISC-V platforms always have a RISC-V timer device for the supervisor-mode + based on the time CSR defined by the RISC-V privileged specification. The + timer interrupts of this device are configured using the RISC-V SBI Time + extension or the RISC-V Sstc extension. + + The clock frequency of RISC-V timer device is specified via the + "timebase-frequency" DT property of "/cpus" DT node which is described + in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + enum: + - riscv,timer + + interrupts-extended: + minItems: 1 + maxItems: 4096 # Should be enough? + + riscv,timer-cannot-wake-cpu: + type: boolean + description: + If present, the timer interrupt cannot wake up the CPU from one or + more suspend/idle states. + +additionalProperties: false + +required: + - compatible + - interrupts-extended + +examples: + - | + timer { + compatible = "riscv,timer"; + interrupts-extended = <&cpu1intc 5>, + <&cpu2intc 5>, + <&cpu3intc 5>, + <&cpu4intc 5>; + }; +... -- 2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <apatel@ventanamicro.com> To: Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de> Cc: Andrew Jones <ajones@ventanamicro.com>, Atish Patra <atishp@atishpatra.org>, Samuel Holland <samuel@sholland.org>, Conor Dooley <conor.dooley@microchip.com>, Anup Patel <anup@brainfault.org>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>, Rob Herring <robh@kernel.org>, Palmer Dabbelt <palmer@rivosinc.com> Subject: [PATCH v6 2/3] dt-bindings: timer: Add bindings for the RISC-V timer device Date: Tue, 3 Jan 2023 19:41:01 +0530 [thread overview] Message-ID: <20230103141102.772228-3-apatel@ventanamicro.com> (raw) In-Reply-To: <20230103141102.772228-1-apatel@ventanamicro.com> We add DT bindings for a separate RISC-V timer DT node which can be used to describe implementation specific behaviour (such as timer interrupt not triggered during non-retentive suspend). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> --- .../bindings/timer/riscv,timer.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/riscv,timer.yaml diff --git a/Documentation/devicetree/bindings/timer/riscv,timer.yaml b/Documentation/devicetree/bindings/timer/riscv,timer.yaml new file mode 100644 index 000000000000..38d67e1a5a79 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/riscv,timer.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/riscv,timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V timer + +maintainers: + - Anup Patel <anup@brainfault.org> + +description: |+ + RISC-V platforms always have a RISC-V timer device for the supervisor-mode + based on the time CSR defined by the RISC-V privileged specification. The + timer interrupts of this device are configured using the RISC-V SBI Time + extension or the RISC-V Sstc extension. + + The clock frequency of RISC-V timer device is specified via the + "timebase-frequency" DT property of "/cpus" DT node which is described + in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + enum: + - riscv,timer + + interrupts-extended: + minItems: 1 + maxItems: 4096 # Should be enough? + + riscv,timer-cannot-wake-cpu: + type: boolean + description: + If present, the timer interrupt cannot wake up the CPU from one or + more suspend/idle states. + +additionalProperties: false + +required: + - compatible + - interrupts-extended + +examples: + - | + timer { + compatible = "riscv,timer"; + interrupts-extended = <&cpu1intc 5>, + <&cpu2intc 5>, + <&cpu3intc 5>, + <&cpu4intc 5>; + }; +... -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-01-03 14:12 UTC|newest] Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-03 14:10 [PATCH v6 0/3] Improve CLOCK_EVT_FEAT_C3STOP feature setting Anup Patel 2023-01-03 14:10 ` Anup Patel 2023-01-03 14:11 ` [PATCH v6 1/3] RISC-V: time: initialize hrtimer based broadcast clock event device Anup Patel 2023-01-03 14:11 ` Anup Patel 2023-02-13 18:26 ` [tip: timers/core] " tip-bot2 for Conor Dooley 2023-01-03 14:11 ` Anup Patel [this message] 2023-01-03 14:11 ` [PATCH v6 2/3] dt-bindings: timer: Add bindings for the RISC-V timer device Anup Patel 2023-02-13 18:26 ` [tip: timers/core] " tip-bot2 for Anup Patel 2023-01-03 14:11 ` [PATCH v6 3/3] clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT Anup Patel 2023-01-03 14:11 ` Anup Patel 2023-02-13 18:26 ` [tip: timers/core] clocksource/drivers/timer-riscv: " tip-bot2 for Anup Patel 2023-01-04 13:02 ` [PATCH v6 0/3] Improve CLOCK_EVT_FEAT_C3STOP feature setting Daniel Lezcano 2023-01-04 13:02 ` Daniel Lezcano 2023-01-04 14:04 ` Anup Patel 2023-01-04 14:04 ` Anup Patel 2023-01-04 22:30 ` Daniel Lezcano 2023-01-04 22:30 ` Daniel Lezcano
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