[igt-dev] [PATCH 1/4] lib/amdgpu: rename function parameter

[igt-dev] [PATCH 1/4] lib/amdgpu: rename function parameter

[vitaly.prosyak]

From: Vitaly Prosyak <vitaly.prosyak@amd.com>

No functional change just cosmetic.
Rename flags parameter to alloc_flags for clarity.
There are mapping flags.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
 lib/amdgpu/amd_memory.c | 10 ++++------
 lib/amdgpu/amd_memory.h |  2 +-
 2 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/lib/amdgpu/amd_memory.c b/lib/amdgpu/amd_memory.c
index 0aa400ac8..e3432a954 100644
--- a/lib/amdgpu/amd_memory.c
+++ b/lib/amdgpu/amd_memory.c
@@ -41,7 +41,7 @@
 				      uint64_t size,
 				      uint64_t alignment,
 				      uint32_t type,
-				      uint64_t flags,
+				      uint64_t alloc_flags,
 				      uint64_t *vmc_addr,
 				      amdgpu_va_handle *va_handle)
 {
@@ -49,7 +49,7 @@
 		.alloc_size = size,
 		.phys_alignment = alignment,
 		.preferred_heap = type,
-		.flags = flags,
+		.flags = alloc_flags,
 	};
 	amdgpu_bo_handle buf_handle;
 	int r;
@@ -57,10 +57,8 @@
 	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
 	igt_assert_eq(r, 0);
 
-	r = amdgpu_va_range_alloc(device_handle,
-				  amdgpu_gpu_va_range_general,
-				  size, alignment, 0, vmc_addr,
-				  va_handle, 0);
+	r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general,
+				   size, alignment, 0, vmc_addr, va_handle, 0);
 	igt_assert_eq(r, 0);
 
 	r = amdgpu_bo_va_op(buf_handle, 0, size, *vmc_addr, 0, AMDGPU_VA_OP_MAP);
diff --git a/lib/amdgpu/amd_memory.h b/lib/amdgpu/amd_memory.h
index 77fd099b0..a06f88923 100644
--- a/lib/amdgpu/amd_memory.h
+++ b/lib/amdgpu/amd_memory.h
@@ -35,7 +35,7 @@ gpu_mem_alloc(amdgpu_device_handle device_handle,
 				      uint64_t size,
 				      uint64_t alignment,
 				      uint32_t type,
-				      uint64_t flags,
+				      uint64_t alloc_flags,
 				      uint64_t *vmc_addr,
 				      amdgpu_va_handle *va_handle);
 int
-- 
2.25.1

[igt-dev] [PATCH 2/4] lib/amdgpu: move function to another file

[vitaly.prosyak]

From: Vitaly Prosyak <vitaly.prosyak@amd.com>

No functional change just cosmetic.
Move function amdgpu_open_devices to the shared file
since other tests will also use it.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
 lib/amdgpu/amd_ip_blocks.c  | 94 ++++++++++++++++++++++++++++++++++---
 lib/amdgpu/amd_ip_blocks.h  |  5 ++
 lib/amdgpu/amd_pci_unplug.c | 69 ---------------------------
 lib/amdgpu/amd_pci_unplug.h |  3 +-
 4 files changed, 93 insertions(+), 78 deletions(-)

diff --git a/lib/amdgpu/amd_ip_blocks.c b/lib/amdgpu/amd_ip_blocks.c
index 3331c40bd..ce1bddffc 100644
--- a/lib/amdgpu/amd_ip_blocks.c
+++ b/lib/amdgpu/amd_ip_blocks.c
@@ -22,6 +22,8 @@
  *
  *
  */
+#include <fcntl.h>
+
 #include "amd_memory.h"
 #include "amd_ip_blocks.h"
 #include "amd_PM4.h"
@@ -616,21 +618,30 @@ int setup_amdgpu_ip_blocks(uint32_t major, uint32_t minor, struct amdgpu_gpu_inf
 		igt_info("amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
 			 amdinfo->family_id, amdinfo->chip_external_rev);
 		return -1;
+	} else {
+		igt_info("amdgpu: %s (family_id, chip_external_rev): (%u, %u)\n",
+				info->name, amdinfo->family_id, amdinfo->chip_external_rev);
 	}
 
-	if (info->family >= CHIP_SIENNA_CICHLID)
+	if (info->family >= CHIP_SIENNA_CICHLID) {
 		info->chip_class = GFX10_3;
-	else if (info->family >= CHIP_NAVI10)
+		igt_info("amdgpu: chip_class GFX10_3\n");
+	} else if (info->family >= CHIP_NAVI10) {
 		info->chip_class = GFX10;
-	else if (info->family >= CHIP_VEGA10)
+		igt_info("amdgpu: chip_class GFX10\n");
+	} else if (info->family >= CHIP_VEGA10) {
 		info->chip_class = GFX9;
-	else if (info->family >= CHIP_TONGA)
+		igt_info("amdgpu: chip_class GFX9\n");
+	} else if (info->family >= CHIP_TONGA) {
 		info->chip_class = GFX8;
-	else if (info->family >= CHIP_BONAIRE)
+		igt_info("amdgpu: chip_class GFX8\n");
+	} else if (info->family >= CHIP_BONAIRE) {
 		info->chip_class = GFX7;
-	else if (info->family >= CHIP_TAHITI)
+		igt_info("amdgpu: chip_class GFX7\n");
+	} else if (info->family >= CHIP_TAHITI) {
 		info->chip_class = GFX6;
-	else {
+		igt_info("amdgpu: chip_class GFX6\n");
+	} else {
 		igt_info("amdgpu: Unknown family.\n");
 		return -1;
 	}
@@ -663,3 +674,72 @@ int setup_amdgpu_ip_blocks(uint32_t major, uint32_t minor, struct amdgpu_gpu_inf
 
 	return 0;
 }
+
+int
+amdgpu_open_devices(bool open_render_node, int  max_cards_supported, int drm_amdgpu_fds[])
+{
+	drmDevicePtr devices[MAX_CARDS_SUPPORTED];
+	int i;
+	int drm_node;
+	int amd_index = 0;
+	int drm_count;
+	int fd;
+	drmVersionPtr version;
+
+	for (i = 0; i < max_cards_supported && i < MAX_CARDS_SUPPORTED; i++)
+		drm_amdgpu_fds[i] = -1;
+
+	drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED);
+
+	if (drm_count < 0) {
+		fprintf(stderr, "drmGetDevices2() returned an error %d\n", drm_count);
+		return 0;
+	}
+
+	for (i = 0; i < drm_count; i++) {
+		/* If this is not PCI device, skip*/
+		if (devices[i]->bustype != DRM_BUS_PCI)
+			continue;
+
+		/* If this is not AMD GPU vender ID, skip*/
+		if (devices[i]->deviceinfo.pci->vendor_id != 0x1002)
+			continue;
+
+		if (open_render_node)
+			drm_node = DRM_NODE_RENDER;
+		else
+			drm_node = DRM_NODE_PRIMARY;
+
+		fd = -1;
+		if (devices[i]->available_nodes & 1 << drm_node)
+			fd = open(
+				devices[i]->nodes[drm_node],
+				O_RDWR | O_CLOEXEC);
+
+		/* This node is not available. */
+		if (fd < 0) continue;
+
+		version = drmGetVersion(fd);
+		if (!version) {
+			fprintf(stderr, "Warning: Cannot get version for %s." "Error is %s\n",
+				devices[i]->nodes[drm_node], strerror(errno));
+			close(fd);
+			continue;
+		}
+
+		if (strcmp(version->name, "amdgpu")) {
+			/* This is not AMDGPU driver, skip.*/
+			drmFreeVersion(version);
+			close(fd);
+			continue;
+		}
+
+		drmFreeVersion(version);
+
+		drm_amdgpu_fds[amd_index] = fd;
+		amd_index++;
+	}
+
+	drmFreeDevices(devices, drm_count);
+	return amd_index;
+}
diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
index 908aacde0..b3620c00f 100644
--- a/lib/amdgpu/amd_ip_blocks.h
+++ b/lib/amdgpu/amd_ip_blocks.h
@@ -27,6 +27,8 @@
 
 #include "amd_registers.h"
 
+#define MAX_CARDS_SUPPORTED 4
+
 enum amd_ip_block_type {
 	AMD_IP_GFX,
 	AMD_IP_COMPUTE,
@@ -136,4 +138,7 @@ struct amdgpu_cmd_base* get_cmd_base(void);
 
 void free_cmd_base(struct amdgpu_cmd_base *base);
 
+int
+amdgpu_open_devices(bool open_render_node, int  max_cards_supported, int drm_amdgpu_fds[]);
+
 #endif
diff --git a/lib/amdgpu/amd_pci_unplug.c b/lib/amdgpu/amd_pci_unplug.c
index 28b3ae393..078398b5e 100644
--- a/lib/amdgpu/amd_pci_unplug.c
+++ b/lib/amdgpu/amd_pci_unplug.c
@@ -21,7 +21,6 @@
  *
 */
 #include <linux/limits.h>
-#include <sys/types.h>
 #include <fcntl.h>
 #include <sys/stat.h>
 #include <pthread.h>
@@ -35,74 +34,6 @@
 #include "xalloc.h"
 #include "amd_ip_blocks.h"
 
-static int
-amdgpu_open_devices(bool open_render_node, int  max_cards_supported, int drm_amdgpu_fds[])
-{
-	drmDevicePtr devices[MAX_CARDS_SUPPORTED];
-	int i;
-	int drm_node;
-	int amd_index = 0;
-	int drm_count;
-	int fd;
-	drmVersionPtr version;
-
-	for (i = 0; i < max_cards_supported && i < MAX_CARDS_SUPPORTED; i++)
-		drm_amdgpu_fds[i] = -1;
-
-	drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED);
-
-	if (drm_count < 0) {
-		fprintf(stderr, "drmGetDevices2() returned an error %d\n", drm_count);
-		return 0;
-	}
-
-	for (i = 0; i < drm_count; i++) {
-		/* If this is not PCI device, skip*/
-		if (devices[i]->bustype != DRM_BUS_PCI)
-			continue;
-
-		/* If this is not AMD GPU vender ID, skip*/
-		if (devices[i]->deviceinfo.pci->vendor_id != 0x1002)
-			continue;
-
-		if (open_render_node)
-			drm_node = DRM_NODE_RENDER;
-		else
-			drm_node = DRM_NODE_PRIMARY;
-
-		fd = -1;
-		if (devices[i]->available_nodes & 1 << drm_node)
-			fd = open(
-				devices[i]->nodes[drm_node],
-				O_RDWR | O_CLOEXEC);
-
-		/* This node is not available. */
-		if (fd < 0) continue;
-
-		version = drmGetVersion(fd);
-		if (!version) {
-			fprintf(stderr, "Warning: Cannot get version for %s." "Error is %s\n",
-				devices[i]->nodes[drm_node], strerror(errno));
-			close(fd);
-			continue;
-		}
-
-		if (strcmp(version->name, "amdgpu")) {
-			/* This is not AMDGPU driver, skip.*/
-			drmFreeVersion(version);
-			close(fd);
-			continue;
-		}
-
-		drmFreeVersion(version);
-
-		drm_amdgpu_fds[amd_index] = fd;
-		amd_index++;
-	}
-
-	drmFreeDevices(devices, drm_count);
-	return amd_index;
-}
 static bool
 amdgpu_node_is_drm(int maj, int min)
 {
diff --git a/lib/amdgpu/amd_pci_unplug.h b/lib/amdgpu/amd_pci_unplug.h
index 509b6ec4c..35d4dce3a 100644
--- a/lib/amdgpu/amd_pci_unplug.h
+++ b/lib/amdgpu/amd_pci_unplug.h
@@ -26,8 +26,7 @@
 
 #include <amdgpu.h>
 #include <amdgpu_drm.h>
-
-#define MAX_CARDS_SUPPORTED 4
+#include "amd_ip_blocks.h"
 
 struct amd_pci_unplug_setup {
 	uint32_t  major_version_req;
-- 
2.25.1

[igt-dev] [PATCH 3/4] lib/amdgpu: add cp dma helper functions

[vitaly.prosyak]

From: Vitaly Prosyak <vitaly.prosyak@amd.com>

CP DMA tests are executed between GTT and VRAM of a single chip
and also between separate ASICs.

 Port cp dma tests from drm_lib with the following improvements:
 - remove many global variables which restrict scalability and readability
 - reuse memory allocation helpers vs new helpers as in the original test
 - use helper structs to reduce the number of parameters in functions.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
 lib/amdgpu/amd_cp_dma.c | 446 ++++++++++++++++++++++++++++++++++++++++
 lib/amdgpu/amd_cp_dma.h |  41 ++++
 lib/meson.build         |   3 +-
 3 files changed, 489 insertions(+), 1 deletion(-)
 create mode 100644 lib/amdgpu/amd_cp_dma.c
 create mode 100644 lib/amdgpu/amd_cp_dma.h

diff --git a/lib/amdgpu/amd_cp_dma.c b/lib/amdgpu/amd_cp_dma.c
new file mode 100644
index 000000000..265cffa4c
--- /dev/null
+++ b/lib/amdgpu/amd_cp_dma.c
@@ -0,0 +1,446 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+#include <unistd.h>
+#include <amdgpu.h>
+#include "amdgpu_drm.h"
+#include "amd_memory.h"
+#include "amd_cp_dma.h"
+
+
+#define IB_SIZE 4096
+#define MAX_RESOURCES 3
+
+#define DMA_SIZE 4097 
+#define DMA_DATA_BYTE 0xea
+#define DMA_SIZE_MAX (1<<26)
+
+struct amdgpu_cp_dma_bo {
+	amdgpu_bo_handle buf_handle;
+	amdgpu_va_handle va_handle;
+	uint64_t gpu_va;
+	uint64_t size;
+};
+
+struct amdgpu_cp_dma_ib {
+	amdgpu_bo_handle ib_handle;
+	uint32_t *ib_cpu;
+	uint64_t ib_mc_address;
+	amdgpu_va_handle ib_va_handle;
+};
+
+struct amdgpu_cp_dma_contex {
+	amdgpu_bo_handle resources[MAX_RESOURCES];
+	unsigned num_resources;
+	uint32_t num_dword;
+	uint8_t *reference_data;
+};
+
+static int
+import_dma_buf_to_bo(amdgpu_device_handle dev, int dmabuf_fd,
+					 struct amdgpu_cp_dma_bo *bo)
+{
+	amdgpu_va_handle va_handle;
+	uint64_t vmc_addr;
+	int r;
+	struct amdgpu_bo_import_result bo_import_result = {};
+
+	r = amdgpu_bo_import(dev, amdgpu_bo_handle_type_dma_buf_fd,
+			dmabuf_fd, &bo_import_result);
+	if (r)
+		goto error_bo_import;
+
+	r = amdgpu_va_range_alloc(dev, amdgpu_gpu_va_range_general,
+				bo_import_result.alloc_size, 0, 0,
+				&vmc_addr, &va_handle, 0);
+	if (r)
+		goto error_va_alloc;
+
+	r = amdgpu_bo_va_op(bo_import_result.buf_handle, 0,
+			bo_import_result.alloc_size, vmc_addr,
+			AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
+			AMDGPU_VM_PAGE_EXECUTABLE,
+			AMDGPU_VA_OP_MAP);
+	if (r)
+		goto error_va_map;
+
+	bo->buf_handle = bo_import_result.buf_handle;
+	bo->va_handle = va_handle;
+	bo->gpu_va = vmc_addr;
+	bo->size = bo_import_result.alloc_size;
+
+	return 0;
+
+error_va_map:
+	amdgpu_bo_va_op(bo_import_result.buf_handle, 0,
+			bo_import_result.alloc_size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
+
+error_va_alloc:
+	amdgpu_va_range_free(va_handle);
+
+error_bo_import:
+	amdgpu_bo_free(bo_import_result.buf_handle);
+
+	return r;
+}
+
+static int
+free_bo(struct amdgpu_cp_dma_bo bo)
+{
+	int r;
+	r = amdgpu_bo_va_op(bo.buf_handle, 0, bo.size, bo.gpu_va, 0, AMDGPU_VA_OP_UNMAP);
+	igt_assert_eq(r, 0);
+
+	r = amdgpu_va_range_free(bo.va_handle);
+	igt_assert_eq(r, 0);
+
+	r = amdgpu_bo_free(bo.buf_handle);
+	igt_assert_eq(r, 0);
+
+	return r;
+}
+
+static int
+submit_and_sync(amdgpu_device_handle device_handle, unsigned ip_type,
+		  amdgpu_context_handle context_handle, uint64_t ib_mc_address,
+		  struct amdgpu_cp_dma_contex *dma_contex)
+{
+	struct amdgpu_cs_request ibs_request = {0};
+	struct amdgpu_cs_ib_info ib_info = {0};
+	struct amdgpu_cs_fence fence_status = {0};
+	uint32_t expired;
+	int r;
+
+	r = amdgpu_bo_list_create(device_handle,
+			dma_contex->num_resources, dma_contex->resources,
+			NULL, &ibs_request.resources);
+	igt_assert_eq(r, 0);
+
+	ib_info.ib_mc_address = ib_mc_address;
+	ib_info.size = dma_contex->num_dword;
+
+	ibs_request.ip_type = ip_type;
+	ibs_request.number_of_ibs = 1;
+	ibs_request.ibs = &ib_info;
+	ibs_request.fence_info.handle = NULL;
+
+	r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
+	igt_assert_eq(r, 0);
+
+	r = amdgpu_bo_list_destroy(ibs_request.resources);
+	igt_assert_eq(r, 0);
+
+	fence_status.context = context_handle;
+	fence_status.ip_type = ip_type;
+	fence_status.fence = ibs_request.seq_no;
+
+	r = amdgpu_cs_query_fence_status(&fence_status, AMDGPU_TIMEOUT_INFINITE,
+									 0, &expired);
+	return r;
+}
+
+static void
+cp_dma_cmd(const struct amdgpu_cp_dma_ib *ib, struct amdgpu_cp_dma_contex *dma_contex,
+	     const struct amdgpu_cp_dma_bo *src_bo, const struct amdgpu_cp_dma_bo *dst_bo)
+{
+	/* TODO use spec defines */
+	ib->ib_cpu[0] = 0xc0055000;
+	ib->ib_cpu[1] = 0x80000000;
+	ib->ib_cpu[2] = src_bo->gpu_va & 0x00000000ffffffff;
+	ib->ib_cpu[3] = (src_bo->gpu_va & 0xffffffff00000000) >> 32;
+	ib->ib_cpu[4] = dst_bo->gpu_va & 0x00000000ffffffff;
+	ib->ib_cpu[5] = (dst_bo->gpu_va & 0xffffffff00000000) >> 32;
+	// size is read from the lower 26bits. 
+	ib->ib_cpu[6] = ((1 << 26) - 1) & DMA_SIZE;
+	ib->ib_cpu[7] = 0xffff1000;
+
+	dma_contex->num_dword = 8;
+
+	dma_contex->resources[0] = src_bo->buf_handle;
+	dma_contex->resources[1] = dst_bo->buf_handle;
+	dma_contex->resources[2] = ib->ib_handle;
+	dma_contex->num_resources = 3;
+}
+
+static int
+amdgpu_cp_dma(amdgpu_device_handle device_handle, unsigned ip_type, amdgpu_context_handle context_handle,
+		const struct amdgpu_cp_dma_ib *ib, struct amdgpu_cp_dma_contex *dma_contex,
+		uint32_t src_heap, uint32_t dst_heap)
+{
+	int r;
+	struct amdgpu_cp_dma_bo src_bo = {0};
+	struct amdgpu_cp_dma_bo dst_bo = {0};
+	void *src_bo_cpu;
+	void *dst_bo_cpu;
+
+	/* allocate the src bo, set its data to DMA_DATA_BYTE */
+	src_bo.buf_handle = gpu_mem_alloc(device_handle, DMA_SIZE, 4096,
+			src_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &src_bo.gpu_va, &src_bo.va_handle);
+
+	r = amdgpu_bo_cpu_map(src_bo.buf_handle, (void **)&src_bo_cpu);
+	igt_assert_eq(r, 0);
+	memset(src_bo_cpu, DMA_DATA_BYTE, DMA_SIZE);
+
+	r = amdgpu_bo_cpu_unmap(src_bo.buf_handle);
+	igt_assert_eq(r, 0);
+
+	/* allocate the dst bo and clear its content to all 0 */
+	dst_bo.buf_handle = gpu_mem_alloc(device_handle, DMA_SIZE, 4096,
+			dst_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &dst_bo.gpu_va, &dst_bo.va_handle);
+
+	r = amdgpu_bo_cpu_map(dst_bo.buf_handle, (void **)&dst_bo_cpu);
+	igt_assert_eq(r, 0);
+
+	memset(dst_bo_cpu, 0, DMA_SIZE);
+
+	/* record CP DMA command and dispatch the command */
+	cp_dma_cmd(ib, dma_contex, &src_bo, &dst_bo);
+
+	r = submit_and_sync(device_handle, ip_type, context_handle, ib->ib_mc_address ,dma_contex);
+	igt_assert_eq(r, 0);
+
+	/* verify the dst bo is filled with DMA_DATA_BYTE */
+	r = memcmp(dst_bo_cpu, dma_contex->reference_data, DMA_SIZE);
+	igt_assert_eq(r, 0);
+
+	r = amdgpu_bo_cpu_unmap(dst_bo.buf_handle);
+	igt_assert_eq(r, 0);
+
+	r = free_bo(src_bo);
+	igt_assert_eq(r, 0);
+
+	r = free_bo(dst_bo);
+	igt_assert_eq(r, 0);
+
+	return r;
+}
+
+static int
+amdgpu_cp_dma_p2p(amdgpu_device_handle device_handle,
+		    amdgpu_device_handle exporting_device_handle,
+		    unsigned ip_type, amdgpu_context_handle context_handle,
+		    uint32_t src_heap, uint32_t dst_heap,
+		    const struct amdgpu_cp_dma_ib *ib, struct amdgpu_cp_dma_contex *dma_contex)
+{
+	int r;
+	struct amdgpu_cp_dma_bo exported_bo = {0};
+	int dma_buf_fd;
+	int dma_buf_fd_dup;
+	struct amdgpu_cp_dma_bo src_bo = {0};
+	struct amdgpu_cp_dma_bo imported_dst_bo = {0};
+
+	void *exported_bo_cpu;
+	void *src_bo_cpu;
+
+	/* allocate a bo on the peer device and export it to dma-buf */
+	exported_bo.buf_handle = gpu_mem_alloc(exporting_device_handle, DMA_SIZE, 4096,
+			src_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &exported_bo.gpu_va, &exported_bo.va_handle);
+
+	/* map the exported bo and clear its content to 0 */
+	r = amdgpu_bo_cpu_map(exported_bo.buf_handle, (void **)&exported_bo_cpu);
+	igt_assert_eq(r, 0);
+	memset(exported_bo_cpu, 0, DMA_SIZE);
+
+	r = amdgpu_bo_export(exported_bo.buf_handle,
+			amdgpu_bo_handle_type_dma_buf_fd, (uint32_t*)&dma_buf_fd);
+	igt_assert_eq(r, 0);
+
+    // According to amdgpu_drm:
+	// "Buffer must be "imported" only using new "fd"
+	// (different from one used by "exporter")"
+	dma_buf_fd_dup = dup(dma_buf_fd);
+	r = close(dma_buf_fd);
+	igt_assert_eq(r, 0);
+
+	/* import the dma-buf to the executing device, imported bo is the DMA destination */
+	r = import_dma_buf_to_bo(device_handle, dma_buf_fd_dup, &imported_dst_bo);
+	igt_assert_eq(r, 0);
+
+	r = close(dma_buf_fd_dup);
+	igt_assert_eq(r, 0);
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	/* allocate the src bo and set its content to DMA_DATA_BYTE */
+
+	src_bo.buf_handle = gpu_mem_alloc(device_handle, DMA_SIZE, 4096,
+			dst_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &src_bo.gpu_va, &src_bo.va_handle);
+
+	igt_assert_eq(r, 0);
+
+	r = amdgpu_bo_cpu_map(src_bo.buf_handle, (void **)&src_bo_cpu);
+	igt_assert_eq(r, 0);
+
+	memset(src_bo_cpu, DMA_DATA_BYTE, DMA_SIZE);
+
+	r = amdgpu_bo_cpu_unmap(src_bo.buf_handle);
+	igt_assert_eq(r, 0);
+
+	/* record CP DMA command and dispatch the command */
+	cp_dma_cmd(ib, dma_contex, &src_bo, &imported_dst_bo);
+
+	r = submit_and_sync(device_handle, ip_type, context_handle, ib->ib_mc_address ,dma_contex);
+
+	igt_assert_eq(r, 0);
+
+	/* verify the exported_bo_cpu is filled with DMA_DATA_BYTE */
+	r = memcmp(exported_bo_cpu, dma_contex->reference_data, DMA_SIZE);
+	igt_assert_eq(r, 0);
+
+	r = amdgpu_bo_cpu_unmap(exported_bo.buf_handle);
+	igt_assert_eq(r, 0);
+
+	r = free_bo(exported_bo);
+	igt_assert_eq(r, 0);
+
+	r = free_bo(imported_dst_bo);
+	igt_assert_eq(r, 0);
+
+	r = free_bo(src_bo);
+	igt_assert_eq(r, 0);
+
+	return r;
+}
+
+static int
+amdgpu_cp_dma_misc(amdgpu_device_handle device_handle, unsigned ip_type,
+		     uint32_t src_heap, uint32_t dst_heap)
+{
+	amdgpu_context_handle context_handle;
+	struct amdgpu_cp_dma_contex dma_contex = {};
+	struct amdgpu_cp_dma_ib dma_ib = {};
+	int r;
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	igt_assert_eq(r, 0);
+	r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
+					AMDGPU_GEM_DOMAIN_GTT, 0,
+					&dma_ib.ib_handle, (void**)&dma_ib.ib_cpu,
+					&dma_ib.ib_mc_address, &dma_ib.ib_va_handle);
+	igt_assert_eq(r, 0);
+
+	dma_contex.reference_data = (uint8_t*)malloc(DMA_SIZE);
+	memset(dma_contex.reference_data, DMA_DATA_BYTE, DMA_SIZE);
+
+	r = amdgpu_cp_dma(device_handle, ip_type, context_handle, &dma_ib,
+					  &dma_contex, src_heap, dst_heap);
+	igt_assert_eq(r, 0);
+
+ 	amdgpu_cs_ctx_free(context_handle);
+ 	free(dma_contex.reference_data);
+ 	amdgpu_bo_unmap_and_free(dma_ib.ib_handle, dma_ib.ib_va_handle,
+ 							 dma_ib.ib_mc_address, IB_SIZE);
+
+	return r;
+}
+
+static int
+amdgpu_cp_dma_misc_p2p(amdgpu_device_handle device_handle,
+			 amdgpu_device_handle exporting_device_handle,
+			 unsigned ip_type,
+			 uint32_t src_heap, uint32_t dst_heap)
+{
+	amdgpu_context_handle context_handle;
+	struct amdgpu_cp_dma_contex dma_contex = {};
+	struct amdgpu_cp_dma_ib dma_ib = {};
+	int r;
+
+	/* create context */
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	igt_assert_eq(r, 0);
+
+	/* init dma_ib */
+	r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
+					AMDGPU_GEM_DOMAIN_GTT, 0,
+					&dma_ib.ib_handle, (void**)&dma_ib.ib_cpu,
+					&dma_ib.ib_mc_address, &dma_ib.ib_va_handle);
+	igt_assert_eq(r, 0);
+
+	/* init dma context */
+	dma_contex.reference_data = (uint8_t*)malloc(DMA_SIZE);
+	memset(dma_contex.reference_data, DMA_DATA_BYTE, DMA_SIZE);
+
+	r = amdgpu_cp_dma_p2p(device_handle, exporting_device_handle, ip_type, context_handle,
+						  src_heap, dst_heap, &dma_ib, &dma_contex);
+	igt_assert_eq(r, 0);
+
+ 	amdgpu_cs_ctx_free(context_handle);
+ 	free(dma_contex.reference_data);
+ 	amdgpu_bo_unmap_and_free(dma_ib.ib_handle, dma_ib.ib_va_handle,
+ 							 dma_ib.ib_mc_address, IB_SIZE);
+
+	return r;
+}
+
+bool
+amdgpu_cp_dma_misc_is_supported(const struct amdgpu_gpu_info *gpu_info)
+{
+	/* why this restiction is here? */
+	/*if (!(gpu_info->family_id >= AMDGPU_FAMILY_AI &&
+			gpu_info->family_id <= AMDGPU_FAMILY_NV)) {
+		return false;
+	}*/
+	return true;
+}
+
+bool
+asic_is_gfx_pipe_removed(const struct amdgpu_gpu_info *gpu_info)
+{
+	int chip_id;
+
+	if (gpu_info->family_id != AMDGPU_FAMILY_AI)
+		return false;
+
+	chip_id = gpu_info->chip_external_rev - gpu_info->chip_rev;
+
+	switch(chip_id) {
+	/* Arcturus */
+	case 0x32:
+	/* Aldebaran */
+	case 0x3c:
+		return true; /* the gfx pipe is removed */
+	}
+	return false;
+}
+
+bool
+amdgpu_cp_dma_misc_p2p_is_supported(const struct amdgpu_gpu_info *gpu_info)
+{
+	bool ret = amdgpu_cp_dma_misc_is_supported(gpu_info);
+	return ret;
+}
+
+
+int
+amdgpu_cp_dma_generic(amdgpu_device_handle device_handle,
+					  amdgpu_device_handle exporting_device_handle, unsigned ip_type,
+					  uint32_t src_heap, uint32_t dst_heap)
+{
+	int r;
+	if (exporting_device_handle != NULL )
+		r = amdgpu_cp_dma_misc_p2p( device_handle, exporting_device_handle,
+									ip_type, src_heap, dst_heap);
+	else
+		amdgpu_cp_dma_misc(device_handle, ip_type, src_heap, dst_heap);
+
+	return r;
+}
+
diff --git a/lib/amdgpu/amd_cp_dma.h b/lib/amdgpu/amd_cp_dma.h
new file mode 100644
index 000000000..3d7826d6c
--- /dev/null
+++ b/lib/amdgpu/amd_cp_dma.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2022 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#ifndef __AMD_CP_DMA_H__
+#define __AMD_CP_DMA_H__
+
+int
+amdgpu_cp_dma_generic(amdgpu_device_handle device_handle,
+			amdgpu_device_handle exporting_device_handle, unsigned ip_type,
+			uint32_t src_heap, uint32_t dst_heap);
+
+bool
+amdgpu_cp_dma_misc_is_supported(const struct amdgpu_gpu_info *gpu_info);
+
+bool
+amdgpu_cp_dma_misc_p2p_is_supported(const struct amdgpu_gpu_info *gpu_info);
+
+bool
+asic_is_gfx_pipe_removed(const struct amdgpu_gpu_info *gpu_info);
+
+#endif
diff --git a/lib/meson.build b/lib/meson.build
index c79e3e952..cc7846869 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -138,7 +138,8 @@ if libdrm_amdgpu.found()
 		'amdgpu/amd_dispatch.c',
 		'amdgpu/amd_deadlock_helpers.c',
 		'amdgpu/amd_pci_unplug.c',
-		'amdgpu/xalloc.h'
+		'amdgpu/xalloc.h',
+		'amdgpu/amd_cp_dma.c'
 	]
 endif
 
-- 
2.25.1

[igt-dev] [PATCH 4/4] tests/amdgpu: add cp dma tests

[vitaly.prosyak]

From: Vitaly Prosyak <vitaly.prosyak@amd.com>

Combine subtests in the tables of phases and engines and
loop through the use cases of the following combinations:
GTT, VRAM for GFX and COMPUTE rings.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
---
 tests/amdgpu/amd_cp_dma_misc.c | 125 +++++++++++++++++++++++++++++++++
 tests/amdgpu/meson.build       |   1 +
 2 files changed, 126 insertions(+)
 create mode 100644 tests/amdgpu/amd_cp_dma_misc.c

diff --git a/tests/amdgpu/amd_cp_dma_misc.c b/tests/amdgpu/amd_cp_dma_misc.c
new file mode 100644
index 000000000..37b6114a9
--- /dev/null
+++ b/tests/amdgpu/amd_cp_dma_misc.c
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright 2014 Advanced Micro Devices, Inc.
+ * Copyright 2023 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include "drmtest.h"
+
+#include <amdgpu.h>
+#include <amdgpu_drm.h>
+#include "lib/amdgpu/amd_cp_dma.h"
+#include "lib/amdgpu/amd_ip_blocks.h"
+
+igt_main
+{
+	amdgpu_device_handle device;
+	amdgpu_device_handle device2;
+	uint32_t major, minor;
+	int r;
+
+	int drm_amdgpu_fds[MAX_CARDS_SUPPORTED];
+	struct amdgpu_gpu_info gpu_info = {};
+	struct amdgpu_gpu_info gpu_info2 = {};
+	int num_devices = 0;
+
+	const struct phase {
+		const char *name;
+		unsigned int src_memory;
+		unsigned int dst_memory;
+	} phase[] = {
+		{ "GTT_to_VRAM",  AMDGPU_GEM_DOMAIN_GTT,  AMDGPU_GEM_DOMAIN_VRAM },
+		{ "VRAM_to_GTT",  AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_DOMAIN_GTT  },
+		{ "VRAM_to_VRAM", AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_DOMAIN_VRAM },
+		{ },
+	}, *p;
+
+	const struct engine {
+		const char *name;
+		unsigned int ip_type;
+	} engines[] = {
+		{ "AMDGPU_HW_IP_GFX",		AMDGPU_HW_IP_GFX     },
+		{ "AMDGPU_HW_IP_COMPUTE",   AMDGPU_HW_IP_COMPUTE },
+		{ },
+	}, *e;
+
+
+	igt_fixture {
+		num_devices = amdgpu_open_devices(true, MAX_CARDS_SUPPORTED, drm_amdgpu_fds);
+		igt_require(num_devices > 0);
+		r = amdgpu_device_initialize(drm_amdgpu_fds[0], &major,
+										 &minor, &device);
+		igt_require(r == 0);
+		igt_info("Initialized amdgpu, driver version %d.%d\n", major, minor);
+		r = amdgpu_query_gpu_info(device, &gpu_info);
+		igt_assert_eq(r, 0);
+		r = setup_amdgpu_ip_blocks( major, minor,  &gpu_info, device);
+		igt_assert_eq(r, 0);
+
+		if (num_devices > 1 ) {
+			/* do test for 2 only */
+			igt_assert_eq(num_devices, 2);
+			r = amdgpu_device_initialize(drm_amdgpu_fds[1], &major,
+											 &minor, &device2);
+			igt_require(r == 0);
+			igt_info("Initialized amdgpu, driver2 version %d.%d\n", major, minor);
+			r = amdgpu_query_gpu_info(device2, &gpu_info2);
+			igt_assert_eq(r, 0);
+		}
+	}
+	if (amdgpu_cp_dma_misc_is_supported(&gpu_info)) {
+		for (p = phase; p->name; p++) {
+			for (e = engines; e->name; e++) {
+				if (e->ip_type == AMDGPU_HW_IP_GFX && asic_is_gfx_pipe_removed(&gpu_info))
+					continue;
+				igt_subtest_f("%s-%s0", p->name, e->name)
+				amdgpu_cp_dma_generic(device, NULL, e->ip_type,p->src_memory, p->dst_memory);
+			}
+		}
+	} else {
+		igt_info("SKIP due to testing device has ASIC family %d that is not supported by CP-DMA test\n",
+				gpu_info.family_id);
+	}
+
+	if (num_devices > 1 && 	amdgpu_cp_dma_misc_p2p_is_supported(&gpu_info2)) {
+		for (p = phase; p->name; p++) {
+			for (e = engines; e->name; e++) {
+				if (e->ip_type == AMDGPU_HW_IP_GFX && asic_is_gfx_pipe_removed(&gpu_info2))
+					continue;
+				igt_subtest_f("%s-%s0", p->name, e->name)
+				amdgpu_cp_dma_generic(device, device2, e->ip_type,p->src_memory, p->dst_memory);
+			}
+		}
+	} else {
+		igt_info("SKIP due to more than one ASIC is required or testing device has ASIC family %d that is not supported by CP-DMA P2P test\n",
+				gpu_info2.family_id);
+	}
+
+	igt_fixture {
+		amdgpu_device_deinitialize(device);
+		close(drm_amdgpu_fds[0]);
+		if (num_devices > 1) {
+			amdgpu_device_deinitialize(device2);
+			close(drm_amdgpu_fds[1]);
+		}
+	}
+}
diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build
index 48b916925..7fff7602f 100644
--- a/tests/amdgpu/meson.build
+++ b/tests/amdgpu/meson.build
@@ -8,6 +8,7 @@ if libdrm_amdgpu.found()
 			  'amd_bypass',
 			  'amd_deadlock',
 			  'amd_pci_unplug',
+			  'amd_cp_dma_misc',
 			  'amd_color',
 			  'amd_cs_nop',
 			  'amd_hotplug',
-- 
2.25.1

[igt-dev] ✓ Fi.CI.BAT: success for series starting with [1/4] lib/amdgpu: rename function parameter

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6635 bytes --]

== Series Details ==

Series: series starting with [1/4] lib/amdgpu: rename function parameter
URL   : https://patchwork.freedesktop.org/series/112416/
State : success

== Summary ==

CI Bug Log - changes from IGT_7108 -> IGTPW_8302
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/index.html

Participating hosts (41 -> 42)
------------------------------

  Additional (2): fi-bsw-kefka fi-pnv-d510 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_8302:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_suspend@basic-s0@smem:
    - {bat-rpls-1}:       NOTRUN -> [DMESG-WARN][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/bat-rpls-1/igt@gem_exec_suspend@basic-s0@smem.html

  
Known issues
------------

  Here are the changes found in IGTPW_8302 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        NOTRUN -> [FAIL][2] ([i915#7229])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-adlp-4:         NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/bat-adlp-4/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@i915_pm_rps@basic-api:
    - bat-adlp-4:         NOTRUN -> [SKIP][4] ([i915#6621])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/bat-adlp-4/igt@i915_pm_rps@basic-api.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - bat-adlp-4:         NOTRUN -> [SKIP][5] ([fdo#111827])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/bat-adlp-4/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-bsw-kefka:       NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/fi-bsw-kefka/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_psr@primary_page_flip:
    - fi-pnv-d510:        NOTRUN -> [SKIP][7] ([fdo#109271]) +44 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/fi-pnv-d510/igt@kms_psr@primary_page_flip.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-bsw-kefka:       NOTRUN -> [SKIP][8] ([fdo#109271]) +17 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/fi-bsw-kefka/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-userptr:
    - bat-adlp-4:         NOTRUN -> [SKIP][9] ([fdo#109295] / [i915#3301] / [i915#3708])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/bat-adlp-4/igt@prime_vgem@basic-userptr.html

  * igt@prime_vgem@basic-write:
    - bat-adlp-4:         NOTRUN -> [SKIP][10] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/bat-adlp-4/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@fbdev@write:
    - fi-blb-e6850:       [SKIP][11] ([fdo#109271]) -> [PASS][12] +4 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/fi-blb-e6850/igt@fbdev@write.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/fi-blb-e6850/igt@fbdev@write.html

  * igt@i915_pm_rpm@basic-rte:
    - bat-adlp-4:         [DMESG-WARN][13] ([i915#7077]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/bat-adlp-4/igt@i915_pm_rpm@basic-rte.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/bat-adlp-4/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-skl-6600u:       [DMESG-FAIL][15] ([i915#5334]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/fi-skl-6600u/igt@i915_selftest@live@gt_heartbeat.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/fi-skl-6600u/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@reset:
    - {bat-rpls-1}:       [DMESG-FAIL][17] ([i915#4983]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/bat-rpls-1/igt@i915_selftest@live@reset.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/bat-rpls-1/igt@i915_selftest@live@reset.html

  * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-2:
    - {bat-dg2-11}:       [FAIL][19] ([i915#7336]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-2.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-2.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
  [i915#7336]: https://gitlab.freedesktop.org/drm/intel/issues/7336


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7108 -> IGTPW_8302

  CI-20190529: 20190529
  CI_DRM_12546: 07a684fbd4d0f5e284e8a782e0298f772fc4164e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8302: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/index.html
  IGT_7108: a6e4162aa99b9f7ad42c3cbcffe7e8d4663febeb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/index.html

[-- Attachment #2: Type: text/html, Size: 7809 bytes --]

[igt-dev] ✓ Fi.CI.IGT: success for series starting with [1/4] lib/amdgpu: rename function parameter

[Patchwork]

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== Series Details ==

Series: series starting with [1/4] lib/amdgpu: rename function parameter
URL   : https://patchwork.freedesktop.org/series/112416/
State : success

== Summary ==

CI Bug Log - changes from IGT_7108_full -> IGTPW_8302_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/index.html

Participating hosts (10 -> 9)
------------------------------

  Missing    (1): shard-tglu-9 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_8302_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_softpin@evict-snoop-interruptible:
    - {shard-dg1}:        NOTRUN -> [SKIP][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-dg1-15/igt@gem_softpin@evict-snoop-interruptible.html

  
Known issues
------------

  Here are the changes found in IGTPW_8302_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-glk:          [PASS][2] -> [FAIL][3] ([i915#2842]) +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-glk4/igt@gem_exec_fair@basic-none-share@rcs0.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-glk6/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-apl:          NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-apl1/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
    - shard-apl:          [PASS][5] -> [INCOMPLETE][6] ([i915#7708])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-apl1/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-apl3/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html

  * igt@gem_spin_batch@user-each:
    - shard-apl:          [PASS][7] -> [FAIL][8] ([i915#2898])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-apl2/igt@gem_spin_batch@user-each.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-apl3/igt@gem_spin_batch@user-each.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#3886]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-apl1/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_chamelium@hdmi-frame-dump:
    - shard-snb:          NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-snb7/igt@kms_chamelium@hdmi-frame-dump.html

  * igt@kms_color_chamelium@ctm-0-50:
    - shard-apl:          NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-apl2/igt@kms_color_chamelium@ctm-0-50.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
    - shard-glk:          [PASS][12] -> [FAIL][13] ([i915#2346])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-apl:          NOTRUN -> [FAIL][14] ([i915#4767])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-apl6/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([i915#2122])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-apl:          NOTRUN -> [SKIP][17] ([fdo#109271]) +82 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-apl3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
    - shard-snb:          NOTRUN -> [SKIP][18] ([fdo#109271]) +17 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-snb7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-apl:          NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#658])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-apl6/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_vblank@pipe-b-wait-idle-hang:
    - shard-apl:          [PASS][20] -> [SKIP][21] ([fdo#109271])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-apl1/igt@kms_vblank@pipe-b-wait-idle-hang.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-apl1/igt@kms_vblank@pipe-b-wait-idle-hang.html
    - shard-glk:          [PASS][22] -> [SKIP][23] ([fdo#109271])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-glk7/igt@kms_vblank@pipe-b-wait-idle-hang.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-glk2/igt@kms_vblank@pipe-b-wait-idle-hang.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@most-busy-check-all@rcs0:
    - {shard-rkl}:        [FAIL][24] ([i915#7742]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html

  * igt@fbdev@unaligned-read:
    - {shard-rkl}:        [SKIP][26] ([i915#2582]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-2/igt@fbdev@unaligned-read.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-6/igt@fbdev@unaligned-read.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - {shard-rkl}:        [FAIL][28] ([i915#6268]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-5/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [FAIL][30] ([i915#2842]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-apl:          [FAIL][32] ([i915#2842]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-apl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-apl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - {shard-rkl}:        [FAIL][34] ([i915#2842]) -> [PASS][35] +3 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-1/igt@gem_exec_fair@basic-pace@rcs0.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-5/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - {shard-rkl}:        [SKIP][36] ([fdo#109313]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-1/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html

  * igt@gem_exec_reloc@basic-cpu-gtt:
    - {shard-rkl}:        [SKIP][38] ([i915#3281]) -> [PASS][39] +4 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-3/igt@gem_exec_reloc@basic-cpu-gtt.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-5/igt@gem_exec_reloc@basic-cpu-gtt.html

  * igt@gem_mmap_gtt@fault-concurrent-x:
    - shard-snb:          [CRASH][40] ([i915#5161]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-snb2/igt@gem_mmap_gtt@fault-concurrent-x.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-snb7/igt@gem_mmap_gtt@fault-concurrent-x.html

  * igt@gem_partial_pwrite_pread@writes-after-reads:
    - shard-apl:          [INCOMPLETE][42] ([i915#7708]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-apl2/igt@gem_partial_pwrite_pread@writes-after-reads.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-apl6/igt@gem_partial_pwrite_pread@writes-after-reads.html

  * igt@gem_pwrite_snooped:
    - {shard-rkl}:        [SKIP][44] ([i915#3282]) -> [PASS][45] +4 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-4/igt@gem_pwrite_snooped.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-5/igt@gem_pwrite_snooped.html

  * igt@gen9_exec_parse@unaligned-access:
    - {shard-rkl}:        [SKIP][46] ([i915#2527]) -> [PASS][47] +2 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-4/igt@gen9_exec_parse@unaligned-access.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-5/igt@gen9_exec_parse@unaligned-access.html

  * igt@i915_pm_rc6_residency@rc6-idle@bcs0:
    - {shard-dg1}:        [FAIL][48] ([i915#3591]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html

  * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
    - {shard-rkl}:        [SKIP][50] ([i915#1397]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@i915_selftest@live@gt_heartbeat:
    - shard-glk:          [DMESG-FAIL][52] ([i915#5334]) -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-glk6/igt@i915_selftest@live@gt_heartbeat.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-glk4/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1:
    - {shard-tglu}:       [FAIL][54] ([i915#2521]) -> [PASS][55]
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-tglu-3/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-tglu-5/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1.html

  * igt@kms_atomic@plane-overlay-legacy:
    - {shard-rkl}:        [SKIP][56] ([i915#1845] / [i915#4098]) -> [PASS][57] +21 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-5/igt@kms_atomic@plane-overlay-legacy.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-6/igt@kms_atomic@plane-overlay-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
    - shard-apl:          [FAIL][58] ([i915#2346]) -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html

  * igt@kms_fbcon_fbt@psr:
    - {shard-rkl}:        [SKIP][60] ([i915#3955]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-4/igt@kms_fbcon_fbt@psr.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-6/igt@kms_fbcon_fbt@psr.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][62] ([i915#79]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - {shard-rkl}:        [SKIP][64] ([i915#1849] / [i915#4098]) -> [PASS][65] +17 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_plane@pixel-format-source-clamping@pipe-b-planes:
    - {shard-rkl}:        [SKIP][66] ([i915#1849]) -> [PASS][67] +1 similar issue
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-1/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-6/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html

  * igt@kms_psr@sprite_plane_onoff:
    - {shard-rkl}:        [SKIP][68] ([i915#1072]) -> [PASS][69] +4 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-1/igt@kms_psr@sprite_plane_onoff.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-6/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-snb:          [SKIP][70] ([fdo#109271]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-snb5/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-snb7/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  * igt@perf@mi-rpc:
    - {shard-rkl}:        [SKIP][72] ([i915#2434]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-rkl-2/igt@perf@mi-rpc.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-rkl-5/igt@perf@mi-rpc.html

  * igt@sysfs_timeslice_duration@timeout@vecs0:
    - {shard-dg1}:        [FAIL][74] ([i915#1755]) -> [PASS][75] +2 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-dg1-14/igt@sysfs_timeslice_duration@timeout@vecs0.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-dg1-14/igt@sysfs_timeslice_duration@timeout@vecs0.html

  
#### Warnings ####

  * igt@kms_plane_alpha_blend@alpha-basic@pipe-c-dp-1:
    - shard-apl:          [FAIL][76] ([i915#4573]) -> [DMESG-FAIL][77] ([IGT#6]) +1 similar issue
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7108/shard-apl7/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-dp-1.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/shard-apl3/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-dp-1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2898]: https://gitlab.freedesktop.org/drm/intel/issues/2898
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3639]: https://gitlab.freedesktop.org/drm/intel/issues/3639
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
  [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#5161]: https://gitlab.freedesktop.org/drm/intel/issues/5161
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
  [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6259]: https://gitlab.freedesktop.org/drm/intel/issues/6259
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
  [i915#7681]: https://gitlab.freedesktop.org/drm/intel/issues/7681
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
  [i915#7708]: https://gitlab.freedesktop.org/drm/intel/issues/7708
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7108 -> IGTPW_8302

  CI-20190529: 20190529
  CI_DRM_12546: 07a684fbd4d0f5e284e8a782e0298f772fc4164e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_8302: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/index.html
  IGT_7108: a6e4162aa99b9f7ad42c3cbcffe7e8d4663febeb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8302/index.html

[-- Attachment #2: Type: text/html, Size: 20960 bytes --]

Re: [igt-dev] [PATCH 1/4] lib/amdgpu: rename function parameter

[Christian König]

Reviewed-by: Christian König <christian.koenig@amd.com> for patch #1 and #2.

Acked-by: Christian König <christian.koenig@amd.com> fro patch #3 and #4.

Thanks,
Christian.

Am 05.01.23 um 01:53 schrieb vitaly.prosyak@amd.com:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>
> No functional change just cosmetic.
> Rename flags parameter to alloc_flags for clarity.
> There are mapping flags.
>
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
>   lib/amdgpu/amd_memory.c | 10 ++++------
>   lib/amdgpu/amd_memory.h |  2 +-
>   2 files changed, 5 insertions(+), 7 deletions(-)
>
> diff --git a/lib/amdgpu/amd_memory.c b/lib/amdgpu/amd_memory.c
> index 0aa400ac8..e3432a954 100644
> --- a/lib/amdgpu/amd_memory.c
> +++ b/lib/amdgpu/amd_memory.c
> @@ -41,7 +41,7 @@
>   				      uint64_t size,
>   				      uint64_t alignment,
>   				      uint32_t type,
> -				      uint64_t flags,
> +				      uint64_t alloc_flags,
>   				      uint64_t *vmc_addr,
>   				      amdgpu_va_handle *va_handle)
>   {
> @@ -49,7 +49,7 @@
>   		.alloc_size = size,
>   		.phys_alignment = alignment,
>   		.preferred_heap = type,
> -		.flags = flags,
> +		.flags = alloc_flags,
>   	};
>   	amdgpu_bo_handle buf_handle;
>   	int r;
> @@ -57,10 +57,8 @@
>   	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
>   	igt_assert_eq(r, 0);
>   
> -	r = amdgpu_va_range_alloc(device_handle,
> -				  amdgpu_gpu_va_range_general,
> -				  size, alignment, 0, vmc_addr,
> -				  va_handle, 0);
> +	r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general,
> +				   size, alignment, 0, vmc_addr, va_handle, 0);
>   	igt_assert_eq(r, 0);
>   
>   	r = amdgpu_bo_va_op(buf_handle, 0, size, *vmc_addr, 0, AMDGPU_VA_OP_MAP);
> diff --git a/lib/amdgpu/amd_memory.h b/lib/amdgpu/amd_memory.h
> index 77fd099b0..a06f88923 100644
> --- a/lib/amdgpu/amd_memory.h
> +++ b/lib/amdgpu/amd_memory.h
> @@ -35,7 +35,7 @@ gpu_mem_alloc(amdgpu_device_handle device_handle,
>   				      uint64_t size,
>   				      uint64_t alignment,
>   				      uint32_t type,
> -				      uint64_t flags,
> +				      uint64_t alloc_flags,
>   				      uint64_t *vmc_addr,
>   				      amdgpu_va_handle *va_handle);
>   int

Re: [igt-dev] [PATCH 1/4] lib/amdgpu: rename function parameter

[Kamil Konieczny]

Hi Vitaly,

On 2023-01-04 at 19:53:17 -0500, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
> 
> No functional change just cosmetic.
> Rename flags parameter to alloc_flags for clarity.
> There are mapping flags.
--^
Maybe put these in same sentence ?

> 
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
>  lib/amdgpu/amd_memory.c | 10 ++++------
>  lib/amdgpu/amd_memory.h |  2 +-
>  2 files changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/lib/amdgpu/amd_memory.c b/lib/amdgpu/amd_memory.c
> index 0aa400ac8..e3432a954 100644
> --- a/lib/amdgpu/amd_memory.c
> +++ b/lib/amdgpu/amd_memory.c
> @@ -41,7 +41,7 @@
>  				      uint64_t size,
>  				      uint64_t alignment,
>  				      uint32_t type,
> -				      uint64_t flags,
> +				      uint64_t alloc_flags,
>  				      uint64_t *vmc_addr,
>  				      amdgpu_va_handle *va_handle)
>  {
> @@ -49,7 +49,7 @@
>  		.alloc_size = size,
>  		.phys_alignment = alignment,
>  		.preferred_heap = type,
> -		.flags = flags,
> +		.flags = alloc_flags,
>  	};
>  	amdgpu_bo_handle buf_handle;
>  	int r;
> @@ -57,10 +57,8 @@
>  	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
>  	igt_assert_eq(r, 0);
>  
> -	r = amdgpu_va_range_alloc(device_handle,
> -				  amdgpu_gpu_va_range_general,
> -				  size, alignment, 0, vmc_addr,
> -				  va_handle, 0);
> +	r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general,
> +				   size, alignment, 0, vmc_addr, va_handle, 0);

This is unrelated to description.

Regards,
Kamil

>  	igt_assert_eq(r, 0);
>  
>  	r = amdgpu_bo_va_op(buf_handle, 0, size, *vmc_addr, 0, AMDGPU_VA_OP_MAP);
> diff --git a/lib/amdgpu/amd_memory.h b/lib/amdgpu/amd_memory.h
> index 77fd099b0..a06f88923 100644
> --- a/lib/amdgpu/amd_memory.h
> +++ b/lib/amdgpu/amd_memory.h
> @@ -35,7 +35,7 @@ gpu_mem_alloc(amdgpu_device_handle device_handle,
>  				      uint64_t size,
>  				      uint64_t alignment,
>  				      uint32_t type,
> -				      uint64_t flags,
> +				      uint64_t alloc_flags,
>  				      uint64_t *vmc_addr,
>  				      amdgpu_va_handle *va_handle);
>  int
> -- 
> 2.25.1
> 

Re: [igt-dev] [PATCH 2/4] lib/amdgpu: move function to another file

[Kamil Konieczny]

Hi Vitaly,

On 2023-01-04 at 19:53:18 -0500, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
> 
> No functional change just cosmetic.

Please do not mix in adding some debug printing with code moving.

> Move function amdgpu_open_devices to the shared file
> since other tests will also use it.
> 
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
>  lib/amdgpu/amd_ip_blocks.c  | 94 ++++++++++++++++++++++++++++++++++---
>  lib/amdgpu/amd_ip_blocks.h  |  5 ++
>  lib/amdgpu/amd_pci_unplug.c | 69 ---------------------------
>  lib/amdgpu/amd_pci_unplug.h |  3 +-
>  4 files changed, 93 insertions(+), 78 deletions(-)
> 
> diff --git a/lib/amdgpu/amd_ip_blocks.c b/lib/amdgpu/amd_ip_blocks.c
> index 3331c40bd..ce1bddffc 100644
> --- a/lib/amdgpu/amd_ip_blocks.c
> +++ b/lib/amdgpu/amd_ip_blocks.c
> @@ -22,6 +22,8 @@
>   *
>   *
>   */
> +#include <fcntl.h>
> +
>  #include "amd_memory.h"
>  #include "amd_ip_blocks.h"
>  #include "amd_PM4.h"
> @@ -616,21 +618,30 @@ int setup_amdgpu_ip_blocks(uint32_t major, uint32_t minor, struct amdgpu_gpu_inf
>  		igt_info("amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
>  			 amdinfo->family_id, amdinfo->chip_external_rev);
>  		return -1;
> +	} else {
> +		igt_info("amdgpu: %s (family_id, chip_external_rev): (%u, %u)\n",
> +				info->name, amdinfo->family_id, amdinfo->chip_external_rev);
>  	}
>  
> -	if (info->family >= CHIP_SIENNA_CICHLID)
> +	if (info->family >= CHIP_SIENNA_CICHLID) {
>  		info->chip_class = GFX10_3;
> -	else if (info->family >= CHIP_NAVI10)
> +		igt_info("amdgpu: chip_class GFX10_3\n");
--------------- ^
Do you really want that at every function use ? Maybe better
to use igt_debug and have separate function for printing ?

> +	} else if (info->family >= CHIP_NAVI10) {
>  		info->chip_class = GFX10;
> -	else if (info->family >= CHIP_VEGA10)
> +		igt_info("amdgpu: chip_class GFX10\n");
> +	} else if (info->family >= CHIP_VEGA10) {
>  		info->chip_class = GFX9;
> -	else if (info->family >= CHIP_TONGA)
> +		igt_info("amdgpu: chip_class GFX9\n");
> +	} else if (info->family >= CHIP_TONGA) {
>  		info->chip_class = GFX8;
> -	else if (info->family >= CHIP_BONAIRE)
> +		igt_info("amdgpu: chip_class GFX8\n");
> +	} else if (info->family >= CHIP_BONAIRE) {
>  		info->chip_class = GFX7;
> -	else if (info->family >= CHIP_TAHITI)
> +		igt_info("amdgpu: chip_class GFX7\n");
> +	} else if (info->family >= CHIP_TAHITI) {
>  		info->chip_class = GFX6;
> -	else {
> +		igt_info("amdgpu: chip_class GFX6\n");
> +	} else {
>  		igt_info("amdgpu: Unknown family.\n");

Here you can print detailed info.

>  		return -1;
>  	}
> @@ -663,3 +674,72 @@ int setup_amdgpu_ip_blocks(uint32_t major, uint32_t minor, struct amdgpu_gpu_inf
>  
>  	return 0;
>  }
> +

Please write description of each new library function.

> +int
> +amdgpu_open_devices(bool open_render_node, int  max_cards_supported, int drm_amdgpu_fds[])
> +{
> +	drmDevicePtr devices[MAX_CARDS_SUPPORTED];
> +	int i;
> +	int drm_node;
> +	int amd_index = 0;
> +	int drm_count;
> +	int fd;
> +	drmVersionPtr version;
> +
> +	for (i = 0; i < max_cards_supported && i < MAX_CARDS_SUPPORTED; i++)
> +		drm_amdgpu_fds[i] = -1;
> +
> +	drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED);
> +
> +	if (drm_count < 0) {
> +		fprintf(stderr, "drmGetDevices2() returned an error %d\n", drm_count);
--------------- ^
We have igt_info() and igt_debug() messages, please use them.

> +		return 0;
> +	}
> +
> +	for (i = 0; i < drm_count; i++) {
> +		/* If this is not PCI device, skip*/
> +		if (devices[i]->bustype != DRM_BUS_PCI)
> +			continue;
> +
> +		/* If this is not AMD GPU vender ID, skip*/
> +		if (devices[i]->deviceinfo.pci->vendor_id != 0x1002)
> +			continue;
> +
> +		if (open_render_node)
> +			drm_node = DRM_NODE_RENDER;
> +		else
> +			drm_node = DRM_NODE_PRIMARY;
> +
> +		fd = -1;
> +		if (devices[i]->available_nodes & 1 << drm_node)
> +			fd = open(
> +				devices[i]->nodes[drm_node],
> +				O_RDWR | O_CLOEXEC);
> +
> +		/* This node is not available. */
> +		if (fd < 0) continue;
--------------------------- ^
This should be at line below.

> +
> +		version = drmGetVersion(fd);
> +		if (!version) {
> +			fprintf(stderr, "Warning: Cannot get version for %s." "Error is %s\n",
---------------------------------------------------------------------------- ^^
Did you mean putting this at line below ?

Please use checkpatch script from linux kernel before sending
patches, it can find some problems with formatting and spelling.

If that was in original code then mention that corrections in
patch message.

> +				devices[i]->nodes[drm_node], strerror(errno));
> +			close(fd);
> +			continue;
> +		}
> +
> +		if (strcmp(version->name, "amdgpu")) {
> +			/* This is not AMDGPU driver, skip.*/
> +			drmFreeVersion(version);
> +			close(fd);
> +			continue;
> +		}
> +
> +		drmFreeVersion(version);
> +
> +		drm_amdgpu_fds[amd_index] = fd;
> +		amd_index++;
> +	}
> +
> +	drmFreeDevices(devices, drm_count);
> +	return amd_index;
> +}
> diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
> index 908aacde0..b3620c00f 100644
> --- a/lib/amdgpu/amd_ip_blocks.h
> +++ b/lib/amdgpu/amd_ip_blocks.h
> @@ -27,6 +27,8 @@
>  
>  #include "amd_registers.h"
>  
> +#define MAX_CARDS_SUPPORTED 4
> +
>  enum amd_ip_block_type {
>  	AMD_IP_GFX,
>  	AMD_IP_COMPUTE,
> @@ -136,4 +138,7 @@ struct amdgpu_cmd_base* get_cmd_base(void);
>  
>  void free_cmd_base(struct amdgpu_cmd_base *base);
>  
> +int
> +amdgpu_open_devices(bool open_render_node, int  max_cards_supported, int drm_amdgpu_fds[]);
------------------------------------------------ ^^
Two spaces, one is enough.

Regards,
Kamil

> +
>  #endif
> diff --git a/lib/amdgpu/amd_pci_unplug.c b/lib/amdgpu/amd_pci_unplug.c
> index 28b3ae393..078398b5e 100644
> --- a/lib/amdgpu/amd_pci_unplug.c
> +++ b/lib/amdgpu/amd_pci_unplug.c
> @@ -21,7 +21,6 @@
>   *
>  */
>  #include <linux/limits.h>
> -#include <sys/types.h>
>  #include <fcntl.h>
>  #include <sys/stat.h>
>  #include <pthread.h>
> @@ -35,74 +34,6 @@
>  #include "xalloc.h"
>  #include "amd_ip_blocks.h"
>  
> -static int
> -amdgpu_open_devices(bool open_render_node, int  max_cards_supported, int drm_amdgpu_fds[])
> -{
> -	drmDevicePtr devices[MAX_CARDS_SUPPORTED];
> -	int i;
> -	int drm_node;
> -	int amd_index = 0;
> -	int drm_count;
> -	int fd;
> -	drmVersionPtr version;
> -
> -	for (i = 0; i < max_cards_supported && i < MAX_CARDS_SUPPORTED; i++)
> -		drm_amdgpu_fds[i] = -1;
> -
> -	drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED);
> -
> -	if (drm_count < 0) {
> -		fprintf(stderr, "drmGetDevices2() returned an error %d\n", drm_count);
> -		return 0;
> -	}
> -
> -	for (i = 0; i < drm_count; i++) {
> -		/* If this is not PCI device, skip*/
> -		if (devices[i]->bustype != DRM_BUS_PCI)
> -			continue;
> -
> -		/* If this is not AMD GPU vender ID, skip*/
> -		if (devices[i]->deviceinfo.pci->vendor_id != 0x1002)
> -			continue;
> -
> -		if (open_render_node)
> -			drm_node = DRM_NODE_RENDER;
> -		else
> -			drm_node = DRM_NODE_PRIMARY;
> -
> -		fd = -1;
> -		if (devices[i]->available_nodes & 1 << drm_node)
> -			fd = open(
> -				devices[i]->nodes[drm_node],
> -				O_RDWR | O_CLOEXEC);
> -
> -		/* This node is not available. */
> -		if (fd < 0) continue;
> -
> -		version = drmGetVersion(fd);
> -		if (!version) {
> -			fprintf(stderr, "Warning: Cannot get version for %s." "Error is %s\n",
> -				devices[i]->nodes[drm_node], strerror(errno));
> -			close(fd);
> -			continue;
> -		}
> -
> -		if (strcmp(version->name, "amdgpu")) {
> -			/* This is not AMDGPU driver, skip.*/
> -			drmFreeVersion(version);
> -			close(fd);
> -			continue;
> -		}
> -
> -		drmFreeVersion(version);
> -
> -		drm_amdgpu_fds[amd_index] = fd;
> -		amd_index++;
> -	}
> -
> -	drmFreeDevices(devices, drm_count);
> -	return amd_index;
> -}
>  static bool
>  amdgpu_node_is_drm(int maj, int min)
>  {
> diff --git a/lib/amdgpu/amd_pci_unplug.h b/lib/amdgpu/amd_pci_unplug.h
> index 509b6ec4c..35d4dce3a 100644
> --- a/lib/amdgpu/amd_pci_unplug.h
> +++ b/lib/amdgpu/amd_pci_unplug.h
> @@ -26,8 +26,7 @@
>  
>  #include <amdgpu.h>
>  #include <amdgpu_drm.h>
> -
> -#define MAX_CARDS_SUPPORTED 4
> +#include "amd_ip_blocks.h"
>  
>  struct amd_pci_unplug_setup {
>  	uint32_t  major_version_req;
> -- 
> 2.25.1
> 

Re: [igt-dev] [PATCH 3/4] lib/amdgpu: add cp dma helper functions

[Kamil Konieczny]

Hi Vitaly,

On 2023-01-04 at 19:53:19 -0500, vitaly.prosyak@amd.com wrote:
> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
> 
> CP DMA tests are executed between GTT and VRAM of a single chip
> and also between separate ASICs.
> 
>  Port cp dma tests from drm_lib with the following improvements:
>  - remove many global variables which restrict scalability and readability
>  - reuse memory allocation helpers vs new helpers as in the original test
>  - use helper structs to reduce the number of parameters in functions.
> 
> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
> ---
>  lib/amdgpu/amd_cp_dma.c | 446 ++++++++++++++++++++++++++++++++++++++++
>  lib/amdgpu/amd_cp_dma.h |  41 ++++
>  lib/meson.build         |   3 +-
>  3 files changed, 489 insertions(+), 1 deletion(-)
>  create mode 100644 lib/amdgpu/amd_cp_dma.c
>  create mode 100644 lib/amdgpu/amd_cp_dma.h
> 
> diff --git a/lib/amdgpu/amd_cp_dma.c b/lib/amdgpu/amd_cp_dma.c
> new file mode 100644
> index 000000000..265cffa4c
> --- /dev/null
> +++ b/lib/amdgpu/amd_cp_dma.c
> @@ -0,0 +1,446 @@
> +/* SPDX-License-Identifier: MIT

Put newline here.

> + * Copyright 2023 Advanced Micro Devices, Inc.
> + *

Please delete text below, SPDX is just replacing this,
also use checkpatch and correct whitespace/newline errors
in this and 4/4 patch. This should be done also below.

Add also description to public lib functions.

> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> +*/
> +#include <unistd.h>
> +#include <amdgpu.h>

Put newline here.

> +#include "amdgpu_drm.h"
> +#include "amd_memory.h"
> +#include "amd_cp_dma.h"
> +
> +

Delete one empty line.

> +#define IB_SIZE 4096
> +#define MAX_RESOURCES 3
> +
> +#define DMA_SIZE 4097 
----------------------- ^
Delete space at end of line, btw DMA size is 4KB + 1 byte ?

> +#define DMA_DATA_BYTE 0xea
> +#define DMA_SIZE_MAX (1<<26)
> +
> +struct amdgpu_cp_dma_bo {
> +	amdgpu_bo_handle buf_handle;
> +	amdgpu_va_handle va_handle;
> +	uint64_t gpu_va;
> +	uint64_t size;
> +};
> +
> +struct amdgpu_cp_dma_ib {
> +	amdgpu_bo_handle ib_handle;
> +	uint32_t *ib_cpu;
> +	uint64_t ib_mc_address;
> +	amdgpu_va_handle ib_va_handle;
> +};
> +
> +struct amdgpu_cp_dma_contex {
> +	amdgpu_bo_handle resources[MAX_RESOURCES];
> +	unsigned num_resources;
> +	uint32_t num_dword;
> +	uint8_t *reference_data;
> +};
> +
> +static int
> +import_dma_buf_to_bo(amdgpu_device_handle dev, int dmabuf_fd,
----------------------- ^
> +					 struct amdgpu_cp_dma_bo *bo)
---------------------------------------- ^
Adjust this line to one above.

> +{
> +	amdgpu_va_handle va_handle;
> +	uint64_t vmc_addr;
> +	int r;
> +	struct amdgpu_bo_import_result bo_import_result = {};
> +
> +	r = amdgpu_bo_import(dev, amdgpu_bo_handle_type_dma_buf_fd,
---------------------------- ^
> +			dmabuf_fd, &bo_import_result);
----------------------- ^
Adjust this line to one above.

These adjustment should be done in many places below.

Regards,
Kamil

> +	if (r)
> +		goto error_bo_import;
> +
> +	r = amdgpu_va_range_alloc(dev, amdgpu_gpu_va_range_general,
> +				bo_import_result.alloc_size, 0, 0,
> +				&vmc_addr, &va_handle, 0);
> +	if (r)
> +		goto error_va_alloc;
> +
> +	r = amdgpu_bo_va_op(bo_import_result.buf_handle, 0,
> +			bo_import_result.alloc_size, vmc_addr,
> +			AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
> +			AMDGPU_VM_PAGE_EXECUTABLE,
> +			AMDGPU_VA_OP_MAP);
> +	if (r)
> +		goto error_va_map;
> +
> +	bo->buf_handle = bo_import_result.buf_handle;
> +	bo->va_handle = va_handle;
> +	bo->gpu_va = vmc_addr;
> +	bo->size = bo_import_result.alloc_size;
> +
> +	return 0;
> +
> +error_va_map:
> +	amdgpu_bo_va_op(bo_import_result.buf_handle, 0,
> +			bo_import_result.alloc_size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
> +
> +error_va_alloc:
> +	amdgpu_va_range_free(va_handle);
> +
> +error_bo_import:
> +	amdgpu_bo_free(bo_import_result.buf_handle);
> +
> +	return r;
> +}
> +
> +static int
> +free_bo(struct amdgpu_cp_dma_bo bo)
> +{
> +	int r;
> +	r = amdgpu_bo_va_op(bo.buf_handle, 0, bo.size, bo.gpu_va, 0, AMDGPU_VA_OP_UNMAP);
> +	igt_assert_eq(r, 0);
> +
> +	r = amdgpu_va_range_free(bo.va_handle);
> +	igt_assert_eq(r, 0);
> +
> +	r = amdgpu_bo_free(bo.buf_handle);
> +	igt_assert_eq(r, 0);
> +
> +	return r;
> +}
> +
> +static int
> +submit_and_sync(amdgpu_device_handle device_handle, unsigned ip_type,
> +		  amdgpu_context_handle context_handle, uint64_t ib_mc_address,
> +		  struct amdgpu_cp_dma_contex *dma_contex)
> +{
> +	struct amdgpu_cs_request ibs_request = {0};
> +	struct amdgpu_cs_ib_info ib_info = {0};
> +	struct amdgpu_cs_fence fence_status = {0};
> +	uint32_t expired;
> +	int r;
> +
> +	r = amdgpu_bo_list_create(device_handle,
> +			dma_contex->num_resources, dma_contex->resources,
> +			NULL, &ibs_request.resources);
> +	igt_assert_eq(r, 0);
> +
> +	ib_info.ib_mc_address = ib_mc_address;
> +	ib_info.size = dma_contex->num_dword;
> +
> +	ibs_request.ip_type = ip_type;
> +	ibs_request.number_of_ibs = 1;
> +	ibs_request.ibs = &ib_info;
> +	ibs_request.fence_info.handle = NULL;
> +
> +	r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
> +	igt_assert_eq(r, 0);
> +
> +	r = amdgpu_bo_list_destroy(ibs_request.resources);
> +	igt_assert_eq(r, 0);
> +
> +	fence_status.context = context_handle;
> +	fence_status.ip_type = ip_type;
> +	fence_status.fence = ibs_request.seq_no;
> +
> +	r = amdgpu_cs_query_fence_status(&fence_status, AMDGPU_TIMEOUT_INFINITE,
> +									 0, &expired);
> +	return r;
> +}
> +
> +static void
> +cp_dma_cmd(const struct amdgpu_cp_dma_ib *ib, struct amdgpu_cp_dma_contex *dma_contex,
> +	     const struct amdgpu_cp_dma_bo *src_bo, const struct amdgpu_cp_dma_bo *dst_bo)
> +{
> +	/* TODO use spec defines */
> +	ib->ib_cpu[0] = 0xc0055000;
> +	ib->ib_cpu[1] = 0x80000000;
> +	ib->ib_cpu[2] = src_bo->gpu_va & 0x00000000ffffffff;
> +	ib->ib_cpu[3] = (src_bo->gpu_va & 0xffffffff00000000) >> 32;
> +	ib->ib_cpu[4] = dst_bo->gpu_va & 0x00000000ffffffff;
> +	ib->ib_cpu[5] = (dst_bo->gpu_va & 0xffffffff00000000) >> 32;
> +	// size is read from the lower 26bits. 
> +	ib->ib_cpu[6] = ((1 << 26) - 1) & DMA_SIZE;
> +	ib->ib_cpu[7] = 0xffff1000;
> +
> +	dma_contex->num_dword = 8;
> +
> +	dma_contex->resources[0] = src_bo->buf_handle;
> +	dma_contex->resources[1] = dst_bo->buf_handle;
> +	dma_contex->resources[2] = ib->ib_handle;
> +	dma_contex->num_resources = 3;
> +}
> +
> +static int
> +amdgpu_cp_dma(amdgpu_device_handle device_handle, unsigned ip_type, amdgpu_context_handle context_handle,
> +		const struct amdgpu_cp_dma_ib *ib, struct amdgpu_cp_dma_contex *dma_contex,
> +		uint32_t src_heap, uint32_t dst_heap)
> +{
> +	int r;
> +	struct amdgpu_cp_dma_bo src_bo = {0};
> +	struct amdgpu_cp_dma_bo dst_bo = {0};
> +	void *src_bo_cpu;
> +	void *dst_bo_cpu;
> +
> +	/* allocate the src bo, set its data to DMA_DATA_BYTE */
> +	src_bo.buf_handle = gpu_mem_alloc(device_handle, DMA_SIZE, 4096,
> +			src_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &src_bo.gpu_va, &src_bo.va_handle);
> +
> +	r = amdgpu_bo_cpu_map(src_bo.buf_handle, (void **)&src_bo_cpu);
> +	igt_assert_eq(r, 0);
> +	memset(src_bo_cpu, DMA_DATA_BYTE, DMA_SIZE);
> +
> +	r = amdgpu_bo_cpu_unmap(src_bo.buf_handle);
> +	igt_assert_eq(r, 0);
> +
> +	/* allocate the dst bo and clear its content to all 0 */
> +	dst_bo.buf_handle = gpu_mem_alloc(device_handle, DMA_SIZE, 4096,
> +			dst_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &dst_bo.gpu_va, &dst_bo.va_handle);
> +
> +	r = amdgpu_bo_cpu_map(dst_bo.buf_handle, (void **)&dst_bo_cpu);
> +	igt_assert_eq(r, 0);
> +
> +	memset(dst_bo_cpu, 0, DMA_SIZE);
> +
> +	/* record CP DMA command and dispatch the command */
> +	cp_dma_cmd(ib, dma_contex, &src_bo, &dst_bo);
> +
> +	r = submit_and_sync(device_handle, ip_type, context_handle, ib->ib_mc_address ,dma_contex);
> +	igt_assert_eq(r, 0);
> +
> +	/* verify the dst bo is filled with DMA_DATA_BYTE */
> +	r = memcmp(dst_bo_cpu, dma_contex->reference_data, DMA_SIZE);
> +	igt_assert_eq(r, 0);
> +
> +	r = amdgpu_bo_cpu_unmap(dst_bo.buf_handle);
> +	igt_assert_eq(r, 0);
> +
> +	r = free_bo(src_bo);
> +	igt_assert_eq(r, 0);
> +
> +	r = free_bo(dst_bo);
> +	igt_assert_eq(r, 0);
> +
> +	return r;
> +}
> +
> +static int
> +amdgpu_cp_dma_p2p(amdgpu_device_handle device_handle,
> +		    amdgpu_device_handle exporting_device_handle,
> +		    unsigned ip_type, amdgpu_context_handle context_handle,
> +		    uint32_t src_heap, uint32_t dst_heap,
> +		    const struct amdgpu_cp_dma_ib *ib, struct amdgpu_cp_dma_contex *dma_contex)
> +{
> +	int r;
> +	struct amdgpu_cp_dma_bo exported_bo = {0};
> +	int dma_buf_fd;
> +	int dma_buf_fd_dup;
> +	struct amdgpu_cp_dma_bo src_bo = {0};
> +	struct amdgpu_cp_dma_bo imported_dst_bo = {0};
> +
> +	void *exported_bo_cpu;
> +	void *src_bo_cpu;
> +
> +	/* allocate a bo on the peer device and export it to dma-buf */
> +	exported_bo.buf_handle = gpu_mem_alloc(exporting_device_handle, DMA_SIZE, 4096,
> +			src_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &exported_bo.gpu_va, &exported_bo.va_handle);
> +
> +	/* map the exported bo and clear its content to 0 */
> +	r = amdgpu_bo_cpu_map(exported_bo.buf_handle, (void **)&exported_bo_cpu);
> +	igt_assert_eq(r, 0);
> +	memset(exported_bo_cpu, 0, DMA_SIZE);
> +
> +	r = amdgpu_bo_export(exported_bo.buf_handle,
> +			amdgpu_bo_handle_type_dma_buf_fd, (uint32_t*)&dma_buf_fd);
> +	igt_assert_eq(r, 0);
> +
> +    // According to amdgpu_drm:
> +	// "Buffer must be "imported" only using new "fd"
> +	// (different from one used by "exporter")"
> +	dma_buf_fd_dup = dup(dma_buf_fd);
> +	r = close(dma_buf_fd);
> +	igt_assert_eq(r, 0);
> +
> +	/* import the dma-buf to the executing device, imported bo is the DMA destination */
> +	r = import_dma_buf_to_bo(device_handle, dma_buf_fd_dup, &imported_dst_bo);
> +	igt_assert_eq(r, 0);
> +
> +	r = close(dma_buf_fd_dup);
> +	igt_assert_eq(r, 0);
> +
> +	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> +	/* allocate the src bo and set its content to DMA_DATA_BYTE */
> +
> +	src_bo.buf_handle = gpu_mem_alloc(device_handle, DMA_SIZE, 4096,
> +			dst_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &src_bo.gpu_va, &src_bo.va_handle);
> +
> +	igt_assert_eq(r, 0);
> +
> +	r = amdgpu_bo_cpu_map(src_bo.buf_handle, (void **)&src_bo_cpu);
> +	igt_assert_eq(r, 0);
> +
> +	memset(src_bo_cpu, DMA_DATA_BYTE, DMA_SIZE);
> +
> +	r = amdgpu_bo_cpu_unmap(src_bo.buf_handle);
> +	igt_assert_eq(r, 0);
> +
> +	/* record CP DMA command and dispatch the command */
> +	cp_dma_cmd(ib, dma_contex, &src_bo, &imported_dst_bo);
> +
> +	r = submit_and_sync(device_handle, ip_type, context_handle, ib->ib_mc_address ,dma_contex);
> +
> +	igt_assert_eq(r, 0);
> +
> +	/* verify the exported_bo_cpu is filled with DMA_DATA_BYTE */
> +	r = memcmp(exported_bo_cpu, dma_contex->reference_data, DMA_SIZE);
> +	igt_assert_eq(r, 0);
> +
> +	r = amdgpu_bo_cpu_unmap(exported_bo.buf_handle);
> +	igt_assert_eq(r, 0);
> +
> +	r = free_bo(exported_bo);
> +	igt_assert_eq(r, 0);
> +
> +	r = free_bo(imported_dst_bo);
> +	igt_assert_eq(r, 0);
> +
> +	r = free_bo(src_bo);
> +	igt_assert_eq(r, 0);
> +
> +	return r;
> +}
> +
> +static int
> +amdgpu_cp_dma_misc(amdgpu_device_handle device_handle, unsigned ip_type,
> +		     uint32_t src_heap, uint32_t dst_heap)
> +{
> +	amdgpu_context_handle context_handle;
> +	struct amdgpu_cp_dma_contex dma_contex = {};
> +	struct amdgpu_cp_dma_ib dma_ib = {};
> +	int r;
> +
> +	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> +	igt_assert_eq(r, 0);
> +	r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
> +					AMDGPU_GEM_DOMAIN_GTT, 0,
> +					&dma_ib.ib_handle, (void**)&dma_ib.ib_cpu,
> +					&dma_ib.ib_mc_address, &dma_ib.ib_va_handle);
> +	igt_assert_eq(r, 0);
> +
> +	dma_contex.reference_data = (uint8_t*)malloc(DMA_SIZE);
> +	memset(dma_contex.reference_data, DMA_DATA_BYTE, DMA_SIZE);
> +
> +	r = amdgpu_cp_dma(device_handle, ip_type, context_handle, &dma_ib,
> +					  &dma_contex, src_heap, dst_heap);
> +	igt_assert_eq(r, 0);
> +
> + 	amdgpu_cs_ctx_free(context_handle);
> + 	free(dma_contex.reference_data);
> + 	amdgpu_bo_unmap_and_free(dma_ib.ib_handle, dma_ib.ib_va_handle,
> + 							 dma_ib.ib_mc_address, IB_SIZE);
> +
> +	return r;
> +}
> +
> +static int
> +amdgpu_cp_dma_misc_p2p(amdgpu_device_handle device_handle,
> +			 amdgpu_device_handle exporting_device_handle,
> +			 unsigned ip_type,
> +			 uint32_t src_heap, uint32_t dst_heap)
> +{
> +	amdgpu_context_handle context_handle;
> +	struct amdgpu_cp_dma_contex dma_contex = {};
> +	struct amdgpu_cp_dma_ib dma_ib = {};
> +	int r;
> +
> +	/* create context */
> +	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
> +	igt_assert_eq(r, 0);
> +
> +	/* init dma_ib */
> +	r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
> +					AMDGPU_GEM_DOMAIN_GTT, 0,
> +					&dma_ib.ib_handle, (void**)&dma_ib.ib_cpu,
> +					&dma_ib.ib_mc_address, &dma_ib.ib_va_handle);
> +	igt_assert_eq(r, 0);
> +
> +	/* init dma context */
> +	dma_contex.reference_data = (uint8_t*)malloc(DMA_SIZE);
> +	memset(dma_contex.reference_data, DMA_DATA_BYTE, DMA_SIZE);
> +
> +	r = amdgpu_cp_dma_p2p(device_handle, exporting_device_handle, ip_type, context_handle,
> +						  src_heap, dst_heap, &dma_ib, &dma_contex);
> +	igt_assert_eq(r, 0);
> +
> + 	amdgpu_cs_ctx_free(context_handle);
> + 	free(dma_contex.reference_data);
> + 	amdgpu_bo_unmap_and_free(dma_ib.ib_handle, dma_ib.ib_va_handle,
> + 							 dma_ib.ib_mc_address, IB_SIZE);
> +
> +	return r;
> +}
> +
> +bool
> +amdgpu_cp_dma_misc_is_supported(const struct amdgpu_gpu_info *gpu_info)
> +{
> +	/* why this restiction is here? */
> +	/*if (!(gpu_info->family_id >= AMDGPU_FAMILY_AI &&
> +			gpu_info->family_id <= AMDGPU_FAMILY_NV)) {
> +		return false;
> +	}*/
> +	return true;
> +}
> +
> +bool
> +asic_is_gfx_pipe_removed(const struct amdgpu_gpu_info *gpu_info)
> +{
> +	int chip_id;
> +
> +	if (gpu_info->family_id != AMDGPU_FAMILY_AI)
> +		return false;
> +
> +	chip_id = gpu_info->chip_external_rev - gpu_info->chip_rev;
> +
> +	switch(chip_id) {
> +	/* Arcturus */
> +	case 0x32:
> +	/* Aldebaran */
> +	case 0x3c:
> +		return true; /* the gfx pipe is removed */
> +	}
> +	return false;
> +}
> +
> +bool
> +amdgpu_cp_dma_misc_p2p_is_supported(const struct amdgpu_gpu_info *gpu_info)
> +{
> +	bool ret = amdgpu_cp_dma_misc_is_supported(gpu_info);
> +	return ret;
> +}
> +
> +
> +int
> +amdgpu_cp_dma_generic(amdgpu_device_handle device_handle,
> +					  amdgpu_device_handle exporting_device_handle, unsigned ip_type,
> +					  uint32_t src_heap, uint32_t dst_heap)
> +{
> +	int r;
> +	if (exporting_device_handle != NULL )
> +		r = amdgpu_cp_dma_misc_p2p( device_handle, exporting_device_handle,
> +									ip_type, src_heap, dst_heap);
> +	else
> +		amdgpu_cp_dma_misc(device_handle, ip_type, src_heap, dst_heap);
> +
> +	return r;
> +}
> +
> diff --git a/lib/amdgpu/amd_cp_dma.h b/lib/amdgpu/amd_cp_dma.h
> new file mode 100644
> index 000000000..3d7826d6c
> --- /dev/null
> +++ b/lib/amdgpu/amd_cp_dma.h
> @@ -0,0 +1,41 @@
> +/* SPDX-License-Identifier: MIT
> + * Copyright 2022 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> +*/
> +
> +#ifndef __AMD_CP_DMA_H__
> +#define __AMD_CP_DMA_H__
> +
> +int
> +amdgpu_cp_dma_generic(amdgpu_device_handle device_handle,
> +			amdgpu_device_handle exporting_device_handle, unsigned ip_type,
> +			uint32_t src_heap, uint32_t dst_heap);
> +
> +bool
> +amdgpu_cp_dma_misc_is_supported(const struct amdgpu_gpu_info *gpu_info);
> +
> +bool
> +amdgpu_cp_dma_misc_p2p_is_supported(const struct amdgpu_gpu_info *gpu_info);
> +
> +bool
> +asic_is_gfx_pipe_removed(const struct amdgpu_gpu_info *gpu_info);
> +
> +#endif
> diff --git a/lib/meson.build b/lib/meson.build
> index c79e3e952..cc7846869 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -138,7 +138,8 @@ if libdrm_amdgpu.found()
>  		'amdgpu/amd_dispatch.c',
>  		'amdgpu/amd_deadlock_helpers.c',
>  		'amdgpu/amd_pci_unplug.c',
> -		'amdgpu/xalloc.h'
> +		'amdgpu/xalloc.h',
> +		'amdgpu/amd_cp_dma.c'
>  	]
>  endif
>  
> -- 
> 2.25.1
> 

Re: [igt-dev] [PATCH 2/4] lib/amdgpu: move function to another file

[vitaly prosyak]

Hi Kamil,

Thanks for the review!

I believe all your suggestions are addressed : 
https://patchwork.freedesktop.org/series/112465/

All 4 patches validated with  ./scripts/checkpatch.pl

Thanks, Vitaly

On 2023-01-05 11:24, Kamil Konieczny wrote:
> Hi Vitaly,
>
> On 2023-01-04 at 19:53:18 -0500, vitaly.prosyak@amd.com wrote:
>> From: Vitaly Prosyak <vitaly.prosyak@amd.com>
>>
>> No functional change just cosmetic.
> Please do not mix in adding some debug printing with code moving.
>
>> Move function amdgpu_open_devices to the shared file
>> since other tests will also use it.
>>
>> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
>> ---
>>   lib/amdgpu/amd_ip_blocks.c  | 94 ++++++++++++++++++++++++++++++++++---
>>   lib/amdgpu/amd_ip_blocks.h  |  5 ++
>>   lib/amdgpu/amd_pci_unplug.c | 69 ---------------------------
>>   lib/amdgpu/amd_pci_unplug.h |  3 +-
>>   4 files changed, 93 insertions(+), 78 deletions(-)
>>
>> diff --git a/lib/amdgpu/amd_ip_blocks.c b/lib/amdgpu/amd_ip_blocks.c
>> index 3331c40bd..ce1bddffc 100644
>> --- a/lib/amdgpu/amd_ip_blocks.c
>> +++ b/lib/amdgpu/amd_ip_blocks.c
>> @@ -22,6 +22,8 @@
>>    *
>>    *
>>    */
>> +#include <fcntl.h>
>> +
>>   #include "amd_memory.h"
>>   #include "amd_ip_blocks.h"
>>   #include "amd_PM4.h"
>> @@ -616,21 +618,30 @@ int setup_amdgpu_ip_blocks(uint32_t major, uint32_t minor, struct amdgpu_gpu_inf
>>   		igt_info("amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
>>   			 amdinfo->family_id, amdinfo->chip_external_rev);
>>   		return -1;
>> +	} else {
>> +		igt_info("amdgpu: %s (family_id, chip_external_rev): (%u, %u)\n",
>> +				info->name, amdinfo->family_id, amdinfo->chip_external_rev);
>>   	}
>>   
>> -	if (info->family >= CHIP_SIENNA_CICHLID)
>> +	if (info->family >= CHIP_SIENNA_CICHLID) {
>>   		info->chip_class = GFX10_3;
>> -	else if (info->family >= CHIP_NAVI10)
>> +		igt_info("amdgpu: chip_class GFX10_3\n");
> --------------- ^
> Do you really want that at every function use ? Maybe better
> to use igt_debug and have separate function for printing ?
>
>> +	} else if (info->family >= CHIP_NAVI10) {
>>   		info->chip_class = GFX10;
>> -	else if (info->family >= CHIP_VEGA10)
>> +		igt_info("amdgpu: chip_class GFX10\n");
>> +	} else if (info->family >= CHIP_VEGA10) {
>>   		info->chip_class = GFX9;
>> -	else if (info->family >= CHIP_TONGA)
>> +		igt_info("amdgpu: chip_class GFX9\n");
>> +	} else if (info->family >= CHIP_TONGA) {
>>   		info->chip_class = GFX8;
>> -	else if (info->family >= CHIP_BONAIRE)
>> +		igt_info("amdgpu: chip_class GFX8\n");
>> +	} else if (info->family >= CHIP_BONAIRE) {
>>   		info->chip_class = GFX7;
>> -	else if (info->family >= CHIP_TAHITI)
>> +		igt_info("amdgpu: chip_class GFX7\n");
>> +	} else if (info->family >= CHIP_TAHITI) {
>>   		info->chip_class = GFX6;
>> -	else {
>> +		igt_info("amdgpu: chip_class GFX6\n");
>> +	} else {
>>   		igt_info("amdgpu: Unknown family.\n");
> Here you can print detailed info.
>
>>   		return -1;
>>   	}
>> @@ -663,3 +674,72 @@ int setup_amdgpu_ip_blocks(uint32_t major, uint32_t minor, struct amdgpu_gpu_inf
>>   
>>   	return 0;
>>   }
>> +
> Please write description of each new library function.
>
>> +int
>> +amdgpu_open_devices(bool open_render_node, int  max_cards_supported, int drm_amdgpu_fds[])
>> +{
>> +	drmDevicePtr devices[MAX_CARDS_SUPPORTED];
>> +	int i;
>> +	int drm_node;
>> +	int amd_index = 0;
>> +	int drm_count;
>> +	int fd;
>> +	drmVersionPtr version;
>> +
>> +	for (i = 0; i < max_cards_supported && i < MAX_CARDS_SUPPORTED; i++)
>> +		drm_amdgpu_fds[i] = -1;
>> +
>> +	drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED);
>> +
>> +	if (drm_count < 0) {
>> +		fprintf(stderr, "drmGetDevices2() returned an error %d\n", drm_count);
> --------------- ^
> We have igt_info() and igt_debug() messages, please use them.
>
>> +		return 0;
>> +	}
>> +
>> +	for (i = 0; i < drm_count; i++) {
>> +		/* If this is not PCI device, skip*/
>> +		if (devices[i]->bustype != DRM_BUS_PCI)
>> +			continue;
>> +
>> +		/* If this is not AMD GPU vender ID, skip*/
>> +		if (devices[i]->deviceinfo.pci->vendor_id != 0x1002)
>> +			continue;
>> +
>> +		if (open_render_node)
>> +			drm_node = DRM_NODE_RENDER;
>> +		else
>> +			drm_node = DRM_NODE_PRIMARY;
>> +
>> +		fd = -1;
>> +		if (devices[i]->available_nodes & 1 << drm_node)
>> +			fd = open(
>> +				devices[i]->nodes[drm_node],
>> +				O_RDWR | O_CLOEXEC);
>> +
>> +		/* This node is not available. */
>> +		if (fd < 0) continue;
> --------------------------- ^
> This should be at line below.
>
>> +
>> +		version = drmGetVersion(fd);
>> +		if (!version) {
>> +			fprintf(stderr, "Warning: Cannot get version for %s." "Error is %s\n",
> ---------------------------------------------------------------------------- ^^
> Did you mean putting this at line below ?
>
> Please use checkpatch script from linux kernel before sending
> patches, it can find some problems with formatting and spelling.
>
> If that was in original code then mention that corrections in
> patch message.
>
>> +				devices[i]->nodes[drm_node], strerror(errno));
>> +			close(fd);
>> +			continue;
>> +		}
>> +
>> +		if (strcmp(version->name, "amdgpu")) {
>> +			/* This is not AMDGPU driver, skip.*/
>> +			drmFreeVersion(version);
>> +			close(fd);
>> +			continue;
>> +		}
>> +
>> +		drmFreeVersion(version);
>> +
>> +		drm_amdgpu_fds[amd_index] = fd;
>> +		amd_index++;
>> +	}
>> +
>> +	drmFreeDevices(devices, drm_count);
>> +	return amd_index;
>> +}
>> diff --git a/lib/amdgpu/amd_ip_blocks.h b/lib/amdgpu/amd_ip_blocks.h
>> index 908aacde0..b3620c00f 100644
>> --- a/lib/amdgpu/amd_ip_blocks.h
>> +++ b/lib/amdgpu/amd_ip_blocks.h
>> @@ -27,6 +27,8 @@
>>   
>>   #include "amd_registers.h"
>>   
>> +#define MAX_CARDS_SUPPORTED 4
>> +
>>   enum amd_ip_block_type {
>>   	AMD_IP_GFX,
>>   	AMD_IP_COMPUTE,
>> @@ -136,4 +138,7 @@ struct amdgpu_cmd_base* get_cmd_base(void);
>>   
>>   void free_cmd_base(struct amdgpu_cmd_base *base);
>>   
>> +int
>> +amdgpu_open_devices(bool open_render_node, int  max_cards_supported, int drm_amdgpu_fds[]);
> ------------------------------------------------ ^^
> Two spaces, one is enough.
>
> Regards,
> Kamil
>
>> +
>>   #endif
>> diff --git a/lib/amdgpu/amd_pci_unplug.c b/lib/amdgpu/amd_pci_unplug.c
>> index 28b3ae393..078398b5e 100644
>> --- a/lib/amdgpu/amd_pci_unplug.c
>> +++ b/lib/amdgpu/amd_pci_unplug.c
>> @@ -21,7 +21,6 @@
>>    *
>>   */
>>   #include <linux/limits.h>
>> -#include <sys/types.h>
>>   #include <fcntl.h>
>>   #include <sys/stat.h>
>>   #include <pthread.h>
>> @@ -35,74 +34,6 @@
>>   #include "xalloc.h"
>>   #include "amd_ip_blocks.h"
>>   
>> -static int
>> -amdgpu_open_devices(bool open_render_node, int  max_cards_supported, int drm_amdgpu_fds[])
>> -{
>> -	drmDevicePtr devices[MAX_CARDS_SUPPORTED];
>> -	int i;
>> -	int drm_node;
>> -	int amd_index = 0;
>> -	int drm_count;
>> -	int fd;
>> -	drmVersionPtr version;
>> -
>> -	for (i = 0; i < max_cards_supported && i < MAX_CARDS_SUPPORTED; i++)
>> -		drm_amdgpu_fds[i] = -1;
>> -
>> -	drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED);
>> -
>> -	if (drm_count < 0) {
>> -		fprintf(stderr, "drmGetDevices2() returned an error %d\n", drm_count);
>> -		return 0;
>> -	}
>> -
>> -	for (i = 0; i < drm_count; i++) {
>> -		/* If this is not PCI device, skip*/
>> -		if (devices[i]->bustype != DRM_BUS_PCI)
>> -			continue;
>> -
>> -		/* If this is not AMD GPU vender ID, skip*/
>> -		if (devices[i]->deviceinfo.pci->vendor_id != 0x1002)
>> -			continue;
>> -
>> -		if (open_render_node)
>> -			drm_node = DRM_NODE_RENDER;
>> -		else
>> -			drm_node = DRM_NODE_PRIMARY;
>> -
>> -		fd = -1;
>> -		if (devices[i]->available_nodes & 1 << drm_node)
>> -			fd = open(
>> -				devices[i]->nodes[drm_node],
>> -				O_RDWR | O_CLOEXEC);
>> -
>> -		/* This node is not available. */
>> -		if (fd < 0) continue;
>> -
>> -		version = drmGetVersion(fd);
>> -		if (!version) {
>> -			fprintf(stderr, "Warning: Cannot get version for %s." "Error is %s\n",
>> -				devices[i]->nodes[drm_node], strerror(errno));
>> -			close(fd);
>> -			continue;
>> -		}
>> -
>> -		if (strcmp(version->name, "amdgpu")) {
>> -			/* This is not AMDGPU driver, skip.*/
>> -			drmFreeVersion(version);
>> -			close(fd);
>> -			continue;
>> -		}
>> -
>> -		drmFreeVersion(version);
>> -
>> -		drm_amdgpu_fds[amd_index] = fd;
>> -		amd_index++;
>> -	}
>> -
>> -	drmFreeDevices(devices, drm_count);
>> -	return amd_index;
>> -}
>>   static bool
>>   amdgpu_node_is_drm(int maj, int min)
>>   {
>> diff --git a/lib/amdgpu/amd_pci_unplug.h b/lib/amdgpu/amd_pci_unplug.h
>> index 509b6ec4c..35d4dce3a 100644
>> --- a/lib/amdgpu/amd_pci_unplug.h
>> +++ b/lib/amdgpu/amd_pci_unplug.h
>> @@ -26,8 +26,7 @@
>>   
>>   #include <amdgpu.h>
>>   #include <amdgpu_drm.h>
>> -
>> -#define MAX_CARDS_SUPPORTED 4
>> +#include "amd_ip_blocks.h"
>>   
>>   struct amd_pci_unplug_setup {
>>   	uint32_t  major_version_req;
>> -- 
>> 2.25.1
>>

[igt-dev] [PATCH 1/4] lib/amdgpu: rename function parameter

[vitaly.prosyak]

From: Vitaly Prosyak <vitaly.prosyak@amd.com>

No functional change just cosmetic.
Rename flags parameter to alloc_flags to avoid ambiguity
with mapping flags.

Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
 lib/amdgpu/amd_memory.c | 4 ++--
 lib/amdgpu/amd_memory.h | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/amdgpu/amd_memory.c b/lib/amdgpu/amd_memory.c
index 0aa400ac8..208e20eb8 100644
--- a/lib/amdgpu/amd_memory.c
+++ b/lib/amdgpu/amd_memory.c
@@ -41,7 +41,7 @@
 				      uint64_t size,
 				      uint64_t alignment,
 				      uint32_t type,
-				      uint64_t flags,
+				      uint64_t alloc_flags,
 				      uint64_t *vmc_addr,
 				      amdgpu_va_handle *va_handle)
 {
@@ -49,7 +49,7 @@
 		.alloc_size = size,
 		.phys_alignment = alignment,
 		.preferred_heap = type,
-		.flags = flags,
+		.flags = alloc_flags,
 	};
 	amdgpu_bo_handle buf_handle;
 	int r;
diff --git a/lib/amdgpu/amd_memory.h b/lib/amdgpu/amd_memory.h
index 77fd099b0..a06f88923 100644
--- a/lib/amdgpu/amd_memory.h
+++ b/lib/amdgpu/amd_memory.h
@@ -35,7 +35,7 @@ gpu_mem_alloc(amdgpu_device_handle device_handle,
 				      uint64_t size,
 				      uint64_t alignment,
 				      uint32_t type,
-				      uint64_t flags,
+				      uint64_t alloc_flags,
 				      uint64_t *vmc_addr,
 				      amdgpu_va_handle *va_handle);
 int
-- 
2.25.1