* [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid
@ 2023-01-09 15:26 Bin Meng
2023-01-09 15:47 ` Philippe Mathieu-Daudé
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Bin Meng @ 2023-01-09 15:26 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
env->mhartid is currently casted to long before printed, which drops
the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
target/riscv/cpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cc75ca7667..a5ed6d3f63 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -660,9 +660,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
(env->priv_ver < isa_edata_arr[i].min_version)) {
isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
#ifndef CONFIG_USER_ONLY
- warn_report("disabling %s extension for hart 0x%lx because "
- "privilege spec version does not match",
- isa_edata_arr[i].name, (unsigned long)env->mhartid);
+ warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
+ " because privilege spec version does not match",
+ isa_edata_arr[i].name, env->mhartid);
#else
warn_report("disabling %s extension because "
"privilege spec version does not match",
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid
2023-01-09 15:26 [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid Bin Meng
@ 2023-01-09 15:47 ` Philippe Mathieu-Daudé
2023-01-09 15:53 ` Bin Meng
2023-01-09 16:04 ` Richard Henderson
2023-01-16 3:14 ` Alistair Francis
2023-01-16 3:46 ` Alistair Francis
2 siblings, 2 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-01-09 15:47 UTC (permalink / raw)
To: Bin Meng, Alistair Francis, qemu-devel, qemu-riscv
Cc: Thomas Huth, Alex Bennée
On 9/1/23 16:26, Bin Meng wrote:
> env->mhartid is currently casted to long before printed, which drops
> the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead.
Oh, a 32-bit host user!
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
> target/riscv/cpu.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cc75ca7667..a5ed6d3f63 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -660,9 +660,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> (env->priv_ver < isa_edata_arr[i].min_version)) {
> isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
> #ifndef CONFIG_USER_ONLY
> - warn_report("disabling %s extension for hart 0x%lx because "
> - "privilege spec version does not match",
> - isa_edata_arr[i].name, (unsigned long)env->mhartid);
> + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
> + " because privilege spec version does not match",
> + isa_edata_arr[i].name, env->mhartid);
Could we cast it to vaddr instead? I'm trying to remove target_[u]long
from hw/ and restrict it to the target/ directory. Per "exec/cpu-common.h":
/**
* vaddr:
* Type wide enough to contain any #target_ulong virtual address.
*/
typedef uint64_t vaddr;
Alternatively, since this value has to be accessed out of target/,
can we change its type to vaddr in CPURISCVState?
Thanks,
Phil.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid
2023-01-09 15:47 ` Philippe Mathieu-Daudé
@ 2023-01-09 15:53 ` Bin Meng
2023-01-09 16:04 ` Richard Henderson
1 sibling, 0 replies; 6+ messages in thread
From: Bin Meng @ 2023-01-09 15:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Bin Meng, Alistair Francis, qemu-devel, qemu-riscv, Thomas Huth,
Alex Bennée
On Mon, Jan 9, 2023 at 11:48 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> On 9/1/23 16:26, Bin Meng wrote:
> > env->mhartid is currently casted to long before printed, which drops
> > the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead.
>
> Oh, a 32-bit host user!
>
> > Signed-off-by: Bin Meng <bmeng@tinylab.org>
> > ---
> >
> > target/riscv/cpu.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index cc75ca7667..a5ed6d3f63 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -660,9 +660,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> > (env->priv_ver < isa_edata_arr[i].min_version)) {
> > isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
> > #ifndef CONFIG_USER_ONLY
> > - warn_report("disabling %s extension for hart 0x%lx because "
> > - "privilege spec version does not match",
> > - isa_edata_arr[i].name, (unsigned long)env->mhartid);
> > + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
> > + " because privilege spec version does not match",
> > + isa_edata_arr[i].name, env->mhartid);
>
> Could we cast it to vaddr instead? I'm trying to remove target_[u]long
> from hw/ and restrict it to the target/ directory. Per "exec/cpu-common.h":
>
> /**
> * vaddr:
> * Type wide enough to contain any #target_ulong virtual address.
> */
> typedef uint64_t vaddr;
>
> Alternatively, since this value has to be accessed out of target/,
> can we change its type to vaddr in CPURISCVState?
>
Technically it does not represent a virtual address but a target
dependent register that can be 32-bit or 64-bit. Change env->mhartid
to vaddr looks weird to me.
Regards,
Bin
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid
2023-01-09 15:47 ` Philippe Mathieu-Daudé
2023-01-09 15:53 ` Bin Meng
@ 2023-01-09 16:04 ` Richard Henderson
1 sibling, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2023-01-09 16:04 UTC (permalink / raw)
To: Philippe Mathieu-Daudé,
Bin Meng, Alistair Francis, qemu-devel, qemu-riscv
Cc: Thomas Huth, Alex Bennée
On 1/9/23 07:47, Philippe Mathieu-Daudé wrote:
> On 9/1/23 16:26, Bin Meng wrote:
>> env->mhartid is currently casted to long before printed, which drops
>> the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead.
>
> Oh, a 32-bit host user!
>
>> Signed-off-by: Bin Meng <bmeng@tinylab.org>
>> ---
>>
>> target/riscv/cpu.c | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index cc75ca7667..a5ed6d3f63 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -660,9 +660,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> (env->priv_ver < isa_edata_arr[i].min_version)) {
>> isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
>> #ifndef CONFIG_USER_ONLY
>> - warn_report("disabling %s extension for hart 0x%lx because "
>> - "privilege spec version does not match",
>> - isa_edata_arr[i].name, (unsigned long)env->mhartid);
>> + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
>> + " because privilege spec version does not match",
>> + isa_edata_arr[i].name, env->mhartid);
>
> Could we cast it to vaddr instead? I'm trying to remove target_[u]long
> from hw/ and restrict it to the target/ directory. Per "exec/cpu-common.h":
This isn't in hw/, it's in target/. And no, it's a target-width register.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid
2023-01-09 15:26 [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid Bin Meng
2023-01-09 15:47 ` Philippe Mathieu-Daudé
@ 2023-01-16 3:14 ` Alistair Francis
2023-01-16 3:46 ` Alistair Francis
2 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2023-01-16 3:14 UTC (permalink / raw)
To: Bin Meng; +Cc: Alistair Francis, qemu-devel, qemu-riscv
On Tue, Jan 10, 2023 at 1:28 AM Bin Meng <bmeng@tinylab.org> wrote:
>
> env->mhartid is currently casted to long before printed, which drops
> the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> target/riscv/cpu.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cc75ca7667..a5ed6d3f63 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -660,9 +660,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> (env->priv_ver < isa_edata_arr[i].min_version)) {
> isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
> #ifndef CONFIG_USER_ONLY
> - warn_report("disabling %s extension for hart 0x%lx because "
> - "privilege spec version does not match",
> - isa_edata_arr[i].name, (unsigned long)env->mhartid);
> + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
> + " because privilege spec version does not match",
> + isa_edata_arr[i].name, env->mhartid);
> #else
> warn_report("disabling %s extension because "
> "privilege spec version does not match",
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid
2023-01-09 15:26 [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid Bin Meng
2023-01-09 15:47 ` Philippe Mathieu-Daudé
2023-01-16 3:14 ` Alistair Francis
@ 2023-01-16 3:46 ` Alistair Francis
2 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2023-01-16 3:46 UTC (permalink / raw)
To: Bin Meng; +Cc: Alistair Francis, qemu-devel, qemu-riscv
On Tue, Jan 10, 2023 at 1:28 AM Bin Meng <bmeng@tinylab.org> wrote:
>
> env->mhartid is currently casted to long before printed, which drops
> the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
>
> target/riscv/cpu.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index cc75ca7667..a5ed6d3f63 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -660,9 +660,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> (env->priv_ver < isa_edata_arr[i].min_version)) {
> isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
> #ifndef CONFIG_USER_ONLY
> - warn_report("disabling %s extension for hart 0x%lx because "
> - "privilege spec version does not match",
> - isa_edata_arr[i].name, (unsigned long)env->mhartid);
> + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
> + " because privilege spec version does not match",
> + isa_edata_arr[i].name, env->mhartid);
> #else
> warn_report("disabling %s extension because "
> "privilege spec version does not match",
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-01-16 3:48 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-09 15:26 [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid Bin Meng
2023-01-09 15:47 ` Philippe Mathieu-Daudé
2023-01-09 15:53 ` Bin Meng
2023-01-09 16:04 ` Richard Henderson
2023-01-16 3:14 ` Alistair Francis
2023-01-16 3:46 ` Alistair Francis
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.