* [igt-dev] [PATCH i-g-t v2 0/6] Introduce blt_cmd_info struct
@ 2022-12-23 11:13 Karolina Stolarek
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 1/6] i915/lib: Add new library for blitter and tiling formats Karolina Stolarek
` (7 more replies)
0 siblings, 8 replies; 21+ messages in thread
From: Karolina Stolarek @ 2022-12-23 11:13 UTC (permalink / raw)
To: igt-dev
This patch series introduces a new way of checking if a specific
tiling format and/or blitter copy command is supported on
the current platform. Instead of using functions with hardcoded
devices, now we store information about available features in
blt_cmd_info struct, each of the instances connected to the
intel_device_info definitions.
Two patches that follow the introduction of blt_cmd_info and
intel_device_info modification are a prep work for the fast
copy test -- extracting needed functions and updating
fill_data() to support TileYF (available only for Pre-gen12).
In addition to this, the patchset adds two fast copy tests: basic
fast-copy where two blit copies are done in separate batches and
fast-copy-emit which uses emit_blt_fast_copy() and manually
crafts two copies in one batch.
v2 of this series is significantly different from v1, especially
when it comes to intel_blt_info (formerly blt_tiling) library
implementation. It has been slimed down, and the API it exposes
now only deals with blt_cmd_info, not i915. So, for example, if
one wishes to query for support for fast copy for i915, they
should use blt_has_fast_copy(i915), exposed by i915_blt library.
The full list of changes can be found below.
v2:
- Add documentation
- Rename blt_tiling to intel_blt_info to better capture the
nature of the library (Zbigniew)
- Rename "can" predicates for blitter commands to use "has"
(Kamil)
- Add a fast copy test with two copies in the same batch buffer
- Add blt_ prefixes to functions extracted from gem_ccs to
avoid name clash (Zbigniew/Kamil)
- Also move set_object_ext() out from gem_ccs so it can be
shared with other tests
- Significantly rewrite intel_blt_info library -- now it only
exposes blt_cmd_supports_tiling and blt_supports_command
and blt_cmd_info definitions that can be used by other
blitter libraries like i915_blt.
- Split introduction of intel_blt_info and usage of the struct
into two commits
- Add functions checking fast and block copy support to
i915_blt library
- Add reference to blt_cmd_info to intel_device_info definitions
(Zbigniew)
- Update commit messages (Kamil)
Karolina Stolarek (6):
i915/lib: Add new library for blitter and tiling formats
lib: Update platform definitions with blitter information
lib/i915_blt: Check for Tile-YF in fast_copy
lib/i915_blt: Add common functions for blt_copy_object
tests/gem_exercise_blt: Add fast-copy test
tests/gem_exercise_blt: Add fast-copy-emit test
.../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
lib/i915/i915_blt.c | 192 +++++++--
lib/i915/i915_blt.h | 48 ++-
lib/i915/intel_blt_info.c | 241 +++++++++++
lib/i915/intel_blt_info.h | 98 +++++
lib/intel_chipset.c | 1 -
lib/intel_chipset.h | 4 +
lib/intel_device_info.c | 47 +++
lib/meson.build | 1 +
tests/i915/gem_ccs.c | 211 +++-------
tests/i915/gem_exercise_blt.c | 394 ++++++++++++++++++
tests/i915/gem_lmem_swapping.c | 81 +---
tests/meson.build | 1 +
13 files changed, 1055 insertions(+), 265 deletions(-)
create mode 100644 lib/i915/intel_blt_info.c
create mode 100644 lib/i915/intel_blt_info.h
create mode 100644 tests/i915/gem_exercise_blt.c
--
2.25.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH i-g-t v2 1/6] i915/lib: Add new library for blitter and tiling formats
2022-12-23 11:13 [igt-dev] [PATCH i-g-t v2 0/6] Introduce blt_cmd_info struct Karolina Stolarek
@ 2022-12-23 11:13 ` Karolina Stolarek
2023-01-09 12:49 ` Zbigniew Kempczyński
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 2/6] lib: Update platform definitions with blitter information Karolina Stolarek
` (6 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Karolina Stolarek @ 2022-12-23 11:13 UTC (permalink / raw)
To: igt-dev
Add structs to describe what blitter commands and tiling formats
are supported per platform. Add a generic functions that check
if a specific blitter command or tiling format is supported.
Move blt_tiling enum to the newely created library and update
its definition. Update i915_blt and block copy tests to reflect
that change.
Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
.../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
lib/i915/i915_blt.c | 31 +--
lib/i915/i915_blt.h | 14 +-
lib/i915/intel_blt_info.c | 241 ++++++++++++++++++
lib/i915/intel_blt_info.h | 98 +++++++
lib/meson.build | 1 +
tests/i915/gem_ccs.c | 15 +-
tests/i915/gem_lmem_swapping.c | 2 +-
8 files changed, 360 insertions(+), 43 deletions(-)
create mode 100644 lib/i915/intel_blt_info.c
create mode 100644 lib/i915/intel_blt_info.h
diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
index 102c8a89..24ee17fc 100644
--- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
+++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
@@ -59,6 +59,7 @@
</chapter>
<chapter>
<title>igt/i915 API Reference</title>
+ <xi:include href="xml/intel_blt_info.xml"/>
<xi:include href="xml/gem_create.xml"/>
<xi:include href="xml/gem_context.xml"/>
<xi:include href="xml/gem_engine_topology.xml"/>
diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
index 54193565..6db135d1 100644
--- a/lib/i915/i915_blt.c
+++ b/lib/i915/i915_blt.c
@@ -217,7 +217,7 @@ bool blt_supports_compression(int i915)
* Returns:
* true if it does, false otherwise.
*/
-bool blt_supports_tiling(int i915, enum blt_tiling tiling)
+bool blt_supports_tiling(int i915, enum blt_tiling_type tiling)
{
uint32_t devid = intel_get_drm_devid(i915);
@@ -238,28 +238,7 @@ bool blt_supports_tiling(int i915, enum blt_tiling tiling)
return true;
}
-/**
- * blt_tiling_name:
- * @tiling: tiling id
- *
- * Returns:
- * name of @tiling passed. Useful to build test names.
- */
-const char *blt_tiling_name(enum blt_tiling tiling)
-{
- switch (tiling) {
- case T_LINEAR: return "linear";
- case T_XMAJOR: return "xmajor";
- case T_YMAJOR: return "ymajor";
- case T_TILE4: return "tile4";
- case T_TILE64: return "tile64";
- }
-
- igt_warn("invalid tiling passed: %d\n", tiling);
- return NULL;
-}
-
-static int __block_tiling(enum blt_tiling tiling)
+static int __block_tiling(enum blt_tiling_type tiling)
{
switch (tiling) {
case T_LINEAR: return 0;
@@ -267,6 +246,9 @@ static int __block_tiling(enum blt_tiling tiling)
case T_YMAJOR: return 1;
case T_TILE4: return 2;
case T_TILE64: return 3;
+ /* type only supported in gen9 fast copy */
+ case T_YFMAJOR:
+ break;
}
igt_warn("invalid tiling passed: %d\n", tiling);
@@ -891,13 +873,14 @@ struct gen12_fast_copy_data {
} dw09;
};
-static int __fast_tiling(enum blt_tiling tiling)
+static int __fast_tiling(enum blt_tiling_type tiling)
{
switch (tiling) {
case T_LINEAR: return 0;
case T_XMAJOR: return 1;
case T_YMAJOR: return 2;
case T_TILE4: return 2;
+ case T_YFMAJOR: return 2;
case T_TILE64: return 3;
}
return 0;
diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
index 34db9bb9..8fa480b8 100644
--- a/lib/i915/i915_blt.h
+++ b/lib/i915/i915_blt.h
@@ -47,6 +47,7 @@
#include <malloc.h>
#include "drm.h"
#include "igt.h"
+#include "intel_blt_info.h"
#define CCS_RATIO 256
@@ -59,14 +60,6 @@ enum blt_color_depth {
CD_128bit,
};
-enum blt_tiling {
- T_LINEAR,
- T_XMAJOR,
- T_YMAJOR,
- T_TILE4,
- T_TILE64,
-};
-
enum blt_compression {
COMPRESSION_DISABLED,
COMPRESSION_ENABLED,
@@ -83,7 +76,7 @@ struct blt_copy_object {
uint32_t region;
uint64_t size;
uint8_t mocs;
- enum blt_tiling tiling;
+ enum blt_tiling_type tiling;
enum blt_compression compression; /* BC only */
enum blt_compression_type compression_type; /* BC only */
uint32_t pitch;
@@ -165,8 +158,7 @@ struct blt_ctrl_surf_copy_data {
};
bool blt_supports_compression(int i915);
-bool blt_supports_tiling(int i915, enum blt_tiling tiling);
-const char *blt_tiling_name(enum blt_tiling tiling);
+bool blt_supports_tiling(int i915, enum blt_tiling_type tiling);
uint64_t emit_blt_block_copy(int i915,
uint64_t ahnd,
diff --git a/lib/i915/intel_blt_info.c b/lib/i915/intel_blt_info.c
new file mode 100644
index 00000000..2f54d1b4
--- /dev/null
+++ b/lib/i915/intel_blt_info.c
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "intel_blt_info.h"
+
+#define BLT_STR_MAX 200
+#define TILE_STR_MAX 60
+#define T_MAX_SHIFT 6
+
+#define BLT_INFO(_cmd, _tiling) { \
+ .blt_cmd_type = _cmd, \
+ .supported_tiling = _tiling \
+ }
+
+static const struct blt_tiling_info src_copy = BLT_INFO(SRC_COPY, T_LINEAR);
+static const struct blt_tiling_info
+ pre_gen8_xy_src_copy = BLT_INFO(XY_SRC_COPY, T_LINEAR | T_XMAJOR);
+static const struct blt_tiling_info
+ gen8_xy_src_copy = BLT_INFO(XY_SRC_COPY,
+ T_LINEAR | T_XMAJOR | T_YMAJOR);
+static const struct blt_tiling_info
+ gen11_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
+ T_LINEAR | T_YMAJOR |
+ T_YFMAJOR | T_TILE64);
+static const struct blt_tiling_info
+ gen12_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
+ T_LINEAR | T_YMAJOR |
+ T_TILE4 | T_TILE64);
+static const struct blt_tiling_info
+ dg2_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
+ T_LINEAR | T_XMAJOR |
+ T_TILE4 | T_TILE64);
+static const struct blt_tiling_info
+ atsm_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
+ T_LINEAR | T_TILE4 |
+ T_TILE64);
+static const struct blt_tiling_info
+ gen12_xy_block_copy = BLT_INFO(XY_BLOCK_COPY,
+ T_LINEAR | T_YMAJOR);
+static const struct blt_tiling_info
+ dg2_xy_block_copy = BLT_INFO(XY_BLOCK_COPY,
+ T_LINEAR | T_XMAJOR |
+ T_TILE4 | T_TILE64);
+static const struct blt_tiling_info
+ atsm_xy_block_copy = BLT_INFO(XY_BLOCK_COPY,
+ T_LINEAR | T_XMAJOR |
+ T_TILE4 | T_TILE64);
+
+const struct blt_cmd_info pre_gen8_blt_info = {
+ .supported_tiling = {
+ [SRC_COPY] = &src_copy,
+ [XY_SRC_COPY] = &pre_gen8_xy_src_copy
+ }
+};
+
+const struct blt_cmd_info gen8_blt_info = {
+ .supported_tiling = {
+ [XY_SRC_COPY] = &gen8_xy_src_copy,
+ }
+};
+
+const struct blt_cmd_info gen11_blt_info = {
+ .supported_tiling = {
+ [XY_SRC_COPY] = &gen8_xy_src_copy,
+ [XY_FAST_COPY] = &gen11_xy_fast_copy,
+ }
+};
+
+const struct blt_cmd_info gen12_blt_info = {
+ .supported_tiling = {
+ [XY_SRC_COPY] = &gen8_xy_src_copy,
+ [XY_FAST_COPY] = &gen12_xy_fast_copy,
+ [XY_BLOCK_COPY] = &gen12_xy_block_copy,
+ }
+};
+
+const struct blt_cmd_info gen12_dg2_blt_info = {
+ .supported_tiling = {
+ [XY_SRC_COPY] = &gen8_xy_src_copy,
+ [XY_FAST_COPY] = &dg2_xy_fast_copy,
+ [XY_BLOCK_COPY] = &dg2_xy_block_copy,
+ }
+};
+
+const struct blt_cmd_info gen12_atsm_blt_info = {
+ .supported_tiling = {
+ [XY_SRC_COPY] = &gen8_xy_src_copy,
+ [XY_FAST_COPY] = &atsm_xy_fast_copy,
+ [XY_BLOCK_COPY] = &atsm_xy_block_copy,
+ }
+};
+
+/**
+ * blt_tiling_name:
+ * @tiling: tiling id
+ *
+ * Returns:
+ * name of @tiling passed. Useful to build test names.
+ */
+const char *blt_tiling_name(enum blt_tiling_type tiling)
+{
+ switch (tiling) {
+ case T_LINEAR: return "linear";
+ case T_XMAJOR: return "xmajor";
+ case T_YMAJOR: return "ymajor";
+ case T_TILE4: return "tile4";
+ case T_TILE64: return "tile64";
+ case T_YFMAJOR: return "yfmajor";
+ default: return NULL;
+ }
+}
+
+/**
+ * blt_supports_command:
+ * @info: Blitter command info struct
+ * @cmd: Blitter command enum
+ *
+ * Checks if @info has an entry of supported tiling formats for @cmd command.
+ *
+ * Returns: true if it does, false otherwise
+ */
+bool blt_supports_command(const struct blt_cmd_info *info,
+ enum blt_cmd_type cmd)
+{
+ igt_require_f(info, "No config found for the platform\n");
+
+ return info->supported_tiling[cmd];
+}
+
+/**
+ * blt_cmd_supports_tiling:
+ * @info: Blitter command info struct
+ * @cmd: Blitter command enum
+ * @tiling: tiling format enum
+ *
+ * Checks if a @cmd entry of @info lists @tiling. It also returns false if
+ * no information about the command is stored.
+ *
+ * Returns: true if it does, false otherwise
+ */
+bool blt_cmd_supports_tiling(const struct blt_cmd_info *info,
+ enum blt_cmd_type cmd,
+ enum blt_tiling_type tiling)
+{
+ struct blt_tiling_info const *tile_config;
+
+ if (!info)
+ return false;
+
+ tile_config = info->supported_tiling[cmd];
+
+ /* no config means no support for that tiling */
+ if (!tile_config)
+ return false;
+
+ return tile_config->supported_tiling & tiling;
+}
+
+static const char *blt_cmd_name(enum blt_cmd_type cmd)
+{
+ switch (cmd) {
+ case SRC_COPY: return "SRC_COPY_BLT";
+ case XY_SRC_COPY: return "XY_SRC_COPY_BLT";
+ case XY_FAST_COPY: return "XY_FAST_COPY_BLT";
+ case XY_BLOCK_COPY: return "XY_BLOCK_COPY_BLT";
+ default: return NULL;
+ }
+}
+
+/* Info dump functions */
+
+static void append_tile(uint32_t tile, char *tile_str)
+{
+ char const *tile_name;
+
+ if (tile) {
+ tile_name = blt_tiling_name(tile);
+ snprintf(tile_str + strlen(tile_str), strlen(tile_name) + 2, "%s ", tile_name);
+ }
+}
+
+static void get_tiling_info(struct blt_cmd_info const *info, enum blt_cmd_type type, char *tile_str)
+{
+ uint32_t mask;
+ struct blt_tiling_info const *tiling = info->supported_tiling[type];
+
+ if (tiling) {
+ for (int i = 0; i < T_MAX_SHIFT; i++) {
+ mask = 1 << i;
+ append_tile(tiling->supported_tiling & mask, tile_str);
+ }
+ }
+
+ tile_str[strlen(tile_str) - 1] = '\0';
+}
+
+/**
+ * dump_devid_blt_info:
+ * @info: pointer to the Blitter command info struct
+ *
+ * Prints a list of supported commands with available tiling formats.
+ *
+ */
+void blt_dump_blt_cmd_info(struct blt_cmd_info const *info)
+{
+ char tiling_str[TILE_STR_MAX];
+ char ln_str[BLT_STR_MAX];
+ char const *blt_type_str;
+ const char *ln_intro = " * ";
+
+ if (!info) {
+ igt_warn("No config available\n");
+ return;
+ }
+
+ igt_info("Supported blitter commands:\n");
+
+ for (int cmd = 0; cmd < __MAX_CMD; cmd++) {
+ if (info->supported_tiling[cmd]) {
+ memset(ln_str, '\0', sizeof(char) * BLT_STR_MAX);
+ memset(tiling_str, '\0', sizeof(char) * TILE_STR_MAX);
+
+ blt_type_str = blt_cmd_name(cmd);
+
+ snprintf(ln_str,
+ strlen(ln_intro) + strlen(blt_type_str) + 1,
+ "%s%s", ln_intro, blt_type_str);
+
+ get_tiling_info(info, cmd, tiling_str);
+
+ snprintf(ln_str + strlen(ln_str),
+ strlen(tiling_str) + 5,
+ " [%s]", tiling_str);
+
+ igt_info("%s\n", ln_str);
+ }
+ }
+}
+
diff --git a/lib/i915/intel_blt_info.h b/lib/i915/intel_blt_info.h
new file mode 100644
index 00000000..39fa5448
--- /dev/null
+++ b/lib/i915/intel_blt_info.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef BLT_TILING_H
+#define BLT_TILING_H
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "igt_core.h"
+
+/**
+ * SECTION:intel_blt_info
+ * @short_description: blitter library to query for available commands and tiling formats
+ * @title: Intel blitter info
+ * @include: intel_blt_info.h
+ *
+ * # Introduction
+ *
+ * When we do a blitter copy, a number of different tiling formats can be used.
+ * The list of available formats and commands varies between generations, in
+ * some cases even within the generation (e.g. block copy tiling formats offered
+ * by TGL vs DG2). Such information is required by different tests, so it's
+ * beneficial to store it in one place – in intel_blt_info, a blitter library
+ * that describes available commands with a list of supported tiling formats.
+ * They are encapsulated in static `blt_cmd_info` instances, each of them
+ * defined per generation or platforms.
+ *
+ * Tiling formats here are described by blt_tiling_type enum, which consists of
+ * bit flags, that can be combined:
+ * `.supported_tiling = T_LINEAR | T_XMAJOR | T_YMAJOR`
+ *
+ * Because of their non-linear nature, it is recommended to use
+ * #for_each_tiling() macro when writing tests that iterate over tiling formats.
+ *
+ * # Usage
+ *
+ * - blt_supports_command(info, cmd) - checks if a blt_cmd_type instance has an
+ * entry for the command
+ * - blt_cmd_supports_tiling(info, cmd, tiling) - checks if a tiling format is
+ * supported by the command. Can
+ * also handle the case when the
+ * command is not available on
+ * the platform.
+ *
+ * These general checks can be wrapped in a command or tiling specific
+ * check, provided by other libraries.
+ *
+ */
+
+enum blt_tiling_type {
+ T_LINEAR = (1),
+ T_XMAJOR = (1 << 1),
+ T_YMAJOR = (1 << 2),
+ T_TILE4 = (1 << 3),
+ T_TILE64 = (1 << 4),
+ T_YFMAJOR = (1 << 5),
+};
+
+enum blt_cmd_type {
+ SRC_COPY,
+ XY_SRC_COPY,
+ XY_FAST_COPY,
+ XY_BLOCK_COPY,
+ __MAX_CMD
+};
+
+struct blt_tiling_info {
+ enum blt_cmd_type blt_cmd_type;
+ uint32_t supported_tiling;
+};
+
+struct blt_cmd_info {
+ struct blt_tiling_info const *supported_tiling[__MAX_CMD];
+};
+
+const struct blt_cmd_info pre_gen8_blt_info;
+const struct blt_cmd_info gen8_blt_info;
+const struct blt_cmd_info gen11_blt_info;
+const struct blt_cmd_info gen12_blt_info;
+const struct blt_cmd_info gen12_dg2_blt_info;
+const struct blt_cmd_info gen12_atsm_blt_info;
+
+#define for_each_tiling(__tiling) \
+ for (__tiling = T_LINEAR; __tiling <= T_YFMAJOR; __tiling = __tiling << 1)
+
+bool blt_supports_command(const struct blt_cmd_info *info,
+ enum blt_cmd_type cmd);
+bool blt_cmd_supports_tiling(const struct blt_cmd_info *info,
+ enum blt_cmd_type cmd,
+ enum blt_tiling_type tiling);
+
+void blt_dump_blt_cmd_info(struct blt_cmd_info const *info);
+const char *blt_tiling_name(enum blt_tiling_type tiling);
+
+#endif // BLT_TILING_H
diff --git a/lib/meson.build b/lib/meson.build
index c79e3e95..2b2dbbca 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -11,6 +11,7 @@ lib_sources = [
'i915/gem_ring.c',
'i915/gem_mman.c',
'i915/gem_vm.c',
+ 'i915/intel_blt_info.c',
'i915/intel_decode.c',
'i915/intel_memory_region.c',
'i915/intel_mocs.c',
diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
index 751f65e6..ed60b81c 100644
--- a/tests/i915/gem_ccs.c
+++ b/tests/i915/gem_ccs.c
@@ -46,7 +46,7 @@ struct test_config {
static void set_object(struct blt_copy_object *obj,
uint32_t handle, uint64_t size, uint32_t region,
- uint8_t mocs, enum blt_tiling tiling,
+ uint8_t mocs, enum blt_tiling_type tiling,
enum blt_compression compression,
enum blt_compression_type compression_type)
{
@@ -108,7 +108,7 @@ static void set_surf_object(struct blt_ctrl_surf_copy_object *obj,
static struct blt_copy_object *
create_object(int i915, uint32_t region,
uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs,
- enum blt_tiling tiling,
+ enum blt_tiling_type tiling,
enum blt_compression compression,
enum blt_compression_type compression_type,
bool create_mapping)
@@ -374,7 +374,7 @@ static void block_copy(int i915,
const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e,
uint32_t region1, uint32_t region2,
- enum blt_tiling mid_tiling,
+ enum blt_tiling_type mid_tiling,
const struct test_config *config)
{
struct blt_copy_data blt = {};
@@ -492,7 +492,7 @@ static void block_multicopy(int i915,
const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e,
uint32_t region1, uint32_t region2,
- enum blt_tiling mid_tiling,
+ enum blt_tiling_type mid_tiling,
const struct test_config *config)
{
struct blt_copy3_data blt3 = {};
@@ -581,7 +581,7 @@ static const struct {
const char *suffix;
void (*copyfn)(int, const intel_ctx_t *,
const struct intel_execution_engine2 *,
- uint32_t, uint32_t, enum blt_tiling,
+ uint32_t, uint32_t, enum blt_tiling_type,
const struct test_config *);
} copyfns[] = {
[BLOCK_COPY] = { "", block_copy },
@@ -596,6 +596,7 @@ static void block_copy_test(int i915,
{
struct igt_collection *regions;
const struct intel_execution_engine2 *e;
+ int tiling;
if (config->compression && !blt_supports_compression(i915))
return;
@@ -603,7 +604,7 @@ static void block_copy_test(int i915,
if (config->inplace && !config->compression)
return;
- for (int tiling = T_LINEAR; tiling <= T_TILE64; tiling++) {
+ for_each_tiling(tiling) {
if (!blt_supports_tiling(i915, tiling) ||
(param.tiling >= 0 && param.tiling != tiling))
continue;
@@ -663,7 +664,7 @@ static int opt_handler(int opt, int opt_index, void *data)
igt_debug("Print surface info: %d\n", param.print_surface_info);
break;
case 't':
- param.tiling = atoi(optarg);
+ param.tiling = 1 << atoi(optarg);
igt_debug("Tiling: %d\n", param.tiling);
break;
case 'W':
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index 75121d41..9388d4de 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -78,7 +78,7 @@ struct object {
static void set_object(struct blt_copy_object *obj,
uint32_t handle, uint64_t size, uint32_t region,
- uint8_t mocs, enum blt_tiling tiling,
+ uint8_t mocs, enum blt_tiling_type tiling,
enum blt_compression compression,
enum blt_compression_type compression_type)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH i-g-t v2 2/6] lib: Update platform definitions with blitter information
2022-12-23 11:13 [igt-dev] [PATCH i-g-t v2 0/6] Introduce blt_cmd_info struct Karolina Stolarek
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 1/6] i915/lib: Add new library for blitter and tiling formats Karolina Stolarek
@ 2022-12-23 11:13 ` Karolina Stolarek
2022-12-28 16:41 ` Kamil Konieczny
2023-01-09 15:20 ` Zbigniew Kempczyński
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 3/6] lib/i915_blt: Check for Tile-YF in fast_copy Karolina Stolarek
` (5 subsequent siblings)
7 siblings, 2 replies; 21+ messages in thread
From: Karolina Stolarek @ 2022-12-23 11:13 UTC (permalink / raw)
To: igt-dev
Update entries in intel_device_info to store information on
supported blitter commands and tiling formats. Add predicates
that check if block or fast copy are supported. Update block
copy tests to use the new checks.
Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
lib/i915/i915_blt.c | 75 +++++++++++++++++++++++++++++++----------
lib/i915/i915_blt.h | 6 +++-
lib/intel_chipset.c | 1 -
lib/intel_chipset.h | 4 +++
lib/intel_device_info.c | 47 ++++++++++++++++++++++++++
tests/i915/gem_ccs.c | 4 +--
6 files changed, 115 insertions(+), 22 deletions(-)
diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
index 6db135d1..00cf7470 100644
--- a/lib/i915/i915_blt.c
+++ b/lib/i915/i915_blt.c
@@ -208,34 +208,73 @@ bool blt_supports_compression(int i915)
}
/**
- * blt_supports_tiling:
+ * blt_has_block_copy
* @i915: drm fd
- * @tiling: tiling id
*
- * Function checks if blitter supports @tiling on @i915 device.
+ * Check if block copy is supported by @i915 device
*
* Returns:
* true if it does, false otherwise.
*/
-bool blt_supports_tiling(int i915, enum blt_tiling_type tiling)
+bool blt_has_block_copy(int i915)
{
- uint32_t devid = intel_get_drm_devid(i915);
+ const struct blt_cmd_info
+ *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
- if (tiling == T_XMAJOR) {
- if (IS_TIGERLAKE(devid) || IS_DG1(devid))
- return false;
- else
- return true;
- }
+ return blt_supports_command(blt_info, XY_BLOCK_COPY);
+}
- if (tiling == T_YMAJOR) {
- if (IS_TIGERLAKE(devid) || IS_DG1(devid))
- return true;
- else
- return false;
- }
+/**
+ * blt_has_fast_copy
+ * @i915: drm fd
+ *
+ * Check if fast copy is supported by @i915 device
+ *
+ * Returns:
+ * true if it does, false otherwise.
+ */
+bool blt_has_fast_copy(int i915)
+{
+ const struct blt_cmd_info
+ *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
+
+ return blt_supports_command(blt_info, XY_FAST_COPY);
+}
+
+/**
+ * blt_fast_copy_supports_tiling
+ * @i915: drm fd
+ * @tiling: tiling format
+ *
+ * Check if fast copy provided by @i915 device supports @tiling format
+ *
+ * Returns:
+ * true if it does, false otherwise.
+ */
+bool blt_fast_copy_supports_tiling(int i915, enum blt_tiling_type tiling)
+{
+ const struct blt_cmd_info
+ *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
+
+ return blt_cmd_supports_tiling(blt_info, XY_FAST_COPY, tiling);
+}
+
+/**
+ * blt_block_copy_supports_tiling
+ * @i915: drm fd
+ * @tiling: tiling format
+ *
+ * Check if block copy provided by @i915 device supports @tiling format
+ *
+ * Returns:
+ * true if it does, false otherwise.
+ */
+bool blt_block_copy_supports_tiling(int i915, enum blt_tiling_type tiling)
+{
+ const struct blt_cmd_info
+ *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
- return true;
+ return blt_cmd_supports_tiling(blt_info, XY_BLOCK_COPY, tiling);
}
static int __block_tiling(enum blt_tiling_type tiling)
diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
index 8fa480b8..3730c7c0 100644
--- a/lib/i915/i915_blt.h
+++ b/lib/i915/i915_blt.h
@@ -158,7 +158,11 @@ struct blt_ctrl_surf_copy_data {
};
bool blt_supports_compression(int i915);
-bool blt_supports_tiling(int i915, enum blt_tiling_type tiling);
+
+bool blt_has_block_copy(int i915);
+bool blt_has_fast_copy(int i915);
+bool blt_fast_copy_supports_tiling(int i915, enum blt_tiling_type tiling);
+bool blt_block_copy_supports_tiling(int i915, enum blt_tiling_type tiling);
uint64_t emit_blt_block_copy(int i915,
uint64_t ahnd,
diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
index efb6f177..4ac067df 100644
--- a/lib/intel_chipset.c
+++ b/lib/intel_chipset.c
@@ -41,7 +41,6 @@
#include "drmtest.h"
#include "intel_chipset.h"
#include "igt_core.h"
-
/**
* SECTION:intel_chipset
* @short_description: Feature macros and chipset helpers
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 9b39472a..a9801b28 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -31,6 +31,8 @@
#include <pciaccess.h>
#include <stdbool.h>
+#include "i915/intel_blt_info.h"
+
#define BIT(x) (1ul <<(x))
struct pci_device *intel_get_pci_device(void);
@@ -86,11 +88,13 @@ struct intel_device_info {
bool is_alderlake_p : 1;
bool is_alderlake_n : 1;
bool is_meteorlake : 1;
+ const struct blt_cmd_info *blt_tiling;
const char *codename;
};
const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
+const struct blt_cmd_info *intel_get_blt_info(uint16_t devid) __attribute__((pure));
unsigned intel_gen(uint16_t devid) __attribute__((pure));
unsigned intel_graphics_ver(uint16_t devid) __attribute__((pure));
unsigned intel_display_ver(uint16_t devid) __attribute__((pure));
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 68dd17ee..ad9dffd8 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -145,6 +145,7 @@ static const struct intel_device_info intel_sandybridge_info = {
.graphics_ver = 6,
.display_ver = 6,
.is_sandybridge = true,
+ .blt_tiling = &pre_gen8_blt_info,
.codename = "sandybridge"
};
static const struct intel_device_info intel_sandybridge_m_info = {
@@ -152,6 +153,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
.display_ver = 6,
.is_mobile = true,
.is_sandybridge = true,
+ .blt_tiling = &pre_gen8_blt_info,
.codename = "sandybridge"
};
@@ -159,6 +161,7 @@ static const struct intel_device_info intel_ivybridge_info = {
.graphics_ver = 7,
.display_ver = 7,
.is_ivybridge = true,
+ .blt_tiling = &pre_gen8_blt_info,
.codename = "ivybridge"
};
static const struct intel_device_info intel_ivybridge_m_info = {
@@ -166,6 +169,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
.display_ver = 7,
.is_mobile = true,
.is_ivybridge = true,
+ .blt_tiling = &pre_gen8_blt_info,
.codename = "ivybridge"
};
@@ -173,6 +177,7 @@ static const struct intel_device_info intel_valleyview_info = {
.graphics_ver = 7,
.display_ver = 7,
.is_valleyview = true,
+ .blt_tiling = &pre_gen8_blt_info,
.codename = "valleyview"
};
@@ -180,6 +185,7 @@ static const struct intel_device_info intel_valleyview_info = {
.graphics_ver = 7, \
.display_ver = 7, \
.is_haswell = true, \
+ .blt_tiling = &pre_gen8_blt_info, \
.codename = "haswell"
static const struct intel_device_info intel_haswell_gt1_info = {
@@ -201,6 +207,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
.graphics_ver = 8, \
.display_ver = 8, \
.is_broadwell = true, \
+ .blt_tiling = &gen8_blt_info, \
.codename = "broadwell"
static const struct intel_device_info intel_broadwell_gt1_info = {
@@ -226,12 +233,14 @@ static const struct intel_device_info intel_cherryview_info = {
.graphics_ver = 8,
.display_ver = 8,
.is_cherryview = true,
+ .blt_tiling = &gen8_blt_info,
.codename = "cherryview"
};
#define SKYLAKE_FIELDS \
.graphics_ver = 9, \
.display_ver = 9, \
+ .blt_tiling = &gen11_blt_info, \
.codename = "skylake", \
.is_skylake = true
@@ -259,6 +268,7 @@ static const struct intel_device_info intel_broxton_info = {
.graphics_ver = 9,
.display_ver = 9,
.is_broxton = true,
+ .blt_tiling = &gen11_blt_info,
.codename = "broxton"
};
@@ -266,6 +276,7 @@ static const struct intel_device_info intel_broxton_info = {
.graphics_ver = 9, \
.display_ver = 9, \
.is_kabylake = true, \
+ .blt_tiling = &gen11_blt_info, \
.codename = "kabylake"
static const struct intel_device_info intel_kabylake_gt1_info = {
@@ -292,6 +303,7 @@ static const struct intel_device_info intel_geminilake_info = {
.graphics_ver = 9,
.display_ver = 9,
.is_geminilake = true,
+ .blt_tiling = &gen11_blt_info,
.codename = "geminilake"
};
@@ -299,6 +311,7 @@ static const struct intel_device_info intel_geminilake_info = {
.graphics_ver = 9, \
.display_ver = 9, \
.is_coffeelake = true, \
+ .blt_tiling = &gen11_blt_info, \
.codename = "coffeelake"
static const struct intel_device_info intel_coffeelake_gt1_info = {
@@ -320,6 +333,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
.graphics_ver = 9, \
.display_ver = 9, \
.is_cometlake = true, \
+ .blt_tiling = &gen11_blt_info, \
.codename = "cometlake"
static const struct intel_device_info intel_cometlake_gt1_info = {
@@ -336,6 +350,7 @@ static const struct intel_device_info intel_cannonlake_info = {
.graphics_ver = 10,
.display_ver = 10,
.is_cannonlake = true,
+ .blt_tiling = &gen11_blt_info,
.codename = "cannonlake"
};
@@ -343,6 +358,7 @@ static const struct intel_device_info intel_icelake_info = {
.graphics_ver = 11,
.display_ver = 11,
.is_icelake = true,
+ .blt_tiling = &gen11_blt_info,
.codename = "icelake"
};
@@ -350,6 +366,7 @@ static const struct intel_device_info intel_elkhartlake_info = {
.graphics_ver = 11,
.display_ver = 11,
.is_elkhartlake = true,
+ .blt_tiling = &gen11_blt_info,
.codename = "elkhartlake"
};
@@ -357,6 +374,7 @@ static const struct intel_device_info intel_jasperlake_info = {
.graphics_ver = 11,
.display_ver = 11,
.is_jasperlake = true,
+ .blt_tiling = &gen11_blt_info,
.codename = "jasperlake"
};
@@ -364,6 +382,7 @@ static const struct intel_device_info intel_tigerlake_gt1_info = {
.graphics_ver = 12,
.display_ver = 12,
.is_tigerlake = true,
+ .blt_tiling = &gen12_blt_info,
.codename = "tigerlake",
.gt = 1,
};
@@ -372,6 +391,7 @@ static const struct intel_device_info intel_tigerlake_gt2_info = {
.graphics_ver = 12,
.display_ver = 12,
.is_tigerlake = true,
+ .blt_tiling = &gen12_blt_info,
.codename = "tigerlake",
.gt = 2,
};
@@ -380,6 +400,7 @@ static const struct intel_device_info intel_rocketlake_info = {
.graphics_ver = 12,
.display_ver = 12,
.is_rocketlake = true,
+ .blt_tiling = &gen12_blt_info,
.codename = "rocketlake"
};
@@ -388,6 +409,7 @@ static const struct intel_device_info intel_dg1_info = {
.graphics_rel = 10,
.display_ver = 12,
.is_dg1 = true,
+ .blt_tiling = &gen12_blt_info,
.codename = "dg1"
};
@@ -398,6 +420,7 @@ static const struct intel_device_info intel_dg2_info = {
.has_4tile = true,
.is_dg2 = true,
.codename = "dg2",
+ .blt_tiling = &gen12_dg2_blt_info,
.has_flatccs = true,
};
@@ -405,6 +428,7 @@ static const struct intel_device_info intel_alderlake_s_info = {
.graphics_ver = 12,
.display_ver = 12,
.is_alderlake_s = true,
+ .blt_tiling = &gen12_blt_info,
.codename = "alderlake_s"
};
@@ -412,6 +436,7 @@ static const struct intel_device_info intel_raptorlake_s_info = {
.graphics_ver = 12,
.display_ver = 12,
.is_raptorlake_s = true,
+ .blt_tiling = &gen12_blt_info,
.codename = "raptorlake_s"
};
@@ -419,6 +444,7 @@ static const struct intel_device_info intel_alderlake_p_info = {
.graphics_ver = 12,
.display_ver = 13,
.is_alderlake_p = true,
+ .blt_tiling = &gen12_blt_info,
.codename = "alderlake_p"
};
@@ -426,6 +452,7 @@ static const struct intel_device_info intel_alderlake_n_info = {
.graphics_ver = 12,
.display_ver = 13,
.is_alderlake_n = true,
+ .blt_tiling = &gen12_blt_info,
.codename = "alderlake_n"
};
@@ -436,6 +463,7 @@ static const struct intel_device_info intel_ats_m_info = {
.is_dg2 = true,
.has_4tile = true,
.codename = "ats_m",
+ .blt_tiling = &gen12_atsm_blt_info,
.has_flatccs = true,
};
@@ -583,6 +611,25 @@ out:
return cache;
}
+/**
+ * intel_get_blt_info:
+ * @devid: pci device id
+ *
+ * Looks up the Blitter information about commands and tiling formats supported
+ * by the device.
+ *
+ * Returns:
+ * The associated blt_cmd_info, NULL if no such information is found
+ */
+const struct blt_cmd_info *intel_get_blt_info(uint16_t devid)
+{
+ const struct intel_device_info *dev_info;
+
+ dev_info = intel_get_device_info(devid);
+
+ return dev_info->blt_tiling;
+}
+
/**
* intel_gen:
* @devid: pci device id
diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
index ed60b81c..10327050 100644
--- a/tests/i915/gem_ccs.c
+++ b/tests/i915/gem_ccs.c
@@ -605,7 +605,7 @@ static void block_copy_test(int i915,
return;
for_each_tiling(tiling) {
- if (!blt_supports_tiling(i915, tiling) ||
+ if (!blt_block_copy_supports_tiling(i915, tiling) ||
(param.tiling >= 0 && param.tiling != tiling))
continue;
@@ -703,7 +703,7 @@ igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
igt_fixture {
i915 = drm_open_driver(DRIVER_INTEL);
igt_require_gem(i915);
- igt_require(AT_LEAST_GEN(intel_get_drm_devid(i915), 12) > 0);
+ igt_require(blt_has_block_copy(i915));
query_info = gem_get_query_memory_regions(i915);
igt_require(query_info);
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH i-g-t v2 3/6] lib/i915_blt: Check for Tile-YF in fast_copy
2022-12-23 11:13 [igt-dev] [PATCH i-g-t v2 0/6] Introduce blt_cmd_info struct Karolina Stolarek
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 1/6] i915/lib: Add new library for blitter and tiling formats Karolina Stolarek
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 2/6] lib: Update platform definitions with blitter information Karolina Stolarek
@ 2022-12-23 11:13 ` Karolina Stolarek
2023-01-09 15:27 ` Zbigniew Kempczyński
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 4/6] lib/i915_blt: Add common functions for blt_copy_object Karolina Stolarek
` (4 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Karolina Stolarek @ 2022-12-23 11:13 UTC (permalink / raw)
To: igt-dev
In older gens Tile4 is not available, we have Tile-YF instead. Check for
both tilings when setting up the fast_copy command.
Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
lib/i915/i915_blt.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
index 00cf7470..23ee2218 100644
--- a/lib/i915/i915_blt.c
+++ b/lib/i915/i915_blt.c
@@ -327,6 +327,11 @@ static enum blt_aux_mode __aux_mode(const struct blt_copy_object *obj)
return AM_AUX_NONE;
}
+static bool __new_tile_y_type(enum blt_tiling_type tiling)
+{
+ return tiling == T_TILE4 || tiling == T_YFMAJOR;
+}
+
static void fill_data(struct gen12_block_copy_data *data,
const struct blt_copy_data *blt,
uint64_t src_offset, uint64_t dst_offset,
@@ -1013,8 +1018,8 @@ uint64_t emit_blt_fast_copy(int i915,
data.dw01.color_depth = __fast_color_depth(blt->color_depth);
data.dw01.dst_memory = __memory_type(blt->dst.region);
data.dw01.src_memory = __memory_type(blt->src.region);
- data.dw01.dst_type_y = blt->dst.tiling == T_TILE4 ? 1 : 0;
- data.dw01.src_type_y = blt->src.tiling == T_TILE4 ? 1 : 0;
+ data.dw01.dst_type_y = __new_tile_y_type(blt->dst.tiling) ? 1 : 0;
+ data.dw01.src_type_y = __new_tile_y_type(blt->src.tiling) ? 1 : 0;
data.dw02.dst_x1 = blt->dst.x1;
data.dw02.dst_y1 = blt->dst.y1;
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH i-g-t v2 4/6] lib/i915_blt: Add common functions for blt_copy_object
2022-12-23 11:13 [igt-dev] [PATCH i-g-t v2 0/6] Introduce blt_cmd_info struct Karolina Stolarek
` (2 preceding siblings ...)
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 3/6] lib/i915_blt: Check for Tile-YF in fast_copy Karolina Stolarek
@ 2022-12-23 11:13 ` Karolina Stolarek
2023-01-09 15:29 ` Zbigniew Kempczyński
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 5/6] tests/gem_exercise_blt: Add fast-copy test Karolina Stolarek
` (3 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Karolina Stolarek @ 2022-12-23 11:13 UTC (permalink / raw)
To: igt-dev
gem_ccs and gem_lmem_swapping tests share a number of functions.
Extract them to i915_blt so they are accessible for both tests.
Delete local definitions. Add blt_* prefixes to avoid potential
name clash.
Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
lib/i915/i915_blt.c | 95 ++++++++++++++++
lib/i915/i915_blt.h | 30 ++++-
tests/i915/gem_ccs.c | 196 +++++++++------------------------
tests/i915/gem_lmem_swapping.c | 81 +++-----------
4 files changed, 191 insertions(+), 211 deletions(-)
diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
index 23ee2218..f0d148e4 100644
--- a/lib/i915/i915_blt.c
+++ b/lib/i915/i915_blt.c
@@ -1123,6 +1123,101 @@ int blt_fast_copy(int i915,
return ret;
}
+void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
+ int16_t x1, int16_t y1, int16_t x2, int16_t y2,
+ uint16_t x_offset, uint16_t y_offset)
+{
+ obj->pitch = pitch;
+ obj->x1 = x1;
+ obj->y1 = y1;
+ obj->x2 = x2;
+ obj->y2 = y2;
+ obj->x_offset = x_offset;
+ obj->y_offset = y_offset;
+}
+
+void blt_set_batch(struct blt_copy_batch *batch,
+ uint32_t handle, uint64_t size, uint32_t region)
+{
+ batch->handle = handle;
+ batch->size = size;
+ batch->region = region;
+}
+
+struct blt_copy_object *
+blt_create_object(int i915, uint32_t region,
+ uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs,
+ enum blt_tiling_type tiling,
+ enum blt_compression compression,
+ enum blt_compression_type compression_type,
+ bool create_mapping)
+{
+ struct blt_copy_object *obj;
+ uint64_t size = width * height * bpp / 8;
+ uint32_t stride = tiling == T_LINEAR ? width * 4 : width;
+ uint32_t handle;
+
+ obj = calloc(1, sizeof(*obj));
+
+ obj->size = size;
+ igt_assert(__gem_create_in_memory_regions(i915, &handle,
+ &size, region) == 0);
+
+ blt_set_object(obj, handle, size, region, mocs, tiling,
+ compression, compression_type);
+ blt_set_geom(obj, stride, 0, 0, width, height, 0, 0);
+
+ if (create_mapping)
+ obj->ptr = gem_mmap__device_coherent(i915, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+
+ return obj;
+}
+
+void blt_destroy_object(int i915, struct blt_copy_object *obj)
+{
+ if (obj->ptr)
+ munmap(obj->ptr, obj->size);
+
+ gem_close(i915, obj->handle);
+ free(obj);
+}
+
+void blt_set_object(struct blt_copy_object *obj,
+ uint32_t handle, uint64_t size, uint32_t region,
+ uint8_t mocs, enum blt_tiling_type tiling,
+ enum blt_compression compression,
+ enum blt_compression_type compression_type)
+{
+ obj->handle = handle;
+ obj->size = size;
+ obj->region = region;
+ obj->mocs = mocs;
+ obj->tiling = tiling;
+ obj->compression = compression;
+ obj->compression_type = compression_type;
+}
+
+void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
+ uint8_t compression_format,
+ uint16_t surface_width, uint16_t surface_height,
+ enum blt_surface_type surface_type)
+{
+ obj->compression_format = compression_format;
+ obj->surface_width = surface_width;
+ obj->surface_height = surface_height;
+ obj->surface_type = surface_type;
+
+ /* Ensure mip tail won't overlap lod */
+ obj->mip_tail_start_lod = 0xf;
+}
+
+void blt_set_copy_object(struct blt_copy_object *obj,
+ const struct blt_copy_object *orig)
+{
+ memcpy(obj, orig, sizeof(*obj));
+}
+
/**
* blt_surface_fill_rect:
* @i915: drm fd
diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
index 3730c7c0..0f084055 100644
--- a/lib/i915/i915_blt.h
+++ b/lib/i915/i915_blt.h
@@ -202,10 +202,36 @@ int blt_fast_copy(int i915,
uint64_t ahnd,
const struct blt_copy_data *blt);
+void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
+ int16_t x1, int16_t y1, int16_t x2, int16_t y2,
+ uint16_t x_offset, uint16_t y_offset);
+void blt_set_batch(struct blt_copy_batch *batch,
+ uint32_t handle, uint64_t size, uint32_t region);
+
+struct blt_copy_object *
+blt_create_object(int i915, uint32_t region,
+ uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs,
+ enum blt_tiling_type tiling,
+ enum blt_compression compression,
+ enum blt_compression_type compression_type,
+ bool create_mapping);
+void blt_destroy_object(int i915, struct blt_copy_object *obj);
+void blt_set_object(struct blt_copy_object *obj,
+ uint32_t handle, uint64_t size, uint32_t region,
+ uint8_t mocs, enum blt_tiling_type tiling,
+ enum blt_compression compression,
+ enum blt_compression_type compression_type);
+void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
+ uint8_t compression_format,
+ uint16_t surface_width, uint16_t surface_height,
+ enum blt_surface_type surface_type);
+void blt_set_copy_object(struct blt_copy_object *obj,
+ const struct blt_copy_object *orig);
+
void blt_surface_info(const char *info,
const struct blt_copy_object *obj);
void blt_surface_fill_rect(int i915, const struct blt_copy_object *obj,
uint32_t width, uint32_t height);
void blt_surface_to_png(int i915, uint32_t run_id, const char *fileid,
- const struct blt_copy_object *obj,
- uint32_t width, uint32_t height);
+ const struct blt_copy_object *obj,
+ uint32_t width, uint32_t height);
diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
index 10327050..b2da04b1 100644
--- a/tests/i915/gem_ccs.c
+++ b/tests/i915/gem_ccs.c
@@ -44,56 +44,6 @@ struct test_config {
bool suspend_resume;
};
-static void set_object(struct blt_copy_object *obj,
- uint32_t handle, uint64_t size, uint32_t region,
- uint8_t mocs, enum blt_tiling_type tiling,
- enum blt_compression compression,
- enum blt_compression_type compression_type)
-{
- obj->handle = handle;
- obj->size = size;
- obj->region = region;
- obj->mocs = mocs;
- obj->tiling = tiling;
- obj->compression = compression;
- obj->compression_type = compression_type;
-}
-
-static void set_geom(struct blt_copy_object *obj, uint32_t pitch,
- int16_t x1, int16_t y1, int16_t x2, int16_t y2,
- uint16_t x_offset, uint16_t y_offset)
-{
- obj->pitch = pitch;
- obj->x1 = x1;
- obj->y1 = y1;
- obj->x2 = x2;
- obj->y2 = y2;
- obj->x_offset = x_offset;
- obj->y_offset = y_offset;
-}
-
-static void set_batch(struct blt_copy_batch *batch,
- uint32_t handle, uint64_t size, uint32_t region)
-{
- batch->handle = handle;
- batch->size = size;
- batch->region = region;
-}
-
-static void set_object_ext(struct blt_block_copy_object_ext *obj,
- uint8_t compression_format,
- uint16_t surface_width, uint16_t surface_height,
- enum blt_surface_type surface_type)
-{
- obj->compression_format = compression_format;
- obj->surface_width = surface_width;
- obj->surface_height = surface_height;
- obj->surface_type = surface_type;
-
- /* Ensure mip tail won't overlap lod */
- obj->mip_tail_start_lod = 0xf;
-}
-
static void set_surf_object(struct blt_ctrl_surf_copy_object *obj,
uint32_t handle, uint32_t region, uint64_t size,
uint8_t mocs, enum blt_access_type access_type)
@@ -105,51 +55,6 @@ static void set_surf_object(struct blt_ctrl_surf_copy_object *obj,
obj->access_type = access_type;
}
-static struct blt_copy_object *
-create_object(int i915, uint32_t region,
- uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs,
- enum blt_tiling_type tiling,
- enum blt_compression compression,
- enum blt_compression_type compression_type,
- bool create_mapping)
-{
- struct blt_copy_object *obj;
- uint64_t size = width * height * bpp / 8;
- uint32_t stride = tiling == T_LINEAR ? width * 4 : width;
- uint32_t handle;
-
- obj = calloc(1, sizeof(*obj));
-
- obj->size = size;
- igt_assert(__gem_create_in_memory_regions(i915, &handle,
- &size, region) == 0);
-
- set_object(obj, handle, size, region, mocs, tiling,
- compression, compression_type);
- set_geom(obj, stride, 0, 0, width, height, 0, 0);
-
- if (create_mapping)
- obj->ptr = gem_mmap__device_coherent(i915, handle, 0, size,
- PROT_READ | PROT_WRITE);
-
- return obj;
-}
-
-static void destroy_object(int i915, struct blt_copy_object *obj)
-{
- if (obj->ptr)
- munmap(obj->ptr, obj->size);
-
- gem_close(i915, obj->handle);
- free(obj);
-}
-
-static void set_blt_object(struct blt_copy_object *obj,
- const struct blt_copy_object *orig)
-{
- memcpy(obj, orig, sizeof(*obj));
-}
-
#define PRINT_SURFACE_INFO(name, obj) do { \
if (param.print_surface_info) \
blt_surface_info((name), (obj)); } while (0)
@@ -189,7 +94,7 @@ static void surf_copy(int i915,
uc_mocs, INDIRECT_ACCESS);
set_surf_object(&surf.dst, ccs, REGION_SMEM, ccssize,
uc_mocs, DIRECT_ACCESS);
- set_batch(&surf.bb, bb, bb_size, REGION_SMEM);
+ blt_set_batch(&surf.bb, bb, bb_size, REGION_SMEM);
blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf);
gem_sync(i915, surf.dst.handle);
@@ -236,13 +141,13 @@ static void surf_copy(int i915,
memset(&blt, 0, sizeof(blt));
blt.color_depth = CD_32bit;
blt.print_bb = param.print_bb;
- set_blt_object(&blt.src, mid);
- set_blt_object(&blt.dst, dst);
- set_object_ext(&ext.src, mid->compression_type, mid->x2, mid->y2, SURFACE_TYPE_2D);
- set_object_ext(&ext.dst, 0, dst->x2, dst->y2, SURFACE_TYPE_2D);
+ blt_set_copy_object(&blt.src, mid);
+ blt_set_copy_object(&blt.dst, dst);
+ blt_set_object_ext(&ext.src, mid->compression_type, mid->x2, mid->y2, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext.dst, 0, dst->x2, dst->y2, SURFACE_TYPE_2D);
bb_size = 4096;
bb = gem_create_from_pool(i915, &bb_size, REGION_SMEM);
- set_batch(&blt.bb, bb, bb_size, REGION_SMEM);
+ blt_set_batch(&blt.bb, bb, bb_size, REGION_SMEM);
blt_block_copy(i915, ctx, e, ahnd, &blt, &ext);
gem_sync(i915, blt.dst.handle);
WRITE_PNG(i915, run_id, "corrupted", &blt.dst, dst->x2, dst->y2);
@@ -399,12 +304,12 @@ static void block_copy(int i915,
if (!blt_supports_compression(i915))
pext = NULL;
- src = create_object(i915, region1, width, height, bpp, uc_mocs,
- T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
- mid = create_object(i915, mid_region, width, height, bpp, uc_mocs,
- mid_tiling, mid_compression, comp_type, true);
- dst = create_object(i915, region1, width, height, bpp, uc_mocs,
- T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
+ src = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
+ T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
+ mid = blt_create_object(i915, mid_region, width, height, bpp, uc_mocs,
+ mid_tiling, mid_compression, comp_type, true);
+ dst = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
+ T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
igt_assert(src->size == dst->size);
PRINT_SURFACE_INFO("src", src);
PRINT_SURFACE_INFO("mid", mid);
@@ -416,11 +321,11 @@ static void block_copy(int i915,
memset(&blt, 0, sizeof(blt));
blt.color_depth = CD_32bit;
blt.print_bb = param.print_bb;
- set_blt_object(&blt.src, src);
- set_blt_object(&blt.dst, mid);
- set_object_ext(&ext.src, 0, width, height, SURFACE_TYPE_2D);
- set_object_ext(&ext.dst, mid_compression_format, width, height, SURFACE_TYPE_2D);
- set_batch(&blt.bb, bb, bb_size, region1);
+ blt_set_copy_object(&blt.src, src);
+ blt_set_copy_object(&blt.dst, mid);
+ blt_set_object_ext(&ext.src, 0, width, height, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext.dst, mid_compression_format, width, height, SURFACE_TYPE_2D);
+ blt_set_batch(&blt.bb, bb, bb_size, region1);
blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
gem_sync(i915, mid->handle);
@@ -462,26 +367,26 @@ static void block_copy(int i915,
memset(&blt, 0, sizeof(blt));
blt.color_depth = CD_32bit;
blt.print_bb = param.print_bb;
- set_blt_object(&blt.src, mid);
- set_blt_object(&blt.dst, dst);
- set_object_ext(&ext.src, mid_compression_format, width, height, SURFACE_TYPE_2D);
- set_object_ext(&ext.dst, 0, width, height, SURFACE_TYPE_2D);
+ blt_set_copy_object(&blt.src, mid);
+ blt_set_copy_object(&blt.dst, dst);
+ blt_set_object_ext(&ext.src, mid_compression_format, width, height, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext.dst, 0, width, height, SURFACE_TYPE_2D);
if (config->inplace) {
- set_object(&blt.dst, mid->handle, dst->size, mid->region, 0,
- T_LINEAR, COMPRESSION_DISABLED, comp_type);
+ blt_set_object(&blt.dst, mid->handle, dst->size, mid->region, 0,
+ T_LINEAR, COMPRESSION_DISABLED, comp_type);
blt.dst.ptr = mid->ptr;
}
- set_batch(&blt.bb, bb, bb_size, region1);
+ blt_set_batch(&blt.bb, bb, bb_size, region1);
blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
gem_sync(i915, blt.dst.handle);
WRITE_PNG(i915, run_id, "dst", &blt.dst, width, height);
result = memcmp(src->ptr, blt.dst.ptr, src->size);
- destroy_object(i915, src);
- destroy_object(i915, mid);
- destroy_object(i915, dst);
+ blt_destroy_object(i915, src);
+ blt_destroy_object(i915, mid);
+ blt_destroy_object(i915, dst);
gem_close(i915, bb);
put_ahnd(ahnd);
@@ -515,14 +420,14 @@ static void block_multicopy(int i915,
if (!blt_supports_compression(i915))
pext3 = NULL;
- src = create_object(i915, region1, width, height, bpp, uc_mocs,
- T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
- mid = create_object(i915, mid_region, width, height, bpp, uc_mocs,
- mid_tiling, mid_compression, comp_type, true);
- dst = create_object(i915, region1, width, height, bpp, uc_mocs,
- mid_tiling, COMPRESSION_DISABLED, comp_type, true);
- final = create_object(i915, region1, width, height, bpp, uc_mocs,
- T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
+ src = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
+ T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
+ mid = blt_create_object(i915, mid_region, width, height, bpp, uc_mocs,
+ mid_tiling, mid_compression, comp_type, true);
+ dst = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
+ mid_tiling, COMPRESSION_DISABLED, comp_type, true);
+ final = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
+ T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
igt_assert(src->size == dst->size);
PRINT_SURFACE_INFO("src", src);
PRINT_SURFACE_INFO("mid", mid);
@@ -534,22 +439,23 @@ static void block_multicopy(int i915,
memset(&blt3, 0, sizeof(blt3));
blt3.color_depth = CD_32bit;
blt3.print_bb = param.print_bb;
- set_blt_object(&blt3.src, src);
- set_blt_object(&blt3.mid, mid);
- set_blt_object(&blt3.dst, dst);
- set_blt_object(&blt3.final, final);
+ blt_set_copy_object(&blt3.src, src);
+ blt_set_copy_object(&blt3.mid, mid);
+ blt_set_copy_object(&blt3.dst, dst);
+ blt_set_copy_object(&blt3.final, final);
if (config->inplace) {
- set_object(&blt3.dst, mid->handle, dst->size, mid->region, mid->mocs,
- mid_tiling, COMPRESSION_DISABLED, comp_type);
+ blt_set_object(&blt3.dst, mid->handle, dst->size, mid->region,
+ mid->mocs, mid_tiling, COMPRESSION_DISABLED,
+ comp_type);
blt3.dst.ptr = mid->ptr;
}
- set_object_ext(&ext3.src, 0, width, height, SURFACE_TYPE_2D);
- set_object_ext(&ext3.mid, mid_compression_format, width, height, SURFACE_TYPE_2D);
- set_object_ext(&ext3.dst, 0, width, height, SURFACE_TYPE_2D);
- set_object_ext(&ext3.final, 0, width, height, SURFACE_TYPE_2D);
- set_batch(&blt3.bb, bb, bb_size, region1);
+ blt_set_object_ext(&ext3.src, 0, width, height, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext3.mid, mid_compression_format, width, height, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext3.dst, 0, width, height, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext3.final, 0, width, height, SURFACE_TYPE_2D);
+ blt_set_batch(&blt3.bb, bb, bb_size, region1);
blt_block_copy3(i915, ctx, e, ahnd, &blt3, pext3);
gem_sync(i915, blt3.final.handle);
@@ -562,10 +468,10 @@ static void block_multicopy(int i915,
result = memcmp(src->ptr, blt3.final.ptr, src->size);
- destroy_object(i915, src);
- destroy_object(i915, mid);
- destroy_object(i915, dst);
- destroy_object(i915, final);
+ blt_destroy_object(i915, src);
+ blt_destroy_object(i915, mid);
+ blt_destroy_object(i915, dst);
+ blt_destroy_object(i915, final);
gem_close(i915, bb);
put_ahnd(ahnd);
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index 9388d4de..55b044ec 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -76,53 +76,6 @@ struct object {
struct blt_copy_object *blt_obj;
};
-static void set_object(struct blt_copy_object *obj,
- uint32_t handle, uint64_t size, uint32_t region,
- uint8_t mocs, enum blt_tiling_type tiling,
- enum blt_compression compression,
- enum blt_compression_type compression_type)
-{
- obj->handle = handle;
- obj->size = size;
- obj->region = region;
- obj->mocs = mocs;
- obj->tiling = tiling;
- obj->compression = compression;
- obj->compression_type = compression_type;
-}
-
-static void set_geom(struct blt_copy_object *obj, uint32_t pitch,
- int16_t x1, int16_t y1, int16_t x2, int16_t y2,
- uint16_t x_offset, uint16_t y_offset)
-{
- obj->pitch = pitch;
- obj->x1 = x1;
- obj->y1 = y1;
- obj->x2 = x2;
- obj->y2 = y2;
- obj->x_offset = x_offset;
- obj->y_offset = y_offset;
-}
-
-static void set_batch(struct blt_copy_batch *batch,
- uint32_t handle, uint64_t size, uint32_t region)
-{
- batch->handle = handle;
- batch->size = size;
- batch->region = region;
-}
-
-static void set_object_ext(struct blt_block_copy_object_ext *obj,
- uint8_t compression_format,
- uint16_t surface_width, uint16_t surface_height,
- enum blt_surface_type surface_type)
-{
- obj->compression_format = compression_format;
- obj->surface_width = surface_width;
- obj->surface_height = surface_height;
- obj->surface_type = surface_type;
-}
-
static uint32_t create_bo(int i915,
uint64_t *size,
struct drm_i915_gem_memory_class_instance *region,
@@ -179,7 +132,7 @@ init_object_ccs(int i915, struct object *obj, struct blt_copy_object *tmp,
cmd = calloc(1, sizeof(*cmd));
igt_assert(cmd);
cmd->handle = gem_create_from_pool(i915, &size, region);
- set_batch(cmd, cmd->handle, size, region);
+ blt_set_batch(cmd, cmd->handle, size, region);
buf = gem_mmap__device_coherent(i915, tmp->handle, 0, obj->size, PROT_WRITE);
gem_set_domain(i915, tmp->handle, I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC);
@@ -195,9 +148,9 @@ init_object_ccs(int i915, struct object *obj, struct blt_copy_object *tmp,
memcpy(&blt.dst, obj->blt_obj, sizeof(blt.dst));
memcpy(&blt.bb, cmd, sizeof(blt.bb));
- set_object_ext(&ext.src, 0, tmp->x2, tmp->y2, SURFACE_TYPE_2D);
- set_object_ext(&ext.dst, 0, obj->blt_obj->x2, obj->blt_obj->y2,
- SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext.src, 0, tmp->x2, tmp->y2, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext.dst, 0, obj->blt_obj->x2, obj->blt_obj->y2,
+ SURFACE_TYPE_2D);
blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
free(cmd);
@@ -244,7 +197,7 @@ verify_object_ccs(int i915, const struct object *obj,
cmd = calloc(1, sizeof(*cmd));
igt_assert(cmd);
cmd->handle = gem_create_from_pool(i915, &size, region);
- set_batch(cmd, cmd->handle, size, region);
+ blt_set_batch(cmd, cmd->handle, size, region);
memset(&blt, 0, sizeof(blt));
blt.color_depth = CD_32bit;
@@ -256,9 +209,9 @@ verify_object_ccs(int i915, const struct object *obj,
blt.dst.x2 = min(obj->blt_obj->x2, tmp->x2);
blt.dst.y2 = min(obj->blt_obj->y2, tmp->y2);
- set_object_ext(&ext.src, 0, obj->blt_obj->x2, obj->blt_obj->y2,
- SURFACE_TYPE_2D);
- set_object_ext(&ext.dst, 0, tmp->x2, tmp->y2, SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext.src, 0, obj->blt_obj->x2, obj->blt_obj->y2,
+ SURFACE_TYPE_2D);
+ blt_set_object_ext(&ext.dst, 0, tmp->x2, tmp->y2, SURFACE_TYPE_2D);
blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
buf = gem_mmap__device_coherent(i915, tmp->handle, 0,
@@ -364,11 +317,11 @@ static void __do_evict(int i915,
tmp->handle = gem_create_in_memory_regions(i915, params->size.max,
INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
- set_object(tmp, tmp->handle, params->size.max,
- INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0),
- intel_get_uc_mocs(i915), T_LINEAR,
- COMPRESSION_DISABLED, COMPRESSION_TYPE_3D);
- set_geom(tmp, stride, 0, 0, width, height, 0, 0);
+ blt_set_object(tmp, tmp->handle, params->size.max,
+ INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0),
+ intel_get_uc_mocs(i915), T_LINEAR,
+ COMPRESSION_DISABLED, COMPRESSION_TYPE_3D);
+ blt_set_geom(tmp, stride, 0, 0, width, height, 0, 0);
}
size = 0;
@@ -395,10 +348,10 @@ static void __do_evict(int i915,
obj->blt_obj = calloc(1, sizeof(*obj->blt_obj));
igt_assert(obj->blt_obj);
- set_object(obj->blt_obj, obj->handle, obj->size, region_id,
- intel_get_uc_mocs(i915), T_LINEAR,
- COMPRESSION_ENABLED, COMPRESSION_TYPE_3D);
- set_geom(obj->blt_obj, stride, 0, 0, width, height, 0, 0);
+ blt_set_object(obj->blt_obj, obj->handle, obj->size, region_id,
+ intel_get_uc_mocs(i915), T_LINEAR,
+ COMPRESSION_ENABLED, COMPRESSION_TYPE_3D);
+ blt_set_geom(obj->blt_obj, stride, 0, 0, width, height, 0, 0);
init_object_ccs(i915, obj, tmp, rand(), blt_ctx,
region_id, ahnd);
} else if (params->flags & TEST_VERIFY) {
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH i-g-t v2 5/6] tests/gem_exercise_blt: Add fast-copy test
2022-12-23 11:13 [igt-dev] [PATCH i-g-t v2 0/6] Introduce blt_cmd_info struct Karolina Stolarek
` (3 preceding siblings ...)
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 4/6] lib/i915_blt: Add common functions for blt_copy_object Karolina Stolarek
@ 2022-12-23 11:13 ` Karolina Stolarek
2023-01-09 15:34 ` Zbigniew Kempczyński
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 6/6] tests/gem_exercise_blt: Add fast-copy-emit test Karolina Stolarek
` (2 subsequent siblings)
7 siblings, 1 reply; 21+ messages in thread
From: Karolina Stolarek @ 2022-12-23 11:13 UTC (permalink / raw)
To: igt-dev
Exercise a basic scenario with two block copies in separate batch
buffers.
Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
tests/i915/gem_exercise_blt.c | 216 ++++++++++++++++++++++++++++++++++
tests/meson.build | 1 +
2 files changed, 217 insertions(+)
create mode 100644 tests/i915/gem_exercise_blt.c
diff --git a/tests/i915/gem_exercise_blt.c b/tests/i915/gem_exercise_blt.c
new file mode 100644
index 00000000..67a8b660
--- /dev/null
+++ b/tests/i915/gem_exercise_blt.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "igt.h"
+#include "drm.h"
+#include "i915/gem.h"
+#include "i915/gem_create.h"
+#include "lib/intel_chipset.h"
+#include "i915/i915_blt.h"
+#include "i915/intel_mocs.h"
+
+IGT_TEST_DESCRIPTION("Exercise blitter commands");
+
+static struct param {
+ int tiling;
+ bool write_png;
+ bool print_bb;
+ bool print_surface_info;
+ int width;
+ int height;
+} param = {
+ .tiling = -1,
+ .write_png = false,
+ .print_bb = false,
+ .print_surface_info = false,
+ .width = 512,
+ .height = 512,
+};
+
+#define PRINT_SURFACE_INFO(name, obj) do { \
+ if (param.print_surface_info) \
+ blt_surface_info((name), (obj)); } while (0)
+
+#define WRITE_PNG(fd, id, name, obj, w, h) do { \
+ if (param.write_png) \
+ blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
+
+static void fast_copy(int i915, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ uint32_t region1, uint32_t region2,
+ enum blt_tiling_type mid_tiling)
+{
+ struct blt_copy_data blt = {};
+ struct blt_copy_object *src, *mid, *dst;
+ const uint32_t bpp = 32;
+ uint64_t bb_size = 4096;
+ uint64_t ahnd = intel_allocator_open_full(i915, ctx->id, 0, 0,
+ INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_LOW_TO_HIGH, 0);
+ uint32_t bb;
+ uint32_t width = param.width, height = param.height;
+ int result;
+
+ igt_assert(__gem_create_in_memory_regions(i915, &bb, &bb_size, region1) == 0);
+
+ src = blt_create_object(i915, region1, width, height, bpp, 0,
+ T_LINEAR, COMPRESSION_DISABLED, 0, true);
+ mid = blt_create_object(i915, region2, width, height, bpp, 0,
+ mid_tiling, COMPRESSION_DISABLED, 0, true);
+ dst = blt_create_object(i915, region1, width, height, bpp, 0,
+ T_LINEAR, COMPRESSION_DISABLED, 0, true);
+ igt_assert(src->size == dst->size);
+
+ blt_surface_fill_rect(i915, src, width, height);
+ WRITE_PNG(i915, mid_tiling, "src", src, width, height);
+
+ memset(&blt, 0, sizeof(blt));
+ blt.color_depth = CD_32bit;
+ blt.print_bb = param.print_bb;
+ blt_set_copy_object(&blt.src, src);
+ blt_set_copy_object(&blt.dst, mid);
+ blt_set_batch(&blt.bb, bb, bb_size, region1);
+
+ blt_fast_copy(i915, ctx, e, ahnd, &blt);
+ gem_sync(i915, mid->handle);
+
+ WRITE_PNG(i915, mid_tiling, "src", &blt.src, width, height);
+ WRITE_PNG(i915, mid_tiling, "mid", &blt.dst, width, height);
+
+ memset(&blt, 0, sizeof(blt));
+ blt.color_depth = CD_32bit;
+ blt.print_bb = param.print_bb;
+ blt_set_copy_object(&blt.src, mid);
+ blt_set_copy_object(&blt.dst, dst);
+ blt_set_batch(&blt.bb, bb, bb_size, region1);
+
+ blt_fast_copy(i915, ctx, e, ahnd, &blt);
+ gem_sync(i915, blt.dst.handle);
+
+ WRITE_PNG(i915, mid_tiling, "dst", &blt.dst, width, height);
+
+ result = memcmp(src->ptr, blt.dst.ptr, src->size);
+
+ blt_destroy_object(i915, src);
+ blt_destroy_object(i915, mid);
+ blt_destroy_object(i915, dst);
+ gem_close(i915, bb);
+ put_ahnd(ahnd);
+
+ igt_assert_f(!result, "source and destination surfaces differs!\n");
+}
+
+static void fast_copy_test(int i915,
+ const intel_ctx_t *ctx,
+ struct igt_collection *set)
+{
+ struct igt_collection *regions;
+ const struct intel_execution_engine2 *e;
+ int tiling;
+
+ for_each_tiling(tiling) {
+ if (!blt_fast_copy_supports_tiling(i915, tiling))
+ continue;
+
+ for_each_ctx_engine(i915, ctx, e) {
+ if (e->class != I915_ENGINE_CLASS_COPY)
+ continue;
+ for_each_variation_r(regions, 2, set) {
+ uint32_t region1, region2;
+ char *regtxt;
+
+ region1 = igt_collection_get_value(regions, 0);
+ region2 = igt_collection_get_value(regions, 1);
+ regtxt = memregion_dynamic_subtest_name(regions);
+
+ igt_dynamic_f("%s-%s",
+ blt_tiling_name(tiling), regtxt) {
+ fast_copy(i915, ctx, e,
+ region1, region2,
+ tiling);
+ }
+
+ free(regtxt);
+ }
+ }
+ }
+}
+
+static int opt_handler(int opt, int opt_index, void *data)
+{
+ switch (opt) {
+ case 'b':
+ param.print_bb = true;
+ igt_debug("Print bb: %d\n", param.print_bb);
+ break;
+ case 'p':
+ param.write_png = true;
+ igt_debug("Write png: %d\n", param.write_png);
+ break;
+ case 's':
+ param.print_surface_info = true;
+ igt_debug("Print surface info: %d\n", param.print_surface_info);
+ break;
+ case 't':
+ param.tiling = 1 << atoi(optarg);
+ igt_debug("Tiling: %d\n", param.tiling);
+ break;
+ case 'W':
+ param.width = atoi(optarg);
+ igt_debug("Width: %d\n", param.width);
+ break;
+ case 'H':
+ param.height = atoi(optarg);
+ igt_debug("Height: %d\n", param.height);
+ break;
+ default:
+ return IGT_OPT_HANDLER_ERROR;
+ }
+
+ return IGT_OPT_HANDLER_SUCCESS;
+}
+
+const char *help_str =
+ " -b\tPrint bb\n"
+ " -p\tWrite PNG\n"
+ " -s\tPrint surface info\n"
+ " -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64, 5 - YFMAJOR)\n"
+ " -W\tWidth (default 512)\n"
+ " -H\tHeight (default 512)"
+ ;
+
+igt_main_args("b:pst:W:H:", NULL, help_str, opt_handler, NULL)
+{
+ struct drm_i915_query_memory_regions *query_info;
+ struct igt_collection *set;
+ const intel_ctx_t *ctx;
+ int i915;
+ igt_hang_t hang;
+
+ igt_fixture {
+ i915 = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(i915);
+ igt_require(blt_has_fast_copy(i915));
+
+ query_info = gem_get_query_memory_regions(i915);
+ igt_require(query_info);
+
+ set = get_memory_region_set(query_info,
+ I915_SYSTEM_MEMORY,
+ I915_DEVICE_MEMORY);
+ ctx = intel_ctx_create_all_physical(i915);
+ hang = igt_allow_hang(i915, ctx->id, 0);
+ }
+
+ igt_describe("Check fast-copy blit");
+ igt_subtest_with_dynamic("fast-copy") {
+ fast_copy_test(i915, ctx, set);
+ }
+
+ igt_fixture {
+ igt_disallow_hang(i915, hang);
+ close(i915);
+ }
+}
diff --git a/tests/meson.build b/tests/meson.build
index cb428998..3c8a3ba3 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -129,6 +129,7 @@ i915_progs = [
'gem_exec_nop',
'gem_exec_parallel',
'gem_exec_params',
+ 'gem_exercise_blt',
'gen7_exec_parse',
'gen9_exec_parse',
'gem_exec_reloc',
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [igt-dev] [PATCH i-g-t v2 6/6] tests/gem_exercise_blt: Add fast-copy-emit test
2022-12-23 11:13 [igt-dev] [PATCH i-g-t v2 0/6] Introduce blt_cmd_info struct Karolina Stolarek
` (4 preceding siblings ...)
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 5/6] tests/gem_exercise_blt: Add fast-copy test Karolina Stolarek
@ 2022-12-23 11:13 ` Karolina Stolarek
2023-01-09 15:38 ` Zbigniew Kempczyński
2022-12-23 12:04 ` [igt-dev] ✓ Fi.CI.BAT: success for Introduce blt_cmd_info struct (rev2) Patchwork
2022-12-23 13:24 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
7 siblings, 1 reply; 21+ messages in thread
From: Karolina Stolarek @ 2022-12-23 11:13 UTC (permalink / raw)
To: igt-dev
Add a subtest where two fast copy commands are executed within the
single batch buffer.
Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
---
tests/i915/gem_exercise_blt.c | 190 ++++++++++++++++++++++++++++++++--
1 file changed, 184 insertions(+), 6 deletions(-)
diff --git a/tests/i915/gem_exercise_blt.c b/tests/i915/gem_exercise_blt.c
index 67a8b660..b8bfc436 100644
--- a/tests/i915/gem_exercise_blt.c
+++ b/tests/i915/gem_exercise_blt.c
@@ -37,6 +37,146 @@ static struct param {
if (param.write_png) \
blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
+struct blt_fast_copy_data {
+ int i915;
+ struct blt_copy_object src;
+ struct blt_copy_object mid;
+ struct blt_copy_object dst;
+
+ struct blt_copy_batch bb;
+ enum blt_color_depth color_depth;
+
+ /* debug stuff */
+ bool print_bb;
+};
+
+static int fast_copy_one_bb(int i915,
+ const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ uint64_t ahnd,
+ const struct blt_fast_copy_data *blt)
+{
+ struct drm_i915_gem_execbuffer2 execbuf = {};
+ struct drm_i915_gem_exec_object2 obj[4] = {};
+ struct blt_copy_data blt_tmp;
+ uint64_t src_offset, mid_offset, dst_offset, bb_offset, alignment;
+ uint64_t bb_pos = 0;
+ uint32_t flags;
+ int ret;
+
+ alignment = gem_detect_safe_alignment(i915);
+
+ src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
+ mid_offset = get_offset(ahnd, blt->mid.handle, blt->mid.size, alignment);
+ dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
+ bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
+
+ /* First blit */
+ memset(&blt_tmp, 0, sizeof(blt_tmp));
+ blt_tmp.src = blt->src;
+ blt_tmp.dst = blt->mid;
+ blt_tmp.bb = blt->bb;
+ blt_tmp.color_depth = blt->color_depth;
+ blt_tmp.print_bb = blt->print_bb;
+ bb_pos = emit_blt_fast_copy(i915, ahnd, &blt_tmp, bb_pos, false);
+
+ /* Second blit */
+ memset(&blt_tmp, 0, sizeof(blt_tmp));
+ blt_tmp.src = blt->mid;
+ blt_tmp.dst = blt->dst;
+ blt_tmp.bb = blt->bb;
+ blt_tmp.color_depth = blt->color_depth;
+ blt_tmp.print_bb = blt->print_bb;
+ bb_pos = emit_blt_fast_copy(i915, ahnd, &blt_tmp, bb_pos, true);
+
+ flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+ obj[0].handle = blt->src.handle;
+ obj[0].offset = CANONICAL(src_offset);
+ obj[0].flags = flags;
+
+ obj[1].handle = blt->mid.handle;
+ obj[1].offset = CANONICAL(mid_offset);
+ obj[1].flags = flags | EXEC_OBJECT_WRITE;
+
+ obj[2].handle = blt->dst.handle;
+ obj[2].offset = CANONICAL(dst_offset);
+ obj[2].flags = flags;
+
+ obj[3].handle = blt->bb.handle;
+ obj[3].offset = CANONICAL(bb_offset);
+ obj[3].flags = flags;
+
+ execbuf.buffer_count = 4;
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.rsvd1 = ctx ? ctx->id : 0;
+ execbuf.flags = e ? e->flags : I915_EXEC_BLT;
+ ret = __gem_execbuf(i915, &execbuf);
+
+ gem_sync(i915, blt->bb.handle);
+
+ return ret;
+}
+
+static void fast_copy_emit(int i915, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ uint32_t region1, uint32_t region2,
+ enum blt_tiling_type mid_tiling)
+{
+ struct blt_fast_copy_data blt = {};
+ struct blt_copy_object *src, *mid, *dst;
+ const uint32_t bpp = 32;
+ uint64_t bb_size = 4096;
+ uint64_t ahnd = intel_allocator_open_full(i915, ctx->id, 0, 0,
+ INTEL_ALLOCATOR_SIMPLE,
+ ALLOC_STRATEGY_LOW_TO_HIGH, 0);
+ uint32_t bb, width = param.width, height = param.height;
+ int result;
+
+ igt_assert(__gem_create_in_memory_regions(i915, &bb, &bb_size, region1) == 0);
+
+ src = blt_create_object(i915, region1, width, height, bpp, 0,
+ T_LINEAR, COMPRESSION_DISABLED, 0, true);
+ mid = blt_create_object(i915, region2, width, height, bpp, 0,
+ mid_tiling, COMPRESSION_DISABLED, 0, true);
+ dst = blt_create_object(i915, region1, width, height, bpp, 0,
+ T_LINEAR, COMPRESSION_DISABLED, 0, true);
+ igt_assert(src->size == dst->size);
+
+ PRINT_SURFACE_INFO("src", src);
+ PRINT_SURFACE_INFO("mid", mid);
+ PRINT_SURFACE_INFO("dst", dst);
+
+ blt_surface_fill_rect(i915, src, width, height);
+ WRITE_PNG(i915, mid_tiling, "src", src, width, height);
+
+ memset(&blt, 0, sizeof(blt));
+ blt.color_depth = CD_32bit;
+ blt.print_bb = param.print_bb;
+ blt_set_copy_object(&blt.src, src);
+ blt_set_copy_object(&blt.mid, mid);
+ blt_set_copy_object(&blt.dst, dst);
+ blt_set_batch(&blt.bb, bb, bb_size, region1);
+
+ fast_copy_one_bb(i915, ctx, e, ahnd, &blt);
+ gem_sync(i915, blt.dst.handle);
+
+ WRITE_PNG(i915, mid_tiling, "mid", &blt.mid, width, height);
+ WRITE_PNG(i915, mid_tiling, "dst", &blt.dst, width, height);
+
+ result = memcmp(src->ptr, blt.dst.ptr, src->size);
+
+ blt_destroy_object(i915, src);
+ blt_destroy_object(i915, mid);
+ blt_destroy_object(i915, dst);
+ gem_close(i915, bb);
+ put_ahnd(ahnd);
+
+ munmap(&bb, bb_size);
+
+ igt_assert_f(!result, "source and destination surfaces differs!\n");
+}
+
static void fast_copy(int i915, const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e,
uint32_t region1, uint32_t region2,
@@ -102,12 +242,42 @@ static void fast_copy(int i915, const intel_ctx_t *ctx,
igt_assert_f(!result, "source and destination surfaces differs!\n");
}
+enum fast_copy_func {
+ FAST_COPY,
+ FAST_COPY_EMIT
+};
+
+static char
+ *full_subtest_str(char *regtxt, enum blt_tiling_type tiling,
+ enum fast_copy_func func)
+{
+ const char *multi_str = "emit";
+ char const *tile_str = blt_tiling_name(tiling);
+ char *name;
+ uint32_t len, sub_len;
+
+ len = strlen(regtxt) + strlen(tile_str) + strlen(multi_str) + 2;
+ name = malloc(len * sizeof(char));
+ igt_assert(name);
+
+ sub_len = snprintf(name, len, "%s-%s", tile_str, regtxt);
+
+ if (func == FAST_COPY_EMIT)
+ snprintf(name + sub_len, len, "-%s", multi_str);
+
+ return name;
+}
+
static void fast_copy_test(int i915,
const intel_ctx_t *ctx,
- struct igt_collection *set)
+ struct igt_collection *set,
+ enum fast_copy_func func)
{
struct igt_collection *regions;
const struct intel_execution_engine2 *e;
+ void (*copy_func)(int i915, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ uint32_t r1, uint32_t r2, enum blt_tiling_type tiling);
int tiling;
for_each_tiling(tiling) {
@@ -119,20 +289,23 @@ static void fast_copy_test(int i915,
continue;
for_each_variation_r(regions, 2, set) {
uint32_t region1, region2;
- char *regtxt;
+ char *regtxt, *test_name;
region1 = igt_collection_get_value(regions, 0);
region2 = igt_collection_get_value(regions, 1);
+
+ copy_func = (func == FAST_COPY) ? fast_copy : fast_copy_emit;
regtxt = memregion_dynamic_subtest_name(regions);
+ test_name = full_subtest_str(regtxt, tiling, func);
- igt_dynamic_f("%s-%s",
- blt_tiling_name(tiling), regtxt) {
- fast_copy(i915, ctx, e,
+ igt_dynamic_f("%s", test_name) {
+ copy_func(i915, ctx, e,
region1, region2,
tiling);
}
free(regtxt);
+ free(test_name);
}
}
}
@@ -206,7 +379,12 @@ igt_main_args("b:pst:W:H:", NULL, help_str, opt_handler, NULL)
igt_describe("Check fast-copy blit");
igt_subtest_with_dynamic("fast-copy") {
- fast_copy_test(i915, ctx, set);
+ fast_copy_test(i915, ctx, set, FAST_COPY);
+ }
+
+ igt_describe("Check multiple fast-copy in one batch");
+ igt_subtest_with_dynamic("fast-copy-emit") {
+ fast_copy_test(i915, ctx, set, FAST_COPY_EMIT);
}
igt_fixture {
--
2.25.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Introduce blt_cmd_info struct (rev2)
2022-12-23 11:13 [igt-dev] [PATCH i-g-t v2 0/6] Introduce blt_cmd_info struct Karolina Stolarek
` (5 preceding siblings ...)
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 6/6] tests/gem_exercise_blt: Add fast-copy-emit test Karolina Stolarek
@ 2022-12-23 12:04 ` Patchwork
2022-12-23 13:24 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
7 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2022-12-23 12:04 UTC (permalink / raw)
To: Karolina Stolarek; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 3967 bytes --]
== Series Details ==
Series: Introduce blt_cmd_info struct (rev2)
URL : https://patchwork.freedesktop.org/series/112055/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12524 -> IGTPW_8270
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/index.html
Participating hosts (45 -> 44)
------------------------------
Missing (1): fi-kbl-soraka
Known issues
------------
Here are the changes found in IGTPW_8270 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@mman:
- fi-rkl-guc: [PASS][1] -> [TIMEOUT][2] ([i915#6794])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/fi-rkl-guc/igt@i915_selftest@live@mman.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/fi-rkl-guc/igt@i915_selftest@live@mman.html
#### Possible fixes ####
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510: [FAIL][3] ([i915#7229]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
* igt@i915_selftest@live@migrate:
- bat-adlp-4: [DMESG-FAIL][5] ([i915#7699]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/bat-adlp-4/igt@i915_selftest@live@migrate.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/bat-adlp-4/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@mman:
- {bat-rpls-1}: [TIMEOUT][7] ([i915#6794]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/bat-rpls-1/igt@i915_selftest@live@mman.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/bat-rpls-1/igt@i915_selftest@live@mman.html
* igt@i915_selftest@live@slpc:
- {bat-adln-1}: [DMESG-FAIL][9] ([i915#6997]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/bat-adln-1/igt@i915_selftest@live@slpc.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/bat-adln-1/igt@i915_selftest@live@slpc.html
* igt@i915_selftest@live@workarounds:
- {bat-rpls-1}: [DMESG-WARN][11] -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/bat-rpls-1/igt@i915_selftest@live@workarounds.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/bat-rpls-1/igt@i915_selftest@live@workarounds.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#6106]: https://gitlab.freedesktop.org/drm/intel/issues/6106
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7351]: https://gitlab.freedesktop.org/drm/intel/issues/7351
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7102 -> IGTPW_8270
CI-20190529: 20190529
CI_DRM_12524: a29956c69a562e85ef8657e39382bc207a339941 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8270: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/index.html
IGT_7102: bacfdc84a9c02556c5441deb21e3a3f18a07347d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@gem_exercise_blt@fast-copy
+igt@gem_exercise_blt@fast-copy-emit
-igt@kms_plane_scaling@max-source-size
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/index.html
[-- Attachment #2: Type: text/html, Size: 4447 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Introduce blt_cmd_info struct (rev2)
2022-12-23 11:13 [igt-dev] [PATCH i-g-t v2 0/6] Introduce blt_cmd_info struct Karolina Stolarek
` (6 preceding siblings ...)
2022-12-23 12:04 ` [igt-dev] ✓ Fi.CI.BAT: success for Introduce blt_cmd_info struct (rev2) Patchwork
@ 2022-12-23 13:24 ` Patchwork
7 siblings, 0 replies; 21+ messages in thread
From: Patchwork @ 2022-12-23 13:24 UTC (permalink / raw)
To: Karolina Stolarek; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 28584 bytes --]
== Series Details ==
Series: Introduce blt_cmd_info struct (rev2)
URL : https://patchwork.freedesktop.org/series/112055/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12524_full -> IGTPW_8270_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/index.html
Participating hosts (13 -> 10)
------------------------------
Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_8270_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_ccs@ctrl-surf-copy:
- {shard-rkl}: [SKIP][1] ([i915#3555] / [i915#5325]) -> [SKIP][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-1/igt@gem_ccs@ctrl-surf-copy.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-5/igt@gem_ccs@ctrl-surf-copy.html
New tests
---------
New tests have been introduced between CI_DRM_12524_full and IGTPW_8270_full:
### New IGT tests (36) ###
* igt@gem_exercise_blt@fast-copy:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit:
- Statuses : 1 skip(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@linear-lmem0-lmem0-emit:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@linear-lmem0-smem-emit:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@linear-smem-lmem0-emit:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@linear-smem-smem-emit:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@tile4-lmem0-lmem0-emit:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@tile4-lmem0-smem-emit:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@tile4-smem-lmem0-emit:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@tile4-smem-smem-emit:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@tile64-lmem0-lmem0-emit:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@tile64-lmem0-smem-emit:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@tile64-smem-lmem0-emit:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@tile64-smem-smem-emit:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@yfmajor-smem-smem-emit:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@ymajor-lmem0-lmem0-emit:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@ymajor-lmem0-smem-emit:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@ymajor-smem-lmem0-emit:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy-emit@ymajor-smem-smem-emit:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@linear-lmem0-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@linear-lmem0-smem:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@linear-smem-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@linear-smem-smem:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@tile4-lmem0-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@tile4-lmem0-smem:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@tile4-smem-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@tile4-smem-smem:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@tile64-lmem0-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@tile64-lmem0-smem:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@tile64-smem-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@tile64-smem-smem:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@yfmajor-smem-smem:
- Statuses : 3 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@ymajor-lmem0-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@ymajor-lmem0-smem:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@ymajor-smem-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exercise_blt@fast-copy@ymajor-smem-smem:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_8270_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-snb5/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2842]) +2 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-apl: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-apl3/igt@gem_lmem_swapping@parallel-random-engines.html
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-glk5/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
- shard-apl: [PASS][8] -> [INCOMPLETE][9] ([i915#7708])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-apl7/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-apl3/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#3886]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-glk4/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#3886]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-apl3/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-crc-fast:
- shard-glk: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +4 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-glk9/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-with-enabled-mode:
- shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-apl2/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html
* igt@kms_color_chamelium@ctm-negative:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +4 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-snb5/igt@kms_color_chamelium@ctm-negative.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#79])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-glk: NOTRUN -> [SKIP][17] ([fdo#109271]) +60 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-glk7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271]) +84 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-apl7/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-dp-1:
- shard-apl: NOTRUN -> [FAIL][19] ([i915#4573]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-apl1/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-dp-1.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-b-hdmi-a-2:
- shard-glk: NOTRUN -> [FAIL][20] ([i915#4573]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-glk1/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-b-hdmi-a-2.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-apl: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#658])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-apl1/igt@kms_psr2_sf@cursor-plane-update-sf.html
- shard-glk: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#658])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-glk2/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-snb: NOTRUN -> [SKIP][23] ([fdo#109271]) +123 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-snb7/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-glk: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#533])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-glk5/igt@kms_vblank@pipe-d-wait-idle.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#2994]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-apl3/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@sema-10:
- shard-glk: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#2994]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-glk9/igt@sysfs_clients@sema-10.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- {shard-rkl}: [SKIP][27] ([i915#658]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-5/igt@feature_discovery@psr2.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-6/igt@feature_discovery@psr2.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [FAIL][29] ([i915#2842]) -> [PASS][30] +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-apl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-apl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- {shard-rkl}: [FAIL][31] ([i915#2842]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-1/igt@gem_exec_fair@basic-pace@vcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-5/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_reloc@basic-wc:
- {shard-rkl}: [SKIP][33] ([i915#3281]) -> [PASS][34] +5 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-3/igt@gem_exec_reloc@basic-wc.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-5/igt@gem_exec_reloc@basic-wc.html
* igt@gem_mmap_gtt@coherency:
- {shard-rkl}: [SKIP][35] ([fdo#111656]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-3/igt@gem_mmap_gtt@coherency.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-5/igt@gem_mmap_gtt@coherency.html
* igt@gem_partial_pwrite_pread@writes-after-reads:
- shard-apl: [INCOMPLETE][37] -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-apl3/igt@gem_partial_pwrite_pread@writes-after-reads.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-apl1/igt@gem_partial_pwrite_pread@writes-after-reads.html
* igt@gem_readwrite@new-obj:
- {shard-rkl}: [SKIP][39] ([i915#3282]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-6/igt@gem_readwrite@new-obj.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-5/igt@gem_readwrite@new-obj.html
* igt@gen9_exec_parse@unaligned-jump:
- {shard-rkl}: [SKIP][41] ([i915#2527]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-2/igt@gen9_exec_parse@unaligned-jump.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-5/igt@gen9_exec_parse@unaligned-jump.html
* igt@i915_hangman@gt-engine-error@bcs0:
- {shard-rkl}: [SKIP][43] ([i915#6258]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-5/igt@i915_hangman@gt-engine-error@bcs0.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-1/igt@i915_hangman@gt-engine-error@bcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}: [WARN][45] ([i915#2681]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-1/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rpm@dpms-lpsp:
- {shard-rkl}: [SKIP][47] ([i915#1397]) -> [PASS][48] +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-2/igt@i915_pm_rpm@dpms-lpsp.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-6/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- {shard-dg1}: [SKIP][49] ([i915#1397]) -> [PASS][50] +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-dg1-14/igt@i915_pm_rpm@dpms-non-lpsp.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-dg1-13/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [FAIL][51] ([i915#2346]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-apl: [FAIL][53] ([i915#2346]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@psr:
- {shard-rkl}: [SKIP][55] ([fdo#110189] / [i915#3955]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-5/igt@kms_fbcon_fbt@psr.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-6/igt@kms_fbcon_fbt@psr.html
* igt@kms_flip@plain-flip-ts-check@c-hdmi-a1:
- shard-glk: [FAIL][57] ([i915#2122]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-glk3/igt@kms_flip@plain-flip-ts-check@c-hdmi-a1.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-glk9/igt@kms_flip@plain-flip-ts-check@c-hdmi-a1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- {shard-rkl}: [SKIP][59] ([i915#1849] / [i915#4098]) -> [PASS][60] +13 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_psr@cursor_render:
- {shard-rkl}: [SKIP][61] ([i915#1072]) -> [PASS][62] +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-3/igt@kms_psr@cursor_render.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-6/igt@kms_psr@cursor_render.html
* igt@kms_universal_plane@cursor-fb-leak-pipe-b:
- {shard-rkl}: [SKIP][63] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][64] +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-2/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-6/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
* igt@kms_vblank@pipe-b-query-idle:
- {shard-rkl}: [SKIP][65] ([i915#1845] / [i915#4098]) -> [PASS][66] +18 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-4/igt@kms_vblank@pipe-b-query-idle.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/shard-rkl-6/igt@kms_vblank@pipe-b-query-idle.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2532]: https://gitlab.freedesktop.org/drm/intel/issues/2532
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7708]: https://gitlab.freedesktop.org/drm/intel/issues/7708
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7102 -> IGTPW_8270
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12524: a29956c69a562e85ef8657e39382bc207a339941 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_8270: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/index.html
IGT_7102: bacfdc84a9c02556c5441deb21e3a3f18a07347d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_8270/index.html
[-- Attachment #2: Type: text/html, Size: 25771 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 2/6] lib: Update platform definitions with blitter information
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 2/6] lib: Update platform definitions with blitter information Karolina Stolarek
@ 2022-12-28 16:41 ` Kamil Konieczny
2023-01-03 9:17 ` Karolina Stolarek
2023-01-09 15:24 ` Zbigniew Kempczyński
2023-01-09 15:20 ` Zbigniew Kempczyński
1 sibling, 2 replies; 21+ messages in thread
From: Kamil Konieczny @ 2022-12-28 16:41 UTC (permalink / raw)
To: igt-dev
Hi Karolina,
On 2022-12-23 at 12:13:47 +0100, Karolina Stolarek wrote:
> Update entries in intel_device_info to store information on
> supported blitter commands and tiling formats. Add predicates
> that check if block or fast copy are supported. Update block
> copy tests to use the new checks.
>
> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
Please put here list of Cc:
Cc: Zbigniew Kempczynski <zbigniew.kempczynski@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> ---
> lib/i915/i915_blt.c | 75 +++++++++++++++++++++++++++++++----------
> lib/i915/i915_blt.h | 6 +++-
> lib/intel_chipset.c | 1 -
> lib/intel_chipset.h | 4 +++
> lib/intel_device_info.c | 47 ++++++++++++++++++++++++++
> tests/i915/gem_ccs.c | 4 +--
> 6 files changed, 115 insertions(+), 22 deletions(-)
>
> diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
> index 6db135d1..00cf7470 100644
> --- a/lib/i915/i915_blt.c
> +++ b/lib/i915/i915_blt.c
> @@ -208,34 +208,73 @@ bool blt_supports_compression(int i915)
> }
>
> /**
> - * blt_supports_tiling:
> + * blt_has_block_copy
> * @i915: drm fd
> - * @tiling: tiling id
> *
> - * Function checks if blitter supports @tiling on @i915 device.
> + * Check if block copy is supported by @i915 device
> *
> * Returns:
> * true if it does, false otherwise.
> */
> -bool blt_supports_tiling(int i915, enum blt_tiling_type tiling)
> +bool blt_has_block_copy(int i915)
> {
> - uint32_t devid = intel_get_drm_devid(i915);
> + const struct blt_cmd_info
> + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
>
> - if (tiling == T_XMAJOR) {
> - if (IS_TIGERLAKE(devid) || IS_DG1(devid))
> - return false;
> - else
> - return true;
> - }
> + return blt_supports_command(blt_info, XY_BLOCK_COPY);
> +}
>
> - if (tiling == T_YMAJOR) {
> - if (IS_TIGERLAKE(devid) || IS_DG1(devid))
> - return true;
> - else
> - return false;
> - }
> +/**
> + * blt_has_fast_copy
> + * @i915: drm fd
> + *
> + * Check if fast copy is supported by @i915 device
> + *
> + * Returns:
> + * true if it does, false otherwise.
> + */
> +bool blt_has_fast_copy(int i915)
> +{
> + const struct blt_cmd_info
> + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
> +
> + return blt_supports_command(blt_info, XY_FAST_COPY);
> +}
> +
> +/**
> + * blt_fast_copy_supports_tiling
> + * @i915: drm fd
> + * @tiling: tiling format
> + *
> + * Check if fast copy provided by @i915 device supports @tiling format
> + *
> + * Returns:
> + * true if it does, false otherwise.
> + */
> +bool blt_fast_copy_supports_tiling(int i915, enum blt_tiling_type tiling)
> +{
> + const struct blt_cmd_info
> + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
> +
> + return blt_cmd_supports_tiling(blt_info, XY_FAST_COPY, tiling);
> +}
> +
> +/**
> + * blt_block_copy_supports_tiling
> + * @i915: drm fd
> + * @tiling: tiling format
> + *
> + * Check if block copy provided by @i915 device supports @tiling format
> + *
> + * Returns:
> + * true if it does, false otherwise.
> + */
> +bool blt_block_copy_supports_tiling(int i915, enum blt_tiling_type tiling)
> +{
> + const struct blt_cmd_info
> + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
>
> - return true;
> + return blt_cmd_supports_tiling(blt_info, XY_BLOCK_COPY, tiling);
> }
>
> static int __block_tiling(enum blt_tiling_type tiling)
> diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
> index 8fa480b8..3730c7c0 100644
> --- a/lib/i915/i915_blt.h
> +++ b/lib/i915/i915_blt.h
> @@ -158,7 +158,11 @@ struct blt_ctrl_surf_copy_data {
> };
>
> bool blt_supports_compression(int i915);
> -bool blt_supports_tiling(int i915, enum blt_tiling_type tiling);
> +
> +bool blt_has_block_copy(int i915);
> +bool blt_has_fast_copy(int i915);
> +bool blt_fast_copy_supports_tiling(int i915, enum blt_tiling_type tiling);
> +bool blt_block_copy_supports_tiling(int i915, enum blt_tiling_type tiling);
>
> uint64_t emit_blt_block_copy(int i915,
> uint64_t ahnd,
> diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
> index efb6f177..4ac067df 100644
> --- a/lib/intel_chipset.c
> +++ b/lib/intel_chipset.c
> @@ -41,7 +41,6 @@
> #include "drmtest.h"
> #include "intel_chipset.h"
> #include "igt_core.h"
> -
- ^
Please do not make unrelated changes in lib (here line was deleted).
> /**
> * SECTION:intel_chipset
> * @short_description: Feature macros and chipset helpers
> diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> index 9b39472a..a9801b28 100644
> --- a/lib/intel_chipset.h
> +++ b/lib/intel_chipset.h
> @@ -31,6 +31,8 @@
> #include <pciaccess.h>
> #include <stdbool.h>
>
> +#include "i915/intel_blt_info.h"
> +
Imho this is a little too big change.
> #define BIT(x) (1ul <<(x))
>
> struct pci_device *intel_get_pci_device(void);
> @@ -86,11 +88,13 @@ struct intel_device_info {
> bool is_alderlake_p : 1;
> bool is_alderlake_n : 1;
> bool is_meteorlake : 1;
> + const struct blt_cmd_info *blt_tiling;
I would expect here to have bits for supported copy commands
like has_xy_block_copy, has_xy_src_block_copy, has_xy_fast_copy
and other. At the end of lib there are macros like HAS_FLATCCS(devid)
so there could be added new ones like HAS_XY_FAST_COPY(devid).
You added comment at your first patch 1/6 that YFmajor tiling
is supported only for gen9 and only for specific blt command (fast copy),
so imho it adds too many complicated info here. I would prefer to
keep that in blt library, not here.
Regards,
Kamil
> const char *codename;
> };
>
> const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
>
> +const struct blt_cmd_info *intel_get_blt_info(uint16_t devid) __attribute__((pure));
> unsigned intel_gen(uint16_t devid) __attribute__((pure));
> unsigned intel_graphics_ver(uint16_t devid) __attribute__((pure));
> unsigned intel_display_ver(uint16_t devid) __attribute__((pure));
> diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> index 68dd17ee..ad9dffd8 100644
> --- a/lib/intel_device_info.c
> +++ b/lib/intel_device_info.c
> @@ -145,6 +145,7 @@ static const struct intel_device_info intel_sandybridge_info = {
> .graphics_ver = 6,
> .display_ver = 6,
> .is_sandybridge = true,
> + .blt_tiling = &pre_gen8_blt_info,
> .codename = "sandybridge"
> };
> static const struct intel_device_info intel_sandybridge_m_info = {
> @@ -152,6 +153,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
> .display_ver = 6,
> .is_mobile = true,
> .is_sandybridge = true,
> + .blt_tiling = &pre_gen8_blt_info,
> .codename = "sandybridge"
> };
>
> @@ -159,6 +161,7 @@ static const struct intel_device_info intel_ivybridge_info = {
> .graphics_ver = 7,
> .display_ver = 7,
> .is_ivybridge = true,
> + .blt_tiling = &pre_gen8_blt_info,
> .codename = "ivybridge"
> };
> static const struct intel_device_info intel_ivybridge_m_info = {
> @@ -166,6 +169,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
> .display_ver = 7,
> .is_mobile = true,
> .is_ivybridge = true,
> + .blt_tiling = &pre_gen8_blt_info,
> .codename = "ivybridge"
> };
>
> @@ -173,6 +177,7 @@ static const struct intel_device_info intel_valleyview_info = {
> .graphics_ver = 7,
> .display_ver = 7,
> .is_valleyview = true,
> + .blt_tiling = &pre_gen8_blt_info,
> .codename = "valleyview"
> };
>
> @@ -180,6 +185,7 @@ static const struct intel_device_info intel_valleyview_info = {
> .graphics_ver = 7, \
> .display_ver = 7, \
> .is_haswell = true, \
> + .blt_tiling = &pre_gen8_blt_info, \
> .codename = "haswell"
>
> static const struct intel_device_info intel_haswell_gt1_info = {
> @@ -201,6 +207,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
> .graphics_ver = 8, \
> .display_ver = 8, \
> .is_broadwell = true, \
> + .blt_tiling = &gen8_blt_info, \
> .codename = "broadwell"
>
> static const struct intel_device_info intel_broadwell_gt1_info = {
> @@ -226,12 +233,14 @@ static const struct intel_device_info intel_cherryview_info = {
> .graphics_ver = 8,
> .display_ver = 8,
> .is_cherryview = true,
> + .blt_tiling = &gen8_blt_info,
> .codename = "cherryview"
> };
>
> #define SKYLAKE_FIELDS \
> .graphics_ver = 9, \
> .display_ver = 9, \
> + .blt_tiling = &gen11_blt_info, \
> .codename = "skylake", \
> .is_skylake = true
>
> @@ -259,6 +268,7 @@ static const struct intel_device_info intel_broxton_info = {
> .graphics_ver = 9,
> .display_ver = 9,
> .is_broxton = true,
> + .blt_tiling = &gen11_blt_info,
> .codename = "broxton"
> };
>
> @@ -266,6 +276,7 @@ static const struct intel_device_info intel_broxton_info = {
> .graphics_ver = 9, \
> .display_ver = 9, \
> .is_kabylake = true, \
> + .blt_tiling = &gen11_blt_info, \
> .codename = "kabylake"
>
> static const struct intel_device_info intel_kabylake_gt1_info = {
> @@ -292,6 +303,7 @@ static const struct intel_device_info intel_geminilake_info = {
> .graphics_ver = 9,
> .display_ver = 9,
> .is_geminilake = true,
> + .blt_tiling = &gen11_blt_info,
> .codename = "geminilake"
> };
>
> @@ -299,6 +311,7 @@ static const struct intel_device_info intel_geminilake_info = {
> .graphics_ver = 9, \
> .display_ver = 9, \
> .is_coffeelake = true, \
> + .blt_tiling = &gen11_blt_info, \
> .codename = "coffeelake"
>
> static const struct intel_device_info intel_coffeelake_gt1_info = {
> @@ -320,6 +333,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
> .graphics_ver = 9, \
> .display_ver = 9, \
> .is_cometlake = true, \
> + .blt_tiling = &gen11_blt_info, \
> .codename = "cometlake"
>
> static const struct intel_device_info intel_cometlake_gt1_info = {
> @@ -336,6 +350,7 @@ static const struct intel_device_info intel_cannonlake_info = {
> .graphics_ver = 10,
> .display_ver = 10,
> .is_cannonlake = true,
> + .blt_tiling = &gen11_blt_info,
> .codename = "cannonlake"
> };
>
> @@ -343,6 +358,7 @@ static const struct intel_device_info intel_icelake_info = {
> .graphics_ver = 11,
> .display_ver = 11,
> .is_icelake = true,
> + .blt_tiling = &gen11_blt_info,
> .codename = "icelake"
> };
>
> @@ -350,6 +366,7 @@ static const struct intel_device_info intel_elkhartlake_info = {
> .graphics_ver = 11,
> .display_ver = 11,
> .is_elkhartlake = true,
> + .blt_tiling = &gen11_blt_info,
> .codename = "elkhartlake"
> };
>
> @@ -357,6 +374,7 @@ static const struct intel_device_info intel_jasperlake_info = {
> .graphics_ver = 11,
> .display_ver = 11,
> .is_jasperlake = true,
> + .blt_tiling = &gen11_blt_info,
> .codename = "jasperlake"
> };
>
> @@ -364,6 +382,7 @@ static const struct intel_device_info intel_tigerlake_gt1_info = {
> .graphics_ver = 12,
> .display_ver = 12,
> .is_tigerlake = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "tigerlake",
> .gt = 1,
> };
> @@ -372,6 +391,7 @@ static const struct intel_device_info intel_tigerlake_gt2_info = {
> .graphics_ver = 12,
> .display_ver = 12,
> .is_tigerlake = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "tigerlake",
> .gt = 2,
> };
> @@ -380,6 +400,7 @@ static const struct intel_device_info intel_rocketlake_info = {
> .graphics_ver = 12,
> .display_ver = 12,
> .is_rocketlake = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "rocketlake"
> };
>
> @@ -388,6 +409,7 @@ static const struct intel_device_info intel_dg1_info = {
> .graphics_rel = 10,
> .display_ver = 12,
> .is_dg1 = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "dg1"
> };
>
> @@ -398,6 +420,7 @@ static const struct intel_device_info intel_dg2_info = {
> .has_4tile = true,
> .is_dg2 = true,
> .codename = "dg2",
> + .blt_tiling = &gen12_dg2_blt_info,
> .has_flatccs = true,
> };
>
> @@ -405,6 +428,7 @@ static const struct intel_device_info intel_alderlake_s_info = {
> .graphics_ver = 12,
> .display_ver = 12,
> .is_alderlake_s = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "alderlake_s"
> };
>
> @@ -412,6 +436,7 @@ static const struct intel_device_info intel_raptorlake_s_info = {
> .graphics_ver = 12,
> .display_ver = 12,
> .is_raptorlake_s = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "raptorlake_s"
> };
>
> @@ -419,6 +444,7 @@ static const struct intel_device_info intel_alderlake_p_info = {
> .graphics_ver = 12,
> .display_ver = 13,
> .is_alderlake_p = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "alderlake_p"
> };
>
> @@ -426,6 +452,7 @@ static const struct intel_device_info intel_alderlake_n_info = {
> .graphics_ver = 12,
> .display_ver = 13,
> .is_alderlake_n = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "alderlake_n"
> };
>
> @@ -436,6 +463,7 @@ static const struct intel_device_info intel_ats_m_info = {
> .is_dg2 = true,
> .has_4tile = true,
> .codename = "ats_m",
> + .blt_tiling = &gen12_atsm_blt_info,
> .has_flatccs = true,
> };
>
> @@ -583,6 +611,25 @@ out:
> return cache;
> }
>
> +/**
> + * intel_get_blt_info:
> + * @devid: pci device id
> + *
> + * Looks up the Blitter information about commands and tiling formats supported
> + * by the device.
> + *
> + * Returns:
> + * The associated blt_cmd_info, NULL if no such information is found
> + */
> +const struct blt_cmd_info *intel_get_blt_info(uint16_t devid)
> +{
> + const struct intel_device_info *dev_info;
> +
> + dev_info = intel_get_device_info(devid);
> +
> + return dev_info->blt_tiling;
> +}
> +
> /**
> * intel_gen:
> * @devid: pci device id
> diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
> index ed60b81c..10327050 100644
> --- a/tests/i915/gem_ccs.c
> +++ b/tests/i915/gem_ccs.c
> @@ -605,7 +605,7 @@ static void block_copy_test(int i915,
> return;
>
> for_each_tiling(tiling) {
> - if (!blt_supports_tiling(i915, tiling) ||
> + if (!blt_block_copy_supports_tiling(i915, tiling) ||
> (param.tiling >= 0 && param.tiling != tiling))
> continue;
>
> @@ -703,7 +703,7 @@ igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
> igt_fixture {
> i915 = drm_open_driver(DRIVER_INTEL);
> igt_require_gem(i915);
> - igt_require(AT_LEAST_GEN(intel_get_drm_devid(i915), 12) > 0);
> + igt_require(blt_has_block_copy(i915));
>
> query_info = gem_get_query_memory_regions(i915);
> igt_require(query_info);
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 2/6] lib: Update platform definitions with blitter information
2022-12-28 16:41 ` Kamil Konieczny
@ 2023-01-03 9:17 ` Karolina Stolarek
2023-01-09 15:24 ` Zbigniew Kempczyński
1 sibling, 0 replies; 21+ messages in thread
From: Karolina Stolarek @ 2023-01-03 9:17 UTC (permalink / raw)
To: Kamil Konieczny; +Cc: igt-dev
Hi Kamil,
Thanks for your review.
On 28.12.2022 17:41, Kamil Konieczny wrote:
> Hi Karolina,
>
> On 2022-12-23 at 12:13:47 +0100, Karolina Stolarek wrote:
>> Update entries in intel_device_info to store information on
>> supported blitter commands and tiling formats. Add predicates
>> that check if block or fast copy are supported. Update block
>> copy tests to use the new checks.
>>
>> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
>
> Please put here list of Cc:
>
> Cc: Zbigniew Kempczynski <zbigniew.kempczynski@intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Will do in the next version
>> ---
>> lib/i915/i915_blt.c | 75 +++++++++++++++++++++++++++++++----------
>> lib/i915/i915_blt.h | 6 +++-
>> lib/intel_chipset.c | 1 -
>> lib/intel_chipset.h | 4 +++
>> lib/intel_device_info.c | 47 ++++++++++++++++++++++++++
>> tests/i915/gem_ccs.c | 4 +--
>> 6 files changed, 115 insertions(+), 22 deletions(-)
>>
>> diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
>> index 6db135d1..00cf7470 100644
>> --- a/lib/i915/i915_blt.c
>> +++ b/lib/i915/i915_blt.c
>> @@ -208,34 +208,73 @@ bool blt_supports_compression(int i915)
>> }
>>
>> /**
>> - * blt_supports_tiling:
>> + * blt_has_block_copy
>> * @i915: drm fd
>> - * @tiling: tiling id
>> *
>> - * Function checks if blitter supports @tiling on @i915 device.
>> + * Check if block copy is supported by @i915 device
>> *
>> * Returns:
>> * true if it does, false otherwise.
>> */
>> -bool blt_supports_tiling(int i915, enum blt_tiling_type tiling)
>> +bool blt_has_block_copy(int i915)
>> {
>> - uint32_t devid = intel_get_drm_devid(i915);
>> + const struct blt_cmd_info
>> + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
>>
>> - if (tiling == T_XMAJOR) {
>> - if (IS_TIGERLAKE(devid) || IS_DG1(devid))
>> - return false;
>> - else
>> - return true;
>> - }
>> + return blt_supports_command(blt_info, XY_BLOCK_COPY);
>> +}
>>
>> - if (tiling == T_YMAJOR) {
>> - if (IS_TIGERLAKE(devid) || IS_DG1(devid))
>> - return true;
>> - else
>> - return false;
>> - }
>> +/**
>> + * blt_has_fast_copy
>> + * @i915: drm fd
>> + *
>> + * Check if fast copy is supported by @i915 device
>> + *
>> + * Returns:
>> + * true if it does, false otherwise.
>> + */
>> +bool blt_has_fast_copy(int i915)
>> +{
>> + const struct blt_cmd_info
>> + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
>> +
>> + return blt_supports_command(blt_info, XY_FAST_COPY);
>> +}
>> +
>> +/**
>> + * blt_fast_copy_supports_tiling
>> + * @i915: drm fd
>> + * @tiling: tiling format
>> + *
>> + * Check if fast copy provided by @i915 device supports @tiling format
>> + *
>> + * Returns:
>> + * true if it does, false otherwise.
>> + */
>> +bool blt_fast_copy_supports_tiling(int i915, enum blt_tiling_type tiling)
>> +{
>> + const struct blt_cmd_info
>> + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
>> +
>> + return blt_cmd_supports_tiling(blt_info, XY_FAST_COPY, tiling);
>> +}
>> +
>> +/**
>> + * blt_block_copy_supports_tiling
>> + * @i915: drm fd
>> + * @tiling: tiling format
>> + *
>> + * Check if block copy provided by @i915 device supports @tiling format
>> + *
>> + * Returns:
>> + * true if it does, false otherwise.
>> + */
>> +bool blt_block_copy_supports_tiling(int i915, enum blt_tiling_type tiling)
>> +{
>> + const struct blt_cmd_info
>> + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
>>
>> - return true;
>> + return blt_cmd_supports_tiling(blt_info, XY_BLOCK_COPY, tiling);
>> }
>>
>> static int __block_tiling(enum blt_tiling_type tiling)
>> diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
>> index 8fa480b8..3730c7c0 100644
>> --- a/lib/i915/i915_blt.h
>> +++ b/lib/i915/i915_blt.h
>> @@ -158,7 +158,11 @@ struct blt_ctrl_surf_copy_data {
>> };
>>
>> bool blt_supports_compression(int i915);
>> -bool blt_supports_tiling(int i915, enum blt_tiling_type tiling);
>> +
>> +bool blt_has_block_copy(int i915);
>> +bool blt_has_fast_copy(int i915);
>> +bool blt_fast_copy_supports_tiling(int i915, enum blt_tiling_type tiling);
>> +bool blt_block_copy_supports_tiling(int i915, enum blt_tiling_type tiling);
>>
>> uint64_t emit_blt_block_copy(int i915,
>> uint64_t ahnd,
>> diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
>> index efb6f177..4ac067df 100644
>> --- a/lib/intel_chipset.c
>> +++ b/lib/intel_chipset.c
>> @@ -41,7 +41,6 @@
>> #include "drmtest.h"
>> #include "intel_chipset.h"
>> #include "igt_core.h"
>> -
> - ^
>
> Please do not make unrelated changes in lib (here line was deleted).
Whoops, didn't mean to add this in, sorry!
>> /**
>> * SECTION:intel_chipset
>> * @short_description: Feature macros and chipset helpers
>> diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
>> index 9b39472a..a9801b28 100644
>> --- a/lib/intel_chipset.h
>> +++ b/lib/intel_chipset.h
>> @@ -31,6 +31,8 @@
>> #include <pciaccess.h>
>> #include <stdbool.h>
>>
>> +#include "i915/intel_blt_info.h"
>> +
>
> Imho this is a little too big change.
The only way to make it smaller is to add the field in one commit and
update intel_device_info definitions later. The latter change is still
being quite big, so I'm not sure if it's worth it.
>
>> #define BIT(x) (1ul <<(x))
>>
>> struct pci_device *intel_get_pci_device(void);
>> @@ -86,11 +88,13 @@ struct intel_device_info {
>> bool is_alderlake_p : 1;
>> bool is_alderlake_n : 1;
>> bool is_meteorlake : 1;
>> + const struct blt_cmd_info *blt_tiling;
>
> I would expect here to have bits for supported copy commands
> like has_xy_block_copy, has_xy_src_block_copy, has_xy_fast_copy
> and other.
We could have many, many more of these commands, like 10 or more. I'd
keep it hidden behind in a lib. Checks if a specific command is
supported are added in the next patch of the series.
> At the end of lib there are macros like HAS_FLATCCS(devid)
> so there could be added new ones like HAS_XY_FAST_COPY(devid) >
> You added comment at your first patch 1/6 that YFmajor tiling
> is supported only for gen9 and only for specific blt command (fast copy),
> so imho it adds too many complicated info here. I would prefer to
> keep that in blt library, not here.
I'm sorry, but I don't follow -- how does it add information about it
here? Do you mean importing enums such as that for tiling? If so, I
agree, it's not ideal. But even now we're polluting this lib with tiling
info (see has_4tile field) where this is more explicit than what I propose.
All the best,
Karolina
>
> Regards,
> Kamil
>
>> const char *codename;
>> };
>>
>> const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
>>
>> +const struct blt_cmd_info *intel_get_blt_info(uint16_t devid) __attribute__((pure));
>> unsigned intel_gen(uint16_t devid) __attribute__((pure));
>> unsigned intel_graphics_ver(uint16_t devid) __attribute__((pure));
>> unsigned intel_display_ver(uint16_t devid) __attribute__((pure));
>> diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
>> index 68dd17ee..ad9dffd8 100644
>> --- a/lib/intel_device_info.c
>> +++ b/lib/intel_device_info.c
>> @@ -145,6 +145,7 @@ static const struct intel_device_info intel_sandybridge_info = {
>> .graphics_ver = 6,
>> .display_ver = 6,
>> .is_sandybridge = true,
>> + .blt_tiling = &pre_gen8_blt_info,
>> .codename = "sandybridge"
>> };
>> static const struct intel_device_info intel_sandybridge_m_info = {
>> @@ -152,6 +153,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
>> .display_ver = 6,
>> .is_mobile = true,
>> .is_sandybridge = true,
>> + .blt_tiling = &pre_gen8_blt_info,
>> .codename = "sandybridge"
>> };
>>
>> @@ -159,6 +161,7 @@ static const struct intel_device_info intel_ivybridge_info = {
>> .graphics_ver = 7,
>> .display_ver = 7,
>> .is_ivybridge = true,
>> + .blt_tiling = &pre_gen8_blt_info,
>> .codename = "ivybridge"
>> };
>> static const struct intel_device_info intel_ivybridge_m_info = {
>> @@ -166,6 +169,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
>> .display_ver = 7,
>> .is_mobile = true,
>> .is_ivybridge = true,
>> + .blt_tiling = &pre_gen8_blt_info,
>> .codename = "ivybridge"
>> };
>>
>> @@ -173,6 +177,7 @@ static const struct intel_device_info intel_valleyview_info = {
>> .graphics_ver = 7,
>> .display_ver = 7,
>> .is_valleyview = true,
>> + .blt_tiling = &pre_gen8_blt_info,
>> .codename = "valleyview"
>> };
>>
>> @@ -180,6 +185,7 @@ static const struct intel_device_info intel_valleyview_info = {
>> .graphics_ver = 7, \
>> .display_ver = 7, \
>> .is_haswell = true, \
>> + .blt_tiling = &pre_gen8_blt_info, \
>> .codename = "haswell"
>>
>> static const struct intel_device_info intel_haswell_gt1_info = {
>> @@ -201,6 +207,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
>> .graphics_ver = 8, \
>> .display_ver = 8, \
>> .is_broadwell = true, \
>> + .blt_tiling = &gen8_blt_info, \
>> .codename = "broadwell"
>>
>> static const struct intel_device_info intel_broadwell_gt1_info = {
>> @@ -226,12 +233,14 @@ static const struct intel_device_info intel_cherryview_info = {
>> .graphics_ver = 8,
>> .display_ver = 8,
>> .is_cherryview = true,
>> + .blt_tiling = &gen8_blt_info,
>> .codename = "cherryview"
>> };
>>
>> #define SKYLAKE_FIELDS \
>> .graphics_ver = 9, \
>> .display_ver = 9, \
>> + .blt_tiling = &gen11_blt_info, \
>> .codename = "skylake", \
>> .is_skylake = true
>>
>> @@ -259,6 +268,7 @@ static const struct intel_device_info intel_broxton_info = {
>> .graphics_ver = 9,
>> .display_ver = 9,
>> .is_broxton = true,
>> + .blt_tiling = &gen11_blt_info,
>> .codename = "broxton"
>> };
>>
>> @@ -266,6 +276,7 @@ static const struct intel_device_info intel_broxton_info = {
>> .graphics_ver = 9, \
>> .display_ver = 9, \
>> .is_kabylake = true, \
>> + .blt_tiling = &gen11_blt_info, \
>> .codename = "kabylake"
>>
>> static const struct intel_device_info intel_kabylake_gt1_info = {
>> @@ -292,6 +303,7 @@ static const struct intel_device_info intel_geminilake_info = {
>> .graphics_ver = 9,
>> .display_ver = 9,
>> .is_geminilake = true,
>> + .blt_tiling = &gen11_blt_info,
>> .codename = "geminilake"
>> };
>>
>> @@ -299,6 +311,7 @@ static const struct intel_device_info intel_geminilake_info = {
>> .graphics_ver = 9, \
>> .display_ver = 9, \
>> .is_coffeelake = true, \
>> + .blt_tiling = &gen11_blt_info, \
>> .codename = "coffeelake"
>>
>> static const struct intel_device_info intel_coffeelake_gt1_info = {
>> @@ -320,6 +333,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
>> .graphics_ver = 9, \
>> .display_ver = 9, \
>> .is_cometlake = true, \
>> + .blt_tiling = &gen11_blt_info, \
>> .codename = "cometlake"
>>
>> static const struct intel_device_info intel_cometlake_gt1_info = {
>> @@ -336,6 +350,7 @@ static const struct intel_device_info intel_cannonlake_info = {
>> .graphics_ver = 10,
>> .display_ver = 10,
>> .is_cannonlake = true,
>> + .blt_tiling = &gen11_blt_info,
>> .codename = "cannonlake"
>> };
>>
>> @@ -343,6 +358,7 @@ static const struct intel_device_info intel_icelake_info = {
>> .graphics_ver = 11,
>> .display_ver = 11,
>> .is_icelake = true,
>> + .blt_tiling = &gen11_blt_info,
>> .codename = "icelake"
>> };
>>
>> @@ -350,6 +366,7 @@ static const struct intel_device_info intel_elkhartlake_info = {
>> .graphics_ver = 11,
>> .display_ver = 11,
>> .is_elkhartlake = true,
>> + .blt_tiling = &gen11_blt_info,
>> .codename = "elkhartlake"
>> };
>>
>> @@ -357,6 +374,7 @@ static const struct intel_device_info intel_jasperlake_info = {
>> .graphics_ver = 11,
>> .display_ver = 11,
>> .is_jasperlake = true,
>> + .blt_tiling = &gen11_blt_info,
>> .codename = "jasperlake"
>> };
>>
>> @@ -364,6 +382,7 @@ static const struct intel_device_info intel_tigerlake_gt1_info = {
>> .graphics_ver = 12,
>> .display_ver = 12,
>> .is_tigerlake = true,
>> + .blt_tiling = &gen12_blt_info,
>> .codename = "tigerlake",
>> .gt = 1,
>> };
>> @@ -372,6 +391,7 @@ static const struct intel_device_info intel_tigerlake_gt2_info = {
>> .graphics_ver = 12,
>> .display_ver = 12,
>> .is_tigerlake = true,
>> + .blt_tiling = &gen12_blt_info,
>> .codename = "tigerlake",
>> .gt = 2,
>> };
>> @@ -380,6 +400,7 @@ static const struct intel_device_info intel_rocketlake_info = {
>> .graphics_ver = 12,
>> .display_ver = 12,
>> .is_rocketlake = true,
>> + .blt_tiling = &gen12_blt_info,
>> .codename = "rocketlake"
>> };
>>
>> @@ -388,6 +409,7 @@ static const struct intel_device_info intel_dg1_info = {
>> .graphics_rel = 10,
>> .display_ver = 12,
>> .is_dg1 = true,
>> + .blt_tiling = &gen12_blt_info,
>> .codename = "dg1"
>> };
>>
>> @@ -398,6 +420,7 @@ static const struct intel_device_info intel_dg2_info = {
>> .has_4tile = true,
>> .is_dg2 = true,
>> .codename = "dg2",
>> + .blt_tiling = &gen12_dg2_blt_info,
>> .has_flatccs = true,
>> };
>>
>> @@ -405,6 +428,7 @@ static const struct intel_device_info intel_alderlake_s_info = {
>> .graphics_ver = 12,
>> .display_ver = 12,
>> .is_alderlake_s = true,
>> + .blt_tiling = &gen12_blt_info,
>> .codename = "alderlake_s"
>> };
>>
>> @@ -412,6 +436,7 @@ static const struct intel_device_info intel_raptorlake_s_info = {
>> .graphics_ver = 12,
>> .display_ver = 12,
>> .is_raptorlake_s = true,
>> + .blt_tiling = &gen12_blt_info,
>> .codename = "raptorlake_s"
>> };
>>
>> @@ -419,6 +444,7 @@ static const struct intel_device_info intel_alderlake_p_info = {
>> .graphics_ver = 12,
>> .display_ver = 13,
>> .is_alderlake_p = true,
>> + .blt_tiling = &gen12_blt_info,
>> .codename = "alderlake_p"
>> };
>>
>> @@ -426,6 +452,7 @@ static const struct intel_device_info intel_alderlake_n_info = {
>> .graphics_ver = 12,
>> .display_ver = 13,
>> .is_alderlake_n = true,
>> + .blt_tiling = &gen12_blt_info,
>> .codename = "alderlake_n"
>> };
>>
>> @@ -436,6 +463,7 @@ static const struct intel_device_info intel_ats_m_info = {
>> .is_dg2 = true,
>> .has_4tile = true,
>> .codename = "ats_m",
>> + .blt_tiling = &gen12_atsm_blt_info,
>> .has_flatccs = true,
>> };
>>
>> @@ -583,6 +611,25 @@ out:
>> return cache;
>> }
>>
>> +/**
>> + * intel_get_blt_info:
>> + * @devid: pci device id
>> + *
>> + * Looks up the Blitter information about commands and tiling formats supported
>> + * by the device.
>> + *
>> + * Returns:
>> + * The associated blt_cmd_info, NULL if no such information is found
>> + */
>> +const struct blt_cmd_info *intel_get_blt_info(uint16_t devid)
>> +{
>> + const struct intel_device_info *dev_info;
>> +
>> + dev_info = intel_get_device_info(devid);
>> +
>> + return dev_info->blt_tiling;
>> +}
>> +
>> /**
>> * intel_gen:
>> * @devid: pci device id
>> diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
>> index ed60b81c..10327050 100644
>> --- a/tests/i915/gem_ccs.c
>> +++ b/tests/i915/gem_ccs.c
>> @@ -605,7 +605,7 @@ static void block_copy_test(int i915,
>> return;
>>
>> for_each_tiling(tiling) {
>> - if (!blt_supports_tiling(i915, tiling) ||
>> + if (!blt_block_copy_supports_tiling(i915, tiling) ||
>> (param.tiling >= 0 && param.tiling != tiling))
>> continue;
>>
>> @@ -703,7 +703,7 @@ igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
>> igt_fixture {
>> i915 = drm_open_driver(DRIVER_INTEL);
>> igt_require_gem(i915);
>> - igt_require(AT_LEAST_GEN(intel_get_drm_devid(i915), 12) > 0);
>> + igt_require(blt_has_block_copy(i915));
>>
>> query_info = gem_get_query_memory_regions(i915);
>> igt_require(query_info);
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 1/6] i915/lib: Add new library for blitter and tiling formats
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 1/6] i915/lib: Add new library for blitter and tiling formats Karolina Stolarek
@ 2023-01-09 12:49 ` Zbigniew Kempczyński
2023-01-10 6:55 ` Karolina Stolarek
0 siblings, 1 reply; 21+ messages in thread
From: Zbigniew Kempczyński @ 2023-01-09 12:49 UTC (permalink / raw)
To: Karolina Stolarek; +Cc: igt-dev
On Fri, Dec 23, 2022 at 12:13:46PM +0100, Karolina Stolarek wrote:
> Add structs to describe what blitter commands and tiling formats
> are supported per platform. Add a generic functions that check
> if a specific blitter command or tiling format is supported.
> Move blt_tiling enum to the newely created library and update
> its definition. Update i915_blt and block copy tests to reflect
> that change.
>
> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
> ---
> .../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
> lib/i915/i915_blt.c | 31 +--
> lib/i915/i915_blt.h | 14 +-
> lib/i915/intel_blt_info.c | 241 ++++++++++++++++++
> lib/i915/intel_blt_info.h | 98 +++++++
> lib/meson.build | 1 +
> tests/i915/gem_ccs.c | 15 +-
> tests/i915/gem_lmem_swapping.c | 2 +-
> 8 files changed, 360 insertions(+), 43 deletions(-)
> create mode 100644 lib/i915/intel_blt_info.c
> create mode 100644 lib/i915/intel_blt_info.h
>
> diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> index 102c8a89..24ee17fc 100644
> --- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> +++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> @@ -59,6 +59,7 @@
> </chapter>
> <chapter>
> <title>igt/i915 API Reference</title>
> + <xi:include href="xml/intel_blt_info.xml"/>
> <xi:include href="xml/gem_create.xml"/>
> <xi:include href="xml/gem_context.xml"/>
> <xi:include href="xml/gem_engine_topology.xml"/>
> diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
> index 54193565..6db135d1 100644
> --- a/lib/i915/i915_blt.c
> +++ b/lib/i915/i915_blt.c
> @@ -217,7 +217,7 @@ bool blt_supports_compression(int i915)
> * Returns:
> * true if it does, false otherwise.
> */
> -bool blt_supports_tiling(int i915, enum blt_tiling tiling)
> +bool blt_supports_tiling(int i915, enum blt_tiling_type tiling)
> {
> uint32_t devid = intel_get_drm_devid(i915);
>
> @@ -238,28 +238,7 @@ bool blt_supports_tiling(int i915, enum blt_tiling tiling)
> return true;
> }
>
> -/**
> - * blt_tiling_name:
> - * @tiling: tiling id
> - *
> - * Returns:
> - * name of @tiling passed. Useful to build test names.
> - */
> -const char *blt_tiling_name(enum blt_tiling tiling)
> -{
> - switch (tiling) {
> - case T_LINEAR: return "linear";
> - case T_XMAJOR: return "xmajor";
> - case T_YMAJOR: return "ymajor";
> - case T_TILE4: return "tile4";
> - case T_TILE64: return "tile64";
> - }
> -
> - igt_warn("invalid tiling passed: %d\n", tiling);
> - return NULL;
> -}
> -
> -static int __block_tiling(enum blt_tiling tiling)
> +static int __block_tiling(enum blt_tiling_type tiling)
> {
> switch (tiling) {
> case T_LINEAR: return 0;
> @@ -267,6 +246,9 @@ static int __block_tiling(enum blt_tiling tiling)
> case T_YMAJOR: return 1;
> case T_TILE4: return 2;
> case T_TILE64: return 3;
> + /* type only supported in gen9 fast copy */
> + case T_YFMAJOR:
> + break;
> }
>
> igt_warn("invalid tiling passed: %d\n", tiling);
> @@ -891,13 +873,14 @@ struct gen12_fast_copy_data {
> } dw09;
> };
>
> -static int __fast_tiling(enum blt_tiling tiling)
> +static int __fast_tiling(enum blt_tiling_type tiling)
> {
> switch (tiling) {
> case T_LINEAR: return 0;
> case T_XMAJOR: return 1;
> case T_YMAJOR: return 2;
> case T_TILE4: return 2;
> + case T_YFMAJOR: return 2;
> case T_TILE64: return 3;
> }
> return 0;
> diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
> index 34db9bb9..8fa480b8 100644
> --- a/lib/i915/i915_blt.h
> +++ b/lib/i915/i915_blt.h
> @@ -47,6 +47,7 @@
> #include <malloc.h>
> #include "drm.h"
> #include "igt.h"
> +#include "intel_blt_info.h"
>
> #define CCS_RATIO 256
>
> @@ -59,14 +60,6 @@ enum blt_color_depth {
> CD_128bit,
> };
>
> -enum blt_tiling {
> - T_LINEAR,
> - T_XMAJOR,
> - T_YMAJOR,
> - T_TILE4,
> - T_TILE64,
> -};
> -
> enum blt_compression {
> COMPRESSION_DISABLED,
> COMPRESSION_ENABLED,
> @@ -83,7 +76,7 @@ struct blt_copy_object {
> uint32_t region;
> uint64_t size;
> uint8_t mocs;
> - enum blt_tiling tiling;
> + enum blt_tiling_type tiling;
> enum blt_compression compression; /* BC only */
> enum blt_compression_type compression_type; /* BC only */
> uint32_t pitch;
> @@ -165,8 +158,7 @@ struct blt_ctrl_surf_copy_data {
> };
>
> bool blt_supports_compression(int i915);
> -bool blt_supports_tiling(int i915, enum blt_tiling tiling);
> -const char *blt_tiling_name(enum blt_tiling tiling);
> +bool blt_supports_tiling(int i915, enum blt_tiling_type tiling);
>
> uint64_t emit_blt_block_copy(int i915,
> uint64_t ahnd,
> diff --git a/lib/i915/intel_blt_info.c b/lib/i915/intel_blt_info.c
> new file mode 100644
> index 00000000..2f54d1b4
> --- /dev/null
> +++ b/lib/i915/intel_blt_info.c
> @@ -0,0 +1,241 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include "intel_blt_info.h"
> +
> +#define BLT_STR_MAX 200
> +#define TILE_STR_MAX 60
> +#define T_MAX_SHIFT 6
I think you can remove this define adding T_TILING_MAX in enum blt_tiling_type.
> +
> +#define BLT_INFO(_cmd, _tiling) { \
> + .blt_cmd_type = _cmd, \
> + .supported_tiling = _tiling \
> + }
> +
> +static const struct blt_tiling_info src_copy = BLT_INFO(SRC_COPY, T_LINEAR);
> +static const struct blt_tiling_info
> + pre_gen8_xy_src_copy = BLT_INFO(XY_SRC_COPY, T_LINEAR | T_XMAJOR);
I wondered to have enum blt_tiling_type incrementing without gaps to introduce
#define BLT_MASK(x) (1 << (x))
then:
static const struct blt_tiling_info
pre_gen8_xy_src_copy = BLT_INFO(XY_SRC_COPY,
BLT_MASK(T_LINEAR) |
BLT_MASK(T_XMAJOR));
and so on. Initialization is not too comfortable but it is in .c file,
so it is encapsulated here.
> +static const struct blt_tiling_info
> + gen8_xy_src_copy = BLT_INFO(XY_SRC_COPY,
> + T_LINEAR | T_XMAJOR | T_YMAJOR);
> +static const struct blt_tiling_info
> + gen11_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
> + T_LINEAR | T_YMAJOR |
> + T_YFMAJOR | T_TILE64);
> +static const struct blt_tiling_info
> + gen12_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
> + T_LINEAR | T_YMAJOR |
> + T_TILE4 | T_TILE64);
> +static const struct blt_tiling_info
> + dg2_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
> + T_LINEAR | T_XMAJOR |
> + T_TILE4 | T_TILE64);
> +static const struct blt_tiling_info
> + atsm_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
> + T_LINEAR | T_TILE4 |
> + T_TILE64);
> +static const struct blt_tiling_info
> + gen12_xy_block_copy = BLT_INFO(XY_BLOCK_COPY,
> + T_LINEAR | T_YMAJOR);
> +static const struct blt_tiling_info
> + dg2_xy_block_copy = BLT_INFO(XY_BLOCK_COPY,
> + T_LINEAR | T_XMAJOR |
> + T_TILE4 | T_TILE64);
> +static const struct blt_tiling_info
> + atsm_xy_block_copy = BLT_INFO(XY_BLOCK_COPY,
> + T_LINEAR | T_XMAJOR |
> + T_TILE4 | T_TILE64);
> +
> +const struct blt_cmd_info pre_gen8_blt_info = {
> + .supported_tiling = {
> + [SRC_COPY] = &src_copy,
> + [XY_SRC_COPY] = &pre_gen8_xy_src_copy
> + }
> +};
> +
> +const struct blt_cmd_info gen8_blt_info = {
> + .supported_tiling = {
> + [XY_SRC_COPY] = &gen8_xy_src_copy,
> + }
> +};
> +
> +const struct blt_cmd_info gen11_blt_info = {
> + .supported_tiling = {
> + [XY_SRC_COPY] = &gen8_xy_src_copy,
> + [XY_FAST_COPY] = &gen11_xy_fast_copy,
> + }
> +};
> +
> +const struct blt_cmd_info gen12_blt_info = {
> + .supported_tiling = {
> + [XY_SRC_COPY] = &gen8_xy_src_copy,
> + [XY_FAST_COPY] = &gen12_xy_fast_copy,
> + [XY_BLOCK_COPY] = &gen12_xy_block_copy,
> + }
> +};
> +
> +const struct blt_cmd_info gen12_dg2_blt_info = {
> + .supported_tiling = {
> + [XY_SRC_COPY] = &gen8_xy_src_copy,
> + [XY_FAST_COPY] = &dg2_xy_fast_copy,
> + [XY_BLOCK_COPY] = &dg2_xy_block_copy,
> + }
> +};
> +
> +const struct blt_cmd_info gen12_atsm_blt_info = {
> + .supported_tiling = {
> + [XY_SRC_COPY] = &gen8_xy_src_copy,
> + [XY_FAST_COPY] = &atsm_xy_fast_copy,
> + [XY_BLOCK_COPY] = &atsm_xy_block_copy,
> + }
> +};
This looks good, we can individually configure supported blt
instructions.
> +
> +/**
> + * blt_tiling_name:
> + * @tiling: tiling id
> + *
> + * Returns:
> + * name of @tiling passed. Useful to build test names.
> + */
> +const char *blt_tiling_name(enum blt_tiling_type tiling)
> +{
> + switch (tiling) {
> + case T_LINEAR: return "linear";
> + case T_XMAJOR: return "xmajor";
> + case T_YMAJOR: return "ymajor";
> + case T_TILE4: return "tile4";
> + case T_TILE64: return "tile64";
> + case T_YFMAJOR: return "yfmajor";
> + default: return NULL;
> + }
> +}
> +
> +/**
> + * blt_supports_command:
> + * @info: Blitter command info struct
> + * @cmd: Blitter command enum
> + *
> + * Checks if @info has an entry of supported tiling formats for @cmd command.
> + *
> + * Returns: true if it does, false otherwise
> + */
> +bool blt_supports_command(const struct blt_cmd_info *info,
> + enum blt_cmd_type cmd)
> +{
> + igt_require_f(info, "No config found for the platform\n");
> +
> + return info->supported_tiling[cmd];
> +}
> +
> +/**
> + * blt_cmd_supports_tiling:
> + * @info: Blitter command info struct
> + * @cmd: Blitter command enum
> + * @tiling: tiling format enum
> + *
> + * Checks if a @cmd entry of @info lists @tiling. It also returns false if
> + * no information about the command is stored.
> + *
> + * Returns: true if it does, false otherwise
> + */
> +bool blt_cmd_supports_tiling(const struct blt_cmd_info *info,
> + enum blt_cmd_type cmd,
> + enum blt_tiling_type tiling)
> +{
> + struct blt_tiling_info const *tile_config;
> +
> + if (!info)
> + return false;
> +
> + tile_config = info->supported_tiling[cmd];
> +
> + /* no config means no support for that tiling */
> + if (!tile_config)
> + return false;
> +
> + return tile_config->supported_tiling & tiling;
> +}
> +
> +static const char *blt_cmd_name(enum blt_cmd_type cmd)
> +{
> + switch (cmd) {
> + case SRC_COPY: return "SRC_COPY_BLT";
> + case XY_SRC_COPY: return "XY_SRC_COPY_BLT";
> + case XY_FAST_COPY: return "XY_FAST_COPY_BLT";
> + case XY_BLOCK_COPY: return "XY_BLOCK_COPY_BLT";
> + default: return NULL;
> + }
> +}
> +
> +/* Info dump functions */
> +
> +static void append_tile(uint32_t tile, char *tile_str)
> +{
> + char const *tile_name;
> +
> + if (tile) {
> + tile_name = blt_tiling_name(tile);
> + snprintf(tile_str + strlen(tile_str), strlen(tile_name) + 2, "%s ", tile_name);
> + }
> +}
> +
> +static void get_tiling_info(struct blt_cmd_info const *info, enum blt_cmd_type type, char *tile_str)
> +{
> + uint32_t mask;
> + struct blt_tiling_info const *tiling = info->supported_tiling[type];
> +
> + if (tiling) {
> + for (int i = 0; i < T_MAX_SHIFT; i++) {
> + mask = 1 << i;
> + append_tile(tiling->supported_tiling & mask, tile_str);
> + }
> + }
> +
> + tile_str[strlen(tile_str) - 1] = '\0';
> +}
> +
> +/**
> + * dump_devid_blt_info:
> + * @info: pointer to the Blitter command info struct
> + *
> + * Prints a list of supported commands with available tiling formats.
> + *
> + */
> +void blt_dump_blt_cmd_info(struct blt_cmd_info const *info)
> +{
> + char tiling_str[TILE_STR_MAX];
> + char ln_str[BLT_STR_MAX];
> + char const *blt_type_str;
> + const char *ln_intro = " * ";
> +
> + if (!info) {
> + igt_warn("No config available\n");
> + return;
> + }
> +
> + igt_info("Supported blitter commands:\n");
> +
> + for (int cmd = 0; cmd < __MAX_CMD; cmd++) {
> + if (info->supported_tiling[cmd]) {
> + memset(ln_str, '\0', sizeof(char) * BLT_STR_MAX);
> + memset(tiling_str, '\0', sizeof(char) * TILE_STR_MAX);
> +
> + blt_type_str = blt_cmd_name(cmd);
> +
> + snprintf(ln_str,
> + strlen(ln_intro) + strlen(blt_type_str) + 1,
> + "%s%s", ln_intro, blt_type_str);
> +
> + get_tiling_info(info, cmd, tiling_str);
> +
> + snprintf(ln_str + strlen(ln_str),
> + strlen(tiling_str) + 5,
> + " [%s]", tiling_str);
> +
> + igt_info("%s\n", ln_str);
> + }
> + }
> +}
Looks a little bit overengineered, can't you just use asprintf()?
> +
> diff --git a/lib/i915/intel_blt_info.h b/lib/i915/intel_blt_info.h
> new file mode 100644
> index 00000000..39fa5448
> --- /dev/null
> +++ b/lib/i915/intel_blt_info.h
> @@ -0,0 +1,98 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef BLT_TILING_H
> +#define BLT_TILING_H
> +
> +#include <stdbool.h>
> +#include <stddef.h>
> +#include <stdint.h>
> +#include "igt_core.h"
> +
> +/**
> + * SECTION:intel_blt_info
> + * @short_description: blitter library to query for available commands and tiling formats
> + * @title: Intel blitter info
> + * @include: intel_blt_info.h
> + *
> + * # Introduction
> + *
> + * When we do a blitter copy, a number of different tiling formats can be used.
> + * The list of available formats and commands varies between generations, in
> + * some cases even within the generation (e.g. block copy tiling formats offered
> + * by TGL vs DG2). Such information is required by different tests, so it's
> + * beneficial to store it in one place – in intel_blt_info, a blitter library
> + * that describes available commands with a list of supported tiling formats.
> + * They are encapsulated in static `blt_cmd_info` instances, each of them
> + * defined per generation or platforms.
> + *
> + * Tiling formats here are described by blt_tiling_type enum, which consists of
> + * bit flags, that can be combined:
> + * `.supported_tiling = T_LINEAR | T_XMAJOR | T_YMAJOR`
> + *
> + * Because of their non-linear nature, it is recommended to use
> + * #for_each_tiling() macro when writing tests that iterate over tiling formats.
> + *
> + * # Usage
> + *
> + * - blt_supports_command(info, cmd) - checks if a blt_cmd_type instance has an
> + * entry for the command
> + * - blt_cmd_supports_tiling(info, cmd, tiling) - checks if a tiling format is
> + * supported by the command. Can
> + * also handle the case when the
> + * command is not available on
> + * the platform.
> + *
> + * These general checks can be wrapped in a command or tiling specific
> + * check, provided by other libraries.
> + *
> + */
> +
> +enum blt_tiling_type {
> + T_LINEAR = (1),
> + T_XMAJOR = (1 << 1),
> + T_YMAJOR = (1 << 2),
> + T_TILE4 = (1 << 3),
> + T_TILE64 = (1 << 4),
> + T_YFMAJOR = (1 << 5),
> +};
What I don't like here is sparse enum. I would just want to have contigues
values and hide the implementation in bits to .c file.
--
Zbigniew
> +
> +enum blt_cmd_type {
> + SRC_COPY,
> + XY_SRC_COPY,
> + XY_FAST_COPY,
> + XY_BLOCK_COPY,
> + __MAX_CMD
> +};
> +
> +struct blt_tiling_info {
> + enum blt_cmd_type blt_cmd_type;
> + uint32_t supported_tiling;
> +};
> +
> +struct blt_cmd_info {
> + struct blt_tiling_info const *supported_tiling[__MAX_CMD];
> +};
> +
> +const struct blt_cmd_info pre_gen8_blt_info;
> +const struct blt_cmd_info gen8_blt_info;
> +const struct blt_cmd_info gen11_blt_info;
> +const struct blt_cmd_info gen12_blt_info;
> +const struct blt_cmd_info gen12_dg2_blt_info;
> +const struct blt_cmd_info gen12_atsm_blt_info;
> +
> +#define for_each_tiling(__tiling) \
> + for (__tiling = T_LINEAR; __tiling <= T_YFMAJOR; __tiling = __tiling << 1)
> +
> +bool blt_supports_command(const struct blt_cmd_info *info,
> + enum blt_cmd_type cmd);
> +bool blt_cmd_supports_tiling(const struct blt_cmd_info *info,
> + enum blt_cmd_type cmd,
> + enum blt_tiling_type tiling);
> +
> +void blt_dump_blt_cmd_info(struct blt_cmd_info const *info);
> +const char *blt_tiling_name(enum blt_tiling_type tiling);
> +
> +#endif // BLT_TILING_H
> diff --git a/lib/meson.build b/lib/meson.build
> index c79e3e95..2b2dbbca 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -11,6 +11,7 @@ lib_sources = [
> 'i915/gem_ring.c',
> 'i915/gem_mman.c',
> 'i915/gem_vm.c',
> + 'i915/intel_blt_info.c',
> 'i915/intel_decode.c',
> 'i915/intel_memory_region.c',
> 'i915/intel_mocs.c',
> diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
> index 751f65e6..ed60b81c 100644
> --- a/tests/i915/gem_ccs.c
> +++ b/tests/i915/gem_ccs.c
> @@ -46,7 +46,7 @@ struct test_config {
>
> static void set_object(struct blt_copy_object *obj,
> uint32_t handle, uint64_t size, uint32_t region,
> - uint8_t mocs, enum blt_tiling tiling,
> + uint8_t mocs, enum blt_tiling_type tiling,
> enum blt_compression compression,
> enum blt_compression_type compression_type)
> {
> @@ -108,7 +108,7 @@ static void set_surf_object(struct blt_ctrl_surf_copy_object *obj,
> static struct blt_copy_object *
> create_object(int i915, uint32_t region,
> uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs,
> - enum blt_tiling tiling,
> + enum blt_tiling_type tiling,
> enum blt_compression compression,
> enum blt_compression_type compression_type,
> bool create_mapping)
> @@ -374,7 +374,7 @@ static void block_copy(int i915,
> const intel_ctx_t *ctx,
> const struct intel_execution_engine2 *e,
> uint32_t region1, uint32_t region2,
> - enum blt_tiling mid_tiling,
> + enum blt_tiling_type mid_tiling,
> const struct test_config *config)
> {
> struct blt_copy_data blt = {};
> @@ -492,7 +492,7 @@ static void block_multicopy(int i915,
> const intel_ctx_t *ctx,
> const struct intel_execution_engine2 *e,
> uint32_t region1, uint32_t region2,
> - enum blt_tiling mid_tiling,
> + enum blt_tiling_type mid_tiling,
> const struct test_config *config)
> {
> struct blt_copy3_data blt3 = {};
> @@ -581,7 +581,7 @@ static const struct {
> const char *suffix;
> void (*copyfn)(int, const intel_ctx_t *,
> const struct intel_execution_engine2 *,
> - uint32_t, uint32_t, enum blt_tiling,
> + uint32_t, uint32_t, enum blt_tiling_type,
> const struct test_config *);
> } copyfns[] = {
> [BLOCK_COPY] = { "", block_copy },
> @@ -596,6 +596,7 @@ static void block_copy_test(int i915,
> {
> struct igt_collection *regions;
> const struct intel_execution_engine2 *e;
> + int tiling;
>
> if (config->compression && !blt_supports_compression(i915))
> return;
> @@ -603,7 +604,7 @@ static void block_copy_test(int i915,
> if (config->inplace && !config->compression)
> return;
>
> - for (int tiling = T_LINEAR; tiling <= T_TILE64; tiling++) {
> + for_each_tiling(tiling) {
> if (!blt_supports_tiling(i915, tiling) ||
> (param.tiling >= 0 && param.tiling != tiling))
> continue;
> @@ -663,7 +664,7 @@ static int opt_handler(int opt, int opt_index, void *data)
> igt_debug("Print surface info: %d\n", param.print_surface_info);
> break;
> case 't':
> - param.tiling = atoi(optarg);
> + param.tiling = 1 << atoi(optarg);
> igt_debug("Tiling: %d\n", param.tiling);
> break;
> case 'W':
> diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
> index 75121d41..9388d4de 100644
> --- a/tests/i915/gem_lmem_swapping.c
> +++ b/tests/i915/gem_lmem_swapping.c
> @@ -78,7 +78,7 @@ struct object {
>
> static void set_object(struct blt_copy_object *obj,
> uint32_t handle, uint64_t size, uint32_t region,
> - uint8_t mocs, enum blt_tiling tiling,
> + uint8_t mocs, enum blt_tiling_type tiling,
> enum blt_compression compression,
> enum blt_compression_type compression_type)
> {
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 2/6] lib: Update platform definitions with blitter information
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 2/6] lib: Update platform definitions with blitter information Karolina Stolarek
2022-12-28 16:41 ` Kamil Konieczny
@ 2023-01-09 15:20 ` Zbigniew Kempczyński
1 sibling, 0 replies; 21+ messages in thread
From: Zbigniew Kempczyński @ 2023-01-09 15:20 UTC (permalink / raw)
To: Karolina Stolarek; +Cc: igt-dev
On Fri, Dec 23, 2022 at 12:13:47PM +0100, Karolina Stolarek wrote:
> Update entries in intel_device_info to store information on
> supported blitter commands and tiling formats. Add predicates
> that check if block or fast copy are supported. Update block
> copy tests to use the new checks.
>
> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
> ---
> lib/i915/i915_blt.c | 75 +++++++++++++++++++++++++++++++----------
> lib/i915/i915_blt.h | 6 +++-
> lib/intel_chipset.c | 1 -
> lib/intel_chipset.h | 4 +++
> lib/intel_device_info.c | 47 ++++++++++++++++++++++++++
> tests/i915/gem_ccs.c | 4 +--
> 6 files changed, 115 insertions(+), 22 deletions(-)
>
> diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
> index 6db135d1..00cf7470 100644
> --- a/lib/i915/i915_blt.c
> +++ b/lib/i915/i915_blt.c
> @@ -208,34 +208,73 @@ bool blt_supports_compression(int i915)
> }
>
> /**
> - * blt_supports_tiling:
> + * blt_has_block_copy
> * @i915: drm fd
> - * @tiling: tiling id
> *
> - * Function checks if blitter supports @tiling on @i915 device.
> + * Check if block copy is supported by @i915 device
> *
> * Returns:
> * true if it does, false otherwise.
> */
> -bool blt_supports_tiling(int i915, enum blt_tiling_type tiling)
> +bool blt_has_block_copy(int i915)
> {
> - uint32_t devid = intel_get_drm_devid(i915);
> + const struct blt_cmd_info
> + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
>
> - if (tiling == T_XMAJOR) {
> - if (IS_TIGERLAKE(devid) || IS_DG1(devid))
> - return false;
> - else
> - return true;
> - }
> + return blt_supports_command(blt_info, XY_BLOCK_COPY);
> +}
>
> - if (tiling == T_YMAJOR) {
> - if (IS_TIGERLAKE(devid) || IS_DG1(devid))
> - return true;
> - else
> - return false;
> - }
> +/**
> + * blt_has_fast_copy
> + * @i915: drm fd
> + *
> + * Check if fast copy is supported by @i915 device
> + *
> + * Returns:
> + * true if it does, false otherwise.
> + */
> +bool blt_has_fast_copy(int i915)
> +{
> + const struct blt_cmd_info
> + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
> +
> + return blt_supports_command(blt_info, XY_FAST_COPY);
> +}
> +
> +/**
> + * blt_fast_copy_supports_tiling
> + * @i915: drm fd
> + * @tiling: tiling format
> + *
> + * Check if fast copy provided by @i915 device supports @tiling format
> + *
> + * Returns:
> + * true if it does, false otherwise.
> + */
> +bool blt_fast_copy_supports_tiling(int i915, enum blt_tiling_type tiling)
> +{
> + const struct blt_cmd_info
> + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
> +
> + return blt_cmd_supports_tiling(blt_info, XY_FAST_COPY, tiling);
> +}
> +
> +/**
> + * blt_block_copy_supports_tiling
> + * @i915: drm fd
> + * @tiling: tiling format
> + *
> + * Check if block copy provided by @i915 device supports @tiling format
> + *
> + * Returns:
> + * true if it does, false otherwise.
> + */
> +bool blt_block_copy_supports_tiling(int i915, enum blt_tiling_type tiling)
> +{
> + const struct blt_cmd_info
> + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
>
> - return true;
> + return blt_cmd_supports_tiling(blt_info, XY_BLOCK_COPY, tiling);
> }
>
> static int __block_tiling(enum blt_tiling_type tiling)
> diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
> index 8fa480b8..3730c7c0 100644
> --- a/lib/i915/i915_blt.h
> +++ b/lib/i915/i915_blt.h
> @@ -158,7 +158,11 @@ struct blt_ctrl_surf_copy_data {
> };
>
> bool blt_supports_compression(int i915);
> -bool blt_supports_tiling(int i915, enum blt_tiling_type tiling);
> +
> +bool blt_has_block_copy(int i915);
> +bool blt_has_fast_copy(int i915);
> +bool blt_fast_copy_supports_tiling(int i915, enum blt_tiling_type tiling);
> +bool blt_block_copy_supports_tiling(int i915, enum blt_tiling_type tiling);
>
> uint64_t emit_blt_block_copy(int i915,
> uint64_t ahnd,
> diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
> index efb6f177..4ac067df 100644
> --- a/lib/intel_chipset.c
> +++ b/lib/intel_chipset.c
> @@ -41,7 +41,6 @@
> #include "drmtest.h"
> #include "intel_chipset.h"
> #include "igt_core.h"
> -
> /**
> * SECTION:intel_chipset
> * @short_description: Feature macros and chipset helpers
> diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> index 9b39472a..a9801b28 100644
> --- a/lib/intel_chipset.h
> +++ b/lib/intel_chipset.h
> @@ -31,6 +31,8 @@
> #include <pciaccess.h>
> #include <stdbool.h>
>
> +#include "i915/intel_blt_info.h"
> +
> #define BIT(x) (1ul <<(x))
>
> struct pci_device *intel_get_pci_device(void);
> @@ -86,11 +88,13 @@ struct intel_device_info {
> bool is_alderlake_p : 1;
> bool is_alderlake_n : 1;
> bool is_meteorlake : 1;
> + const struct blt_cmd_info *blt_tiling;
Yes, this looks exactly I wanted to have.
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
--
Zbigniew
> const char *codename;
> };
>
> const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
>
> +const struct blt_cmd_info *intel_get_blt_info(uint16_t devid) __attribute__((pure));
> unsigned intel_gen(uint16_t devid) __attribute__((pure));
> unsigned intel_graphics_ver(uint16_t devid) __attribute__((pure));
> unsigned intel_display_ver(uint16_t devid) __attribute__((pure));
> diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> index 68dd17ee..ad9dffd8 100644
> --- a/lib/intel_device_info.c
> +++ b/lib/intel_device_info.c
> @@ -145,6 +145,7 @@ static const struct intel_device_info intel_sandybridge_info = {
> .graphics_ver = 6,
> .display_ver = 6,
> .is_sandybridge = true,
> + .blt_tiling = &pre_gen8_blt_info,
> .codename = "sandybridge"
> };
> static const struct intel_device_info intel_sandybridge_m_info = {
> @@ -152,6 +153,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
> .display_ver = 6,
> .is_mobile = true,
> .is_sandybridge = true,
> + .blt_tiling = &pre_gen8_blt_info,
> .codename = "sandybridge"
> };
>
> @@ -159,6 +161,7 @@ static const struct intel_device_info intel_ivybridge_info = {
> .graphics_ver = 7,
> .display_ver = 7,
> .is_ivybridge = true,
> + .blt_tiling = &pre_gen8_blt_info,
> .codename = "ivybridge"
> };
> static const struct intel_device_info intel_ivybridge_m_info = {
> @@ -166,6 +169,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
> .display_ver = 7,
> .is_mobile = true,
> .is_ivybridge = true,
> + .blt_tiling = &pre_gen8_blt_info,
> .codename = "ivybridge"
> };
>
> @@ -173,6 +177,7 @@ static const struct intel_device_info intel_valleyview_info = {
> .graphics_ver = 7,
> .display_ver = 7,
> .is_valleyview = true,
> + .blt_tiling = &pre_gen8_blt_info,
> .codename = "valleyview"
> };
>
> @@ -180,6 +185,7 @@ static const struct intel_device_info intel_valleyview_info = {
> .graphics_ver = 7, \
> .display_ver = 7, \
> .is_haswell = true, \
> + .blt_tiling = &pre_gen8_blt_info, \
> .codename = "haswell"
>
> static const struct intel_device_info intel_haswell_gt1_info = {
> @@ -201,6 +207,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
> .graphics_ver = 8, \
> .display_ver = 8, \
> .is_broadwell = true, \
> + .blt_tiling = &gen8_blt_info, \
> .codename = "broadwell"
>
> static const struct intel_device_info intel_broadwell_gt1_info = {
> @@ -226,12 +233,14 @@ static const struct intel_device_info intel_cherryview_info = {
> .graphics_ver = 8,
> .display_ver = 8,
> .is_cherryview = true,
> + .blt_tiling = &gen8_blt_info,
> .codename = "cherryview"
> };
>
> #define SKYLAKE_FIELDS \
> .graphics_ver = 9, \
> .display_ver = 9, \
> + .blt_tiling = &gen11_blt_info, \
> .codename = "skylake", \
> .is_skylake = true
>
> @@ -259,6 +268,7 @@ static const struct intel_device_info intel_broxton_info = {
> .graphics_ver = 9,
> .display_ver = 9,
> .is_broxton = true,
> + .blt_tiling = &gen11_blt_info,
> .codename = "broxton"
> };
>
> @@ -266,6 +276,7 @@ static const struct intel_device_info intel_broxton_info = {
> .graphics_ver = 9, \
> .display_ver = 9, \
> .is_kabylake = true, \
> + .blt_tiling = &gen11_blt_info, \
> .codename = "kabylake"
>
> static const struct intel_device_info intel_kabylake_gt1_info = {
> @@ -292,6 +303,7 @@ static const struct intel_device_info intel_geminilake_info = {
> .graphics_ver = 9,
> .display_ver = 9,
> .is_geminilake = true,
> + .blt_tiling = &gen11_blt_info,
> .codename = "geminilake"
> };
>
> @@ -299,6 +311,7 @@ static const struct intel_device_info intel_geminilake_info = {
> .graphics_ver = 9, \
> .display_ver = 9, \
> .is_coffeelake = true, \
> + .blt_tiling = &gen11_blt_info, \
> .codename = "coffeelake"
>
> static const struct intel_device_info intel_coffeelake_gt1_info = {
> @@ -320,6 +333,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
> .graphics_ver = 9, \
> .display_ver = 9, \
> .is_cometlake = true, \
> + .blt_tiling = &gen11_blt_info, \
> .codename = "cometlake"
>
> static const struct intel_device_info intel_cometlake_gt1_info = {
> @@ -336,6 +350,7 @@ static const struct intel_device_info intel_cannonlake_info = {
> .graphics_ver = 10,
> .display_ver = 10,
> .is_cannonlake = true,
> + .blt_tiling = &gen11_blt_info,
> .codename = "cannonlake"
> };
>
> @@ -343,6 +358,7 @@ static const struct intel_device_info intel_icelake_info = {
> .graphics_ver = 11,
> .display_ver = 11,
> .is_icelake = true,
> + .blt_tiling = &gen11_blt_info,
> .codename = "icelake"
> };
>
> @@ -350,6 +366,7 @@ static const struct intel_device_info intel_elkhartlake_info = {
> .graphics_ver = 11,
> .display_ver = 11,
> .is_elkhartlake = true,
> + .blt_tiling = &gen11_blt_info,
> .codename = "elkhartlake"
> };
>
> @@ -357,6 +374,7 @@ static const struct intel_device_info intel_jasperlake_info = {
> .graphics_ver = 11,
> .display_ver = 11,
> .is_jasperlake = true,
> + .blt_tiling = &gen11_blt_info,
> .codename = "jasperlake"
> };
>
> @@ -364,6 +382,7 @@ static const struct intel_device_info intel_tigerlake_gt1_info = {
> .graphics_ver = 12,
> .display_ver = 12,
> .is_tigerlake = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "tigerlake",
> .gt = 1,
> };
> @@ -372,6 +391,7 @@ static const struct intel_device_info intel_tigerlake_gt2_info = {
> .graphics_ver = 12,
> .display_ver = 12,
> .is_tigerlake = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "tigerlake",
> .gt = 2,
> };
> @@ -380,6 +400,7 @@ static const struct intel_device_info intel_rocketlake_info = {
> .graphics_ver = 12,
> .display_ver = 12,
> .is_rocketlake = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "rocketlake"
> };
>
> @@ -388,6 +409,7 @@ static const struct intel_device_info intel_dg1_info = {
> .graphics_rel = 10,
> .display_ver = 12,
> .is_dg1 = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "dg1"
> };
>
> @@ -398,6 +420,7 @@ static const struct intel_device_info intel_dg2_info = {
> .has_4tile = true,
> .is_dg2 = true,
> .codename = "dg2",
> + .blt_tiling = &gen12_dg2_blt_info,
> .has_flatccs = true,
> };
>
> @@ -405,6 +428,7 @@ static const struct intel_device_info intel_alderlake_s_info = {
> .graphics_ver = 12,
> .display_ver = 12,
> .is_alderlake_s = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "alderlake_s"
> };
>
> @@ -412,6 +436,7 @@ static const struct intel_device_info intel_raptorlake_s_info = {
> .graphics_ver = 12,
> .display_ver = 12,
> .is_raptorlake_s = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "raptorlake_s"
> };
>
> @@ -419,6 +444,7 @@ static const struct intel_device_info intel_alderlake_p_info = {
> .graphics_ver = 12,
> .display_ver = 13,
> .is_alderlake_p = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "alderlake_p"
> };
>
> @@ -426,6 +452,7 @@ static const struct intel_device_info intel_alderlake_n_info = {
> .graphics_ver = 12,
> .display_ver = 13,
> .is_alderlake_n = true,
> + .blt_tiling = &gen12_blt_info,
> .codename = "alderlake_n"
> };
>
> @@ -436,6 +463,7 @@ static const struct intel_device_info intel_ats_m_info = {
> .is_dg2 = true,
> .has_4tile = true,
> .codename = "ats_m",
> + .blt_tiling = &gen12_atsm_blt_info,
> .has_flatccs = true,
> };
>
> @@ -583,6 +611,25 @@ out:
> return cache;
> }
>
> +/**
> + * intel_get_blt_info:
> + * @devid: pci device id
> + *
> + * Looks up the Blitter information about commands and tiling formats supported
> + * by the device.
> + *
> + * Returns:
> + * The associated blt_cmd_info, NULL if no such information is found
> + */
> +const struct blt_cmd_info *intel_get_blt_info(uint16_t devid)
> +{
> + const struct intel_device_info *dev_info;
> +
> + dev_info = intel_get_device_info(devid);
> +
> + return dev_info->blt_tiling;
> +}
> +
> /**
> * intel_gen:
> * @devid: pci device id
> diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
> index ed60b81c..10327050 100644
> --- a/tests/i915/gem_ccs.c
> +++ b/tests/i915/gem_ccs.c
> @@ -605,7 +605,7 @@ static void block_copy_test(int i915,
> return;
>
> for_each_tiling(tiling) {
> - if (!blt_supports_tiling(i915, tiling) ||
> + if (!blt_block_copy_supports_tiling(i915, tiling) ||
> (param.tiling >= 0 && param.tiling != tiling))
> continue;
>
> @@ -703,7 +703,7 @@ igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
> igt_fixture {
> i915 = drm_open_driver(DRIVER_INTEL);
> igt_require_gem(i915);
> - igt_require(AT_LEAST_GEN(intel_get_drm_devid(i915), 12) > 0);
> + igt_require(blt_has_block_copy(i915));
>
> query_info = gem_get_query_memory_regions(i915);
> igt_require(query_info);
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 2/6] lib: Update platform definitions with blitter information
2022-12-28 16:41 ` Kamil Konieczny
2023-01-03 9:17 ` Karolina Stolarek
@ 2023-01-09 15:24 ` Zbigniew Kempczyński
1 sibling, 0 replies; 21+ messages in thread
From: Zbigniew Kempczyński @ 2023-01-09 15:24 UTC (permalink / raw)
To: Kamil Konieczny, igt-dev, Karolina Stolarek
On Wed, Dec 28, 2022 at 05:41:41PM +0100, Kamil Konieczny wrote:
> Hi Karolina,
>
> On 2022-12-23 at 12:13:47 +0100, Karolina Stolarek wrote:
> > Update entries in intel_device_info to store information on
> > supported blitter commands and tiling formats. Add predicates
> > that check if block or fast copy are supported. Update block
> > copy tests to use the new checks.
> >
> > Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
>
> Please put here list of Cc:
>
> Cc: Zbigniew Kempczynski <zbigniew.kempczynski@intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
>
> > ---
> > lib/i915/i915_blt.c | 75 +++++++++++++++++++++++++++++++----------
> > lib/i915/i915_blt.h | 6 +++-
> > lib/intel_chipset.c | 1 -
> > lib/intel_chipset.h | 4 +++
> > lib/intel_device_info.c | 47 ++++++++++++++++++++++++++
> > tests/i915/gem_ccs.c | 4 +--
> > 6 files changed, 115 insertions(+), 22 deletions(-)
> >
> > diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
> > index 6db135d1..00cf7470 100644
> > --- a/lib/i915/i915_blt.c
> > +++ b/lib/i915/i915_blt.c
> > @@ -208,34 +208,73 @@ bool blt_supports_compression(int i915)
> > }
> >
> > /**
> > - * blt_supports_tiling:
> > + * blt_has_block_copy
> > * @i915: drm fd
> > - * @tiling: tiling id
> > *
> > - * Function checks if blitter supports @tiling on @i915 device.
> > + * Check if block copy is supported by @i915 device
> > *
> > * Returns:
> > * true if it does, false otherwise.
> > */
> > -bool blt_supports_tiling(int i915, enum blt_tiling_type tiling)
> > +bool blt_has_block_copy(int i915)
> > {
> > - uint32_t devid = intel_get_drm_devid(i915);
> > + const struct blt_cmd_info
> > + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
> >
> > - if (tiling == T_XMAJOR) {
> > - if (IS_TIGERLAKE(devid) || IS_DG1(devid))
> > - return false;
> > - else
> > - return true;
> > - }
> > + return blt_supports_command(blt_info, XY_BLOCK_COPY);
> > +}
> >
> > - if (tiling == T_YMAJOR) {
> > - if (IS_TIGERLAKE(devid) || IS_DG1(devid))
> > - return true;
> > - else
> > - return false;
> > - }
> > +/**
> > + * blt_has_fast_copy
> > + * @i915: drm fd
> > + *
> > + * Check if fast copy is supported by @i915 device
> > + *
> > + * Returns:
> > + * true if it does, false otherwise.
> > + */
> > +bool blt_has_fast_copy(int i915)
> > +{
> > + const struct blt_cmd_info
> > + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
> > +
> > + return blt_supports_command(blt_info, XY_FAST_COPY);
> > +}
> > +
> > +/**
> > + * blt_fast_copy_supports_tiling
> > + * @i915: drm fd
> > + * @tiling: tiling format
> > + *
> > + * Check if fast copy provided by @i915 device supports @tiling format
> > + *
> > + * Returns:
> > + * true if it does, false otherwise.
> > + */
> > +bool blt_fast_copy_supports_tiling(int i915, enum blt_tiling_type tiling)
> > +{
> > + const struct blt_cmd_info
> > + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
> > +
> > + return blt_cmd_supports_tiling(blt_info, XY_FAST_COPY, tiling);
> > +}
> > +
> > +/**
> > + * blt_block_copy_supports_tiling
> > + * @i915: drm fd
> > + * @tiling: tiling format
> > + *
> > + * Check if block copy provided by @i915 device supports @tiling format
> > + *
> > + * Returns:
> > + * true if it does, false otherwise.
> > + */
> > +bool blt_block_copy_supports_tiling(int i915, enum blt_tiling_type tiling)
> > +{
> > + const struct blt_cmd_info
> > + *blt_info = intel_get_blt_info(intel_get_drm_devid(i915));
> >
> > - return true;
> > + return blt_cmd_supports_tiling(blt_info, XY_BLOCK_COPY, tiling);
> > }
> >
> > static int __block_tiling(enum blt_tiling_type tiling)
> > diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
> > index 8fa480b8..3730c7c0 100644
> > --- a/lib/i915/i915_blt.h
> > +++ b/lib/i915/i915_blt.h
> > @@ -158,7 +158,11 @@ struct blt_ctrl_surf_copy_data {
> > };
> >
> > bool blt_supports_compression(int i915);
> > -bool blt_supports_tiling(int i915, enum blt_tiling_type tiling);
> > +
> > +bool blt_has_block_copy(int i915);
> > +bool blt_has_fast_copy(int i915);
> > +bool blt_fast_copy_supports_tiling(int i915, enum blt_tiling_type tiling);
> > +bool blt_block_copy_supports_tiling(int i915, enum blt_tiling_type tiling);
> >
> > uint64_t emit_blt_block_copy(int i915,
> > uint64_t ahnd,
> > diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
> > index efb6f177..4ac067df 100644
> > --- a/lib/intel_chipset.c
> > +++ b/lib/intel_chipset.c
> > @@ -41,7 +41,6 @@
> > #include "drmtest.h"
> > #include "intel_chipset.h"
> > #include "igt_core.h"
> > -
> - ^
>
> Please do not make unrelated changes in lib (here line was deleted).
>
> > /**
> > * SECTION:intel_chipset
> > * @short_description: Feature macros and chipset helpers
> > diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> > index 9b39472a..a9801b28 100644
> > --- a/lib/intel_chipset.h
> > +++ b/lib/intel_chipset.h
> > @@ -31,6 +31,8 @@
> > #include <pciaccess.h>
> > #include <stdbool.h>
> >
> > +#include "i915/intel_blt_info.h"
> > +
>
> Imho this is a little too big change.
>
> > #define BIT(x) (1ul <<(x))
> >
> > struct pci_device *intel_get_pci_device(void);
> > @@ -86,11 +88,13 @@ struct intel_device_info {
> > bool is_alderlake_p : 1;
> > bool is_alderlake_n : 1;
> > bool is_meteorlake : 1;
> > + const struct blt_cmd_info *blt_tiling;
>
> I would expect here to have bits for supported copy commands
> like has_xy_block_copy, has_xy_src_block_copy, has_xy_fast_copy
> and other. At the end of lib there are macros like HAS_FLATCCS(devid)
> so there could be added new ones like HAS_XY_FAST_COPY(devid).
>
> You added comment at your first patch 1/6 that YFmajor tiling
> is supported only for gen9 and only for specific blt command (fast copy),
> so imho it adds too many complicated info here. I would prefer to
> keep that in blt library, not here.
We want to have this information on platform granularity. Tiling formats
change in platforms on same release so we want to fully control matrix
of commands:tiling-formats here. Looks complicated but only from the
implementation point. Usage of this is straightforward.
--
Zbigniew
>
> Regards,
> Kamil
>
> > const char *codename;
> > };
> >
> > const struct intel_device_info *intel_get_device_info(uint16_t devid) __attribute__((pure));
> >
> > +const struct blt_cmd_info *intel_get_blt_info(uint16_t devid) __attribute__((pure));
> > unsigned intel_gen(uint16_t devid) __attribute__((pure));
> > unsigned intel_graphics_ver(uint16_t devid) __attribute__((pure));
> > unsigned intel_display_ver(uint16_t devid) __attribute__((pure));
> > diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> > index 68dd17ee..ad9dffd8 100644
> > --- a/lib/intel_device_info.c
> > +++ b/lib/intel_device_info.c
> > @@ -145,6 +145,7 @@ static const struct intel_device_info intel_sandybridge_info = {
> > .graphics_ver = 6,
> > .display_ver = 6,
> > .is_sandybridge = true,
> > + .blt_tiling = &pre_gen8_blt_info,
> > .codename = "sandybridge"
> > };
> > static const struct intel_device_info intel_sandybridge_m_info = {
> > @@ -152,6 +153,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
> > .display_ver = 6,
> > .is_mobile = true,
> > .is_sandybridge = true,
> > + .blt_tiling = &pre_gen8_blt_info,
> > .codename = "sandybridge"
> > };
> >
> > @@ -159,6 +161,7 @@ static const struct intel_device_info intel_ivybridge_info = {
> > .graphics_ver = 7,
> > .display_ver = 7,
> > .is_ivybridge = true,
> > + .blt_tiling = &pre_gen8_blt_info,
> > .codename = "ivybridge"
> > };
> > static const struct intel_device_info intel_ivybridge_m_info = {
> > @@ -166,6 +169,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
> > .display_ver = 7,
> > .is_mobile = true,
> > .is_ivybridge = true,
> > + .blt_tiling = &pre_gen8_blt_info,
> > .codename = "ivybridge"
> > };
> >
> > @@ -173,6 +177,7 @@ static const struct intel_device_info intel_valleyview_info = {
> > .graphics_ver = 7,
> > .display_ver = 7,
> > .is_valleyview = true,
> > + .blt_tiling = &pre_gen8_blt_info,
> > .codename = "valleyview"
> > };
> >
> > @@ -180,6 +185,7 @@ static const struct intel_device_info intel_valleyview_info = {
> > .graphics_ver = 7, \
> > .display_ver = 7, \
> > .is_haswell = true, \
> > + .blt_tiling = &pre_gen8_blt_info, \
> > .codename = "haswell"
> >
> > static const struct intel_device_info intel_haswell_gt1_info = {
> > @@ -201,6 +207,7 @@ static const struct intel_device_info intel_haswell_gt3_info = {
> > .graphics_ver = 8, \
> > .display_ver = 8, \
> > .is_broadwell = true, \
> > + .blt_tiling = &gen8_blt_info, \
> > .codename = "broadwell"
> >
> > static const struct intel_device_info intel_broadwell_gt1_info = {
> > @@ -226,12 +233,14 @@ static const struct intel_device_info intel_cherryview_info = {
> > .graphics_ver = 8,
> > .display_ver = 8,
> > .is_cherryview = true,
> > + .blt_tiling = &gen8_blt_info,
> > .codename = "cherryview"
> > };
> >
> > #define SKYLAKE_FIELDS \
> > .graphics_ver = 9, \
> > .display_ver = 9, \
> > + .blt_tiling = &gen11_blt_info, \
> > .codename = "skylake", \
> > .is_skylake = true
> >
> > @@ -259,6 +268,7 @@ static const struct intel_device_info intel_broxton_info = {
> > .graphics_ver = 9,
> > .display_ver = 9,
> > .is_broxton = true,
> > + .blt_tiling = &gen11_blt_info,
> > .codename = "broxton"
> > };
> >
> > @@ -266,6 +276,7 @@ static const struct intel_device_info intel_broxton_info = {
> > .graphics_ver = 9, \
> > .display_ver = 9, \
> > .is_kabylake = true, \
> > + .blt_tiling = &gen11_blt_info, \
> > .codename = "kabylake"
> >
> > static const struct intel_device_info intel_kabylake_gt1_info = {
> > @@ -292,6 +303,7 @@ static const struct intel_device_info intel_geminilake_info = {
> > .graphics_ver = 9,
> > .display_ver = 9,
> > .is_geminilake = true,
> > + .blt_tiling = &gen11_blt_info,
> > .codename = "geminilake"
> > };
> >
> > @@ -299,6 +311,7 @@ static const struct intel_device_info intel_geminilake_info = {
> > .graphics_ver = 9, \
> > .display_ver = 9, \
> > .is_coffeelake = true, \
> > + .blt_tiling = &gen11_blt_info, \
> > .codename = "coffeelake"
> >
> > static const struct intel_device_info intel_coffeelake_gt1_info = {
> > @@ -320,6 +333,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
> > .graphics_ver = 9, \
> > .display_ver = 9, \
> > .is_cometlake = true, \
> > + .blt_tiling = &gen11_blt_info, \
> > .codename = "cometlake"
> >
> > static const struct intel_device_info intel_cometlake_gt1_info = {
> > @@ -336,6 +350,7 @@ static const struct intel_device_info intel_cannonlake_info = {
> > .graphics_ver = 10,
> > .display_ver = 10,
> > .is_cannonlake = true,
> > + .blt_tiling = &gen11_blt_info,
> > .codename = "cannonlake"
> > };
> >
> > @@ -343,6 +358,7 @@ static const struct intel_device_info intel_icelake_info = {
> > .graphics_ver = 11,
> > .display_ver = 11,
> > .is_icelake = true,
> > + .blt_tiling = &gen11_blt_info,
> > .codename = "icelake"
> > };
> >
> > @@ -350,6 +366,7 @@ static const struct intel_device_info intel_elkhartlake_info = {
> > .graphics_ver = 11,
> > .display_ver = 11,
> > .is_elkhartlake = true,
> > + .blt_tiling = &gen11_blt_info,
> > .codename = "elkhartlake"
> > };
> >
> > @@ -357,6 +374,7 @@ static const struct intel_device_info intel_jasperlake_info = {
> > .graphics_ver = 11,
> > .display_ver = 11,
> > .is_jasperlake = true,
> > + .blt_tiling = &gen11_blt_info,
> > .codename = "jasperlake"
> > };
> >
> > @@ -364,6 +382,7 @@ static const struct intel_device_info intel_tigerlake_gt1_info = {
> > .graphics_ver = 12,
> > .display_ver = 12,
> > .is_tigerlake = true,
> > + .blt_tiling = &gen12_blt_info,
> > .codename = "tigerlake",
> > .gt = 1,
> > };
> > @@ -372,6 +391,7 @@ static const struct intel_device_info intel_tigerlake_gt2_info = {
> > .graphics_ver = 12,
> > .display_ver = 12,
> > .is_tigerlake = true,
> > + .blt_tiling = &gen12_blt_info,
> > .codename = "tigerlake",
> > .gt = 2,
> > };
> > @@ -380,6 +400,7 @@ static const struct intel_device_info intel_rocketlake_info = {
> > .graphics_ver = 12,
> > .display_ver = 12,
> > .is_rocketlake = true,
> > + .blt_tiling = &gen12_blt_info,
> > .codename = "rocketlake"
> > };
> >
> > @@ -388,6 +409,7 @@ static const struct intel_device_info intel_dg1_info = {
> > .graphics_rel = 10,
> > .display_ver = 12,
> > .is_dg1 = true,
> > + .blt_tiling = &gen12_blt_info,
> > .codename = "dg1"
> > };
> >
> > @@ -398,6 +420,7 @@ static const struct intel_device_info intel_dg2_info = {
> > .has_4tile = true,
> > .is_dg2 = true,
> > .codename = "dg2",
> > + .blt_tiling = &gen12_dg2_blt_info,
> > .has_flatccs = true,
> > };
> >
> > @@ -405,6 +428,7 @@ static const struct intel_device_info intel_alderlake_s_info = {
> > .graphics_ver = 12,
> > .display_ver = 12,
> > .is_alderlake_s = true,
> > + .blt_tiling = &gen12_blt_info,
> > .codename = "alderlake_s"
> > };
> >
> > @@ -412,6 +436,7 @@ static const struct intel_device_info intel_raptorlake_s_info = {
> > .graphics_ver = 12,
> > .display_ver = 12,
> > .is_raptorlake_s = true,
> > + .blt_tiling = &gen12_blt_info,
> > .codename = "raptorlake_s"
> > };
> >
> > @@ -419,6 +444,7 @@ static const struct intel_device_info intel_alderlake_p_info = {
> > .graphics_ver = 12,
> > .display_ver = 13,
> > .is_alderlake_p = true,
> > + .blt_tiling = &gen12_blt_info,
> > .codename = "alderlake_p"
> > };
> >
> > @@ -426,6 +452,7 @@ static const struct intel_device_info intel_alderlake_n_info = {
> > .graphics_ver = 12,
> > .display_ver = 13,
> > .is_alderlake_n = true,
> > + .blt_tiling = &gen12_blt_info,
> > .codename = "alderlake_n"
> > };
> >
> > @@ -436,6 +463,7 @@ static const struct intel_device_info intel_ats_m_info = {
> > .is_dg2 = true,
> > .has_4tile = true,
> > .codename = "ats_m",
> > + .blt_tiling = &gen12_atsm_blt_info,
> > .has_flatccs = true,
> > };
> >
> > @@ -583,6 +611,25 @@ out:
> > return cache;
> > }
> >
> > +/**
> > + * intel_get_blt_info:
> > + * @devid: pci device id
> > + *
> > + * Looks up the Blitter information about commands and tiling formats supported
> > + * by the device.
> > + *
> > + * Returns:
> > + * The associated blt_cmd_info, NULL if no such information is found
> > + */
> > +const struct blt_cmd_info *intel_get_blt_info(uint16_t devid)
> > +{
> > + const struct intel_device_info *dev_info;
> > +
> > + dev_info = intel_get_device_info(devid);
> > +
> > + return dev_info->blt_tiling;
> > +}
> > +
> > /**
> > * intel_gen:
> > * @devid: pci device id
> > diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
> > index ed60b81c..10327050 100644
> > --- a/tests/i915/gem_ccs.c
> > +++ b/tests/i915/gem_ccs.c
> > @@ -605,7 +605,7 @@ static void block_copy_test(int i915,
> > return;
> >
> > for_each_tiling(tiling) {
> > - if (!blt_supports_tiling(i915, tiling) ||
> > + if (!blt_block_copy_supports_tiling(i915, tiling) ||
> > (param.tiling >= 0 && param.tiling != tiling))
> > continue;
> >
> > @@ -703,7 +703,7 @@ igt_main_args("bf:pst:W:H:", NULL, help_str, opt_handler, NULL)
> > igt_fixture {
> > i915 = drm_open_driver(DRIVER_INTEL);
> > igt_require_gem(i915);
> > - igt_require(AT_LEAST_GEN(intel_get_drm_devid(i915), 12) > 0);
> > + igt_require(blt_has_block_copy(i915));
> >
> > query_info = gem_get_query_memory_regions(i915);
> > igt_require(query_info);
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 3/6] lib/i915_blt: Check for Tile-YF in fast_copy
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 3/6] lib/i915_blt: Check for Tile-YF in fast_copy Karolina Stolarek
@ 2023-01-09 15:27 ` Zbigniew Kempczyński
0 siblings, 0 replies; 21+ messages in thread
From: Zbigniew Kempczyński @ 2023-01-09 15:27 UTC (permalink / raw)
To: Karolina Stolarek; +Cc: igt-dev
On Fri, Dec 23, 2022 at 12:13:48PM +0100, Karolina Stolarek wrote:
> In older gens Tile4 is not available, we have Tile-YF instead. Check for
> both tilings when setting up the fast_copy command.
>
> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
> ---
> lib/i915/i915_blt.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
> index 00cf7470..23ee2218 100644
> --- a/lib/i915/i915_blt.c
> +++ b/lib/i915/i915_blt.c
> @@ -327,6 +327,11 @@ static enum blt_aux_mode __aux_mode(const struct blt_copy_object *obj)
> return AM_AUX_NONE;
> }
>
> +static bool __new_tile_y_type(enum blt_tiling_type tiling)
> +{
> + return tiling == T_TILE4 || tiling == T_YFMAJOR;
> +}
> +
> static void fill_data(struct gen12_block_copy_data *data,
> const struct blt_copy_data *blt,
> uint64_t src_offset, uint64_t dst_offset,
> @@ -1013,8 +1018,8 @@ uint64_t emit_blt_fast_copy(int i915,
> data.dw01.color_depth = __fast_color_depth(blt->color_depth);
> data.dw01.dst_memory = __memory_type(blt->dst.region);
> data.dw01.src_memory = __memory_type(blt->src.region);
> - data.dw01.dst_type_y = blt->dst.tiling == T_TILE4 ? 1 : 0;
> - data.dw01.src_type_y = blt->src.tiling == T_TILE4 ? 1 : 0;
> + data.dw01.dst_type_y = __new_tile_y_type(blt->dst.tiling) ? 1 : 0;
> + data.dw01.src_type_y = __new_tile_y_type(blt->src.tiling) ? 1 : 0;
Looks ok for me,
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
--
Zbigniew
>
> data.dw02.dst_x1 = blt->dst.x1;
> data.dw02.dst_y1 = blt->dst.y1;
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 4/6] lib/i915_blt: Add common functions for blt_copy_object
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 4/6] lib/i915_blt: Add common functions for blt_copy_object Karolina Stolarek
@ 2023-01-09 15:29 ` Zbigniew Kempczyński
0 siblings, 0 replies; 21+ messages in thread
From: Zbigniew Kempczyński @ 2023-01-09 15:29 UTC (permalink / raw)
To: Karolina Stolarek; +Cc: igt-dev
On Fri, Dec 23, 2022 at 12:13:49PM +0100, Karolina Stolarek wrote:
> gem_ccs and gem_lmem_swapping tests share a number of functions.
> Extract them to i915_blt so they are accessible for both tests.
> Delete local definitions. Add blt_* prefixes to avoid potential
> name clash.
>
> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
Ok, you've migrated common initialization part to library.
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
--
Zbigniew
> ---
> lib/i915/i915_blt.c | 95 ++++++++++++++++
> lib/i915/i915_blt.h | 30 ++++-
> tests/i915/gem_ccs.c | 196 +++++++++------------------------
> tests/i915/gem_lmem_swapping.c | 81 +++-----------
> 4 files changed, 191 insertions(+), 211 deletions(-)
>
> diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
> index 23ee2218..f0d148e4 100644
> --- a/lib/i915/i915_blt.c
> +++ b/lib/i915/i915_blt.c
> @@ -1123,6 +1123,101 @@ int blt_fast_copy(int i915,
> return ret;
> }
>
> +void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
> + int16_t x1, int16_t y1, int16_t x2, int16_t y2,
> + uint16_t x_offset, uint16_t y_offset)
> +{
> + obj->pitch = pitch;
> + obj->x1 = x1;
> + obj->y1 = y1;
> + obj->x2 = x2;
> + obj->y2 = y2;
> + obj->x_offset = x_offset;
> + obj->y_offset = y_offset;
> +}
> +
> +void blt_set_batch(struct blt_copy_batch *batch,
> + uint32_t handle, uint64_t size, uint32_t region)
> +{
> + batch->handle = handle;
> + batch->size = size;
> + batch->region = region;
> +}
> +
> +struct blt_copy_object *
> +blt_create_object(int i915, uint32_t region,
> + uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs,
> + enum blt_tiling_type tiling,
> + enum blt_compression compression,
> + enum blt_compression_type compression_type,
> + bool create_mapping)
> +{
> + struct blt_copy_object *obj;
> + uint64_t size = width * height * bpp / 8;
> + uint32_t stride = tiling == T_LINEAR ? width * 4 : width;
> + uint32_t handle;
> +
> + obj = calloc(1, sizeof(*obj));
> +
> + obj->size = size;
> + igt_assert(__gem_create_in_memory_regions(i915, &handle,
> + &size, region) == 0);
> +
> + blt_set_object(obj, handle, size, region, mocs, tiling,
> + compression, compression_type);
> + blt_set_geom(obj, stride, 0, 0, width, height, 0, 0);
> +
> + if (create_mapping)
> + obj->ptr = gem_mmap__device_coherent(i915, handle, 0, size,
> + PROT_READ | PROT_WRITE);
> +
> + return obj;
> +}
> +
> +void blt_destroy_object(int i915, struct blt_copy_object *obj)
> +{
> + if (obj->ptr)
> + munmap(obj->ptr, obj->size);
> +
> + gem_close(i915, obj->handle);
> + free(obj);
> +}
> +
> +void blt_set_object(struct blt_copy_object *obj,
> + uint32_t handle, uint64_t size, uint32_t region,
> + uint8_t mocs, enum blt_tiling_type tiling,
> + enum blt_compression compression,
> + enum blt_compression_type compression_type)
> +{
> + obj->handle = handle;
> + obj->size = size;
> + obj->region = region;
> + obj->mocs = mocs;
> + obj->tiling = tiling;
> + obj->compression = compression;
> + obj->compression_type = compression_type;
> +}
> +
> +void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
> + uint8_t compression_format,
> + uint16_t surface_width, uint16_t surface_height,
> + enum blt_surface_type surface_type)
> +{
> + obj->compression_format = compression_format;
> + obj->surface_width = surface_width;
> + obj->surface_height = surface_height;
> + obj->surface_type = surface_type;
> +
> + /* Ensure mip tail won't overlap lod */
> + obj->mip_tail_start_lod = 0xf;
> +}
> +
> +void blt_set_copy_object(struct blt_copy_object *obj,
> + const struct blt_copy_object *orig)
> +{
> + memcpy(obj, orig, sizeof(*obj));
> +}
> +
> /**
> * blt_surface_fill_rect:
> * @i915: drm fd
> diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
> index 3730c7c0..0f084055 100644
> --- a/lib/i915/i915_blt.h
> +++ b/lib/i915/i915_blt.h
> @@ -202,10 +202,36 @@ int blt_fast_copy(int i915,
> uint64_t ahnd,
> const struct blt_copy_data *blt);
>
> +void blt_set_geom(struct blt_copy_object *obj, uint32_t pitch,
> + int16_t x1, int16_t y1, int16_t x2, int16_t y2,
> + uint16_t x_offset, uint16_t y_offset);
> +void blt_set_batch(struct blt_copy_batch *batch,
> + uint32_t handle, uint64_t size, uint32_t region);
> +
> +struct blt_copy_object *
> +blt_create_object(int i915, uint32_t region,
> + uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs,
> + enum blt_tiling_type tiling,
> + enum blt_compression compression,
> + enum blt_compression_type compression_type,
> + bool create_mapping);
> +void blt_destroy_object(int i915, struct blt_copy_object *obj);
> +void blt_set_object(struct blt_copy_object *obj,
> + uint32_t handle, uint64_t size, uint32_t region,
> + uint8_t mocs, enum blt_tiling_type tiling,
> + enum blt_compression compression,
> + enum blt_compression_type compression_type);
> +void blt_set_object_ext(struct blt_block_copy_object_ext *obj,
> + uint8_t compression_format,
> + uint16_t surface_width, uint16_t surface_height,
> + enum blt_surface_type surface_type);
> +void blt_set_copy_object(struct blt_copy_object *obj,
> + const struct blt_copy_object *orig);
> +
> void blt_surface_info(const char *info,
> const struct blt_copy_object *obj);
> void blt_surface_fill_rect(int i915, const struct blt_copy_object *obj,
> uint32_t width, uint32_t height);
> void blt_surface_to_png(int i915, uint32_t run_id, const char *fileid,
> - const struct blt_copy_object *obj,
> - uint32_t width, uint32_t height);
> + const struct blt_copy_object *obj,
> + uint32_t width, uint32_t height);
> diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
> index 10327050..b2da04b1 100644
> --- a/tests/i915/gem_ccs.c
> +++ b/tests/i915/gem_ccs.c
> @@ -44,56 +44,6 @@ struct test_config {
> bool suspend_resume;
> };
>
> -static void set_object(struct blt_copy_object *obj,
> - uint32_t handle, uint64_t size, uint32_t region,
> - uint8_t mocs, enum blt_tiling_type tiling,
> - enum blt_compression compression,
> - enum blt_compression_type compression_type)
> -{
> - obj->handle = handle;
> - obj->size = size;
> - obj->region = region;
> - obj->mocs = mocs;
> - obj->tiling = tiling;
> - obj->compression = compression;
> - obj->compression_type = compression_type;
> -}
> -
> -static void set_geom(struct blt_copy_object *obj, uint32_t pitch,
> - int16_t x1, int16_t y1, int16_t x2, int16_t y2,
> - uint16_t x_offset, uint16_t y_offset)
> -{
> - obj->pitch = pitch;
> - obj->x1 = x1;
> - obj->y1 = y1;
> - obj->x2 = x2;
> - obj->y2 = y2;
> - obj->x_offset = x_offset;
> - obj->y_offset = y_offset;
> -}
> -
> -static void set_batch(struct blt_copy_batch *batch,
> - uint32_t handle, uint64_t size, uint32_t region)
> -{
> - batch->handle = handle;
> - batch->size = size;
> - batch->region = region;
> -}
> -
> -static void set_object_ext(struct blt_block_copy_object_ext *obj,
> - uint8_t compression_format,
> - uint16_t surface_width, uint16_t surface_height,
> - enum blt_surface_type surface_type)
> -{
> - obj->compression_format = compression_format;
> - obj->surface_width = surface_width;
> - obj->surface_height = surface_height;
> - obj->surface_type = surface_type;
> -
> - /* Ensure mip tail won't overlap lod */
> - obj->mip_tail_start_lod = 0xf;
> -}
> -
> static void set_surf_object(struct blt_ctrl_surf_copy_object *obj,
> uint32_t handle, uint32_t region, uint64_t size,
> uint8_t mocs, enum blt_access_type access_type)
> @@ -105,51 +55,6 @@ static void set_surf_object(struct blt_ctrl_surf_copy_object *obj,
> obj->access_type = access_type;
> }
>
> -static struct blt_copy_object *
> -create_object(int i915, uint32_t region,
> - uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs,
> - enum blt_tiling_type tiling,
> - enum blt_compression compression,
> - enum blt_compression_type compression_type,
> - bool create_mapping)
> -{
> - struct blt_copy_object *obj;
> - uint64_t size = width * height * bpp / 8;
> - uint32_t stride = tiling == T_LINEAR ? width * 4 : width;
> - uint32_t handle;
> -
> - obj = calloc(1, sizeof(*obj));
> -
> - obj->size = size;
> - igt_assert(__gem_create_in_memory_regions(i915, &handle,
> - &size, region) == 0);
> -
> - set_object(obj, handle, size, region, mocs, tiling,
> - compression, compression_type);
> - set_geom(obj, stride, 0, 0, width, height, 0, 0);
> -
> - if (create_mapping)
> - obj->ptr = gem_mmap__device_coherent(i915, handle, 0, size,
> - PROT_READ | PROT_WRITE);
> -
> - return obj;
> -}
> -
> -static void destroy_object(int i915, struct blt_copy_object *obj)
> -{
> - if (obj->ptr)
> - munmap(obj->ptr, obj->size);
> -
> - gem_close(i915, obj->handle);
> - free(obj);
> -}
> -
> -static void set_blt_object(struct blt_copy_object *obj,
> - const struct blt_copy_object *orig)
> -{
> - memcpy(obj, orig, sizeof(*obj));
> -}
> -
> #define PRINT_SURFACE_INFO(name, obj) do { \
> if (param.print_surface_info) \
> blt_surface_info((name), (obj)); } while (0)
> @@ -189,7 +94,7 @@ static void surf_copy(int i915,
> uc_mocs, INDIRECT_ACCESS);
> set_surf_object(&surf.dst, ccs, REGION_SMEM, ccssize,
> uc_mocs, DIRECT_ACCESS);
> - set_batch(&surf.bb, bb, bb_size, REGION_SMEM);
> + blt_set_batch(&surf.bb, bb, bb_size, REGION_SMEM);
> blt_ctrl_surf_copy(i915, ctx, e, ahnd, &surf);
> gem_sync(i915, surf.dst.handle);
>
> @@ -236,13 +141,13 @@ static void surf_copy(int i915,
> memset(&blt, 0, sizeof(blt));
> blt.color_depth = CD_32bit;
> blt.print_bb = param.print_bb;
> - set_blt_object(&blt.src, mid);
> - set_blt_object(&blt.dst, dst);
> - set_object_ext(&ext.src, mid->compression_type, mid->x2, mid->y2, SURFACE_TYPE_2D);
> - set_object_ext(&ext.dst, 0, dst->x2, dst->y2, SURFACE_TYPE_2D);
> + blt_set_copy_object(&blt.src, mid);
> + blt_set_copy_object(&blt.dst, dst);
> + blt_set_object_ext(&ext.src, mid->compression_type, mid->x2, mid->y2, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext.dst, 0, dst->x2, dst->y2, SURFACE_TYPE_2D);
> bb_size = 4096;
> bb = gem_create_from_pool(i915, &bb_size, REGION_SMEM);
> - set_batch(&blt.bb, bb, bb_size, REGION_SMEM);
> + blt_set_batch(&blt.bb, bb, bb_size, REGION_SMEM);
> blt_block_copy(i915, ctx, e, ahnd, &blt, &ext);
> gem_sync(i915, blt.dst.handle);
> WRITE_PNG(i915, run_id, "corrupted", &blt.dst, dst->x2, dst->y2);
> @@ -399,12 +304,12 @@ static void block_copy(int i915,
> if (!blt_supports_compression(i915))
> pext = NULL;
>
> - src = create_object(i915, region1, width, height, bpp, uc_mocs,
> - T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> - mid = create_object(i915, mid_region, width, height, bpp, uc_mocs,
> - mid_tiling, mid_compression, comp_type, true);
> - dst = create_object(i915, region1, width, height, bpp, uc_mocs,
> - T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> + src = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
> + T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> + mid = blt_create_object(i915, mid_region, width, height, bpp, uc_mocs,
> + mid_tiling, mid_compression, comp_type, true);
> + dst = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
> + T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> igt_assert(src->size == dst->size);
> PRINT_SURFACE_INFO("src", src);
> PRINT_SURFACE_INFO("mid", mid);
> @@ -416,11 +321,11 @@ static void block_copy(int i915,
> memset(&blt, 0, sizeof(blt));
> blt.color_depth = CD_32bit;
> blt.print_bb = param.print_bb;
> - set_blt_object(&blt.src, src);
> - set_blt_object(&blt.dst, mid);
> - set_object_ext(&ext.src, 0, width, height, SURFACE_TYPE_2D);
> - set_object_ext(&ext.dst, mid_compression_format, width, height, SURFACE_TYPE_2D);
> - set_batch(&blt.bb, bb, bb_size, region1);
> + blt_set_copy_object(&blt.src, src);
> + blt_set_copy_object(&blt.dst, mid);
> + blt_set_object_ext(&ext.src, 0, width, height, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext.dst, mid_compression_format, width, height, SURFACE_TYPE_2D);
> + blt_set_batch(&blt.bb, bb, bb_size, region1);
>
> blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
> gem_sync(i915, mid->handle);
> @@ -462,26 +367,26 @@ static void block_copy(int i915,
> memset(&blt, 0, sizeof(blt));
> blt.color_depth = CD_32bit;
> blt.print_bb = param.print_bb;
> - set_blt_object(&blt.src, mid);
> - set_blt_object(&blt.dst, dst);
> - set_object_ext(&ext.src, mid_compression_format, width, height, SURFACE_TYPE_2D);
> - set_object_ext(&ext.dst, 0, width, height, SURFACE_TYPE_2D);
> + blt_set_copy_object(&blt.src, mid);
> + blt_set_copy_object(&blt.dst, dst);
> + blt_set_object_ext(&ext.src, mid_compression_format, width, height, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext.dst, 0, width, height, SURFACE_TYPE_2D);
> if (config->inplace) {
> - set_object(&blt.dst, mid->handle, dst->size, mid->region, 0,
> - T_LINEAR, COMPRESSION_DISABLED, comp_type);
> + blt_set_object(&blt.dst, mid->handle, dst->size, mid->region, 0,
> + T_LINEAR, COMPRESSION_DISABLED, comp_type);
> blt.dst.ptr = mid->ptr;
> }
>
> - set_batch(&blt.bb, bb, bb_size, region1);
> + blt_set_batch(&blt.bb, bb, bb_size, region1);
> blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
> gem_sync(i915, blt.dst.handle);
> WRITE_PNG(i915, run_id, "dst", &blt.dst, width, height);
>
> result = memcmp(src->ptr, blt.dst.ptr, src->size);
>
> - destroy_object(i915, src);
> - destroy_object(i915, mid);
> - destroy_object(i915, dst);
> + blt_destroy_object(i915, src);
> + blt_destroy_object(i915, mid);
> + blt_destroy_object(i915, dst);
> gem_close(i915, bb);
> put_ahnd(ahnd);
>
> @@ -515,14 +420,14 @@ static void block_multicopy(int i915,
> if (!blt_supports_compression(i915))
> pext3 = NULL;
>
> - src = create_object(i915, region1, width, height, bpp, uc_mocs,
> - T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> - mid = create_object(i915, mid_region, width, height, bpp, uc_mocs,
> - mid_tiling, mid_compression, comp_type, true);
> - dst = create_object(i915, region1, width, height, bpp, uc_mocs,
> - mid_tiling, COMPRESSION_DISABLED, comp_type, true);
> - final = create_object(i915, region1, width, height, bpp, uc_mocs,
> - T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> + src = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
> + T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> + mid = blt_create_object(i915, mid_region, width, height, bpp, uc_mocs,
> + mid_tiling, mid_compression, comp_type, true);
> + dst = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
> + mid_tiling, COMPRESSION_DISABLED, comp_type, true);
> + final = blt_create_object(i915, region1, width, height, bpp, uc_mocs,
> + T_LINEAR, COMPRESSION_DISABLED, comp_type, true);
> igt_assert(src->size == dst->size);
> PRINT_SURFACE_INFO("src", src);
> PRINT_SURFACE_INFO("mid", mid);
> @@ -534,22 +439,23 @@ static void block_multicopy(int i915,
> memset(&blt3, 0, sizeof(blt3));
> blt3.color_depth = CD_32bit;
> blt3.print_bb = param.print_bb;
> - set_blt_object(&blt3.src, src);
> - set_blt_object(&blt3.mid, mid);
> - set_blt_object(&blt3.dst, dst);
> - set_blt_object(&blt3.final, final);
> + blt_set_copy_object(&blt3.src, src);
> + blt_set_copy_object(&blt3.mid, mid);
> + blt_set_copy_object(&blt3.dst, dst);
> + blt_set_copy_object(&blt3.final, final);
>
> if (config->inplace) {
> - set_object(&blt3.dst, mid->handle, dst->size, mid->region, mid->mocs,
> - mid_tiling, COMPRESSION_DISABLED, comp_type);
> + blt_set_object(&blt3.dst, mid->handle, dst->size, mid->region,
> + mid->mocs, mid_tiling, COMPRESSION_DISABLED,
> + comp_type);
> blt3.dst.ptr = mid->ptr;
> }
>
> - set_object_ext(&ext3.src, 0, width, height, SURFACE_TYPE_2D);
> - set_object_ext(&ext3.mid, mid_compression_format, width, height, SURFACE_TYPE_2D);
> - set_object_ext(&ext3.dst, 0, width, height, SURFACE_TYPE_2D);
> - set_object_ext(&ext3.final, 0, width, height, SURFACE_TYPE_2D);
> - set_batch(&blt3.bb, bb, bb_size, region1);
> + blt_set_object_ext(&ext3.src, 0, width, height, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext3.mid, mid_compression_format, width, height, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext3.dst, 0, width, height, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext3.final, 0, width, height, SURFACE_TYPE_2D);
> + blt_set_batch(&blt3.bb, bb, bb_size, region1);
>
> blt_block_copy3(i915, ctx, e, ahnd, &blt3, pext3);
> gem_sync(i915, blt3.final.handle);
> @@ -562,10 +468,10 @@ static void block_multicopy(int i915,
>
> result = memcmp(src->ptr, blt3.final.ptr, src->size);
>
> - destroy_object(i915, src);
> - destroy_object(i915, mid);
> - destroy_object(i915, dst);
> - destroy_object(i915, final);
> + blt_destroy_object(i915, src);
> + blt_destroy_object(i915, mid);
> + blt_destroy_object(i915, dst);
> + blt_destroy_object(i915, final);
> gem_close(i915, bb);
> put_ahnd(ahnd);
>
> diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
> index 9388d4de..55b044ec 100644
> --- a/tests/i915/gem_lmem_swapping.c
> +++ b/tests/i915/gem_lmem_swapping.c
> @@ -76,53 +76,6 @@ struct object {
> struct blt_copy_object *blt_obj;
> };
>
> -static void set_object(struct blt_copy_object *obj,
> - uint32_t handle, uint64_t size, uint32_t region,
> - uint8_t mocs, enum blt_tiling_type tiling,
> - enum blt_compression compression,
> - enum blt_compression_type compression_type)
> -{
> - obj->handle = handle;
> - obj->size = size;
> - obj->region = region;
> - obj->mocs = mocs;
> - obj->tiling = tiling;
> - obj->compression = compression;
> - obj->compression_type = compression_type;
> -}
> -
> -static void set_geom(struct blt_copy_object *obj, uint32_t pitch,
> - int16_t x1, int16_t y1, int16_t x2, int16_t y2,
> - uint16_t x_offset, uint16_t y_offset)
> -{
> - obj->pitch = pitch;
> - obj->x1 = x1;
> - obj->y1 = y1;
> - obj->x2 = x2;
> - obj->y2 = y2;
> - obj->x_offset = x_offset;
> - obj->y_offset = y_offset;
> -}
> -
> -static void set_batch(struct blt_copy_batch *batch,
> - uint32_t handle, uint64_t size, uint32_t region)
> -{
> - batch->handle = handle;
> - batch->size = size;
> - batch->region = region;
> -}
> -
> -static void set_object_ext(struct blt_block_copy_object_ext *obj,
> - uint8_t compression_format,
> - uint16_t surface_width, uint16_t surface_height,
> - enum blt_surface_type surface_type)
> -{
> - obj->compression_format = compression_format;
> - obj->surface_width = surface_width;
> - obj->surface_height = surface_height;
> - obj->surface_type = surface_type;
> -}
> -
> static uint32_t create_bo(int i915,
> uint64_t *size,
> struct drm_i915_gem_memory_class_instance *region,
> @@ -179,7 +132,7 @@ init_object_ccs(int i915, struct object *obj, struct blt_copy_object *tmp,
> cmd = calloc(1, sizeof(*cmd));
> igt_assert(cmd);
> cmd->handle = gem_create_from_pool(i915, &size, region);
> - set_batch(cmd, cmd->handle, size, region);
> + blt_set_batch(cmd, cmd->handle, size, region);
>
> buf = gem_mmap__device_coherent(i915, tmp->handle, 0, obj->size, PROT_WRITE);
> gem_set_domain(i915, tmp->handle, I915_GEM_DOMAIN_WC, I915_GEM_DOMAIN_WC);
> @@ -195,9 +148,9 @@ init_object_ccs(int i915, struct object *obj, struct blt_copy_object *tmp,
> memcpy(&blt.dst, obj->blt_obj, sizeof(blt.dst));
> memcpy(&blt.bb, cmd, sizeof(blt.bb));
>
> - set_object_ext(&ext.src, 0, tmp->x2, tmp->y2, SURFACE_TYPE_2D);
> - set_object_ext(&ext.dst, 0, obj->blt_obj->x2, obj->blt_obj->y2,
> - SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext.src, 0, tmp->x2, tmp->y2, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext.dst, 0, obj->blt_obj->x2, obj->blt_obj->y2,
> + SURFACE_TYPE_2D);
>
> blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
> free(cmd);
> @@ -244,7 +197,7 @@ verify_object_ccs(int i915, const struct object *obj,
> cmd = calloc(1, sizeof(*cmd));
> igt_assert(cmd);
> cmd->handle = gem_create_from_pool(i915, &size, region);
> - set_batch(cmd, cmd->handle, size, region);
> + blt_set_batch(cmd, cmd->handle, size, region);
>
> memset(&blt, 0, sizeof(blt));
> blt.color_depth = CD_32bit;
> @@ -256,9 +209,9 @@ verify_object_ccs(int i915, const struct object *obj,
> blt.dst.x2 = min(obj->blt_obj->x2, tmp->x2);
> blt.dst.y2 = min(obj->blt_obj->y2, tmp->y2);
>
> - set_object_ext(&ext.src, 0, obj->blt_obj->x2, obj->blt_obj->y2,
> - SURFACE_TYPE_2D);
> - set_object_ext(&ext.dst, 0, tmp->x2, tmp->y2, SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext.src, 0, obj->blt_obj->x2, obj->blt_obj->y2,
> + SURFACE_TYPE_2D);
> + blt_set_object_ext(&ext.dst, 0, tmp->x2, tmp->y2, SURFACE_TYPE_2D);
> blt_block_copy(i915, ctx, e, ahnd, &blt, pext);
>
> buf = gem_mmap__device_coherent(i915, tmp->handle, 0,
> @@ -364,11 +317,11 @@ static void __do_evict(int i915,
>
> tmp->handle = gem_create_in_memory_regions(i915, params->size.max,
> INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0));
> - set_object(tmp, tmp->handle, params->size.max,
> - INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0),
> - intel_get_uc_mocs(i915), T_LINEAR,
> - COMPRESSION_DISABLED, COMPRESSION_TYPE_3D);
> - set_geom(tmp, stride, 0, 0, width, height, 0, 0);
> + blt_set_object(tmp, tmp->handle, params->size.max,
> + INTEL_MEMORY_REGION_ID(I915_SYSTEM_MEMORY, 0),
> + intel_get_uc_mocs(i915), T_LINEAR,
> + COMPRESSION_DISABLED, COMPRESSION_TYPE_3D);
> + blt_set_geom(tmp, stride, 0, 0, width, height, 0, 0);
> }
>
> size = 0;
> @@ -395,10 +348,10 @@ static void __do_evict(int i915,
>
> obj->blt_obj = calloc(1, sizeof(*obj->blt_obj));
> igt_assert(obj->blt_obj);
> - set_object(obj->blt_obj, obj->handle, obj->size, region_id,
> - intel_get_uc_mocs(i915), T_LINEAR,
> - COMPRESSION_ENABLED, COMPRESSION_TYPE_3D);
> - set_geom(obj->blt_obj, stride, 0, 0, width, height, 0, 0);
> + blt_set_object(obj->blt_obj, obj->handle, obj->size, region_id,
> + intel_get_uc_mocs(i915), T_LINEAR,
> + COMPRESSION_ENABLED, COMPRESSION_TYPE_3D);
> + blt_set_geom(obj->blt_obj, stride, 0, 0, width, height, 0, 0);
> init_object_ccs(i915, obj, tmp, rand(), blt_ctx,
> region_id, ahnd);
> } else if (params->flags & TEST_VERIFY) {
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 5/6] tests/gem_exercise_blt: Add fast-copy test
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 5/6] tests/gem_exercise_blt: Add fast-copy test Karolina Stolarek
@ 2023-01-09 15:34 ` Zbigniew Kempczyński
2023-01-10 6:57 ` Karolina Stolarek
0 siblings, 1 reply; 21+ messages in thread
From: Zbigniew Kempczyński @ 2023-01-09 15:34 UTC (permalink / raw)
To: Karolina Stolarek; +Cc: igt-dev
On Fri, Dec 23, 2022 at 12:13:50PM +0100, Karolina Stolarek wrote:
> Exercise a basic scenario with two block copies in separate batch
> buffers.
>
> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
> ---
> tests/i915/gem_exercise_blt.c | 216 ++++++++++++++++++++++++++++++++++
> tests/meson.build | 1 +
> 2 files changed, 217 insertions(+)
> create mode 100644 tests/i915/gem_exercise_blt.c
>
> diff --git a/tests/i915/gem_exercise_blt.c b/tests/i915/gem_exercise_blt.c
> new file mode 100644
> index 00000000..67a8b660
> --- /dev/null
> +++ b/tests/i915/gem_exercise_blt.c
> @@ -0,0 +1,216 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include "igt.h"
> +#include "drm.h"
> +#include "i915/gem.h"
> +#include "i915/gem_create.h"
> +#include "lib/intel_chipset.h"
> +#include "i915/i915_blt.h"
> +#include "i915/intel_mocs.h"
> +
> +IGT_TEST_DESCRIPTION("Exercise blitter commands");
> +
> +static struct param {
> + int tiling;
> + bool write_png;
> + bool print_bb;
> + bool print_surface_info;
> + int width;
> + int height;
> +} param = {
> + .tiling = -1,
> + .write_png = false,
> + .print_bb = false,
> + .print_surface_info = false,
> + .width = 512,
> + .height = 512,
> +};
> +
> +#define PRINT_SURFACE_INFO(name, obj) do { \
> + if (param.print_surface_info) \
> + blt_surface_info((name), (obj)); } while (0)
> +
> +#define WRITE_PNG(fd, id, name, obj, w, h) do { \
> + if (param.write_png) \
> + blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
> +
> +static void fast_copy(int i915, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e,
> + uint32_t region1, uint32_t region2,
> + enum blt_tiling_type mid_tiling)
> +{
> + struct blt_copy_data blt = {};
> + struct blt_copy_object *src, *mid, *dst;
> + const uint32_t bpp = 32;
> + uint64_t bb_size = 4096;
> + uint64_t ahnd = intel_allocator_open_full(i915, ctx->id, 0, 0,
> + INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
> + uint32_t bb;
> + uint32_t width = param.width, height = param.height;
> + int result;
> +
> + igt_assert(__gem_create_in_memory_regions(i915, &bb, &bb_size, region1) == 0);
> +
> + src = blt_create_object(i915, region1, width, height, bpp, 0,
> + T_LINEAR, COMPRESSION_DISABLED, 0, true);
> + mid = blt_create_object(i915, region2, width, height, bpp, 0,
> + mid_tiling, COMPRESSION_DISABLED, 0, true);
> + dst = blt_create_object(i915, region1, width, height, bpp, 0,
> + T_LINEAR, COMPRESSION_DISABLED, 0, true);
> + igt_assert(src->size == dst->size);
> +
> + blt_surface_fill_rect(i915, src, width, height);
> + WRITE_PNG(i915, mid_tiling, "src", src, width, height);
> +
> + memset(&blt, 0, sizeof(blt));
> + blt.color_depth = CD_32bit;
> + blt.print_bb = param.print_bb;
> + blt_set_copy_object(&blt.src, src);
> + blt_set_copy_object(&blt.dst, mid);
> + blt_set_batch(&blt.bb, bb, bb_size, region1);
> +
> + blt_fast_copy(i915, ctx, e, ahnd, &blt);
> + gem_sync(i915, mid->handle);
> +
> + WRITE_PNG(i915, mid_tiling, "src", &blt.src, width, height);
You're writing src png second time. Some pngs will overwrite when
different regions are in use, but that's not a problem for me.
Dumping pngs is for debugging purposes so direct subtest selection
will narrow this to interesting case.
I haven't spotted other issues, with above fixed:
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
--
Zbigniew
> + WRITE_PNG(i915, mid_tiling, "mid", &blt.dst, width, height);
> +
> + memset(&blt, 0, sizeof(blt));
> + blt.color_depth = CD_32bit;
> + blt.print_bb = param.print_bb;
> + blt_set_copy_object(&blt.src, mid);
> + blt_set_copy_object(&blt.dst, dst);
> + blt_set_batch(&blt.bb, bb, bb_size, region1);
> +
> + blt_fast_copy(i915, ctx, e, ahnd, &blt);
> + gem_sync(i915, blt.dst.handle);
> +
> + WRITE_PNG(i915, mid_tiling, "dst", &blt.dst, width, height);
> +
> + result = memcmp(src->ptr, blt.dst.ptr, src->size);
> +
> + blt_destroy_object(i915, src);
> + blt_destroy_object(i915, mid);
> + blt_destroy_object(i915, dst);
> + gem_close(i915, bb);
> + put_ahnd(ahnd);
> +
> + igt_assert_f(!result, "source and destination surfaces differs!\n");
> +}
> +
> +static void fast_copy_test(int i915,
> + const intel_ctx_t *ctx,
> + struct igt_collection *set)
> +{
> + struct igt_collection *regions;
> + const struct intel_execution_engine2 *e;
> + int tiling;
> +
> + for_each_tiling(tiling) {
> + if (!blt_fast_copy_supports_tiling(i915, tiling))
> + continue;
> +
> + for_each_ctx_engine(i915, ctx, e) {
> + if (e->class != I915_ENGINE_CLASS_COPY)
> + continue;
> + for_each_variation_r(regions, 2, set) {
> + uint32_t region1, region2;
> + char *regtxt;
> +
> + region1 = igt_collection_get_value(regions, 0);
> + region2 = igt_collection_get_value(regions, 1);
> + regtxt = memregion_dynamic_subtest_name(regions);
> +
> + igt_dynamic_f("%s-%s",
> + blt_tiling_name(tiling), regtxt) {
> + fast_copy(i915, ctx, e,
> + region1, region2,
> + tiling);
> + }
> +
> + free(regtxt);
> + }
> + }
> + }
> +}
> +
> +static int opt_handler(int opt, int opt_index, void *data)
> +{
> + switch (opt) {
> + case 'b':
> + param.print_bb = true;
> + igt_debug("Print bb: %d\n", param.print_bb);
> + break;
> + case 'p':
> + param.write_png = true;
> + igt_debug("Write png: %d\n", param.write_png);
> + break;
> + case 's':
> + param.print_surface_info = true;
> + igt_debug("Print surface info: %d\n", param.print_surface_info);
> + break;
> + case 't':
> + param.tiling = 1 << atoi(optarg);
> + igt_debug("Tiling: %d\n", param.tiling);
> + break;
> + case 'W':
> + param.width = atoi(optarg);
> + igt_debug("Width: %d\n", param.width);
> + break;
> + case 'H':
> + param.height = atoi(optarg);
> + igt_debug("Height: %d\n", param.height);
> + break;
> + default:
> + return IGT_OPT_HANDLER_ERROR;
> + }
> +
> + return IGT_OPT_HANDLER_SUCCESS;
> +}
> +
> +const char *help_str =
> + " -b\tPrint bb\n"
> + " -p\tWrite PNG\n"
> + " -s\tPrint surface info\n"
> + " -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64, 5 - YFMAJOR)\n"
> + " -W\tWidth (default 512)\n"
> + " -H\tHeight (default 512)"
> + ;
> +
> +igt_main_args("b:pst:W:H:", NULL, help_str, opt_handler, NULL)
> +{
> + struct drm_i915_query_memory_regions *query_info;
> + struct igt_collection *set;
> + const intel_ctx_t *ctx;
> + int i915;
> + igt_hang_t hang;
> +
> + igt_fixture {
> + i915 = drm_open_driver(DRIVER_INTEL);
> + igt_require_gem(i915);
> + igt_require(blt_has_fast_copy(i915));
> +
> + query_info = gem_get_query_memory_regions(i915);
> + igt_require(query_info);
> +
> + set = get_memory_region_set(query_info,
> + I915_SYSTEM_MEMORY,
> + I915_DEVICE_MEMORY);
> + ctx = intel_ctx_create_all_physical(i915);
> + hang = igt_allow_hang(i915, ctx->id, 0);
> + }
> +
> + igt_describe("Check fast-copy blit");
> + igt_subtest_with_dynamic("fast-copy") {
> + fast_copy_test(i915, ctx, set);
> + }
> +
> + igt_fixture {
> + igt_disallow_hang(i915, hang);
> + close(i915);
> + }
> +}
> diff --git a/tests/meson.build b/tests/meson.build
> index cb428998..3c8a3ba3 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -129,6 +129,7 @@ i915_progs = [
> 'gem_exec_nop',
> 'gem_exec_parallel',
> 'gem_exec_params',
> + 'gem_exercise_blt',
> 'gen7_exec_parse',
> 'gen9_exec_parse',
> 'gem_exec_reloc',
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 6/6] tests/gem_exercise_blt: Add fast-copy-emit test
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 6/6] tests/gem_exercise_blt: Add fast-copy-emit test Karolina Stolarek
@ 2023-01-09 15:38 ` Zbigniew Kempczyński
2023-01-10 6:57 ` Karolina Stolarek
0 siblings, 1 reply; 21+ messages in thread
From: Zbigniew Kempczyński @ 2023-01-09 15:38 UTC (permalink / raw)
To: Karolina Stolarek; +Cc: igt-dev
On Fri, Dec 23, 2022 at 12:13:51PM +0100, Karolina Stolarek wrote:
> Add a subtest where two fast copy commands are executed within the
> single batch buffer.
>
> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
> ---
> tests/i915/gem_exercise_blt.c | 190 ++++++++++++++++++++++++++++++++--
> 1 file changed, 184 insertions(+), 6 deletions(-)
>
> diff --git a/tests/i915/gem_exercise_blt.c b/tests/i915/gem_exercise_blt.c
> index 67a8b660..b8bfc436 100644
> --- a/tests/i915/gem_exercise_blt.c
> +++ b/tests/i915/gem_exercise_blt.c
> @@ -37,6 +37,146 @@ static struct param {
> if (param.write_png) \
> blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
>
> +struct blt_fast_copy_data {
> + int i915;
> + struct blt_copy_object src;
> + struct blt_copy_object mid;
> + struct blt_copy_object dst;
> +
> + struct blt_copy_batch bb;
> + enum blt_color_depth color_depth;
> +
> + /* debug stuff */
> + bool print_bb;
> +};
> +
> +static int fast_copy_one_bb(int i915,
> + const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e,
> + uint64_t ahnd,
> + const struct blt_fast_copy_data *blt)
> +{
> + struct drm_i915_gem_execbuffer2 execbuf = {};
> + struct drm_i915_gem_exec_object2 obj[4] = {};
> + struct blt_copy_data blt_tmp;
> + uint64_t src_offset, mid_offset, dst_offset, bb_offset, alignment;
> + uint64_t bb_pos = 0;
> + uint32_t flags;
> + int ret;
> +
> + alignment = gem_detect_safe_alignment(i915);
> +
> + src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
> + mid_offset = get_offset(ahnd, blt->mid.handle, blt->mid.size, alignment);
> + dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
> + bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
> +
> + /* First blit */
> + memset(&blt_tmp, 0, sizeof(blt_tmp));
> + blt_tmp.src = blt->src;
> + blt_tmp.dst = blt->mid;
> + blt_tmp.bb = blt->bb;
> + blt_tmp.color_depth = blt->color_depth;
> + blt_tmp.print_bb = blt->print_bb;
> + bb_pos = emit_blt_fast_copy(i915, ahnd, &blt_tmp, bb_pos, false);
> +
> + /* Second blit */
> + memset(&blt_tmp, 0, sizeof(blt_tmp));
> + blt_tmp.src = blt->mid;
> + blt_tmp.dst = blt->dst;
> + blt_tmp.bb = blt->bb;
> + blt_tmp.color_depth = blt->color_depth;
> + blt_tmp.print_bb = blt->print_bb;
> + bb_pos = emit_blt_fast_copy(i915, ahnd, &blt_tmp, bb_pos, true);
Pipelined blits? Nice!
> +
> + flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +
> + obj[0].handle = blt->src.handle;
> + obj[0].offset = CANONICAL(src_offset);
> + obj[0].flags = flags;
> +
> + obj[1].handle = blt->mid.handle;
> + obj[1].offset = CANONICAL(mid_offset);
> + obj[1].flags = flags | EXEC_OBJECT_WRITE;
> +
> + obj[2].handle = blt->dst.handle;
> + obj[2].offset = CANONICAL(dst_offset);
> + obj[2].flags = flags;
> +
> + obj[3].handle = blt->bb.handle;
> + obj[3].offset = CANONICAL(bb_offset);
> + obj[3].flags = flags;
> +
> + execbuf.buffer_count = 4;
> + execbuf.buffers_ptr = to_user_pointer(obj);
> + execbuf.rsvd1 = ctx ? ctx->id : 0;
> + execbuf.flags = e ? e->flags : I915_EXEC_BLT;
> + ret = __gem_execbuf(i915, &execbuf);
> +
> + gem_sync(i915, blt->bb.handle);
> +
> + return ret;
> +}
> +
> +static void fast_copy_emit(int i915, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e,
> + uint32_t region1, uint32_t region2,
> + enum blt_tiling_type mid_tiling)
> +{
> + struct blt_fast_copy_data blt = {};
> + struct blt_copy_object *src, *mid, *dst;
> + const uint32_t bpp = 32;
> + uint64_t bb_size = 4096;
> + uint64_t ahnd = intel_allocator_open_full(i915, ctx->id, 0, 0,
> + INTEL_ALLOCATOR_SIMPLE,
> + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
> + uint32_t bb, width = param.width, height = param.height;
> + int result;
> +
> + igt_assert(__gem_create_in_memory_regions(i915, &bb, &bb_size, region1) == 0);
> +
> + src = blt_create_object(i915, region1, width, height, bpp, 0,
> + T_LINEAR, COMPRESSION_DISABLED, 0, true);
> + mid = blt_create_object(i915, region2, width, height, bpp, 0,
> + mid_tiling, COMPRESSION_DISABLED, 0, true);
> + dst = blt_create_object(i915, region1, width, height, bpp, 0,
> + T_LINEAR, COMPRESSION_DISABLED, 0, true);
> + igt_assert(src->size == dst->size);
> +
> + PRINT_SURFACE_INFO("src", src);
> + PRINT_SURFACE_INFO("mid", mid);
> + PRINT_SURFACE_INFO("dst", dst);
> +
> + blt_surface_fill_rect(i915, src, width, height);
> + WRITE_PNG(i915, mid_tiling, "src", src, width, height);
> +
> + memset(&blt, 0, sizeof(blt));
> + blt.color_depth = CD_32bit;
> + blt.print_bb = param.print_bb;
> + blt_set_copy_object(&blt.src, src);
> + blt_set_copy_object(&blt.mid, mid);
> + blt_set_copy_object(&blt.dst, dst);
> + blt_set_batch(&blt.bb, bb, bb_size, region1);
> +
> + fast_copy_one_bb(i915, ctx, e, ahnd, &blt);
> + gem_sync(i915, blt.dst.handle);
> +
> + WRITE_PNG(i915, mid_tiling, "mid", &blt.mid, width, height);
> + WRITE_PNG(i915, mid_tiling, "dst", &blt.dst, width, height);
> +
> + result = memcmp(src->ptr, blt.dst.ptr, src->size);
> +
> + blt_destroy_object(i915, src);
> + blt_destroy_object(i915, mid);
> + blt_destroy_object(i915, dst);
> + gem_close(i915, bb);
> + put_ahnd(ahnd);
> +
> + munmap(&bb, bb_size);
> +
> + igt_assert_f(!result, "source and destination surfaces differs!\n");
> +}
> +
> static void fast_copy(int i915, const intel_ctx_t *ctx,
> const struct intel_execution_engine2 *e,
> uint32_t region1, uint32_t region2,
> @@ -102,12 +242,42 @@ static void fast_copy(int i915, const intel_ctx_t *ctx,
> igt_assert_f(!result, "source and destination surfaces differs!\n");
> }
>
> +enum fast_copy_func {
> + FAST_COPY,
> + FAST_COPY_EMIT
> +};
> +
> +static char
> + *full_subtest_str(char *regtxt, enum blt_tiling_type tiling,
> + enum fast_copy_func func)
> +{
> + const char *multi_str = "emit";
> + char const *tile_str = blt_tiling_name(tiling);
> + char *name;
> + uint32_t len, sub_len;
> +
> + len = strlen(regtxt) + strlen(tile_str) + strlen(multi_str) + 2;
Similar to other patch - looks overengineered. Maybe asprintf() will help
you to avoid calling strlen().
--
Zbigniew
> + name = malloc(len * sizeof(char));
> + igt_assert(name);
> +
> + sub_len = snprintf(name, len, "%s-%s", tile_str, regtxt);
> +
> + if (func == FAST_COPY_EMIT)
> + snprintf(name + sub_len, len, "-%s", multi_str);
> +
> + return name;
> +}
> +
> static void fast_copy_test(int i915,
> const intel_ctx_t *ctx,
> - struct igt_collection *set)
> + struct igt_collection *set,
> + enum fast_copy_func func)
> {
> struct igt_collection *regions;
> const struct intel_execution_engine2 *e;
> + void (*copy_func)(int i915, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e,
> + uint32_t r1, uint32_t r2, enum blt_tiling_type tiling);
> int tiling;
>
> for_each_tiling(tiling) {
> @@ -119,20 +289,23 @@ static void fast_copy_test(int i915,
> continue;
> for_each_variation_r(regions, 2, set) {
> uint32_t region1, region2;
> - char *regtxt;
> + char *regtxt, *test_name;
>
> region1 = igt_collection_get_value(regions, 0);
> region2 = igt_collection_get_value(regions, 1);
> +
> + copy_func = (func == FAST_COPY) ? fast_copy : fast_copy_emit;
> regtxt = memregion_dynamic_subtest_name(regions);
> + test_name = full_subtest_str(regtxt, tiling, func);
>
> - igt_dynamic_f("%s-%s",
> - blt_tiling_name(tiling), regtxt) {
> - fast_copy(i915, ctx, e,
> + igt_dynamic_f("%s", test_name) {
> + copy_func(i915, ctx, e,
> region1, region2,
> tiling);
> }
>
> free(regtxt);
> + free(test_name);
> }
> }
> }
> @@ -206,7 +379,12 @@ igt_main_args("b:pst:W:H:", NULL, help_str, opt_handler, NULL)
>
> igt_describe("Check fast-copy blit");
> igt_subtest_with_dynamic("fast-copy") {
> - fast_copy_test(i915, ctx, set);
> + fast_copy_test(i915, ctx, set, FAST_COPY);
> + }
> +
> + igt_describe("Check multiple fast-copy in one batch");
> + igt_subtest_with_dynamic("fast-copy-emit") {
> + fast_copy_test(i915, ctx, set, FAST_COPY_EMIT);
> }
>
> igt_fixture {
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 1/6] i915/lib: Add new library for blitter and tiling formats
2023-01-09 12:49 ` Zbigniew Kempczyński
@ 2023-01-10 6:55 ` Karolina Stolarek
0 siblings, 0 replies; 21+ messages in thread
From: Karolina Stolarek @ 2023-01-10 6:55 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
Hi Zbigniew,
Thank you very much for your review.
On 09.01.2023 13:49, Zbigniew Kempczyński wrote:
> On Fri, Dec 23, 2022 at 12:13:46PM +0100, Karolina Stolarek wrote:
>> Add structs to describe what blitter commands and tiling formats
>> are supported per platform. Add a generic functions that check
>> if a specific blitter command or tiling format is supported.
>> Move blt_tiling enum to the newely created library and update
>> its definition. Update i915_blt and block copy tests to reflect
>> that change.
>>
>> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
>> ---
>> .../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
>> lib/i915/i915_blt.c | 31 +--
>> lib/i915/i915_blt.h | 14 +-
>> lib/i915/intel_blt_info.c | 241 ++++++++++++++++++
>> lib/i915/intel_blt_info.h | 98 +++++++
>> lib/meson.build | 1 +
>> tests/i915/gem_ccs.c | 15 +-
>> tests/i915/gem_lmem_swapping.c | 2 +-
>> 8 files changed, 360 insertions(+), 43 deletions(-)
>> create mode 100644 lib/i915/intel_blt_info.c
>> create mode 100644 lib/i915/intel_blt_info.h
>>
>> diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
>> index 102c8a89..24ee17fc 100644
>> --- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
>> +++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
>> @@ -59,6 +59,7 @@
>> </chapter>
>> <chapter>
>> <title>igt/i915 API Reference</title>
>> + <xi:include href="xml/intel_blt_info.xml"/>
>> <xi:include href="xml/gem_create.xml"/>
>> <xi:include href="xml/gem_context.xml"/>
>> <xi:include href="xml/gem_engine_topology.xml"/>
>> diff --git a/lib/i915/i915_blt.c b/lib/i915/i915_blt.c
>> index 54193565..6db135d1 100644
>> --- a/lib/i915/i915_blt.c
>> +++ b/lib/i915/i915_blt.c
>> @@ -217,7 +217,7 @@ bool blt_supports_compression(int i915)
>> * Returns:
>> * true if it does, false otherwise.
>> */
>> -bool blt_supports_tiling(int i915, enum blt_tiling tiling)
>> +bool blt_supports_tiling(int i915, enum blt_tiling_type tiling)
>> {
>> uint32_t devid = intel_get_drm_devid(i915);
>>
>> @@ -238,28 +238,7 @@ bool blt_supports_tiling(int i915, enum blt_tiling tiling)
>> return true;
>> }
>>
>> -/**
>> - * blt_tiling_name:
>> - * @tiling: tiling id
>> - *
>> - * Returns:
>> - * name of @tiling passed. Useful to build test names.
>> - */
>> -const char *blt_tiling_name(enum blt_tiling tiling)
>> -{
>> - switch (tiling) {
>> - case T_LINEAR: return "linear";
>> - case T_XMAJOR: return "xmajor";
>> - case T_YMAJOR: return "ymajor";
>> - case T_TILE4: return "tile4";
>> - case T_TILE64: return "tile64";
>> - }
>> -
>> - igt_warn("invalid tiling passed: %d\n", tiling);
>> - return NULL;
>> -}
>> -
>> -static int __block_tiling(enum blt_tiling tiling)
>> +static int __block_tiling(enum blt_tiling_type tiling)
>> {
>> switch (tiling) {
>> case T_LINEAR: return 0;
>> @@ -267,6 +246,9 @@ static int __block_tiling(enum blt_tiling tiling)
>> case T_YMAJOR: return 1;
>> case T_TILE4: return 2;
>> case T_TILE64: return 3;
>> + /* type only supported in gen9 fast copy */
>> + case T_YFMAJOR:
>> + break;
>> }
>>
>> igt_warn("invalid tiling passed: %d\n", tiling);
>> @@ -891,13 +873,14 @@ struct gen12_fast_copy_data {
>> } dw09;
>> };
>>
>> -static int __fast_tiling(enum blt_tiling tiling)
>> +static int __fast_tiling(enum blt_tiling_type tiling)
>> {
>> switch (tiling) {
>> case T_LINEAR: return 0;
>> case T_XMAJOR: return 1;
>> case T_YMAJOR: return 2;
>> case T_TILE4: return 2;
>> + case T_YFMAJOR: return 2;
>> case T_TILE64: return 3;
>> }
>> return 0;
>> diff --git a/lib/i915/i915_blt.h b/lib/i915/i915_blt.h
>> index 34db9bb9..8fa480b8 100644
>> --- a/lib/i915/i915_blt.h
>> +++ b/lib/i915/i915_blt.h
>> @@ -47,6 +47,7 @@
>> #include <malloc.h>
>> #include "drm.h"
>> #include "igt.h"
>> +#include "intel_blt_info.h"
>>
>> #define CCS_RATIO 256
>>
>> @@ -59,14 +60,6 @@ enum blt_color_depth {
>> CD_128bit,
>> };
>>
>> -enum blt_tiling {
>> - T_LINEAR,
>> - T_XMAJOR,
>> - T_YMAJOR,
>> - T_TILE4,
>> - T_TILE64,
>> -};
>> -
>> enum blt_compression {
>> COMPRESSION_DISABLED,
>> COMPRESSION_ENABLED,
>> @@ -83,7 +76,7 @@ struct blt_copy_object {
>> uint32_t region;
>> uint64_t size;
>> uint8_t mocs;
>> - enum blt_tiling tiling;
>> + enum blt_tiling_type tiling;
>> enum blt_compression compression; /* BC only */
>> enum blt_compression_type compression_type; /* BC only */
>> uint32_t pitch;
>> @@ -165,8 +158,7 @@ struct blt_ctrl_surf_copy_data {
>> };
>>
>> bool blt_supports_compression(int i915);
>> -bool blt_supports_tiling(int i915, enum blt_tiling tiling);
>> -const char *blt_tiling_name(enum blt_tiling tiling);
>> +bool blt_supports_tiling(int i915, enum blt_tiling_type tiling);
>>
>> uint64_t emit_blt_block_copy(int i915,
>> uint64_t ahnd,
>> diff --git a/lib/i915/intel_blt_info.c b/lib/i915/intel_blt_info.c
>> new file mode 100644
>> index 00000000..2f54d1b4
>> --- /dev/null
>> +++ b/lib/i915/intel_blt_info.c
>> @@ -0,0 +1,241 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#include "intel_blt_info.h"
>> +
>> +#define BLT_STR_MAX 200
>> +#define TILE_STR_MAX 60
>> +#define T_MAX_SHIFT 6
>
> I think you can remove this define adding T_TILING_MAX in enum blt_tiling_type.
Yeah, not sure why I didn't do it after updating the commands enum
>
>> +
>> +#define BLT_INFO(_cmd, _tiling) { \
>> + .blt_cmd_type = _cmd, \
>> + .supported_tiling = _tiling \
>> + }
>> +
>> +static const struct blt_tiling_info src_copy = BLT_INFO(SRC_COPY, T_LINEAR);
>> +static const struct blt_tiling_info
>> + pre_gen8_xy_src_copy = BLT_INFO(XY_SRC_COPY, T_LINEAR | T_XMAJOR);
>
> I wondered to have enum blt_tiling_type incrementing without gaps to introduce
>
> #define BLT_MASK(x) (1 << (x))
I believe we have BIT(x) defined in intel_chipset.h, so I'll use it
instead. Thanks for your suggestion!
>
> then:
>
> static const struct blt_tiling_info
> pre_gen8_xy_src_copy = BLT_INFO(XY_SRC_COPY,
> BLT_MASK(T_LINEAR) |
> BLT_MASK(T_XMAJOR));
>
> and so on. Initialization is not too comfortable but it is in .c file,
> so it is encapsulated here.
>
>> +static const struct blt_tiling_info
>> + gen8_xy_src_copy = BLT_INFO(XY_SRC_COPY,
>> + T_LINEAR | T_XMAJOR | T_YMAJOR);
>> +static const struct blt_tiling_info
>> + gen11_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
>> + T_LINEAR | T_YMAJOR |
>> + T_YFMAJOR | T_TILE64);
>> +static const struct blt_tiling_info
>> + gen12_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
>> + T_LINEAR | T_YMAJOR |
>> + T_TILE4 | T_TILE64);
>> +static const struct blt_tiling_info
>> + dg2_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
>> + T_LINEAR | T_XMAJOR |
>> + T_TILE4 | T_TILE64);
>> +static const struct blt_tiling_info
>> + atsm_xy_fast_copy = BLT_INFO(XY_FAST_COPY,
>> + T_LINEAR | T_TILE4 |
>> + T_TILE64);
>> +static const struct blt_tiling_info
>> + gen12_xy_block_copy = BLT_INFO(XY_BLOCK_COPY,
>> + T_LINEAR | T_YMAJOR);
>> +static const struct blt_tiling_info
>> + dg2_xy_block_copy = BLT_INFO(XY_BLOCK_COPY,
>> + T_LINEAR | T_XMAJOR |
>> + T_TILE4 | T_TILE64);
>> +static const struct blt_tiling_info
>> + atsm_xy_block_copy = BLT_INFO(XY_BLOCK_COPY,
>> + T_LINEAR | T_XMAJOR |
>> + T_TILE4 | T_TILE64);
>> +
>> +const struct blt_cmd_info pre_gen8_blt_info = {
>> + .supported_tiling = {
>> + [SRC_COPY] = &src_copy,
>> + [XY_SRC_COPY] = &pre_gen8_xy_src_copy
>> + }
>> +};
>> +
>> +const struct blt_cmd_info gen8_blt_info = {
>> + .supported_tiling = {
>> + [XY_SRC_COPY] = &gen8_xy_src_copy,
>> + }
>> +};
>> +
>> +const struct blt_cmd_info gen11_blt_info = {
>> + .supported_tiling = {
>> + [XY_SRC_COPY] = &gen8_xy_src_copy,
>> + [XY_FAST_COPY] = &gen11_xy_fast_copy,
>> + }
>> +};
>> +
>> +const struct blt_cmd_info gen12_blt_info = {
>> + .supported_tiling = {
>> + [XY_SRC_COPY] = &gen8_xy_src_copy,
>> + [XY_FAST_COPY] = &gen12_xy_fast_copy,
>> + [XY_BLOCK_COPY] = &gen12_xy_block_copy,
>> + }
>> +};
>> +
>> +const struct blt_cmd_info gen12_dg2_blt_info = {
>> + .supported_tiling = {
>> + [XY_SRC_COPY] = &gen8_xy_src_copy,
>> + [XY_FAST_COPY] = &dg2_xy_fast_copy,
>> + [XY_BLOCK_COPY] = &dg2_xy_block_copy,
>> + }
>> +};
>> +
>> +const struct blt_cmd_info gen12_atsm_blt_info = {
>> + .supported_tiling = {
>> + [XY_SRC_COPY] = &gen8_xy_src_copy,
>> + [XY_FAST_COPY] = &atsm_xy_fast_copy,
>> + [XY_BLOCK_COPY] = &atsm_xy_block_copy,
>> + }
>> +};
>
> This looks good, we can individually configure supported blt
> instructions.
>
>
>> +
>> +/**
>> + * blt_tiling_name:
>> + * @tiling: tiling id
>> + *
>> + * Returns:
>> + * name of @tiling passed. Useful to build test names.
>> + */
>> +const char *blt_tiling_name(enum blt_tiling_type tiling)
>> +{
>> + switch (tiling) {
>> + case T_LINEAR: return "linear";
>> + case T_XMAJOR: return "xmajor";
>> + case T_YMAJOR: return "ymajor";
>> + case T_TILE4: return "tile4";
>> + case T_TILE64: return "tile64";
>> + case T_YFMAJOR: return "yfmajor";
>> + default: return NULL;
>> + }
>> +}
>> +
>> +/**
>> + * blt_supports_command:
>> + * @info: Blitter command info struct
>> + * @cmd: Blitter command enum
>> + *
>> + * Checks if @info has an entry of supported tiling formats for @cmd command.
>> + *
>> + * Returns: true if it does, false otherwise
>> + */
>> +bool blt_supports_command(const struct blt_cmd_info *info,
>> + enum blt_cmd_type cmd)
>> +{
>> + igt_require_f(info, "No config found for the platform\n");
>> +
>> + return info->supported_tiling[cmd];
>> +}
>> +
>> +/**
>> + * blt_cmd_supports_tiling:
>> + * @info: Blitter command info struct
>> + * @cmd: Blitter command enum
>> + * @tiling: tiling format enum
>> + *
>> + * Checks if a @cmd entry of @info lists @tiling. It also returns false if
>> + * no information about the command is stored.
>> + *
>> + * Returns: true if it does, false otherwise
>> + */
>> +bool blt_cmd_supports_tiling(const struct blt_cmd_info *info,
>> + enum blt_cmd_type cmd,
>> + enum blt_tiling_type tiling)
>> +{
>> + struct blt_tiling_info const *tile_config;
>> +
>> + if (!info)
>> + return false;
>> +
>> + tile_config = info->supported_tiling[cmd];
>> +
>> + /* no config means no support for that tiling */
>> + if (!tile_config)
>> + return false;
>> +
>> + return tile_config->supported_tiling & tiling;
>> +}
>> +
>> +static const char *blt_cmd_name(enum blt_cmd_type cmd)
>> +{
>> + switch (cmd) {
>> + case SRC_COPY: return "SRC_COPY_BLT";
>> + case XY_SRC_COPY: return "XY_SRC_COPY_BLT";
>> + case XY_FAST_COPY: return "XY_FAST_COPY_BLT";
>> + case XY_BLOCK_COPY: return "XY_BLOCK_COPY_BLT";
>> + default: return NULL;
>> + }
>> +}
>> +
>> +/* Info dump functions */
>> +
>> +static void append_tile(uint32_t tile, char *tile_str)
>> +{
>> + char const *tile_name;
>> +
>> + if (tile) {
>> + tile_name = blt_tiling_name(tile);
>> + snprintf(tile_str + strlen(tile_str), strlen(tile_name) + 2, "%s ", tile_name);
>> + }
>> +}
>> +
>> +static void get_tiling_info(struct blt_cmd_info const *info, enum blt_cmd_type type, char *tile_str)
>> +{
>> + uint32_t mask;
>> + struct blt_tiling_info const *tiling = info->supported_tiling[type];
>> +
>> + if (tiling) {
>> + for (int i = 0; i < T_MAX_SHIFT; i++) {
>> + mask = 1 << i;
>> + append_tile(tiling->supported_tiling & mask, tile_str);
>> + }
>> + }
>> +
>> + tile_str[strlen(tile_str) - 1] = '\0';
>> +}
>> +
>> +/**
>> + * dump_devid_blt_info:
>> + * @info: pointer to the Blitter command info struct
>> + *
>> + * Prints a list of supported commands with available tiling formats.
>> + *
>> + */
>> +void blt_dump_blt_cmd_info(struct blt_cmd_info const *info)
>> +{
>> + char tiling_str[TILE_STR_MAX];
>> + char ln_str[BLT_STR_MAX];
>> + char const *blt_type_str;
>> + const char *ln_intro = " * ";
>> +
>> + if (!info) {
>> + igt_warn("No config available\n");
>> + return;
>> + }
>> +
>> + igt_info("Supported blitter commands:\n");
>> +
>> + for (int cmd = 0; cmd < __MAX_CMD; cmd++) {
>> + if (info->supported_tiling[cmd]) {
>> + memset(ln_str, '\0', sizeof(char) * BLT_STR_MAX);
>> + memset(tiling_str, '\0', sizeof(char) * TILE_STR_MAX);
>> +
>> + blt_type_str = blt_cmd_name(cmd);
>> +
>> + snprintf(ln_str,
>> + strlen(ln_intro) + strlen(blt_type_str) + 1,
>> + "%s%s", ln_intro, blt_type_str);
>> +
>> + get_tiling_info(info, cmd, tiling_str);
>> +
>> + snprintf(ln_str + strlen(ln_str),
>> + strlen(tiling_str) + 5,
>> + " [%s]", tiling_str);
>> +
>> + igt_info("%s\n", ln_str);
>> + }
>> + }
>> +}
>
> Looks a little bit overengineered, can't you just use asprintf()?
Well, probably because I haven't used it before ;) Sounds reasonable,
thanks.
>
>
>
>> +
>> diff --git a/lib/i915/intel_blt_info.h b/lib/i915/intel_blt_info.h
>> new file mode 100644
>> index 00000000..39fa5448
>> --- /dev/null
>> +++ b/lib/i915/intel_blt_info.h
>> @@ -0,0 +1,98 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#ifndef BLT_TILING_H
>> +#define BLT_TILING_H
>> +
>> +#include <stdbool.h>
>> +#include <stddef.h>
>> +#include <stdint.h>
>> +#include "igt_core.h"
>> +
>> +/**
>> + * SECTION:intel_blt_info
>> + * @short_description: blitter library to query for available commands and tiling formats
>> + * @title: Intel blitter info
>> + * @include: intel_blt_info.h
>> + *
>> + * # Introduction
>> + *
>> + * When we do a blitter copy, a number of different tiling formats can be used.
>> + * The list of available formats and commands varies between generations, in
>> + * some cases even within the generation (e.g. block copy tiling formats offered
>> + * by TGL vs DG2). Such information is required by different tests, so it's
>> + * beneficial to store it in one place – in intel_blt_info, a blitter library
>> + * that describes available commands with a list of supported tiling formats.
>> + * They are encapsulated in static `blt_cmd_info` instances, each of them
>> + * defined per generation or platforms.
>> + *
>> + * Tiling formats here are described by blt_tiling_type enum, which consists of
>> + * bit flags, that can be combined:
>> + * `.supported_tiling = T_LINEAR | T_XMAJOR | T_YMAJOR`
>> + *
>> + * Because of their non-linear nature, it is recommended to use
>> + * #for_each_tiling() macro when writing tests that iterate over tiling formats.
>> + *
>> + * # Usage
>> + *
>> + * - blt_supports_command(info, cmd) - checks if a blt_cmd_type instance has an
>> + * entry for the command
>> + * - blt_cmd_supports_tiling(info, cmd, tiling) - checks if a tiling format is
>> + * supported by the command. Can
>> + * also handle the case when the
>> + * command is not available on
>> + * the platform.
>> + *
>> + * These general checks can be wrapped in a command or tiling specific
>> + * check, provided by other libraries.
>> + *
>> + */
>> +
>> +enum blt_tiling_type {
>> + T_LINEAR = (1),
>> + T_XMAJOR = (1 << 1),
>> + T_YMAJOR = (1 << 2),
>> + T_TILE4 = (1 << 3),
>> + T_TILE64 = (1 << 4),
>> + T_YFMAJOR = (1 << 5),
>> +};
>
> What I don't like here is sparse enum. I would just want to have contigues
> values and hide the implementation in bits to .c file.
I see now how bug-prone such enum is... The initialization part with
BIT(X) isn't perfect either, but still, it's better. T_LINEAR is going
to be 0 here.
All the best,
Karolina
>
> --
> Zbigniew
>
>> +
>> +enum blt_cmd_type {
>> + SRC_COPY,
>> + XY_SRC_COPY,
>> + XY_FAST_COPY,
>> + XY_BLOCK_COPY,
>> + __MAX_CMD
>> +};
>> +
>> +struct blt_tiling_info {
>> + enum blt_cmd_type blt_cmd_type;
>> + uint32_t supported_tiling;
>> +};
>> +
>> +struct blt_cmd_info {
>> + struct blt_tiling_info const *supported_tiling[__MAX_CMD];
>> +};
>> +
>> +const struct blt_cmd_info pre_gen8_blt_info;
>> +const struct blt_cmd_info gen8_blt_info;
>> +const struct blt_cmd_info gen11_blt_info;
>> +const struct blt_cmd_info gen12_blt_info;
>> +const struct blt_cmd_info gen12_dg2_blt_info;
>> +const struct blt_cmd_info gen12_atsm_blt_info;
>> +
>> +#define for_each_tiling(__tiling) \
>> + for (__tiling = T_LINEAR; __tiling <= T_YFMAJOR; __tiling = __tiling << 1)
>> +
>> +bool blt_supports_command(const struct blt_cmd_info *info,
>> + enum blt_cmd_type cmd);
>> +bool blt_cmd_supports_tiling(const struct blt_cmd_info *info,
>> + enum blt_cmd_type cmd,
>> + enum blt_tiling_type tiling);
>> +
>> +void blt_dump_blt_cmd_info(struct blt_cmd_info const *info);
>> +const char *blt_tiling_name(enum blt_tiling_type tiling);
>> +
>> +#endif // BLT_TILING_H
>> diff --git a/lib/meson.build b/lib/meson.build
>> index c79e3e95..2b2dbbca 100644
>> --- a/lib/meson.build
>> +++ b/lib/meson.build
>> @@ -11,6 +11,7 @@ lib_sources = [
>> 'i915/gem_ring.c',
>> 'i915/gem_mman.c',
>> 'i915/gem_vm.c',
>> + 'i915/intel_blt_info.c',
>> 'i915/intel_decode.c',
>> 'i915/intel_memory_region.c',
>> 'i915/intel_mocs.c',
>> diff --git a/tests/i915/gem_ccs.c b/tests/i915/gem_ccs.c
>> index 751f65e6..ed60b81c 100644
>> --- a/tests/i915/gem_ccs.c
>> +++ b/tests/i915/gem_ccs.c
>> @@ -46,7 +46,7 @@ struct test_config {
>>
>> static void set_object(struct blt_copy_object *obj,
>> uint32_t handle, uint64_t size, uint32_t region,
>> - uint8_t mocs, enum blt_tiling tiling,
>> + uint8_t mocs, enum blt_tiling_type tiling,
>> enum blt_compression compression,
>> enum blt_compression_type compression_type)
>> {
>> @@ -108,7 +108,7 @@ static void set_surf_object(struct blt_ctrl_surf_copy_object *obj,
>> static struct blt_copy_object *
>> create_object(int i915, uint32_t region,
>> uint32_t width, uint32_t height, uint32_t bpp, uint8_t mocs,
>> - enum blt_tiling tiling,
>> + enum blt_tiling_type tiling,
>> enum blt_compression compression,
>> enum blt_compression_type compression_type,
>> bool create_mapping)
>> @@ -374,7 +374,7 @@ static void block_copy(int i915,
>> const intel_ctx_t *ctx,
>> const struct intel_execution_engine2 *e,
>> uint32_t region1, uint32_t region2,
>> - enum blt_tiling mid_tiling,
>> + enum blt_tiling_type mid_tiling,
>> const struct test_config *config)
>> {
>> struct blt_copy_data blt = {};
>> @@ -492,7 +492,7 @@ static void block_multicopy(int i915,
>> const intel_ctx_t *ctx,
>> const struct intel_execution_engine2 *e,
>> uint32_t region1, uint32_t region2,
>> - enum blt_tiling mid_tiling,
>> + enum blt_tiling_type mid_tiling,
>> const struct test_config *config)
>> {
>> struct blt_copy3_data blt3 = {};
>> @@ -581,7 +581,7 @@ static const struct {
>> const char *suffix;
>> void (*copyfn)(int, const intel_ctx_t *,
>> const struct intel_execution_engine2 *,
>> - uint32_t, uint32_t, enum blt_tiling,
>> + uint32_t, uint32_t, enum blt_tiling_type,
>> const struct test_config *);
>> } copyfns[] = {
>> [BLOCK_COPY] = { "", block_copy },
>> @@ -596,6 +596,7 @@ static void block_copy_test(int i915,
>> {
>> struct igt_collection *regions;
>> const struct intel_execution_engine2 *e;
>> + int tiling;
>>
>> if (config->compression && !blt_supports_compression(i915))
>> return;
>> @@ -603,7 +604,7 @@ static void block_copy_test(int i915,
>> if (config->inplace && !config->compression)
>> return;
>>
>> - for (int tiling = T_LINEAR; tiling <= T_TILE64; tiling++) {
>> + for_each_tiling(tiling) {
>> if (!blt_supports_tiling(i915, tiling) ||
>> (param.tiling >= 0 && param.tiling != tiling))
>> continue;
>> @@ -663,7 +664,7 @@ static int opt_handler(int opt, int opt_index, void *data)
>> igt_debug("Print surface info: %d\n", param.print_surface_info);
>> break;
>> case 't':
>> - param.tiling = atoi(optarg);
>> + param.tiling = 1 << atoi(optarg);
>> igt_debug("Tiling: %d\n", param.tiling);
>> break;
>> case 'W':
>> diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
>> index 75121d41..9388d4de 100644
>> --- a/tests/i915/gem_lmem_swapping.c
>> +++ b/tests/i915/gem_lmem_swapping.c
>> @@ -78,7 +78,7 @@ struct object {
>>
>> static void set_object(struct blt_copy_object *obj,
>> uint32_t handle, uint64_t size, uint32_t region,
>> - uint8_t mocs, enum blt_tiling tiling,
>> + uint8_t mocs, enum blt_tiling_type tiling,
>> enum blt_compression compression,
>> enum blt_compression_type compression_type)
>> {
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 5/6] tests/gem_exercise_blt: Add fast-copy test
2023-01-09 15:34 ` Zbigniew Kempczyński
@ 2023-01-10 6:57 ` Karolina Stolarek
0 siblings, 0 replies; 21+ messages in thread
From: Karolina Stolarek @ 2023-01-10 6:57 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 09.01.2023 16:34, Zbigniew Kempczyński wrote:
> On Fri, Dec 23, 2022 at 12:13:50PM +0100, Karolina Stolarek wrote:
>> Exercise a basic scenario with two block copies in separate batch
>> buffers.
>>
>> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
>> ---
>> tests/i915/gem_exercise_blt.c | 216 ++++++++++++++++++++++++++++++++++
>> tests/meson.build | 1 +
>> 2 files changed, 217 insertions(+)
>> create mode 100644 tests/i915/gem_exercise_blt.c
>>
>> diff --git a/tests/i915/gem_exercise_blt.c b/tests/i915/gem_exercise_blt.c
>> new file mode 100644
>> index 00000000..67a8b660
>> --- /dev/null
>> +++ b/tests/i915/gem_exercise_blt.c
>> @@ -0,0 +1,216 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#include "igt.h"
>> +#include "drm.h"
>> +#include "i915/gem.h"
>> +#include "i915/gem_create.h"
>> +#include "lib/intel_chipset.h"
>> +#include "i915/i915_blt.h"
>> +#include "i915/intel_mocs.h"
>> +
>> +IGT_TEST_DESCRIPTION("Exercise blitter commands");
>> +
>> +static struct param {
>> + int tiling;
>> + bool write_png;
>> + bool print_bb;
>> + bool print_surface_info;
>> + int width;
>> + int height;
>> +} param = {
>> + .tiling = -1,
>> + .write_png = false,
>> + .print_bb = false,
>> + .print_surface_info = false,
>> + .width = 512,
>> + .height = 512,
>> +};
>> +
>> +#define PRINT_SURFACE_INFO(name, obj) do { \
>> + if (param.print_surface_info) \
>> + blt_surface_info((name), (obj)); } while (0)
>> +
>> +#define WRITE_PNG(fd, id, name, obj, w, h) do { \
>> + if (param.write_png) \
>> + blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
>> +
>> +static void fast_copy(int i915, const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e,
>> + uint32_t region1, uint32_t region2,
>> + enum blt_tiling_type mid_tiling)
>> +{
>> + struct blt_copy_data blt = {};
>> + struct blt_copy_object *src, *mid, *dst;
>> + const uint32_t bpp = 32;
>> + uint64_t bb_size = 4096;
>> + uint64_t ahnd = intel_allocator_open_full(i915, ctx->id, 0, 0,
>> + INTEL_ALLOCATOR_SIMPLE,
>> + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
>> + uint32_t bb;
>> + uint32_t width = param.width, height = param.height;
>> + int result;
>> +
>> + igt_assert(__gem_create_in_memory_regions(i915, &bb, &bb_size, region1) == 0);
>> +
>> + src = blt_create_object(i915, region1, width, height, bpp, 0,
>> + T_LINEAR, COMPRESSION_DISABLED, 0, true);
>> + mid = blt_create_object(i915, region2, width, height, bpp, 0,
>> + mid_tiling, COMPRESSION_DISABLED, 0, true);
>> + dst = blt_create_object(i915, region1, width, height, bpp, 0,
>> + T_LINEAR, COMPRESSION_DISABLED, 0, true);
>> + igt_assert(src->size == dst->size);
>> +
>> + blt_surface_fill_rect(i915, src, width, height);
>> + WRITE_PNG(i915, mid_tiling, "src", src, width, height);
>> +
>> + memset(&blt, 0, sizeof(blt));
>> + blt.color_depth = CD_32bit;
>> + blt.print_bb = param.print_bb;
>> + blt_set_copy_object(&blt.src, src);
>> + blt_set_copy_object(&blt.dst, mid);
>> + blt_set_batch(&blt.bb, bb, bb_size, region1);
>> +
>> + blt_fast_copy(i915, ctx, e, ahnd, &blt);
>> + gem_sync(i915, mid->handle);
>> +
>> + WRITE_PNG(i915, mid_tiling, "src", &blt.src, width, height);
>
> You're writing src png second time. Some pngs will overwrite when
> different regions are in use, but that's not a problem for me.
> Dumping pngs is for debugging purposes so direct subtest selection
> will narrow this to interesting case.
Whoops, it slipped through the cracks, didn't mean to do that!
>
> I haven't spotted other issues, with above fixed:
>
> Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Thanks,
Karolina
>
> --
> Zbigniew
>
>> + WRITE_PNG(i915, mid_tiling, "mid", &blt.dst, width, height);
>> +
>> + memset(&blt, 0, sizeof(blt));
>> + blt.color_depth = CD_32bit;
>> + blt.print_bb = param.print_bb;
>> + blt_set_copy_object(&blt.src, mid);
>> + blt_set_copy_object(&blt.dst, dst);
>> + blt_set_batch(&blt.bb, bb, bb_size, region1);
>> +
>> + blt_fast_copy(i915, ctx, e, ahnd, &blt);
>> + gem_sync(i915, blt.dst.handle);
>> +
>> + WRITE_PNG(i915, mid_tiling, "dst", &blt.dst, width, height);
>> +
>> + result = memcmp(src->ptr, blt.dst.ptr, src->size);
>> +
>> + blt_destroy_object(i915, src);
>> + blt_destroy_object(i915, mid);
>> + blt_destroy_object(i915, dst);
>> + gem_close(i915, bb);
>> + put_ahnd(ahnd);
>> +
>> + igt_assert_f(!result, "source and destination surfaces differs!\n");
>> +}
>> +
>> +static void fast_copy_test(int i915,
>> + const intel_ctx_t *ctx,
>> + struct igt_collection *set)
>> +{
>> + struct igt_collection *regions;
>> + const struct intel_execution_engine2 *e;
>> + int tiling;
>> +
>> + for_each_tiling(tiling) {
>> + if (!blt_fast_copy_supports_tiling(i915, tiling))
>> + continue;
>> +
>> + for_each_ctx_engine(i915, ctx, e) {
>> + if (e->class != I915_ENGINE_CLASS_COPY)
>> + continue;
>> + for_each_variation_r(regions, 2, set) {
>> + uint32_t region1, region2;
>> + char *regtxt;
>> +
>> + region1 = igt_collection_get_value(regions, 0);
>> + region2 = igt_collection_get_value(regions, 1);
>> + regtxt = memregion_dynamic_subtest_name(regions);
>> +
>> + igt_dynamic_f("%s-%s",
>> + blt_tiling_name(tiling), regtxt) {
>> + fast_copy(i915, ctx, e,
>> + region1, region2,
>> + tiling);
>> + }
>> +
>> + free(regtxt);
>> + }
>> + }
>> + }
>> +}
>> +
>> +static int opt_handler(int opt, int opt_index, void *data)
>> +{
>> + switch (opt) {
>> + case 'b':
>> + param.print_bb = true;
>> + igt_debug("Print bb: %d\n", param.print_bb);
>> + break;
>> + case 'p':
>> + param.write_png = true;
>> + igt_debug("Write png: %d\n", param.write_png);
>> + break;
>> + case 's':
>> + param.print_surface_info = true;
>> + igt_debug("Print surface info: %d\n", param.print_surface_info);
>> + break;
>> + case 't':
>> + param.tiling = 1 << atoi(optarg);
>> + igt_debug("Tiling: %d\n", param.tiling);
>> + break;
>> + case 'W':
>> + param.width = atoi(optarg);
>> + igt_debug("Width: %d\n", param.width);
>> + break;
>> + case 'H':
>> + param.height = atoi(optarg);
>> + igt_debug("Height: %d\n", param.height);
>> + break;
>> + default:
>> + return IGT_OPT_HANDLER_ERROR;
>> + }
>> +
>> + return IGT_OPT_HANDLER_SUCCESS;
>> +}
>> +
>> +const char *help_str =
>> + " -b\tPrint bb\n"
>> + " -p\tWrite PNG\n"
>> + " -s\tPrint surface info\n"
>> + " -t\tTiling format (0 - linear, 1 - XMAJOR, 2 - YMAJOR, 3 - TILE4, 4 - TILE64, 5 - YFMAJOR)\n"
>> + " -W\tWidth (default 512)\n"
>> + " -H\tHeight (default 512)"
>> + ;
>> +
>> +igt_main_args("b:pst:W:H:", NULL, help_str, opt_handler, NULL)
>> +{
>> + struct drm_i915_query_memory_regions *query_info;
>> + struct igt_collection *set;
>> + const intel_ctx_t *ctx;
>> + int i915;
>> + igt_hang_t hang;
>> +
>> + igt_fixture {
>> + i915 = drm_open_driver(DRIVER_INTEL);
>> + igt_require_gem(i915);
>> + igt_require(blt_has_fast_copy(i915));
>> +
>> + query_info = gem_get_query_memory_regions(i915);
>> + igt_require(query_info);
>> +
>> + set = get_memory_region_set(query_info,
>> + I915_SYSTEM_MEMORY,
>> + I915_DEVICE_MEMORY);
>> + ctx = intel_ctx_create_all_physical(i915);
>> + hang = igt_allow_hang(i915, ctx->id, 0);
>> + }
>> +
>> + igt_describe("Check fast-copy blit");
>> + igt_subtest_with_dynamic("fast-copy") {
>> + fast_copy_test(i915, ctx, set);
>> + }
>> +
>> + igt_fixture {
>> + igt_disallow_hang(i915, hang);
>> + close(i915);
>> + }
>> +}
>> diff --git a/tests/meson.build b/tests/meson.build
>> index cb428998..3c8a3ba3 100644
>> --- a/tests/meson.build
>> +++ b/tests/meson.build
>> @@ -129,6 +129,7 @@ i915_progs = [
>> 'gem_exec_nop',
>> 'gem_exec_parallel',
>> 'gem_exec_params',
>> + 'gem_exercise_blt',
>> 'gen7_exec_parse',
>> 'gen9_exec_parse',
>> 'gem_exec_reloc',
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 6/6] tests/gem_exercise_blt: Add fast-copy-emit test
2023-01-09 15:38 ` Zbigniew Kempczyński
@ 2023-01-10 6:57 ` Karolina Stolarek
0 siblings, 0 replies; 21+ messages in thread
From: Karolina Stolarek @ 2023-01-10 6:57 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On 09.01.2023 16:38, Zbigniew Kempczyński wrote:
> On Fri, Dec 23, 2022 at 12:13:51PM +0100, Karolina Stolarek wrote:
>> Add a subtest where two fast copy commands are executed within the
>> single batch buffer.
>>
>> Signed-off-by: Karolina Stolarek <karolina.stolarek@intel.com>
>> ---
>> tests/i915/gem_exercise_blt.c | 190 ++++++++++++++++++++++++++++++++--
>> 1 file changed, 184 insertions(+), 6 deletions(-)
>>
>> diff --git a/tests/i915/gem_exercise_blt.c b/tests/i915/gem_exercise_blt.c
>> index 67a8b660..b8bfc436 100644
>> --- a/tests/i915/gem_exercise_blt.c
>> +++ b/tests/i915/gem_exercise_blt.c
>> @@ -37,6 +37,146 @@ static struct param {
>> if (param.write_png) \
>> blt_surface_to_png((fd), (id), (name), (obj), (w), (h)); } while (0)
>>
>> +struct blt_fast_copy_data {
>> + int i915;
>> + struct blt_copy_object src;
>> + struct blt_copy_object mid;
>> + struct blt_copy_object dst;
>> +
>> + struct blt_copy_batch bb;
>> + enum blt_color_depth color_depth;
>> +
>> + /* debug stuff */
>> + bool print_bb;
>> +};
>> +
>> +static int fast_copy_one_bb(int i915,
>> + const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e,
>> + uint64_t ahnd,
>> + const struct blt_fast_copy_data *blt)
>> +{
>> + struct drm_i915_gem_execbuffer2 execbuf = {};
>> + struct drm_i915_gem_exec_object2 obj[4] = {};
>> + struct blt_copy_data blt_tmp;
>> + uint64_t src_offset, mid_offset, dst_offset, bb_offset, alignment;
>> + uint64_t bb_pos = 0;
>> + uint32_t flags;
>> + int ret;
>> +
>> + alignment = gem_detect_safe_alignment(i915);
>> +
>> + src_offset = get_offset(ahnd, blt->src.handle, blt->src.size, alignment);
>> + mid_offset = get_offset(ahnd, blt->mid.handle, blt->mid.size, alignment);
>> + dst_offset = get_offset(ahnd, blt->dst.handle, blt->dst.size, alignment);
>> + bb_offset = get_offset(ahnd, blt->bb.handle, blt->bb.size, alignment);
>> +
>> + /* First blit */
>> + memset(&blt_tmp, 0, sizeof(blt_tmp));
>> + blt_tmp.src = blt->src;
>> + blt_tmp.dst = blt->mid;
>> + blt_tmp.bb = blt->bb;
>> + blt_tmp.color_depth = blt->color_depth;
>> + blt_tmp.print_bb = blt->print_bb;
>> + bb_pos = emit_blt_fast_copy(i915, ahnd, &blt_tmp, bb_pos, false);
>> +
>> + /* Second blit */
>> + memset(&blt_tmp, 0, sizeof(blt_tmp));
>> + blt_tmp.src = blt->mid;
>> + blt_tmp.dst = blt->dst;
>> + blt_tmp.bb = blt->bb;
>> + blt_tmp.color_depth = blt->color_depth;
>> + blt_tmp.print_bb = blt->print_bb;
>> + bb_pos = emit_blt_fast_copy(i915, ahnd, &blt_tmp, bb_pos, true);
>
> Pipelined blits? Nice!
>
>> +
>> + flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
>> +
>> + obj[0].handle = blt->src.handle;
>> + obj[0].offset = CANONICAL(src_offset);
>> + obj[0].flags = flags;
>> +
>> + obj[1].handle = blt->mid.handle;
>> + obj[1].offset = CANONICAL(mid_offset);
>> + obj[1].flags = flags | EXEC_OBJECT_WRITE;
>> +
>> + obj[2].handle = blt->dst.handle;
>> + obj[2].offset = CANONICAL(dst_offset);
>> + obj[2].flags = flags;
>> +
>> + obj[3].handle = blt->bb.handle;
>> + obj[3].offset = CANONICAL(bb_offset);
>> + obj[3].flags = flags;
>> +
>> + execbuf.buffer_count = 4;
>> + execbuf.buffers_ptr = to_user_pointer(obj);
>> + execbuf.rsvd1 = ctx ? ctx->id : 0;
>> + execbuf.flags = e ? e->flags : I915_EXEC_BLT;
>> + ret = __gem_execbuf(i915, &execbuf);
>> +
>> + gem_sync(i915, blt->bb.handle);
>> +
>> + return ret;
>> +}
>> +
>> +static void fast_copy_emit(int i915, const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e,
>> + uint32_t region1, uint32_t region2,
>> + enum blt_tiling_type mid_tiling)
>> +{
>> + struct blt_fast_copy_data blt = {};
>> + struct blt_copy_object *src, *mid, *dst;
>> + const uint32_t bpp = 32;
>> + uint64_t bb_size = 4096;
>> + uint64_t ahnd = intel_allocator_open_full(i915, ctx->id, 0, 0,
>> + INTEL_ALLOCATOR_SIMPLE,
>> + ALLOC_STRATEGY_LOW_TO_HIGH, 0);
>> + uint32_t bb, width = param.width, height = param.height;
>> + int result;
>> +
>> + igt_assert(__gem_create_in_memory_regions(i915, &bb, &bb_size, region1) == 0);
>> +
>> + src = blt_create_object(i915, region1, width, height, bpp, 0,
>> + T_LINEAR, COMPRESSION_DISABLED, 0, true);
>> + mid = blt_create_object(i915, region2, width, height, bpp, 0,
>> + mid_tiling, COMPRESSION_DISABLED, 0, true);
>> + dst = blt_create_object(i915, region1, width, height, bpp, 0,
>> + T_LINEAR, COMPRESSION_DISABLED, 0, true);
>> + igt_assert(src->size == dst->size);
>> +
>> + PRINT_SURFACE_INFO("src", src);
>> + PRINT_SURFACE_INFO("mid", mid);
>> + PRINT_SURFACE_INFO("dst", dst);
>> +
>> + blt_surface_fill_rect(i915, src, width, height);
>> + WRITE_PNG(i915, mid_tiling, "src", src, width, height);
>> +
>> + memset(&blt, 0, sizeof(blt));
>> + blt.color_depth = CD_32bit;
>> + blt.print_bb = param.print_bb;
>> + blt_set_copy_object(&blt.src, src);
>> + blt_set_copy_object(&blt.mid, mid);
>> + blt_set_copy_object(&blt.dst, dst);
>> + blt_set_batch(&blt.bb, bb, bb_size, region1);
>> +
>> + fast_copy_one_bb(i915, ctx, e, ahnd, &blt);
>> + gem_sync(i915, blt.dst.handle);
>> +
>> + WRITE_PNG(i915, mid_tiling, "mid", &blt.mid, width, height);
>> + WRITE_PNG(i915, mid_tiling, "dst", &blt.dst, width, height);
>> +
>> + result = memcmp(src->ptr, blt.dst.ptr, src->size);
>> +
>> + blt_destroy_object(i915, src);
>> + blt_destroy_object(i915, mid);
>> + blt_destroy_object(i915, dst);
>> + gem_close(i915, bb);
>> + put_ahnd(ahnd);
>> +
>> + munmap(&bb, bb_size);
>> +
>> + igt_assert_f(!result, "source and destination surfaces differs!\n");
>> +}
>> +
>> static void fast_copy(int i915, const intel_ctx_t *ctx,
>> const struct intel_execution_engine2 *e,
>> uint32_t region1, uint32_t region2,
>> @@ -102,12 +242,42 @@ static void fast_copy(int i915, const intel_ctx_t *ctx,
>> igt_assert_f(!result, "source and destination surfaces differs!\n");
>> }
>>
>> +enum fast_copy_func {
>> + FAST_COPY,
>> + FAST_COPY_EMIT
>> +};
>> +
>> +static char
>> + *full_subtest_str(char *regtxt, enum blt_tiling_type tiling,
>> + enum fast_copy_func func)
>> +{
>> + const char *multi_str = "emit";
>> + char const *tile_str = blt_tiling_name(tiling);
>> + char *name;
>> + uint32_t len, sub_len;
>> +
>> + len = strlen(regtxt) + strlen(tile_str) + strlen(multi_str) + 2;
>
> Similar to other patch - looks overengineered. Maybe asprintf() will help
> you to avoid calling strlen().
Yeah, I just didn't know how to do it better at that time. I'll give
asprintf() a try.
Many thanks,
Karolina
>
> --
> Zbigniew
>
>> + name = malloc(len * sizeof(char));
>> + igt_assert(name);
>> +
>> + sub_len = snprintf(name, len, "%s-%s", tile_str, regtxt);
>> +
>> + if (func == FAST_COPY_EMIT)
>> + snprintf(name + sub_len, len, "-%s", multi_str);
>> +
>> + return name;
>> +}
>> +
>> static void fast_copy_test(int i915,
>> const intel_ctx_t *ctx,
>> - struct igt_collection *set)
>> + struct igt_collection *set,
>> + enum fast_copy_func func)
>> {
>> struct igt_collection *regions;
>> const struct intel_execution_engine2 *e;
>> + void (*copy_func)(int i915, const intel_ctx_t *ctx,
>> + const struct intel_execution_engine2 *e,
>> + uint32_t r1, uint32_t r2, enum blt_tiling_type tiling);
>> int tiling;
>>
>> for_each_tiling(tiling) {
>> @@ -119,20 +289,23 @@ static void fast_copy_test(int i915,
>> continue;
>> for_each_variation_r(regions, 2, set) {
>> uint32_t region1, region2;
>> - char *regtxt;
>> + char *regtxt, *test_name;
>>
>> region1 = igt_collection_get_value(regions, 0);
>> region2 = igt_collection_get_value(regions, 1);
>> +
>> + copy_func = (func == FAST_COPY) ? fast_copy : fast_copy_emit;
>> regtxt = memregion_dynamic_subtest_name(regions);
>> + test_name = full_subtest_str(regtxt, tiling, func);
>>
>> - igt_dynamic_f("%s-%s",
>> - blt_tiling_name(tiling), regtxt) {
>> - fast_copy(i915, ctx, e,
>> + igt_dynamic_f("%s", test_name) {
>> + copy_func(i915, ctx, e,
>> region1, region2,
>> tiling);
>> }
>>
>> free(regtxt);
>> + free(test_name);
>> }
>> }
>> }
>> @@ -206,7 +379,12 @@ igt_main_args("b:pst:W:H:", NULL, help_str, opt_handler, NULL)
>>
>> igt_describe("Check fast-copy blit");
>> igt_subtest_with_dynamic("fast-copy") {
>> - fast_copy_test(i915, ctx, set);
>> + fast_copy_test(i915, ctx, set, FAST_COPY);
>> + }
>> +
>> + igt_describe("Check multiple fast-copy in one batch");
>> + igt_subtest_with_dynamic("fast-copy-emit") {
>> + fast_copy_test(i915, ctx, set, FAST_COPY_EMIT);
>> }
>>
>> igt_fixture {
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2023-01-10 6:58 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-23 11:13 [igt-dev] [PATCH i-g-t v2 0/6] Introduce blt_cmd_info struct Karolina Stolarek
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 1/6] i915/lib: Add new library for blitter and tiling formats Karolina Stolarek
2023-01-09 12:49 ` Zbigniew Kempczyński
2023-01-10 6:55 ` Karolina Stolarek
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 2/6] lib: Update platform definitions with blitter information Karolina Stolarek
2022-12-28 16:41 ` Kamil Konieczny
2023-01-03 9:17 ` Karolina Stolarek
2023-01-09 15:24 ` Zbigniew Kempczyński
2023-01-09 15:20 ` Zbigniew Kempczyński
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 3/6] lib/i915_blt: Check for Tile-YF in fast_copy Karolina Stolarek
2023-01-09 15:27 ` Zbigniew Kempczyński
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 4/6] lib/i915_blt: Add common functions for blt_copy_object Karolina Stolarek
2023-01-09 15:29 ` Zbigniew Kempczyński
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 5/6] tests/gem_exercise_blt: Add fast-copy test Karolina Stolarek
2023-01-09 15:34 ` Zbigniew Kempczyński
2023-01-10 6:57 ` Karolina Stolarek
2022-12-23 11:13 ` [igt-dev] [PATCH i-g-t v2 6/6] tests/gem_exercise_blt: Add fast-copy-emit test Karolina Stolarek
2023-01-09 15:38 ` Zbigniew Kempczyński
2023-01-10 6:57 ` Karolina Stolarek
2022-12-23 12:04 ` [igt-dev] ✓ Fi.CI.BAT: success for Introduce blt_cmd_info struct (rev2) Patchwork
2022-12-23 13:24 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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