* [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
@ 2023-01-12 9:27 Chaitanya Kumar Borah
2023-01-12 9:27 ` [Intel-gfx] [RFC v2 1/2] drm/i915: Add sub platform for 480MHz CDCLK step Chaitanya Kumar Borah
` (4 more replies)
0 siblings, 5 replies; 17+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-12 9:27 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have an RPL-U
device id. This particular step is to support 120Hz panels
more efficiently.
This patchset adds a new table to include this new CDCLK
step. Details can be found in BSpec entry 55409.
Create a new sub-platform to identify RPL-U which will enable
us to make the differentiation during CDCLK initialization.
Furthermore, we need to make a distinction between ES (Engineering
Sample) and QS (Quality Sample) parts as this change comes only
to QS parts. This version of the patch does not include this change
as we are yet to make a decision if this particular part needs
to be upstreamed.(see comments on revision 2)
Chaitanya Kumar Borah (2):
drm/i915: Add sub platform for 480MHz CDCLK step
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 8 +++++++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
include/drm/i915_pciids.h | 11 +++++----
6 files changed, 46 insertions(+), 4 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [RFC v2 1/2] drm/i915: Add sub platform for 480MHz CDCLK step
2023-01-12 9:27 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
@ 2023-01-12 9:27 ` Chaitanya Kumar Borah
2023-01-12 11:03 ` Jani Nikula
2023-01-12 9:27 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
` (3 subsequent siblings)
4 siblings, 1 reply; 17+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-12 9:27 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
Add a new sub platform INTEL_SUBPLATFORM_480CDCLK to identify
device ids that need the 480MHz CDCLK step. Separate out RPLU
device ids and add them to both RPL and 480CDCLK subplatforms.
v2: (Matt)
- Sort PCI-IDs numerically
- Name the sub-platform to accurately depict what it is for
- Make RPL-U part of RPL subplatform
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 8 ++++++++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
include/drm/i915_pciids.h | 11 +++++++----
5 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 48fd82722f12..fc5518314598 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
#define IS_ADLP_RPLP(dev_priv) \
IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
+#define IS_ADLP_WITH_480CDCLK(dev_priv) \
+ IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_480CDCLK)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv) \
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 6cc65079b18d..e9f3b99b3e00 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1234,6 +1234,7 @@ static const struct pci_device_id pciidlist[] = {
INTEL_DG1_IDS(&dg1_info),
INTEL_RPLS_IDS(&adl_s_info),
INTEL_RPLP_IDS(&adl_p_info),
+ INTEL_RPLU_IDS(&adl_p_info),
INTEL_DG2_IDS(&dg2_info),
INTEL_ATS_M_IDS(&ats_m_info),
INTEL_MTL_IDS(&mtl_info),
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 849baf6c3b3c..a1732ad519fb 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -199,6 +199,11 @@ static const u16 subplatform_n_ids[] = {
static const u16 subplatform_rpl_ids[] = {
INTEL_RPLS_IDS(0),
INTEL_RPLP_IDS(0),
+ INTEL_RPLU_IDS(0)
+};
+
+static const u16 subplatform_480cdclk_ids[] = {
+ INTEL_RPLU_IDS(0),
};
static const u16 subplatform_g10_ids[] = {
@@ -268,6 +273,9 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
} else if (find_devid(devid, subplatform_rpl_ids,
ARRAY_SIZE(subplatform_rpl_ids))) {
mask = BIT(INTEL_SUBPLATFORM_RPL);
+ if (find_devid(devid, subplatform_480cdclk_ids,
+ ARRAY_SIZE(subplatform_480cdclk_ids)))
+ mask |= BIT(INTEL_SUBPLATFORM_480CDCLK);
} else if (find_devid(devid, subplatform_g10_ids,
ARRAY_SIZE(subplatform_g10_ids))) {
mask = BIT(INTEL_SUBPLATFORM_G10);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index d588e5fd2eea..4f488c900273 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -127,6 +127,8 @@ enum intel_platform {
* bit set
*/
#define INTEL_SUBPLATFORM_N 1
+/* Sub Platform with 480MHz CDCLK step */
+#define INTEL_SUBPLATFORM_480CDCLK 2
/* MTL */
#define INTEL_SUBPLATFORM_M 0
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 4a4c190f7698..758be5fb09a2 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -684,14 +684,17 @@
INTEL_VGA_DEVICE(0xA78A, info), \
INTEL_VGA_DEVICE(0xA78B, info)
+/* RPL-U */
+#define INTEL_RPLU_IDS(info) \
+ INTEL_VGA_DEVICE(0xA721, info), \
+ INTEL_VGA_DEVICE(0xA7A1, info), \
+ INTEL_VGA_DEVICE(0xA7A9, info)
+
/* RPL-P */
#define INTEL_RPLP_IDS(info) \
INTEL_VGA_DEVICE(0xA720, info), \
- INTEL_VGA_DEVICE(0xA721, info), \
INTEL_VGA_DEVICE(0xA7A0, info), \
- INTEL_VGA_DEVICE(0xA7A1, info), \
- INTEL_VGA_DEVICE(0xA7A8, info), \
- INTEL_VGA_DEVICE(0xA7A9, info)
+ INTEL_VGA_DEVICE(0xA7A8, info)
/* DG2 */
#define INTEL_DG2_G10_IDS(info) \
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2023-01-12 9:27 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-12 9:27 ` [Intel-gfx] [RFC v2 1/2] drm/i915: Add sub platform for 480MHz CDCLK step Chaitanya Kumar Borah
@ 2023-01-12 9:27 ` Chaitanya Kumar Borah
2023-01-12 9:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add new CDCLK step for RPL-U (rev4) Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 17+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-12 9:27 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.
BSpec: 55409
v2: (Matt)
- Add missing clock steps
- Correct reference clock typo
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0c107a38f9d0..ba365ef17abc 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1329,6 +1329,30 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals rplu_cdclk_table[] = {
+ { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
+ { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
+ { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+ { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
+ { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+ { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+ { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
+ { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
+ { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+ { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
+ { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+ { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+ { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+ {}
+};
+
static const struct intel_cdclk_vals dg2_cdclk_table[] = {
{ .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
{ .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
@@ -3353,6 +3377,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
+ else if (IS_ADLP_WITH_480CDCLK(dev_priv))
+ dev_priv->display.cdclk.table = rplu_cdclk_table;
else
dev_priv->display.cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add new CDCLK step for RPL-U (rev4)
2023-01-12 9:27 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-12 9:27 ` [Intel-gfx] [RFC v2 1/2] drm/i915: Add sub platform for 480MHz CDCLK step Chaitanya Kumar Borah
2023-01-12 9:27 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
@ 2023-01-12 9:49 ` Patchwork
2023-01-12 14:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-12 18:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-01-12 9:49 UTC (permalink / raw)
To: Borah, Chaitanya Kumar; +Cc: intel-gfx
== Series Details ==
Series: Add new CDCLK step for RPL-U (rev4)
URL : https://patchwork.freedesktop.org/series/111472/
State : warning
== Summary ==
Error: dim checkpatch failed
5f2b67ffb5e8 drm/i915: Add sub platform for 480MHz CDCLK step
-:90: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#90: FILE: include/drm/i915_pciids.h:688:
+#define INTEL_RPLU_IDS(info) \
+ INTEL_VGA_DEVICE(0xA721, info), \
+ INTEL_VGA_DEVICE(0xA7A1, info), \
+ INTEL_VGA_DEVICE(0xA7A9, info)
-:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#90: FILE: include/drm/i915_pciids.h:688:
+#define INTEL_RPLU_IDS(info) \
+ INTEL_VGA_DEVICE(0xA721, info), \
+ INTEL_VGA_DEVICE(0xA7A1, info), \
+ INTEL_VGA_DEVICE(0xA7A9, info)
total: 1 errors, 0 warnings, 1 checks, 64 lines checked
c2a71b9c1e33 drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [RFC v2 1/2] drm/i915: Add sub platform for 480MHz CDCLK step
2023-01-12 9:27 ` [Intel-gfx] [RFC v2 1/2] drm/i915: Add sub platform for 480MHz CDCLK step Chaitanya Kumar Borah
@ 2023-01-12 11:03 ` Jani Nikula
2023-01-12 11:29 ` Jani Nikula
2023-01-12 17:32 ` Matt Roper
0 siblings, 2 replies; 17+ messages in thread
From: Jani Nikula @ 2023-01-12 11:03 UTC (permalink / raw)
To: Chaitanya Kumar Borah, intel-gfx; +Cc: ville.syrjala
On Thu, 12 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
> Add a new sub platform INTEL_SUBPLATFORM_480CDCLK to identify
> device ids that need the 480MHz CDCLK step. Separate out RPLU
> device ids and add them to both RPL and 480CDCLK subplatforms.
>
> v2: (Matt)
> - Sort PCI-IDs numerically
> - Name the sub-platform to accurately depict what it is for
Did Matt actually ask you to call it INTEL_SUBPLATFORM_480CDCLK?
Personally, I don't like it, because RPL-U has its own PCI IDs and
that's what it's called in the specs. I'd prefer what it was.
(The one outlier is INTEL_SUBPLATFORM_PORTF and I don't like that one
either.)
BR,
Jani.
> - Make RPL-U part of RPL subplatform
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.c | 8 ++++++++
> drivers/gpu/drm/i915/intel_device_info.h | 2 ++
> include/drm/i915_pciids.h | 11 +++++++----
> 5 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 48fd82722f12..fc5518314598 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> #define IS_ADLP_RPLP(dev_priv) \
> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> +#define IS_ADLP_WITH_480CDCLK(dev_priv) \
> + IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_480CDCLK)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 6cc65079b18d..e9f3b99b3e00 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -1234,6 +1234,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_DG1_IDS(&dg1_info),
> INTEL_RPLS_IDS(&adl_s_info),
> INTEL_RPLP_IDS(&adl_p_info),
> + INTEL_RPLU_IDS(&adl_p_info),
> INTEL_DG2_IDS(&dg2_info),
> INTEL_ATS_M_IDS(&ats_m_info),
> INTEL_MTL_IDS(&mtl_info),
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 849baf6c3b3c..a1732ad519fb 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -199,6 +199,11 @@ static const u16 subplatform_n_ids[] = {
> static const u16 subplatform_rpl_ids[] = {
> INTEL_RPLS_IDS(0),
> INTEL_RPLP_IDS(0),
> + INTEL_RPLU_IDS(0)
> +};
> +
> +static const u16 subplatform_480cdclk_ids[] = {
> + INTEL_RPLU_IDS(0),
> };
>
> static const u16 subplatform_g10_ids[] = {
> @@ -268,6 +273,9 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> } else if (find_devid(devid, subplatform_rpl_ids,
> ARRAY_SIZE(subplatform_rpl_ids))) {
> mask = BIT(INTEL_SUBPLATFORM_RPL);
> + if (find_devid(devid, subplatform_480cdclk_ids,
> + ARRAY_SIZE(subplatform_480cdclk_ids)))
> + mask |= BIT(INTEL_SUBPLATFORM_480CDCLK);
> } else if (find_devid(devid, subplatform_g10_ids,
> ARRAY_SIZE(subplatform_g10_ids))) {
> mask = BIT(INTEL_SUBPLATFORM_G10);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index d588e5fd2eea..4f488c900273 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -127,6 +127,8 @@ enum intel_platform {
> * bit set
> */
> #define INTEL_SUBPLATFORM_N 1
> +/* Sub Platform with 480MHz CDCLK step */
> +#define INTEL_SUBPLATFORM_480CDCLK 2
>
> /* MTL */
> #define INTEL_SUBPLATFORM_M 0
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 4a4c190f7698..758be5fb09a2 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -684,14 +684,17 @@
> INTEL_VGA_DEVICE(0xA78A, info), \
> INTEL_VGA_DEVICE(0xA78B, info)
>
> +/* RPL-U */
> +#define INTEL_RPLU_IDS(info) \
> + INTEL_VGA_DEVICE(0xA721, info), \
> + INTEL_VGA_DEVICE(0xA7A1, info), \
> + INTEL_VGA_DEVICE(0xA7A9, info)
> +
> /* RPL-P */
> #define INTEL_RPLP_IDS(info) \
> INTEL_VGA_DEVICE(0xA720, info), \
> - INTEL_VGA_DEVICE(0xA721, info), \
> INTEL_VGA_DEVICE(0xA7A0, info), \
> - INTEL_VGA_DEVICE(0xA7A1, info), \
> - INTEL_VGA_DEVICE(0xA7A8, info), \
> - INTEL_VGA_DEVICE(0xA7A9, info)
> + INTEL_VGA_DEVICE(0xA7A8, info)
>
> /* DG2 */
> #define INTEL_DG2_G10_IDS(info) \
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [RFC v2 1/2] drm/i915: Add sub platform for 480MHz CDCLK step
2023-01-12 11:03 ` Jani Nikula
@ 2023-01-12 11:29 ` Jani Nikula
2023-01-12 17:32 ` Matt Roper
1 sibling, 0 replies; 17+ messages in thread
From: Jani Nikula @ 2023-01-12 11:29 UTC (permalink / raw)
To: Chaitanya Kumar Borah, intel-gfx; +Cc: ville.syrjala
On Thu, 12 Jan 2023, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Thu, 12 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
>> Add a new sub platform INTEL_SUBPLATFORM_480CDCLK to identify
>> device ids that need the 480MHz CDCLK step. Separate out RPLU
>> device ids and add them to both RPL and 480CDCLK subplatforms.
>>
>> v2: (Matt)
>> - Sort PCI-IDs numerically
>> - Name the sub-platform to accurately depict what it is for
>
> Did Matt actually ask you to call it INTEL_SUBPLATFORM_480CDCLK?
>
> Personally, I don't like it, because RPL-U has its own PCI IDs and
> that's what it's called in the specs. I'd prefer what it was.
>
> (The one outlier is INTEL_SUBPLATFORM_PORTF and I don't like that one
> either.)
To iterate, sub-platforms are about *platforms*, identified by PCI IDs,
and they are *not* about features.
If you want to add a macro about a *feature*, for convenience, or for
the purpose of self-documenting code, you add a HAS_FEATURE() macro.
For example:
#define HAS_480_MHZ_CDCLK(__i915) IS_ADLP_RPLU(__i915)
Later on, you can add more platforms to that feature macro if needed.
And if there turns out to be *other* features that are specific to
RPL-U, you don't have to check for them using a macro that refers to a
specific CDCLK frequency.
In summary, this is a resounding no to IS_ADLP_WITH_480CDCLK() and
INTEL_SUBPLATFORM_480CDCLK.
BR,
Jani.
>
> BR,
> Jani.
>
>
>> - Make RPL-U part of RPL subplatform
>>
>> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>> drivers/gpu/drm/i915/i915_pci.c | 1 +
>> drivers/gpu/drm/i915/intel_device_info.c | 8 ++++++++
>> drivers/gpu/drm/i915/intel_device_info.h | 2 ++
>> include/drm/i915_pciids.h | 11 +++++++----
>> 5 files changed, 20 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 48fd82722f12..fc5518314598 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
>> #define IS_ADLP_RPLP(dev_priv) \
>> IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
>> +#define IS_ADLP_WITH_480CDCLK(dev_priv) \
>> + IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_480CDCLK)
>> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>> #define IS_BDW_ULT(dev_priv) \
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
>> index 6cc65079b18d..e9f3b99b3e00 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -1234,6 +1234,7 @@ static const struct pci_device_id pciidlist[] = {
>> INTEL_DG1_IDS(&dg1_info),
>> INTEL_RPLS_IDS(&adl_s_info),
>> INTEL_RPLP_IDS(&adl_p_info),
>> + INTEL_RPLU_IDS(&adl_p_info),
>> INTEL_DG2_IDS(&dg2_info),
>> INTEL_ATS_M_IDS(&ats_m_info),
>> INTEL_MTL_IDS(&mtl_info),
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index 849baf6c3b3c..a1732ad519fb 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -199,6 +199,11 @@ static const u16 subplatform_n_ids[] = {
>> static const u16 subplatform_rpl_ids[] = {
>> INTEL_RPLS_IDS(0),
>> INTEL_RPLP_IDS(0),
>> + INTEL_RPLU_IDS(0)
>> +};
>> +
>> +static const u16 subplatform_480cdclk_ids[] = {
>> + INTEL_RPLU_IDS(0),
>> };
>>
>> static const u16 subplatform_g10_ids[] = {
>> @@ -268,6 +273,9 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>> } else if (find_devid(devid, subplatform_rpl_ids,
>> ARRAY_SIZE(subplatform_rpl_ids))) {
>> mask = BIT(INTEL_SUBPLATFORM_RPL);
>> + if (find_devid(devid, subplatform_480cdclk_ids,
>> + ARRAY_SIZE(subplatform_480cdclk_ids)))
>> + mask |= BIT(INTEL_SUBPLATFORM_480CDCLK);
>> } else if (find_devid(devid, subplatform_g10_ids,
>> ARRAY_SIZE(subplatform_g10_ids))) {
>> mask = BIT(INTEL_SUBPLATFORM_G10);
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index d588e5fd2eea..4f488c900273 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -127,6 +127,8 @@ enum intel_platform {
>> * bit set
>> */
>> #define INTEL_SUBPLATFORM_N 1
>> +/* Sub Platform with 480MHz CDCLK step */
>> +#define INTEL_SUBPLATFORM_480CDCLK 2
>>
>> /* MTL */
>> #define INTEL_SUBPLATFORM_M 0
>> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>> index 4a4c190f7698..758be5fb09a2 100644
>> --- a/include/drm/i915_pciids.h
>> +++ b/include/drm/i915_pciids.h
>> @@ -684,14 +684,17 @@
>> INTEL_VGA_DEVICE(0xA78A, info), \
>> INTEL_VGA_DEVICE(0xA78B, info)
>>
>> +/* RPL-U */
>> +#define INTEL_RPLU_IDS(info) \
>> + INTEL_VGA_DEVICE(0xA721, info), \
>> + INTEL_VGA_DEVICE(0xA7A1, info), \
>> + INTEL_VGA_DEVICE(0xA7A9, info)
>> +
>> /* RPL-P */
>> #define INTEL_RPLP_IDS(info) \
>> INTEL_VGA_DEVICE(0xA720, info), \
>> - INTEL_VGA_DEVICE(0xA721, info), \
>> INTEL_VGA_DEVICE(0xA7A0, info), \
>> - INTEL_VGA_DEVICE(0xA7A1, info), \
>> - INTEL_VGA_DEVICE(0xA7A8, info), \
>> - INTEL_VGA_DEVICE(0xA7A9, info)
>> + INTEL_VGA_DEVICE(0xA7A8, info)
>>
>> /* DG2 */
>> #define INTEL_DG2_G10_IDS(info) \
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Add new CDCLK step for RPL-U (rev4)
2023-01-12 9:27 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
` (2 preceding siblings ...)
2023-01-12 9:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add new CDCLK step for RPL-U (rev4) Patchwork
@ 2023-01-12 14:57 ` Patchwork
2023-01-12 18:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-01-12 14:57 UTC (permalink / raw)
To: Borah, Chaitanya Kumar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4219 bytes --]
== Series Details ==
Series: Add new CDCLK step for RPL-U (rev4)
URL : https://patchwork.freedesktop.org/series/111472/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12575 -> Patchwork_111472v4
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/index.html
Participating hosts (34 -> 34)
------------------------------
Additional (1): fi-kbl-soraka
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_111472v4 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510: [PASS][1] -> [FAIL][2] ([i915#7229])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][5] ([i915#1886])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@guc_hang:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][6] ([i915#7640])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/fi-kbl-soraka/igt@i915_selftest@live@guc_hang.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271]) +15 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/fi-kbl-soraka/igt@kms_chamelium_frames@hdmi-crc-fast.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- fi-rkl-guc: NOTRUN -> [SKIP][8] ([i915#7828])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/fi-rkl-guc/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-snb-2600: NOTRUN -> [SKIP][9] ([fdo#109271])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/fi-snb-2600/igt@kms_setmode@basic-clone-single-crtc.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_lrc:
- fi-rkl-guc: [INCOMPLETE][10] ([i915#4983]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/fi-rkl-guc/igt@i915_selftest@live@gt_lrc.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
[i915#7640]: https://gitlab.freedesktop.org/drm/intel/issues/7640
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
Build changes
-------------
* Linux: CI_DRM_12575 -> Patchwork_111472v4
CI-20190529: 20190529
CI_DRM_12575: 52754fc9f57a4e13ccd1ce908d5d86219121e1b9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7117: 67669415954a763e2d1aa1bed6ef3786c0d17807 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111472v4: 52754fc9f57a4e13ccd1ce908d5d86219121e1b9 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
a6af7ecb7e40 drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
2856d6c0d265 drm/i915: Add sub platform for 480MHz CDCLK step
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/index.html
[-- Attachment #2: Type: text/html, Size: 5247 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [RFC v2 1/2] drm/i915: Add sub platform for 480MHz CDCLK step
2023-01-12 11:03 ` Jani Nikula
2023-01-12 11:29 ` Jani Nikula
@ 2023-01-12 17:32 ` Matt Roper
2023-01-13 4:38 ` Borah, Chaitanya Kumar
1 sibling, 1 reply; 17+ messages in thread
From: Matt Roper @ 2023-01-12 17:32 UTC (permalink / raw)
To: Jani Nikula; +Cc: ville.syrjala, intel-gfx
On Thu, Jan 12, 2023 at 01:03:44PM +0200, Jani Nikula wrote:
> On Thu, 12 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
> > Add a new sub platform INTEL_SUBPLATFORM_480CDCLK to identify
> > device ids that need the 480MHz CDCLK step. Separate out RPLU
> > device ids and add them to both RPL and 480CDCLK subplatforms.
> >
> > v2: (Matt)
> > - Sort PCI-IDs numerically
> > - Name the sub-platform to accurately depict what it is for
>
> Did Matt actually ask you to call it INTEL_SUBPLATFORM_480CDCLK?
>
> Personally, I don't like it, because RPL-U has its own PCI IDs and
> that's what it's called in the specs. I'd prefer what it was.
>
> (The one outlier is INTEL_SUBPLATFORM_PORTF and I don't like that one
> either.)
I think initially the plan was to not match RPL-U, but rather to only
match a specific subset of RPL-U that had this special cdclk (which I
think was determined by CPU vendor string or something). If that's no
longer something we care about, then it probably isn't as important to
have the more precise subplatform name anymore.
Matt
>
> BR,
> Jani.
>
>
> > - Make RPL-U part of RPL subplatform
> >
> > Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > drivers/gpu/drm/i915/intel_device_info.c | 8 ++++++++
> > drivers/gpu/drm/i915/intel_device_info.h | 2 ++
> > include/drm/i915_pciids.h | 11 +++++++----
> > 5 files changed, 20 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 48fd82722f12..fc5518314598 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> > #define IS_ADLP_RPLP(dev_priv) \
> > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> > +#define IS_ADLP_WITH_480CDCLK(dev_priv) \
> > + IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_480CDCLK)
> > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> > (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> > #define IS_BDW_ULT(dev_priv) \
> > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> > index 6cc65079b18d..e9f3b99b3e00 100644
> > --- a/drivers/gpu/drm/i915/i915_pci.c
> > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > @@ -1234,6 +1234,7 @@ static const struct pci_device_id pciidlist[] = {
> > INTEL_DG1_IDS(&dg1_info),
> > INTEL_RPLS_IDS(&adl_s_info),
> > INTEL_RPLP_IDS(&adl_p_info),
> > + INTEL_RPLU_IDS(&adl_p_info),
> > INTEL_DG2_IDS(&dg2_info),
> > INTEL_ATS_M_IDS(&ats_m_info),
> > INTEL_MTL_IDS(&mtl_info),
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> > index 849baf6c3b3c..a1732ad519fb 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -199,6 +199,11 @@ static const u16 subplatform_n_ids[] = {
> > static const u16 subplatform_rpl_ids[] = {
> > INTEL_RPLS_IDS(0),
> > INTEL_RPLP_IDS(0),
> > + INTEL_RPLU_IDS(0)
> > +};
> > +
> > +static const u16 subplatform_480cdclk_ids[] = {
> > + INTEL_RPLU_IDS(0),
> > };
> >
> > static const u16 subplatform_g10_ids[] = {
> > @@ -268,6 +273,9 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> > } else if (find_devid(devid, subplatform_rpl_ids,
> > ARRAY_SIZE(subplatform_rpl_ids))) {
> > mask = BIT(INTEL_SUBPLATFORM_RPL);
> > + if (find_devid(devid, subplatform_480cdclk_ids,
> > + ARRAY_SIZE(subplatform_480cdclk_ids)))
> > + mask |= BIT(INTEL_SUBPLATFORM_480CDCLK);
> > } else if (find_devid(devid, subplatform_g10_ids,
> > ARRAY_SIZE(subplatform_g10_ids))) {
> > mask = BIT(INTEL_SUBPLATFORM_G10);
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> > index d588e5fd2eea..4f488c900273 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -127,6 +127,8 @@ enum intel_platform {
> > * bit set
> > */
> > #define INTEL_SUBPLATFORM_N 1
> > +/* Sub Platform with 480MHz CDCLK step */
> > +#define INTEL_SUBPLATFORM_480CDCLK 2
> >
> > /* MTL */
> > #define INTEL_SUBPLATFORM_M 0
> > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > index 4a4c190f7698..758be5fb09a2 100644
> > --- a/include/drm/i915_pciids.h
> > +++ b/include/drm/i915_pciids.h
> > @@ -684,14 +684,17 @@
> > INTEL_VGA_DEVICE(0xA78A, info), \
> > INTEL_VGA_DEVICE(0xA78B, info)
> >
> > +/* RPL-U */
> > +#define INTEL_RPLU_IDS(info) \
> > + INTEL_VGA_DEVICE(0xA721, info), \
> > + INTEL_VGA_DEVICE(0xA7A1, info), \
> > + INTEL_VGA_DEVICE(0xA7A9, info)
> > +
> > /* RPL-P */
> > #define INTEL_RPLP_IDS(info) \
> > INTEL_VGA_DEVICE(0xA720, info), \
> > - INTEL_VGA_DEVICE(0xA721, info), \
> > INTEL_VGA_DEVICE(0xA7A0, info), \
> > - INTEL_VGA_DEVICE(0xA7A1, info), \
> > - INTEL_VGA_DEVICE(0xA7A8, info), \
> > - INTEL_VGA_DEVICE(0xA7A9, info)
> > + INTEL_VGA_DEVICE(0xA7A8, info)
> >
> > /* DG2 */
> > #define INTEL_DG2_G10_IDS(info) \
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Add new CDCLK step for RPL-U (rev4)
2023-01-12 9:27 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
` (3 preceding siblings ...)
2023-01-12 14:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-01-12 18:44 ` Patchwork
4 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-01-12 18:44 UTC (permalink / raw)
To: Borah, Chaitanya Kumar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 18889 bytes --]
== Series Details ==
Series: Add new CDCLK step for RPL-U (rev4)
URL : https://patchwork.freedesktop.org/series/111472/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12575_full -> Patchwork_111472v4_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/index.html
Participating hosts (14 -> 11)
------------------------------
Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
Known issues
------------
Here are the changes found in Patchwork_111472v4_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#2842])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-glk7/igt@gem_exec_fair@basic-throttle@rcs0.html
#### Possible fixes ####
* igt@drm_fdinfo@idle@rcs0:
- {shard-rkl}: [FAIL][3] ([i915#7742]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-rkl-2/igt@drm_fdinfo@idle@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-rkl-1/igt@drm_fdinfo@idle@rcs0.html
* igt@drm_read@short-buffer-block:
- {shard-rkl}: [SKIP][5] ([i915#4098]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-rkl-1/igt@drm_read@short-buffer-block.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-rkl-6/igt@drm_read@short-buffer-block.html
* igt@drm_read@short-buffer-nonblock:
- {shard-tglu}: [SKIP][7] ([i915#1845]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-tglu-6/igt@drm_read@short-buffer-nonblock.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-tglu-4/igt@drm_read@short-buffer-nonblock.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-rkl}: [FAIL][9] ([i915#6268]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-rkl-1/igt@gem_ctx_exec@basic-nohangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-rkl-6/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- {shard-rkl}: [FAIL][11] ([i915#2842]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-rkl-6/igt@gem_exec_fair@basic-none-share@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-rkl-5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_reloc@basic-write-read-noreloc:
- {shard-rkl}: [SKIP][13] ([i915#3281]) -> [PASS][14] +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-rkl-6/igt@gem_exec_reloc@basic-write-read-noreloc.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-noreloc.html
* igt@gem_mmap_wc@set-cache-level:
- {shard-tglu}: [SKIP][15] ([i915#1850]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-tglu-6/igt@gem_mmap_wc@set-cache-level.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-tglu-4/igt@gem_mmap_wc@set-cache-level.html
* igt@gem_pread@snoop:
- {shard-rkl}: [SKIP][17] ([i915#3282]) -> [PASS][18] +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-rkl-6/igt@gem_pread@snoop.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-rkl-5/igt@gem_pread@snoop.html
* igt@gen9_exec_parse@secure-batches:
- {shard-rkl}: [SKIP][19] ([i915#2527]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-rkl-4/igt@gen9_exec_parse@secure-batches.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-rkl-5/igt@gen9_exec_parse@secure-batches.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-tglu}: [SKIP][21] ([i915#1397]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-tglu-6/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-tglu-4/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-dg1}: [SKIP][23] ([i915#1397]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-dg1-18/igt@i915_pm_rpm@modeset-lpsp-stress.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-dg1-14/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- {shard-tglu}: [SKIP][25] ([i915#1845] / [i915#7651]) -> [PASS][26] +3 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-tglu-6/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-tglu-4/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- {shard-rkl}: [SKIP][27] ([i915#1845] / [i915#4098]) -> [PASS][28] +9 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-rkl-1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_dp_aux_dev:
- {shard-rkl}: [SKIP][29] ([i915#1257]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-rkl-1/igt@kms_dp_aux_dev.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-rkl-6/igt@kms_dp_aux_dev.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite:
- {shard-tglu}: [SKIP][31] ([i915#1849]) -> [PASS][32] +4 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-tglu-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
- {shard-rkl}: [SKIP][33] ([i915#1849] / [i915#4098]) -> [PASS][34] +6 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
* igt@kms_plane@pixel-format@pipe-b-planes:
- {shard-tglu}: [SKIP][35] ([i915#1849] / [i915#3558]) -> [PASS][36] +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-tglu-6/igt@kms_plane@pixel-format@pipe-b-planes.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-tglu-4/igt@kms_plane@pixel-format@pipe-b-planes.html
* igt@kms_plane@plane-position-hole-dpms@pipe-b-planes:
- {shard-rkl}: [SKIP][37] ([i915#1849]) -> [PASS][38] +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-rkl-1/igt@kms_plane@plane-position-hole-dpms@pipe-b-planes.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-rkl-6/igt@kms_plane@plane-position-hole-dpms@pipe-b-planes.html
* igt@kms_vblank@pipe-b-wait-forked-busy-hang:
- {shard-tglu}: [SKIP][39] ([i915#7651]) -> [PASS][40] +6 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-tglu-6/igt@kms_vblank@pipe-b-wait-forked-busy-hang.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-tglu-4/igt@kms_vblank@pipe-b-wait-forked-busy-hang.html
* igt@prime_vgem@coherency-gtt:
- {shard-rkl}: [SKIP][41] ([fdo#109295] / [fdo#111656] / [i915#3708]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-rkl-6/igt@prime_vgem@coherency-gtt.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-rkl-5/igt@prime_vgem@coherency-gtt.html
* igt@sysfs_heartbeat_interval@precise@vecs0:
- {shard-rkl}: [FAIL][43] ([i915#1755]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12575/shard-rkl-2/igt@sysfs_heartbeat_interval@precise@vecs0.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/shard-rkl-1/igt@sysfs_heartbeat_interval@precise@vecs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7679]: https://gitlab.freedesktop.org/drm/intel/issues/7679
[i915#7681]: https://gitlab.freedesktop.org/drm/intel/issues/7681
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
Build changes
-------------
* Linux: CI_DRM_12575 -> Patchwork_111472v4
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_12575: 52754fc9f57a4e13ccd1ce908d5d86219121e1b9 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7117: 67669415954a763e2d1aa1bed6ef3786c0d17807 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_111472v4: 52754fc9f57a4e13ccd1ce908d5d86219121e1b9 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111472v4/index.html
[-- Attachment #2: Type: text/html, Size: 12624 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [RFC v2 1/2] drm/i915: Add sub platform for 480MHz CDCLK step
2023-01-12 17:32 ` Matt Roper
@ 2023-01-13 4:38 ` Borah, Chaitanya Kumar
0 siblings, 0 replies; 17+ messages in thread
From: Borah, Chaitanya Kumar @ 2023-01-13 4:38 UTC (permalink / raw)
To: Roper, Matthew D, Jani Nikula; +Cc: intel-gfx, Syrjala, Ville
Hello Jani and Matt,
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Thursday, January 12, 2023 11:03 PM
> To: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>; intel-
> gfx@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>; Syrjala,
> Ville <ville.syrjala@intel.com>; Srivatsa, Anusha
> <anusha.srivatsa@intel.com>; Atwood, Matthew S
> <matthew.s.atwood@intel.com>
> Subject: Re: [RFC v2 1/2] drm/i915: Add sub platform for 480MHz CDCLK step
>
> On Thu, Jan 12, 2023 at 01:03:44PM +0200, Jani Nikula wrote:
> > On Thu, 12 Jan 2023, Chaitanya Kumar Borah
> <chaitanya.kumar.borah@intel.com> wrote:
> > > Add a new sub platform INTEL_SUBPLATFORM_480CDCLK to identify
> device
> > > ids that need the 480MHz CDCLK step. Separate out RPLU device ids
> > > and add them to both RPL and 480CDCLK subplatforms.
> > >
> > > v2: (Matt)
> > > - Sort PCI-IDs numerically
> > > - Name the sub-platform to accurately depict what it is for
> >
> > Did Matt actually ask you to call it INTEL_SUBPLATFORM_480CDCLK?
> >
> > Personally, I don't like it, because RPL-U has its own PCI IDs and
> > that's what it's called in the specs. I'd prefer what it was.
> >
> > (The one outlier is INTEL_SUBPLATFORM_PORTF and I don't like that one
> > either.)
>
> I think initially the plan was to not match RPL-U, but rather to only match a
> specific subset of RPL-U that had this special cdclk (which I think was
> determined by CPU vendor string or something). If that's no longer
> something we care about, then it probably isn't as important to have the
> more precise subplatform name anymore.
>
I will go back to the RPLU subplatform implementation. What do you think of adding RPL-U ids to RPL subplatform as well? Shall we retain that?
Regards
Chaitanya
>
> Matt
>
> >
> > BR,
> > Jani.
> >
> >
> > > - Make RPL-U part of RPL subplatform
> > >
> > > Signed-off-by: Chaitanya Kumar Borah
> > > <chaitanya.kumar.borah@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > > drivers/gpu/drm/i915/i915_pci.c | 1 +
> > > drivers/gpu/drm/i915/intel_device_info.c | 8 ++++++++
> > > drivers/gpu/drm/i915/intel_device_info.h | 2 ++
> > > include/drm/i915_pciids.h | 11 +++++++----
> > > 5 files changed, 20 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > b/drivers/gpu/drm/i915/i915_drv.h index 48fd82722f12..fc5518314598
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -619,6 +619,8 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> > > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> INTEL_SUBPLATFORM_N)
> > > #define IS_ADLP_RPLP(dev_priv) \
> > > IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> INTEL_SUBPLATFORM_RPL)
> > > +#define IS_ADLP_WITH_480CDCLK(dev_priv) \
> > > + IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P,
> > > +INTEL_SUBPLATFORM_480CDCLK)
> > > #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> > > (INTEL_DEVID(dev_priv) & 0xFF00) ==
> 0x0C00) #define
> > > IS_BDW_ULT(dev_priv) \ diff --git a/drivers/gpu/drm/i915/i915_pci.c
> > > b/drivers/gpu/drm/i915/i915_pci.c index 6cc65079b18d..e9f3b99b3e00
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_pci.c
> > > +++ b/drivers/gpu/drm/i915/i915_pci.c
> > > @@ -1234,6 +1234,7 @@ static const struct pci_device_id pciidlist[] = {
> > > INTEL_DG1_IDS(&dg1_info),
> > > INTEL_RPLS_IDS(&adl_s_info),
> > > INTEL_RPLP_IDS(&adl_p_info),
> > > + INTEL_RPLU_IDS(&adl_p_info),
> > > INTEL_DG2_IDS(&dg2_info),
> > > INTEL_ATS_M_IDS(&ats_m_info),
> > > INTEL_MTL_IDS(&mtl_info),
> > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > > b/drivers/gpu/drm/i915/intel_device_info.c
> > > index 849baf6c3b3c..a1732ad519fb 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > > @@ -199,6 +199,11 @@ static const u16 subplatform_n_ids[] = {
> > > static const u16 subplatform_rpl_ids[] = {
> > > INTEL_RPLS_IDS(0),
> > > INTEL_RPLP_IDS(0),
> > > + INTEL_RPLU_IDS(0)
> > > +};
> > > +
> > > +static const u16 subplatform_480cdclk_ids[] = {
> > > + INTEL_RPLU_IDS(0),
> > > };
> > >
> > > static const u16 subplatform_g10_ids[] = { @@ -268,6 +273,9 @@
> > > static void intel_device_info_subplatform_init(struct drm_i915_private
> *i915)
> > > } else if (find_devid(devid, subplatform_rpl_ids,
> > > ARRAY_SIZE(subplatform_rpl_ids))) {
> > > mask = BIT(INTEL_SUBPLATFORM_RPL);
> > > + if (find_devid(devid, subplatform_480cdclk_ids,
> > > + ARRAY_SIZE(subplatform_480cdclk_ids)))
> > > + mask |= BIT(INTEL_SUBPLATFORM_480CDCLK);
> > > } else if (find_devid(devid, subplatform_g10_ids,
> > > ARRAY_SIZE(subplatform_g10_ids))) {
> > > mask = BIT(INTEL_SUBPLATFORM_G10); diff --git
> > > a/drivers/gpu/drm/i915/intel_device_info.h
> > > b/drivers/gpu/drm/i915/intel_device_info.h
> > > index d588e5fd2eea..4f488c900273 100644
> > > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > > @@ -127,6 +127,8 @@ enum intel_platform {
> > > * bit set
> > > */
> > > #define INTEL_SUBPLATFORM_N 1
> > > +/* Sub Platform with 480MHz CDCLK step */ #define
> > > +INTEL_SUBPLATFORM_480CDCLK 2
> > >
> > > /* MTL */
> > > #define INTEL_SUBPLATFORM_M 0
> > > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > > index 4a4c190f7698..758be5fb09a2 100644
> > > --- a/include/drm/i915_pciids.h
> > > +++ b/include/drm/i915_pciids.h
> > > @@ -684,14 +684,17 @@
> > > INTEL_VGA_DEVICE(0xA78A, info), \
> > > INTEL_VGA_DEVICE(0xA78B, info)
> > >
> > > +/* RPL-U */
> > > +#define INTEL_RPLU_IDS(info) \
> > > + INTEL_VGA_DEVICE(0xA721, info), \
> > > + INTEL_VGA_DEVICE(0xA7A1, info), \
> > > + INTEL_VGA_DEVICE(0xA7A9, info)
> > > +
> > > /* RPL-P */
> > > #define INTEL_RPLP_IDS(info) \
> > > INTEL_VGA_DEVICE(0xA720, info), \
> > > - INTEL_VGA_DEVICE(0xA721, info), \
> > > INTEL_VGA_DEVICE(0xA7A0, info), \
> > > - INTEL_VGA_DEVICE(0xA7A1, info), \
> > > - INTEL_VGA_DEVICE(0xA7A8, info), \
> > > - INTEL_VGA_DEVICE(0xA7A9, info)
> > > + INTEL_VGA_DEVICE(0xA7A8, info)
> > >
> > > /* DG2 */
> > > #define INTEL_DG2_G10_IDS(info) \
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
2023-02-28 0:35 ` Matt Roper
@ 2023-02-28 10:42 ` Borah, Chaitanya Kumar
0 siblings, 0 replies; 17+ messages in thread
From: Borah, Chaitanya Kumar @ 2023-02-28 10:42 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: Syrjala, Ville, intel-gfx
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Tuesday, February 28, 2023 6:06 AM
> To: Borah, Chaitanya Kumar <chaitanya.kumar.borah@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; jani.nikula@linux.intel.com; Shankar,
> Uma <uma.shankar@intel.com>; Syrjala, Ville <ville.syrjala@intel.com>;
> Srivatsa, Anusha <anusha.srivatsa@intel.com>; Atwood, Matthew S
> <matthew.s.atwood@intel.com>
> Subject: Re: [RFC 0/2] Add new CDCLK step for RPL-U
>
> On Mon, Jan 30, 2023 at 03:38:04PM +0530, Chaitanya Kumar Borah wrote:
> > A new step of 480MHz has been added on SKUs that have an RPL-U device
> > id. This particular step is to support 120Hz panels more efficiently.
> >
> > This patchset adds a new table to include this new CDCLK step. Details
> > can be found in BSpec entry 55409.
>
> Hi Chaitanya. It looks like we probably need one more change related to the
> 480MHz rate beyond what was in this series. For platforms that support this
> rate, we can set voltage level 1 (see bspec 49208) whereas the i915 code at
> the moment will push it up to voltage level 2 instead.
Hello Matt,
Thank you for pointing it out. I will have a look and float a patch ASAP.
Regards
Chaitanya
>
>
> Matt
>
> >
> > Create a new sub-platform to identify RPL-U which will enable us to
> > make the differentiation during CDCLK initialization.
> >
> > Furthermore, we need to make a distinction between ES (Engineering
> > Sample) and QS (Quality Sample) parts as this change comes only to QS
> > parts. This version of the patch does not include this change as we
> > are yet to make a decision if this particular part needs to be
> > upstreamed.(see comments on revision 2)
> >
> > Chaitanya Kumar Borah (2):
> > drm/i915: Add RPL-U sub platform
> > drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
> >
> > drivers/gpu/drm/i915/display/intel_cdclk.c | 26
> ++++++++++++++++++++++
> > drivers/gpu/drm/i915/i915_drv.h | 2 ++
> > drivers/gpu/drm/i915/intel_device_info.c | 7 ++++++
> > drivers/gpu/drm/i915/intel_device_info.h | 1 +
> > include/drm/i915_pciids.h | 12 ++++++----
> > 5 files changed, 44 insertions(+), 4 deletions(-)
> >
> > --
> > 2.25.1
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
2023-01-30 10:08 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-02-16 10:52 ` Jani Nikula
@ 2023-02-28 0:35 ` Matt Roper
2023-02-28 10:42 ` Borah, Chaitanya Kumar
1 sibling, 1 reply; 17+ messages in thread
From: Matt Roper @ 2023-02-28 0:35 UTC (permalink / raw)
To: Chaitanya Kumar Borah; +Cc: ville.syrjala, intel-gfx
On Mon, Jan 30, 2023 at 03:38:04PM +0530, Chaitanya Kumar Borah wrote:
> A new step of 480MHz has been added on SKUs that have an RPL-U
> device id. This particular step is to support 120Hz panels
> more efficiently.
>
> This patchset adds a new table to include this new CDCLK
> step. Details can be found in BSpec entry 55409.
Hi Chaitanya. It looks like we probably need one more change related to
the 480MHz rate beyond what was in this series. For platforms that
support this rate, we can set voltage level 1 (see bspec 49208) whereas
the i915 code at the moment will push it up to voltage level 2 instead.
Matt
>
> Create a new sub-platform to identify RPL-U which will enable
> us to make the differentiation during CDCLK initialization.
>
> Furthermore, we need to make a distinction between ES (Engineering
> Sample) and QS (Quality Sample) parts as this change comes only
> to QS parts. This version of the patch does not include this change
> as we are yet to make a decision if this particular part needs
> to be upstreamed.(see comments on revision 2)
>
> Chaitanya Kumar Borah (2):
> drm/i915: Add RPL-U sub platform
> drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
>
> drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_device_info.c | 7 ++++++
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> include/drm/i915_pciids.h | 12 ++++++----
> 5 files changed, 44 insertions(+), 4 deletions(-)
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
2023-01-30 10:08 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
@ 2023-02-16 10:52 ` Jani Nikula
2023-02-28 0:35 ` Matt Roper
1 sibling, 0 replies; 17+ messages in thread
From: Jani Nikula @ 2023-02-16 10:52 UTC (permalink / raw)
To: Chaitanya Kumar Borah, intel-gfx; +Cc: ville.syrjala
On Mon, 30 Jan 2023, Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> wrote:
> A new step of 480MHz has been added on SKUs that have an RPL-U
> device id. This particular step is to support 120Hz panels
> more efficiently.
>
> This patchset adds a new table to include this new CDCLK
> step. Details can be found in BSpec entry 55409.
>
> Create a new sub-platform to identify RPL-U which will enable
> us to make the differentiation during CDCLK initialization.
Thanks, pushed the series to drm-intel-next.
BR,
Jani.
>
> Furthermore, we need to make a distinction between ES (Engineering
> Sample) and QS (Quality Sample) parts as this change comes only
> to QS parts. This version of the patch does not include this change
> as we are yet to make a decision if this particular part needs
> to be upstreamed.(see comments on revision 2)
>
> Chaitanya Kumar Borah (2):
> drm/i915: Add RPL-U sub platform
> drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
>
> drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/intel_device_info.c | 7 ++++++
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> include/drm/i915_pciids.h | 12 ++++++----
> 5 files changed, 44 insertions(+), 4 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
@ 2023-01-30 10:08 Chaitanya Kumar Borah
2023-02-16 10:52 ` Jani Nikula
2023-02-28 0:35 ` Matt Roper
0 siblings, 2 replies; 17+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-30 10:08 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have an RPL-U
device id. This particular step is to support 120Hz panels
more efficiently.
This patchset adds a new table to include this new CDCLK
step. Details can be found in BSpec entry 55409.
Create a new sub-platform to identify RPL-U which will enable
us to make the differentiation during CDCLK initialization.
Furthermore, we need to make a distinction between ES (Engineering
Sample) and QS (Quality Sample) parts as this change comes only
to QS parts. This version of the patch does not include this change
as we are yet to make a decision if this particular part needs
to be upstreamed.(see comments on revision 2)
Chaitanya Kumar Borah (2):
drm/i915: Add RPL-U sub platform
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
drivers/gpu/drm/i915/display/intel_cdclk.c | 26 ++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 7 ++++++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
include/drm/i915_pciids.h | 12 ++++++----
5 files changed, 44 insertions(+), 4 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
@ 2023-01-17 7:42 Chaitanya Kumar Borah
0 siblings, 0 replies; 17+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-17 7:42 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have an RPL-U
device id. This particular step is to support 120Hz panels
more efficiently.
This patchset adds a new table to include this new CDCLK
step. Details can be found in BSpec entry 55409.
Create a new sub-platform to identify RPL-U which will enable
us to make the differentiation during CDCLK initialization.
Furthermore, we need to make a distinction between ES (Engineering
Sample) and QS (Quality Sample) parts as this change comes only
to QS parts. This version of the patch does not include this change
as we are yet to make a decision if this particular part needs
to be upstreamed.(see comments on revision 2)
Chaitanya Kumar Borah (2):
drm/i915: Add RPL-U sub platform
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
drivers/gpu/drm/i915/display/intel_cdclk.c | 27 ++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 8 +++++++
drivers/gpu/drm/i915/intel_device_info.h | 2 ++
include/drm/i915_pciids.h | 11 +++++----
6 files changed, 47 insertions(+), 4 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
@ 2023-01-07 5:36 Chaitanya Kumar Borah
0 siblings, 0 replies; 17+ messages in thread
From: Chaitanya Kumar Borah @ 2023-01-07 5:36 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have an RPL-U
device id. This particular step is to support 120Hz panels
more efficiently.
This patchset adds a new table to include this new CDCLK
step. Details can be found in BSpec entry 55409.
Create a new sub-platform to identify RPL-U which will enable
us to make the differentiation during CDCLK initialization.
Furthermore, we need to make a distinction between ES (Engineering
Sample) and QS (Quality Sample) parts as this change comes only
to QS parts. This version of the patch does not include this change
as we are yet to make a decision if this particular part needs
to be upstreamed.(see comments on previous versions)
Chaitanya Kumar Borah (2):
drm/i915: Add rplu sub platform
drm/i915/display: Add 480 MHz CDCLK steps for RPL-U
arch/x86/kernel/early-quirks.c | 1 +
drivers/gpu/drm/i915/display/intel_cdclk.c | 23 ++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 7 +++++++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_step.c | 3 +++
include/drm/i915_pciids.h | 7 +++++--
8 files changed, 43 insertions(+), 2 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U
@ 2022-11-30 7:46 Chaitanya Kumar Borah
0 siblings, 0 replies; 17+ messages in thread
From: Chaitanya Kumar Borah @ 2022-11-30 7:46 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala
A new step of 480MHz has been added on SKUs that have a RPL-U
device id. This particular step is to better support 120Hz panels.
This patchset adds a new table to include this new CDCLK
step. Details can be found in BSpec entry 55409.
In addition to identifying RPL-U device id, we need to make a
distinction between ES and QS parts as this change comes only to
QS parts. For this CPUID Brand string is used. 480Mhz step is only
supported in SKUs which does not contain the string "Genuine Intel" in
the Brand string.
Even though ES parts will be deprecated in future we are adding this
distinction since they are currently in use. However, here the question
arises if we keep this change in upstream or not as this could just be dead
code down the line. Feedbacks are appreciated on this.
Chaitanya Kumar Borah (2):
drm/i915: Add RPL-U CDCLK table
drm/i915: Add additional check for 480Mhz step CDCLK
drivers/gpu/drm/i915/display/intel_cdclk.c | 53 ++++++++++++++++++++++
1 file changed, 53 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2023-02-28 10:42 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-12 9:27 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-01-12 9:27 ` [Intel-gfx] [RFC v2 1/2] drm/i915: Add sub platform for 480MHz CDCLK step Chaitanya Kumar Borah
2023-01-12 11:03 ` Jani Nikula
2023-01-12 11:29 ` Jani Nikula
2023-01-12 17:32 ` Matt Roper
2023-01-13 4:38 ` Borah, Chaitanya Kumar
2023-01-12 9:27 ` [Intel-gfx] [RFC 2/2] drm/i915/display: Add 480 MHz CDCLK steps for RPL-U Chaitanya Kumar Borah
2023-01-12 9:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add new CDCLK step for RPL-U (rev4) Patchwork
2023-01-12 14:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-01-12 18:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-01-30 10:08 [Intel-gfx] [RFC 0/2] Add new CDCLK step for RPL-U Chaitanya Kumar Borah
2023-02-16 10:52 ` Jani Nikula
2023-02-28 0:35 ` Matt Roper
2023-02-28 10:42 ` Borah, Chaitanya Kumar
2023-01-17 7:42 Chaitanya Kumar Borah
2023-01-07 5:36 Chaitanya Kumar Borah
2022-11-30 7:46 Chaitanya Kumar Borah
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