* [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds
@ 2023-01-19 13:54 Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 01/15] target/arm: Move 64-bit TCG CPUs into tcg/ Fabiano Rosas
` (14 more replies)
0 siblings, 15 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
This series makes the necessary changes to allow the use of
--disable-tcg for arm.
Based on "target/arm: CONFIG_TCG=n part 1":
https://lore.kernel.org/r/20230118193518.26433-1-farosas@suse.de
Since v3:
Aside from minor review comments, the larger changes in this version
are:
- The split of 64-bit CPUs into tcg/cpu64.c. I have moved everything
aside from the cortex-a53 and cortex-a57 cpus which could in theory
be used with KVM.
- qtest vs. default cpu. By removing the default CPU for KVM we now
need to make sure the tests pass a -cpu option.
I don't think allowing tests without -cpu would be feasible because
we'd have to go searching for every piece of code that assumes a cpu
is always present.
v3:
https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de
v2:
https://lore.kernel.org/r/20230109224232.11661-1-farosas@suse.de
v1:
https://lore.kernel.org/r/20230104215835.24692-1-farosas@suse.de
Claudio Fontana (1):
target/arm: move cpu_tcg to tcg/cpu32.c
Fabiano Rosas (14):
target/arm: Move 64-bit TCG CPUs into tcg/
target/arm: Remove default cpu for KVM-only builds
tests/qtest: arm-cpu-features: Match tests to required accelerators
tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
tests/qtest: Add qtest_get_machine_args
tests/qtest: Adjust qom-test to always set a -cpu option
tests/qtest: Adjust test-hmp to always pass -cpu option
tests/qtest: Adjust device-introspect-test to always set a -cpu option
tests/qtest: aarch64: Set -cpu for numa-test
tests/qemu-iotests: Allow passing a -cpu option in the QEMU cmdline
tests/tcg: Do not build/run TCG tests if TCG is disabled
target/avocado: Pass parameters to migration test on aarch64
arm/Kconfig: Always select SEMIHOSTING when TCG is present
arm/Kconfig: Do not build TCG-only boards on a KVM-only build
configs/devices/aarch64-softmmu/default.mak | 4 -
configs/devices/arm-softmmu/default.mak | 39 --
configure | 6 +-
hw/arm/Kconfig | 43 +-
hw/arm/virt.c | 9 +
target/arm/Kconfig | 7 +
target/arm/cpu64.c | 633 +------------------
target/arm/internals.h | 4 +
target/arm/meson.build | 1 -
target/arm/{cpu_tcg.c => tcg/cpu32.c} | 13 +-
target/arm/tcg/cpu64.c | 654 ++++++++++++++++++++
target/arm/tcg/meson.build | 2 +
tests/avocado/migration.py | 11 +-
tests/qemu-iotests/testenv.py | 7 +
tests/qtest/arm-cpu-features.c | 34 +-
tests/qtest/device-introspect-test.c | 17 +-
tests/qtest/libqtest.c | 99 +++
tests/qtest/libqtest.h | 11 +
tests/qtest/meson.build | 12 +-
tests/qtest/numa-test.c | 1 +
tests/qtest/qom-test.c | 19 +-
tests/qtest/test-hmp.c | 34 +-
22 files changed, 960 insertions(+), 700 deletions(-)
rename target/arm/{cpu_tcg.c => tcg/cpu32.c} (99%)
create mode 100644 target/arm/tcg/cpu64.c
--
2.35.3
^ permalink raw reply [flat|nested] 45+ messages in thread
* [RFC PATCH v4 01/15] target/arm: Move 64-bit TCG CPUs into tcg/
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 18:31 ` Richard Henderson
2023-01-19 13:54 ` [RFC PATCH v4 02/15] target/arm: move cpu_tcg to tcg/cpu32.c Fabiano Rosas
` (13 subsequent siblings)
14 siblings, 1 reply; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
Move the 64-bit CPUs that are TCG-only:
- cortex-a35
- cortex-a55
- cortex-a72
- cortex-a76
- a64fx
- neoverse-n1
Keep the CPUs that can be used with KVM:
- cortex-a57
- cortex-a53
- max
- host
For the special case "max" CPU, there's a nuance that while KVM/HVF
use the "host" model instead, we still cannot move all of the TCG code
into the tcg directory because the qtests might reach the !kvm && !hvf
branch. Keep the cortex_a57_initfn() call to cover that scenario.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
target/arm/cpu64.c | 633 +----------------------------------
target/arm/internals.h | 4 +
target/arm/tcg/cpu64.c | 654 +++++++++++++++++++++++++++++++++++++
target/arm/tcg/meson.build | 1 +
4 files changed, 671 insertions(+), 621 deletions(-)
create mode 100644 target/arm/tcg/cpu64.c
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 5dfdae7bd2..226f57c669 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -24,6 +24,8 @@
#include "qemu/module.h"
#include "sysemu/kvm.h"
#include "sysemu/hvf.h"
+#include "sysemu/qtest.h"
+#include "sysemu/tcg.h"
#include "kvm_arm.h"
#include "hvf_arm.h"
#include "qapi/visitor.h"
@@ -31,86 +33,6 @@
#include "internals.h"
#include "cpregs.h"
-static void aarch64_a35_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,cortex-a35";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
-
- /* From B2.2 AArch64 identification registers. */
- cpu->midr = 0x411fd040;
- cpu->revidr = 0;
- cpu->ctr = 0x84448004;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
- cpu->isar.id_dfr0 = 0x03010066;
- cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_aa64pfr0 = 0x00002222;
- cpu->isar.id_aa64pfr1 = 0;
- cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64dfr1 = 0;
- cpu->isar.id_aa64isar0 = 0x00011120;
- cpu->isar.id_aa64isar1 = 0;
- cpu->isar.id_aa64mmfr0 = 0x00101122;
- cpu->isar.id_aa64mmfr1 = 0;
- cpu->clidr = 0x0a200023;
- cpu->dcz_blocksize = 4;
-
- /* From B2.4 AArch64 Virtual Memory control registers */
- cpu->reset_sctlr = 0x00c50838;
-
- /* From B2.10 AArch64 performance monitor registers */
- cpu->isar.reset_pmcr_el0 = 0x410a3000;
-
- /* From B2.29 Cache ID registers */
- cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
- cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
- cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */
-
- /* From B3.5 VGIC Type register */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- /* From C6.4 Debug ID Register */
- cpu->isar.dbgdidr = 0x3516d000;
- /* From C6.5 Debug Device ID Register */
- cpu->isar.dbgdevid = 0x00110f13;
- /* From C6.6 Debug Device ID Register 1 */
- cpu->isar.dbgdevid1 = 0x2;
-
- /* From Cortex-A35 SIMD and Floating-point Support r1p0 */
- /* From 3.2 AArch32 register summary */
- cpu->reset_fpsid = 0x41034043;
-
- /* From 2.2 AArch64 register summary */
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x12111111;
- cpu->isar.mvfr2 = 0x00000043;
-
- /* These values are the same with A53/A57/A72. */
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
{
/*
@@ -310,47 +232,6 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
cpu->sve_vq.map = vq_map;
}
-static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- uint32_t value;
-
- /* All vector lengths are disabled when SVE is off. */
- if (!cpu_isar_feature(aa64_sve, cpu)) {
- value = 0;
- } else {
- value = cpu->sve_max_vq;
- }
- visit_type_uint32(v, name, &value, errp);
-}
-
-static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- ARMCPU *cpu = ARM_CPU(obj);
- uint32_t max_vq;
-
- if (!visit_type_uint32(v, name, &max_vq, errp)) {
- return;
- }
-
- if (kvm_enabled() && !kvm_arm_sve_supported()) {
- error_setg(errp, "cannot set sve-max-vq");
- error_append_hint(errp, "SVE not supported by KVM on this host\n");
- return;
- }
-
- if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
- error_setg(errp, "unsupported SVE vector length");
- error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
- ARM_MAX_VQ);
- return;
- }
-
- cpu->sve_max_vq = max_vq;
-}
-
/*
* Note that cpu_arm_{get,set}_vq cannot use the simpler
* object_property_add_bool interface because they make use of the
@@ -541,7 +422,7 @@ static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v,
}
#endif
-static void aarch64_add_sve_properties(Object *obj)
+void aarch64_add_sve_properties(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
uint32_t vq;
@@ -564,7 +445,7 @@ static void aarch64_add_sve_properties(Object *obj)
#endif
}
-static void aarch64_add_sme_properties(Object *obj)
+void aarch64_add_sme_properties(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
uint32_t vq;
@@ -629,7 +510,7 @@ static Property arm_cpu_pauth_property =
static Property arm_cpu_pauth_impdef_property =
DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false);
-static void aarch64_add_pauth_properties(Object *obj)
+void aarch64_add_pauth_properties(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -650,9 +531,6 @@ static void aarch64_add_pauth_properties(Object *obj)
}
}
-static Property arm_cpu_lpa2_property =
- DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);
-
void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
{
uint64_t t;
@@ -787,316 +665,6 @@ static void aarch64_a53_initfn(Object *obj)
define_cortex_a72_a57_a53_cp_reginfo(cpu);
}
-static void aarch64_a55_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,cortex-a55";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
-
- /* Ordered by B2.4 AArch64 registers by functional group */
- cpu->clidr = 0x82000023;
- cpu->ctr = 0x84448004; /* L1Ip = VIPT */
- cpu->dcz_blocksize = 4; /* 64 bytes */
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00011011;
- cpu->isar.id_pfr2 = 0x00000011;
- cpu->midr = 0x412FD050; /* r2p0 */
- cpu->revidr = 0;
-
- /* From B2.23 CCSIDR_EL1 */
- cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
- cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
- cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
-
- /* From B2.96 SCTLR_EL3 */
- cpu->reset_sctlr = 0x30c50838;
-
- /* From B4.45 ICH_VTR_EL2 */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x13211111;
- cpu->isar.mvfr2 = 0x00000043;
-
- /* From D5.4 AArch64 PMU register summary */
- cpu->isar.reset_pmcr_el0 = 0x410b3000;
-}
-
-static void aarch64_a72_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,cortex-a72";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
- cpu->midr = 0x410fd083;
- cpu->revidr = 0x00000000;
- cpu->reset_fpsid = 0x41034080;
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x12111111;
- cpu->isar.mvfr2 = 0x00000043;
- cpu->ctr = 0x8444c004;
- cpu->reset_sctlr = 0x00c50838;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
- cpu->isar.id_dfr0 = 0x03010066;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_aa64pfr0 = 0x00002222;
- cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64isar0 = 0x00011120;
- cpu->isar.id_aa64mmfr0 = 0x00001124;
- cpu->isar.dbgdidr = 0x3516d000;
- cpu->isar.dbgdevid = 0x01110f13;
- cpu->isar.dbgdevid1 = 0x2;
- cpu->isar.reset_pmcr_el0 = 0x41023000;
- cpu->clidr = 0x0a200023;
- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
- cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
- cpu->dcz_blocksize = 4; /* 64 bytes */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
-}
-
-static void aarch64_a76_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,cortex-a76";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
-
- /* Ordered by B2.4 AArch64 registers by functional group */
- cpu->clidr = 0x82000023;
- cpu->ctr = 0x8444C004;
- cpu->dcz_blocksize = 4;
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
- cpu->isar.id_pfr2 = 0x00000011;
- cpu->midr = 0x414fd0b1; /* r4p1 */
- cpu->revidr = 0;
-
- /* From B2.18 CCSIDR_EL1 */
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
- cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
-
- /* From B2.93 SCTLR_EL3 */
- cpu->reset_sctlr = 0x30c50838;
-
- /* From B4.23 ICH_VTR_EL2 */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- /* From B5.1 AdvSIMD AArch64 register summary */
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x13211111;
- cpu->isar.mvfr2 = 0x00000043;
-
- /* From D5.1 AArch64 PMU register summary */
- cpu->isar.reset_pmcr_el0 = 0x410b3000;
-}
-
-static void aarch64_a64fx_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,a64fx";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
- cpu->midr = 0x461f0010;
- cpu->revidr = 0x00000000;
- cpu->ctr = 0x86668006;
- cpu->reset_sctlr = 0x30000180;
- cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
- cpu->isar.id_aa64pfr1 = 0x0000000000000000;
- cpu->isar.id_aa64dfr0 = 0x0000000010305408;
- cpu->isar.id_aa64dfr1 = 0x0000000000000000;
- cpu->id_aa64afr0 = 0x0000000000000000;
- cpu->id_aa64afr1 = 0x0000000000000000;
- cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
- cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
- cpu->isar.id_aa64isar0 = 0x0000000010211120;
- cpu->isar.id_aa64isar1 = 0x0000000000010001;
- cpu->isar.id_aa64zfr0 = 0x0000000000000000;
- cpu->clidr = 0x0000000080000023;
- cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
- cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
- cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
- cpu->dcz_blocksize = 6; /* 256 bytes */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- /* The A64FX supports only 128, 256 and 512 bit vector lengths */
- aarch64_add_sve_properties(obj);
- cpu->sve_vq.supported = (1 << 0) /* 128bit */
- | (1 << 1) /* 256bit */
- | (1 << 3); /* 512bit */
-
- cpu->isar.reset_pmcr_el0 = 0x46014040;
-
- /* TODO: Add A64FX specific HPC extension registers */
-}
-
-static void aarch64_neoverse_n1_initfn(Object *obj)
-{
- ARMCPU *cpu = ARM_CPU(obj);
-
- cpu->dtb_compatible = "arm,neoverse-n1";
- set_feature(&cpu->env, ARM_FEATURE_V8);
- set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
- set_feature(&cpu->env, ARM_FEATURE_EL2);
- set_feature(&cpu->env, ARM_FEATURE_EL3);
- set_feature(&cpu->env, ARM_FEATURE_PMU);
-
- /* Ordered by B2.4 AArch64 registers by functional group */
- cpu->clidr = 0x82000023;
- cpu->ctr = 0x8444c004;
- cpu->dcz_blocksize = 4;
- cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
- cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
- cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
- cpu->isar.id_pfr2 = 0x00000011;
- cpu->midr = 0x414fd0c1; /* r4p1 */
- cpu->revidr = 0;
-
- /* From B2.23 CCSIDR_EL1 */
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
- cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
-
- /* From B2.98 SCTLR_EL3 */
- cpu->reset_sctlr = 0x30c50838;
-
- /* From B4.23 ICH_VTR_EL2 */
- cpu->gic_num_lrs = 4;
- cpu->gic_vpribits = 5;
- cpu->gic_vprebits = 5;
- cpu->gic_pribits = 5;
-
- /* From B5.1 AdvSIMD AArch64 register summary */
- cpu->isar.mvfr0 = 0x10110222;
- cpu->isar.mvfr1 = 0x13211111;
- cpu->isar.mvfr2 = 0x00000043;
-
- /* From D5.1 AArch64 PMU register summary */
- cpu->isar.reset_pmcr_el0 = 0x410c3000;
-}
-
static void aarch64_host_initfn(Object *obj)
{
#if defined(CONFIG_KVM)
@@ -1115,203 +683,26 @@ static void aarch64_host_initfn(Object *obj)
#endif
}
-/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
- * otherwise, a CPU with as many features enabled as our emulation supports.
- * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
- * this only needs to handle 64 bits.
- */
static void aarch64_max_initfn(Object *obj)
{
- ARMCPU *cpu = ARM_CPU(obj);
- uint64_t t;
- uint32_t u;
-
if (kvm_enabled() || hvf_enabled()) {
/* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
aarch64_host_initfn(obj);
- return;
}
- /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
-
- aarch64_a57_initfn(obj);
-
- /*
- * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
- * one and try to apply errata workarounds or use impdef features we
- * don't provide.
- * An IMPLEMENTER field of 0 means "reserved for software use";
- * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
- * to see which features are present";
- * the VARIANT, PARTNUM and REVISION fields are all implementation
- * defined and we choose to define PARTNUM just in case guest
- * code needs to distinguish this QEMU CPU from other software
- * implementations, though this shouldn't be needed.
- */
- t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
- t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
- t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
- t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
- t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
- cpu->midr = t;
-
- /*
- * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS}
- * are zero.
- */
- u = cpu->clidr;
- u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0);
- u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0);
- cpu->clidr = u;
-
- t = cpu->isar.id_aa64isar0;
- t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
- t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
- t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
- t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
- t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
- t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
- t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
- t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
- t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
- t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
- t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
- cpu->isar.id_aa64isar0 = t;
-
- t = cpu->isar.id_aa64isar1;
- t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
- t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
- t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
- t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
- t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
- t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
- t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
- t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
- t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
- t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
- cpu->isar.id_aa64isar1 = t;
-
- t = cpu->isar.id_aa64pfr0;
- t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
- t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
- t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */
- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
- t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
- t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
- t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
- t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
- cpu->isar.id_aa64pfr0 = t;
-
- t = cpu->isar.id_aa64pfr1;
- t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
- t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
- /*
- * Begin with full support for MTE. This will be downgraded to MTE=0
- * during realize if the board provides no tag memory, much like
- * we do for EL2 with the virtualization=on property.
- */
- t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
- t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */
- t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
- t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
- cpu->isar.id_aa64pfr1 = t;
-
- t = cpu->isar.id_aa64mmfr0;
- t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
- t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
- t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
- t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
- t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
- cpu->isar.id_aa64mmfr0 = t;
-
- t = cpu->isar.id_aa64mmfr1;
- t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
- t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
- t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
- t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
- t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
- t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */
- t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
- t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */
- t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
- cpu->isar.id_aa64mmfr1 = t;
-
- t = cpu->isar.id_aa64mmfr2;
- t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
- t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
- t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
- t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
- t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
- t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */
- t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
- t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
- t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
- t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
- t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
- cpu->isar.id_aa64mmfr2 = t;
-
- t = cpu->isar.id_aa64zfr0;
- t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
- t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
- t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
- t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */
- t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
- t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
- t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
- t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
- t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
- cpu->isar.id_aa64zfr0 = t;
-
- t = cpu->isar.id_aa64dfr0;
- t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
- t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
- cpu->isar.id_aa64dfr0 = t;
-
- t = cpu->isar.id_aa64smfr0;
- t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
- t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */
- t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */
- t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */
- t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */
- t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
- t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */
- cpu->isar.id_aa64smfr0 = t;
-
- /* Replicate the same data to the 32-bit id registers. */
- aa32_max_features(cpu);
-
-#ifdef CONFIG_USER_ONLY
- /*
- * For usermode -cpu max we can use a larger and more efficient DCZ
- * blocksize since we don't have to follow what the hardware does.
- */
- cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
- cpu->dcz_blocksize = 7; /* 512 bytes */
-#endif
-
- cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
- cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
+ if (tcg_enabled() || qtest_enabled()) {
+ aarch64_a57_initfn(obj);
+ }
- aarch64_add_pauth_properties(obj);
- aarch64_add_sve_properties(obj);
- aarch64_add_sme_properties(obj);
- object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
- cpu_max_set_sve_max_vq, NULL, NULL);
- qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
+ if (tcg_enabled()) {
+ /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
+ aarch64_max_tcg_initfn(obj);
+ }
}
static const ARMCPUInfo aarch64_cpus[] = {
- { .name = "cortex-a35", .initfn = aarch64_a35_initfn },
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
- { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
- { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
- { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
- { .name = "a64fx", .initfn = aarch64_a64fx_initfn },
- { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
{ .name = "max", .initfn = aarch64_max_initfn },
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
{ .name = "host", .initfn = aarch64_host_initfn },
diff --git a/target/arm/internals.h b/target/arm/internals.h
index a8fb8aa363..72e3d2fef2 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1364,6 +1364,10 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
+void aarch64_max_tcg_initfn(Object *obj);
+void aarch64_add_pauth_properties(Object *obj);
+void aarch64_add_sve_properties(Object *obj);
+void aarch64_add_sme_properties(Object *obj);
#endif
bool el_is_in_host(CPUARMState *env, int el);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
new file mode 100644
index 0000000000..4d5bdddae4
--- /dev/null
+++ b/target/arm/tcg/cpu64.c
@@ -0,0 +1,654 @@
+/*
+ * QEMU AArch64 TCG CPUs
+ *
+ * Copyright (c) 2013 Linaro Ltd
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "qemu/module.h"
+#include "qapi/visitor.h"
+#include "hw/qdev-properties.h"
+#include "internals.h"
+#include "cpregs.h"
+
+static void aarch64_a35_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a35";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+ /* From B2.2 AArch64 identification registers. */
+ cpu->midr = 0x411fd040;
+ cpu->revidr = 0;
+ cpu->ctr = 0x84448004;
+ cpu->isar.id_pfr0 = 0x00000131;
+ cpu->isar.id_pfr1 = 0x00011011;
+ cpu->isar.id_dfr0 = 0x03010066;
+ cpu->id_afr0 = 0;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02102211;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00011142;
+ cpu->isar.id_isar5 = 0x00011121;
+ cpu->isar.id_aa64pfr0 = 0x00002222;
+ cpu->isar.id_aa64pfr1 = 0;
+ cpu->isar.id_aa64dfr0 = 0x10305106;
+ cpu->isar.id_aa64dfr1 = 0;
+ cpu->isar.id_aa64isar0 = 0x00011120;
+ cpu->isar.id_aa64isar1 = 0;
+ cpu->isar.id_aa64mmfr0 = 0x00101122;
+ cpu->isar.id_aa64mmfr1 = 0;
+ cpu->clidr = 0x0a200023;
+ cpu->dcz_blocksize = 4;
+
+ /* From B2.4 AArch64 Virtual Memory control registers */
+ cpu->reset_sctlr = 0x00c50838;
+
+ /* From B2.10 AArch64 performance monitor registers */
+ cpu->isar.reset_pmcr_el0 = 0x410a3000;
+
+ /* From B2.29 Cache ID registers */
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
+ cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */
+
+ /* From B3.5 VGIC Type register */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ /* From C6.4 Debug ID Register */
+ cpu->isar.dbgdidr = 0x3516d000;
+ /* From C6.5 Debug Device ID Register */
+ cpu->isar.dbgdevid = 0x00110f13;
+ /* From C6.6 Debug Device ID Register 1 */
+ cpu->isar.dbgdevid1 = 0x2;
+
+ /* From Cortex-A35 SIMD and Floating-point Support r1p0 */
+ /* From 3.2 AArch32 register summary */
+ cpu->reset_fpsid = 0x41034043;
+
+ /* From 2.2 AArch64 register summary */
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x12111111;
+ cpu->isar.mvfr2 = 0x00000043;
+
+ /* These values are the same with A53/A57/A72. */
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
+}
+
+static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ uint32_t value;
+
+ /* All vector lengths are disabled when SVE is off. */
+ if (!cpu_isar_feature(aa64_sve, cpu)) {
+ value = 0;
+ } else {
+ value = cpu->sve_max_vq;
+ }
+ visit_type_uint32(v, name, &value, errp);
+}
+
+static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ uint32_t max_vq;
+
+ if (!visit_type_uint32(v, name, &max_vq, errp)) {
+ return;
+ }
+
+ if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
+ error_setg(errp, "unsupported SVE vector length");
+ error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
+ ARM_MAX_VQ);
+ return;
+ }
+
+ cpu->sve_max_vq = max_vq;
+}
+
+static Property arm_cpu_lpa2_property =
+ DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);
+
+static void aarch64_a55_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a55";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+ /* Ordered by B2.4 AArch64 registers by functional group */
+ cpu->clidr = 0x82000023;
+ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
+ cpu->dcz_blocksize = 4; /* 64 bytes */
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_dfr0 = 0x04010088;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00011142;
+ cpu->isar.id_isar5 = 0x01011121;
+ cpu->isar.id_isar6 = 0x00000010;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02122211;
+ cpu->isar.id_mmfr4 = 0x00021110;
+ cpu->isar.id_pfr0 = 0x10010131;
+ cpu->isar.id_pfr1 = 0x00011011;
+ cpu->isar.id_pfr2 = 0x00000011;
+ cpu->midr = 0x412FD050; /* r2p0 */
+ cpu->revidr = 0;
+
+ /* From B2.23 CCSIDR_EL1 */
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
+ cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
+
+ /* From B2.96 SCTLR_EL3 */
+ cpu->reset_sctlr = 0x30c50838;
+
+ /* From B4.45 ICH_VTR_EL2 */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x13211111;
+ cpu->isar.mvfr2 = 0x00000043;
+
+ /* From D5.4 AArch64 PMU register summary */
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
+}
+
+static void aarch64_a72_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a72";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+ cpu->midr = 0x410fd083;
+ cpu->revidr = 0x00000000;
+ cpu->reset_fpsid = 0x41034080;
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x12111111;
+ cpu->isar.mvfr2 = 0x00000043;
+ cpu->ctr = 0x8444c004;
+ cpu->reset_sctlr = 0x00c50838;
+ cpu->isar.id_pfr0 = 0x00000131;
+ cpu->isar.id_pfr1 = 0x00011011;
+ cpu->isar.id_dfr0 = 0x03010066;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02102211;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00011142;
+ cpu->isar.id_isar5 = 0x00011121;
+ cpu->isar.id_aa64pfr0 = 0x00002222;
+ cpu->isar.id_aa64dfr0 = 0x10305106;
+ cpu->isar.id_aa64isar0 = 0x00011120;
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
+ cpu->isar.dbgdidr = 0x3516d000;
+ cpu->isar.dbgdevid = 0x01110f13;
+ cpu->isar.dbgdevid1 = 0x2;
+ cpu->isar.reset_pmcr_el0 = 0x41023000;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
+ cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
+ cpu->dcz_blocksize = 4; /* 64 bytes */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
+}
+
+static void aarch64_a76_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a76";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+ /* Ordered by B2.4 AArch64 registers by functional group */
+ cpu->clidr = 0x82000023;
+ cpu->ctr = 0x8444C004;
+ cpu->dcz_blocksize = 4;
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_dfr0 = 0x04010088;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00010142;
+ cpu->isar.id_isar5 = 0x01011121;
+ cpu->isar.id_isar6 = 0x00000010;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02122211;
+ cpu->isar.id_mmfr4 = 0x00021110;
+ cpu->isar.id_pfr0 = 0x10010131;
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
+ cpu->isar.id_pfr2 = 0x00000011;
+ cpu->midr = 0x414fd0b1; /* r4p1 */
+ cpu->revidr = 0;
+
+ /* From B2.18 CCSIDR_EL1 */
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+ cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
+
+ /* From B2.93 SCTLR_EL3 */
+ cpu->reset_sctlr = 0x30c50838;
+
+ /* From B4.23 ICH_VTR_EL2 */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ /* From B5.1 AdvSIMD AArch64 register summary */
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x13211111;
+ cpu->isar.mvfr2 = 0x00000043;
+
+ /* From D5.1 AArch64 PMU register summary */
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
+}
+
+static void aarch64_a64fx_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,a64fx";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+ cpu->midr = 0x461f0010;
+ cpu->revidr = 0x00000000;
+ cpu->ctr = 0x86668006;
+ cpu->reset_sctlr = 0x30000180;
+ cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
+ cpu->isar.id_aa64pfr1 = 0x0000000000000000;
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408;
+ cpu->isar.id_aa64dfr1 = 0x0000000000000000;
+ cpu->id_aa64afr0 = 0x0000000000000000;
+ cpu->id_aa64afr1 = 0x0000000000000000;
+ cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
+ cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
+ cpu->isar.id_aa64isar0 = 0x0000000010211120;
+ cpu->isar.id_aa64isar1 = 0x0000000000010001;
+ cpu->isar.id_aa64zfr0 = 0x0000000000000000;
+ cpu->clidr = 0x0000000080000023;
+ cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
+ cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
+ cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
+ cpu->dcz_blocksize = 6; /* 256 bytes */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ /* The A64FX supports only 128, 256 and 512 bit vector lengths */
+ aarch64_add_sve_properties(obj);
+ cpu->sve_vq.supported = (1 << 0) /* 128bit */
+ | (1 << 1) /* 256bit */
+ | (1 << 3); /* 512bit */
+
+ cpu->isar.reset_pmcr_el0 = 0x46014040;
+
+ /* TODO: Add A64FX specific HPC extension registers */
+}
+
+static void aarch64_neoverse_n1_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,neoverse-n1";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+ /* Ordered by B2.4 AArch64 registers by functional group */
+ cpu->clidr = 0x82000023;
+ cpu->ctr = 0x8444c004;
+ cpu->dcz_blocksize = 4;
+ cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
+ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_dfr0 = 0x04010088;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232042;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00010142;
+ cpu->isar.id_isar5 = 0x01011121;
+ cpu->isar.id_isar6 = 0x00000010;
+ cpu->isar.id_mmfr0 = 0x10201105;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01260000;
+ cpu->isar.id_mmfr3 = 0x02122211;
+ cpu->isar.id_mmfr4 = 0x00021110;
+ cpu->isar.id_pfr0 = 0x10010131;
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
+ cpu->isar.id_pfr2 = 0x00000011;
+ cpu->midr = 0x414fd0c1; /* r4p1 */
+ cpu->revidr = 0;
+
+ /* From B2.23 CCSIDR_EL1 */
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
+ cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
+
+ /* From B2.98 SCTLR_EL3 */
+ cpu->reset_sctlr = 0x30c50838;
+
+ /* From B4.23 ICH_VTR_EL2 */
+ cpu->gic_num_lrs = 4;
+ cpu->gic_vpribits = 5;
+ cpu->gic_vprebits = 5;
+ cpu->gic_pribits = 5;
+
+ /* From B5.1 AdvSIMD AArch64 register summary */
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x13211111;
+ cpu->isar.mvfr2 = 0x00000043;
+
+ /* From D5.1 AArch64 PMU register summary */
+ cpu->isar.reset_pmcr_el0 = 0x410c3000;
+}
+
+/*
+ * -cpu max: a CPU with as many features enabled as our emulation supports.
+ * The version of '-cpu max' for qemu-system-arm is defined in cpu_tcg.c;
+ * this only needs to handle 64 bits.
+ */
+void aarch64_max_tcg_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t t;
+ uint32_t u;
+
+ /*
+ * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
+ * one and try to apply errata workarounds or use impdef features we
+ * don't provide.
+ * An IMPLEMENTER field of 0 means "reserved for software use";
+ * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
+ * to see which features are present";
+ * the VARIANT, PARTNUM and REVISION fields are all implementation
+ * defined and we choose to define PARTNUM just in case guest
+ * code needs to distinguish this QEMU CPU from other software
+ * implementations, though this shouldn't be needed.
+ */
+ t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
+ t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
+ t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
+ t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
+ t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
+ cpu->midr = t;
+
+ /*
+ * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS}
+ * are zero.
+ */
+ u = cpu->clidr;
+ u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0);
+ u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0);
+ cpu->clidr = u;
+
+ t = cpu->isar.id_aa64isar0;
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
+ t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
+ t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
+ t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
+ t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
+ t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
+ t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
+ t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
+ cpu->isar.id_aa64isar0 = t;
+
+ t = cpu->isar.id_aa64isar1;
+ t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
+ t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
+ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
+ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
+ t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
+ t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
+ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
+ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
+ t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
+ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
+ cpu->isar.id_aa64isar1 = t;
+
+ t = cpu->isar.id_aa64pfr0;
+ t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
+ t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
+ t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */
+ t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
+ t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
+ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
+ t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
+ cpu->isar.id_aa64pfr0 = t;
+
+ t = cpu->isar.id_aa64pfr1;
+ t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
+ t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
+ /*
+ * Begin with full support for MTE. This will be downgraded to MTE=0
+ * during realize if the board provides no tag memory, much like
+ * we do for EL2 with the virtualization=on property.
+ */
+ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
+ t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */
+ t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
+ cpu->isar.id_aa64pfr1 = t;
+
+ t = cpu->isar.id_aa64mmfr0;
+ t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
+ t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
+ cpu->isar.id_aa64mmfr0 = t;
+
+ t = cpu->isar.id_aa64mmfr1;
+ t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
+ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
+ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
+ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
+ t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */
+ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
+ t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */
+ t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
+ cpu->isar.id_aa64mmfr1 = t;
+
+ t = cpu->isar.id_aa64mmfr2;
+ t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
+ t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
+ t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
+ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
+ t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */
+ t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
+ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
+ t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
+ t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
+ t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
+ cpu->isar.id_aa64mmfr2 = t;
+
+ t = cpu->isar.id_aa64zfr0;
+ t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
+ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
+ t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
+ t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */
+ t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
+ t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
+ t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
+ t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
+ t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
+ cpu->isar.id_aa64zfr0 = t;
+
+ t = cpu->isar.id_aa64dfr0;
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
+ cpu->isar.id_aa64dfr0 = t;
+
+ t = cpu->isar.id_aa64smfr0;
+ t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */
+ t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */
+ t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
+ t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */
+ cpu->isar.id_aa64smfr0 = t;
+
+ /* Replicate the same data to the 32-bit id registers. */
+ aa32_max_features(cpu);
+
+#ifdef CONFIG_USER_ONLY
+ /*
+ * For usermode -cpu max we can use a larger and more efficient DCZ
+ * blocksize since we don't have to follow what the hardware does.
+ */
+ cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
+ cpu->dcz_blocksize = 7; /* 512 bytes */
+#endif
+
+ cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
+ cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
+
+ aarch64_add_pauth_properties(obj);
+ aarch64_add_sve_properties(obj);
+ aarch64_add_sme_properties(obj);
+ object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
+ cpu_max_set_sve_max_vq, NULL, NULL);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
+}
+
+static const ARMCPUInfo aarch64_cpus[] = {
+ { .name = "cortex-a35", .initfn = aarch64_a35_initfn },
+ { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
+ { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
+ { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
+ { .name = "a64fx", .initfn = aarch64_a64fx_initfn },
+ { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
+};
+
+static void aarch64_cpu_register_types(void)
+{
+ size_t i;
+
+ for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
+ aarch64_cpu_register(&aarch64_cpus[i]);
+ }
+}
+
+type_init(aarch64_cpu_register_types)
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 25bc98999e..8debe81fd5 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -36,6 +36,7 @@ arm_ss.add(files(
))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
+ 'cpu64.c',
'translate-a64.c',
'translate-sve.c',
'translate-sme.c',
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 02/15] target/arm: move cpu_tcg to tcg/cpu32.c
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 01/15] target/arm: Move 64-bit TCG CPUs into tcg/ Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 03/15] target/arm: Remove default cpu for KVM-only builds Fabiano Rosas
` (12 subsequent siblings)
14 siblings, 0 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
From: Claudio Fontana <cfontana@suse.de>
move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/meson.build | 1 -
target/arm/{cpu_tcg.c => tcg/cpu32.c} | 13 +++----------
target/arm/tcg/cpu64.c | 2 +-
target/arm/tcg/meson.build | 1 +
4 files changed, 5 insertions(+), 12 deletions(-)
rename target/arm/{cpu_tcg.c => tcg/cpu32.c} (99%)
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 595d22a099..88f1a5c570 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -5,7 +5,6 @@ arm_ss.add(files(
'gdbstub.c',
'helper.c',
'vfp_helper.c',
- 'cpu_tcg.c',
))
arm_ss.add(zlib)
diff --git a/target/arm/cpu_tcg.c b/target/arm/tcg/cpu32.c
similarity index 99%
rename from target/arm/cpu_tcg.c
rename to target/arm/tcg/cpu32.c
index 64d5a785c1..caa5252ad9 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/tcg/cpu32.c
@@ -1,5 +1,5 @@
/*
- * QEMU ARM TCG CPUs.
+ * QEMU ARM TCG-only CPUs.
*
* Copyright (c) 2012 SUSE LINUX Products GmbH
*
@@ -10,9 +10,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#ifdef CONFIG_TCG
#include "hw/core/tcg-cpu-ops.h"
-#endif /* CONFIG_TCG */
#include "internals.h"
#include "target/arm/idau.h"
#if !defined(CONFIG_USER_ONLY)
@@ -93,7 +91,7 @@ void aa32_max_features(ARMCPU *cpu)
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+#if !defined(CONFIG_USER_ONLY)
static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
CPUClass *cc = CPU_GET_CLASS(cs);
@@ -117,7 +115,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
return ret;
}
-#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
+#endif /* !CONFIG_USER_ONLY */
static void arm926_initfn(Object *obj)
{
@@ -1013,7 +1011,6 @@ static void pxa270c5_initfn(Object *obj)
cpu->reset_sctlr = 0x00000078;
}
-#ifdef CONFIG_TCG
static const struct TCGCPUOps arm_v7m_tcg_ops = {
.initialize = arm_translate_init,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
@@ -1034,7 +1031,6 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = {
.debug_check_breakpoint = arm_debug_check_breakpoint,
#endif /* !CONFIG_USER_ONLY */
};
-#endif /* CONFIG_TCG */
static void arm_v7m_class_init(ObjectClass *oc, void *data)
{
@@ -1042,10 +1038,7 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
acc->info = data;
-#ifdef CONFIG_TCG
cc->tcg_ops = &arm_v7m_tcg_ops;
-#endif /* CONFIG_TCG */
-
cc->gdb_core_xml_file = "arm-m-profile.xml";
}
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 4d5bdddae4..92943853ce 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -457,7 +457,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
/*
* -cpu max: a CPU with as many features enabled as our emulation supports.
- * The version of '-cpu max' for qemu-system-arm is defined in cpu_tcg.c;
+ * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c;
* this only needs to handle 64 bits.
*/
void aarch64_max_tcg_initfn(Object *obj)
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index 8debe81fd5..cea1e594c1 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -18,6 +18,7 @@ gen = [
arm_ss.add(gen)
arm_ss.add(files(
+ 'cpu32.c',
'translate.c',
'translate-m-nocp.c',
'translate-mve.c',
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 03/15] target/arm: Remove default cpu for KVM-only builds
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 01/15] target/arm: Move 64-bit TCG CPUs into tcg/ Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 02/15] target/arm: move cpu_tcg to tcg/cpu32.c Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 20:19 ` Richard Henderson
2023-01-20 12:24 ` Daniel P. Berrangé
2023-01-19 13:54 ` [RFC PATCH v4 04/15] tests/qtest: arm-cpu-features: Match tests to required accelerators Fabiano Rosas
` (11 subsequent siblings)
14 siblings, 2 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Laurent Vivier
We'd prefer if the user always had to specify the machine and cpu
options in the command line instead of relying on defaults.
Since the KVM build already doesn't work with the current default of
cortex-a15, remove the default altogether for KVM builds.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
hw/arm/virt.c | 9 +++++++++
tests/qtest/arm-cpu-features.c | 12 +++++++++---
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index ea2413a0ba..fa8baf3156 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -203,8 +203,10 @@ static const int a15irqmap[] = {
};
static const char *valid_cpus[] = {
+#ifdef CONFIG_TCG
ARM_CPU_TYPE_NAME("cortex-a7"),
ARM_CPU_TYPE_NAME("cortex-a15"),
+#endif
ARM_CPU_TYPE_NAME("cortex-a35"),
ARM_CPU_TYPE_NAME("cortex-a53"),
ARM_CPU_TYPE_NAME("cortex-a55"),
@@ -2025,6 +2027,11 @@ static void machvirt_init(MachineState *machine)
unsigned int smp_cpus = machine->smp.cpus;
unsigned int max_cpus = machine->smp.max_cpus;
+ if (!machine->cpu_type) {
+ error_report("No -cpu specified, and there is no default");
+ exit(1);
+ }
+
if (!cpu_type_valid(machine->cpu_type)) {
error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
exit(1);
@@ -3003,7 +3010,9 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
mc->minimum_page_bits = 12;
mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
+#ifdef CONFIG_TCG
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
+#endif
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
mc->kvm_type = virt_kvm_type;
assert(!mc->get_hotplug_handler);
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 8691802950..4ff2014bea 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -506,9 +506,15 @@ static void test_query_cpu_model_expansion_kvm(const void *data)
QDict *resp;
char *error;
- assert_error(qts, "cortex-a15",
- "We cannot guarantee the CPU type 'cortex-a15' works "
- "with KVM on this host", NULL);
+ if (qtest_has_accel("tcg")) {
+ assert_error(qts, "cortex-a15",
+ "We cannot guarantee the CPU type 'cortex-a15' works "
+ "with KVM on this host", NULL);
+ } else {
+ assert_error(qts, "cortex-a15",
+ "The CPU type 'cortex-a15' is not a "
+ "recognized ARM CPU type", NULL);
+ }
assert_has_feature_enabled(qts, "host", "aarch64");
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 04/15] tests/qtest: arm-cpu-features: Match tests to required accelerators
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (2 preceding siblings ...)
2023-01-19 13:54 ` [RFC PATCH v4 03/15] target/arm: Remove default cpu for KVM-only builds Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 18:37 ` Richard Henderson
2023-01-20 10:11 ` Thomas Huth
2023-01-19 13:54 ` [RFC PATCH v4 05/15] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG Fabiano Rosas
` (10 subsequent siblings)
14 siblings, 2 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Laurent Vivier
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
tests/qtest/arm-cpu-features.c | 22 +++++++++++++++-------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
index 4ff2014bea..1555b0bab8 100644
--- a/tests/qtest/arm-cpu-features.c
+++ b/tests/qtest/arm-cpu-features.c
@@ -21,7 +21,7 @@
#define SVE_MAX_VQ 16
#define MACHINE "-machine virt,gic-version=max -accel tcg "
-#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg "
+#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
#define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \
" 'arguments': { 'type': 'full', "
#define QUERY_TAIL "}}"
@@ -613,31 +613,39 @@ int main(int argc, char **argv)
{
g_test_init(&argc, &argv, NULL);
- qtest_add_data_func("/arm/query-cpu-model-expansion",
- NULL, test_query_cpu_model_expansion);
+ if (qtest_has_accel("tcg")) {
+ qtest_add_data_func("/arm/query-cpu-model-expansion",
+ NULL, test_query_cpu_model_expansion);
+ }
+
+ if (!g_str_equal(qtest_get_arch(), "aarch64")) {
+ goto out;
+ }
/*
* For now we only run KVM specific tests with AArch64 QEMU in
* order avoid attempting to run an AArch32 QEMU with KVM on
* AArch64 hosts. That won't work and isn't easy to detect.
*/
- if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
+ if (qtest_has_accel("kvm")) {
/*
* This tests target the 'host' CPU type, so register it only if
* KVM is available.
*/
qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
NULL, test_query_cpu_model_expansion_kvm);
+
+ qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
+ NULL, sve_tests_sve_off_kvm);
}
- if (g_str_equal(qtest_get_arch(), "aarch64")) {
+ if (qtest_has_accel("tcg")) {
qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
NULL, sve_tests_sve_max_vq_8);
qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
NULL, sve_tests_sve_off);
- qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
- NULL, sve_tests_sve_off_kvm);
}
+out:
return g_test_run();
}
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 05/15] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (3 preceding siblings ...)
2023-01-19 13:54 ` [RFC PATCH v4 04/15] tests/qtest: arm-cpu-features: Match tests to required accelerators Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 18:39 ` Richard Henderson
` (2 more replies)
2023-01-19 13:54 ` [RFC PATCH v4 06/15] tests/qtest: Add qtest_get_machine_args Fabiano Rosas
` (9 subsequent siblings)
14 siblings, 3 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Laurent Vivier
These tests set -accel tcg, so restrict them to when TCG is present.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
tests/qtest/meson.build | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 1af63f8bd2..9dd5c2de6e 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -204,8 +204,8 @@ qtests_arm = \
# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
qtests_aarch64 = \
(cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \
- (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \
- (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \
+ (config_all_devices.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? \
+ ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \
(config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
(config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
['arm-cpu-features',
@@ -295,11 +295,15 @@ qtests = {
'tpm-crb-test': [io, tpmemu_files],
'tpm-tis-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'],
'tpm-tis-test': [io, tpmemu_files, 'tpm-tis-util.c'],
- 'tpm-tis-device-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'],
- 'tpm-tis-device-test': [io, tpmemu_files, 'tpm-tis-util.c'],
'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'),
}
+if config_all_devices.has_key('CONFIG_TCG')
+ qtests += { 'tpm-tis-device-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'],
+ 'tpm-tis-device-test': [io, tpmemu_files, 'tpm-tis-util.c'], }
+endif
+
+
gvnc = dependency('gvnc-1.0', required: false)
if gvnc.found()
qtests += {'vnc-display-test': [gvnc]}
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 06/15] tests/qtest: Add qtest_get_machine_args
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (4 preceding siblings ...)
2023-01-19 13:54 ` [RFC PATCH v4 05/15] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 18:55 ` Richard Henderson
2023-01-20 11:48 ` Thomas Huth
2023-01-19 13:54 ` [RFC PATCH v4 07/15] tests/qtest: Adjust qom-test to always set a -cpu option Fabiano Rosas
` (8 subsequent siblings)
14 siblings, 2 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Laurent Vivier
QEMU machines might not have a default value defined for the -cpu
option. Add a custom init function that takes care of selecting the
default cpu in case the test did not specify one. For the machines
that do not have a default, the value MUST be provided by the test.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
tests/qtest/libqtest.c | 99 ++++++++++++++++++++++++++++++++++++++++++
tests/qtest/libqtest.h | 11 +++++
2 files changed, 110 insertions(+)
diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c
index 5cb38f90da..db8a40f0c7 100644
--- a/tests/qtest/libqtest.c
+++ b/tests/qtest/libqtest.c
@@ -1265,8 +1265,57 @@ static bool qtest_is_old_versioned_machine(const char *mname)
struct MachInfo {
char *name;
char *alias;
+ char *default_cpu;
};
+static char *qtest_get_cpu_name(QString *type)
+{
+ QDict *response, *cpuinfo;
+ QList *list;
+ const QListEntry *p;
+ QObject *qobj;
+ QString *qstr;
+ QTestState *qts;
+ char *cname = NULL;
+
+ qts = qtest_init("-machine none");
+ response = qtest_qmp(qts, "{ 'execute': 'query-cpu-definitions' }");
+ g_assert(response);
+ list = qdict_get_qlist(response, "return");
+
+ if (!list) {
+ /* Not all architectures implement query-cpu-definitions */
+ goto out;
+ }
+
+ for (p = qlist_first(list); p; p = qlist_next(p)) {
+ cpuinfo = qobject_to(QDict, qlist_entry_obj(p));
+ g_assert(cpuinfo);
+
+ qobj = qdict_get(cpuinfo, "typename");
+ g_assert(qobj);
+ qstr = qobject_to(QString, qobj);
+ g_assert(qstr);
+
+ if (g_str_equal(qstring_get_str(qstr),
+ qstring_get_str(type))) {
+ qobj = qdict_get(cpuinfo, "name");
+ g_assert(qobj);
+ qstr = qobject_to(QString, qobj);
+ g_assert(qstr);
+
+ cname = g_strdup(qstring_get_str(qstr));
+ break;
+ }
+ }
+
+out:
+ qtest_quit(qts);
+ qobject_unref(response);
+
+ return cname;
+}
+
/*
* Returns an array with pointers to the available machine names.
* The terminating entry has the name set to NULL.
@@ -1312,6 +1361,15 @@ static struct MachInfo *qtest_get_machines(void)
} else {
machines[idx].alias = NULL;
}
+
+ qobj = qdict_get(minfo, "default-cpu-type");
+ if (qobj) { /* The default cpu is optional */
+ qstr = qobject_to(QString, qobj);
+ g_assert(qstr);
+ machines[idx].default_cpu = qtest_get_cpu_name(qstr);
+ } else {
+ machines[idx].default_cpu = NULL;
+ }
}
qtest_quit(qts);
@@ -1321,6 +1379,47 @@ static struct MachInfo *qtest_get_machines(void)
return machines;
}
+static const char *qtest_get_default_cpu(const char* machine)
+{
+ struct MachInfo *machines;
+ char *cpu = NULL;
+ int i;
+
+ if (g_str_equal(machine, "none")) {
+ return cpu;
+ }
+
+ machines = qtest_get_machines();
+
+ for (i = 0; machines[i].name != NULL; i++) {
+ if (g_str_equal(machines[i].name, machine)) {
+ cpu = machines[i].default_cpu;
+ break;
+ }
+ }
+
+ return cpu;
+}
+
+char *qtest_get_machine_args(const char *mname, const char *cname,
+ const char *extra_args)
+{
+ const char *cpu;
+
+ cpu = cname ?: qtest_get_default_cpu(mname);
+ if (!cpu) {
+ /*
+ * There is no default cpu and the test did not provide a cpu
+ * name for this architecture/machine combination. The QEMU
+ * binary might still know how to select a cpu, so leave the
+ * -cpu option out.
+ */
+ return g_strdup_printf("-machine %s %s", mname, extra_args ?: "");
+ }
+ return g_strdup_printf("-machine %s -cpu %s %s", mname, cpu,
+ extra_args ?: "");
+}
+
void qtest_cb_for_every_machine(void (*cb)(const char *machine),
bool skip_old_versioned)
{
diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h
index fcf1c3c3b3..f86f876c17 100644
--- a/tests/qtest/libqtest.h
+++ b/tests/qtest/libqtest.h
@@ -75,6 +75,17 @@ QTestState *qtest_init_without_qmp_handshake(const char *extra_args);
*/
QTestState *qtest_init_with_serial(const char *extra_args, int *sock_fd);
+/**
+ * qtest_get_machine_args:
+ * @mname: the machine name.
+ * @cname: the cpu name.
+ * @extra_args: other arguments to concatenated in the args string.
+ *
+ * Returns: pointer to args.
+ */
+char *qtest_get_machine_args(const char *mname, const char *cname,
+ const char *extra_args);
+
/**
* qtest_wait_qemu:
* @s: #QTestState instance to operate on.
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 07/15] tests/qtest: Adjust qom-test to always set a -cpu option
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (5 preceding siblings ...)
2023-01-19 13:54 ` [RFC PATCH v4 06/15] tests/qtest: Add qtest_get_machine_args Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 19:00 ` Richard Henderson
2023-01-19 13:54 ` [RFC PATCH v4 08/15] tests/qtest: Adjust test-hmp to always pass " Fabiano Rosas
` (7 subsequent siblings)
14 siblings, 1 reply; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Laurent Vivier
Start using the qtest_get_machine_args function, which explicitly
sets the -cpu option according to the machine default.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
tests/qtest/qom-test.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/qom-test.c b/tests/qtest/qom-test.c
index d380261f8f..462e3c4281 100644
--- a/tests/qtest/qom-test.c
+++ b/tests/qtest/qom-test.c
@@ -78,14 +78,28 @@ static void test_properties(QTestState *qts, const char *path, bool recurse)
qobject_unref(response);
}
+static const char *arch_get_cpu(const char *machine)
+{
+ const char *arch = qtest_get_arch();
+
+ if (g_str_equal(arch, "aarch64")) {
+ if (!strncmp(machine, "virt", 4)) {
+ return "cortex-a57";
+ }
+ }
+
+ return NULL;
+}
+
static void test_machine(gconstpointer data)
{
const char *machine = data;
+ char *args;
QDict *response;
QTestState *qts;
- qts = qtest_initf("-machine %s", machine);
-
+ args = qtest_get_machine_args(machine, arch_get_cpu(machine), NULL);
+ qts = qtest_init(args);
test_properties(qts, "/machine", true);
response = qtest_qmp(qts, "{ 'execute': 'quit' }");
@@ -94,6 +108,7 @@ static void test_machine(gconstpointer data)
qtest_quit(qts);
g_free((void *)machine);
+ g_free((void *)args);
}
static void add_machine_test_case(const char *mname)
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 08/15] tests/qtest: Adjust test-hmp to always pass -cpu option
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (6 preceding siblings ...)
2023-01-19 13:54 ` [RFC PATCH v4 07/15] tests/qtest: Adjust qom-test to always set a -cpu option Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 14:06 ` Dr. David Alan Gilbert
2023-01-19 13:54 ` [RFC PATCH v4 09/15] tests/qtest: Adjust device-introspect-test to always set a " Fabiano Rosas
` (6 subsequent siblings)
14 siblings, 1 reply; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Dr. David Alan Gilbert, Thomas Huth, Laurent Vivier
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
tests/qtest/test-hmp.c | 34 +++++++++++++++++++++++++++++++---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/tests/qtest/test-hmp.c b/tests/qtest/test-hmp.c
index f8b22abe4c..c367612d4a 100644
--- a/tests/qtest/test-hmp.c
+++ b/tests/qtest/test-hmp.c
@@ -121,21 +121,49 @@ static void test_info_commands(QTestState *qts)
g_free(info_buf);
}
+static const char *arch_get_cpu(const char *machine)
+{
+ const char *arch = qtest_get_arch();
+
+ if (g_str_equal(arch, "aarch64")) {
+ if (!strncmp(machine, "virt", 4)) {
+ return "cortex-a57";
+ }
+ }
+
+ return NULL;
+}
+
static void test_machine(gconstpointer data)
{
const char *machine = data;
char *args;
QTestState *qts;
- args = g_strdup_printf("-S -M %s", machine);
+ args = qtest_get_machine_args(machine, arch_get_cpu(machine), "-S");
qts = qtest_init(args);
test_info_commands(qts);
test_commands(qts);
qtest_quit(qts);
- g_free(args);
g_free((void *)data);
+ g_free((void *)args);
+}
+
+static void test_none_with_memory(void)
+{
+ QTestState *qts;
+ char *args;
+
+ args = qtest_get_machine_args("none", NULL, "-S -m 2");
+ qts = qtest_init(args);
+
+ test_info_commands(qts);
+ test_commands(qts);
+
+ qtest_quit(qts);
+ g_free((void *)args);
}
static void add_machine_test_case(const char *mname)
@@ -160,7 +188,7 @@ int main(int argc, char **argv)
qtest_cb_for_every_machine(add_machine_test_case, g_test_quick());
/* as none machine has no memory by default, add a test case with memory */
- qtest_add_data_func("hmp/none+2MB", g_strdup("none -m 2"), test_machine);
+ qtest_add_func("hmp/none+2MB", test_none_with_memory);
return g_test_run();
}
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 09/15] tests/qtest: Adjust device-introspect-test to always set a -cpu option
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (7 preceding siblings ...)
2023-01-19 13:54 ` [RFC PATCH v4 08/15] tests/qtest: Adjust test-hmp to always pass " Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 10/15] tests/qtest: aarch64: Set -cpu for numa-test Fabiano Rosas
` (5 subsequent siblings)
14 siblings, 0 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Laurent Vivier
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
tests/qtest/device-introspect-test.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/tests/qtest/device-introspect-test.c b/tests/qtest/device-introspect-test.c
index 5b0ffe43f5..7d6ff6e3ef 100644
--- a/tests/qtest/device-introspect-test.c
+++ b/tests/qtest/device-introspect-test.c
@@ -304,17 +304,30 @@ static void test_abstract_interfaces(void)
qtest_quit(qts);
}
+static const char *arch_get_cpu(const char *mname)
+{
+ const char *arch = qtest_get_arch();
+
+ if (g_str_equal(arch, "aarch64")) {
+ if (!strncmp(mname, "virt", 4)) {
+ return "cortex-a57";
+ }
+ }
+
+ return NULL;
+}
+
static void add_machine_test_case(const char *mname)
{
char *path, *args;
path = g_strdup_printf("device/introspect/concrete/defaults/%s", mname);
- args = g_strdup_printf("-M %s", mname);
+ args = qtest_get_machine_args(mname, arch_get_cpu(mname), NULL);
qtest_add_data_func(path, args, test_device_intro_concrete);
g_free(path);
path = g_strdup_printf("device/introspect/concrete/nodefaults/%s", mname);
- args = g_strdup_printf("-nodefaults -M %s", mname);
+ args = qtest_get_machine_args(mname, arch_get_cpu(mname), "-nodefaults");
qtest_add_data_func(path, args, test_device_intro_concrete);
g_free(path);
}
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 10/15] tests/qtest: aarch64: Set -cpu for numa-test
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (8 preceding siblings ...)
2023-01-19 13:54 ` [RFC PATCH v4 09/15] tests/qtest: Adjust device-introspect-test to always set a " Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 11/15] tests/qemu-iotests: Allow passing a -cpu option in the QEMU cmdline Fabiano Rosas
` (4 subsequent siblings)
14 siblings, 0 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Laurent Vivier
The aarch64 KVM-only builds no longer have a default cpu. We need to
explicitly give one in the command line.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
tests/qtest/numa-test.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c
index c5eb13f349..7a6cf17b2a 100644
--- a/tests/qtest/numa-test.c
+++ b/tests/qtest/numa-test.c
@@ -559,6 +559,7 @@ int main(int argc, char **argv)
if (g_str_equal(arch, "aarch64")) {
g_string_append(args, " -machine virt");
+ g_string_append(args, " -cpu cortex-a57");
}
g_test_init(&argc, &argv, NULL);
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 11/15] tests/qemu-iotests: Allow passing a -cpu option in the QEMU cmdline
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (9 preceding siblings ...)
2023-01-19 13:54 ` [RFC PATCH v4 10/15] tests/qtest: aarch64: Set -cpu for numa-test Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 19:09 ` Richard Henderson
2023-01-19 13:54 ` [RFC PATCH v4 12/15] tests/tcg: Do not build/run TCG tests if TCG is disabled Fabiano Rosas
` (3 subsequent siblings)
14 siblings, 1 reply; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Kevin Wolf, Hanna Reitz
We're removing the default CPU from aarch64. Every QEMU invocation is
expected to have an explicit -cpu value.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
tests/qemu-iotests/testenv.py | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/tests/qemu-iotests/testenv.py b/tests/qemu-iotests/testenv.py
index a864c74b12..4bb80ea656 100644
--- a/tests/qemu-iotests/testenv.py
+++ b/tests/qemu-iotests/testenv.py
@@ -244,6 +244,13 @@ def __init__(self, imgfmt: str, imgproto: str, aiomode: str,
if self.qemu_prog.endswith(f'qemu-system-{suffix}'):
self.qemu_options += f' -machine {machine}'
+ cpu_map = (
+ ('aarch64', 'cortex-a57'),
+ )
+ for suffix, cpu in cpu_map:
+ if self.qemu_prog.endswith(f'qemu-system-{suffix}'):
+ self.qemu_options += f' -cpu {cpu}'
+
# QEMU_DEFAULT_MACHINE
self.qemu_default_machine = get_default_machine(self.qemu_prog)
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 12/15] tests/tcg: Do not build/run TCG tests if TCG is disabled
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (10 preceding siblings ...)
2023-01-19 13:54 ` [RFC PATCH v4 11/15] tests/qemu-iotests: Allow passing a -cpu option in the QEMU cmdline Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 18:52 ` Richard Henderson
2023-01-19 19:49 ` Philippe Mathieu-Daudé
2023-01-19 13:54 ` [RFC PATCH v4 13/15] target/avocado: Pass parameters to migration test on aarch64 Fabiano Rosas
` (2 subsequent siblings)
14 siblings, 2 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth
The tests under tests/tcg depend on the TCG accelerator. Do not build
them if --disable-tcg was given in the configure line.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
configure | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/configure b/configure
index 9e407ce2e3..64960c6000 100755
--- a/configure
+++ b/configure
@@ -2483,7 +2483,11 @@ for target in $target_list; do
tcg_tests_targets="$tcg_tests_targets $target"
fi
done
-echo "TCG_TESTS_TARGETS=$tcg_tests_targets" >> config-host.mak)
+
+if test "$tcg" = "enabled"; then
+ echo "TCG_TESTS_TARGETS=$tcg_tests_targets" >> config-host.mak
+fi
+)
if test "$skip_meson" = no; then
cross="config-meson.cross.new"
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 13/15] target/avocado: Pass parameters to migration test on aarch64
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (11 preceding siblings ...)
2023-01-19 13:54 ` [RFC PATCH v4 12/15] tests/tcg: Do not build/run TCG tests if TCG is disabled Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 19:29 ` Richard Henderson
2023-01-19 13:54 ` [RFC PATCH v4 14/15] arm/Kconfig: Always select SEMIHOSTING when TCG is present Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 15/15] arm/Kconfig: Do not build TCG-only boards on a KVM-only build Fabiano Rosas
14 siblings, 1 reply; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Cleber Rosa, Wainer dos Santos Moschetta, Beraldo Leal
The migration tests are currently broken for an aarch64 host because
the tests pass no 'machine' and 'cpu' options on the QEMU command
line. Most other architectures define a default value in QEMU for
these options, but arm does not.
Add these options to the test class in case the test is being executed
in an aarch64 host.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
Don't we want to run migration tests for all the built targets? A
cleaner approach would be to just subclass Migration for each
archictecture like in boot_linux.py.
---
tests/avocado/migration.py | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/tests/avocado/migration.py b/tests/avocado/migration.py
index 4b25680c50..f1c43622c0 100644
--- a/tests/avocado/migration.py
+++ b/tests/avocado/migration.py
@@ -11,6 +11,8 @@
import tempfile
+import os
+
from avocado_qemu import QemuSystemTest
from avocado import skipUnless
@@ -26,6 +28,14 @@ class Migration(QemuSystemTest):
timeout = 10
+ def setUp(self):
+ super().setUp()
+
+ arch = os.uname()[4]
+ if arch == 'aarch64':
+ self.machine = 'virt'
+ self.cpu = 'max'
+
@staticmethod
def migration_finished(vm):
return vm.command('query-migrate')['status'] in ('completed', 'failed')
@@ -62,7 +72,6 @@ def _get_free_port(self):
self.cancel('Failed to find a free port')
return port
-
def test_migration_with_tcp_localhost(self):
dest_uri = 'tcp:localhost:%u' % self._get_free_port()
self.do_migrate(dest_uri)
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 14/15] arm/Kconfig: Always select SEMIHOSTING when TCG is present
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (12 preceding siblings ...)
2023-01-19 13:54 ` [RFC PATCH v4 13/15] target/avocado: Pass parameters to migration test on aarch64 Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 18:50 ` Richard Henderson
2023-01-19 13:54 ` [RFC PATCH v4 15/15] arm/Kconfig: Do not build TCG-only boards on a KVM-only build Fabiano Rosas
14 siblings, 1 reply; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
We are about to enable the build without TCG, so CONFIG_SEMIHOSTING
and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in
default.mak anymore. So reflect the change in a Kconfig.
Instead of using semihosting/Kconfig, use a target-specific file, so
that the change doesn't affect other architectures which might
implement semihosting in a way compatible with KVM.
The selection from ARM_v7M needs to be removed to avoid a cycle during
parsing.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
The linux-user build does not use Kconfig. Is it worth it to add
support to it? There's just the semihosting config so far.
---
configs/devices/arm-softmmu/default.mak | 2 --
hw/arm/Kconfig | 1 -
target/arm/Kconfig | 7 +++++++
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
index 1b49a7830c..cb3e5aea65 100644
--- a/configs/devices/arm-softmmu/default.mak
+++ b/configs/devices/arm-softmmu/default.mak
@@ -40,6 +40,4 @@ CONFIG_MICROBIT=y
CONFIG_FSL_IMX25=y
CONFIG_FSL_IMX7=y
CONFIG_FSL_IMX6UL=y
-CONFIG_SEMIHOSTING=y
-CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
CONFIG_ALLWINNER_H3=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 19d6b9d95f..e0da8841db 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -316,7 +316,6 @@ config ARM_V7M
# currently v7M must be included in a TCG build due to translate.c
default y if TCG && (ARM || AARCH64)
select PTIMER
- select ARM_COMPATIBLE_SEMIHOSTING
config ALLWINNER_A10
bool
diff --git a/target/arm/Kconfig b/target/arm/Kconfig
index 3f3394a22b..39f05b6420 100644
--- a/target/arm/Kconfig
+++ b/target/arm/Kconfig
@@ -4,3 +4,10 @@ config ARM
config AARCH64
bool
select ARM
+
+# This config exists just so we can make SEMIHOSTING default when TCG
+# is selected without also changing it for other architectures.
+config ARM_SEMIHOSTING
+ bool
+ default y if TCG && ARM
+ select ARM_COMPATIBLE_SEMIHOSTING
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* [RFC PATCH v4 15/15] arm/Kconfig: Do not build TCG-only boards on a KVM-only build
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
` (13 preceding siblings ...)
2023-01-19 13:54 ` [RFC PATCH v4 14/15] arm/Kconfig: Always select SEMIHOSTING when TCG is present Fabiano Rosas
@ 2023-01-19 13:54 ` Fabiano Rosas
2023-01-19 18:50 ` Richard Henderson
14 siblings, 1 reply; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 13:54 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
Move all the CONFIG_FOO=y from default.mak into "default y if TCG"
statements in Kconfig. That way they won't be selected when
CONFIG_TCG=n.
I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to
keep the two default.mak files not empty and keep aarch64-default.mak
including arm-default.mak. That way we don't surprise anyone that's
used to altering these files.
With this change we can start building with --disable-tcg.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
---
sbsa-ref has an explicit check to avoid running with KVM
xlnx-versal-virt has avocado tests tagged with tcg
---
configs/devices/aarch64-softmmu/default.mak | 4 --
configs/devices/arm-softmmu/default.mak | 37 ------------------
hw/arm/Kconfig | 42 ++++++++++++++++++++-
3 files changed, 41 insertions(+), 42 deletions(-)
diff --git a/configs/devices/aarch64-softmmu/default.mak b/configs/devices/aarch64-softmmu/default.mak
index cf43ac8da1..70e05a197d 100644
--- a/configs/devices/aarch64-softmmu/default.mak
+++ b/configs/devices/aarch64-softmmu/default.mak
@@ -2,7 +2,3 @@
# We support all the 32 bit boards so need all their config
include ../arm-softmmu/default.mak
-
-CONFIG_XLNX_ZYNQMP_ARM=y
-CONFIG_XLNX_VERSAL=y
-CONFIG_SBSA_REF=y
diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak
index cb3e5aea65..647fbce88d 100644
--- a/configs/devices/arm-softmmu/default.mak
+++ b/configs/devices/arm-softmmu/default.mak
@@ -4,40 +4,3 @@
# CONFIG_TEST_DEVICES=n
CONFIG_ARM_VIRT=y
-CONFIG_CUBIEBOARD=y
-CONFIG_EXYNOS4=y
-CONFIG_HIGHBANK=y
-CONFIG_INTEGRATOR=y
-CONFIG_FSL_IMX31=y
-CONFIG_MUSICPAL=y
-CONFIG_MUSCA=y
-CONFIG_CHEETAH=y
-CONFIG_SX1=y
-CONFIG_NSERIES=y
-CONFIG_STELLARIS=y
-CONFIG_STM32VLDISCOVERY=y
-CONFIG_REALVIEW=y
-CONFIG_VERSATILE=y
-CONFIG_VEXPRESS=y
-CONFIG_ZYNQ=y
-CONFIG_MAINSTONE=y
-CONFIG_GUMSTIX=y
-CONFIG_SPITZ=y
-CONFIG_TOSA=y
-CONFIG_Z2=y
-CONFIG_NPCM7XX=y
-CONFIG_COLLIE=y
-CONFIG_ASPEED_SOC=y
-CONFIG_NETDUINO2=y
-CONFIG_NETDUINOPLUS2=y
-CONFIG_OLIMEX_STM32_H405=y
-CONFIG_MPS2=y
-CONFIG_RASPI=y
-CONFIG_DIGIC=y
-CONFIG_SABRELITE=y
-CONFIG_EMCRAFT_SF2=y
-CONFIG_MICROBIT=y
-CONFIG_FSL_IMX25=y
-CONFIG_FSL_IMX7=y
-CONFIG_FSL_IMX6UL=y
-CONFIG_ALLWINNER_H3=y
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index e0da8841db..4a2460311a 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -34,20 +34,24 @@ config ARM_VIRT
config CHEETAH
bool
+ default y if TCG && ARM
select OMAP
select TSC210X
config CUBIEBOARD
bool
+ default y if TCG && ARM
select ALLWINNER_A10
config DIGIC
bool
+ default y if TCG && ARM
select PTIMER
select PFLASH_CFI02
config EXYNOS4
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select A9MPCORE
select I2C
@@ -60,6 +64,7 @@ config EXYNOS4
config HIGHBANK
bool
+ default y if TCG && ARM
select A9MPCORE
select A15MPCORE
select AHCI
@@ -74,6 +79,7 @@ config HIGHBANK
config INTEGRATOR
bool
+ default y if TCG && ARM
select ARM_TIMER
select INTEGRATOR_DEBUG
select PL011 # UART
@@ -86,12 +92,14 @@ config INTEGRATOR
config MAINSTONE
bool
+ default y if TCG && ARM
select PXA2XX
select PFLASH_CFI01
select SMC91C111
config MUSCA
bool
+ default y if TCG && ARM
select ARMSSE
select PL011
select PL031
@@ -103,6 +111,7 @@ config MARVELL_88W8618
config MUSICPAL
bool
+ default y if TCG && ARM
select OR_IRQ
select BITBANG_I2C
select MARVELL_88W8618
@@ -113,18 +122,22 @@ config MUSICPAL
config NETDUINO2
bool
+ default y if TCG && ARM
select STM32F205_SOC
config NETDUINOPLUS2
bool
+ default y if TCG && ARM
select STM32F405_SOC
config OLIMEX_STM32_H405
bool
+ default y if TCG && ARM
select STM32F405_SOC
config NSERIES
bool
+ default y if TCG && ARM
select OMAP
select TMP105 # tempature sensor
select BLIZZARD # LCD/TV controller
@@ -157,12 +170,14 @@ config PXA2XX
config GUMSTIX
bool
+ default y if TCG && ARM
select PFLASH_CFI01
select SMC91C111
select PXA2XX
config TOSA
bool
+ default y if TCG && ARM
select ZAURUS # scoop
select MICRODRIVE
select PXA2XX
@@ -170,6 +185,7 @@ config TOSA
config SPITZ
bool
+ default y if TCG && ARM
select ADS7846 # touch-screen controller
select MAX111X # A/D converter
select WM8750 # audio codec
@@ -182,6 +198,7 @@ config SPITZ
config Z2
bool
+ default y if TCG && ARM
select PFLASH_CFI01
select WM8750
select PL011 # UART
@@ -189,6 +206,7 @@ config Z2
config REALVIEW
bool
+ default y if TCG && ARM
imply PCI_DEVICES
imply PCI_TESTDEV
imply I2C_DEVICES
@@ -217,6 +235,7 @@ config REALVIEW
config SBSA_REF
bool
+ default y if TCG && AARCH64
imply PCI_DEVICES
select AHCI
select ARM_SMMUV3
@@ -232,11 +251,13 @@ config SBSA_REF
config SABRELITE
bool
+ default y if TCG && ARM
select FSL_IMX6
select SSI_M25P80
config STELLARIS
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select ARM_V7M
select CMSDK_APB_WATCHDOG
@@ -254,6 +275,7 @@ config STELLARIS
config STM32VLDISCOVERY
bool
+ default y if TCG && ARM
select STM32F100_SOC
config STRONGARM
@@ -262,16 +284,19 @@ config STRONGARM
config COLLIE
bool
+ default y if TCG && ARM
select PFLASH_CFI01
select ZAURUS # scoop
select STRONGARM
config SX1
bool
+ default y if TCG && ARM
select OMAP
config VERSATILE
bool
+ default y if TCG && ARM
select ARM_TIMER # sp804
select PFLASH_CFI01
select LSI_SCSI_PCI
@@ -283,6 +308,7 @@ config VERSATILE
config VEXPRESS
bool
+ default y if TCG && ARM
select A9MPCORE
select A15MPCORE
select ARM_MPTIMER
@@ -298,6 +324,7 @@ config VEXPRESS
config ZYNQ
bool
+ default y if TCG && ARM
select A9MPCORE
select CADENCE # UART
select PFLASH_CFI02
@@ -314,7 +341,7 @@ config ZYNQ
config ARM_V7M
bool
# currently v7M must be included in a TCG build due to translate.c
- default y if TCG && (ARM || AARCH64)
+ default y if TCG && ARM
select PTIMER
config ALLWINNER_A10
@@ -332,6 +359,7 @@ config ALLWINNER_A10
config ALLWINNER_H3
bool
+ default y if TCG && ARM
select ALLWINNER_A10_PIT
select ALLWINNER_SUN8I_EMAC
select ALLWINNER_I2C
@@ -345,6 +373,7 @@ config ALLWINNER_H3
config RASPI
bool
+ default y if TCG && ARM
select FRAMEBUFFER
select PL011 # UART
select SDHCI
@@ -375,6 +404,7 @@ config STM32F405_SOC
config XLNX_ZYNQMP_ARM
bool
+ default y if TCG && AARCH64
select AHCI
select ARM_GIC
select CADENCE
@@ -391,6 +421,7 @@ config XLNX_ZYNQMP_ARM
config XLNX_VERSAL
bool
+ default y if TCG && AARCH64
select ARM_GIC
select PL011
select CADENCE
@@ -404,6 +435,7 @@ config XLNX_VERSAL
config NPCM7XX
bool
+ default y if TCG && ARM
select A9MPCORE
select ADM1272
select ARM_GIC
@@ -420,6 +452,7 @@ config NPCM7XX
config FSL_IMX25
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select IMX
select IMX_FEC
@@ -429,6 +462,7 @@ config FSL_IMX25
config FSL_IMX31
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select SERIAL
select IMX
@@ -449,6 +483,7 @@ config FSL_IMX6
config ASPEED_SOC
bool
+ default y if TCG && ARM
select DS1338
select FTGMAC100
select I2C
@@ -469,6 +504,7 @@ config ASPEED_SOC
config MPS2
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select ARMSSE
select LAN9118
@@ -484,6 +520,7 @@ config MPS2
config FSL_IMX7
bool
+ default y if TCG && ARM
imply PCI_DEVICES
imply TEST_DEVICES
imply I2C_DEVICES
@@ -502,6 +539,7 @@ config ARM_SMMUV3
config FSL_IMX6UL
bool
+ default y if TCG && ARM
imply I2C_DEVICES
select A15MPCORE
select IMX
@@ -513,6 +551,7 @@ config FSL_IMX6UL
config MICROBIT
bool
+ default y if TCG && ARM
select NRF51_SOC
config NRF51_SOC
@@ -524,6 +563,7 @@ config NRF51_SOC
config EMCRAFT_SF2
bool
+ default y if TCG && ARM
select MSF2
select SSI_M25P80
--
2.35.3
^ permalink raw reply related [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 08/15] tests/qtest: Adjust test-hmp to always pass -cpu option
2023-01-19 13:54 ` [RFC PATCH v4 08/15] tests/qtest: Adjust test-hmp to always pass " Fabiano Rosas
@ 2023-01-19 14:06 ` Dr. David Alan Gilbert
2023-01-19 14:39 ` Fabiano Rosas
0 siblings, 1 reply; 45+ messages in thread
From: Dr. David Alan Gilbert @ 2023-01-19 14:06 UTC (permalink / raw)
To: Fabiano Rosas
Cc: qemu-devel, qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Laurent Vivier
* Fabiano Rosas (farosas@suse.de) wrote:
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> tests/qtest/test-hmp.c | 34 +++++++++++++++++++++++++++++++---
> 1 file changed, 31 insertions(+), 3 deletions(-)
>
> diff --git a/tests/qtest/test-hmp.c b/tests/qtest/test-hmp.c
> index f8b22abe4c..c367612d4a 100644
> --- a/tests/qtest/test-hmp.c
> +++ b/tests/qtest/test-hmp.c
> @@ -121,21 +121,49 @@ static void test_info_commands(QTestState *qts)
> g_free(info_buf);
> }
>
> +static const char *arch_get_cpu(const char *machine)
> +{
> + const char *arch = qtest_get_arch();
> +
> + if (g_str_equal(arch, "aarch64")) {
> + if (!strncmp(machine, "virt", 4)) {
> + return "cortex-a57";
Won't that break on a kvm host on a different CPU?
Would -cpu max work on everything?
Dave
> + }
> + }
> +
> + return NULL;
> +}
> +
> static void test_machine(gconstpointer data)
> {
> const char *machine = data;
> char *args;
> QTestState *qts;
>
> - args = g_strdup_printf("-S -M %s", machine);
> + args = qtest_get_machine_args(machine, arch_get_cpu(machine), "-S");
> qts = qtest_init(args);
>
> test_info_commands(qts);
> test_commands(qts);
>
> qtest_quit(qts);
> - g_free(args);
> g_free((void *)data);
> + g_free((void *)args);
> +}
> +
> +static void test_none_with_memory(void)
> +{
> + QTestState *qts;
> + char *args;
> +
> + args = qtest_get_machine_args("none", NULL, "-S -m 2");
> + qts = qtest_init(args);
> +
> + test_info_commands(qts);
> + test_commands(qts);
> +
> + qtest_quit(qts);
> + g_free((void *)args);
> }
>
> static void add_machine_test_case(const char *mname)
> @@ -160,7 +188,7 @@ int main(int argc, char **argv)
> qtest_cb_for_every_machine(add_machine_test_case, g_test_quick());
>
> /* as none machine has no memory by default, add a test case with memory */
> - qtest_add_data_func("hmp/none+2MB", g_strdup("none -m 2"), test_machine);
> + qtest_add_func("hmp/none+2MB", test_none_with_memory);
>
> return g_test_run();
> }
> --
> 2.35.3
>
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 08/15] tests/qtest: Adjust test-hmp to always pass -cpu option
2023-01-19 14:06 ` Dr. David Alan Gilbert
@ 2023-01-19 14:39 ` Fabiano Rosas
0 siblings, 0 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 14:39 UTC (permalink / raw)
To: Dr. David Alan Gilbert
Cc: qemu-devel, qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Laurent Vivier
"Dr. David Alan Gilbert" <dgilbert@redhat.com> writes:
> * Fabiano Rosas (farosas@suse.de) wrote:
>> Signed-off-by: Fabiano Rosas <farosas@suse.de>
>> ---
>> tests/qtest/test-hmp.c | 34 +++++++++++++++++++++++++++++++---
>> 1 file changed, 31 insertions(+), 3 deletions(-)
>>
>> diff --git a/tests/qtest/test-hmp.c b/tests/qtest/test-hmp.c
>> index f8b22abe4c..c367612d4a 100644
>> --- a/tests/qtest/test-hmp.c
>> +++ b/tests/qtest/test-hmp.c
>> @@ -121,21 +121,49 @@ static void test_info_commands(QTestState *qts)
>> g_free(info_buf);
>> }
>>
>> +static const char *arch_get_cpu(const char *machine)
>> +{
>> + const char *arch = qtest_get_arch();
>> +
>> + if (g_str_equal(arch, "aarch64")) {
>> + if (!strncmp(machine, "virt", 4)) {
>> + return "cortex-a57";
>
> Won't that break on a kvm host on a different CPU?
> Would -cpu max work on everything?
These tests run with -accel qtest only. No TCG or KVM. So this won't
break a KVM host with a different CPU. But we also cannot expect that
cpu to do anything useful. This is more to avoid initial configuration
code to break due to lack of cpu.
About -cpu max, before this series, it works because of a nuance of the
code which does:
aarch64_max_initfn:
if kvm || hvf
host
else
cortex-a57
extra_features that depend on TCG
After this series this becomes roughly (see patch 01):
aarch64_max_initfn:
if kvm || hvf
host
else if qtest
cortex-a57
#ifdef CONFIG_TCG
else if tcg
cortex-a57
extra_features that depend on TCG
#endif
The above routine causes us to have two different -cpu max depending on
whether TCG is built in or not, so I'm basically bypassing it and
hardcoding cortex-a57 to be consistent.
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 01/15] target/arm: Move 64-bit TCG CPUs into tcg/
2023-01-19 13:54 ` [RFC PATCH v4 01/15] target/arm: Move 64-bit TCG CPUs into tcg/ Fabiano Rosas
@ 2023-01-19 18:31 ` Richard Henderson
2023-01-19 19:07 ` Fabiano Rosas
0 siblings, 1 reply; 45+ messages in thread
From: Richard Henderson @ 2023-01-19 18:31 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck
On 1/19/23 03:54, Fabiano Rosas wrote:
> Move the 64-bit CPUs that are TCG-only:
> - cortex-a35
> - cortex-a55
> - cortex-a72
> - cortex-a76
> - a64fx
> - neoverse-n1
>
> Keep the CPUs that can be used with KVM:
> - cortex-a57
> - cortex-a53
> - max
> - host
All of those cpus can be used with kvm, if and only if you have matching hardware. There
is no rationale for considering any of them differently.
r~
>
> For the special case "max" CPU, there's a nuance that while KVM/HVF
> use the "host" model instead, we still cannot move all of the TCG code
> into the tcg directory because the qtests might reach the !kvm && !hvf
> branch. Keep the cortex_a57_initfn() call to cover that scenario.
>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> target/arm/cpu64.c | 633 +----------------------------------
> target/arm/internals.h | 4 +
> target/arm/tcg/cpu64.c | 654 +++++++++++++++++++++++++++++++++++++
> target/arm/tcg/meson.build | 1 +
> 4 files changed, 671 insertions(+), 621 deletions(-)
> create mode 100644 target/arm/tcg/cpu64.c
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 5dfdae7bd2..226f57c669 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -24,6 +24,8 @@
> #include "qemu/module.h"
> #include "sysemu/kvm.h"
> #include "sysemu/hvf.h"
> +#include "sysemu/qtest.h"
> +#include "sysemu/tcg.h"
> #include "kvm_arm.h"
> #include "hvf_arm.h"
> #include "qapi/visitor.h"
> @@ -31,86 +33,6 @@
> #include "internals.h"
> #include "cpregs.h"
>
> -static void aarch64_a35_initfn(Object *obj)
> -{
> - ARMCPU *cpu = ARM_CPU(obj);
> -
> - cpu->dtb_compatible = "arm,cortex-a35";
> - set_feature(&cpu->env, ARM_FEATURE_V8);
> - set_feature(&cpu->env, ARM_FEATURE_NEON);
> - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> - set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> - set_feature(&cpu->env, ARM_FEATURE_EL2);
> - set_feature(&cpu->env, ARM_FEATURE_EL3);
> - set_feature(&cpu->env, ARM_FEATURE_PMU);
> -
> - /* From B2.2 AArch64 identification registers. */
> - cpu->midr = 0x411fd040;
> - cpu->revidr = 0;
> - cpu->ctr = 0x84448004;
> - cpu->isar.id_pfr0 = 0x00000131;
> - cpu->isar.id_pfr1 = 0x00011011;
> - cpu->isar.id_dfr0 = 0x03010066;
> - cpu->id_afr0 = 0;
> - cpu->isar.id_mmfr0 = 0x10201105;
> - cpu->isar.id_mmfr1 = 0x40000000;
> - cpu->isar.id_mmfr2 = 0x01260000;
> - cpu->isar.id_mmfr3 = 0x02102211;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00011142;
> - cpu->isar.id_isar5 = 0x00011121;
> - cpu->isar.id_aa64pfr0 = 0x00002222;
> - cpu->isar.id_aa64pfr1 = 0;
> - cpu->isar.id_aa64dfr0 = 0x10305106;
> - cpu->isar.id_aa64dfr1 = 0;
> - cpu->isar.id_aa64isar0 = 0x00011120;
> - cpu->isar.id_aa64isar1 = 0;
> - cpu->isar.id_aa64mmfr0 = 0x00101122;
> - cpu->isar.id_aa64mmfr1 = 0;
> - cpu->clidr = 0x0a200023;
> - cpu->dcz_blocksize = 4;
> -
> - /* From B2.4 AArch64 Virtual Memory control registers */
> - cpu->reset_sctlr = 0x00c50838;
> -
> - /* From B2.10 AArch64 performance monitor registers */
> - cpu->isar.reset_pmcr_el0 = 0x410a3000;
> -
> - /* From B2.29 Cache ID registers */
> - cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
> - cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
> - cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */
> -
> - /* From B3.5 VGIC Type register */
> - cpu->gic_num_lrs = 4;
> - cpu->gic_vpribits = 5;
> - cpu->gic_vprebits = 5;
> - cpu->gic_pribits = 5;
> -
> - /* From C6.4 Debug ID Register */
> - cpu->isar.dbgdidr = 0x3516d000;
> - /* From C6.5 Debug Device ID Register */
> - cpu->isar.dbgdevid = 0x00110f13;
> - /* From C6.6 Debug Device ID Register 1 */
> - cpu->isar.dbgdevid1 = 0x2;
> -
> - /* From Cortex-A35 SIMD and Floating-point Support r1p0 */
> - /* From 3.2 AArch32 register summary */
> - cpu->reset_fpsid = 0x41034043;
> -
> - /* From 2.2 AArch64 register summary */
> - cpu->isar.mvfr0 = 0x10110222;
> - cpu->isar.mvfr1 = 0x12111111;
> - cpu->isar.mvfr2 = 0x00000043;
> -
> - /* These values are the same with A53/A57/A72. */
> - define_cortex_a72_a57_a53_cp_reginfo(cpu);
> -}
> -
> void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
> {
> /*
> @@ -310,47 +232,6 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
> cpu->sve_vq.map = vq_map;
> }
>
> -static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> -{
> - ARMCPU *cpu = ARM_CPU(obj);
> - uint32_t value;
> -
> - /* All vector lengths are disabled when SVE is off. */
> - if (!cpu_isar_feature(aa64_sve, cpu)) {
> - value = 0;
> - } else {
> - value = cpu->sve_max_vq;
> - }
> - visit_type_uint32(v, name, &value, errp);
> -}
> -
> -static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> -{
> - ARMCPU *cpu = ARM_CPU(obj);
> - uint32_t max_vq;
> -
> - if (!visit_type_uint32(v, name, &max_vq, errp)) {
> - return;
> - }
> -
> - if (kvm_enabled() && !kvm_arm_sve_supported()) {
> - error_setg(errp, "cannot set sve-max-vq");
> - error_append_hint(errp, "SVE not supported by KVM on this host\n");
> - return;
> - }
> -
> - if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
> - error_setg(errp, "unsupported SVE vector length");
> - error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
> - ARM_MAX_VQ);
> - return;
> - }
> -
> - cpu->sve_max_vq = max_vq;
> -}
> -
> /*
> * Note that cpu_arm_{get,set}_vq cannot use the simpler
> * object_property_add_bool interface because they make use of the
> @@ -541,7 +422,7 @@ static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v,
> }
> #endif
>
> -static void aarch64_add_sve_properties(Object *obj)
> +void aarch64_add_sve_properties(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> uint32_t vq;
> @@ -564,7 +445,7 @@ static void aarch64_add_sve_properties(Object *obj)
> #endif
> }
>
> -static void aarch64_add_sme_properties(Object *obj)
> +void aarch64_add_sme_properties(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
> uint32_t vq;
> @@ -629,7 +510,7 @@ static Property arm_cpu_pauth_property =
> static Property arm_cpu_pauth_impdef_property =
> DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false);
>
> -static void aarch64_add_pauth_properties(Object *obj)
> +void aarch64_add_pauth_properties(Object *obj)
> {
> ARMCPU *cpu = ARM_CPU(obj);
>
> @@ -650,9 +531,6 @@ static void aarch64_add_pauth_properties(Object *obj)
> }
> }
>
> -static Property arm_cpu_lpa2_property =
> - DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);
> -
> void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
> {
> uint64_t t;
> @@ -787,316 +665,6 @@ static void aarch64_a53_initfn(Object *obj)
> define_cortex_a72_a57_a53_cp_reginfo(cpu);
> }
>
> -static void aarch64_a55_initfn(Object *obj)
> -{
> - ARMCPU *cpu = ARM_CPU(obj);
> -
> - cpu->dtb_compatible = "arm,cortex-a55";
> - set_feature(&cpu->env, ARM_FEATURE_V8);
> - set_feature(&cpu->env, ARM_FEATURE_NEON);
> - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> - set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> - set_feature(&cpu->env, ARM_FEATURE_EL2);
> - set_feature(&cpu->env, ARM_FEATURE_EL3);
> - set_feature(&cpu->env, ARM_FEATURE_PMU);
> -
> - /* Ordered by B2.4 AArch64 registers by functional group */
> - cpu->clidr = 0x82000023;
> - cpu->ctr = 0x84448004; /* L1Ip = VIPT */
> - cpu->dcz_blocksize = 4; /* 64 bytes */
> - cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
> - cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
> - cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
> - cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
> - cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> - cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
> - cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
> - cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
> - cpu->id_afr0 = 0x00000000;
> - cpu->isar.id_dfr0 = 0x04010088;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00011142;
> - cpu->isar.id_isar5 = 0x01011121;
> - cpu->isar.id_isar6 = 0x00000010;
> - cpu->isar.id_mmfr0 = 0x10201105;
> - cpu->isar.id_mmfr1 = 0x40000000;
> - cpu->isar.id_mmfr2 = 0x01260000;
> - cpu->isar.id_mmfr3 = 0x02122211;
> - cpu->isar.id_mmfr4 = 0x00021110;
> - cpu->isar.id_pfr0 = 0x10010131;
> - cpu->isar.id_pfr1 = 0x00011011;
> - cpu->isar.id_pfr2 = 0x00000011;
> - cpu->midr = 0x412FD050; /* r2p0 */
> - cpu->revidr = 0;
> -
> - /* From B2.23 CCSIDR_EL1 */
> - cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
> - cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
> - cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
> -
> - /* From B2.96 SCTLR_EL3 */
> - cpu->reset_sctlr = 0x30c50838;
> -
> - /* From B4.45 ICH_VTR_EL2 */
> - cpu->gic_num_lrs = 4;
> - cpu->gic_vpribits = 5;
> - cpu->gic_vprebits = 5;
> - cpu->gic_pribits = 5;
> -
> - cpu->isar.mvfr0 = 0x10110222;
> - cpu->isar.mvfr1 = 0x13211111;
> - cpu->isar.mvfr2 = 0x00000043;
> -
> - /* From D5.4 AArch64 PMU register summary */
> - cpu->isar.reset_pmcr_el0 = 0x410b3000;
> -}
> -
> -static void aarch64_a72_initfn(Object *obj)
> -{
> - ARMCPU *cpu = ARM_CPU(obj);
> -
> - cpu->dtb_compatible = "arm,cortex-a72";
> - set_feature(&cpu->env, ARM_FEATURE_V8);
> - set_feature(&cpu->env, ARM_FEATURE_NEON);
> - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> - set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> - set_feature(&cpu->env, ARM_FEATURE_EL2);
> - set_feature(&cpu->env, ARM_FEATURE_EL3);
> - set_feature(&cpu->env, ARM_FEATURE_PMU);
> - cpu->midr = 0x410fd083;
> - cpu->revidr = 0x00000000;
> - cpu->reset_fpsid = 0x41034080;
> - cpu->isar.mvfr0 = 0x10110222;
> - cpu->isar.mvfr1 = 0x12111111;
> - cpu->isar.mvfr2 = 0x00000043;
> - cpu->ctr = 0x8444c004;
> - cpu->reset_sctlr = 0x00c50838;
> - cpu->isar.id_pfr0 = 0x00000131;
> - cpu->isar.id_pfr1 = 0x00011011;
> - cpu->isar.id_dfr0 = 0x03010066;
> - cpu->id_afr0 = 0x00000000;
> - cpu->isar.id_mmfr0 = 0x10201105;
> - cpu->isar.id_mmfr1 = 0x40000000;
> - cpu->isar.id_mmfr2 = 0x01260000;
> - cpu->isar.id_mmfr3 = 0x02102211;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00011142;
> - cpu->isar.id_isar5 = 0x00011121;
> - cpu->isar.id_aa64pfr0 = 0x00002222;
> - cpu->isar.id_aa64dfr0 = 0x10305106;
> - cpu->isar.id_aa64isar0 = 0x00011120;
> - cpu->isar.id_aa64mmfr0 = 0x00001124;
> - cpu->isar.dbgdidr = 0x3516d000;
> - cpu->isar.dbgdevid = 0x01110f13;
> - cpu->isar.dbgdevid1 = 0x2;
> - cpu->isar.reset_pmcr_el0 = 0x41023000;
> - cpu->clidr = 0x0a200023;
> - cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
> - cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
> - cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
> - cpu->dcz_blocksize = 4; /* 64 bytes */
> - cpu->gic_num_lrs = 4;
> - cpu->gic_vpribits = 5;
> - cpu->gic_vprebits = 5;
> - cpu->gic_pribits = 5;
> - define_cortex_a72_a57_a53_cp_reginfo(cpu);
> -}
> -
> -static void aarch64_a76_initfn(Object *obj)
> -{
> - ARMCPU *cpu = ARM_CPU(obj);
> -
> - cpu->dtb_compatible = "arm,cortex-a76";
> - set_feature(&cpu->env, ARM_FEATURE_V8);
> - set_feature(&cpu->env, ARM_FEATURE_NEON);
> - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> - set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> - set_feature(&cpu->env, ARM_FEATURE_EL2);
> - set_feature(&cpu->env, ARM_FEATURE_EL3);
> - set_feature(&cpu->env, ARM_FEATURE_PMU);
> -
> - /* Ordered by B2.4 AArch64 registers by functional group */
> - cpu->clidr = 0x82000023;
> - cpu->ctr = 0x8444C004;
> - cpu->dcz_blocksize = 4;
> - cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
> - cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
> - cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
> - cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
> - cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> - cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
> - cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
> - cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
> - cpu->id_afr0 = 0x00000000;
> - cpu->isar.id_dfr0 = 0x04010088;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00010142;
> - cpu->isar.id_isar5 = 0x01011121;
> - cpu->isar.id_isar6 = 0x00000010;
> - cpu->isar.id_mmfr0 = 0x10201105;
> - cpu->isar.id_mmfr1 = 0x40000000;
> - cpu->isar.id_mmfr2 = 0x01260000;
> - cpu->isar.id_mmfr3 = 0x02122211;
> - cpu->isar.id_mmfr4 = 0x00021110;
> - cpu->isar.id_pfr0 = 0x10010131;
> - cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
> - cpu->isar.id_pfr2 = 0x00000011;
> - cpu->midr = 0x414fd0b1; /* r4p1 */
> - cpu->revidr = 0;
> -
> - /* From B2.18 CCSIDR_EL1 */
> - cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
> - cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
> - cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
> -
> - /* From B2.93 SCTLR_EL3 */
> - cpu->reset_sctlr = 0x30c50838;
> -
> - /* From B4.23 ICH_VTR_EL2 */
> - cpu->gic_num_lrs = 4;
> - cpu->gic_vpribits = 5;
> - cpu->gic_vprebits = 5;
> - cpu->gic_pribits = 5;
> -
> - /* From B5.1 AdvSIMD AArch64 register summary */
> - cpu->isar.mvfr0 = 0x10110222;
> - cpu->isar.mvfr1 = 0x13211111;
> - cpu->isar.mvfr2 = 0x00000043;
> -
> - /* From D5.1 AArch64 PMU register summary */
> - cpu->isar.reset_pmcr_el0 = 0x410b3000;
> -}
> -
> -static void aarch64_a64fx_initfn(Object *obj)
> -{
> - ARMCPU *cpu = ARM_CPU(obj);
> -
> - cpu->dtb_compatible = "arm,a64fx";
> - set_feature(&cpu->env, ARM_FEATURE_V8);
> - set_feature(&cpu->env, ARM_FEATURE_NEON);
> - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> - set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> - set_feature(&cpu->env, ARM_FEATURE_EL2);
> - set_feature(&cpu->env, ARM_FEATURE_EL3);
> - set_feature(&cpu->env, ARM_FEATURE_PMU);
> - cpu->midr = 0x461f0010;
> - cpu->revidr = 0x00000000;
> - cpu->ctr = 0x86668006;
> - cpu->reset_sctlr = 0x30000180;
> - cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
> - cpu->isar.id_aa64pfr1 = 0x0000000000000000;
> - cpu->isar.id_aa64dfr0 = 0x0000000010305408;
> - cpu->isar.id_aa64dfr1 = 0x0000000000000000;
> - cpu->id_aa64afr0 = 0x0000000000000000;
> - cpu->id_aa64afr1 = 0x0000000000000000;
> - cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
> - cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
> - cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
> - cpu->isar.id_aa64isar0 = 0x0000000010211120;
> - cpu->isar.id_aa64isar1 = 0x0000000000010001;
> - cpu->isar.id_aa64zfr0 = 0x0000000000000000;
> - cpu->clidr = 0x0000000080000023;
> - cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
> - cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
> - cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
> - cpu->dcz_blocksize = 6; /* 256 bytes */
> - cpu->gic_num_lrs = 4;
> - cpu->gic_vpribits = 5;
> - cpu->gic_vprebits = 5;
> - cpu->gic_pribits = 5;
> -
> - /* The A64FX supports only 128, 256 and 512 bit vector lengths */
> - aarch64_add_sve_properties(obj);
> - cpu->sve_vq.supported = (1 << 0) /* 128bit */
> - | (1 << 1) /* 256bit */
> - | (1 << 3); /* 512bit */
> -
> - cpu->isar.reset_pmcr_el0 = 0x46014040;
> -
> - /* TODO: Add A64FX specific HPC extension registers */
> -}
> -
> -static void aarch64_neoverse_n1_initfn(Object *obj)
> -{
> - ARMCPU *cpu = ARM_CPU(obj);
> -
> - cpu->dtb_compatible = "arm,neoverse-n1";
> - set_feature(&cpu->env, ARM_FEATURE_V8);
> - set_feature(&cpu->env, ARM_FEATURE_NEON);
> - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> - set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> - set_feature(&cpu->env, ARM_FEATURE_EL2);
> - set_feature(&cpu->env, ARM_FEATURE_EL3);
> - set_feature(&cpu->env, ARM_FEATURE_PMU);
> -
> - /* Ordered by B2.4 AArch64 registers by functional group */
> - cpu->clidr = 0x82000023;
> - cpu->ctr = 0x8444c004;
> - cpu->dcz_blocksize = 4;
> - cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
> - cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
> - cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
> - cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
> - cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> - cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
> - cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
> - cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
> - cpu->id_afr0 = 0x00000000;
> - cpu->isar.id_dfr0 = 0x04010088;
> - cpu->isar.id_isar0 = 0x02101110;
> - cpu->isar.id_isar1 = 0x13112111;
> - cpu->isar.id_isar2 = 0x21232042;
> - cpu->isar.id_isar3 = 0x01112131;
> - cpu->isar.id_isar4 = 0x00010142;
> - cpu->isar.id_isar5 = 0x01011121;
> - cpu->isar.id_isar6 = 0x00000010;
> - cpu->isar.id_mmfr0 = 0x10201105;
> - cpu->isar.id_mmfr1 = 0x40000000;
> - cpu->isar.id_mmfr2 = 0x01260000;
> - cpu->isar.id_mmfr3 = 0x02122211;
> - cpu->isar.id_mmfr4 = 0x00021110;
> - cpu->isar.id_pfr0 = 0x10010131;
> - cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
> - cpu->isar.id_pfr2 = 0x00000011;
> - cpu->midr = 0x414fd0c1; /* r4p1 */
> - cpu->revidr = 0;
> -
> - /* From B2.23 CCSIDR_EL1 */
> - cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
> - cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
> - cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
> -
> - /* From B2.98 SCTLR_EL3 */
> - cpu->reset_sctlr = 0x30c50838;
> -
> - /* From B4.23 ICH_VTR_EL2 */
> - cpu->gic_num_lrs = 4;
> - cpu->gic_vpribits = 5;
> - cpu->gic_vprebits = 5;
> - cpu->gic_pribits = 5;
> -
> - /* From B5.1 AdvSIMD AArch64 register summary */
> - cpu->isar.mvfr0 = 0x10110222;
> - cpu->isar.mvfr1 = 0x13211111;
> - cpu->isar.mvfr2 = 0x00000043;
> -
> - /* From D5.1 AArch64 PMU register summary */
> - cpu->isar.reset_pmcr_el0 = 0x410c3000;
> -}
> -
> static void aarch64_host_initfn(Object *obj)
> {
> #if defined(CONFIG_KVM)
> @@ -1115,203 +683,26 @@ static void aarch64_host_initfn(Object *obj)
> #endif
> }
>
> -/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
> - * otherwise, a CPU with as many features enabled as our emulation supports.
> - * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
> - * this only needs to handle 64 bits.
> - */
> static void aarch64_max_initfn(Object *obj)
> {
> - ARMCPU *cpu = ARM_CPU(obj);
> - uint64_t t;
> - uint32_t u;
> -
> if (kvm_enabled() || hvf_enabled()) {
> /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
> aarch64_host_initfn(obj);
> - return;
> }
>
> - /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
> -
> - aarch64_a57_initfn(obj);
> -
> - /*
> - * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
> - * one and try to apply errata workarounds or use impdef features we
> - * don't provide.
> - * An IMPLEMENTER field of 0 means "reserved for software use";
> - * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
> - * to see which features are present";
> - * the VARIANT, PARTNUM and REVISION fields are all implementation
> - * defined and we choose to define PARTNUM just in case guest
> - * code needs to distinguish this QEMU CPU from other software
> - * implementations, though this shouldn't be needed.
> - */
> - t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
> - t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
> - t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
> - t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
> - t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
> - cpu->midr = t;
> -
> - /*
> - * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS}
> - * are zero.
> - */
> - u = cpu->clidr;
> - u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0);
> - u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0);
> - cpu->clidr = u;
> -
> - t = cpu->isar.id_aa64isar0;
> - t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
> - t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
> - t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
> - t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
> - t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
> - t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
> - t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
> - t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
> - t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
> - t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
> - t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
> - t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
> - t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
> - t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
> - cpu->isar.id_aa64isar0 = t;
> -
> - t = cpu->isar.id_aa64isar1;
> - t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
> - t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
> - t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
> - t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
> - t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
> - t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
> - t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
> - t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
> - t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
> - t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
> - cpu->isar.id_aa64isar1 = t;
> -
> - t = cpu->isar.id_aa64pfr0;
> - t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
> - t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
> - t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */
> - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
> - t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
> - t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
> - t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
> - t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
> - cpu->isar.id_aa64pfr0 = t;
> -
> - t = cpu->isar.id_aa64pfr1;
> - t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
> - t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
> - /*
> - * Begin with full support for MTE. This will be downgraded to MTE=0
> - * during realize if the board provides no tag memory, much like
> - * we do for EL2 with the virtualization=on property.
> - */
> - t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
> - t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */
> - t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
> - t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
> - cpu->isar.id_aa64pfr1 = t;
> -
> - t = cpu->isar.id_aa64mmfr0;
> - t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
> - t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
> - t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
> - t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
> - t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
> - cpu->isar.id_aa64mmfr0 = t;
> -
> - t = cpu->isar.id_aa64mmfr1;
> - t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
> - t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
> - t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
> - t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
> - t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
> - t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */
> - t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
> - t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */
> - t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
> - cpu->isar.id_aa64mmfr1 = t;
> -
> - t = cpu->isar.id_aa64mmfr2;
> - t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
> - t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
> - t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
> - t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
> - t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
> - t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */
> - t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
> - t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
> - t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
> - t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
> - t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
> - cpu->isar.id_aa64mmfr2 = t;
> -
> - t = cpu->isar.id_aa64zfr0;
> - t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
> - t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
> - t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
> - t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */
> - t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
> - t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
> - t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
> - t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
> - t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
> - cpu->isar.id_aa64zfr0 = t;
> -
> - t = cpu->isar.id_aa64dfr0;
> - t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
> - t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
> - cpu->isar.id_aa64dfr0 = t;
> -
> - t = cpu->isar.id_aa64smfr0;
> - t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
> - t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */
> - t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */
> - t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */
> - t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */
> - t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
> - t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */
> - cpu->isar.id_aa64smfr0 = t;
> -
> - /* Replicate the same data to the 32-bit id registers. */
> - aa32_max_features(cpu);
> -
> -#ifdef CONFIG_USER_ONLY
> - /*
> - * For usermode -cpu max we can use a larger and more efficient DCZ
> - * blocksize since we don't have to follow what the hardware does.
> - */
> - cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
> - cpu->dcz_blocksize = 7; /* 512 bytes */
> -#endif
> -
> - cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
> - cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
> + if (tcg_enabled() || qtest_enabled()) {
> + aarch64_a57_initfn(obj);
> + }
>
> - aarch64_add_pauth_properties(obj);
> - aarch64_add_sve_properties(obj);
> - aarch64_add_sme_properties(obj);
> - object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
> - cpu_max_set_sve_max_vq, NULL, NULL);
> - qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
> + if (tcg_enabled()) {
> + /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
> + aarch64_max_tcg_initfn(obj);
> + }
> }
>
> static const ARMCPUInfo aarch64_cpus[] = {
> - { .name = "cortex-a35", .initfn = aarch64_a35_initfn },
> { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
> { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
> - { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
> - { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
> - { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
> - { .name = "a64fx", .initfn = aarch64_a64fx_initfn },
> - { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
> { .name = "max", .initfn = aarch64_max_initfn },
> #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
> { .name = "host", .initfn = aarch64_host_initfn },
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index a8fb8aa363..72e3d2fef2 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -1364,6 +1364,10 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
> void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
> void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
> void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
> +void aarch64_max_tcg_initfn(Object *obj);
> +void aarch64_add_pauth_properties(Object *obj);
> +void aarch64_add_sve_properties(Object *obj);
> +void aarch64_add_sme_properties(Object *obj);
> #endif
>
> bool el_is_in_host(CPUARMState *env, int el);
> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
> new file mode 100644
> index 0000000000..4d5bdddae4
> --- /dev/null
> +++ b/target/arm/tcg/cpu64.c
> @@ -0,0 +1,654 @@
> +/*
> + * QEMU AArch64 TCG CPUs
> + *
> + * Copyright (c) 2013 Linaro Ltd
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see
> + * <http://www.gnu.org/licenses/gpl-2.0.html>
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "cpu.h"
> +#include "qemu/module.h"
> +#include "qapi/visitor.h"
> +#include "hw/qdev-properties.h"
> +#include "internals.h"
> +#include "cpregs.h"
> +
> +static void aarch64_a35_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cpu->dtb_compatible = "arm,cortex-a35";
> + set_feature(&cpu->env, ARM_FEATURE_V8);
> + set_feature(&cpu->env, ARM_FEATURE_NEON);
> + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> + set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> + set_feature(&cpu->env, ARM_FEATURE_EL2);
> + set_feature(&cpu->env, ARM_FEATURE_EL3);
> + set_feature(&cpu->env, ARM_FEATURE_PMU);
> +
> + /* From B2.2 AArch64 identification registers. */
> + cpu->midr = 0x411fd040;
> + cpu->revidr = 0;
> + cpu->ctr = 0x84448004;
> + cpu->isar.id_pfr0 = 0x00000131;
> + cpu->isar.id_pfr1 = 0x00011011;
> + cpu->isar.id_dfr0 = 0x03010066;
> + cpu->id_afr0 = 0;
> + cpu->isar.id_mmfr0 = 0x10201105;
> + cpu->isar.id_mmfr1 = 0x40000000;
> + cpu->isar.id_mmfr2 = 0x01260000;
> + cpu->isar.id_mmfr3 = 0x02102211;
> + cpu->isar.id_isar0 = 0x02101110;
> + cpu->isar.id_isar1 = 0x13112111;
> + cpu->isar.id_isar2 = 0x21232042;
> + cpu->isar.id_isar3 = 0x01112131;
> + cpu->isar.id_isar4 = 0x00011142;
> + cpu->isar.id_isar5 = 0x00011121;
> + cpu->isar.id_aa64pfr0 = 0x00002222;
> + cpu->isar.id_aa64pfr1 = 0;
> + cpu->isar.id_aa64dfr0 = 0x10305106;
> + cpu->isar.id_aa64dfr1 = 0;
> + cpu->isar.id_aa64isar0 = 0x00011120;
> + cpu->isar.id_aa64isar1 = 0;
> + cpu->isar.id_aa64mmfr0 = 0x00101122;
> + cpu->isar.id_aa64mmfr1 = 0;
> + cpu->clidr = 0x0a200023;
> + cpu->dcz_blocksize = 4;
> +
> + /* From B2.4 AArch64 Virtual Memory control registers */
> + cpu->reset_sctlr = 0x00c50838;
> +
> + /* From B2.10 AArch64 performance monitor registers */
> + cpu->isar.reset_pmcr_el0 = 0x410a3000;
> +
> + /* From B2.29 Cache ID registers */
> + cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
> + cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
> + cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */
> +
> + /* From B3.5 VGIC Type register */
> + cpu->gic_num_lrs = 4;
> + cpu->gic_vpribits = 5;
> + cpu->gic_vprebits = 5;
> + cpu->gic_pribits = 5;
> +
> + /* From C6.4 Debug ID Register */
> + cpu->isar.dbgdidr = 0x3516d000;
> + /* From C6.5 Debug Device ID Register */
> + cpu->isar.dbgdevid = 0x00110f13;
> + /* From C6.6 Debug Device ID Register 1 */
> + cpu->isar.dbgdevid1 = 0x2;
> +
> + /* From Cortex-A35 SIMD and Floating-point Support r1p0 */
> + /* From 3.2 AArch32 register summary */
> + cpu->reset_fpsid = 0x41034043;
> +
> + /* From 2.2 AArch64 register summary */
> + cpu->isar.mvfr0 = 0x10110222;
> + cpu->isar.mvfr1 = 0x12111111;
> + cpu->isar.mvfr2 = 0x00000043;
> +
> + /* These values are the same with A53/A57/A72. */
> + define_cortex_a72_a57_a53_cp_reginfo(cpu);
> +}
> +
> +static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> + uint32_t value;
> +
> + /* All vector lengths are disabled when SVE is off. */
> + if (!cpu_isar_feature(aa64_sve, cpu)) {
> + value = 0;
> + } else {
> + value = cpu->sve_max_vq;
> + }
> + visit_type_uint32(v, name, &value, errp);
> +}
> +
> +static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
> + void *opaque, Error **errp)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> + uint32_t max_vq;
> +
> + if (!visit_type_uint32(v, name, &max_vq, errp)) {
> + return;
> + }
> +
> + if (max_vq == 0 || max_vq > ARM_MAX_VQ) {
> + error_setg(errp, "unsupported SVE vector length");
> + error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n",
> + ARM_MAX_VQ);
> + return;
> + }
> +
> + cpu->sve_max_vq = max_vq;
> +}
> +
> +static Property arm_cpu_lpa2_property =
> + DEFINE_PROP_BOOL("lpa2", ARMCPU, prop_lpa2, true);
> +
> +static void aarch64_a55_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cpu->dtb_compatible = "arm,cortex-a55";
> + set_feature(&cpu->env, ARM_FEATURE_V8);
> + set_feature(&cpu->env, ARM_FEATURE_NEON);
> + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> + set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> + set_feature(&cpu->env, ARM_FEATURE_EL2);
> + set_feature(&cpu->env, ARM_FEATURE_EL3);
> + set_feature(&cpu->env, ARM_FEATURE_PMU);
> +
> + /* Ordered by B2.4 AArch64 registers by functional group */
> + cpu->clidr = 0x82000023;
> + cpu->ctr = 0x84448004; /* L1Ip = VIPT */
> + cpu->dcz_blocksize = 4; /* 64 bytes */
> + cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
> + cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
> + cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
> + cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
> + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
> + cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
> + cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
> + cpu->id_afr0 = 0x00000000;
> + cpu->isar.id_dfr0 = 0x04010088;
> + cpu->isar.id_isar0 = 0x02101110;
> + cpu->isar.id_isar1 = 0x13112111;
> + cpu->isar.id_isar2 = 0x21232042;
> + cpu->isar.id_isar3 = 0x01112131;
> + cpu->isar.id_isar4 = 0x00011142;
> + cpu->isar.id_isar5 = 0x01011121;
> + cpu->isar.id_isar6 = 0x00000010;
> + cpu->isar.id_mmfr0 = 0x10201105;
> + cpu->isar.id_mmfr1 = 0x40000000;
> + cpu->isar.id_mmfr2 = 0x01260000;
> + cpu->isar.id_mmfr3 = 0x02122211;
> + cpu->isar.id_mmfr4 = 0x00021110;
> + cpu->isar.id_pfr0 = 0x10010131;
> + cpu->isar.id_pfr1 = 0x00011011;
> + cpu->isar.id_pfr2 = 0x00000011;
> + cpu->midr = 0x412FD050; /* r2p0 */
> + cpu->revidr = 0;
> +
> + /* From B2.23 CCSIDR_EL1 */
> + cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
> + cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */
> + cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */
> +
> + /* From B2.96 SCTLR_EL3 */
> + cpu->reset_sctlr = 0x30c50838;
> +
> + /* From B4.45 ICH_VTR_EL2 */
> + cpu->gic_num_lrs = 4;
> + cpu->gic_vpribits = 5;
> + cpu->gic_vprebits = 5;
> + cpu->gic_pribits = 5;
> +
> + cpu->isar.mvfr0 = 0x10110222;
> + cpu->isar.mvfr1 = 0x13211111;
> + cpu->isar.mvfr2 = 0x00000043;
> +
> + /* From D5.4 AArch64 PMU register summary */
> + cpu->isar.reset_pmcr_el0 = 0x410b3000;
> +}
> +
> +static void aarch64_a72_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cpu->dtb_compatible = "arm,cortex-a72";
> + set_feature(&cpu->env, ARM_FEATURE_V8);
> + set_feature(&cpu->env, ARM_FEATURE_NEON);
> + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> + set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> + set_feature(&cpu->env, ARM_FEATURE_EL2);
> + set_feature(&cpu->env, ARM_FEATURE_EL3);
> + set_feature(&cpu->env, ARM_FEATURE_PMU);
> + cpu->midr = 0x410fd083;
> + cpu->revidr = 0x00000000;
> + cpu->reset_fpsid = 0x41034080;
> + cpu->isar.mvfr0 = 0x10110222;
> + cpu->isar.mvfr1 = 0x12111111;
> + cpu->isar.mvfr2 = 0x00000043;
> + cpu->ctr = 0x8444c004;
> + cpu->reset_sctlr = 0x00c50838;
> + cpu->isar.id_pfr0 = 0x00000131;
> + cpu->isar.id_pfr1 = 0x00011011;
> + cpu->isar.id_dfr0 = 0x03010066;
> + cpu->id_afr0 = 0x00000000;
> + cpu->isar.id_mmfr0 = 0x10201105;
> + cpu->isar.id_mmfr1 = 0x40000000;
> + cpu->isar.id_mmfr2 = 0x01260000;
> + cpu->isar.id_mmfr3 = 0x02102211;
> + cpu->isar.id_isar0 = 0x02101110;
> + cpu->isar.id_isar1 = 0x13112111;
> + cpu->isar.id_isar2 = 0x21232042;
> + cpu->isar.id_isar3 = 0x01112131;
> + cpu->isar.id_isar4 = 0x00011142;
> + cpu->isar.id_isar5 = 0x00011121;
> + cpu->isar.id_aa64pfr0 = 0x00002222;
> + cpu->isar.id_aa64dfr0 = 0x10305106;
> + cpu->isar.id_aa64isar0 = 0x00011120;
> + cpu->isar.id_aa64mmfr0 = 0x00001124;
> + cpu->isar.dbgdidr = 0x3516d000;
> + cpu->isar.dbgdevid = 0x01110f13;
> + cpu->isar.dbgdevid1 = 0x2;
> + cpu->isar.reset_pmcr_el0 = 0x41023000;
> + cpu->clidr = 0x0a200023;
> + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
> + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
> + cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
> + cpu->dcz_blocksize = 4; /* 64 bytes */
> + cpu->gic_num_lrs = 4;
> + cpu->gic_vpribits = 5;
> + cpu->gic_vprebits = 5;
> + cpu->gic_pribits = 5;
> + define_cortex_a72_a57_a53_cp_reginfo(cpu);
> +}
> +
> +static void aarch64_a76_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cpu->dtb_compatible = "arm,cortex-a76";
> + set_feature(&cpu->env, ARM_FEATURE_V8);
> + set_feature(&cpu->env, ARM_FEATURE_NEON);
> + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> + set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> + set_feature(&cpu->env, ARM_FEATURE_EL2);
> + set_feature(&cpu->env, ARM_FEATURE_EL3);
> + set_feature(&cpu->env, ARM_FEATURE_PMU);
> +
> + /* Ordered by B2.4 AArch64 registers by functional group */
> + cpu->clidr = 0x82000023;
> + cpu->ctr = 0x8444C004;
> + cpu->dcz_blocksize = 4;
> + cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
> + cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
> + cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
> + cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
> + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
> + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
> + cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
> + cpu->id_afr0 = 0x00000000;
> + cpu->isar.id_dfr0 = 0x04010088;
> + cpu->isar.id_isar0 = 0x02101110;
> + cpu->isar.id_isar1 = 0x13112111;
> + cpu->isar.id_isar2 = 0x21232042;
> + cpu->isar.id_isar3 = 0x01112131;
> + cpu->isar.id_isar4 = 0x00010142;
> + cpu->isar.id_isar5 = 0x01011121;
> + cpu->isar.id_isar6 = 0x00000010;
> + cpu->isar.id_mmfr0 = 0x10201105;
> + cpu->isar.id_mmfr1 = 0x40000000;
> + cpu->isar.id_mmfr2 = 0x01260000;
> + cpu->isar.id_mmfr3 = 0x02122211;
> + cpu->isar.id_mmfr4 = 0x00021110;
> + cpu->isar.id_pfr0 = 0x10010131;
> + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
> + cpu->isar.id_pfr2 = 0x00000011;
> + cpu->midr = 0x414fd0b1; /* r4p1 */
> + cpu->revidr = 0;
> +
> + /* From B2.18 CCSIDR_EL1 */
> + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
> + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
> + cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
> +
> + /* From B2.93 SCTLR_EL3 */
> + cpu->reset_sctlr = 0x30c50838;
> +
> + /* From B4.23 ICH_VTR_EL2 */
> + cpu->gic_num_lrs = 4;
> + cpu->gic_vpribits = 5;
> + cpu->gic_vprebits = 5;
> + cpu->gic_pribits = 5;
> +
> + /* From B5.1 AdvSIMD AArch64 register summary */
> + cpu->isar.mvfr0 = 0x10110222;
> + cpu->isar.mvfr1 = 0x13211111;
> + cpu->isar.mvfr2 = 0x00000043;
> +
> + /* From D5.1 AArch64 PMU register summary */
> + cpu->isar.reset_pmcr_el0 = 0x410b3000;
> +}
> +
> +static void aarch64_a64fx_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cpu->dtb_compatible = "arm,a64fx";
> + set_feature(&cpu->env, ARM_FEATURE_V8);
> + set_feature(&cpu->env, ARM_FEATURE_NEON);
> + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> + set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> + set_feature(&cpu->env, ARM_FEATURE_EL2);
> + set_feature(&cpu->env, ARM_FEATURE_EL3);
> + set_feature(&cpu->env, ARM_FEATURE_PMU);
> + cpu->midr = 0x461f0010;
> + cpu->revidr = 0x00000000;
> + cpu->ctr = 0x86668006;
> + cpu->reset_sctlr = 0x30000180;
> + cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
> + cpu->isar.id_aa64pfr1 = 0x0000000000000000;
> + cpu->isar.id_aa64dfr0 = 0x0000000010305408;
> + cpu->isar.id_aa64dfr1 = 0x0000000000000000;
> + cpu->id_aa64afr0 = 0x0000000000000000;
> + cpu->id_aa64afr1 = 0x0000000000000000;
> + cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
> + cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
> + cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
> + cpu->isar.id_aa64isar0 = 0x0000000010211120;
> + cpu->isar.id_aa64isar1 = 0x0000000000010001;
> + cpu->isar.id_aa64zfr0 = 0x0000000000000000;
> + cpu->clidr = 0x0000000080000023;
> + cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
> + cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
> + cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
> + cpu->dcz_blocksize = 6; /* 256 bytes */
> + cpu->gic_num_lrs = 4;
> + cpu->gic_vpribits = 5;
> + cpu->gic_vprebits = 5;
> + cpu->gic_pribits = 5;
> +
> + /* The A64FX supports only 128, 256 and 512 bit vector lengths */
> + aarch64_add_sve_properties(obj);
> + cpu->sve_vq.supported = (1 << 0) /* 128bit */
> + | (1 << 1) /* 256bit */
> + | (1 << 3); /* 512bit */
> +
> + cpu->isar.reset_pmcr_el0 = 0x46014040;
> +
> + /* TODO: Add A64FX specific HPC extension registers */
> +}
> +
> +static void aarch64_neoverse_n1_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> +
> + cpu->dtb_compatible = "arm,neoverse-n1";
> + set_feature(&cpu->env, ARM_FEATURE_V8);
> + set_feature(&cpu->env, ARM_FEATURE_NEON);
> + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
> + set_feature(&cpu->env, ARM_FEATURE_AARCH64);
> + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
> + set_feature(&cpu->env, ARM_FEATURE_EL2);
> + set_feature(&cpu->env, ARM_FEATURE_EL3);
> + set_feature(&cpu->env, ARM_FEATURE_PMU);
> +
> + /* Ordered by B2.4 AArch64 registers by functional group */
> + cpu->clidr = 0x82000023;
> + cpu->ctr = 0x8444c004;
> + cpu->dcz_blocksize = 4;
> + cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
> + cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
> + cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
> + cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
> + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
> + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
> + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
> + cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
> + cpu->id_afr0 = 0x00000000;
> + cpu->isar.id_dfr0 = 0x04010088;
> + cpu->isar.id_isar0 = 0x02101110;
> + cpu->isar.id_isar1 = 0x13112111;
> + cpu->isar.id_isar2 = 0x21232042;
> + cpu->isar.id_isar3 = 0x01112131;
> + cpu->isar.id_isar4 = 0x00010142;
> + cpu->isar.id_isar5 = 0x01011121;
> + cpu->isar.id_isar6 = 0x00000010;
> + cpu->isar.id_mmfr0 = 0x10201105;
> + cpu->isar.id_mmfr1 = 0x40000000;
> + cpu->isar.id_mmfr2 = 0x01260000;
> + cpu->isar.id_mmfr3 = 0x02122211;
> + cpu->isar.id_mmfr4 = 0x00021110;
> + cpu->isar.id_pfr0 = 0x10010131;
> + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
> + cpu->isar.id_pfr2 = 0x00000011;
> + cpu->midr = 0x414fd0c1; /* r4p1 */
> + cpu->revidr = 0;
> +
> + /* From B2.23 CCSIDR_EL1 */
> + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
> + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
> + cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
> +
> + /* From B2.98 SCTLR_EL3 */
> + cpu->reset_sctlr = 0x30c50838;
> +
> + /* From B4.23 ICH_VTR_EL2 */
> + cpu->gic_num_lrs = 4;
> + cpu->gic_vpribits = 5;
> + cpu->gic_vprebits = 5;
> + cpu->gic_pribits = 5;
> +
> + /* From B5.1 AdvSIMD AArch64 register summary */
> + cpu->isar.mvfr0 = 0x10110222;
> + cpu->isar.mvfr1 = 0x13211111;
> + cpu->isar.mvfr2 = 0x00000043;
> +
> + /* From D5.1 AArch64 PMU register summary */
> + cpu->isar.reset_pmcr_el0 = 0x410c3000;
> +}
> +
> +/*
> + * -cpu max: a CPU with as many features enabled as our emulation supports.
> + * The version of '-cpu max' for qemu-system-arm is defined in cpu_tcg.c;
> + * this only needs to handle 64 bits.
> + */
> +void aarch64_max_tcg_initfn(Object *obj)
> +{
> + ARMCPU *cpu = ARM_CPU(obj);
> + uint64_t t;
> + uint32_t u;
> +
> + /*
> + * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
> + * one and try to apply errata workarounds or use impdef features we
> + * don't provide.
> + * An IMPLEMENTER field of 0 means "reserved for software use";
> + * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
> + * to see which features are present";
> + * the VARIANT, PARTNUM and REVISION fields are all implementation
> + * defined and we choose to define PARTNUM just in case guest
> + * code needs to distinguish this QEMU CPU from other software
> + * implementations, though this shouldn't be needed.
> + */
> + t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
> + t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
> + t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
> + t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
> + t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
> + cpu->midr = t;
> +
> + /*
> + * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS}
> + * are zero.
> + */
> + u = cpu->clidr;
> + u = FIELD_DP32(u, CLIDR_EL1, LOUIS, 0);
> + u = FIELD_DP32(u, CLIDR_EL1, LOUU, 0);
> + cpu->clidr = u;
> +
> + t = cpu->isar.id_aa64isar0;
> + t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
> + t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
> + t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
> + t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
> + t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */
> + t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */
> + t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */
> + t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */
> + t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */
> + t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */
> + t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */
> + t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
> + t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
> + t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
> + cpu->isar.id_aa64isar0 = t;
> +
> + t = cpu->isar.id_aa64isar1;
> + t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
> + t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */
> + t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */
> + t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */
> + t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */
> + t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
> + t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
> + t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
> + t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
> + t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
> + cpu->isar.id_aa64isar1 = t;
> +
> + t = cpu->isar.id_aa64pfr0;
> + t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
> + t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
> + t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */
> + t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
> + t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
> + t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
> + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */
> + t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
> + cpu->isar.id_aa64pfr0 = t;
> +
> + t = cpu->isar.id_aa64pfr1;
> + t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
> + t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
> + /*
> + * Begin with full support for MTE. This will be downgraded to MTE=0
> + * during realize if the board provides no tag memory, much like
> + * we do for EL2 with the virtualization=on property.
> + */
> + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */
> + t = FIELD_DP64(t, ID_AA64PFR1, RAS_FRAC, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */
> + t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
> + t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */
> + cpu->isar.id_aa64pfr1 = t;
> +
> + t = cpu->isar.id_aa64mmfr0;
> + t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
> + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
> + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
> + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN64_2, 2); /* 64k stage2 supported */
> + t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
> + cpu->isar.id_aa64mmfr0 = t;
> +
> + t = cpu->isar.id_aa64mmfr1;
> + t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
> + t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
> + t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
> + t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */
> + t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */
> + t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */
> + t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */
> + t = FIELD_DP64(t, ID_AA64MMFR1, ETS, 1); /* FEAT_ETS */
> + t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
> + cpu->isar.id_aa64mmfr1 = t;
> +
> + t = cpu->isar.id_aa64mmfr2;
> + t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
> + t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
> + t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
> + t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
> + t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
> + t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */
> + t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
> + t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
> + t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
> + t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
> + t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
> + cpu->isar.id_aa64mmfr2 = t;
> +
> + t = cpu->isar.id_aa64zfr0;
> + t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
> + t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
> + t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
> + t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */
> + t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */
> + t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */
> + t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
> + t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
> + t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
> + cpu->isar.id_aa64zfr0 = t;
> +
> + t = cpu->isar.id_aa64dfr0;
> + t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
> + t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
> + cpu->isar.id_aa64dfr0 = t;
> +
> + t = cpu->isar.id_aa64smfr0;
> + t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
> + t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */
> + t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */
> + t = FIELD_DP64(t, ID_AA64SMFR0, I8I32, 0xf); /* FEAT_SME */
> + t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */
> + t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
> + t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */
> + cpu->isar.id_aa64smfr0 = t;
> +
> + /* Replicate the same data to the 32-bit id registers. */
> + aa32_max_features(cpu);
> +
> +#ifdef CONFIG_USER_ONLY
> + /*
> + * For usermode -cpu max we can use a larger and more efficient DCZ
> + * blocksize since we don't have to follow what the hardware does.
> + */
> + cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
> + cpu->dcz_blocksize = 7; /* 512 bytes */
> +#endif
> +
> + cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ);
> + cpu->sme_vq.supported = SVE_VQ_POW2_MAP;
> +
> + aarch64_add_pauth_properties(obj);
> + aarch64_add_sve_properties(obj);
> + aarch64_add_sme_properties(obj);
> + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
> + cpu_max_set_sve_max_vq, NULL, NULL);
> + qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
> +}
> +
> +static const ARMCPUInfo aarch64_cpus[] = {
> + { .name = "cortex-a35", .initfn = aarch64_a35_initfn },
> + { .name = "cortex-a55", .initfn = aarch64_a55_initfn },
> + { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
> + { .name = "cortex-a76", .initfn = aarch64_a76_initfn },
> + { .name = "a64fx", .initfn = aarch64_a64fx_initfn },
> + { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
> +};
> +
> +static void aarch64_cpu_register_types(void)
> +{
> + size_t i;
> +
> + for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
> + aarch64_cpu_register(&aarch64_cpus[i]);
> + }
> +}
> +
> +type_init(aarch64_cpu_register_types)
> diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
> index 25bc98999e..8debe81fd5 100644
> --- a/target/arm/tcg/meson.build
> +++ b/target/arm/tcg/meson.build
> @@ -36,6 +36,7 @@ arm_ss.add(files(
> ))
>
> arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
> + 'cpu64.c',
> 'translate-a64.c',
> 'translate-sve.c',
> 'translate-sme.c',
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 04/15] tests/qtest: arm-cpu-features: Match tests to required accelerators
2023-01-19 13:54 ` [RFC PATCH v4 04/15] tests/qtest: arm-cpu-features: Match tests to required accelerators Fabiano Rosas
@ 2023-01-19 18:37 ` Richard Henderson
2023-01-20 10:11 ` Thomas Huth
1 sibling, 0 replies; 45+ messages in thread
From: Richard Henderson @ 2023-01-19 18:37 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck, Thomas Huth,
Laurent Vivier
On 1/19/23 03:54, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas<farosas@suse.de>
> ---
> tests/qtest/arm-cpu-features.c | 22 +++++++++++++++-------
> 1 file changed, 15 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 05/15] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
2023-01-19 13:54 ` [RFC PATCH v4 05/15] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG Fabiano Rosas
@ 2023-01-19 18:39 ` Richard Henderson
2023-01-20 10:14 ` Thomas Huth
2023-01-20 10:19 ` Thomas Huth
2 siblings, 0 replies; 45+ messages in thread
From: Richard Henderson @ 2023-01-19 18:39 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck, Thomas Huth,
Laurent Vivier
On 1/19/23 03:54, Fabiano Rosas wrote:
> These tests set -accel tcg, so restrict them to when TCG is present.
>
> Signed-off-by: Fabiano Rosas<farosas@suse.de>
> ---
> tests/qtest/meson.build | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
Acked-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 14/15] arm/Kconfig: Always select SEMIHOSTING when TCG is present
2023-01-19 13:54 ` [RFC PATCH v4 14/15] arm/Kconfig: Always select SEMIHOSTING when TCG is present Fabiano Rosas
@ 2023-01-19 18:50 ` Richard Henderson
2023-01-19 20:03 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 45+ messages in thread
From: Richard Henderson @ 2023-01-19 18:50 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck
On 1/19/23 03:54, Fabiano Rosas wrote:
> We are about to enable the build without TCG, so CONFIG_SEMIHOSTING
> and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in
> default.mak anymore. So reflect the change in a Kconfig.
>
> Instead of using semihosting/Kconfig, use a target-specific file, so
> that the change doesn't affect other architectures which might
> implement semihosting in a way compatible with KVM.
>
> The selection from ARM_v7M needs to be removed to avoid a cycle during
> parsing.
>
> Signed-off-by: Fabiano Rosas<farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> The linux-user build does not use Kconfig. Is it worth it to add
> support to it? There's just the semihosting config so far.
Probably not.
r~
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 15/15] arm/Kconfig: Do not build TCG-only boards on a KVM-only build
2023-01-19 13:54 ` [RFC PATCH v4 15/15] arm/Kconfig: Do not build TCG-only boards on a KVM-only build Fabiano Rosas
@ 2023-01-19 18:50 ` Richard Henderson
2023-01-19 20:08 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 45+ messages in thread
From: Richard Henderson @ 2023-01-19 18:50 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck
On 1/19/23 03:54, Fabiano Rosas wrote:
> Move all the CONFIG_FOO=y from default.mak into "default y if TCG"
> statements in Kconfig. That way they won't be selected when
> CONFIG_TCG=n.
>
> I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to
> keep the two default.mak files not empty and keep aarch64-default.mak
> including arm-default.mak. That way we don't surprise anyone that's
> used to altering these files.
>
> With this change we can start building with --disable-tcg.
>
> Signed-off-by: Fabiano Rosas<farosas@suse.de>
> ---
> sbsa-ref has an explicit check to avoid running with KVM
> xlnx-versal-virt has avocado tests tagged with tcg
> ---
> configs/devices/aarch64-softmmu/default.mak | 4 --
> configs/devices/arm-softmmu/default.mak | 37 ------------------
> hw/arm/Kconfig | 42 ++++++++++++++++++++-
> 3 files changed, 41 insertions(+), 42 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 12/15] tests/tcg: Do not build/run TCG tests if TCG is disabled
2023-01-19 13:54 ` [RFC PATCH v4 12/15] tests/tcg: Do not build/run TCG tests if TCG is disabled Fabiano Rosas
@ 2023-01-19 18:52 ` Richard Henderson
2023-01-19 19:49 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 45+ messages in thread
From: Richard Henderson @ 2023-01-19 18:52 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck, Thomas Huth
On 1/19/23 03:54, Fabiano Rosas wrote:
> The tests under tests/tcg depend on the TCG accelerator. Do not build
> them if --disable-tcg was given in the configure line.
>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> configure | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
Amusing that this wasn't found earlier. But it does in fact give nonsense results for
--disable-tcg on x86_64 host as well.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 06/15] tests/qtest: Add qtest_get_machine_args
2023-01-19 13:54 ` [RFC PATCH v4 06/15] tests/qtest: Add qtest_get_machine_args Fabiano Rosas
@ 2023-01-19 18:55 ` Richard Henderson
2023-01-20 11:48 ` Thomas Huth
1 sibling, 0 replies; 45+ messages in thread
From: Richard Henderson @ 2023-01-19 18:55 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck, Thomas Huth,
Laurent Vivier
On 1/19/23 03:54, Fabiano Rosas wrote:
> QEMU machines might not have a default value defined for the -cpu
> option. Add a custom init function that takes care of selecting the
> default cpu in case the test did not specify one. For the machines
> that do not have a default, the value MUST be provided by the test.
>
> Signed-off-by: Fabiano Rosas<farosas@suse.de>
> ---
> tests/qtest/libqtest.c | 99 ++++++++++++++++++++++++++++++++++++++++++
> tests/qtest/libqtest.h | 11 +++++
> 2 files changed, 110 insertions(+)
Looks plausible.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 07/15] tests/qtest: Adjust qom-test to always set a -cpu option
2023-01-19 13:54 ` [RFC PATCH v4 07/15] tests/qtest: Adjust qom-test to always set a -cpu option Fabiano Rosas
@ 2023-01-19 19:00 ` Richard Henderson
2023-01-19 19:12 ` Fabiano Rosas
0 siblings, 1 reply; 45+ messages in thread
From: Richard Henderson @ 2023-01-19 19:00 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck, Thomas Huth,
Laurent Vivier
On 1/19/23 03:54, Fabiano Rosas wrote:
> Start using the qtest_get_machine_args function, which explicitly
> sets the -cpu option according to the machine default.
>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> tests/qtest/qom-test.c | 19 +++++++++++++++++--
> 1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/tests/qtest/qom-test.c b/tests/qtest/qom-test.c
> index d380261f8f..462e3c4281 100644
> --- a/tests/qtest/qom-test.c
> +++ b/tests/qtest/qom-test.c
> @@ -78,14 +78,28 @@ static void test_properties(QTestState *qts, const char *path, bool recurse)
> qobject_unref(response);
> }
>
> +static const char *arch_get_cpu(const char *machine)
> +{
> + const char *arch = qtest_get_arch();
> +
> + if (g_str_equal(arch, "aarch64")) {
> + if (!strncmp(machine, "virt", 4)) {
> + return "cortex-a57";
I'm not keen on hard-coding cortex-a57 instead of max, even if they happen to evaluate to
mostly the same thing currently for -accel qtest.
Nor am I keen on replicating this N times across N qtest files.
Better perhaps in libqtest.c, or something?
Or even directly in qtest_get_machine_args()?
r~
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 01/15] target/arm: Move 64-bit TCG CPUs into tcg/
2023-01-19 18:31 ` Richard Henderson
@ 2023-01-19 19:07 ` Fabiano Rosas
2023-01-19 19:17 ` Richard Henderson
0 siblings, 1 reply; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 19:07 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck
Richard Henderson <richard.henderson@linaro.org> writes:
> On 1/19/23 03:54, Fabiano Rosas wrote:
>> Move the 64-bit CPUs that are TCG-only:
>> - cortex-a35
>> - cortex-a55
>> - cortex-a72
>> - cortex-a76
>> - a64fx
>> - neoverse-n1
>>
>> Keep the CPUs that can be used with KVM:
>> - cortex-a57
>> - cortex-a53
>> - max
>> - host
>
> All of those cpus can be used with kvm, if and only if you have matching hardware. There
> is no rationale for considering any of them differently.
But is that allowed by QEMU today? If so I must be missing something. I
see that kvm_arch_init_vcpu looks at cpu->kvm_target, which is only set
at kvm_arm_set_cpu_features_from_host, called from aarch64_host_initfn.
if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
!object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
error_report("KVM is not supported for this guest CPU type");
return -EINVAL;
}
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 11/15] tests/qemu-iotests: Allow passing a -cpu option in the QEMU cmdline
2023-01-19 13:54 ` [RFC PATCH v4 11/15] tests/qemu-iotests: Allow passing a -cpu option in the QEMU cmdline Fabiano Rosas
@ 2023-01-19 19:09 ` Richard Henderson
2023-01-19 19:21 ` Fabiano Rosas
0 siblings, 1 reply; 45+ messages in thread
From: Richard Henderson @ 2023-01-19 19:09 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck, Kevin Wolf,
Hanna Reitz
On 1/19/23 03:54, Fabiano Rosas wrote:
> + cpu_map = (
> + ('aarch64', 'cortex-a57'),
> + )
This isn't a map...
> + for suffix, cpu in cpu_map:
> + if self.qemu_prog.endswith(f'qemu-system-{suffix}'):
> + self.qemu_options += f' -cpu {cpu}'
... which causes you to use a loop here, instead of a map lookup.
Also, not keen on cortex-a57 vs max, again.
You want something like
cpu_map = {
'aarch64': 'max'
}
m = re.match('qemu-system-(.*)', self.qemu_prog)
if m and m.group(1) in cpu_map:
self.qemu_options += ' -cpu ' + cpu_map[m.group(1)]
My python is rough, so take that with a lot of testing...
r~
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 07/15] tests/qtest: Adjust qom-test to always set a -cpu option
2023-01-19 19:00 ` Richard Henderson
@ 2023-01-19 19:12 ` Fabiano Rosas
0 siblings, 0 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 19:12 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck, Thomas Huth,
Laurent Vivier
Richard Henderson <richard.henderson@linaro.org> writes:
> On 1/19/23 03:54, Fabiano Rosas wrote:
>> Start using the qtest_get_machine_args function, which explicitly
>> sets the -cpu option according to the machine default.
>>
>> Signed-off-by: Fabiano Rosas <farosas@suse.de>
>> ---
>> tests/qtest/qom-test.c | 19 +++++++++++++++++--
>> 1 file changed, 17 insertions(+), 2 deletions(-)
>>
>> diff --git a/tests/qtest/qom-test.c b/tests/qtest/qom-test.c
>> index d380261f8f..462e3c4281 100644
>> --- a/tests/qtest/qom-test.c
>> +++ b/tests/qtest/qom-test.c
>> @@ -78,14 +78,28 @@ static void test_properties(QTestState *qts, const char *path, bool recurse)
>> qobject_unref(response);
>> }
>>
>> +static const char *arch_get_cpu(const char *machine)
>> +{
>> + const char *arch = qtest_get_arch();
>> +
>> + if (g_str_equal(arch, "aarch64")) {
>> + if (!strncmp(machine, "virt", 4)) {
>> + return "cortex-a57";
>
> I'm not keen on hard-coding cortex-a57 instead of max, even if they happen to evaluate to
> mostly the same thing currently for -accel qtest.
Ok.
> Nor am I keen on replicating this N times across N qtest files.
> Better perhaps in libqtest.c, or something?
> Or even directly in qtest_get_machine_args()?
Ah right, this was a callback in a previous version so there was no
"cpu" parameter to qtest_get_machine_args. Now I could indeed move
arch_get_cpu into libqtest.c somewhere.
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 01/15] target/arm: Move 64-bit TCG CPUs into tcg/
2023-01-19 19:07 ` Fabiano Rosas
@ 2023-01-19 19:17 ` Richard Henderson
0 siblings, 0 replies; 45+ messages in thread
From: Richard Henderson @ 2023-01-19 19:17 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck
On 1/19/23 09:07, Fabiano Rosas wrote:
> Richard Henderson <richard.henderson@linaro.org> writes:
>
>> On 1/19/23 03:54, Fabiano Rosas wrote:
>>> Move the 64-bit CPUs that are TCG-only:
>>> - cortex-a35
>>> - cortex-a55
>>> - cortex-a72
>>> - cortex-a76
>>> - a64fx
>>> - neoverse-n1
>>>
>>> Keep the CPUs that can be used with KVM:
>>> - cortex-a57
>>> - cortex-a53
>>> - max
>>> - host
>>
>> All of those cpus can be used with kvm, if and only if you have matching hardware. There
>> is no rationale for considering any of them differently.
>
> But is that allowed by QEMU today? If so I must be missing something. I
> see that kvm_arch_init_vcpu looks at cpu->kvm_target, which is only set
> at kvm_arm_set_cpu_features_from_host, called from aarch64_host_initfn.
>
> if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
> !object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
> error_report("KVM is not supported for this guest CPU type");
> return -EINVAL;
> }
Hmm, no, you're right. It could guess that some of those could be marked
KVM_ARM_TARGET_GENERIC_V8, but there's probably no point, since -cpu {host,max} are the
only reasonable options to use with kvm, practically.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 11/15] tests/qemu-iotests: Allow passing a -cpu option in the QEMU cmdline
2023-01-19 19:09 ` Richard Henderson
@ 2023-01-19 19:21 ` Fabiano Rosas
0 siblings, 0 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 19:21 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck, Kevin Wolf,
Hanna Reitz
Richard Henderson <richard.henderson@linaro.org> writes:
> On 1/19/23 03:54, Fabiano Rosas wrote:
>> + cpu_map = (
>> + ('aarch64', 'cortex-a57'),
>> + )
>
> This isn't a map...
Right, a dict would be more suitable here. I had just copied the code
from machine_map a few lines above.
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 13/15] target/avocado: Pass parameters to migration test on aarch64
2023-01-19 13:54 ` [RFC PATCH v4 13/15] target/avocado: Pass parameters to migration test on aarch64 Fabiano Rosas
@ 2023-01-19 19:29 ` Richard Henderson
0 siblings, 0 replies; 45+ messages in thread
From: Richard Henderson @ 2023-01-19 19:29 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck, Cleber Rosa,
Wainer dos Santos Moschetta, Beraldo Leal
On 1/19/23 03:54, Fabiano Rosas wrote:
> The migration tests are currently broken for an aarch64 host because
> the tests pass no 'machine' and 'cpu' options on the QEMU command
> line. Most other architectures define a default value in QEMU for
> these options, but arm does not.
>
> Add these options to the test class in case the test is being executed
> in an aarch64 host.
>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> Don't we want to run migration tests for all the built targets? A
> cleaner approach would be to just subclass Migration for each
> archictecture like in boot_linux.py.
> ---
> tests/avocado/migration.py | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> @@ -62,7 +72,6 @@ def _get_free_port(self):
> self.cancel('Failed to find a free port')
> return port
>
> -
> def test_migration_with_tcp_localhost(self):
> dest_uri = 'tcp:localhost:%u' % self._get_free_port()
> self.do_migrate(dest_uri)
Unrelated change. Also, I think there's some python style guide that suggests 2 lines
between functions and classes.
r~
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 12/15] tests/tcg: Do not build/run TCG tests if TCG is disabled
2023-01-19 13:54 ` [RFC PATCH v4 12/15] tests/tcg: Do not build/run TCG tests if TCG is disabled Fabiano Rosas
2023-01-19 18:52 ` Richard Henderson
@ 2023-01-19 19:49 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 45+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-01-19 19:49 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Richard Henderson, Alex Bennée,
Paolo Bonzini, Claudio Fontana, Eduardo Habkost, Alexander Graf,
Cornelia Huck, Thomas Huth
On 19/1/23 14:54, Fabiano Rosas wrote:
> The tests under tests/tcg depend on the TCG accelerator. Do not build
> them if --disable-tcg was given in the configure line.
>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> configure | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 14/15] arm/Kconfig: Always select SEMIHOSTING when TCG is present
2023-01-19 18:50 ` Richard Henderson
@ 2023-01-19 20:03 ` Philippe Mathieu-Daudé
2023-01-19 21:40 ` Fabiano Rosas
0 siblings, 1 reply; 45+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-01-19 20:03 UTC (permalink / raw)
To: Richard Henderson, Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth
On 19/1/23 19:50, Richard Henderson wrote:
> On 1/19/23 03:54, Fabiano Rosas wrote:
>> We are about to enable the build without TCG, so CONFIG_SEMIHOSTING
>> and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in
>> default.mak anymore. So reflect the change in a Kconfig.
>>
>> Instead of using semihosting/Kconfig, use a target-specific file, so
>> that the change doesn't affect other architectures which might
>> implement semihosting in a way compatible with KVM.
>>
>> The selection from ARM_v7M needs to be removed to avoid a cycle during
>> parsing.
>>
>> Signed-off-by: Fabiano Rosas<farosas@suse.de>
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>> The linux-user build does not use Kconfig. Is it worth it to add
>> support to it? There's just the semihosting config so far.
>
> Probably not.
I hit this limitation last week trying to restrict libdecnumber to
powerpc targets.
Fabiano, do you see how this can be done easily?
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 15/15] arm/Kconfig: Do not build TCG-only boards on a KVM-only build
2023-01-19 18:50 ` Richard Henderson
@ 2023-01-19 20:08 ` Philippe Mathieu-Daudé
2023-01-19 21:47 ` Fabiano Rosas
0 siblings, 1 reply; 45+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-01-19 20:08 UTC (permalink / raw)
To: Richard Henderson, Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
On 19/1/23 19:50, Richard Henderson wrote:
> On 1/19/23 03:54, Fabiano Rosas wrote:
>> Move all the CONFIG_FOO=y from default.mak into "default y if TCG"
>> statements in Kconfig. That way they won't be selected when
>> CONFIG_TCG=n.
>>
>> I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to
>> keep the two default.mak files not empty and keep aarch64-default.mak
>> including arm-default.mak. That way we don't surprise anyone that's
>> used to altering these files.
>>
>> With this change we can start building with --disable-tcg.
>>
>> Signed-off-by: Fabiano Rosas<farosas@suse.de>
>> ---
>> sbsa-ref has an explicit check to avoid running with KVM
>> xlnx-versal-virt has avocado tests tagged with tcg
>> ---
>> configs/devices/aarch64-softmmu/default.mak | 4 --
>> configs/devices/arm-softmmu/default.mak | 37 ------------------
>> hw/arm/Kconfig | 42 ++++++++++++++++++++-
>> 3 files changed, 41 insertions(+), 42 deletions(-)
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
The previous version was cleaner IMHO, not restricting only the
machines but also the cores:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg777724.html
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 03/15] target/arm: Remove default cpu for KVM-only builds
2023-01-19 13:54 ` [RFC PATCH v4 03/15] target/arm: Remove default cpu for KVM-only builds Fabiano Rosas
@ 2023-01-19 20:19 ` Richard Henderson
2023-01-20 12:24 ` Daniel P. Berrangé
1 sibling, 0 replies; 45+ messages in thread
From: Richard Henderson @ 2023-01-19 20:19 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Alex Bennée, Paolo Bonzini, Claudio Fontana,
Eduardo Habkost, Alexander Graf, Cornelia Huck, Thomas Huth,
Laurent Vivier
On 1/19/23 03:54, Fabiano Rosas wrote:
> We'd prefer if the user always had to specify the machine and cpu
> options in the command line instead of relying on defaults.
>
> Since the KVM build already doesn't work with the current default of
> cortex-a15, remove the default altogether for KVM builds.
>
> Signed-off-by: Fabiano Rosas<farosas@suse.de>
> ---
> hw/arm/virt.c | 9 +++++++++
> tests/qtest/arm-cpu-features.c | 12 +++++++++---
> 2 files changed, 18 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 14/15] arm/Kconfig: Always select SEMIHOSTING when TCG is present
2023-01-19 20:03 ` Philippe Mathieu-Daudé
@ 2023-01-19 21:40 ` Fabiano Rosas
0 siblings, 0 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 21:40 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel
Cc: qemu-arm, Peter Maydell, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth
Philippe Mathieu-Daudé <philmd@linaro.org> writes:
> On 19/1/23 19:50, Richard Henderson wrote:
>> On 1/19/23 03:54, Fabiano Rosas wrote:
>>> We are about to enable the build without TCG, so CONFIG_SEMIHOSTING
>>> and CONFIG_ARM_COMPATIBLE_SEMIHOSTING cannot be unconditionally set in
>>> default.mak anymore. So reflect the change in a Kconfig.
>>>
>>> Instead of using semihosting/Kconfig, use a target-specific file, so
>>> that the change doesn't affect other architectures which might
>>> implement semihosting in a way compatible with KVM.
>>>
>>> The selection from ARM_v7M needs to be removed to avoid a cycle during
>>> parsing.
>>>
>>> Signed-off-by: Fabiano Rosas<farosas@suse.de>
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>
>>> The linux-user build does not use Kconfig. Is it worth it to add
>>> support to it? There's just the semihosting config so far.
>>
>> Probably not.
>
> I hit this limitation last week trying to restrict libdecnumber to
> powerpc targets.
>
> Fabiano, do you see how this can be done easily?
If you grep for Kconfig in the top level meson.build, that code there
could be adapted to also include linux-user targets.
I did some experimenting and I could generate linux-user.mak files with
all the configs from the existing Kconfigs. It would be a matter of
adding the proper CONFIG_SOFTMMU, CONFIG_LINUX_USER options to separate
the two and then hooking up the .mak files with the rest of the
build. That last part I'm not sure how to do.
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 15/15] arm/Kconfig: Do not build TCG-only boards on a KVM-only build
2023-01-19 20:08 ` Philippe Mathieu-Daudé
@ 2023-01-19 21:47 ` Fabiano Rosas
0 siblings, 0 replies; 45+ messages in thread
From: Fabiano Rosas @ 2023-01-19 21:47 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Richard Henderson, qemu-devel
Cc: qemu-arm, Peter Maydell, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck
Philippe Mathieu-Daudé <philmd@linaro.org> writes:
> On 19/1/23 19:50, Richard Henderson wrote:
>> On 1/19/23 03:54, Fabiano Rosas wrote:
>>> Move all the CONFIG_FOO=y from default.mak into "default y if TCG"
>>> statements in Kconfig. That way they won't be selected when
>>> CONFIG_TCG=n.
>>>
>>> I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to
>>> keep the two default.mak files not empty and keep aarch64-default.mak
>>> including arm-default.mak. That way we don't surprise anyone that's
>>> used to altering these files.
>>>
>>> With this change we can start building with --disable-tcg.
>>>
>>> Signed-off-by: Fabiano Rosas<farosas@suse.de>
>>> ---
>>> sbsa-ref has an explicit check to avoid running with KVM
>>> xlnx-versal-virt has avocado tests tagged with tcg
>>> ---
>>> configs/devices/aarch64-softmmu/default.mak | 4 --
>>> configs/devices/arm-softmmu/default.mak | 37 ------------------
>>> hw/arm/Kconfig | 42 ++++++++++++++++++++-
>>> 3 files changed, 41 insertions(+), 42 deletions(-)
>>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> The previous version was cleaner IMHO, not restricting only the
> machines but also the cores:
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg777724.html
I'm not able to apply that thread, there's missing emails in lore. =/
What do you suggest here? I like that you added detailed descriptions of
what was being removed and why. But it seems there's a lot left to be
restricted still, compared to this patch.
I also don't really understand what you mean by "also the cores". This
series already moved all cpus under CONFIG_TCG and what's left is only
the machines. If there's extra refinement to the configs, we should
definitely look into doing it, but I think that could come as a
follow-up series.
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 04/15] tests/qtest: arm-cpu-features: Match tests to required accelerators
2023-01-19 13:54 ` [RFC PATCH v4 04/15] tests/qtest: arm-cpu-features: Match tests to required accelerators Fabiano Rosas
2023-01-19 18:37 ` Richard Henderson
@ 2023-01-20 10:11 ` Thomas Huth
1 sibling, 0 replies; 45+ messages in thread
From: Thomas Huth @ 2023-01-20 10:11 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Laurent Vivier
On 19/01/2023 14.54, Fabiano Rosas wrote:
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> tests/qtest/arm-cpu-features.c | 22 +++++++++++++++-------
> 1 file changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
> index 4ff2014bea..1555b0bab8 100644
> --- a/tests/qtest/arm-cpu-features.c
> +++ b/tests/qtest/arm-cpu-features.c
> @@ -21,7 +21,7 @@
> #define SVE_MAX_VQ 16
>
> #define MACHINE "-machine virt,gic-version=max -accel tcg "
> -#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm -accel tcg "
> +#define MACHINE_KVM "-machine virt,gic-version=max -accel kvm "
> #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \
> " 'arguments': { 'type': 'full', "
> #define QUERY_TAIL "}}"
> @@ -613,31 +613,39 @@ int main(int argc, char **argv)
> {
> g_test_init(&argc, &argv, NULL);
>
> - qtest_add_data_func("/arm/query-cpu-model-expansion",
> - NULL, test_query_cpu_model_expansion);
> + if (qtest_has_accel("tcg")) {
> + qtest_add_data_func("/arm/query-cpu-model-expansion",
> + NULL, test_query_cpu_model_expansion);
> + }
> +
> + if (!g_str_equal(qtest_get_arch(), "aarch64")) {
> + goto out;
> + }
>
> /*
> * For now we only run KVM specific tests with AArch64 QEMU in
> * order avoid attempting to run an AArch32 QEMU with KVM on
> * AArch64 hosts. That won't work and isn't easy to detect.
> */
> - if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")) {
> + if (qtest_has_accel("kvm")) {
> /*
> * This tests target the 'host' CPU type, so register it only if
> * KVM is available.
> */
> qtest_add_data_func("/arm/kvm/query-cpu-model-expansion",
> NULL, test_query_cpu_model_expansion_kvm);
> +
> + qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
> + NULL, sve_tests_sve_off_kvm);
> }
>
> - if (g_str_equal(qtest_get_arch(), "aarch64")) {
> + if (qtest_has_accel("tcg")) {
> qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq-8",
> NULL, sve_tests_sve_max_vq_8);
> qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off",
> NULL, sve_tests_sve_off);
> - qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off",
> - NULL, sve_tests_sve_off_kvm);
> }
>
> +out:
> return g_test_run();
> }
Acked-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 05/15] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
2023-01-19 13:54 ` [RFC PATCH v4 05/15] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG Fabiano Rosas
2023-01-19 18:39 ` Richard Henderson
@ 2023-01-20 10:14 ` Thomas Huth
2023-01-20 10:19 ` Thomas Huth
2 siblings, 0 replies; 45+ messages in thread
From: Thomas Huth @ 2023-01-20 10:14 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Laurent Vivier
On 19/01/2023 14.54, Fabiano Rosas wrote:
> These tests set -accel tcg, so restrict them to when TCG is present.
>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> tests/qtest/meson.build | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
> index 1af63f8bd2..9dd5c2de6e 100644
> --- a/tests/qtest/meson.build
> +++ b/tests/qtest/meson.build
> @@ -204,8 +204,8 @@ qtests_arm = \
> # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
> qtests_aarch64 = \
> (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \
> - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \
> - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \
> + (config_all_devices.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? \
> + ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \
> (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
> (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
> ['arm-cpu-features',
> @@ -295,11 +295,15 @@ qtests = {
> 'tpm-crb-test': [io, tpmemu_files],
> 'tpm-tis-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'],
> 'tpm-tis-test': [io, tpmemu_files, 'tpm-tis-util.c'],
> - 'tpm-tis-device-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'],
> - 'tpm-tis-device-test': [io, tpmemu_files, 'tpm-tis-util.c'],
> 'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'),
> }
>
> +if config_all_devices.has_key('CONFIG_TCG')
> + qtests += { 'tpm-tis-device-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'],
> + 'tpm-tis-device-test': [io, tpmemu_files, 'tpm-tis-util.c'], }
> +endif
> +
> +
> gvnc = dependency('gvnc-1.0', required: false)
> if gvnc.found()
> qtests += {'vnc-display-test': [gvnc]}
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 05/15] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
2023-01-19 13:54 ` [RFC PATCH v4 05/15] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG Fabiano Rosas
2023-01-19 18:39 ` Richard Henderson
2023-01-20 10:14 ` Thomas Huth
@ 2023-01-20 10:19 ` Thomas Huth
2 siblings, 0 replies; 45+ messages in thread
From: Thomas Huth @ 2023-01-20 10:19 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Laurent Vivier
On 19/01/2023 14.54, Fabiano Rosas wrote:
> These tests set -accel tcg, so restrict them to when TCG is present.
>
> Signed-off-by: Fabiano Rosas <farosas@suse.de>
> ---
> tests/qtest/meson.build | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
> index 1af63f8bd2..9dd5c2de6e 100644
> --- a/tests/qtest/meson.build
> +++ b/tests/qtest/meson.build
> @@ -204,8 +204,8 @@ qtests_arm = \
> # TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-test unconditional
> qtests_aarch64 = \
> (cpu != 'arm' and unpack_edk2_blobs ? ['bios-tables-test'] : []) + \
> - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-test'] : []) + \
> - (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-swtpm-test'] : []) + \
> + (config_all_devices.has_key('CONFIG_TCG') and config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? \
> + ['tpm-tis-device-test', 'tpm-tis-device-swtpm-test'] : []) + \
> (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test', 'fuzz-xlnx-dp-test'] : []) + \
> (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \
> ['arm-cpu-features',
> @@ -295,11 +295,15 @@ qtests = {
> 'tpm-crb-test': [io, tpmemu_files],
> 'tpm-tis-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'],
> 'tpm-tis-test': [io, tpmemu_files, 'tpm-tis-util.c'],
> - 'tpm-tis-device-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'],
> - 'tpm-tis-device-test': [io, tpmemu_files, 'tpm-tis-util.c'],
> 'vmgenid-test': files('boot-sector.c', 'acpi-utils.c'),
> }
>
> +if config_all_devices.has_key('CONFIG_TCG')
> + qtests += { 'tpm-tis-device-swtpm-test': [io, tpmemu_files, 'tpm-tis-util.c'],
> + 'tpm-tis-device-test': [io, tpmemu_files, 'tpm-tis-util.c'], }
> +endif
Hmmm, I think the second hunk is maybe not necessary - it's just for
declaring the dependencies, but not for adding the tests to the set that is
run later.
Thomas
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 06/15] tests/qtest: Add qtest_get_machine_args
2023-01-19 13:54 ` [RFC PATCH v4 06/15] tests/qtest: Add qtest_get_machine_args Fabiano Rosas
2023-01-19 18:55 ` Richard Henderson
@ 2023-01-20 11:48 ` Thomas Huth
2023-01-20 12:00 ` Cornelia Huck
1 sibling, 1 reply; 45+ messages in thread
From: Thomas Huth @ 2023-01-20 11:48 UTC (permalink / raw)
To: Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Laurent Vivier
On 19/01/2023 14.54, Fabiano Rosas wrote:
> QEMU machines might not have a default value defined for the -cpu
> option.
Which machines for example? ... I thought we'd have a default CPU everywhere?
Thomas
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 06/15] tests/qtest: Add qtest_get_machine_args
2023-01-20 11:48 ` Thomas Huth
@ 2023-01-20 12:00 ` Cornelia Huck
2023-01-20 12:12 ` Thomas Huth
0 siblings, 1 reply; 45+ messages in thread
From: Cornelia Huck @ 2023-01-20 12:00 UTC (permalink / raw)
To: Thomas Huth, Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Laurent Vivier
On Fri, Jan 20 2023, Thomas Huth <thuth@redhat.com> wrote:
> On 19/01/2023 14.54, Fabiano Rosas wrote:
>> QEMU machines might not have a default value defined for the -cpu
>> option.
>
> Which machines for example? ... I thought we'd have a default CPU everywhere?
There's a patch further above that removes it for KVM on Arm... do you
think that's a bad idea? In that case, I'm not sure what the default for
that case should even be...
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 06/15] tests/qtest: Add qtest_get_machine_args
2023-01-20 12:00 ` Cornelia Huck
@ 2023-01-20 12:12 ` Thomas Huth
0 siblings, 0 replies; 45+ messages in thread
From: Thomas Huth @ 2023-01-20 12:12 UTC (permalink / raw)
To: Cornelia Huck, Fabiano Rosas, qemu-devel
Cc: qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Laurent Vivier
On 20/01/2023 13.00, Cornelia Huck wrote:
> On Fri, Jan 20 2023, Thomas Huth <thuth@redhat.com> wrote:
>
>> On 19/01/2023 14.54, Fabiano Rosas wrote:
>>> QEMU machines might not have a default value defined for the -cpu
>>> option.
>>
>> Which machines for example? ... I thought we'd have a default CPU everywhere?
>
> There's a patch further above that removes it for KVM on Arm... do you
> think that's a bad idea? In that case, I'm not sure what the default for
> that case should even be...
Well, if there is just one machine in the whole of QEMU that does not have a
default CPU anymore, that calls for trouble, I think (as we can already see
in this series where you have to rework a lot of qtests). It's likely better
to set another CPU as default in that machine in that case. What about
simply using "max" or "host" if TCG is disabled there?
Thomas
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [RFC PATCH v4 03/15] target/arm: Remove default cpu for KVM-only builds
2023-01-19 13:54 ` [RFC PATCH v4 03/15] target/arm: Remove default cpu for KVM-only builds Fabiano Rosas
2023-01-19 20:19 ` Richard Henderson
@ 2023-01-20 12:24 ` Daniel P. Berrangé
1 sibling, 0 replies; 45+ messages in thread
From: Daniel P. Berrangé @ 2023-01-20 12:24 UTC (permalink / raw)
To: Fabiano Rosas
Cc: qemu-devel, qemu-arm, Peter Maydell, Philippe Mathieu-Daudé,
Richard Henderson, Alex Bennée, Paolo Bonzini,
Claudio Fontana, Eduardo Habkost, Alexander Graf, Cornelia Huck,
Thomas Huth, Laurent Vivier
On Thu, Jan 19, 2023 at 10:54:12AM -0300, Fabiano Rosas wrote:
> We'd prefer if the user always had to specify the machine and cpu
> options in the command line instead of relying on defaults.
>
> Since the KVM build already doesn't work with the current default of
> cortex-a15, remove the default altogether for KVM builds.
IMHO not having a working default CPU model is a undesirable
state to be in and user hostile, especially so when it makes
aarch64 be a special case compared to other targets.
Can't we just make 'host' be the default model for KVM, if
the named CPU models don't work ?
With regards,
Daniel
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^ permalink raw reply [flat|nested] 45+ messages in thread
end of thread, other threads:[~2023-01-20 12:26 UTC | newest]
Thread overview: 45+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-19 13:54 [RFC PATCH v4 00/15] target/arm: Allow CONFIG_TCG=n builds Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 01/15] target/arm: Move 64-bit TCG CPUs into tcg/ Fabiano Rosas
2023-01-19 18:31 ` Richard Henderson
2023-01-19 19:07 ` Fabiano Rosas
2023-01-19 19:17 ` Richard Henderson
2023-01-19 13:54 ` [RFC PATCH v4 02/15] target/arm: move cpu_tcg to tcg/cpu32.c Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 03/15] target/arm: Remove default cpu for KVM-only builds Fabiano Rosas
2023-01-19 20:19 ` Richard Henderson
2023-01-20 12:24 ` Daniel P. Berrangé
2023-01-19 13:54 ` [RFC PATCH v4 04/15] tests/qtest: arm-cpu-features: Match tests to required accelerators Fabiano Rosas
2023-01-19 18:37 ` Richard Henderson
2023-01-20 10:11 ` Thomas Huth
2023-01-19 13:54 ` [RFC PATCH v4 05/15] tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG Fabiano Rosas
2023-01-19 18:39 ` Richard Henderson
2023-01-20 10:14 ` Thomas Huth
2023-01-20 10:19 ` Thomas Huth
2023-01-19 13:54 ` [RFC PATCH v4 06/15] tests/qtest: Add qtest_get_machine_args Fabiano Rosas
2023-01-19 18:55 ` Richard Henderson
2023-01-20 11:48 ` Thomas Huth
2023-01-20 12:00 ` Cornelia Huck
2023-01-20 12:12 ` Thomas Huth
2023-01-19 13:54 ` [RFC PATCH v4 07/15] tests/qtest: Adjust qom-test to always set a -cpu option Fabiano Rosas
2023-01-19 19:00 ` Richard Henderson
2023-01-19 19:12 ` Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 08/15] tests/qtest: Adjust test-hmp to always pass " Fabiano Rosas
2023-01-19 14:06 ` Dr. David Alan Gilbert
2023-01-19 14:39 ` Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 09/15] tests/qtest: Adjust device-introspect-test to always set a " Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 10/15] tests/qtest: aarch64: Set -cpu for numa-test Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 11/15] tests/qemu-iotests: Allow passing a -cpu option in the QEMU cmdline Fabiano Rosas
2023-01-19 19:09 ` Richard Henderson
2023-01-19 19:21 ` Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 12/15] tests/tcg: Do not build/run TCG tests if TCG is disabled Fabiano Rosas
2023-01-19 18:52 ` Richard Henderson
2023-01-19 19:49 ` Philippe Mathieu-Daudé
2023-01-19 13:54 ` [RFC PATCH v4 13/15] target/avocado: Pass parameters to migration test on aarch64 Fabiano Rosas
2023-01-19 19:29 ` Richard Henderson
2023-01-19 13:54 ` [RFC PATCH v4 14/15] arm/Kconfig: Always select SEMIHOSTING when TCG is present Fabiano Rosas
2023-01-19 18:50 ` Richard Henderson
2023-01-19 20:03 ` Philippe Mathieu-Daudé
2023-01-19 21:40 ` Fabiano Rosas
2023-01-19 13:54 ` [RFC PATCH v4 15/15] arm/Kconfig: Do not build TCG-only boards on a KVM-only build Fabiano Rosas
2023-01-19 18:50 ` Richard Henderson
2023-01-19 20:08 ` Philippe Mathieu-Daudé
2023-01-19 21:47 ` Fabiano Rosas
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