From: Jonathan Cameron <Jonathan.Cameron@huawei.com> To: <qemu-devel@nongnu.org>, Michael Tsirkin <mst@redhat.com> Cc: Ben Widawsky <bwidawsk@kernel.org>, <linux-cxl@vger.kernel.org>, <linuxarm@huawei.com>, Ira Weiny <ira.weiny@intel.com>, Dave Jiang <dave.jiang@intel.com>, <alison.schofield@intel.com>, Mike Maslenkin <mike.maslenkin@gmail.com> Subject: [PATCH v2 1/7] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Date: Fri, 20 Jan 2023 14:24:44 +0000 [thread overview] Message-ID: <20230120142450.16089-2-Jonathan.Cameron@huawei.com> (raw) In-Reply-To: <20230120142450.16089-1-Jonathan.Cameron@huawei.com> This register in AER should be both writeable and should have a default value with a couple of the errors masked including the Uncorrectable Internal Error used by CXL for it's error reporting. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> --- hw/pci/pcie_aer.c | 4 ++++ include/hw/pci/pcie_regs.h | 3 +++ 2 files changed, 7 insertions(+) diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c index 9a19be44ae..909e027d99 100644 --- a/hw/pci/pcie_aer.c +++ b/hw/pci/pcie_aer.c @@ -112,6 +112,10 @@ int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset, pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS, PCI_ERR_UNC_SUPPORTED); + pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK, + PCI_ERR_UNC_MASK_DEFAULT); + pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK, + PCI_ERR_UNC_SUPPORTED); pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER, PCI_ERR_UNC_SEVERITY_DEFAULT); diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 963dc2e170..6ec4785448 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -155,6 +155,9 @@ typedef enum PCIExpLinkWidth { PCI_ERR_UNC_ATOP_EBLOCKED | \ PCI_ERR_UNC_TLP_PRF_BLOCKED) +#define PCI_ERR_UNC_MASK_DEFAULT (PCI_ERR_UNC_INTN | \ + PCI_ERR_UNC_TLP_PRF_BLOCKED) + #define PCI_ERR_UNC_SEVERITY_DEFAULT (PCI_ERR_UNC_DLP | \ PCI_ERR_UNC_SDN | \ PCI_ERR_UNC_FCP | \ -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org> To: <qemu-devel@nongnu.org>, Michael Tsirkin <mst@redhat.com> Cc: Ben Widawsky <bwidawsk@kernel.org>, <linux-cxl@vger.kernel.org>, <linuxarm@huawei.com>, Ira Weiny <ira.weiny@intel.com>, Dave Jiang <dave.jiang@intel.com>, <alison.schofield@intel.com>, Mike Maslenkin <mike.maslenkin@gmail.com> Subject: [PATCH v2 1/7] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Date: Fri, 20 Jan 2023 14:24:44 +0000 [thread overview] Message-ID: <20230120142450.16089-2-Jonathan.Cameron@huawei.com> (raw) In-Reply-To: <20230120142450.16089-1-Jonathan.Cameron@huawei.com> This register in AER should be both writeable and should have a default value with a couple of the errors masked including the Uncorrectable Internal Error used by CXL for it's error reporting. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> --- hw/pci/pcie_aer.c | 4 ++++ include/hw/pci/pcie_regs.h | 3 +++ 2 files changed, 7 insertions(+) diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c index 9a19be44ae..909e027d99 100644 --- a/hw/pci/pcie_aer.c +++ b/hw/pci/pcie_aer.c @@ -112,6 +112,10 @@ int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset, pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS, PCI_ERR_UNC_SUPPORTED); + pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK, + PCI_ERR_UNC_MASK_DEFAULT); + pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK, + PCI_ERR_UNC_SUPPORTED); pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER, PCI_ERR_UNC_SEVERITY_DEFAULT); diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 963dc2e170..6ec4785448 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -155,6 +155,9 @@ typedef enum PCIExpLinkWidth { PCI_ERR_UNC_ATOP_EBLOCKED | \ PCI_ERR_UNC_TLP_PRF_BLOCKED) +#define PCI_ERR_UNC_MASK_DEFAULT (PCI_ERR_UNC_INTN | \ + PCI_ERR_UNC_TLP_PRF_BLOCKED) + #define PCI_ERR_UNC_SEVERITY_DEFAULT (PCI_ERR_UNC_DLP | \ PCI_ERR_UNC_SDN | \ PCI_ERR_UNC_FCP | \ -- 2.37.2
next prev parent reply other threads:[~2023-01-20 14:26 UTC|newest] Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-01-20 14:24 [PATCH v2 0/7] hw/cxl: RAS error emulation and injection Jonathan Cameron via 2023-01-20 14:24 ` Jonathan Cameron 2023-01-20 14:24 ` Jonathan Cameron [this message] 2023-01-20 14:24 ` [PATCH v2 1/7] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Jonathan Cameron via 2023-01-20 14:24 ` [PATCH v2 2/7] hw/pci/aer: Add missing routing for AER errors Jonathan Cameron via 2023-01-20 14:24 ` Jonathan Cameron 2023-01-20 14:24 ` [PATCH v2 3/7] hw/pci-bridge/cxl_root_port: Wire up AER Jonathan Cameron 2023-01-20 14:24 ` Jonathan Cameron via 2023-01-20 14:24 ` [PATCH v2 4/7] hw/pci-bridge/cxl_root_port: Wire up MSI Jonathan Cameron via 2023-01-20 14:24 ` Jonathan Cameron 2023-01-20 14:24 ` [PATCH v2 5/7] hw/mem/cxl-type3: Add AER extended capability Jonathan Cameron via 2023-01-20 14:24 ` Jonathan Cameron 2023-01-20 14:24 ` [PATCH v2 6/7] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use Jonathan Cameron 2023-01-20 14:24 ` Jonathan Cameron via 2023-01-20 14:24 ` [PATCH v2 7/7] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron 2023-01-20 14:24 ` Jonathan Cameron via 2023-01-26 17:35 ` Jonathan Cameron 2023-01-26 17:35 ` Jonathan Cameron via 2023-01-26 5:42 ` [PATCH v2 0/7] hw/cxl: RAS error emulation and injection Ira Weiny 2023-01-26 10:00 ` Jonathan Cameron 2023-01-26 10:00 ` Jonathan Cameron via
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