[PATCH v2 0/2] media: meson: vdec: add HEVC decode codec

[PATCH v2 0/2] media: meson: vdec: add HEVC decode codec

[Christian Hewitt]

This mini-series adds support for HEVC decoding. It combines the original codec
work done by Maxime Jourdan in 2019 [0] and improvements by Benjamin Roszak in
2021 [1]. Only GXBB/GXL/GXM are enabled as decoding currently crashes on G12A
and later SoCs when trying to decode a 10-bit HEVC stream.

The goal of upstreaming the driver in its current state is to encourage greater
community contribution towards adding missing features, and fixing the bugs and
conformance issues necessary to get out of staging.

The HEVC codec presented here is generally partnered with FFMpeg sources that
are being maintained by the Raspberry Pi Foundation [2] and [3] that contain
numerous improvements to v4l2_m2m (and v4l2_request) support. There is active
work in progress to refine the changeset and send it upstream.

Christian

[0] https://github.com/Elyotna/linux/commits/4.20/v4l2-m2m-pr
[1] https://gitlab.com/benjamin545/linux-amlogic/-/commits/aml-hevc
[2] https://github.com/jc-kynesim/rpi-ffmpeg/commits/release/4.4/rpi_import_1
[3] https://github.com/jc-kynesim/rpi-ffmpeg/tree/dev/5.1.2/rpi_import_1

Changes from v1:
- Fix unused val warning reported by kernel test robot <lkp@intel.com>

Benjamin Roszak (1):
  media: meson: vdec: implement 10bit bitstream handling

Maxime Jourdan (1):
  media: meson: vdec: add HEVC decode codec

 drivers/staging/media/meson/vdec/Makefile     |    2 +-
 drivers/staging/media/meson/vdec/codec_h264.c |    3 +-
 drivers/staging/media/meson/vdec/codec_hevc.c | 1462 +++++++++++++++++
 drivers/staging/media/meson/vdec/codec_hevc.h |   13 +
 .../media/meson/vdec/codec_hevc_common.c      |  161 +-
 .../media/meson/vdec/codec_hevc_common.h      |    3 +-
 drivers/staging/media/meson/vdec/codec_vp9.c  |   35 +-
 drivers/staging/media/meson/vdec/esparser.c   |    4 +-
 drivers/staging/media/meson/vdec/hevc_regs.h  |    1 +
 drivers/staging/media/meson/vdec/vdec.h       |    1 +
 .../staging/media/meson/vdec/vdec_helpers.c   |   44 +-
 .../staging/media/meson/vdec/vdec_helpers.h   |   10 +-
 .../staging/media/meson/vdec/vdec_platform.c  |   37 +
 13 files changed, 1677 insertions(+), 99 deletions(-)
 create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.c
 create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.h

-- 
2.34.1

[PATCH v2 0/2] media: meson: vdec: add HEVC decode codec

[Christian Hewitt]

This mini-series adds support for HEVC decoding. It combines the original codec
work done by Maxime Jourdan in 2019 [0] and improvements by Benjamin Roszak in
2021 [1]. Only GXBB/GXL/GXM are enabled as decoding currently crashes on G12A
and later SoCs when trying to decode a 10-bit HEVC stream.

The goal of upstreaming the driver in its current state is to encourage greater
community contribution towards adding missing features, and fixing the bugs and
conformance issues necessary to get out of staging.

The HEVC codec presented here is generally partnered with FFMpeg sources that
are being maintained by the Raspberry Pi Foundation [2] and [3] that contain
numerous improvements to v4l2_m2m (and v4l2_request) support. There is active
work in progress to refine the changeset and send it upstream.

Christian

[0] https://github.com/Elyotna/linux/commits/4.20/v4l2-m2m-pr
[1] https://gitlab.com/benjamin545/linux-amlogic/-/commits/aml-hevc
[2] https://github.com/jc-kynesim/rpi-ffmpeg/commits/release/4.4/rpi_import_1
[3] https://github.com/jc-kynesim/rpi-ffmpeg/tree/dev/5.1.2/rpi_import_1

Changes from v1:
- Fix unused val warning reported by kernel test robot <lkp@intel.com>

Benjamin Roszak (1):
  media: meson: vdec: implement 10bit bitstream handling

Maxime Jourdan (1):
  media: meson: vdec: add HEVC decode codec

 drivers/staging/media/meson/vdec/Makefile     |    2 +-
 drivers/staging/media/meson/vdec/codec_h264.c |    3 +-
 drivers/staging/media/meson/vdec/codec_hevc.c | 1462 +++++++++++++++++
 drivers/staging/media/meson/vdec/codec_hevc.h |   13 +
 .../media/meson/vdec/codec_hevc_common.c      |  161 +-
 .../media/meson/vdec/codec_hevc_common.h      |    3 +-
 drivers/staging/media/meson/vdec/codec_vp9.c  |   35 +-
 drivers/staging/media/meson/vdec/esparser.c   |    4 +-
 drivers/staging/media/meson/vdec/hevc_regs.h  |    1 +
 drivers/staging/media/meson/vdec/vdec.h       |    1 +
 .../staging/media/meson/vdec/vdec_helpers.c   |   44 +-
 .../staging/media/meson/vdec/vdec_helpers.h   |   10 +-
 .../staging/media/meson/vdec/vdec_platform.c  |   37 +
 13 files changed, 1677 insertions(+), 99 deletions(-)
 create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.c
 create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.h

-- 
2.34.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 0/2] media: meson: vdec: add HEVC decode codec

[Christian Hewitt]

This mini-series adds support for HEVC decoding. It combines the original codec
work done by Maxime Jourdan in 2019 [0] and improvements by Benjamin Roszak in
2021 [1]. Only GXBB/GXL/GXM are enabled as decoding currently crashes on G12A
and later SoCs when trying to decode a 10-bit HEVC stream.

The goal of upstreaming the driver in its current state is to encourage greater
community contribution towards adding missing features, and fixing the bugs and
conformance issues necessary to get out of staging.

The HEVC codec presented here is generally partnered with FFMpeg sources that
are being maintained by the Raspberry Pi Foundation [2] and [3] that contain
numerous improvements to v4l2_m2m (and v4l2_request) support. There is active
work in progress to refine the changeset and send it upstream.

Christian

[0] https://github.com/Elyotna/linux/commits/4.20/v4l2-m2m-pr
[1] https://gitlab.com/benjamin545/linux-amlogic/-/commits/aml-hevc
[2] https://github.com/jc-kynesim/rpi-ffmpeg/commits/release/4.4/rpi_import_1
[3] https://github.com/jc-kynesim/rpi-ffmpeg/tree/dev/5.1.2/rpi_import_1

Changes from v1:
- Fix unused val warning reported by kernel test robot <lkp@intel.com>

Benjamin Roszak (1):
  media: meson: vdec: implement 10bit bitstream handling

Maxime Jourdan (1):
  media: meson: vdec: add HEVC decode codec

 drivers/staging/media/meson/vdec/Makefile     |    2 +-
 drivers/staging/media/meson/vdec/codec_h264.c |    3 +-
 drivers/staging/media/meson/vdec/codec_hevc.c | 1462 +++++++++++++++++
 drivers/staging/media/meson/vdec/codec_hevc.h |   13 +
 .../media/meson/vdec/codec_hevc_common.c      |  161 +-
 .../media/meson/vdec/codec_hevc_common.h      |    3 +-
 drivers/staging/media/meson/vdec/codec_vp9.c  |   35 +-
 drivers/staging/media/meson/vdec/esparser.c   |    4 +-
 drivers/staging/media/meson/vdec/hevc_regs.h  |    1 +
 drivers/staging/media/meson/vdec/vdec.h       |    1 +
 .../staging/media/meson/vdec/vdec_helpers.c   |   44 +-
 .../staging/media/meson/vdec/vdec_helpers.h   |   10 +-
 .../staging/media/meson/vdec/vdec_platform.c  |   37 +
 13 files changed, 1677 insertions(+), 99 deletions(-)
 create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.c
 create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.h

-- 
2.34.1


_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

[PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Christian Hewitt]

From: Benjamin Roszak <benjamin545@gmail.com>

In order to support 10bit bitstream decoding, buffers and MMU
handling must be cleaned up to support either downscale output
from compressed 10bit decoding to uncompressed 8bit NV12 output
or to compressed 10bit proprietary encoded frame format.

For that, "am21c" name is moved to "amfbc" to reflect the upstream
Amlogic Compressed framebuffer modifier naming.

Compressed frame buffers allocation is also cleaned up so it
can be shared with the HEVC decoder implementation.

Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
 drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
 .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
 .../media/meson/vdec/codec_hevc_common.h      |   3 +-
 drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
 drivers/staging/media/meson/vdec/esparser.c   |   1 +
 drivers/staging/media/meson/vdec/vdec.h       |   1 +
 .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
 .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
 8 files changed, 161 insertions(+), 97 deletions(-)

diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
index c61128fc4bb9..d53c9a464bde 100644
--- a/drivers/staging/media/meson/vdec/codec_h264.c
+++ b/drivers/staging/media/meson/vdec/codec_h264.c
@@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
 		frame_width, frame_height, crop_right, crop_bottom);
 
 	codec_h264_set_par(sess);
-	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
+	amvdec_src_change(sess, frame_width, frame_height,
+			  h264->max_refs + 5, 8);
 }
 
 /*
diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
index 0315cc0911cd..1c74b4837dcb 100644
--- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
+++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
@@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
 void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
 {
 	struct amvdec_core *core = sess->core;
-	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
-	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
+	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
+					 sess->pixfmt_cap, is_10bit);
+	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
+					       is_10bit, use_mmu);
+	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
 
 	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
 		/* Enable 2-plane reference read mode */
@@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
 		return;
 	}
 
+	/* enable mem saving mode for 8-bit */
+	if (!is_10bit)
+		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
+	else
+		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
+
 	if (codec_hevc_use_mmu(core->platform->revision,
 			       sess->pixfmt_cap, is_10bit))
 		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
+	else if (!is_10bit)
+		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
 	else
 		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
 
@@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
 
 		idx = vb->index;
 
-		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
+		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
 			buf_y_paddr = comm->fbc_buffer_paddr[idx];
 		else
 			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
@@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
 {
 	struct amvdec_core *core = sess->core;
 	struct v4l2_m2m_buffer *buf;
-	u32 revision = core->platform->revision;
 	u32 pixfmt_cap = sess->pixfmt_cap;
+	const u32 revision = core->platform->revision;
 	int i;
 
 	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
@@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
 		dma_addr_t buf_uv_paddr = 0;
 		u32 idx = vb->index;
 
-		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
-			buf_y_paddr = comm->mmu_header_paddr[idx];
-		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
-			buf_y_paddr = comm->fbc_buffer_paddr[idx];
-		else
+		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
+			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
+				buf_y_paddr = comm->mmu_header_paddr[idx];
+			else
+				buf_y_paddr = comm->fbc_buffer_paddr[idx];
+		} else {
 			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
+		}
 
 		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
 				 buf_y_paddr >> 5);
@@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
 		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
 }
 
-void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
+void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
 				 struct codec_hevc_common *comm)
 {
 	struct device *dev = sess->core->dev;
-	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
 	int i;
 
 	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
-		if (comm->fbc_buffer_vaddr[i]) {
-			dma_free_coherent(dev, am21_size,
-					  comm->fbc_buffer_vaddr[i],
-					  comm->fbc_buffer_paddr[i]);
-			comm->fbc_buffer_vaddr[i] = NULL;
+		if (comm->mmu_header_vaddr[i]) {
+			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
+					  comm->mmu_header_vaddr[i],
+					  comm->mmu_header_paddr[i]);
+			comm->mmu_header_vaddr[i] = NULL;
 		}
 	}
 }
-EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
+EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
 
-static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
+static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
 					struct codec_hevc_common *comm)
 {
 	struct device *dev = sess->core->dev;
 	struct v4l2_m2m_buffer *buf;
-	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
 
 	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
 		u32 idx = buf->vb.vb2_buf.index;
 		dma_addr_t paddr;
-		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
-						 GFP_KERNEL);
+		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
+						 &paddr, GFP_KERNEL);
 		if (!vaddr) {
-			codec_hevc_free_fbc_buffers(sess, comm);
+			codec_hevc_free_mmu_headers(sess, comm);
 			return -ENOMEM;
 		}
 
-		comm->fbc_buffer_vaddr[idx] = vaddr;
-		comm->fbc_buffer_paddr[idx] = paddr;
+		comm->mmu_header_vaddr[idx] = vaddr;
+		comm->mmu_header_paddr[idx] = paddr;
 	}
 
 	return 0;
 }
 
-void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
+void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
 				 struct codec_hevc_common *comm)
 {
 	struct device *dev = sess->core->dev;
+	u32 use_mmu;
+	u32 am21_size;
 	int i;
 
+	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
+				     sess->pixfmt_cap,
+				sess->bitdepth == 10 ? 1 : 0);
+
+	am21_size = amvdec_amfbc_size(sess->width, sess->height,
+				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
+
 	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
-		if (comm->mmu_header_vaddr[i]) {
-			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
-					  comm->mmu_header_vaddr[i],
-					  comm->mmu_header_paddr[i]);
-			comm->mmu_header_vaddr[i] = NULL;
+		if (comm->fbc_buffer_vaddr[i]) {
+			dma_free_coherent(dev, am21_size,
+					  comm->fbc_buffer_vaddr[i],
+					  comm->fbc_buffer_paddr[i]);
+			comm->fbc_buffer_vaddr[i] = NULL;
 		}
 	}
 
@@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
 				  comm->mmu_map_paddr);
 		comm->mmu_map_vaddr = NULL;
 	}
+
+	codec_hevc_free_mmu_headers(sess, comm);
 }
-EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
+EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
 
-static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
+static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
 					struct codec_hevc_common *comm)
 {
 	struct device *dev = sess->core->dev;
 	struct v4l2_m2m_buffer *buf;
+	u32 use_mmu;
+	u32 am21_size;
+	const u32 revision = sess->core->platform->revision;
+	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
+	int ret;
 
-	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
-						 &comm->mmu_map_paddr,
-						 GFP_KERNEL);
-	if (!comm->mmu_map_vaddr)
-		return -ENOMEM;
+	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
+				     is_10bit);
+
+	am21_size = amvdec_amfbc_size(sess->width, sess->height,
+				      is_10bit, use_mmu);
 
 	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
 		u32 idx = buf->vb.vb2_buf.index;
 		dma_addr_t paddr;
-		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
-						 &paddr, GFP_KERNEL);
+
+		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
+						 GFP_KERNEL);
 		if (!vaddr) {
-			codec_hevc_free_mmu_headers(sess, comm);
+			codec_hevc_free_fbc_buffers(sess, comm);
 			return -ENOMEM;
 		}
 
-		comm->mmu_header_vaddr[idx] = vaddr;
-		comm->mmu_header_paddr[idx] = paddr;
+		comm->fbc_buffer_vaddr[idx] = vaddr;
+		comm->fbc_buffer_paddr[idx] = paddr;
+	}
+
+	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
+	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
+		ret = codec_hevc_alloc_mmu_headers(sess, comm);
+		if (ret) {
+			codec_hevc_free_fbc_buffers(sess, comm);
+			return ret;
+		}
 	}
 
 	return 0;
@@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
 			     int is_10bit)
 {
 	struct amvdec_core *core = sess->core;
+	struct device *dev = core->dev;
 	int ret;
 
-	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
-		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
-		if (ret)
-			return ret;
+	if (codec_hevc_use_mmu(core->platform->revision,
+			       sess->pixfmt_cap, is_10bit)) {
+		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
+							 &comm->mmu_map_paddr,
+							 GFP_KERNEL);
+		if (!comm->mmu_map_vaddr)
+			return -ENOMEM;
 	}
 
 	if (codec_hevc_use_mmu(core->platform->revision,
-			       sess->pixfmt_cap, is_10bit)) {
-		ret = codec_hevc_alloc_mmu_headers(sess, comm);
-		if (ret) {
-			codec_hevc_free_fbc_buffers(sess, comm);
+			       sess->pixfmt_cap, is_10bit) ||
+	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
+		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
+		if (ret)
 			return ret;
-		}
 	}
 
 	if (core->platform->revision == VDEC_REVISION_GXBB)
@@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
 
 void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
 			     struct codec_hevc_common *comm,
-			     struct vb2_buffer *vb)
+			     struct vb2_buffer *vb,
+			     u32 is_10bit)
 {
-	u32 size = amvdec_am21c_size(sess->width, sess->height);
-	u32 nb_pages = size / PAGE_SIZE;
+	u32 use_mmu;
+	u32 size;
+	u32 nb_pages;
 	u32 *mmu_map = comm->mmu_map_vaddr;
 	u32 first_page;
 	u32 i;
 
-	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
-		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
-	else
-		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
+	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
+				     sess->pixfmt_cap, is_10bit);
+
+	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
+				 use_mmu);
 
+	nb_pages = size / PAGE_SIZE;
+	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
 	for (i = 0; i < nb_pages; ++i)
 		mmu_map[i] = first_page + i;
 }
diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
index cf072b8a9da2..13f9f1d90a94 100644
--- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
+++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
@@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
 
 void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
 			     struct codec_hevc_common *comm,
-			     struct vb2_buffer *vb);
+			     struct vb2_buffer *vb,
+			     u32 is_10bit);
 
 #endif
diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
index 394df5761556..8e3bbf0db4b3 100644
--- a/drivers/staging/media/meson/vdec/codec_vp9.c
+++ b/drivers/staging/media/meson/vdec/codec_vp9.c
@@ -458,12 +458,6 @@ struct codec_vp9 {
 	struct list_head ref_frames_list;
 	u32 frames_num;
 
-	/* In case of downsampling (decoding with FBC but outputting in NV12M),
-	 * we need to allocate additional buffers for FBC.
-	 */
-	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
-	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
-
 	int ref_frame_map[REF_FRAMES];
 	int next_ref_frame_map[REF_FRAMES];
 	struct vp9_frame *frame_refs[REFS_PER_FRAME];
@@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
 		buf_y_paddr =
 		       vb2_dma_contig_plane_dma_addr(vb, 0);
 
-	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
-		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
-		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
+	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
 		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
-	}
 
 	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
 		buf_y_paddr =
@@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
 
 	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
 			       vp9->is_10bit)) {
-		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
-				 vp9->common.mmu_header_paddr[vb->index]);
+		dma_addr_t header_adr;
+
+		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
+			header_adr = vp9->common.mmu_header_paddr[vb->index];
+		else
+			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
+		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
 		/* use HEVC_CM_HEADER_START_ADDR */
 		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
 	}
@@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
 {
 	struct amvdec_core *core = sess->core;
 	u32 scale = 0;
+	u32 use_mmu;
 	u32 sz;
 	int i;
 
+	use_mmu = codec_hevc_use_mmu(core->platform->revision,
+				     sess->pixfmt_cap, vp9->is_10bit);
+
 	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
 	codec_vp9_set_refs(sess, vp9);
 	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
@@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
 		    vp9->frame_refs[i]->height != vp9->height)
 			scale = 1;
 
-		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
-					    vp9->frame_refs[i]->height);
+		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
+					    vp9->frame_refs[i]->height,
+					    vp9->is_10bit, use_mmu);
 
 		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
 				 vp9->frame_refs[i]->width);
@@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
 	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
 			       vp9->is_10bit))
 		codec_hevc_fill_mmu_map(sess, &vp9->common,
-					&vp9->cur_frame->vbuf->vb2_buf);
+					&vp9->cur_frame->vbuf->vb2_buf,
+					vp9->is_10bit);
 
 	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
 
@@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
 
 	codec_vp9_fetch_rpm(sess);
 	if (codec_vp9_process_rpm(vp9)) {
-		amvdec_src_change(sess, vp9->width, vp9->height, 16);
+		amvdec_src_change(sess, vp9->width, vp9->height, 16,
+				  vp9->is_10bit ? 10 : 8);
 
 		/* No frame is actually processed */
 		vp9->cur_frame = NULL;
diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
index 1904d58875ad..3cd29ab4f979 100644
--- a/drivers/staging/media/meson/vdec/esparser.c
+++ b/drivers/staging/media/meson/vdec/esparser.c
@@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
 		if (esparser_vififo_get_free_space(sess) < payload_size ||
 		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
 			return -EAGAIN;
+
 	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
 		return -EAGAIN;
 	}
diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
index 0906b8fb5cc6..a48170fe4cff 100644
--- a/drivers/staging/media/meson/vdec/vdec.h
+++ b/drivers/staging/media/meson/vdec/vdec.h
@@ -244,6 +244,7 @@ struct amvdec_session {
 	u32 width;
 	u32 height;
 	u32 colorspace;
+	u32 bitdepth;
 	u8 ycbcr_enc;
 	u8 quantization;
 	u8 xfer_func;
diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
index 7d2a75653250..fef76142f0c5 100644
--- a/drivers/staging/media/meson/vdec/vdec_helpers.c
+++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
@@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
 }
 EXPORT_SYMBOL_GPL(amvdec_write_parser);
 
-/* 4 KiB per 64x32 block */
-u32 amvdec_am21c_body_size(u32 width, u32 height)
+/* AMFBC body is made out of 64x32 blocks with varying block size */
+u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
 {
 	u32 width_64 = ALIGN(width, 64) / 64;
 	u32 height_32 = ALIGN(height, 32) / 32;
+	u32 blk_size = 4096;
 
-	return SZ_4K * width_64 * height_32;
+	if (!is_10bit) {
+		if (use_mmu)
+			blk_size = 3200;
+		else
+			blk_size = 3072;
+	}
+
+	return blk_size * width_64 * height_32;
 }
-EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
+EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
 
 /* 32 bytes per 128x64 block */
-u32 amvdec_am21c_head_size(u32 width, u32 height)
+u32 amvdec_amfbc_head_size(u32 width, u32 height)
 {
 	u32 width_128 = ALIGN(width, 128) / 128;
 	u32 height_64 = ALIGN(height, 64) / 64;
 
 	return 32 * width_128 * height_64;
 }
-EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
+EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
 
-u32 amvdec_am21c_size(u32 width, u32 height)
+u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
 {
-	return ALIGN(amvdec_am21c_body_size(width, height) +
-		     amvdec_am21c_head_size(width, height), SZ_64K);
+	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
+		     amvdec_amfbc_head_size(width, height), SZ_64K);
 }
-EXPORT_SYMBOL_GPL(amvdec_am21c_size);
+EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
 
 static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
 {
@@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
 EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
 
 void amvdec_src_change(struct amvdec_session *sess, u32 width,
-		       u32 height, u32 dpb_size)
+		       u32 height, u32 dpb_size, u32 bitdepth)
 {
 	static const struct v4l2_event ev = {
 		.type = V4L2_EVENT_SOURCE_CHANGE,
@@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
 
 	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
 
+	sess->bitdepth = bitdepth;
+
 	/*
 	 * Check if the capture queue is already configured well for our
-	 * usecase. If so, keep decoding with it and do not send the event
+	 * usecase. If so, keep decoding with it.
 	 */
 	if (sess->streamon_cap &&
 	    sess->width == width &&
 	    sess->height == height &&
 	    dpb_size <= sess->num_dst_bufs) {
 		sess->fmt_out->codec_ops->resume(sess);
-		return;
+	} else {
+		sess->status = STATUS_NEEDS_RESUME;
+		sess->changed_format = 0;
 	}
 
-	sess->changed_format = 0;
 	sess->width = width;
 	sess->height = height;
-	sess->status = STATUS_NEEDS_RESUME;
 
-	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
-		width, height, dpb_size);
+	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
+		width, height, dpb_size, bitdepth);
 	v4l2_event_queue_fh(&sess->fh, &ev);
 }
 EXPORT_SYMBOL_GPL(amvdec_src_change);
diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
index 4bf3e61d081b..1a711679d26a 100644
--- a/drivers/staging/media/meson/vdec/vdec_helpers.h
+++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
@@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
 u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
 void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
 
-u32 amvdec_am21c_body_size(u32 width, u32 height);
-u32 amvdec_am21c_head_size(u32 width, u32 height);
-u32 amvdec_am21c_size(u32 width, u32 height);
+/* Helpers for the Amlogic compressed framebuffer format */
+u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
+u32 amvdec_amfbc_head_size(u32 width, u32 height);
+u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
 
 /**
  * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
@@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
  * @width: picture width detected by the hardware
  * @height: picture height detected by the hardware
  * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
+ * @bitdepth: Bit depth (usually 10 or 8) of the coded content
  */
 void amvdec_src_change(struct amvdec_session *sess, u32 width,
-		       u32 height, u32 dpb_size);
+		       u32 height, u32 dpb_size, u32 bitdepth);
 
 /**
  * amvdec_abort() - Abort the current decoding session
-- 
2.34.1

[PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Christian Hewitt]

From: Benjamin Roszak <benjamin545@gmail.com>

In order to support 10bit bitstream decoding, buffers and MMU
handling must be cleaned up to support either downscale output
from compressed 10bit decoding to uncompressed 8bit NV12 output
or to compressed 10bit proprietary encoded frame format.

For that, "am21c" name is moved to "amfbc" to reflect the upstream
Amlogic Compressed framebuffer modifier naming.

Compressed frame buffers allocation is also cleaned up so it
can be shared with the HEVC decoder implementation.

Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
 drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
 .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
 .../media/meson/vdec/codec_hevc_common.h      |   3 +-
 drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
 drivers/staging/media/meson/vdec/esparser.c   |   1 +
 drivers/staging/media/meson/vdec/vdec.h       |   1 +
 .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
 .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
 8 files changed, 161 insertions(+), 97 deletions(-)

diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
index c61128fc4bb9..d53c9a464bde 100644
--- a/drivers/staging/media/meson/vdec/codec_h264.c
+++ b/drivers/staging/media/meson/vdec/codec_h264.c
@@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
 		frame_width, frame_height, crop_right, crop_bottom);
 
 	codec_h264_set_par(sess);
-	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
+	amvdec_src_change(sess, frame_width, frame_height,
+			  h264->max_refs + 5, 8);
 }
 
 /*
diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
index 0315cc0911cd..1c74b4837dcb 100644
--- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
+++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
@@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
 void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
 {
 	struct amvdec_core *core = sess->core;
-	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
-	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
+	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
+					 sess->pixfmt_cap, is_10bit);
+	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
+					       is_10bit, use_mmu);
+	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
 
 	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
 		/* Enable 2-plane reference read mode */
@@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
 		return;
 	}
 
+	/* enable mem saving mode for 8-bit */
+	if (!is_10bit)
+		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
+	else
+		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
+
 	if (codec_hevc_use_mmu(core->platform->revision,
 			       sess->pixfmt_cap, is_10bit))
 		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
+	else if (!is_10bit)
+		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
 	else
 		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
 
@@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
 
 		idx = vb->index;
 
-		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
+		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
 			buf_y_paddr = comm->fbc_buffer_paddr[idx];
 		else
 			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
@@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
 {
 	struct amvdec_core *core = sess->core;
 	struct v4l2_m2m_buffer *buf;
-	u32 revision = core->platform->revision;
 	u32 pixfmt_cap = sess->pixfmt_cap;
+	const u32 revision = core->platform->revision;
 	int i;
 
 	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
@@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
 		dma_addr_t buf_uv_paddr = 0;
 		u32 idx = vb->index;
 
-		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
-			buf_y_paddr = comm->mmu_header_paddr[idx];
-		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
-			buf_y_paddr = comm->fbc_buffer_paddr[idx];
-		else
+		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
+			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
+				buf_y_paddr = comm->mmu_header_paddr[idx];
+			else
+				buf_y_paddr = comm->fbc_buffer_paddr[idx];
+		} else {
 			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
+		}
 
 		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
 				 buf_y_paddr >> 5);
@@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
 		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
 }
 
-void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
+void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
 				 struct codec_hevc_common *comm)
 {
 	struct device *dev = sess->core->dev;
-	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
 	int i;
 
 	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
-		if (comm->fbc_buffer_vaddr[i]) {
-			dma_free_coherent(dev, am21_size,
-					  comm->fbc_buffer_vaddr[i],
-					  comm->fbc_buffer_paddr[i]);
-			comm->fbc_buffer_vaddr[i] = NULL;
+		if (comm->mmu_header_vaddr[i]) {
+			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
+					  comm->mmu_header_vaddr[i],
+					  comm->mmu_header_paddr[i]);
+			comm->mmu_header_vaddr[i] = NULL;
 		}
 	}
 }
-EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
+EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
 
-static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
+static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
 					struct codec_hevc_common *comm)
 {
 	struct device *dev = sess->core->dev;
 	struct v4l2_m2m_buffer *buf;
-	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
 
 	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
 		u32 idx = buf->vb.vb2_buf.index;
 		dma_addr_t paddr;
-		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
-						 GFP_KERNEL);
+		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
+						 &paddr, GFP_KERNEL);
 		if (!vaddr) {
-			codec_hevc_free_fbc_buffers(sess, comm);
+			codec_hevc_free_mmu_headers(sess, comm);
 			return -ENOMEM;
 		}
 
-		comm->fbc_buffer_vaddr[idx] = vaddr;
-		comm->fbc_buffer_paddr[idx] = paddr;
+		comm->mmu_header_vaddr[idx] = vaddr;
+		comm->mmu_header_paddr[idx] = paddr;
 	}
 
 	return 0;
 }
 
-void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
+void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
 				 struct codec_hevc_common *comm)
 {
 	struct device *dev = sess->core->dev;
+	u32 use_mmu;
+	u32 am21_size;
 	int i;
 
+	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
+				     sess->pixfmt_cap,
+				sess->bitdepth == 10 ? 1 : 0);
+
+	am21_size = amvdec_amfbc_size(sess->width, sess->height,
+				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
+
 	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
-		if (comm->mmu_header_vaddr[i]) {
-			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
-					  comm->mmu_header_vaddr[i],
-					  comm->mmu_header_paddr[i]);
-			comm->mmu_header_vaddr[i] = NULL;
+		if (comm->fbc_buffer_vaddr[i]) {
+			dma_free_coherent(dev, am21_size,
+					  comm->fbc_buffer_vaddr[i],
+					  comm->fbc_buffer_paddr[i]);
+			comm->fbc_buffer_vaddr[i] = NULL;
 		}
 	}
 
@@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
 				  comm->mmu_map_paddr);
 		comm->mmu_map_vaddr = NULL;
 	}
+
+	codec_hevc_free_mmu_headers(sess, comm);
 }
-EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
+EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
 
-static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
+static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
 					struct codec_hevc_common *comm)
 {
 	struct device *dev = sess->core->dev;
 	struct v4l2_m2m_buffer *buf;
+	u32 use_mmu;
+	u32 am21_size;
+	const u32 revision = sess->core->platform->revision;
+	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
+	int ret;
 
-	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
-						 &comm->mmu_map_paddr,
-						 GFP_KERNEL);
-	if (!comm->mmu_map_vaddr)
-		return -ENOMEM;
+	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
+				     is_10bit);
+
+	am21_size = amvdec_amfbc_size(sess->width, sess->height,
+				      is_10bit, use_mmu);
 
 	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
 		u32 idx = buf->vb.vb2_buf.index;
 		dma_addr_t paddr;
-		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
-						 &paddr, GFP_KERNEL);
+
+		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
+						 GFP_KERNEL);
 		if (!vaddr) {
-			codec_hevc_free_mmu_headers(sess, comm);
+			codec_hevc_free_fbc_buffers(sess, comm);
 			return -ENOMEM;
 		}
 
-		comm->mmu_header_vaddr[idx] = vaddr;
-		comm->mmu_header_paddr[idx] = paddr;
+		comm->fbc_buffer_vaddr[idx] = vaddr;
+		comm->fbc_buffer_paddr[idx] = paddr;
+	}
+
+	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
+	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
+		ret = codec_hevc_alloc_mmu_headers(sess, comm);
+		if (ret) {
+			codec_hevc_free_fbc_buffers(sess, comm);
+			return ret;
+		}
 	}
 
 	return 0;
@@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
 			     int is_10bit)
 {
 	struct amvdec_core *core = sess->core;
+	struct device *dev = core->dev;
 	int ret;
 
-	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
-		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
-		if (ret)
-			return ret;
+	if (codec_hevc_use_mmu(core->platform->revision,
+			       sess->pixfmt_cap, is_10bit)) {
+		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
+							 &comm->mmu_map_paddr,
+							 GFP_KERNEL);
+		if (!comm->mmu_map_vaddr)
+			return -ENOMEM;
 	}
 
 	if (codec_hevc_use_mmu(core->platform->revision,
-			       sess->pixfmt_cap, is_10bit)) {
-		ret = codec_hevc_alloc_mmu_headers(sess, comm);
-		if (ret) {
-			codec_hevc_free_fbc_buffers(sess, comm);
+			       sess->pixfmt_cap, is_10bit) ||
+	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
+		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
+		if (ret)
 			return ret;
-		}
 	}
 
 	if (core->platform->revision == VDEC_REVISION_GXBB)
@@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
 
 void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
 			     struct codec_hevc_common *comm,
-			     struct vb2_buffer *vb)
+			     struct vb2_buffer *vb,
+			     u32 is_10bit)
 {
-	u32 size = amvdec_am21c_size(sess->width, sess->height);
-	u32 nb_pages = size / PAGE_SIZE;
+	u32 use_mmu;
+	u32 size;
+	u32 nb_pages;
 	u32 *mmu_map = comm->mmu_map_vaddr;
 	u32 first_page;
 	u32 i;
 
-	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
-		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
-	else
-		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
+	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
+				     sess->pixfmt_cap, is_10bit);
+
+	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
+				 use_mmu);
 
+	nb_pages = size / PAGE_SIZE;
+	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
 	for (i = 0; i < nb_pages; ++i)
 		mmu_map[i] = first_page + i;
 }
diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
index cf072b8a9da2..13f9f1d90a94 100644
--- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
+++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
@@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
 
 void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
 			     struct codec_hevc_common *comm,
-			     struct vb2_buffer *vb);
+			     struct vb2_buffer *vb,
+			     u32 is_10bit);
 
 #endif
diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
index 394df5761556..8e3bbf0db4b3 100644
--- a/drivers/staging/media/meson/vdec/codec_vp9.c
+++ b/drivers/staging/media/meson/vdec/codec_vp9.c
@@ -458,12 +458,6 @@ struct codec_vp9 {
 	struct list_head ref_frames_list;
 	u32 frames_num;
 
-	/* In case of downsampling (decoding with FBC but outputting in NV12M),
-	 * we need to allocate additional buffers for FBC.
-	 */
-	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
-	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
-
 	int ref_frame_map[REF_FRAMES];
 	int next_ref_frame_map[REF_FRAMES];
 	struct vp9_frame *frame_refs[REFS_PER_FRAME];
@@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
 		buf_y_paddr =
 		       vb2_dma_contig_plane_dma_addr(vb, 0);
 
-	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
-		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
-		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
+	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
 		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
-	}
 
 	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
 		buf_y_paddr =
@@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
 
 	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
 			       vp9->is_10bit)) {
-		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
-				 vp9->common.mmu_header_paddr[vb->index]);
+		dma_addr_t header_adr;
+
+		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
+			header_adr = vp9->common.mmu_header_paddr[vb->index];
+		else
+			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
+		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
 		/* use HEVC_CM_HEADER_START_ADDR */
 		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
 	}
@@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
 {
 	struct amvdec_core *core = sess->core;
 	u32 scale = 0;
+	u32 use_mmu;
 	u32 sz;
 	int i;
 
+	use_mmu = codec_hevc_use_mmu(core->platform->revision,
+				     sess->pixfmt_cap, vp9->is_10bit);
+
 	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
 	codec_vp9_set_refs(sess, vp9);
 	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
@@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
 		    vp9->frame_refs[i]->height != vp9->height)
 			scale = 1;
 
-		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
-					    vp9->frame_refs[i]->height);
+		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
+					    vp9->frame_refs[i]->height,
+					    vp9->is_10bit, use_mmu);
 
 		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
 				 vp9->frame_refs[i]->width);
@@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
 	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
 			       vp9->is_10bit))
 		codec_hevc_fill_mmu_map(sess, &vp9->common,
-					&vp9->cur_frame->vbuf->vb2_buf);
+					&vp9->cur_frame->vbuf->vb2_buf,
+					vp9->is_10bit);
 
 	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
 
@@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
 
 	codec_vp9_fetch_rpm(sess);
 	if (codec_vp9_process_rpm(vp9)) {
-		amvdec_src_change(sess, vp9->width, vp9->height, 16);
+		amvdec_src_change(sess, vp9->width, vp9->height, 16,
+				  vp9->is_10bit ? 10 : 8);
 
 		/* No frame is actually processed */
 		vp9->cur_frame = NULL;
diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
index 1904d58875ad..3cd29ab4f979 100644
--- a/drivers/staging/media/meson/vdec/esparser.c
+++ b/drivers/staging/media/meson/vdec/esparser.c
@@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
 		if (esparser_vififo_get_free_space(sess) < payload_size ||
 		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
 			return -EAGAIN;
+
 	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
 		return -EAGAIN;
 	}
diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
index 0906b8fb5cc6..a48170fe4cff 100644
--- a/drivers/staging/media/meson/vdec/vdec.h
+++ b/drivers/staging/media/meson/vdec/vdec.h
@@ -244,6 +244,7 @@ struct amvdec_session {
 	u32 width;
 	u32 height;
 	u32 colorspace;
+	u32 bitdepth;
 	u8 ycbcr_enc;
 	u8 quantization;
 	u8 xfer_func;
diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
index 7d2a75653250..fef76142f0c5 100644
--- a/drivers/staging/media/meson/vdec/vdec_helpers.c
+++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
@@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
 }
 EXPORT_SYMBOL_GPL(amvdec_write_parser);
 
-/* 4 KiB per 64x32 block */
-u32 amvdec_am21c_body_size(u32 width, u32 height)
+/* AMFBC body is made out of 64x32 blocks with varying block size */
+u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
 {
 	u32 width_64 = ALIGN(width, 64) / 64;
 	u32 height_32 = ALIGN(height, 32) / 32;
+	u32 blk_size = 4096;
 
-	return SZ_4K * width_64 * height_32;
+	if (!is_10bit) {
+		if (use_mmu)
+			blk_size = 3200;
+		else
+			blk_size = 3072;
+	}
+
+	return blk_size * width_64 * height_32;
 }
-EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
+EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
 
 /* 32 bytes per 128x64 block */
-u32 amvdec_am21c_head_size(u32 width, u32 height)
+u32 amvdec_amfbc_head_size(u32 width, u32 height)
 {
 	u32 width_128 = ALIGN(width, 128) / 128;
 	u32 height_64 = ALIGN(height, 64) / 64;
 
 	return 32 * width_128 * height_64;
 }
-EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
+EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
 
-u32 amvdec_am21c_size(u32 width, u32 height)
+u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
 {
-	return ALIGN(amvdec_am21c_body_size(width, height) +
-		     amvdec_am21c_head_size(width, height), SZ_64K);
+	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
+		     amvdec_amfbc_head_size(width, height), SZ_64K);
 }
-EXPORT_SYMBOL_GPL(amvdec_am21c_size);
+EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
 
 static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
 {
@@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
 EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
 
 void amvdec_src_change(struct amvdec_session *sess, u32 width,
-		       u32 height, u32 dpb_size)
+		       u32 height, u32 dpb_size, u32 bitdepth)
 {
 	static const struct v4l2_event ev = {
 		.type = V4L2_EVENT_SOURCE_CHANGE,
@@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
 
 	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
 
+	sess->bitdepth = bitdepth;
+
 	/*
 	 * Check if the capture queue is already configured well for our
-	 * usecase. If so, keep decoding with it and do not send the event
+	 * usecase. If so, keep decoding with it.
 	 */
 	if (sess->streamon_cap &&
 	    sess->width == width &&
 	    sess->height == height &&
 	    dpb_size <= sess->num_dst_bufs) {
 		sess->fmt_out->codec_ops->resume(sess);
-		return;
+	} else {
+		sess->status = STATUS_NEEDS_RESUME;
+		sess->changed_format = 0;
 	}
 
-	sess->changed_format = 0;
 	sess->width = width;
 	sess->height = height;
-	sess->status = STATUS_NEEDS_RESUME;
 
-	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
-		width, height, dpb_size);
+	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
+		width, height, dpb_size, bitdepth);
 	v4l2_event_queue_fh(&sess->fh, &ev);
 }
 EXPORT_SYMBOL_GPL(amvdec_src_change);
diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
index 4bf3e61d081b..1a711679d26a 100644
--- a/drivers/staging/media/meson/vdec/vdec_helpers.h
+++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
@@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
 u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
 void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
 
-u32 amvdec_am21c_body_size(u32 width, u32 height);
-u32 amvdec_am21c_head_size(u32 width, u32 height);
-u32 amvdec_am21c_size(u32 width, u32 height);
+/* Helpers for the Amlogic compressed framebuffer format */
+u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
+u32 amvdec_amfbc_head_size(u32 width, u32 height);
+u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
 
 /**
  * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
@@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
  * @width: picture width detected by the hardware
  * @height: picture height detected by the hardware
  * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
+ * @bitdepth: Bit depth (usually 10 or 8) of the coded content
  */
 void amvdec_src_change(struct amvdec_session *sess, u32 width,
-		       u32 height, u32 dpb_size);
+		       u32 height, u32 dpb_size, u32 bitdepth);
 
 /**
  * amvdec_abort() - Abort the current decoding session
-- 
2.34.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Christian Hewitt]

From: Benjamin Roszak <benjamin545@gmail.com>

In order to support 10bit bitstream decoding, buffers and MMU
handling must be cleaned up to support either downscale output
from compressed 10bit decoding to uncompressed 8bit NV12 output
or to compressed 10bit proprietary encoded frame format.

For that, "am21c" name is moved to "amfbc" to reflect the upstream
Amlogic Compressed framebuffer modifier naming.

Compressed frame buffers allocation is also cleaned up so it
can be shared with the HEVC decoder implementation.

Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
 drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
 .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
 .../media/meson/vdec/codec_hevc_common.h      |   3 +-
 drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
 drivers/staging/media/meson/vdec/esparser.c   |   1 +
 drivers/staging/media/meson/vdec/vdec.h       |   1 +
 .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
 .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
 8 files changed, 161 insertions(+), 97 deletions(-)

diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
index c61128fc4bb9..d53c9a464bde 100644
--- a/drivers/staging/media/meson/vdec/codec_h264.c
+++ b/drivers/staging/media/meson/vdec/codec_h264.c
@@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
 		frame_width, frame_height, crop_right, crop_bottom);
 
 	codec_h264_set_par(sess);
-	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
+	amvdec_src_change(sess, frame_width, frame_height,
+			  h264->max_refs + 5, 8);
 }
 
 /*
diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
index 0315cc0911cd..1c74b4837dcb 100644
--- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
+++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
@@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
 void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
 {
 	struct amvdec_core *core = sess->core;
-	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
-	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
+	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
+					 sess->pixfmt_cap, is_10bit);
+	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
+					       is_10bit, use_mmu);
+	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
 
 	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
 		/* Enable 2-plane reference read mode */
@@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
 		return;
 	}
 
+	/* enable mem saving mode for 8-bit */
+	if (!is_10bit)
+		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
+	else
+		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
+
 	if (codec_hevc_use_mmu(core->platform->revision,
 			       sess->pixfmt_cap, is_10bit))
 		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
+	else if (!is_10bit)
+		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
 	else
 		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
 
@@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
 
 		idx = vb->index;
 
-		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
+		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
 			buf_y_paddr = comm->fbc_buffer_paddr[idx];
 		else
 			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
@@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
 {
 	struct amvdec_core *core = sess->core;
 	struct v4l2_m2m_buffer *buf;
-	u32 revision = core->platform->revision;
 	u32 pixfmt_cap = sess->pixfmt_cap;
+	const u32 revision = core->platform->revision;
 	int i;
 
 	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
@@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
 		dma_addr_t buf_uv_paddr = 0;
 		u32 idx = vb->index;
 
-		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
-			buf_y_paddr = comm->mmu_header_paddr[idx];
-		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
-			buf_y_paddr = comm->fbc_buffer_paddr[idx];
-		else
+		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
+			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
+				buf_y_paddr = comm->mmu_header_paddr[idx];
+			else
+				buf_y_paddr = comm->fbc_buffer_paddr[idx];
+		} else {
 			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
+		}
 
 		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
 				 buf_y_paddr >> 5);
@@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
 		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
 }
 
-void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
+void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
 				 struct codec_hevc_common *comm)
 {
 	struct device *dev = sess->core->dev;
-	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
 	int i;
 
 	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
-		if (comm->fbc_buffer_vaddr[i]) {
-			dma_free_coherent(dev, am21_size,
-					  comm->fbc_buffer_vaddr[i],
-					  comm->fbc_buffer_paddr[i]);
-			comm->fbc_buffer_vaddr[i] = NULL;
+		if (comm->mmu_header_vaddr[i]) {
+			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
+					  comm->mmu_header_vaddr[i],
+					  comm->mmu_header_paddr[i]);
+			comm->mmu_header_vaddr[i] = NULL;
 		}
 	}
 }
-EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
+EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
 
-static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
+static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
 					struct codec_hevc_common *comm)
 {
 	struct device *dev = sess->core->dev;
 	struct v4l2_m2m_buffer *buf;
-	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
 
 	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
 		u32 idx = buf->vb.vb2_buf.index;
 		dma_addr_t paddr;
-		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
-						 GFP_KERNEL);
+		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
+						 &paddr, GFP_KERNEL);
 		if (!vaddr) {
-			codec_hevc_free_fbc_buffers(sess, comm);
+			codec_hevc_free_mmu_headers(sess, comm);
 			return -ENOMEM;
 		}
 
-		comm->fbc_buffer_vaddr[idx] = vaddr;
-		comm->fbc_buffer_paddr[idx] = paddr;
+		comm->mmu_header_vaddr[idx] = vaddr;
+		comm->mmu_header_paddr[idx] = paddr;
 	}
 
 	return 0;
 }
 
-void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
+void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
 				 struct codec_hevc_common *comm)
 {
 	struct device *dev = sess->core->dev;
+	u32 use_mmu;
+	u32 am21_size;
 	int i;
 
+	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
+				     sess->pixfmt_cap,
+				sess->bitdepth == 10 ? 1 : 0);
+
+	am21_size = amvdec_amfbc_size(sess->width, sess->height,
+				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
+
 	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
-		if (comm->mmu_header_vaddr[i]) {
-			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
-					  comm->mmu_header_vaddr[i],
-					  comm->mmu_header_paddr[i]);
-			comm->mmu_header_vaddr[i] = NULL;
+		if (comm->fbc_buffer_vaddr[i]) {
+			dma_free_coherent(dev, am21_size,
+					  comm->fbc_buffer_vaddr[i],
+					  comm->fbc_buffer_paddr[i]);
+			comm->fbc_buffer_vaddr[i] = NULL;
 		}
 	}
 
@@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
 				  comm->mmu_map_paddr);
 		comm->mmu_map_vaddr = NULL;
 	}
+
+	codec_hevc_free_mmu_headers(sess, comm);
 }
-EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
+EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
 
-static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
+static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
 					struct codec_hevc_common *comm)
 {
 	struct device *dev = sess->core->dev;
 	struct v4l2_m2m_buffer *buf;
+	u32 use_mmu;
+	u32 am21_size;
+	const u32 revision = sess->core->platform->revision;
+	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
+	int ret;
 
-	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
-						 &comm->mmu_map_paddr,
-						 GFP_KERNEL);
-	if (!comm->mmu_map_vaddr)
-		return -ENOMEM;
+	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
+				     is_10bit);
+
+	am21_size = amvdec_amfbc_size(sess->width, sess->height,
+				      is_10bit, use_mmu);
 
 	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
 		u32 idx = buf->vb.vb2_buf.index;
 		dma_addr_t paddr;
-		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
-						 &paddr, GFP_KERNEL);
+
+		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
+						 GFP_KERNEL);
 		if (!vaddr) {
-			codec_hevc_free_mmu_headers(sess, comm);
+			codec_hevc_free_fbc_buffers(sess, comm);
 			return -ENOMEM;
 		}
 
-		comm->mmu_header_vaddr[idx] = vaddr;
-		comm->mmu_header_paddr[idx] = paddr;
+		comm->fbc_buffer_vaddr[idx] = vaddr;
+		comm->fbc_buffer_paddr[idx] = paddr;
+	}
+
+	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
+	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
+		ret = codec_hevc_alloc_mmu_headers(sess, comm);
+		if (ret) {
+			codec_hevc_free_fbc_buffers(sess, comm);
+			return ret;
+		}
 	}
 
 	return 0;
@@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
 			     int is_10bit)
 {
 	struct amvdec_core *core = sess->core;
+	struct device *dev = core->dev;
 	int ret;
 
-	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
-		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
-		if (ret)
-			return ret;
+	if (codec_hevc_use_mmu(core->platform->revision,
+			       sess->pixfmt_cap, is_10bit)) {
+		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
+							 &comm->mmu_map_paddr,
+							 GFP_KERNEL);
+		if (!comm->mmu_map_vaddr)
+			return -ENOMEM;
 	}
 
 	if (codec_hevc_use_mmu(core->platform->revision,
-			       sess->pixfmt_cap, is_10bit)) {
-		ret = codec_hevc_alloc_mmu_headers(sess, comm);
-		if (ret) {
-			codec_hevc_free_fbc_buffers(sess, comm);
+			       sess->pixfmt_cap, is_10bit) ||
+	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
+		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
+		if (ret)
 			return ret;
-		}
 	}
 
 	if (core->platform->revision == VDEC_REVISION_GXBB)
@@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
 
 void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
 			     struct codec_hevc_common *comm,
-			     struct vb2_buffer *vb)
+			     struct vb2_buffer *vb,
+			     u32 is_10bit)
 {
-	u32 size = amvdec_am21c_size(sess->width, sess->height);
-	u32 nb_pages = size / PAGE_SIZE;
+	u32 use_mmu;
+	u32 size;
+	u32 nb_pages;
 	u32 *mmu_map = comm->mmu_map_vaddr;
 	u32 first_page;
 	u32 i;
 
-	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
-		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
-	else
-		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
+	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
+				     sess->pixfmt_cap, is_10bit);
+
+	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
+				 use_mmu);
 
+	nb_pages = size / PAGE_SIZE;
+	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
 	for (i = 0; i < nb_pages; ++i)
 		mmu_map[i] = first_page + i;
 }
diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
index cf072b8a9da2..13f9f1d90a94 100644
--- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
+++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
@@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
 
 void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
 			     struct codec_hevc_common *comm,
-			     struct vb2_buffer *vb);
+			     struct vb2_buffer *vb,
+			     u32 is_10bit);
 
 #endif
diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
index 394df5761556..8e3bbf0db4b3 100644
--- a/drivers/staging/media/meson/vdec/codec_vp9.c
+++ b/drivers/staging/media/meson/vdec/codec_vp9.c
@@ -458,12 +458,6 @@ struct codec_vp9 {
 	struct list_head ref_frames_list;
 	u32 frames_num;
 
-	/* In case of downsampling (decoding with FBC but outputting in NV12M),
-	 * we need to allocate additional buffers for FBC.
-	 */
-	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
-	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
-
 	int ref_frame_map[REF_FRAMES];
 	int next_ref_frame_map[REF_FRAMES];
 	struct vp9_frame *frame_refs[REFS_PER_FRAME];
@@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
 		buf_y_paddr =
 		       vb2_dma_contig_plane_dma_addr(vb, 0);
 
-	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
-		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
-		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
+	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
 		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
-	}
 
 	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
 		buf_y_paddr =
@@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
 
 	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
 			       vp9->is_10bit)) {
-		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
-				 vp9->common.mmu_header_paddr[vb->index]);
+		dma_addr_t header_adr;
+
+		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
+			header_adr = vp9->common.mmu_header_paddr[vb->index];
+		else
+			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
+		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
 		/* use HEVC_CM_HEADER_START_ADDR */
 		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
 	}
@@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
 {
 	struct amvdec_core *core = sess->core;
 	u32 scale = 0;
+	u32 use_mmu;
 	u32 sz;
 	int i;
 
+	use_mmu = codec_hevc_use_mmu(core->platform->revision,
+				     sess->pixfmt_cap, vp9->is_10bit);
+
 	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
 	codec_vp9_set_refs(sess, vp9);
 	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
@@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
 		    vp9->frame_refs[i]->height != vp9->height)
 			scale = 1;
 
-		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
-					    vp9->frame_refs[i]->height);
+		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
+					    vp9->frame_refs[i]->height,
+					    vp9->is_10bit, use_mmu);
 
 		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
 				 vp9->frame_refs[i]->width);
@@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
 	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
 			       vp9->is_10bit))
 		codec_hevc_fill_mmu_map(sess, &vp9->common,
-					&vp9->cur_frame->vbuf->vb2_buf);
+					&vp9->cur_frame->vbuf->vb2_buf,
+					vp9->is_10bit);
 
 	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
 
@@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
 
 	codec_vp9_fetch_rpm(sess);
 	if (codec_vp9_process_rpm(vp9)) {
-		amvdec_src_change(sess, vp9->width, vp9->height, 16);
+		amvdec_src_change(sess, vp9->width, vp9->height, 16,
+				  vp9->is_10bit ? 10 : 8);
 
 		/* No frame is actually processed */
 		vp9->cur_frame = NULL;
diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
index 1904d58875ad..3cd29ab4f979 100644
--- a/drivers/staging/media/meson/vdec/esparser.c
+++ b/drivers/staging/media/meson/vdec/esparser.c
@@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
 		if (esparser_vififo_get_free_space(sess) < payload_size ||
 		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
 			return -EAGAIN;
+
 	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
 		return -EAGAIN;
 	}
diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
index 0906b8fb5cc6..a48170fe4cff 100644
--- a/drivers/staging/media/meson/vdec/vdec.h
+++ b/drivers/staging/media/meson/vdec/vdec.h
@@ -244,6 +244,7 @@ struct amvdec_session {
 	u32 width;
 	u32 height;
 	u32 colorspace;
+	u32 bitdepth;
 	u8 ycbcr_enc;
 	u8 quantization;
 	u8 xfer_func;
diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
index 7d2a75653250..fef76142f0c5 100644
--- a/drivers/staging/media/meson/vdec/vdec_helpers.c
+++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
@@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
 }
 EXPORT_SYMBOL_GPL(amvdec_write_parser);
 
-/* 4 KiB per 64x32 block */
-u32 amvdec_am21c_body_size(u32 width, u32 height)
+/* AMFBC body is made out of 64x32 blocks with varying block size */
+u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
 {
 	u32 width_64 = ALIGN(width, 64) / 64;
 	u32 height_32 = ALIGN(height, 32) / 32;
+	u32 blk_size = 4096;
 
-	return SZ_4K * width_64 * height_32;
+	if (!is_10bit) {
+		if (use_mmu)
+			blk_size = 3200;
+		else
+			blk_size = 3072;
+	}
+
+	return blk_size * width_64 * height_32;
 }
-EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
+EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
 
 /* 32 bytes per 128x64 block */
-u32 amvdec_am21c_head_size(u32 width, u32 height)
+u32 amvdec_amfbc_head_size(u32 width, u32 height)
 {
 	u32 width_128 = ALIGN(width, 128) / 128;
 	u32 height_64 = ALIGN(height, 64) / 64;
 
 	return 32 * width_128 * height_64;
 }
-EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
+EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
 
-u32 amvdec_am21c_size(u32 width, u32 height)
+u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
 {
-	return ALIGN(amvdec_am21c_body_size(width, height) +
-		     amvdec_am21c_head_size(width, height), SZ_64K);
+	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
+		     amvdec_amfbc_head_size(width, height), SZ_64K);
 }
-EXPORT_SYMBOL_GPL(amvdec_am21c_size);
+EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
 
 static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
 {
@@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
 EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
 
 void amvdec_src_change(struct amvdec_session *sess, u32 width,
-		       u32 height, u32 dpb_size)
+		       u32 height, u32 dpb_size, u32 bitdepth)
 {
 	static const struct v4l2_event ev = {
 		.type = V4L2_EVENT_SOURCE_CHANGE,
@@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
 
 	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
 
+	sess->bitdepth = bitdepth;
+
 	/*
 	 * Check if the capture queue is already configured well for our
-	 * usecase. If so, keep decoding with it and do not send the event
+	 * usecase. If so, keep decoding with it.
 	 */
 	if (sess->streamon_cap &&
 	    sess->width == width &&
 	    sess->height == height &&
 	    dpb_size <= sess->num_dst_bufs) {
 		sess->fmt_out->codec_ops->resume(sess);
-		return;
+	} else {
+		sess->status = STATUS_NEEDS_RESUME;
+		sess->changed_format = 0;
 	}
 
-	sess->changed_format = 0;
 	sess->width = width;
 	sess->height = height;
-	sess->status = STATUS_NEEDS_RESUME;
 
-	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
-		width, height, dpb_size);
+	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
+		width, height, dpb_size, bitdepth);
 	v4l2_event_queue_fh(&sess->fh, &ev);
 }
 EXPORT_SYMBOL_GPL(amvdec_src_change);
diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
index 4bf3e61d081b..1a711679d26a 100644
--- a/drivers/staging/media/meson/vdec/vdec_helpers.h
+++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
@@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
 u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
 void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
 
-u32 amvdec_am21c_body_size(u32 width, u32 height);
-u32 amvdec_am21c_head_size(u32 width, u32 height);
-u32 amvdec_am21c_size(u32 width, u32 height);
+/* Helpers for the Amlogic compressed framebuffer format */
+u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
+u32 amvdec_amfbc_head_size(u32 width, u32 height);
+u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
 
 /**
  * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
@@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
  * @width: picture width detected by the hardware
  * @height: picture height detected by the hardware
  * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
+ * @bitdepth: Bit depth (usually 10 or 8) of the coded content
  */
 void amvdec_src_change(struct amvdec_session *sess, u32 width,
-		       u32 height, u32 dpb_size);
+		       u32 height, u32 dpb_size, u32 bitdepth);
 
 /**
  * amvdec_abort() - Abort the current decoding session
-- 
2.34.1


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Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Nicolas Dufresne]

Hi,

Le mardi 24 janvier 2023 à 03:40 +0000, Christian Hewitt a écrit :
> From: Benjamin Roszak <benjamin545@gmail.com>
> 
> In order to support 10bit bitstream decoding, buffers and MMU
> handling must be cleaned up to support either downscale output
> from compressed 10bit decoding to uncompressed 8bit NV12 output
> or to compressed 10bit proprietary encoded frame format.

I understand this is step forward, and agree with the patches in general, though
I'd like to know if we can expect 10bit secondary buffers in the future ? Or is
the AMFBC that only 10bit format supported ? Should be expect the 10bit format
definition to be added later ?

> 
> For that, "am21c" name is moved to "amfbc" to reflect the upstream
> Amlogic Compressed framebuffer modifier naming.
> 
> Compressed frame buffers allocation is also cleaned up so it
> can be shared with the HEVC decoder implementation.
> 
> Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
> ---
>  drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
>  .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
>  .../media/meson/vdec/codec_hevc_common.h      |   3 +-
>  drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
>  drivers/staging/media/meson/vdec/esparser.c   |   1 +
>  drivers/staging/media/meson/vdec/vdec.h       |   1 +
>  .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
>  .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
>  8 files changed, 161 insertions(+), 97 deletions(-)
> 
> diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
> index c61128fc4bb9..d53c9a464bde 100644
> --- a/drivers/staging/media/meson/vdec/codec_h264.c
> +++ b/drivers/staging/media/meson/vdec/codec_h264.c
> @@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
>  		frame_width, frame_height, crop_right, crop_bottom);
>  
>  	codec_h264_set_par(sess);
> -	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
> +	amvdec_src_change(sess, frame_width, frame_height,
> +			  h264->max_refs + 5, 8);
>  }
>  
>  /*
> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
> index 0315cc0911cd..1c74b4837dcb 100644
> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
> @@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
>  void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>  {
>  	struct amvdec_core *core = sess->core;
> -	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
> -	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
> +	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
> +					 sess->pixfmt_cap, is_10bit);
> +	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
> +					       is_10bit, use_mmu);
> +	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
>  
>  	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
>  		/* Enable 2-plane reference read mode */
> @@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>  		return;
>  	}
>  
> +	/* enable mem saving mode for 8-bit */
> +	if (!is_10bit)
> +		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
> +	else
> +		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
> +
>  	if (codec_hevc_use_mmu(core->platform->revision,
>  			       sess->pixfmt_cap, is_10bit))
>  		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
> +	else if (!is_10bit)
> +		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
>  	else
>  		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
>  
> @@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
>  
>  		idx = vb->index;
>  
> -		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
> +		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
>  			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>  		else
>  			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
> @@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>  {
>  	struct amvdec_core *core = sess->core;
>  	struct v4l2_m2m_buffer *buf;
> -	u32 revision = core->platform->revision;
>  	u32 pixfmt_cap = sess->pixfmt_cap;
> +	const u32 revision = core->platform->revision;
>  	int i;
>  
>  	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
> @@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>  		dma_addr_t buf_uv_paddr = 0;
>  		u32 idx = vb->index;
>  
> -		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
> -			buf_y_paddr = comm->mmu_header_paddr[idx];
> -		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
> -			buf_y_paddr = comm->fbc_buffer_paddr[idx];
> -		else
> +		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
> +			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
> +				buf_y_paddr = comm->mmu_header_paddr[idx];
> +			else
> +				buf_y_paddr = comm->fbc_buffer_paddr[idx];
> +		} else {
>  			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
> +		}
>  
>  		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
>  				 buf_y_paddr >> 5);
> @@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>  		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
>  }
>  
> -void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
> +void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>  				 struct codec_hevc_common *comm)
>  {
>  	struct device *dev = sess->core->dev;
> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>  	int i;
>  
>  	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
> -		if (comm->fbc_buffer_vaddr[i]) {
> -			dma_free_coherent(dev, am21_size,
> -					  comm->fbc_buffer_vaddr[i],
> -					  comm->fbc_buffer_paddr[i]);
> -			comm->fbc_buffer_vaddr[i] = NULL;
> +		if (comm->mmu_header_vaddr[i]) {
> +			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> +					  comm->mmu_header_vaddr[i],
> +					  comm->mmu_header_paddr[i]);
> +			comm->mmu_header_vaddr[i] = NULL;
>  		}
>  	}
>  }
> -EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
> +EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>  
> -static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
> +static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>  					struct codec_hevc_common *comm)
>  {
>  	struct device *dev = sess->core->dev;
>  	struct v4l2_m2m_buffer *buf;
> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>  
>  	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>  		u32 idx = buf->vb.vb2_buf.index;
>  		dma_addr_t paddr;
> -		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
> -						 GFP_KERNEL);
> +		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> +						 &paddr, GFP_KERNEL);
>  		if (!vaddr) {
> -			codec_hevc_free_fbc_buffers(sess, comm);
> +			codec_hevc_free_mmu_headers(sess, comm);
>  			return -ENOMEM;
>  		}
>  
> -		comm->fbc_buffer_vaddr[idx] = vaddr;
> -		comm->fbc_buffer_paddr[idx] = paddr;
> +		comm->mmu_header_vaddr[idx] = vaddr;
> +		comm->mmu_header_paddr[idx] = paddr;
>  	}
>  
>  	return 0;
>  }
>  
> -void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
> +void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>  				 struct codec_hevc_common *comm)
>  {
>  	struct device *dev = sess->core->dev;
> +	u32 use_mmu;
> +	u32 am21_size;
>  	int i;
>  
> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
> +				     sess->pixfmt_cap,
> +				sess->bitdepth == 10 ? 1 : 0);
> +
> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
> +				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
> +
>  	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
> -		if (comm->mmu_header_vaddr[i]) {
> -			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> -					  comm->mmu_header_vaddr[i],
> -					  comm->mmu_header_paddr[i]);
> -			comm->mmu_header_vaddr[i] = NULL;
> +		if (comm->fbc_buffer_vaddr[i]) {
> +			dma_free_coherent(dev, am21_size,
> +					  comm->fbc_buffer_vaddr[i],
> +					  comm->fbc_buffer_paddr[i]);
> +			comm->fbc_buffer_vaddr[i] = NULL;
>  		}
>  	}
>  
> @@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>  				  comm->mmu_map_paddr);
>  		comm->mmu_map_vaddr = NULL;
>  	}
> +
> +	codec_hevc_free_mmu_headers(sess, comm);
>  }
> -EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
> +EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>  
> -static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
> +static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>  					struct codec_hevc_common *comm)
>  {
>  	struct device *dev = sess->core->dev;
>  	struct v4l2_m2m_buffer *buf;
> +	u32 use_mmu;
> +	u32 am21_size;
> +	const u32 revision = sess->core->platform->revision;
> +	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
> +	int ret;
>  
> -	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
> -						 &comm->mmu_map_paddr,
> -						 GFP_KERNEL);
> -	if (!comm->mmu_map_vaddr)
> -		return -ENOMEM;
> +	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
> +				     is_10bit);
> +
> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
> +				      is_10bit, use_mmu);
>  
>  	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>  		u32 idx = buf->vb.vb2_buf.index;
>  		dma_addr_t paddr;
> -		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> -						 &paddr, GFP_KERNEL);
> +
> +		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
> +						 GFP_KERNEL);
>  		if (!vaddr) {
> -			codec_hevc_free_mmu_headers(sess, comm);
> +			codec_hevc_free_fbc_buffers(sess, comm);
>  			return -ENOMEM;
>  		}
>  
> -		comm->mmu_header_vaddr[idx] = vaddr;
> -		comm->mmu_header_paddr[idx] = paddr;
> +		comm->fbc_buffer_vaddr[idx] = vaddr;
> +		comm->fbc_buffer_paddr[idx] = paddr;
> +	}
> +
> +	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> +		ret = codec_hevc_alloc_mmu_headers(sess, comm);
> +		if (ret) {
> +			codec_hevc_free_fbc_buffers(sess, comm);
> +			return ret;
> +		}
>  	}
>  
>  	return 0;
> @@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>  			     int is_10bit)
>  {
>  	struct amvdec_core *core = sess->core;
> +	struct device *dev = core->dev;
>  	int ret;
>  
> -	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> -		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
> -		if (ret)
> -			return ret;
> +	if (codec_hevc_use_mmu(core->platform->revision,
> +			       sess->pixfmt_cap, is_10bit)) {
> +		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
> +							 &comm->mmu_map_paddr,
> +							 GFP_KERNEL);
> +		if (!comm->mmu_map_vaddr)
> +			return -ENOMEM;
>  	}
>  
>  	if (codec_hevc_use_mmu(core->platform->revision,
> -			       sess->pixfmt_cap, is_10bit)) {
> -		ret = codec_hevc_alloc_mmu_headers(sess, comm);
> -		if (ret) {
> -			codec_hevc_free_fbc_buffers(sess, comm);
> +			       sess->pixfmt_cap, is_10bit) ||
> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> +		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
> +		if (ret)
>  			return ret;
> -		}
>  	}
>  
>  	if (core->platform->revision == VDEC_REVISION_GXBB)
> @@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
>  
>  void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>  			     struct codec_hevc_common *comm,
> -			     struct vb2_buffer *vb)
> +			     struct vb2_buffer *vb,
> +			     u32 is_10bit)
>  {
> -	u32 size = amvdec_am21c_size(sess->width, sess->height);
> -	u32 nb_pages = size / PAGE_SIZE;
> +	u32 use_mmu;
> +	u32 size;
> +	u32 nb_pages;
>  	u32 *mmu_map = comm->mmu_map_vaddr;
>  	u32 first_page;
>  	u32 i;
>  
> -	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
> -		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
> -	else
> -		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
> +				     sess->pixfmt_cap, is_10bit);
> +
> +	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
> +				 use_mmu);
>  
> +	nb_pages = size / PAGE_SIZE;
> +	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>  	for (i = 0; i < nb_pages; ++i)
>  		mmu_map[i] = first_page + i;
>  }
> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
> index cf072b8a9da2..13f9f1d90a94 100644
> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
> @@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>  
>  void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>  			     struct codec_hevc_common *comm,
> -			     struct vb2_buffer *vb);
> +			     struct vb2_buffer *vb,
> +			     u32 is_10bit);
>  
>  #endif
> diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
> index 394df5761556..8e3bbf0db4b3 100644
> --- a/drivers/staging/media/meson/vdec/codec_vp9.c
> +++ b/drivers/staging/media/meson/vdec/codec_vp9.c
> @@ -458,12 +458,6 @@ struct codec_vp9 {
>  	struct list_head ref_frames_list;
>  	u32 frames_num;
>  
> -	/* In case of downsampling (decoding with FBC but outputting in NV12M),
> -	 * we need to allocate additional buffers for FBC.
> -	 */
> -	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
> -	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
> -
>  	int ref_frame_map[REF_FRAMES];
>  	int next_ref_frame_map[REF_FRAMES];
>  	struct vp9_frame *frame_refs[REFS_PER_FRAME];
> @@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>  		buf_y_paddr =
>  		       vb2_dma_contig_plane_dma_addr(vb, 0);
>  
> -	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
> -		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
> -		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
> +	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
>  		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
> -	}
>  
>  	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
>  		buf_y_paddr =
> @@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>  
>  	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>  			       vp9->is_10bit)) {
> -		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
> -				 vp9->common.mmu_header_paddr[vb->index]);
> +		dma_addr_t header_adr;
> +
> +		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
> +			header_adr = vp9->common.mmu_header_paddr[vb->index];
> +		else
> +			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
> +		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
>  		/* use HEVC_CM_HEADER_START_ADDR */
>  		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
>  	}
> @@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>  {
>  	struct amvdec_core *core = sess->core;
>  	u32 scale = 0;
> +	u32 use_mmu;
>  	u32 sz;
>  	int i;
>  
> +	use_mmu = codec_hevc_use_mmu(core->platform->revision,
> +				     sess->pixfmt_cap, vp9->is_10bit);
> +
>  	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
>  	codec_vp9_set_refs(sess, vp9);
>  	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
> @@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>  		    vp9->frame_refs[i]->height != vp9->height)
>  			scale = 1;
>  
> -		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
> -					    vp9->frame_refs[i]->height);
> +		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
> +					    vp9->frame_refs[i]->height,
> +					    vp9->is_10bit, use_mmu);
>  
>  		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
>  				 vp9->frame_refs[i]->width);
> @@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
>  	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>  			       vp9->is_10bit))
>  		codec_hevc_fill_mmu_map(sess, &vp9->common,
> -					&vp9->cur_frame->vbuf->vb2_buf);
> +					&vp9->cur_frame->vbuf->vb2_buf,
> +					vp9->is_10bit);
>  
>  	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
>  
> @@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
>  
>  	codec_vp9_fetch_rpm(sess);
>  	if (codec_vp9_process_rpm(vp9)) {
> -		amvdec_src_change(sess, vp9->width, vp9->height, 16);
> +		amvdec_src_change(sess, vp9->width, vp9->height, 16,
> +				  vp9->is_10bit ? 10 : 8);
>  
>  		/* No frame is actually processed */
>  		vp9->cur_frame = NULL;
> diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
> index 1904d58875ad..3cd29ab4f979 100644
> --- a/drivers/staging/media/meson/vdec/esparser.c
> +++ b/drivers/staging/media/meson/vdec/esparser.c
> @@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
>  		if (esparser_vififo_get_free_space(sess) < payload_size ||
>  		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
>  			return -EAGAIN;
> +
>  	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
>  		return -EAGAIN;
>  	}
> diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
> index 0906b8fb5cc6..a48170fe4cff 100644
> --- a/drivers/staging/media/meson/vdec/vdec.h
> +++ b/drivers/staging/media/meson/vdec/vdec.h
> @@ -244,6 +244,7 @@ struct amvdec_session {
>  	u32 width;
>  	u32 height;
>  	u32 colorspace;
> +	u32 bitdepth;
>  	u8 ycbcr_enc;
>  	u8 quantization;
>  	u8 xfer_func;
> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
> index 7d2a75653250..fef76142f0c5 100644
> --- a/drivers/staging/media/meson/vdec/vdec_helpers.c
> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
> @@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
>  }
>  EXPORT_SYMBOL_GPL(amvdec_write_parser);
>  
> -/* 4 KiB per 64x32 block */
> -u32 amvdec_am21c_body_size(u32 width, u32 height)
> +/* AMFBC body is made out of 64x32 blocks with varying block size */
> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>  {
>  	u32 width_64 = ALIGN(width, 64) / 64;
>  	u32 height_32 = ALIGN(height, 32) / 32;
> +	u32 blk_size = 4096;
>  
> -	return SZ_4K * width_64 * height_32;
> +	if (!is_10bit) {
> +		if (use_mmu)
> +			blk_size = 3200;
> +		else
> +			blk_size = 3072;
> +	}
> +
> +	return blk_size * width_64 * height_32;
>  }
> -EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
> +EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
>  
>  /* 32 bytes per 128x64 block */
> -u32 amvdec_am21c_head_size(u32 width, u32 height)
> +u32 amvdec_amfbc_head_size(u32 width, u32 height)
>  {
>  	u32 width_128 = ALIGN(width, 128) / 128;
>  	u32 height_64 = ALIGN(height, 64) / 64;
>  
>  	return 32 * width_128 * height_64;
>  }
> -EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
> +EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
>  
> -u32 amvdec_am21c_size(u32 width, u32 height)
> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>  {
> -	return ALIGN(amvdec_am21c_body_size(width, height) +
> -		     amvdec_am21c_head_size(width, height), SZ_64K);
> +	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
> +		     amvdec_amfbc_head_size(width, height), SZ_64K);
>  }
> -EXPORT_SYMBOL_GPL(amvdec_am21c_size);
> +EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
>  
>  static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
>  {
> @@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>  EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
>  
>  void amvdec_src_change(struct amvdec_session *sess, u32 width,
> -		       u32 height, u32 dpb_size)
> +		       u32 height, u32 dpb_size, u32 bitdepth)
>  {
>  	static const struct v4l2_event ev = {
>  		.type = V4L2_EVENT_SOURCE_CHANGE,
> @@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
>  
>  	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
>  
> +	sess->bitdepth = bitdepth;
> +
>  	/*
>  	 * Check if the capture queue is already configured well for our
> -	 * usecase. If so, keep decoding with it and do not send the event
> +	 * usecase. If so, keep decoding with it.
>  	 */
>  	if (sess->streamon_cap &&
>  	    sess->width == width &&
>  	    sess->height == height &&
>  	    dpb_size <= sess->num_dst_bufs) {
>  		sess->fmt_out->codec_ops->resume(sess);
> -		return;
> +	} else {
> +		sess->status = STATUS_NEEDS_RESUME;
> +		sess->changed_format = 0;
>  	}
>  
> -	sess->changed_format = 0;
>  	sess->width = width;
>  	sess->height = height;
> -	sess->status = STATUS_NEEDS_RESUME;
>  
> -	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
> -		width, height, dpb_size);
> +	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
> +		width, height, dpb_size, bitdepth);
>  	v4l2_event_queue_fh(&sess->fh, &ev);
>  }
>  EXPORT_SYMBOL_GPL(amvdec_src_change);
> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
> index 4bf3e61d081b..1a711679d26a 100644
> --- a/drivers/staging/media/meson/vdec/vdec_helpers.h
> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
> @@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
>  u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
>  void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
>  
> -u32 amvdec_am21c_body_size(u32 width, u32 height);
> -u32 amvdec_am21c_head_size(u32 width, u32 height);
> -u32 amvdec_am21c_size(u32 width, u32 height);
> +/* Helpers for the Amlogic compressed framebuffer format */
> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
> +u32 amvdec_amfbc_head_size(u32 width, u32 height);
> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>  
>  /**
>   * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
> @@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>   * @width: picture width detected by the hardware
>   * @height: picture height detected by the hardware
>   * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
> + * @bitdepth: Bit depth (usually 10 or 8) of the coded content
>   */
>  void amvdec_src_change(struct amvdec_session *sess, u32 width,
> -		       u32 height, u32 dpb_size);
> +		       u32 height, u32 dpb_size, u32 bitdepth);
>  
>  /**
>   * amvdec_abort() - Abort the current decoding session

Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Nicolas Dufresne]

Hi,

Le mardi 24 janvier 2023 à 03:40 +0000, Christian Hewitt a écrit :
> From: Benjamin Roszak <benjamin545@gmail.com>
> 
> In order to support 10bit bitstream decoding, buffers and MMU
> handling must be cleaned up to support either downscale output
> from compressed 10bit decoding to uncompressed 8bit NV12 output
> or to compressed 10bit proprietary encoded frame format.

I understand this is step forward, and agree with the patches in general, though
I'd like to know if we can expect 10bit secondary buffers in the future ? Or is
the AMFBC that only 10bit format supported ? Should be expect the 10bit format
definition to be added later ?

> 
> For that, "am21c" name is moved to "amfbc" to reflect the upstream
> Amlogic Compressed framebuffer modifier naming.
> 
> Compressed frame buffers allocation is also cleaned up so it
> can be shared with the HEVC decoder implementation.
> 
> Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
> ---
>  drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
>  .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
>  .../media/meson/vdec/codec_hevc_common.h      |   3 +-
>  drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
>  drivers/staging/media/meson/vdec/esparser.c   |   1 +
>  drivers/staging/media/meson/vdec/vdec.h       |   1 +
>  .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
>  .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
>  8 files changed, 161 insertions(+), 97 deletions(-)
> 
> diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
> index c61128fc4bb9..d53c9a464bde 100644
> --- a/drivers/staging/media/meson/vdec/codec_h264.c
> +++ b/drivers/staging/media/meson/vdec/codec_h264.c
> @@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
>  		frame_width, frame_height, crop_right, crop_bottom);
>  
>  	codec_h264_set_par(sess);
> -	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
> +	amvdec_src_change(sess, frame_width, frame_height,
> +			  h264->max_refs + 5, 8);
>  }
>  
>  /*
> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
> index 0315cc0911cd..1c74b4837dcb 100644
> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
> @@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
>  void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>  {
>  	struct amvdec_core *core = sess->core;
> -	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
> -	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
> +	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
> +					 sess->pixfmt_cap, is_10bit);
> +	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
> +					       is_10bit, use_mmu);
> +	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
>  
>  	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
>  		/* Enable 2-plane reference read mode */
> @@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>  		return;
>  	}
>  
> +	/* enable mem saving mode for 8-bit */
> +	if (!is_10bit)
> +		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
> +	else
> +		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
> +
>  	if (codec_hevc_use_mmu(core->platform->revision,
>  			       sess->pixfmt_cap, is_10bit))
>  		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
> +	else if (!is_10bit)
> +		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
>  	else
>  		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
>  
> @@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
>  
>  		idx = vb->index;
>  
> -		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
> +		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
>  			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>  		else
>  			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
> @@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>  {
>  	struct amvdec_core *core = sess->core;
>  	struct v4l2_m2m_buffer *buf;
> -	u32 revision = core->platform->revision;
>  	u32 pixfmt_cap = sess->pixfmt_cap;
> +	const u32 revision = core->platform->revision;
>  	int i;
>  
>  	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
> @@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>  		dma_addr_t buf_uv_paddr = 0;
>  		u32 idx = vb->index;
>  
> -		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
> -			buf_y_paddr = comm->mmu_header_paddr[idx];
> -		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
> -			buf_y_paddr = comm->fbc_buffer_paddr[idx];
> -		else
> +		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
> +			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
> +				buf_y_paddr = comm->mmu_header_paddr[idx];
> +			else
> +				buf_y_paddr = comm->fbc_buffer_paddr[idx];
> +		} else {
>  			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
> +		}
>  
>  		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
>  				 buf_y_paddr >> 5);
> @@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>  		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
>  }
>  
> -void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
> +void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>  				 struct codec_hevc_common *comm)
>  {
>  	struct device *dev = sess->core->dev;
> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>  	int i;
>  
>  	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
> -		if (comm->fbc_buffer_vaddr[i]) {
> -			dma_free_coherent(dev, am21_size,
> -					  comm->fbc_buffer_vaddr[i],
> -					  comm->fbc_buffer_paddr[i]);
> -			comm->fbc_buffer_vaddr[i] = NULL;
> +		if (comm->mmu_header_vaddr[i]) {
> +			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> +					  comm->mmu_header_vaddr[i],
> +					  comm->mmu_header_paddr[i]);
> +			comm->mmu_header_vaddr[i] = NULL;
>  		}
>  	}
>  }
> -EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
> +EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>  
> -static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
> +static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>  					struct codec_hevc_common *comm)
>  {
>  	struct device *dev = sess->core->dev;
>  	struct v4l2_m2m_buffer *buf;
> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>  
>  	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>  		u32 idx = buf->vb.vb2_buf.index;
>  		dma_addr_t paddr;
> -		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
> -						 GFP_KERNEL);
> +		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> +						 &paddr, GFP_KERNEL);
>  		if (!vaddr) {
> -			codec_hevc_free_fbc_buffers(sess, comm);
> +			codec_hevc_free_mmu_headers(sess, comm);
>  			return -ENOMEM;
>  		}
>  
> -		comm->fbc_buffer_vaddr[idx] = vaddr;
> -		comm->fbc_buffer_paddr[idx] = paddr;
> +		comm->mmu_header_vaddr[idx] = vaddr;
> +		comm->mmu_header_paddr[idx] = paddr;
>  	}
>  
>  	return 0;
>  }
>  
> -void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
> +void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>  				 struct codec_hevc_common *comm)
>  {
>  	struct device *dev = sess->core->dev;
> +	u32 use_mmu;
> +	u32 am21_size;
>  	int i;
>  
> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
> +				     sess->pixfmt_cap,
> +				sess->bitdepth == 10 ? 1 : 0);
> +
> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
> +				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
> +
>  	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
> -		if (comm->mmu_header_vaddr[i]) {
> -			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> -					  comm->mmu_header_vaddr[i],
> -					  comm->mmu_header_paddr[i]);
> -			comm->mmu_header_vaddr[i] = NULL;
> +		if (comm->fbc_buffer_vaddr[i]) {
> +			dma_free_coherent(dev, am21_size,
> +					  comm->fbc_buffer_vaddr[i],
> +					  comm->fbc_buffer_paddr[i]);
> +			comm->fbc_buffer_vaddr[i] = NULL;
>  		}
>  	}
>  
> @@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>  				  comm->mmu_map_paddr);
>  		comm->mmu_map_vaddr = NULL;
>  	}
> +
> +	codec_hevc_free_mmu_headers(sess, comm);
>  }
> -EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
> +EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>  
> -static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
> +static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>  					struct codec_hevc_common *comm)
>  {
>  	struct device *dev = sess->core->dev;
>  	struct v4l2_m2m_buffer *buf;
> +	u32 use_mmu;
> +	u32 am21_size;
> +	const u32 revision = sess->core->platform->revision;
> +	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
> +	int ret;
>  
> -	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
> -						 &comm->mmu_map_paddr,
> -						 GFP_KERNEL);
> -	if (!comm->mmu_map_vaddr)
> -		return -ENOMEM;
> +	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
> +				     is_10bit);
> +
> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
> +				      is_10bit, use_mmu);
>  
>  	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>  		u32 idx = buf->vb.vb2_buf.index;
>  		dma_addr_t paddr;
> -		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> -						 &paddr, GFP_KERNEL);
> +
> +		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
> +						 GFP_KERNEL);
>  		if (!vaddr) {
> -			codec_hevc_free_mmu_headers(sess, comm);
> +			codec_hevc_free_fbc_buffers(sess, comm);
>  			return -ENOMEM;
>  		}
>  
> -		comm->mmu_header_vaddr[idx] = vaddr;
> -		comm->mmu_header_paddr[idx] = paddr;
> +		comm->fbc_buffer_vaddr[idx] = vaddr;
> +		comm->fbc_buffer_paddr[idx] = paddr;
> +	}
> +
> +	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> +		ret = codec_hevc_alloc_mmu_headers(sess, comm);
> +		if (ret) {
> +			codec_hevc_free_fbc_buffers(sess, comm);
> +			return ret;
> +		}
>  	}
>  
>  	return 0;
> @@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>  			     int is_10bit)
>  {
>  	struct amvdec_core *core = sess->core;
> +	struct device *dev = core->dev;
>  	int ret;
>  
> -	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> -		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
> -		if (ret)
> -			return ret;
> +	if (codec_hevc_use_mmu(core->platform->revision,
> +			       sess->pixfmt_cap, is_10bit)) {
> +		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
> +							 &comm->mmu_map_paddr,
> +							 GFP_KERNEL);
> +		if (!comm->mmu_map_vaddr)
> +			return -ENOMEM;
>  	}
>  
>  	if (codec_hevc_use_mmu(core->platform->revision,
> -			       sess->pixfmt_cap, is_10bit)) {
> -		ret = codec_hevc_alloc_mmu_headers(sess, comm);
> -		if (ret) {
> -			codec_hevc_free_fbc_buffers(sess, comm);
> +			       sess->pixfmt_cap, is_10bit) ||
> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> +		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
> +		if (ret)
>  			return ret;
> -		}
>  	}
>  
>  	if (core->platform->revision == VDEC_REVISION_GXBB)
> @@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
>  
>  void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>  			     struct codec_hevc_common *comm,
> -			     struct vb2_buffer *vb)
> +			     struct vb2_buffer *vb,
> +			     u32 is_10bit)
>  {
> -	u32 size = amvdec_am21c_size(sess->width, sess->height);
> -	u32 nb_pages = size / PAGE_SIZE;
> +	u32 use_mmu;
> +	u32 size;
> +	u32 nb_pages;
>  	u32 *mmu_map = comm->mmu_map_vaddr;
>  	u32 first_page;
>  	u32 i;
>  
> -	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
> -		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
> -	else
> -		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
> +				     sess->pixfmt_cap, is_10bit);
> +
> +	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
> +				 use_mmu);
>  
> +	nb_pages = size / PAGE_SIZE;
> +	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>  	for (i = 0; i < nb_pages; ++i)
>  		mmu_map[i] = first_page + i;
>  }
> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
> index cf072b8a9da2..13f9f1d90a94 100644
> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
> @@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>  
>  void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>  			     struct codec_hevc_common *comm,
> -			     struct vb2_buffer *vb);
> +			     struct vb2_buffer *vb,
> +			     u32 is_10bit);
>  
>  #endif
> diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
> index 394df5761556..8e3bbf0db4b3 100644
> --- a/drivers/staging/media/meson/vdec/codec_vp9.c
> +++ b/drivers/staging/media/meson/vdec/codec_vp9.c
> @@ -458,12 +458,6 @@ struct codec_vp9 {
>  	struct list_head ref_frames_list;
>  	u32 frames_num;
>  
> -	/* In case of downsampling (decoding with FBC but outputting in NV12M),
> -	 * we need to allocate additional buffers for FBC.
> -	 */
> -	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
> -	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
> -
>  	int ref_frame_map[REF_FRAMES];
>  	int next_ref_frame_map[REF_FRAMES];
>  	struct vp9_frame *frame_refs[REFS_PER_FRAME];
> @@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>  		buf_y_paddr =
>  		       vb2_dma_contig_plane_dma_addr(vb, 0);
>  
> -	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
> -		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
> -		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
> +	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
>  		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
> -	}
>  
>  	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
>  		buf_y_paddr =
> @@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>  
>  	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>  			       vp9->is_10bit)) {
> -		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
> -				 vp9->common.mmu_header_paddr[vb->index]);
> +		dma_addr_t header_adr;
> +
> +		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
> +			header_adr = vp9->common.mmu_header_paddr[vb->index];
> +		else
> +			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
> +		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
>  		/* use HEVC_CM_HEADER_START_ADDR */
>  		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
>  	}
> @@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>  {
>  	struct amvdec_core *core = sess->core;
>  	u32 scale = 0;
> +	u32 use_mmu;
>  	u32 sz;
>  	int i;
>  
> +	use_mmu = codec_hevc_use_mmu(core->platform->revision,
> +				     sess->pixfmt_cap, vp9->is_10bit);
> +
>  	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
>  	codec_vp9_set_refs(sess, vp9);
>  	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
> @@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>  		    vp9->frame_refs[i]->height != vp9->height)
>  			scale = 1;
>  
> -		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
> -					    vp9->frame_refs[i]->height);
> +		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
> +					    vp9->frame_refs[i]->height,
> +					    vp9->is_10bit, use_mmu);
>  
>  		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
>  				 vp9->frame_refs[i]->width);
> @@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
>  	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>  			       vp9->is_10bit))
>  		codec_hevc_fill_mmu_map(sess, &vp9->common,
> -					&vp9->cur_frame->vbuf->vb2_buf);
> +					&vp9->cur_frame->vbuf->vb2_buf,
> +					vp9->is_10bit);
>  
>  	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
>  
> @@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
>  
>  	codec_vp9_fetch_rpm(sess);
>  	if (codec_vp9_process_rpm(vp9)) {
> -		amvdec_src_change(sess, vp9->width, vp9->height, 16);
> +		amvdec_src_change(sess, vp9->width, vp9->height, 16,
> +				  vp9->is_10bit ? 10 : 8);
>  
>  		/* No frame is actually processed */
>  		vp9->cur_frame = NULL;
> diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
> index 1904d58875ad..3cd29ab4f979 100644
> --- a/drivers/staging/media/meson/vdec/esparser.c
> +++ b/drivers/staging/media/meson/vdec/esparser.c
> @@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
>  		if (esparser_vififo_get_free_space(sess) < payload_size ||
>  		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
>  			return -EAGAIN;
> +
>  	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
>  		return -EAGAIN;
>  	}
> diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
> index 0906b8fb5cc6..a48170fe4cff 100644
> --- a/drivers/staging/media/meson/vdec/vdec.h
> +++ b/drivers/staging/media/meson/vdec/vdec.h
> @@ -244,6 +244,7 @@ struct amvdec_session {
>  	u32 width;
>  	u32 height;
>  	u32 colorspace;
> +	u32 bitdepth;
>  	u8 ycbcr_enc;
>  	u8 quantization;
>  	u8 xfer_func;
> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
> index 7d2a75653250..fef76142f0c5 100644
> --- a/drivers/staging/media/meson/vdec/vdec_helpers.c
> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
> @@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
>  }
>  EXPORT_SYMBOL_GPL(amvdec_write_parser);
>  
> -/* 4 KiB per 64x32 block */
> -u32 amvdec_am21c_body_size(u32 width, u32 height)
> +/* AMFBC body is made out of 64x32 blocks with varying block size */
> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>  {
>  	u32 width_64 = ALIGN(width, 64) / 64;
>  	u32 height_32 = ALIGN(height, 32) / 32;
> +	u32 blk_size = 4096;
>  
> -	return SZ_4K * width_64 * height_32;
> +	if (!is_10bit) {
> +		if (use_mmu)
> +			blk_size = 3200;
> +		else
> +			blk_size = 3072;
> +	}
> +
> +	return blk_size * width_64 * height_32;
>  }
> -EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
> +EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
>  
>  /* 32 bytes per 128x64 block */
> -u32 amvdec_am21c_head_size(u32 width, u32 height)
> +u32 amvdec_amfbc_head_size(u32 width, u32 height)
>  {
>  	u32 width_128 = ALIGN(width, 128) / 128;
>  	u32 height_64 = ALIGN(height, 64) / 64;
>  
>  	return 32 * width_128 * height_64;
>  }
> -EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
> +EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
>  
> -u32 amvdec_am21c_size(u32 width, u32 height)
> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>  {
> -	return ALIGN(amvdec_am21c_body_size(width, height) +
> -		     amvdec_am21c_head_size(width, height), SZ_64K);
> +	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
> +		     amvdec_amfbc_head_size(width, height), SZ_64K);
>  }
> -EXPORT_SYMBOL_GPL(amvdec_am21c_size);
> +EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
>  
>  static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
>  {
> @@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>  EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
>  
>  void amvdec_src_change(struct amvdec_session *sess, u32 width,
> -		       u32 height, u32 dpb_size)
> +		       u32 height, u32 dpb_size, u32 bitdepth)
>  {
>  	static const struct v4l2_event ev = {
>  		.type = V4L2_EVENT_SOURCE_CHANGE,
> @@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
>  
>  	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
>  
> +	sess->bitdepth = bitdepth;
> +
>  	/*
>  	 * Check if the capture queue is already configured well for our
> -	 * usecase. If so, keep decoding with it and do not send the event
> +	 * usecase. If so, keep decoding with it.
>  	 */
>  	if (sess->streamon_cap &&
>  	    sess->width == width &&
>  	    sess->height == height &&
>  	    dpb_size <= sess->num_dst_bufs) {
>  		sess->fmt_out->codec_ops->resume(sess);
> -		return;
> +	} else {
> +		sess->status = STATUS_NEEDS_RESUME;
> +		sess->changed_format = 0;
>  	}
>  
> -	sess->changed_format = 0;
>  	sess->width = width;
>  	sess->height = height;
> -	sess->status = STATUS_NEEDS_RESUME;
>  
> -	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
> -		width, height, dpb_size);
> +	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
> +		width, height, dpb_size, bitdepth);
>  	v4l2_event_queue_fh(&sess->fh, &ev);
>  }
>  EXPORT_SYMBOL_GPL(amvdec_src_change);
> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
> index 4bf3e61d081b..1a711679d26a 100644
> --- a/drivers/staging/media/meson/vdec/vdec_helpers.h
> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
> @@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
>  u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
>  void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
>  
> -u32 amvdec_am21c_body_size(u32 width, u32 height);
> -u32 amvdec_am21c_head_size(u32 width, u32 height);
> -u32 amvdec_am21c_size(u32 width, u32 height);
> +/* Helpers for the Amlogic compressed framebuffer format */
> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
> +u32 amvdec_amfbc_head_size(u32 width, u32 height);
> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>  
>  /**
>   * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
> @@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>   * @width: picture width detected by the hardware
>   * @height: picture height detected by the hardware
>   * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
> + * @bitdepth: Bit depth (usually 10 or 8) of the coded content
>   */
>  void amvdec_src_change(struct amvdec_session *sess, u32 width,
> -		       u32 height, u32 dpb_size);
> +		       u32 height, u32 dpb_size, u32 bitdepth);
>  
>  /**
>   * amvdec_abort() - Abort the current decoding session


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Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Nicolas Dufresne]

Hi,

Le mardi 24 janvier 2023 à 03:40 +0000, Christian Hewitt a écrit :
> From: Benjamin Roszak <benjamin545@gmail.com>
> 
> In order to support 10bit bitstream decoding, buffers and MMU
> handling must be cleaned up to support either downscale output
> from compressed 10bit decoding to uncompressed 8bit NV12 output
> or to compressed 10bit proprietary encoded frame format.

I understand this is step forward, and agree with the patches in general, though
I'd like to know if we can expect 10bit secondary buffers in the future ? Or is
the AMFBC that only 10bit format supported ? Should be expect the 10bit format
definition to be added later ?

> 
> For that, "am21c" name is moved to "amfbc" to reflect the upstream
> Amlogic Compressed framebuffer modifier naming.
> 
> Compressed frame buffers allocation is also cleaned up so it
> can be shared with the HEVC decoder implementation.
> 
> Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
> ---
>  drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
>  .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
>  .../media/meson/vdec/codec_hevc_common.h      |   3 +-
>  drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
>  drivers/staging/media/meson/vdec/esparser.c   |   1 +
>  drivers/staging/media/meson/vdec/vdec.h       |   1 +
>  .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
>  .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
>  8 files changed, 161 insertions(+), 97 deletions(-)
> 
> diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
> index c61128fc4bb9..d53c9a464bde 100644
> --- a/drivers/staging/media/meson/vdec/codec_h264.c
> +++ b/drivers/staging/media/meson/vdec/codec_h264.c
> @@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
>  		frame_width, frame_height, crop_right, crop_bottom);
>  
>  	codec_h264_set_par(sess);
> -	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
> +	amvdec_src_change(sess, frame_width, frame_height,
> +			  h264->max_refs + 5, 8);
>  }
>  
>  /*
> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
> index 0315cc0911cd..1c74b4837dcb 100644
> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
> @@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
>  void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>  {
>  	struct amvdec_core *core = sess->core;
> -	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
> -	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
> +	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
> +					 sess->pixfmt_cap, is_10bit);
> +	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
> +					       is_10bit, use_mmu);
> +	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
>  
>  	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
>  		/* Enable 2-plane reference read mode */
> @@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>  		return;
>  	}
>  
> +	/* enable mem saving mode for 8-bit */
> +	if (!is_10bit)
> +		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
> +	else
> +		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
> +
>  	if (codec_hevc_use_mmu(core->platform->revision,
>  			       sess->pixfmt_cap, is_10bit))
>  		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
> +	else if (!is_10bit)
> +		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
>  	else
>  		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
>  
> @@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
>  
>  		idx = vb->index;
>  
> -		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
> +		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
>  			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>  		else
>  			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
> @@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>  {
>  	struct amvdec_core *core = sess->core;
>  	struct v4l2_m2m_buffer *buf;
> -	u32 revision = core->platform->revision;
>  	u32 pixfmt_cap = sess->pixfmt_cap;
> +	const u32 revision = core->platform->revision;
>  	int i;
>  
>  	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
> @@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>  		dma_addr_t buf_uv_paddr = 0;
>  		u32 idx = vb->index;
>  
> -		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
> -			buf_y_paddr = comm->mmu_header_paddr[idx];
> -		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
> -			buf_y_paddr = comm->fbc_buffer_paddr[idx];
> -		else
> +		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
> +			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
> +				buf_y_paddr = comm->mmu_header_paddr[idx];
> +			else
> +				buf_y_paddr = comm->fbc_buffer_paddr[idx];
> +		} else {
>  			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
> +		}
>  
>  		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
>  				 buf_y_paddr >> 5);
> @@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>  		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
>  }
>  
> -void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
> +void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>  				 struct codec_hevc_common *comm)
>  {
>  	struct device *dev = sess->core->dev;
> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>  	int i;
>  
>  	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
> -		if (comm->fbc_buffer_vaddr[i]) {
> -			dma_free_coherent(dev, am21_size,
> -					  comm->fbc_buffer_vaddr[i],
> -					  comm->fbc_buffer_paddr[i]);
> -			comm->fbc_buffer_vaddr[i] = NULL;
> +		if (comm->mmu_header_vaddr[i]) {
> +			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> +					  comm->mmu_header_vaddr[i],
> +					  comm->mmu_header_paddr[i]);
> +			comm->mmu_header_vaddr[i] = NULL;
>  		}
>  	}
>  }
> -EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
> +EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>  
> -static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
> +static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>  					struct codec_hevc_common *comm)
>  {
>  	struct device *dev = sess->core->dev;
>  	struct v4l2_m2m_buffer *buf;
> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>  
>  	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>  		u32 idx = buf->vb.vb2_buf.index;
>  		dma_addr_t paddr;
> -		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
> -						 GFP_KERNEL);
> +		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> +						 &paddr, GFP_KERNEL);
>  		if (!vaddr) {
> -			codec_hevc_free_fbc_buffers(sess, comm);
> +			codec_hevc_free_mmu_headers(sess, comm);
>  			return -ENOMEM;
>  		}
>  
> -		comm->fbc_buffer_vaddr[idx] = vaddr;
> -		comm->fbc_buffer_paddr[idx] = paddr;
> +		comm->mmu_header_vaddr[idx] = vaddr;
> +		comm->mmu_header_paddr[idx] = paddr;
>  	}
>  
>  	return 0;
>  }
>  
> -void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
> +void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>  				 struct codec_hevc_common *comm)
>  {
>  	struct device *dev = sess->core->dev;
> +	u32 use_mmu;
> +	u32 am21_size;
>  	int i;
>  
> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
> +				     sess->pixfmt_cap,
> +				sess->bitdepth == 10 ? 1 : 0);
> +
> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
> +				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
> +
>  	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
> -		if (comm->mmu_header_vaddr[i]) {
> -			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> -					  comm->mmu_header_vaddr[i],
> -					  comm->mmu_header_paddr[i]);
> -			comm->mmu_header_vaddr[i] = NULL;
> +		if (comm->fbc_buffer_vaddr[i]) {
> +			dma_free_coherent(dev, am21_size,
> +					  comm->fbc_buffer_vaddr[i],
> +					  comm->fbc_buffer_paddr[i]);
> +			comm->fbc_buffer_vaddr[i] = NULL;
>  		}
>  	}
>  
> @@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>  				  comm->mmu_map_paddr);
>  		comm->mmu_map_vaddr = NULL;
>  	}
> +
> +	codec_hevc_free_mmu_headers(sess, comm);
>  }
> -EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
> +EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>  
> -static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
> +static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>  					struct codec_hevc_common *comm)
>  {
>  	struct device *dev = sess->core->dev;
>  	struct v4l2_m2m_buffer *buf;
> +	u32 use_mmu;
> +	u32 am21_size;
> +	const u32 revision = sess->core->platform->revision;
> +	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
> +	int ret;
>  
> -	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
> -						 &comm->mmu_map_paddr,
> -						 GFP_KERNEL);
> -	if (!comm->mmu_map_vaddr)
> -		return -ENOMEM;
> +	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
> +				     is_10bit);
> +
> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
> +				      is_10bit, use_mmu);
>  
>  	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>  		u32 idx = buf->vb.vb2_buf.index;
>  		dma_addr_t paddr;
> -		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> -						 &paddr, GFP_KERNEL);
> +
> +		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
> +						 GFP_KERNEL);
>  		if (!vaddr) {
> -			codec_hevc_free_mmu_headers(sess, comm);
> +			codec_hevc_free_fbc_buffers(sess, comm);
>  			return -ENOMEM;
>  		}
>  
> -		comm->mmu_header_vaddr[idx] = vaddr;
> -		comm->mmu_header_paddr[idx] = paddr;
> +		comm->fbc_buffer_vaddr[idx] = vaddr;
> +		comm->fbc_buffer_paddr[idx] = paddr;
> +	}
> +
> +	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> +		ret = codec_hevc_alloc_mmu_headers(sess, comm);
> +		if (ret) {
> +			codec_hevc_free_fbc_buffers(sess, comm);
> +			return ret;
> +		}
>  	}
>  
>  	return 0;
> @@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>  			     int is_10bit)
>  {
>  	struct amvdec_core *core = sess->core;
> +	struct device *dev = core->dev;
>  	int ret;
>  
> -	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> -		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
> -		if (ret)
> -			return ret;
> +	if (codec_hevc_use_mmu(core->platform->revision,
> +			       sess->pixfmt_cap, is_10bit)) {
> +		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
> +							 &comm->mmu_map_paddr,
> +							 GFP_KERNEL);
> +		if (!comm->mmu_map_vaddr)
> +			return -ENOMEM;
>  	}
>  
>  	if (codec_hevc_use_mmu(core->platform->revision,
> -			       sess->pixfmt_cap, is_10bit)) {
> -		ret = codec_hevc_alloc_mmu_headers(sess, comm);
> -		if (ret) {
> -			codec_hevc_free_fbc_buffers(sess, comm);
> +			       sess->pixfmt_cap, is_10bit) ||
> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> +		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
> +		if (ret)
>  			return ret;
> -		}
>  	}
>  
>  	if (core->platform->revision == VDEC_REVISION_GXBB)
> @@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
>  
>  void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>  			     struct codec_hevc_common *comm,
> -			     struct vb2_buffer *vb)
> +			     struct vb2_buffer *vb,
> +			     u32 is_10bit)
>  {
> -	u32 size = amvdec_am21c_size(sess->width, sess->height);
> -	u32 nb_pages = size / PAGE_SIZE;
> +	u32 use_mmu;
> +	u32 size;
> +	u32 nb_pages;
>  	u32 *mmu_map = comm->mmu_map_vaddr;
>  	u32 first_page;
>  	u32 i;
>  
> -	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
> -		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
> -	else
> -		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
> +				     sess->pixfmt_cap, is_10bit);
> +
> +	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
> +				 use_mmu);
>  
> +	nb_pages = size / PAGE_SIZE;
> +	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>  	for (i = 0; i < nb_pages; ++i)
>  		mmu_map[i] = first_page + i;
>  }
> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
> index cf072b8a9da2..13f9f1d90a94 100644
> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
> @@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>  
>  void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>  			     struct codec_hevc_common *comm,
> -			     struct vb2_buffer *vb);
> +			     struct vb2_buffer *vb,
> +			     u32 is_10bit);
>  
>  #endif
> diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
> index 394df5761556..8e3bbf0db4b3 100644
> --- a/drivers/staging/media/meson/vdec/codec_vp9.c
> +++ b/drivers/staging/media/meson/vdec/codec_vp9.c
> @@ -458,12 +458,6 @@ struct codec_vp9 {
>  	struct list_head ref_frames_list;
>  	u32 frames_num;
>  
> -	/* In case of downsampling (decoding with FBC but outputting in NV12M),
> -	 * we need to allocate additional buffers for FBC.
> -	 */
> -	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
> -	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
> -
>  	int ref_frame_map[REF_FRAMES];
>  	int next_ref_frame_map[REF_FRAMES];
>  	struct vp9_frame *frame_refs[REFS_PER_FRAME];
> @@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>  		buf_y_paddr =
>  		       vb2_dma_contig_plane_dma_addr(vb, 0);
>  
> -	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
> -		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
> -		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
> +	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
>  		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
> -	}
>  
>  	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
>  		buf_y_paddr =
> @@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>  
>  	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>  			       vp9->is_10bit)) {
> -		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
> -				 vp9->common.mmu_header_paddr[vb->index]);
> +		dma_addr_t header_adr;
> +
> +		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
> +			header_adr = vp9->common.mmu_header_paddr[vb->index];
> +		else
> +			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
> +		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
>  		/* use HEVC_CM_HEADER_START_ADDR */
>  		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
>  	}
> @@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>  {
>  	struct amvdec_core *core = sess->core;
>  	u32 scale = 0;
> +	u32 use_mmu;
>  	u32 sz;
>  	int i;
>  
> +	use_mmu = codec_hevc_use_mmu(core->platform->revision,
> +				     sess->pixfmt_cap, vp9->is_10bit);
> +
>  	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
>  	codec_vp9_set_refs(sess, vp9);
>  	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
> @@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>  		    vp9->frame_refs[i]->height != vp9->height)
>  			scale = 1;
>  
> -		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
> -					    vp9->frame_refs[i]->height);
> +		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
> +					    vp9->frame_refs[i]->height,
> +					    vp9->is_10bit, use_mmu);
>  
>  		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
>  				 vp9->frame_refs[i]->width);
> @@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
>  	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>  			       vp9->is_10bit))
>  		codec_hevc_fill_mmu_map(sess, &vp9->common,
> -					&vp9->cur_frame->vbuf->vb2_buf);
> +					&vp9->cur_frame->vbuf->vb2_buf,
> +					vp9->is_10bit);
>  
>  	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
>  
> @@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
>  
>  	codec_vp9_fetch_rpm(sess);
>  	if (codec_vp9_process_rpm(vp9)) {
> -		amvdec_src_change(sess, vp9->width, vp9->height, 16);
> +		amvdec_src_change(sess, vp9->width, vp9->height, 16,
> +				  vp9->is_10bit ? 10 : 8);
>  
>  		/* No frame is actually processed */
>  		vp9->cur_frame = NULL;
> diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
> index 1904d58875ad..3cd29ab4f979 100644
> --- a/drivers/staging/media/meson/vdec/esparser.c
> +++ b/drivers/staging/media/meson/vdec/esparser.c
> @@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
>  		if (esparser_vififo_get_free_space(sess) < payload_size ||
>  		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
>  			return -EAGAIN;
> +
>  	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
>  		return -EAGAIN;
>  	}
> diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
> index 0906b8fb5cc6..a48170fe4cff 100644
> --- a/drivers/staging/media/meson/vdec/vdec.h
> +++ b/drivers/staging/media/meson/vdec/vdec.h
> @@ -244,6 +244,7 @@ struct amvdec_session {
>  	u32 width;
>  	u32 height;
>  	u32 colorspace;
> +	u32 bitdepth;
>  	u8 ycbcr_enc;
>  	u8 quantization;
>  	u8 xfer_func;
> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
> index 7d2a75653250..fef76142f0c5 100644
> --- a/drivers/staging/media/meson/vdec/vdec_helpers.c
> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
> @@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
>  }
>  EXPORT_SYMBOL_GPL(amvdec_write_parser);
>  
> -/* 4 KiB per 64x32 block */
> -u32 amvdec_am21c_body_size(u32 width, u32 height)
> +/* AMFBC body is made out of 64x32 blocks with varying block size */
> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>  {
>  	u32 width_64 = ALIGN(width, 64) / 64;
>  	u32 height_32 = ALIGN(height, 32) / 32;
> +	u32 blk_size = 4096;
>  
> -	return SZ_4K * width_64 * height_32;
> +	if (!is_10bit) {
> +		if (use_mmu)
> +			blk_size = 3200;
> +		else
> +			blk_size = 3072;
> +	}
> +
> +	return blk_size * width_64 * height_32;
>  }
> -EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
> +EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
>  
>  /* 32 bytes per 128x64 block */
> -u32 amvdec_am21c_head_size(u32 width, u32 height)
> +u32 amvdec_amfbc_head_size(u32 width, u32 height)
>  {
>  	u32 width_128 = ALIGN(width, 128) / 128;
>  	u32 height_64 = ALIGN(height, 64) / 64;
>  
>  	return 32 * width_128 * height_64;
>  }
> -EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
> +EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
>  
> -u32 amvdec_am21c_size(u32 width, u32 height)
> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>  {
> -	return ALIGN(amvdec_am21c_body_size(width, height) +
> -		     amvdec_am21c_head_size(width, height), SZ_64K);
> +	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
> +		     amvdec_amfbc_head_size(width, height), SZ_64K);
>  }
> -EXPORT_SYMBOL_GPL(amvdec_am21c_size);
> +EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
>  
>  static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
>  {
> @@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>  EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
>  
>  void amvdec_src_change(struct amvdec_session *sess, u32 width,
> -		       u32 height, u32 dpb_size)
> +		       u32 height, u32 dpb_size, u32 bitdepth)
>  {
>  	static const struct v4l2_event ev = {
>  		.type = V4L2_EVENT_SOURCE_CHANGE,
> @@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
>  
>  	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
>  
> +	sess->bitdepth = bitdepth;
> +
>  	/*
>  	 * Check if the capture queue is already configured well for our
> -	 * usecase. If so, keep decoding with it and do not send the event
> +	 * usecase. If so, keep decoding with it.
>  	 */
>  	if (sess->streamon_cap &&
>  	    sess->width == width &&
>  	    sess->height == height &&
>  	    dpb_size <= sess->num_dst_bufs) {
>  		sess->fmt_out->codec_ops->resume(sess);
> -		return;
> +	} else {
> +		sess->status = STATUS_NEEDS_RESUME;
> +		sess->changed_format = 0;
>  	}
>  
> -	sess->changed_format = 0;
>  	sess->width = width;
>  	sess->height = height;
> -	sess->status = STATUS_NEEDS_RESUME;
>  
> -	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
> -		width, height, dpb_size);
> +	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
> +		width, height, dpb_size, bitdepth);
>  	v4l2_event_queue_fh(&sess->fh, &ev);
>  }
>  EXPORT_SYMBOL_GPL(amvdec_src_change);
> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
> index 4bf3e61d081b..1a711679d26a 100644
> --- a/drivers/staging/media/meson/vdec/vdec_helpers.h
> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
> @@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
>  u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
>  void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
>  
> -u32 amvdec_am21c_body_size(u32 width, u32 height);
> -u32 amvdec_am21c_head_size(u32 width, u32 height);
> -u32 amvdec_am21c_size(u32 width, u32 height);
> +/* Helpers for the Amlogic compressed framebuffer format */
> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
> +u32 amvdec_amfbc_head_size(u32 width, u32 height);
> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>  
>  /**
>   * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
> @@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>   * @width: picture width detected by the hardware
>   * @height: picture height detected by the hardware
>   * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
> + * @bitdepth: Bit depth (usually 10 or 8) of the coded content
>   */
>  void amvdec_src_change(struct amvdec_session *sess, u32 width,
> -		       u32 height, u32 dpb_size);
> +		       u32 height, u32 dpb_size, u32 bitdepth);
>  
>  /**
>   * amvdec_abort() - Abort the current decoding session


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Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Neil Armstrong]

On 24/01/2023 16:21, Nicolas Dufresne wrote:
> Hi,
> 
> Le mardi 24 janvier 2023 à 03:40 +0000, Christian Hewitt a écrit :
>> From: Benjamin Roszak <benjamin545@gmail.com>
>>
>> In order to support 10bit bitstream decoding, buffers and MMU
>> handling must be cleaned up to support either downscale output
>> from compressed 10bit decoding to uncompressed 8bit NV12 output
>> or to compressed 10bit proprietary encoded frame format.
> 
> I understand this is step forward, and agree with the patches in general, though
> I'd like to know if we can expect 10bit secondary buffers in the future ? Or is
> the AMFBC that only 10bit format supported ? Should be expect the 10bit format
> definition to be added later ?

The support exist, but it stopped when nobody aggreed on how to handle the different
layouts generated by the decoder.

There's at least 4 possible layouts vs how we represent then in DRM :
- GX 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
- GX 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
- G12 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,AMLOGIC_FBC_OPTION_MEM_SAVING)
- G12 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC()AMLOGIC_FBC_LAYOUT_SCATTER, AMLOGIC_FBC_OPTION_MEM_SAVING)

And probably more depending on new SoCs and new codecs.

Neil

> 
>>
>> For that, "am21c" name is moved to "amfbc" to reflect the upstream
>> Amlogic Compressed framebuffer modifier naming.
>>
>> Compressed frame buffers allocation is also cleaned up so it
>> can be shared with the HEVC decoder implementation.
>>
>> Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
>> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
>> ---
>>   drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
>>   .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
>>   .../media/meson/vdec/codec_hevc_common.h      |   3 +-
>>   drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
>>   drivers/staging/media/meson/vdec/esparser.c   |   1 +
>>   drivers/staging/media/meson/vdec/vdec.h       |   1 +
>>   .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
>>   .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
>>   8 files changed, 161 insertions(+), 97 deletions(-)
>>
>> diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
>> index c61128fc4bb9..d53c9a464bde 100644
>> --- a/drivers/staging/media/meson/vdec/codec_h264.c
>> +++ b/drivers/staging/media/meson/vdec/codec_h264.c
>> @@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
>>   		frame_width, frame_height, crop_right, crop_bottom);
>>   
>>   	codec_h264_set_par(sess);
>> -	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
>> +	amvdec_src_change(sess, frame_width, frame_height,
>> +			  h264->max_refs + 5, 8);
>>   }
>>   
>>   /*
>> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
>> index 0315cc0911cd..1c74b4837dcb 100644
>> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
>> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
>> @@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
>>   void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>>   {
>>   	struct amvdec_core *core = sess->core;
>> -	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
>> -	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
>> +	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
>> +					 sess->pixfmt_cap, is_10bit);
>> +	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
>> +					       is_10bit, use_mmu);
>> +	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
>>   
>>   	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
>>   		/* Enable 2-plane reference read mode */
>> @@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>>   		return;
>>   	}
>>   
>> +	/* enable mem saving mode for 8-bit */
>> +	if (!is_10bit)
>> +		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
>> +	else
>> +		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
>> +
>>   	if (codec_hevc_use_mmu(core->platform->revision,
>>   			       sess->pixfmt_cap, is_10bit))
>>   		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
>> +	else if (!is_10bit)
>> +		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
>>   	else
>>   		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
>>   
>> @@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
>>   
>>   		idx = vb->index;
>>   
>> -		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
>> +		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
>>   			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>>   		else
>>   			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
>> @@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>   {
>>   	struct amvdec_core *core = sess->core;
>>   	struct v4l2_m2m_buffer *buf;
>> -	u32 revision = core->platform->revision;
>>   	u32 pixfmt_cap = sess->pixfmt_cap;
>> +	const u32 revision = core->platform->revision;
>>   	int i;
>>   
>>   	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
>> @@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>   		dma_addr_t buf_uv_paddr = 0;
>>   		u32 idx = vb->index;
>>   
>> -		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
>> -			buf_y_paddr = comm->mmu_header_paddr[idx];
>> -		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
>> -			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>> -		else
>> +		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
>> +			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
>> +				buf_y_paddr = comm->mmu_header_paddr[idx];
>> +			else
>> +				buf_y_paddr = comm->fbc_buffer_paddr[idx];
>> +		} else {
>>   			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
>> +		}
>>   
>>   		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
>>   				 buf_y_paddr >> 5);
>> @@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>   		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
>>   }
>>   
>> -void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>> +void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>   				 struct codec_hevc_common *comm)
>>   {
>>   	struct device *dev = sess->core->dev;
>> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>>   	int i;
>>   
>>   	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
>> -		if (comm->fbc_buffer_vaddr[i]) {
>> -			dma_free_coherent(dev, am21_size,
>> -					  comm->fbc_buffer_vaddr[i],
>> -					  comm->fbc_buffer_paddr[i]);
>> -			comm->fbc_buffer_vaddr[i] = NULL;
>> +		if (comm->mmu_header_vaddr[i]) {
>> +			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>> +					  comm->mmu_header_vaddr[i],
>> +					  comm->mmu_header_paddr[i]);
>> +			comm->mmu_header_vaddr[i] = NULL;
>>   		}
>>   	}
>>   }
>> -EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>> +EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>>   
>> -static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>> +static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>>   					struct codec_hevc_common *comm)
>>   {
>>   	struct device *dev = sess->core->dev;
>>   	struct v4l2_m2m_buffer *buf;
>> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>>   
>>   	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>>   		u32 idx = buf->vb.vb2_buf.index;
>>   		dma_addr_t paddr;
>> -		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
>> -						 GFP_KERNEL);
>> +		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>> +						 &paddr, GFP_KERNEL);
>>   		if (!vaddr) {
>> -			codec_hevc_free_fbc_buffers(sess, comm);
>> +			codec_hevc_free_mmu_headers(sess, comm);
>>   			return -ENOMEM;
>>   		}
>>   
>> -		comm->fbc_buffer_vaddr[idx] = vaddr;
>> -		comm->fbc_buffer_paddr[idx] = paddr;
>> +		comm->mmu_header_vaddr[idx] = vaddr;
>> +		comm->mmu_header_paddr[idx] = paddr;
>>   	}
>>   
>>   	return 0;
>>   }
>>   
>> -void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>> +void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>>   				 struct codec_hevc_common *comm)
>>   {
>>   	struct device *dev = sess->core->dev;
>> +	u32 use_mmu;
>> +	u32 am21_size;
>>   	int i;
>>   
>> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
>> +				     sess->pixfmt_cap,
>> +				sess->bitdepth == 10 ? 1 : 0);
>> +
>> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
>> +				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
>> +
>>   	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
>> -		if (comm->mmu_header_vaddr[i]) {
>> -			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>> -					  comm->mmu_header_vaddr[i],
>> -					  comm->mmu_header_paddr[i]);
>> -			comm->mmu_header_vaddr[i] = NULL;
>> +		if (comm->fbc_buffer_vaddr[i]) {
>> +			dma_free_coherent(dev, am21_size,
>> +					  comm->fbc_buffer_vaddr[i],
>> +					  comm->fbc_buffer_paddr[i]);
>> +			comm->fbc_buffer_vaddr[i] = NULL;
>>   		}
>>   	}
>>   
>> @@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>   				  comm->mmu_map_paddr);
>>   		comm->mmu_map_vaddr = NULL;
>>   	}
>> +
>> +	codec_hevc_free_mmu_headers(sess, comm);
>>   }
>> -EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>> +EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>>   
>> -static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>> +static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>>   					struct codec_hevc_common *comm)
>>   {
>>   	struct device *dev = sess->core->dev;
>>   	struct v4l2_m2m_buffer *buf;
>> +	u32 use_mmu;
>> +	u32 am21_size;
>> +	const u32 revision = sess->core->platform->revision;
>> +	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
>> +	int ret;
>>   
>> -	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
>> -						 &comm->mmu_map_paddr,
>> -						 GFP_KERNEL);
>> -	if (!comm->mmu_map_vaddr)
>> -		return -ENOMEM;
>> +	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
>> +				     is_10bit);
>> +
>> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
>> +				      is_10bit, use_mmu);
>>   
>>   	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>>   		u32 idx = buf->vb.vb2_buf.index;
>>   		dma_addr_t paddr;
>> -		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>> -						 &paddr, GFP_KERNEL);
>> +
>> +		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
>> +						 GFP_KERNEL);
>>   		if (!vaddr) {
>> -			codec_hevc_free_mmu_headers(sess, comm);
>> +			codec_hevc_free_fbc_buffers(sess, comm);
>>   			return -ENOMEM;
>>   		}
>>   
>> -		comm->mmu_header_vaddr[idx] = vaddr;
>> -		comm->mmu_header_paddr[idx] = paddr;
>> +		comm->fbc_buffer_vaddr[idx] = vaddr;
>> +		comm->fbc_buffer_paddr[idx] = paddr;
>> +	}
>> +
>> +	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
>> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>> +		ret = codec_hevc_alloc_mmu_headers(sess, comm);
>> +		if (ret) {
>> +			codec_hevc_free_fbc_buffers(sess, comm);
>> +			return ret;
>> +		}
>>   	}
>>   
>>   	return 0;
>> @@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>>   			     int is_10bit)
>>   {
>>   	struct amvdec_core *core = sess->core;
>> +	struct device *dev = core->dev;
>>   	int ret;
>>   
>> -	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>> -		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
>> -		if (ret)
>> -			return ret;
>> +	if (codec_hevc_use_mmu(core->platform->revision,
>> +			       sess->pixfmt_cap, is_10bit)) {
>> +		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
>> +							 &comm->mmu_map_paddr,
>> +							 GFP_KERNEL);
>> +		if (!comm->mmu_map_vaddr)
>> +			return -ENOMEM;
>>   	}
>>   
>>   	if (codec_hevc_use_mmu(core->platform->revision,
>> -			       sess->pixfmt_cap, is_10bit)) {
>> -		ret = codec_hevc_alloc_mmu_headers(sess, comm);
>> -		if (ret) {
>> -			codec_hevc_free_fbc_buffers(sess, comm);
>> +			       sess->pixfmt_cap, is_10bit) ||
>> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>> +		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
>> +		if (ret)
>>   			return ret;
>> -		}
>>   	}
>>   
>>   	if (core->platform->revision == VDEC_REVISION_GXBB)
>> @@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
>>   
>>   void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>>   			     struct codec_hevc_common *comm,
>> -			     struct vb2_buffer *vb)
>> +			     struct vb2_buffer *vb,
>> +			     u32 is_10bit)
>>   {
>> -	u32 size = amvdec_am21c_size(sess->width, sess->height);
>> -	u32 nb_pages = size / PAGE_SIZE;
>> +	u32 use_mmu;
>> +	u32 size;
>> +	u32 nb_pages;
>>   	u32 *mmu_map = comm->mmu_map_vaddr;
>>   	u32 first_page;
>>   	u32 i;
>>   
>> -	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
>> -		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>> -	else
>> -		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
>> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
>> +				     sess->pixfmt_cap, is_10bit);
>> +
>> +	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
>> +				 use_mmu);
>>   
>> +	nb_pages = size / PAGE_SIZE;
>> +	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>>   	for (i = 0; i < nb_pages; ++i)
>>   		mmu_map[i] = first_page + i;
>>   }
>> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
>> index cf072b8a9da2..13f9f1d90a94 100644
>> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
>> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
>> @@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>>   
>>   void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>>   			     struct codec_hevc_common *comm,
>> -			     struct vb2_buffer *vb);
>> +			     struct vb2_buffer *vb,
>> +			     u32 is_10bit);
>>   
>>   #endif
>> diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
>> index 394df5761556..8e3bbf0db4b3 100644
>> --- a/drivers/staging/media/meson/vdec/codec_vp9.c
>> +++ b/drivers/staging/media/meson/vdec/codec_vp9.c
>> @@ -458,12 +458,6 @@ struct codec_vp9 {
>>   	struct list_head ref_frames_list;
>>   	u32 frames_num;
>>   
>> -	/* In case of downsampling (decoding with FBC but outputting in NV12M),
>> -	 * we need to allocate additional buffers for FBC.
>> -	 */
>> -	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
>> -	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
>> -
>>   	int ref_frame_map[REF_FRAMES];
>>   	int next_ref_frame_map[REF_FRAMES];
>>   	struct vp9_frame *frame_refs[REFS_PER_FRAME];
>> @@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>>   		buf_y_paddr =
>>   		       vb2_dma_contig_plane_dma_addr(vb, 0);
>>   
>> -	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
>> -		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
>> -		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
>> +	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
>>   		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
>> -	}
>>   
>>   	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
>>   		buf_y_paddr =
>> @@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>>   
>>   	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>>   			       vp9->is_10bit)) {
>> -		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
>> -				 vp9->common.mmu_header_paddr[vb->index]);
>> +		dma_addr_t header_adr;
>> +
>> +		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
>> +			header_adr = vp9->common.mmu_header_paddr[vb->index];
>> +		else
>> +			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
>> +		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
>>   		/* use HEVC_CM_HEADER_START_ADDR */
>>   		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
>>   	}
>> @@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>>   {
>>   	struct amvdec_core *core = sess->core;
>>   	u32 scale = 0;
>> +	u32 use_mmu;
>>   	u32 sz;
>>   	int i;
>>   
>> +	use_mmu = codec_hevc_use_mmu(core->platform->revision,
>> +				     sess->pixfmt_cap, vp9->is_10bit);
>> +
>>   	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
>>   	codec_vp9_set_refs(sess, vp9);
>>   	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
>> @@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>>   		    vp9->frame_refs[i]->height != vp9->height)
>>   			scale = 1;
>>   
>> -		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
>> -					    vp9->frame_refs[i]->height);
>> +		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
>> +					    vp9->frame_refs[i]->height,
>> +					    vp9->is_10bit, use_mmu);
>>   
>>   		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
>>   				 vp9->frame_refs[i]->width);
>> @@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
>>   	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>>   			       vp9->is_10bit))
>>   		codec_hevc_fill_mmu_map(sess, &vp9->common,
>> -					&vp9->cur_frame->vbuf->vb2_buf);
>> +					&vp9->cur_frame->vbuf->vb2_buf,
>> +					vp9->is_10bit);
>>   
>>   	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
>>   
>> @@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
>>   
>>   	codec_vp9_fetch_rpm(sess);
>>   	if (codec_vp9_process_rpm(vp9)) {
>> -		amvdec_src_change(sess, vp9->width, vp9->height, 16);
>> +		amvdec_src_change(sess, vp9->width, vp9->height, 16,
>> +				  vp9->is_10bit ? 10 : 8);
>>   
>>   		/* No frame is actually processed */
>>   		vp9->cur_frame = NULL;
>> diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
>> index 1904d58875ad..3cd29ab4f979 100644
>> --- a/drivers/staging/media/meson/vdec/esparser.c
>> +++ b/drivers/staging/media/meson/vdec/esparser.c
>> @@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
>>   		if (esparser_vififo_get_free_space(sess) < payload_size ||
>>   		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
>>   			return -EAGAIN;
>> +
>>   	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
>>   		return -EAGAIN;
>>   	}
>> diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
>> index 0906b8fb5cc6..a48170fe4cff 100644
>> --- a/drivers/staging/media/meson/vdec/vdec.h
>> +++ b/drivers/staging/media/meson/vdec/vdec.h
>> @@ -244,6 +244,7 @@ struct amvdec_session {
>>   	u32 width;
>>   	u32 height;
>>   	u32 colorspace;
>> +	u32 bitdepth;
>>   	u8 ycbcr_enc;
>>   	u8 quantization;
>>   	u8 xfer_func;
>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
>> index 7d2a75653250..fef76142f0c5 100644
>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.c
>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
>> @@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
>>   }
>>   EXPORT_SYMBOL_GPL(amvdec_write_parser);
>>   
>> -/* 4 KiB per 64x32 block */
>> -u32 amvdec_am21c_body_size(u32 width, u32 height)
>> +/* AMFBC body is made out of 64x32 blocks with varying block size */
>> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>>   {
>>   	u32 width_64 = ALIGN(width, 64) / 64;
>>   	u32 height_32 = ALIGN(height, 32) / 32;
>> +	u32 blk_size = 4096;
>>   
>> -	return SZ_4K * width_64 * height_32;
>> +	if (!is_10bit) {
>> +		if (use_mmu)
>> +			blk_size = 3200;
>> +		else
>> +			blk_size = 3072;
>> +	}
>> +
>> +	return blk_size * width_64 * height_32;
>>   }
>> -EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
>>   
>>   /* 32 bytes per 128x64 block */
>> -u32 amvdec_am21c_head_size(u32 width, u32 height)
>> +u32 amvdec_amfbc_head_size(u32 width, u32 height)
>>   {
>>   	u32 width_128 = ALIGN(width, 128) / 128;
>>   	u32 height_64 = ALIGN(height, 64) / 64;
>>   
>>   	return 32 * width_128 * height_64;
>>   }
>> -EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
>>   
>> -u32 amvdec_am21c_size(u32 width, u32 height)
>> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>>   {
>> -	return ALIGN(amvdec_am21c_body_size(width, height) +
>> -		     amvdec_am21c_head_size(width, height), SZ_64K);
>> +	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
>> +		     amvdec_amfbc_head_size(width, height), SZ_64K);
>>   }
>> -EXPORT_SYMBOL_GPL(amvdec_am21c_size);
>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
>>   
>>   static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
>>   {
>> @@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>>   EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
>>   
>>   void amvdec_src_change(struct amvdec_session *sess, u32 width,
>> -		       u32 height, u32 dpb_size)
>> +		       u32 height, u32 dpb_size, u32 bitdepth)
>>   {
>>   	static const struct v4l2_event ev = {
>>   		.type = V4L2_EVENT_SOURCE_CHANGE,
>> @@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
>>   
>>   	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
>>   
>> +	sess->bitdepth = bitdepth;
>> +
>>   	/*
>>   	 * Check if the capture queue is already configured well for our
>> -	 * usecase. If so, keep decoding with it and do not send the event
>> +	 * usecase. If so, keep decoding with it.
>>   	 */
>>   	if (sess->streamon_cap &&
>>   	    sess->width == width &&
>>   	    sess->height == height &&
>>   	    dpb_size <= sess->num_dst_bufs) {
>>   		sess->fmt_out->codec_ops->resume(sess);
>> -		return;
>> +	} else {
>> +		sess->status = STATUS_NEEDS_RESUME;
>> +		sess->changed_format = 0;
>>   	}
>>   
>> -	sess->changed_format = 0;
>>   	sess->width = width;
>>   	sess->height = height;
>> -	sess->status = STATUS_NEEDS_RESUME;
>>   
>> -	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
>> -		width, height, dpb_size);
>> +	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
>> +		width, height, dpb_size, bitdepth);
>>   	v4l2_event_queue_fh(&sess->fh, &ev);
>>   }
>>   EXPORT_SYMBOL_GPL(amvdec_src_change);
>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
>> index 4bf3e61d081b..1a711679d26a 100644
>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.h
>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
>> @@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
>>   u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
>>   void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
>>   
>> -u32 amvdec_am21c_body_size(u32 width, u32 height);
>> -u32 amvdec_am21c_head_size(u32 width, u32 height);
>> -u32 amvdec_am21c_size(u32 width, u32 height);
>> +/* Helpers for the Amlogic compressed framebuffer format */
>> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>> +u32 amvdec_amfbc_head_size(u32 width, u32 height);
>> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>>   
>>   /**
>>    * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
>> @@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>>    * @width: picture width detected by the hardware
>>    * @height: picture height detected by the hardware
>>    * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
>> + * @bitdepth: Bit depth (usually 10 or 8) of the coded content
>>    */
>>   void amvdec_src_change(struct amvdec_session *sess, u32 width,
>> -		       u32 height, u32 dpb_size);
>> +		       u32 height, u32 dpb_size, u32 bitdepth);
>>   
>>   /**
>>    * amvdec_abort() - Abort the current decoding session
> 

Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Neil Armstrong]

On 24/01/2023 16:21, Nicolas Dufresne wrote:
> Hi,
> 
> Le mardi 24 janvier 2023 à 03:40 +0000, Christian Hewitt a écrit :
>> From: Benjamin Roszak <benjamin545@gmail.com>
>>
>> In order to support 10bit bitstream decoding, buffers and MMU
>> handling must be cleaned up to support either downscale output
>> from compressed 10bit decoding to uncompressed 8bit NV12 output
>> or to compressed 10bit proprietary encoded frame format.
> 
> I understand this is step forward, and agree with the patches in general, though
> I'd like to know if we can expect 10bit secondary buffers in the future ? Or is
> the AMFBC that only 10bit format supported ? Should be expect the 10bit format
> definition to be added later ?

The support exist, but it stopped when nobody aggreed on how to handle the different
layouts generated by the decoder.

There's at least 4 possible layouts vs how we represent then in DRM :
- GX 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
- GX 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
- G12 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,AMLOGIC_FBC_OPTION_MEM_SAVING)
- G12 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC()AMLOGIC_FBC_LAYOUT_SCATTER, AMLOGIC_FBC_OPTION_MEM_SAVING)

And probably more depending on new SoCs and new codecs.

Neil

> 
>>
>> For that, "am21c" name is moved to "amfbc" to reflect the upstream
>> Amlogic Compressed framebuffer modifier naming.
>>
>> Compressed frame buffers allocation is also cleaned up so it
>> can be shared with the HEVC decoder implementation.
>>
>> Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
>> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
>> ---
>>   drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
>>   .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
>>   .../media/meson/vdec/codec_hevc_common.h      |   3 +-
>>   drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
>>   drivers/staging/media/meson/vdec/esparser.c   |   1 +
>>   drivers/staging/media/meson/vdec/vdec.h       |   1 +
>>   .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
>>   .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
>>   8 files changed, 161 insertions(+), 97 deletions(-)
>>
>> diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
>> index c61128fc4bb9..d53c9a464bde 100644
>> --- a/drivers/staging/media/meson/vdec/codec_h264.c
>> +++ b/drivers/staging/media/meson/vdec/codec_h264.c
>> @@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
>>   		frame_width, frame_height, crop_right, crop_bottom);
>>   
>>   	codec_h264_set_par(sess);
>> -	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
>> +	amvdec_src_change(sess, frame_width, frame_height,
>> +			  h264->max_refs + 5, 8);
>>   }
>>   
>>   /*
>> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
>> index 0315cc0911cd..1c74b4837dcb 100644
>> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
>> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
>> @@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
>>   void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>>   {
>>   	struct amvdec_core *core = sess->core;
>> -	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
>> -	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
>> +	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
>> +					 sess->pixfmt_cap, is_10bit);
>> +	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
>> +					       is_10bit, use_mmu);
>> +	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
>>   
>>   	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
>>   		/* Enable 2-plane reference read mode */
>> @@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>>   		return;
>>   	}
>>   
>> +	/* enable mem saving mode for 8-bit */
>> +	if (!is_10bit)
>> +		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
>> +	else
>> +		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
>> +
>>   	if (codec_hevc_use_mmu(core->platform->revision,
>>   			       sess->pixfmt_cap, is_10bit))
>>   		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
>> +	else if (!is_10bit)
>> +		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
>>   	else
>>   		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
>>   
>> @@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
>>   
>>   		idx = vb->index;
>>   
>> -		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
>> +		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
>>   			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>>   		else
>>   			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
>> @@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>   {
>>   	struct amvdec_core *core = sess->core;
>>   	struct v4l2_m2m_buffer *buf;
>> -	u32 revision = core->platform->revision;
>>   	u32 pixfmt_cap = sess->pixfmt_cap;
>> +	const u32 revision = core->platform->revision;
>>   	int i;
>>   
>>   	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
>> @@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>   		dma_addr_t buf_uv_paddr = 0;
>>   		u32 idx = vb->index;
>>   
>> -		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
>> -			buf_y_paddr = comm->mmu_header_paddr[idx];
>> -		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
>> -			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>> -		else
>> +		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
>> +			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
>> +				buf_y_paddr = comm->mmu_header_paddr[idx];
>> +			else
>> +				buf_y_paddr = comm->fbc_buffer_paddr[idx];
>> +		} else {
>>   			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
>> +		}
>>   
>>   		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
>>   				 buf_y_paddr >> 5);
>> @@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>   		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
>>   }
>>   
>> -void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>> +void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>   				 struct codec_hevc_common *comm)
>>   {
>>   	struct device *dev = sess->core->dev;
>> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>>   	int i;
>>   
>>   	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
>> -		if (comm->fbc_buffer_vaddr[i]) {
>> -			dma_free_coherent(dev, am21_size,
>> -					  comm->fbc_buffer_vaddr[i],
>> -					  comm->fbc_buffer_paddr[i]);
>> -			comm->fbc_buffer_vaddr[i] = NULL;
>> +		if (comm->mmu_header_vaddr[i]) {
>> +			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>> +					  comm->mmu_header_vaddr[i],
>> +					  comm->mmu_header_paddr[i]);
>> +			comm->mmu_header_vaddr[i] = NULL;
>>   		}
>>   	}
>>   }
>> -EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>> +EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>>   
>> -static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>> +static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>>   					struct codec_hevc_common *comm)
>>   {
>>   	struct device *dev = sess->core->dev;
>>   	struct v4l2_m2m_buffer *buf;
>> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>>   
>>   	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>>   		u32 idx = buf->vb.vb2_buf.index;
>>   		dma_addr_t paddr;
>> -		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
>> -						 GFP_KERNEL);
>> +		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>> +						 &paddr, GFP_KERNEL);
>>   		if (!vaddr) {
>> -			codec_hevc_free_fbc_buffers(sess, comm);
>> +			codec_hevc_free_mmu_headers(sess, comm);
>>   			return -ENOMEM;
>>   		}
>>   
>> -		comm->fbc_buffer_vaddr[idx] = vaddr;
>> -		comm->fbc_buffer_paddr[idx] = paddr;
>> +		comm->mmu_header_vaddr[idx] = vaddr;
>> +		comm->mmu_header_paddr[idx] = paddr;
>>   	}
>>   
>>   	return 0;
>>   }
>>   
>> -void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>> +void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>>   				 struct codec_hevc_common *comm)
>>   {
>>   	struct device *dev = sess->core->dev;
>> +	u32 use_mmu;
>> +	u32 am21_size;
>>   	int i;
>>   
>> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
>> +				     sess->pixfmt_cap,
>> +				sess->bitdepth == 10 ? 1 : 0);
>> +
>> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
>> +				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
>> +
>>   	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
>> -		if (comm->mmu_header_vaddr[i]) {
>> -			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>> -					  comm->mmu_header_vaddr[i],
>> -					  comm->mmu_header_paddr[i]);
>> -			comm->mmu_header_vaddr[i] = NULL;
>> +		if (comm->fbc_buffer_vaddr[i]) {
>> +			dma_free_coherent(dev, am21_size,
>> +					  comm->fbc_buffer_vaddr[i],
>> +					  comm->fbc_buffer_paddr[i]);
>> +			comm->fbc_buffer_vaddr[i] = NULL;
>>   		}
>>   	}
>>   
>> @@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>   				  comm->mmu_map_paddr);
>>   		comm->mmu_map_vaddr = NULL;
>>   	}
>> +
>> +	codec_hevc_free_mmu_headers(sess, comm);
>>   }
>> -EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>> +EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>>   
>> -static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>> +static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>>   					struct codec_hevc_common *comm)
>>   {
>>   	struct device *dev = sess->core->dev;
>>   	struct v4l2_m2m_buffer *buf;
>> +	u32 use_mmu;
>> +	u32 am21_size;
>> +	const u32 revision = sess->core->platform->revision;
>> +	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
>> +	int ret;
>>   
>> -	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
>> -						 &comm->mmu_map_paddr,
>> -						 GFP_KERNEL);
>> -	if (!comm->mmu_map_vaddr)
>> -		return -ENOMEM;
>> +	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
>> +				     is_10bit);
>> +
>> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
>> +				      is_10bit, use_mmu);
>>   
>>   	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>>   		u32 idx = buf->vb.vb2_buf.index;
>>   		dma_addr_t paddr;
>> -		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>> -						 &paddr, GFP_KERNEL);
>> +
>> +		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
>> +						 GFP_KERNEL);
>>   		if (!vaddr) {
>> -			codec_hevc_free_mmu_headers(sess, comm);
>> +			codec_hevc_free_fbc_buffers(sess, comm);
>>   			return -ENOMEM;
>>   		}
>>   
>> -		comm->mmu_header_vaddr[idx] = vaddr;
>> -		comm->mmu_header_paddr[idx] = paddr;
>> +		comm->fbc_buffer_vaddr[idx] = vaddr;
>> +		comm->fbc_buffer_paddr[idx] = paddr;
>> +	}
>> +
>> +	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
>> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>> +		ret = codec_hevc_alloc_mmu_headers(sess, comm);
>> +		if (ret) {
>> +			codec_hevc_free_fbc_buffers(sess, comm);
>> +			return ret;
>> +		}
>>   	}
>>   
>>   	return 0;
>> @@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>>   			     int is_10bit)
>>   {
>>   	struct amvdec_core *core = sess->core;
>> +	struct device *dev = core->dev;
>>   	int ret;
>>   
>> -	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>> -		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
>> -		if (ret)
>> -			return ret;
>> +	if (codec_hevc_use_mmu(core->platform->revision,
>> +			       sess->pixfmt_cap, is_10bit)) {
>> +		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
>> +							 &comm->mmu_map_paddr,
>> +							 GFP_KERNEL);
>> +		if (!comm->mmu_map_vaddr)
>> +			return -ENOMEM;
>>   	}
>>   
>>   	if (codec_hevc_use_mmu(core->platform->revision,
>> -			       sess->pixfmt_cap, is_10bit)) {
>> -		ret = codec_hevc_alloc_mmu_headers(sess, comm);
>> -		if (ret) {
>> -			codec_hevc_free_fbc_buffers(sess, comm);
>> +			       sess->pixfmt_cap, is_10bit) ||
>> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>> +		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
>> +		if (ret)
>>   			return ret;
>> -		}
>>   	}
>>   
>>   	if (core->platform->revision == VDEC_REVISION_GXBB)
>> @@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
>>   
>>   void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>>   			     struct codec_hevc_common *comm,
>> -			     struct vb2_buffer *vb)
>> +			     struct vb2_buffer *vb,
>> +			     u32 is_10bit)
>>   {
>> -	u32 size = amvdec_am21c_size(sess->width, sess->height);
>> -	u32 nb_pages = size / PAGE_SIZE;
>> +	u32 use_mmu;
>> +	u32 size;
>> +	u32 nb_pages;
>>   	u32 *mmu_map = comm->mmu_map_vaddr;
>>   	u32 first_page;
>>   	u32 i;
>>   
>> -	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
>> -		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>> -	else
>> -		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
>> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
>> +				     sess->pixfmt_cap, is_10bit);
>> +
>> +	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
>> +				 use_mmu);
>>   
>> +	nb_pages = size / PAGE_SIZE;
>> +	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>>   	for (i = 0; i < nb_pages; ++i)
>>   		mmu_map[i] = first_page + i;
>>   }
>> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
>> index cf072b8a9da2..13f9f1d90a94 100644
>> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
>> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
>> @@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>>   
>>   void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>>   			     struct codec_hevc_common *comm,
>> -			     struct vb2_buffer *vb);
>> +			     struct vb2_buffer *vb,
>> +			     u32 is_10bit);
>>   
>>   #endif
>> diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
>> index 394df5761556..8e3bbf0db4b3 100644
>> --- a/drivers/staging/media/meson/vdec/codec_vp9.c
>> +++ b/drivers/staging/media/meson/vdec/codec_vp9.c
>> @@ -458,12 +458,6 @@ struct codec_vp9 {
>>   	struct list_head ref_frames_list;
>>   	u32 frames_num;
>>   
>> -	/* In case of downsampling (decoding with FBC but outputting in NV12M),
>> -	 * we need to allocate additional buffers for FBC.
>> -	 */
>> -	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
>> -	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
>> -
>>   	int ref_frame_map[REF_FRAMES];
>>   	int next_ref_frame_map[REF_FRAMES];
>>   	struct vp9_frame *frame_refs[REFS_PER_FRAME];
>> @@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>>   		buf_y_paddr =
>>   		       vb2_dma_contig_plane_dma_addr(vb, 0);
>>   
>> -	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
>> -		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
>> -		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
>> +	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
>>   		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
>> -	}
>>   
>>   	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
>>   		buf_y_paddr =
>> @@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>>   
>>   	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>>   			       vp9->is_10bit)) {
>> -		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
>> -				 vp9->common.mmu_header_paddr[vb->index]);
>> +		dma_addr_t header_adr;
>> +
>> +		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
>> +			header_adr = vp9->common.mmu_header_paddr[vb->index];
>> +		else
>> +			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
>> +		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
>>   		/* use HEVC_CM_HEADER_START_ADDR */
>>   		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
>>   	}
>> @@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>>   {
>>   	struct amvdec_core *core = sess->core;
>>   	u32 scale = 0;
>> +	u32 use_mmu;
>>   	u32 sz;
>>   	int i;
>>   
>> +	use_mmu = codec_hevc_use_mmu(core->platform->revision,
>> +				     sess->pixfmt_cap, vp9->is_10bit);
>> +
>>   	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
>>   	codec_vp9_set_refs(sess, vp9);
>>   	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
>> @@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>>   		    vp9->frame_refs[i]->height != vp9->height)
>>   			scale = 1;
>>   
>> -		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
>> -					    vp9->frame_refs[i]->height);
>> +		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
>> +					    vp9->frame_refs[i]->height,
>> +					    vp9->is_10bit, use_mmu);
>>   
>>   		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
>>   				 vp9->frame_refs[i]->width);
>> @@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
>>   	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>>   			       vp9->is_10bit))
>>   		codec_hevc_fill_mmu_map(sess, &vp9->common,
>> -					&vp9->cur_frame->vbuf->vb2_buf);
>> +					&vp9->cur_frame->vbuf->vb2_buf,
>> +					vp9->is_10bit);
>>   
>>   	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
>>   
>> @@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
>>   
>>   	codec_vp9_fetch_rpm(sess);
>>   	if (codec_vp9_process_rpm(vp9)) {
>> -		amvdec_src_change(sess, vp9->width, vp9->height, 16);
>> +		amvdec_src_change(sess, vp9->width, vp9->height, 16,
>> +				  vp9->is_10bit ? 10 : 8);
>>   
>>   		/* No frame is actually processed */
>>   		vp9->cur_frame = NULL;
>> diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
>> index 1904d58875ad..3cd29ab4f979 100644
>> --- a/drivers/staging/media/meson/vdec/esparser.c
>> +++ b/drivers/staging/media/meson/vdec/esparser.c
>> @@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
>>   		if (esparser_vififo_get_free_space(sess) < payload_size ||
>>   		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
>>   			return -EAGAIN;
>> +
>>   	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
>>   		return -EAGAIN;
>>   	}
>> diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
>> index 0906b8fb5cc6..a48170fe4cff 100644
>> --- a/drivers/staging/media/meson/vdec/vdec.h
>> +++ b/drivers/staging/media/meson/vdec/vdec.h
>> @@ -244,6 +244,7 @@ struct amvdec_session {
>>   	u32 width;
>>   	u32 height;
>>   	u32 colorspace;
>> +	u32 bitdepth;
>>   	u8 ycbcr_enc;
>>   	u8 quantization;
>>   	u8 xfer_func;
>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
>> index 7d2a75653250..fef76142f0c5 100644
>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.c
>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
>> @@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
>>   }
>>   EXPORT_SYMBOL_GPL(amvdec_write_parser);
>>   
>> -/* 4 KiB per 64x32 block */
>> -u32 amvdec_am21c_body_size(u32 width, u32 height)
>> +/* AMFBC body is made out of 64x32 blocks with varying block size */
>> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>>   {
>>   	u32 width_64 = ALIGN(width, 64) / 64;
>>   	u32 height_32 = ALIGN(height, 32) / 32;
>> +	u32 blk_size = 4096;
>>   
>> -	return SZ_4K * width_64 * height_32;
>> +	if (!is_10bit) {
>> +		if (use_mmu)
>> +			blk_size = 3200;
>> +		else
>> +			blk_size = 3072;
>> +	}
>> +
>> +	return blk_size * width_64 * height_32;
>>   }
>> -EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
>>   
>>   /* 32 bytes per 128x64 block */
>> -u32 amvdec_am21c_head_size(u32 width, u32 height)
>> +u32 amvdec_amfbc_head_size(u32 width, u32 height)
>>   {
>>   	u32 width_128 = ALIGN(width, 128) / 128;
>>   	u32 height_64 = ALIGN(height, 64) / 64;
>>   
>>   	return 32 * width_128 * height_64;
>>   }
>> -EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
>>   
>> -u32 amvdec_am21c_size(u32 width, u32 height)
>> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>>   {
>> -	return ALIGN(amvdec_am21c_body_size(width, height) +
>> -		     amvdec_am21c_head_size(width, height), SZ_64K);
>> +	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
>> +		     amvdec_amfbc_head_size(width, height), SZ_64K);
>>   }
>> -EXPORT_SYMBOL_GPL(amvdec_am21c_size);
>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
>>   
>>   static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
>>   {
>> @@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>>   EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
>>   
>>   void amvdec_src_change(struct amvdec_session *sess, u32 width,
>> -		       u32 height, u32 dpb_size)
>> +		       u32 height, u32 dpb_size, u32 bitdepth)
>>   {
>>   	static const struct v4l2_event ev = {
>>   		.type = V4L2_EVENT_SOURCE_CHANGE,
>> @@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
>>   
>>   	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
>>   
>> +	sess->bitdepth = bitdepth;
>> +
>>   	/*
>>   	 * Check if the capture queue is already configured well for our
>> -	 * usecase. If so, keep decoding with it and do not send the event
>> +	 * usecase. If so, keep decoding with it.
>>   	 */
>>   	if (sess->streamon_cap &&
>>   	    sess->width == width &&
>>   	    sess->height == height &&
>>   	    dpb_size <= sess->num_dst_bufs) {
>>   		sess->fmt_out->codec_ops->resume(sess);
>> -		return;
>> +	} else {
>> +		sess->status = STATUS_NEEDS_RESUME;
>> +		sess->changed_format = 0;
>>   	}
>>   
>> -	sess->changed_format = 0;
>>   	sess->width = width;
>>   	sess->height = height;
>> -	sess->status = STATUS_NEEDS_RESUME;
>>   
>> -	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
>> -		width, height, dpb_size);
>> +	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
>> +		width, height, dpb_size, bitdepth);
>>   	v4l2_event_queue_fh(&sess->fh, &ev);
>>   }
>>   EXPORT_SYMBOL_GPL(amvdec_src_change);
>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
>> index 4bf3e61d081b..1a711679d26a 100644
>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.h
>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
>> @@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
>>   u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
>>   void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
>>   
>> -u32 amvdec_am21c_body_size(u32 width, u32 height);
>> -u32 amvdec_am21c_head_size(u32 width, u32 height);
>> -u32 amvdec_am21c_size(u32 width, u32 height);
>> +/* Helpers for the Amlogic compressed framebuffer format */
>> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>> +u32 amvdec_amfbc_head_size(u32 width, u32 height);
>> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>>   
>>   /**
>>    * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
>> @@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>>    * @width: picture width detected by the hardware
>>    * @height: picture height detected by the hardware
>>    * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
>> + * @bitdepth: Bit depth (usually 10 or 8) of the coded content
>>    */
>>   void amvdec_src_change(struct amvdec_session *sess, u32 width,
>> -		       u32 height, u32 dpb_size);
>> +		       u32 height, u32 dpb_size, u32 bitdepth);
>>   
>>   /**
>>    * amvdec_abort() - Abort the current decoding session
> 


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Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Neil Armstrong]

On 24/01/2023 16:21, Nicolas Dufresne wrote:
> Hi,
> 
> Le mardi 24 janvier 2023 à 03:40 +0000, Christian Hewitt a écrit :
>> From: Benjamin Roszak <benjamin545@gmail.com>
>>
>> In order to support 10bit bitstream decoding, buffers and MMU
>> handling must be cleaned up to support either downscale output
>> from compressed 10bit decoding to uncompressed 8bit NV12 output
>> or to compressed 10bit proprietary encoded frame format.
> 
> I understand this is step forward, and agree with the patches in general, though
> I'd like to know if we can expect 10bit secondary buffers in the future ? Or is
> the AMFBC that only 10bit format supported ? Should be expect the 10bit format
> definition to be added later ?

The support exist, but it stopped when nobody aggreed on how to handle the different
layouts generated by the decoder.

There's at least 4 possible layouts vs how we represent then in DRM :
- GX 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
- GX 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
- G12 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,AMLOGIC_FBC_OPTION_MEM_SAVING)
- G12 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC()AMLOGIC_FBC_LAYOUT_SCATTER, AMLOGIC_FBC_OPTION_MEM_SAVING)

And probably more depending on new SoCs and new codecs.

Neil

> 
>>
>> For that, "am21c" name is moved to "amfbc" to reflect the upstream
>> Amlogic Compressed framebuffer modifier naming.
>>
>> Compressed frame buffers allocation is also cleaned up so it
>> can be shared with the HEVC decoder implementation.
>>
>> Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
>> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
>> ---
>>   drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
>>   .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
>>   .../media/meson/vdec/codec_hevc_common.h      |   3 +-
>>   drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
>>   drivers/staging/media/meson/vdec/esparser.c   |   1 +
>>   drivers/staging/media/meson/vdec/vdec.h       |   1 +
>>   .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
>>   .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
>>   8 files changed, 161 insertions(+), 97 deletions(-)
>>
>> diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
>> index c61128fc4bb9..d53c9a464bde 100644
>> --- a/drivers/staging/media/meson/vdec/codec_h264.c
>> +++ b/drivers/staging/media/meson/vdec/codec_h264.c
>> @@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
>>   		frame_width, frame_height, crop_right, crop_bottom);
>>   
>>   	codec_h264_set_par(sess);
>> -	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
>> +	amvdec_src_change(sess, frame_width, frame_height,
>> +			  h264->max_refs + 5, 8);
>>   }
>>   
>>   /*
>> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
>> index 0315cc0911cd..1c74b4837dcb 100644
>> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
>> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
>> @@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
>>   void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>>   {
>>   	struct amvdec_core *core = sess->core;
>> -	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
>> -	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
>> +	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
>> +					 sess->pixfmt_cap, is_10bit);
>> +	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
>> +					       is_10bit, use_mmu);
>> +	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
>>   
>>   	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
>>   		/* Enable 2-plane reference read mode */
>> @@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>>   		return;
>>   	}
>>   
>> +	/* enable mem saving mode for 8-bit */
>> +	if (!is_10bit)
>> +		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
>> +	else
>> +		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
>> +
>>   	if (codec_hevc_use_mmu(core->platform->revision,
>>   			       sess->pixfmt_cap, is_10bit))
>>   		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
>> +	else if (!is_10bit)
>> +		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
>>   	else
>>   		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
>>   
>> @@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
>>   
>>   		idx = vb->index;
>>   
>> -		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
>> +		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
>>   			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>>   		else
>>   			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
>> @@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>   {
>>   	struct amvdec_core *core = sess->core;
>>   	struct v4l2_m2m_buffer *buf;
>> -	u32 revision = core->platform->revision;
>>   	u32 pixfmt_cap = sess->pixfmt_cap;
>> +	const u32 revision = core->platform->revision;
>>   	int i;
>>   
>>   	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
>> @@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>   		dma_addr_t buf_uv_paddr = 0;
>>   		u32 idx = vb->index;
>>   
>> -		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
>> -			buf_y_paddr = comm->mmu_header_paddr[idx];
>> -		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
>> -			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>> -		else
>> +		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
>> +			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
>> +				buf_y_paddr = comm->mmu_header_paddr[idx];
>> +			else
>> +				buf_y_paddr = comm->fbc_buffer_paddr[idx];
>> +		} else {
>>   			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
>> +		}
>>   
>>   		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
>>   				 buf_y_paddr >> 5);
>> @@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>   		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
>>   }
>>   
>> -void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>> +void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>   				 struct codec_hevc_common *comm)
>>   {
>>   	struct device *dev = sess->core->dev;
>> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>>   	int i;
>>   
>>   	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
>> -		if (comm->fbc_buffer_vaddr[i]) {
>> -			dma_free_coherent(dev, am21_size,
>> -					  comm->fbc_buffer_vaddr[i],
>> -					  comm->fbc_buffer_paddr[i]);
>> -			comm->fbc_buffer_vaddr[i] = NULL;
>> +		if (comm->mmu_header_vaddr[i]) {
>> +			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>> +					  comm->mmu_header_vaddr[i],
>> +					  comm->mmu_header_paddr[i]);
>> +			comm->mmu_header_vaddr[i] = NULL;
>>   		}
>>   	}
>>   }
>> -EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>> +EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>>   
>> -static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>> +static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>>   					struct codec_hevc_common *comm)
>>   {
>>   	struct device *dev = sess->core->dev;
>>   	struct v4l2_m2m_buffer *buf;
>> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>>   
>>   	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>>   		u32 idx = buf->vb.vb2_buf.index;
>>   		dma_addr_t paddr;
>> -		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
>> -						 GFP_KERNEL);
>> +		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>> +						 &paddr, GFP_KERNEL);
>>   		if (!vaddr) {
>> -			codec_hevc_free_fbc_buffers(sess, comm);
>> +			codec_hevc_free_mmu_headers(sess, comm);
>>   			return -ENOMEM;
>>   		}
>>   
>> -		comm->fbc_buffer_vaddr[idx] = vaddr;
>> -		comm->fbc_buffer_paddr[idx] = paddr;
>> +		comm->mmu_header_vaddr[idx] = vaddr;
>> +		comm->mmu_header_paddr[idx] = paddr;
>>   	}
>>   
>>   	return 0;
>>   }
>>   
>> -void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>> +void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>>   				 struct codec_hevc_common *comm)
>>   {
>>   	struct device *dev = sess->core->dev;
>> +	u32 use_mmu;
>> +	u32 am21_size;
>>   	int i;
>>   
>> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
>> +				     sess->pixfmt_cap,
>> +				sess->bitdepth == 10 ? 1 : 0);
>> +
>> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
>> +				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
>> +
>>   	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
>> -		if (comm->mmu_header_vaddr[i]) {
>> -			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>> -					  comm->mmu_header_vaddr[i],
>> -					  comm->mmu_header_paddr[i]);
>> -			comm->mmu_header_vaddr[i] = NULL;
>> +		if (comm->fbc_buffer_vaddr[i]) {
>> +			dma_free_coherent(dev, am21_size,
>> +					  comm->fbc_buffer_vaddr[i],
>> +					  comm->fbc_buffer_paddr[i]);
>> +			comm->fbc_buffer_vaddr[i] = NULL;
>>   		}
>>   	}
>>   
>> @@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>   				  comm->mmu_map_paddr);
>>   		comm->mmu_map_vaddr = NULL;
>>   	}
>> +
>> +	codec_hevc_free_mmu_headers(sess, comm);
>>   }
>> -EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>> +EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>>   
>> -static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>> +static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>>   					struct codec_hevc_common *comm)
>>   {
>>   	struct device *dev = sess->core->dev;
>>   	struct v4l2_m2m_buffer *buf;
>> +	u32 use_mmu;
>> +	u32 am21_size;
>> +	const u32 revision = sess->core->platform->revision;
>> +	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
>> +	int ret;
>>   
>> -	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
>> -						 &comm->mmu_map_paddr,
>> -						 GFP_KERNEL);
>> -	if (!comm->mmu_map_vaddr)
>> -		return -ENOMEM;
>> +	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
>> +				     is_10bit);
>> +
>> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
>> +				      is_10bit, use_mmu);
>>   
>>   	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>>   		u32 idx = buf->vb.vb2_buf.index;
>>   		dma_addr_t paddr;
>> -		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>> -						 &paddr, GFP_KERNEL);
>> +
>> +		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
>> +						 GFP_KERNEL);
>>   		if (!vaddr) {
>> -			codec_hevc_free_mmu_headers(sess, comm);
>> +			codec_hevc_free_fbc_buffers(sess, comm);
>>   			return -ENOMEM;
>>   		}
>>   
>> -		comm->mmu_header_vaddr[idx] = vaddr;
>> -		comm->mmu_header_paddr[idx] = paddr;
>> +		comm->fbc_buffer_vaddr[idx] = vaddr;
>> +		comm->fbc_buffer_paddr[idx] = paddr;
>> +	}
>> +
>> +	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
>> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>> +		ret = codec_hevc_alloc_mmu_headers(sess, comm);
>> +		if (ret) {
>> +			codec_hevc_free_fbc_buffers(sess, comm);
>> +			return ret;
>> +		}
>>   	}
>>   
>>   	return 0;
>> @@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>>   			     int is_10bit)
>>   {
>>   	struct amvdec_core *core = sess->core;
>> +	struct device *dev = core->dev;
>>   	int ret;
>>   
>> -	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>> -		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
>> -		if (ret)
>> -			return ret;
>> +	if (codec_hevc_use_mmu(core->platform->revision,
>> +			       sess->pixfmt_cap, is_10bit)) {
>> +		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
>> +							 &comm->mmu_map_paddr,
>> +							 GFP_KERNEL);
>> +		if (!comm->mmu_map_vaddr)
>> +			return -ENOMEM;
>>   	}
>>   
>>   	if (codec_hevc_use_mmu(core->platform->revision,
>> -			       sess->pixfmt_cap, is_10bit)) {
>> -		ret = codec_hevc_alloc_mmu_headers(sess, comm);
>> -		if (ret) {
>> -			codec_hevc_free_fbc_buffers(sess, comm);
>> +			       sess->pixfmt_cap, is_10bit) ||
>> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>> +		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
>> +		if (ret)
>>   			return ret;
>> -		}
>>   	}
>>   
>>   	if (core->platform->revision == VDEC_REVISION_GXBB)
>> @@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
>>   
>>   void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>>   			     struct codec_hevc_common *comm,
>> -			     struct vb2_buffer *vb)
>> +			     struct vb2_buffer *vb,
>> +			     u32 is_10bit)
>>   {
>> -	u32 size = amvdec_am21c_size(sess->width, sess->height);
>> -	u32 nb_pages = size / PAGE_SIZE;
>> +	u32 use_mmu;
>> +	u32 size;
>> +	u32 nb_pages;
>>   	u32 *mmu_map = comm->mmu_map_vaddr;
>>   	u32 first_page;
>>   	u32 i;
>>   
>> -	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
>> -		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>> -	else
>> -		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
>> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
>> +				     sess->pixfmt_cap, is_10bit);
>> +
>> +	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
>> +				 use_mmu);
>>   
>> +	nb_pages = size / PAGE_SIZE;
>> +	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>>   	for (i = 0; i < nb_pages; ++i)
>>   		mmu_map[i] = first_page + i;
>>   }
>> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
>> index cf072b8a9da2..13f9f1d90a94 100644
>> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
>> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
>> @@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>>   
>>   void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>>   			     struct codec_hevc_common *comm,
>> -			     struct vb2_buffer *vb);
>> +			     struct vb2_buffer *vb,
>> +			     u32 is_10bit);
>>   
>>   #endif
>> diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
>> index 394df5761556..8e3bbf0db4b3 100644
>> --- a/drivers/staging/media/meson/vdec/codec_vp9.c
>> +++ b/drivers/staging/media/meson/vdec/codec_vp9.c
>> @@ -458,12 +458,6 @@ struct codec_vp9 {
>>   	struct list_head ref_frames_list;
>>   	u32 frames_num;
>>   
>> -	/* In case of downsampling (decoding with FBC but outputting in NV12M),
>> -	 * we need to allocate additional buffers for FBC.
>> -	 */
>> -	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
>> -	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
>> -
>>   	int ref_frame_map[REF_FRAMES];
>>   	int next_ref_frame_map[REF_FRAMES];
>>   	struct vp9_frame *frame_refs[REFS_PER_FRAME];
>> @@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>>   		buf_y_paddr =
>>   		       vb2_dma_contig_plane_dma_addr(vb, 0);
>>   
>> -	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
>> -		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
>> -		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
>> +	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
>>   		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
>> -	}
>>   
>>   	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
>>   		buf_y_paddr =
>> @@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>>   
>>   	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>>   			       vp9->is_10bit)) {
>> -		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
>> -				 vp9->common.mmu_header_paddr[vb->index]);
>> +		dma_addr_t header_adr;
>> +
>> +		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
>> +			header_adr = vp9->common.mmu_header_paddr[vb->index];
>> +		else
>> +			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
>> +		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
>>   		/* use HEVC_CM_HEADER_START_ADDR */
>>   		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
>>   	}
>> @@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>>   {
>>   	struct amvdec_core *core = sess->core;
>>   	u32 scale = 0;
>> +	u32 use_mmu;
>>   	u32 sz;
>>   	int i;
>>   
>> +	use_mmu = codec_hevc_use_mmu(core->platform->revision,
>> +				     sess->pixfmt_cap, vp9->is_10bit);
>> +
>>   	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
>>   	codec_vp9_set_refs(sess, vp9);
>>   	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
>> @@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>>   		    vp9->frame_refs[i]->height != vp9->height)
>>   			scale = 1;
>>   
>> -		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
>> -					    vp9->frame_refs[i]->height);
>> +		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
>> +					    vp9->frame_refs[i]->height,
>> +					    vp9->is_10bit, use_mmu);
>>   
>>   		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
>>   				 vp9->frame_refs[i]->width);
>> @@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
>>   	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>>   			       vp9->is_10bit))
>>   		codec_hevc_fill_mmu_map(sess, &vp9->common,
>> -					&vp9->cur_frame->vbuf->vb2_buf);
>> +					&vp9->cur_frame->vbuf->vb2_buf,
>> +					vp9->is_10bit);
>>   
>>   	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
>>   
>> @@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
>>   
>>   	codec_vp9_fetch_rpm(sess);
>>   	if (codec_vp9_process_rpm(vp9)) {
>> -		amvdec_src_change(sess, vp9->width, vp9->height, 16);
>> +		amvdec_src_change(sess, vp9->width, vp9->height, 16,
>> +				  vp9->is_10bit ? 10 : 8);
>>   
>>   		/* No frame is actually processed */
>>   		vp9->cur_frame = NULL;
>> diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
>> index 1904d58875ad..3cd29ab4f979 100644
>> --- a/drivers/staging/media/meson/vdec/esparser.c
>> +++ b/drivers/staging/media/meson/vdec/esparser.c
>> @@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
>>   		if (esparser_vififo_get_free_space(sess) < payload_size ||
>>   		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
>>   			return -EAGAIN;
>> +
>>   	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
>>   		return -EAGAIN;
>>   	}
>> diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
>> index 0906b8fb5cc6..a48170fe4cff 100644
>> --- a/drivers/staging/media/meson/vdec/vdec.h
>> +++ b/drivers/staging/media/meson/vdec/vdec.h
>> @@ -244,6 +244,7 @@ struct amvdec_session {
>>   	u32 width;
>>   	u32 height;
>>   	u32 colorspace;
>> +	u32 bitdepth;
>>   	u8 ycbcr_enc;
>>   	u8 quantization;
>>   	u8 xfer_func;
>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
>> index 7d2a75653250..fef76142f0c5 100644
>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.c
>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
>> @@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
>>   }
>>   EXPORT_SYMBOL_GPL(amvdec_write_parser);
>>   
>> -/* 4 KiB per 64x32 block */
>> -u32 amvdec_am21c_body_size(u32 width, u32 height)
>> +/* AMFBC body is made out of 64x32 blocks with varying block size */
>> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>>   {
>>   	u32 width_64 = ALIGN(width, 64) / 64;
>>   	u32 height_32 = ALIGN(height, 32) / 32;
>> +	u32 blk_size = 4096;
>>   
>> -	return SZ_4K * width_64 * height_32;
>> +	if (!is_10bit) {
>> +		if (use_mmu)
>> +			blk_size = 3200;
>> +		else
>> +			blk_size = 3072;
>> +	}
>> +
>> +	return blk_size * width_64 * height_32;
>>   }
>> -EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
>>   
>>   /* 32 bytes per 128x64 block */
>> -u32 amvdec_am21c_head_size(u32 width, u32 height)
>> +u32 amvdec_amfbc_head_size(u32 width, u32 height)
>>   {
>>   	u32 width_128 = ALIGN(width, 128) / 128;
>>   	u32 height_64 = ALIGN(height, 64) / 64;
>>   
>>   	return 32 * width_128 * height_64;
>>   }
>> -EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
>>   
>> -u32 amvdec_am21c_size(u32 width, u32 height)
>> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>>   {
>> -	return ALIGN(amvdec_am21c_body_size(width, height) +
>> -		     amvdec_am21c_head_size(width, height), SZ_64K);
>> +	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
>> +		     amvdec_amfbc_head_size(width, height), SZ_64K);
>>   }
>> -EXPORT_SYMBOL_GPL(amvdec_am21c_size);
>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
>>   
>>   static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
>>   {
>> @@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>>   EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
>>   
>>   void amvdec_src_change(struct amvdec_session *sess, u32 width,
>> -		       u32 height, u32 dpb_size)
>> +		       u32 height, u32 dpb_size, u32 bitdepth)
>>   {
>>   	static const struct v4l2_event ev = {
>>   		.type = V4L2_EVENT_SOURCE_CHANGE,
>> @@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
>>   
>>   	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
>>   
>> +	sess->bitdepth = bitdepth;
>> +
>>   	/*
>>   	 * Check if the capture queue is already configured well for our
>> -	 * usecase. If so, keep decoding with it and do not send the event
>> +	 * usecase. If so, keep decoding with it.
>>   	 */
>>   	if (sess->streamon_cap &&
>>   	    sess->width == width &&
>>   	    sess->height == height &&
>>   	    dpb_size <= sess->num_dst_bufs) {
>>   		sess->fmt_out->codec_ops->resume(sess);
>> -		return;
>> +	} else {
>> +		sess->status = STATUS_NEEDS_RESUME;
>> +		sess->changed_format = 0;
>>   	}
>>   
>> -	sess->changed_format = 0;
>>   	sess->width = width;
>>   	sess->height = height;
>> -	sess->status = STATUS_NEEDS_RESUME;
>>   
>> -	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
>> -		width, height, dpb_size);
>> +	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
>> +		width, height, dpb_size, bitdepth);
>>   	v4l2_event_queue_fh(&sess->fh, &ev);
>>   }
>>   EXPORT_SYMBOL_GPL(amvdec_src_change);
>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
>> index 4bf3e61d081b..1a711679d26a 100644
>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.h
>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
>> @@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
>>   u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
>>   void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
>>   
>> -u32 amvdec_am21c_body_size(u32 width, u32 height);
>> -u32 amvdec_am21c_head_size(u32 width, u32 height);
>> -u32 amvdec_am21c_size(u32 width, u32 height);
>> +/* Helpers for the Amlogic compressed framebuffer format */
>> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>> +u32 amvdec_amfbc_head_size(u32 width, u32 height);
>> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>>   
>>   /**
>>    * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
>> @@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>>    * @width: picture width detected by the hardware
>>    * @height: picture height detected by the hardware
>>    * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
>> + * @bitdepth: Bit depth (usually 10 or 8) of the coded content
>>    */
>>   void amvdec_src_change(struct amvdec_session *sess, u32 width,
>> -		       u32 height, u32 dpb_size);
>> +		       u32 height, u32 dpb_size, u32 bitdepth);
>>   
>>   /**
>>    * amvdec_abort() - Abort the current decoding session
> 


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Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Nicolas Dufresne]

Le mardi 24 janvier 2023 à 16:26 +0100, Neil Armstrong a écrit :
> On 24/01/2023 16:21, Nicolas Dufresne wrote:
> > Hi,
> > 
> > Le mardi 24 janvier 2023 à 03:40 +0000, Christian Hewitt a écrit :
> > > From: Benjamin Roszak <benjamin545@gmail.com>
> > > 
> > > In order to support 10bit bitstream decoding, buffers and MMU
> > > handling must be cleaned up to support either downscale output
> > > from compressed 10bit decoding to uncompressed 8bit NV12 output
> > > or to compressed 10bit proprietary encoded frame format.
> > 
> > I understand this is step forward, and agree with the patches in general, though
> > I'd like to know if we can expect 10bit secondary buffers in the future ? Or is
> > the AMFBC that only 10bit format supported ? Should be expect the 10bit format
> > definition to be added later ?
> 
> The support exist, but it stopped when nobody aggreed on how to handle the different
> layouts generated by the decoder.
> 
> There's at least 4 possible layouts vs how we represent then in DRM :
> - GX 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
> - GX 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
> - G12 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,AMLOGIC_FBC_OPTION_MEM_SAVING)
> - G12 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC()AMLOGIC_FBC_LAYOUT_SCATTER, AMLOGIC_FBC_OPTION_MEM_SAVING)
> 
> And probably more depending on new SoCs and new codecs.

Thanks, I didn't know. I think V4L2 strategy here would be to pick and expose
just the minimum to make the mainline driver viable for 10bit decoding (unless
again you have a secondary format like P010 available). This would suite better
your users then just waiting for the perfect system to be in place.

p.s AMLOGIC_FBC_OPTION_MEM_SAVING is unlikely a layout from its name. FBC is
generally loss-less for correctness, but loss-less compression always have a
worse case scenerio bigger then the original, so we still need to reserve big
chunk of memory. For memory limited device, ARM came up with lossy compressor,
that guaranty a certain compression ratio. This name sounds like a similar
feature to me.

Nicolas

> 
> Neil
> 
> > 
> > > 
> > > For that, "am21c" name is moved to "amfbc" to reflect the upstream
> > > Amlogic Compressed framebuffer modifier naming.
> > > 
> > > Compressed frame buffers allocation is also cleaned up so it
> > > can be shared with the HEVC decoder implementation.
> > > 
> > > Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
> > > Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
> > > ---
> > >   drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
> > >   .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
> > >   .../media/meson/vdec/codec_hevc_common.h      |   3 +-
> > >   drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
> > >   drivers/staging/media/meson/vdec/esparser.c   |   1 +
> > >   drivers/staging/media/meson/vdec/vdec.h       |   1 +
> > >   .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
> > >   .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
> > >   8 files changed, 161 insertions(+), 97 deletions(-)
> > > 
> > > diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
> > > index c61128fc4bb9..d53c9a464bde 100644
> > > --- a/drivers/staging/media/meson/vdec/codec_h264.c
> > > +++ b/drivers/staging/media/meson/vdec/codec_h264.c
> > > @@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
> > >   		frame_width, frame_height, crop_right, crop_bottom);
> > >   
> > >   	codec_h264_set_par(sess);
> > > -	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
> > > +	amvdec_src_change(sess, frame_width, frame_height,
> > > +			  h264->max_refs + 5, 8);
> > >   }
> > >   
> > >   /*
> > > diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
> > > index 0315cc0911cd..1c74b4837dcb 100644
> > > --- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
> > > +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
> > > @@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
> > >   void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
> > >   {
> > >   	struct amvdec_core *core = sess->core;
> > > -	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
> > > -	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
> > > +	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
> > > +					 sess->pixfmt_cap, is_10bit);
> > > +	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
> > > +					       is_10bit, use_mmu);
> > > +	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
> > >   
> > >   	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
> > >   		/* Enable 2-plane reference read mode */
> > > @@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
> > >   		return;
> > >   	}
> > >   
> > > +	/* enable mem saving mode for 8-bit */
> > > +	if (!is_10bit)
> > > +		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
> > > +	else
> > > +		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
> > > +
> > >   	if (codec_hevc_use_mmu(core->platform->revision,
> > >   			       sess->pixfmt_cap, is_10bit))
> > >   		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
> > > +	else if (!is_10bit)
> > > +		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
> > >   	else
> > >   		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
> > >   
> > > @@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
> > >   
> > >   		idx = vb->index;
> > >   
> > > -		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
> > > +		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
> > >   			buf_y_paddr = comm->fbc_buffer_paddr[idx];
> > >   		else
> > >   			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
> > > @@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
> > >   {
> > >   	struct amvdec_core *core = sess->core;
> > >   	struct v4l2_m2m_buffer *buf;
> > > -	u32 revision = core->platform->revision;
> > >   	u32 pixfmt_cap = sess->pixfmt_cap;
> > > +	const u32 revision = core->platform->revision;
> > >   	int i;
> > >   
> > >   	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
> > > @@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
> > >   		dma_addr_t buf_uv_paddr = 0;
> > >   		u32 idx = vb->index;
> > >   
> > > -		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
> > > -			buf_y_paddr = comm->mmu_header_paddr[idx];
> > > -		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
> > > -			buf_y_paddr = comm->fbc_buffer_paddr[idx];
> > > -		else
> > > +		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
> > > +			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
> > > +				buf_y_paddr = comm->mmu_header_paddr[idx];
> > > +			else
> > > +				buf_y_paddr = comm->fbc_buffer_paddr[idx];
> > > +		} else {
> > >   			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
> > > +		}
> > >   
> > >   		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
> > >   				 buf_y_paddr >> 5);
> > > @@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
> > >   		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
> > >   }
> > >   
> > > -void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
> > > +void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
> > >   				 struct codec_hevc_common *comm)
> > >   {
> > >   	struct device *dev = sess->core->dev;
> > > -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
> > >   	int i;
> > >   
> > >   	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
> > > -		if (comm->fbc_buffer_vaddr[i]) {
> > > -			dma_free_coherent(dev, am21_size,
> > > -					  comm->fbc_buffer_vaddr[i],
> > > -					  comm->fbc_buffer_paddr[i]);
> > > -			comm->fbc_buffer_vaddr[i] = NULL;
> > > +		if (comm->mmu_header_vaddr[i]) {
> > > +			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> > > +					  comm->mmu_header_vaddr[i],
> > > +					  comm->mmu_header_paddr[i]);
> > > +			comm->mmu_header_vaddr[i] = NULL;
> > >   		}
> > >   	}
> > >   }
> > > -EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
> > > +EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
> > >   
> > > -static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
> > > +static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
> > >   					struct codec_hevc_common *comm)
> > >   {
> > >   	struct device *dev = sess->core->dev;
> > >   	struct v4l2_m2m_buffer *buf;
> > > -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
> > >   
> > >   	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
> > >   		u32 idx = buf->vb.vb2_buf.index;
> > >   		dma_addr_t paddr;
> > > -		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
> > > -						 GFP_KERNEL);
> > > +		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> > > +						 &paddr, GFP_KERNEL);
> > >   		if (!vaddr) {
> > > -			codec_hevc_free_fbc_buffers(sess, comm);
> > > +			codec_hevc_free_mmu_headers(sess, comm);
> > >   			return -ENOMEM;
> > >   		}
> > >   
> > > -		comm->fbc_buffer_vaddr[idx] = vaddr;
> > > -		comm->fbc_buffer_paddr[idx] = paddr;
> > > +		comm->mmu_header_vaddr[idx] = vaddr;
> > > +		comm->mmu_header_paddr[idx] = paddr;
> > >   	}
> > >   
> > >   	return 0;
> > >   }
> > >   
> > > -void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
> > > +void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
> > >   				 struct codec_hevc_common *comm)
> > >   {
> > >   	struct device *dev = sess->core->dev;
> > > +	u32 use_mmu;
> > > +	u32 am21_size;
> > >   	int i;
> > >   
> > > +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
> > > +				     sess->pixfmt_cap,
> > > +				sess->bitdepth == 10 ? 1 : 0);
> > > +
> > > +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
> > > +				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
> > > +
> > >   	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
> > > -		if (comm->mmu_header_vaddr[i]) {
> > > -			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> > > -					  comm->mmu_header_vaddr[i],
> > > -					  comm->mmu_header_paddr[i]);
> > > -			comm->mmu_header_vaddr[i] = NULL;
> > > +		if (comm->fbc_buffer_vaddr[i]) {
> > > +			dma_free_coherent(dev, am21_size,
> > > +					  comm->fbc_buffer_vaddr[i],
> > > +					  comm->fbc_buffer_paddr[i]);
> > > +			comm->fbc_buffer_vaddr[i] = NULL;
> > >   		}
> > >   	}
> > >   
> > > @@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
> > >   				  comm->mmu_map_paddr);
> > >   		comm->mmu_map_vaddr = NULL;
> > >   	}
> > > +
> > > +	codec_hevc_free_mmu_headers(sess, comm);
> > >   }
> > > -EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
> > > +EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
> > >   
> > > -static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
> > > +static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
> > >   					struct codec_hevc_common *comm)
> > >   {
> > >   	struct device *dev = sess->core->dev;
> > >   	struct v4l2_m2m_buffer *buf;
> > > +	u32 use_mmu;
> > > +	u32 am21_size;
> > > +	const u32 revision = sess->core->platform->revision;
> > > +	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
> > > +	int ret;
> > >   
> > > -	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
> > > -						 &comm->mmu_map_paddr,
> > > -						 GFP_KERNEL);
> > > -	if (!comm->mmu_map_vaddr)
> > > -		return -ENOMEM;
> > > +	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
> > > +				     is_10bit);
> > > +
> > > +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
> > > +				      is_10bit, use_mmu);
> > >   
> > >   	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
> > >   		u32 idx = buf->vb.vb2_buf.index;
> > >   		dma_addr_t paddr;
> > > -		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> > > -						 &paddr, GFP_KERNEL);
> > > +
> > > +		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
> > > +						 GFP_KERNEL);
> > >   		if (!vaddr) {
> > > -			codec_hevc_free_mmu_headers(sess, comm);
> > > +			codec_hevc_free_fbc_buffers(sess, comm);
> > >   			return -ENOMEM;
> > >   		}
> > >   
> > > -		comm->mmu_header_vaddr[idx] = vaddr;
> > > -		comm->mmu_header_paddr[idx] = paddr;
> > > +		comm->fbc_buffer_vaddr[idx] = vaddr;
> > > +		comm->fbc_buffer_paddr[idx] = paddr;
> > > +	}
> > > +
> > > +	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
> > > +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> > > +		ret = codec_hevc_alloc_mmu_headers(sess, comm);
> > > +		if (ret) {
> > > +			codec_hevc_free_fbc_buffers(sess, comm);
> > > +			return ret;
> > > +		}
> > >   	}
> > >   
> > >   	return 0;
> > > @@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
> > >   			     int is_10bit)
> > >   {
> > >   	struct amvdec_core *core = sess->core;
> > > +	struct device *dev = core->dev;
> > >   	int ret;
> > >   
> > > -	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> > > -		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
> > > -		if (ret)
> > > -			return ret;
> > > +	if (codec_hevc_use_mmu(core->platform->revision,
> > > +			       sess->pixfmt_cap, is_10bit)) {
> > > +		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
> > > +							 &comm->mmu_map_paddr,
> > > +							 GFP_KERNEL);
> > > +		if (!comm->mmu_map_vaddr)
> > > +			return -ENOMEM;
> > >   	}
> > >   
> > >   	if (codec_hevc_use_mmu(core->platform->revision,
> > > -			       sess->pixfmt_cap, is_10bit)) {
> > > -		ret = codec_hevc_alloc_mmu_headers(sess, comm);
> > > -		if (ret) {
> > > -			codec_hevc_free_fbc_buffers(sess, comm);
> > > +			       sess->pixfmt_cap, is_10bit) ||
> > > +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> > > +		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
> > > +		if (ret)
> > >   			return ret;
> > > -		}
> > >   	}
> > >   
> > >   	if (core->platform->revision == VDEC_REVISION_GXBB)
> > > @@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
> > >   
> > >   void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
> > >   			     struct codec_hevc_common *comm,
> > > -			     struct vb2_buffer *vb)
> > > +			     struct vb2_buffer *vb,
> > > +			     u32 is_10bit)
> > >   {
> > > -	u32 size = amvdec_am21c_size(sess->width, sess->height);
> > > -	u32 nb_pages = size / PAGE_SIZE;
> > > +	u32 use_mmu;
> > > +	u32 size;
> > > +	u32 nb_pages;
> > >   	u32 *mmu_map = comm->mmu_map_vaddr;
> > >   	u32 first_page;
> > >   	u32 i;
> > >   
> > > -	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
> > > -		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
> > > -	else
> > > -		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
> > > +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
> > > +				     sess->pixfmt_cap, is_10bit);
> > > +
> > > +	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
> > > +				 use_mmu);
> > >   
> > > +	nb_pages = size / PAGE_SIZE;
> > > +	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
> > >   	for (i = 0; i < nb_pages; ++i)
> > >   		mmu_map[i] = first_page + i;
> > >   }
> > > diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
> > > index cf072b8a9da2..13f9f1d90a94 100644
> > > --- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
> > > +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
> > > @@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
> > >   
> > >   void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
> > >   			     struct codec_hevc_common *comm,
> > > -			     struct vb2_buffer *vb);
> > > +			     struct vb2_buffer *vb,
> > > +			     u32 is_10bit);
> > >   
> > >   #endif
> > > diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
> > > index 394df5761556..8e3bbf0db4b3 100644
> > > --- a/drivers/staging/media/meson/vdec/codec_vp9.c
> > > +++ b/drivers/staging/media/meson/vdec/codec_vp9.c
> > > @@ -458,12 +458,6 @@ struct codec_vp9 {
> > >   	struct list_head ref_frames_list;
> > >   	u32 frames_num;
> > >   
> > > -	/* In case of downsampling (decoding with FBC but outputting in NV12M),
> > > -	 * we need to allocate additional buffers for FBC.
> > > -	 */
> > > -	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
> > > -	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
> > > -
> > >   	int ref_frame_map[REF_FRAMES];
> > >   	int next_ref_frame_map[REF_FRAMES];
> > >   	struct vp9_frame *frame_refs[REFS_PER_FRAME];
> > > @@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
> > >   		buf_y_paddr =
> > >   		       vb2_dma_contig_plane_dma_addr(vb, 0);
> > >   
> > > -	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
> > > -		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
> > > -		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
> > > +	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
> > >   		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
> > > -	}
> > >   
> > >   	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
> > >   		buf_y_paddr =
> > > @@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
> > >   
> > >   	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
> > >   			       vp9->is_10bit)) {
> > > -		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
> > > -				 vp9->common.mmu_header_paddr[vb->index]);
> > > +		dma_addr_t header_adr;
> > > +
> > > +		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
> > > +			header_adr = vp9->common.mmu_header_paddr[vb->index];
> > > +		else
> > > +			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
> > > +		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
> > >   		/* use HEVC_CM_HEADER_START_ADDR */
> > >   		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
> > >   	}
> > > @@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
> > >   {
> > >   	struct amvdec_core *core = sess->core;
> > >   	u32 scale = 0;
> > > +	u32 use_mmu;
> > >   	u32 sz;
> > >   	int i;
> > >   
> > > +	use_mmu = codec_hevc_use_mmu(core->platform->revision,
> > > +				     sess->pixfmt_cap, vp9->is_10bit);
> > > +
> > >   	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
> > >   	codec_vp9_set_refs(sess, vp9);
> > >   	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
> > > @@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
> > >   		    vp9->frame_refs[i]->height != vp9->height)
> > >   			scale = 1;
> > >   
> > > -		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
> > > -					    vp9->frame_refs[i]->height);
> > > +		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
> > > +					    vp9->frame_refs[i]->height,
> > > +					    vp9->is_10bit, use_mmu);
> > >   
> > >   		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
> > >   				 vp9->frame_refs[i]->width);
> > > @@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
> > >   	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
> > >   			       vp9->is_10bit))
> > >   		codec_hevc_fill_mmu_map(sess, &vp9->common,
> > > -					&vp9->cur_frame->vbuf->vb2_buf);
> > > +					&vp9->cur_frame->vbuf->vb2_buf,
> > > +					vp9->is_10bit);
> > >   
> > >   	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
> > >   
> > > @@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
> > >   
> > >   	codec_vp9_fetch_rpm(sess);
> > >   	if (codec_vp9_process_rpm(vp9)) {
> > > -		amvdec_src_change(sess, vp9->width, vp9->height, 16);
> > > +		amvdec_src_change(sess, vp9->width, vp9->height, 16,
> > > +				  vp9->is_10bit ? 10 : 8);
> > >   
> > >   		/* No frame is actually processed */
> > >   		vp9->cur_frame = NULL;
> > > diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
> > > index 1904d58875ad..3cd29ab4f979 100644
> > > --- a/drivers/staging/media/meson/vdec/esparser.c
> > > +++ b/drivers/staging/media/meson/vdec/esparser.c
> > > @@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
> > >   		if (esparser_vififo_get_free_space(sess) < payload_size ||
> > >   		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
> > >   			return -EAGAIN;
> > > +
> > >   	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
> > >   		return -EAGAIN;
> > >   	}
> > > diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
> > > index 0906b8fb5cc6..a48170fe4cff 100644
> > > --- a/drivers/staging/media/meson/vdec/vdec.h
> > > +++ b/drivers/staging/media/meson/vdec/vdec.h
> > > @@ -244,6 +244,7 @@ struct amvdec_session {
> > >   	u32 width;
> > >   	u32 height;
> > >   	u32 colorspace;
> > > +	u32 bitdepth;
> > >   	u8 ycbcr_enc;
> > >   	u8 quantization;
> > >   	u8 xfer_func;
> > > diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
> > > index 7d2a75653250..fef76142f0c5 100644
> > > --- a/drivers/staging/media/meson/vdec/vdec_helpers.c
> > > +++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
> > > @@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
> > >   }
> > >   EXPORT_SYMBOL_GPL(amvdec_write_parser);
> > >   
> > > -/* 4 KiB per 64x32 block */
> > > -u32 amvdec_am21c_body_size(u32 width, u32 height)
> > > +/* AMFBC body is made out of 64x32 blocks with varying block size */
> > > +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
> > >   {
> > >   	u32 width_64 = ALIGN(width, 64) / 64;
> > >   	u32 height_32 = ALIGN(height, 32) / 32;
> > > +	u32 blk_size = 4096;
> > >   
> > > -	return SZ_4K * width_64 * height_32;
> > > +	if (!is_10bit) {
> > > +		if (use_mmu)
> > > +			blk_size = 3200;
> > > +		else
> > > +			blk_size = 3072;
> > > +	}
> > > +
> > > +	return blk_size * width_64 * height_32;
> > >   }
> > > -EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
> > > +EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
> > >   
> > >   /* 32 bytes per 128x64 block */
> > > -u32 amvdec_am21c_head_size(u32 width, u32 height)
> > > +u32 amvdec_amfbc_head_size(u32 width, u32 height)
> > >   {
> > >   	u32 width_128 = ALIGN(width, 128) / 128;
> > >   	u32 height_64 = ALIGN(height, 64) / 64;
> > >   
> > >   	return 32 * width_128 * height_64;
> > >   }
> > > -EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
> > > +EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
> > >   
> > > -u32 amvdec_am21c_size(u32 width, u32 height)
> > > +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
> > >   {
> > > -	return ALIGN(amvdec_am21c_body_size(width, height) +
> > > -		     amvdec_am21c_head_size(width, height), SZ_64K);
> > > +	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
> > > +		     amvdec_amfbc_head_size(width, height), SZ_64K);
> > >   }
> > > -EXPORT_SYMBOL_GPL(amvdec_am21c_size);
> > > +EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
> > >   
> > >   static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
> > >   {
> > > @@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
> > >   EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
> > >   
> > >   void amvdec_src_change(struct amvdec_session *sess, u32 width,
> > > -		       u32 height, u32 dpb_size)
> > > +		       u32 height, u32 dpb_size, u32 bitdepth)
> > >   {
> > >   	static const struct v4l2_event ev = {
> > >   		.type = V4L2_EVENT_SOURCE_CHANGE,
> > > @@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
> > >   
> > >   	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
> > >   
> > > +	sess->bitdepth = bitdepth;
> > > +
> > >   	/*
> > >   	 * Check if the capture queue is already configured well for our
> > > -	 * usecase. If so, keep decoding with it and do not send the event
> > > +	 * usecase. If so, keep decoding with it.
> > >   	 */
> > >   	if (sess->streamon_cap &&
> > >   	    sess->width == width &&
> > >   	    sess->height == height &&
> > >   	    dpb_size <= sess->num_dst_bufs) {
> > >   		sess->fmt_out->codec_ops->resume(sess);
> > > -		return;
> > > +	} else {
> > > +		sess->status = STATUS_NEEDS_RESUME;
> > > +		sess->changed_format = 0;
> > >   	}
> > >   
> > > -	sess->changed_format = 0;
> > >   	sess->width = width;
> > >   	sess->height = height;
> > > -	sess->status = STATUS_NEEDS_RESUME;
> > >   
> > > -	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
> > > -		width, height, dpb_size);
> > > +	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
> > > +		width, height, dpb_size, bitdepth);
> > >   	v4l2_event_queue_fh(&sess->fh, &ev);
> > >   }
> > >   EXPORT_SYMBOL_GPL(amvdec_src_change);
> > > diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
> > > index 4bf3e61d081b..1a711679d26a 100644
> > > --- a/drivers/staging/media/meson/vdec/vdec_helpers.h
> > > +++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
> > > @@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
> > >   u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
> > >   void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
> > >   
> > > -u32 amvdec_am21c_body_size(u32 width, u32 height);
> > > -u32 amvdec_am21c_head_size(u32 width, u32 height);
> > > -u32 amvdec_am21c_size(u32 width, u32 height);
> > > +/* Helpers for the Amlogic compressed framebuffer format */
> > > +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
> > > +u32 amvdec_amfbc_head_size(u32 width, u32 height);
> > > +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
> > >   
> > >   /**
> > >    * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
> > > @@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
> > >    * @width: picture width detected by the hardware
> > >    * @height: picture height detected by the hardware
> > >    * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
> > > + * @bitdepth: Bit depth (usually 10 or 8) of the coded content
> > >    */
> > >   void amvdec_src_change(struct amvdec_session *sess, u32 width,
> > > -		       u32 height, u32 dpb_size);
> > > +		       u32 height, u32 dpb_size, u32 bitdepth);
> > >   
> > >   /**
> > >    * amvdec_abort() - Abort the current decoding session
> > 
> 

Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Nicolas Dufresne]

Le mardi 24 janvier 2023 à 16:26 +0100, Neil Armstrong a écrit :
> On 24/01/2023 16:21, Nicolas Dufresne wrote:
> > Hi,
> > 
> > Le mardi 24 janvier 2023 à 03:40 +0000, Christian Hewitt a écrit :
> > > From: Benjamin Roszak <benjamin545@gmail.com>
> > > 
> > > In order to support 10bit bitstream decoding, buffers and MMU
> > > handling must be cleaned up to support either downscale output
> > > from compressed 10bit decoding to uncompressed 8bit NV12 output
> > > or to compressed 10bit proprietary encoded frame format.
> > 
> > I understand this is step forward, and agree with the patches in general, though
> > I'd like to know if we can expect 10bit secondary buffers in the future ? Or is
> > the AMFBC that only 10bit format supported ? Should be expect the 10bit format
> > definition to be added later ?
> 
> The support exist, but it stopped when nobody aggreed on how to handle the different
> layouts generated by the decoder.
> 
> There's at least 4 possible layouts vs how we represent then in DRM :
> - GX 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
> - GX 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
> - G12 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,AMLOGIC_FBC_OPTION_MEM_SAVING)
> - G12 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC()AMLOGIC_FBC_LAYOUT_SCATTER, AMLOGIC_FBC_OPTION_MEM_SAVING)
> 
> And probably more depending on new SoCs and new codecs.

Thanks, I didn't know. I think V4L2 strategy here would be to pick and expose
just the minimum to make the mainline driver viable for 10bit decoding (unless
again you have a secondary format like P010 available). This would suite better
your users then just waiting for the perfect system to be in place.

p.s AMLOGIC_FBC_OPTION_MEM_SAVING is unlikely a layout from its name. FBC is
generally loss-less for correctness, but loss-less compression always have a
worse case scenerio bigger then the original, so we still need to reserve big
chunk of memory. For memory limited device, ARM came up with lossy compressor,
that guaranty a certain compression ratio. This name sounds like a similar
feature to me.

Nicolas

> 
> Neil
> 
> > 
> > > 
> > > For that, "am21c" name is moved to "amfbc" to reflect the upstream
> > > Amlogic Compressed framebuffer modifier naming.
> > > 
> > > Compressed frame buffers allocation is also cleaned up so it
> > > can be shared with the HEVC decoder implementation.
> > > 
> > > Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
> > > Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
> > > ---
> > >   drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
> > >   .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
> > >   .../media/meson/vdec/codec_hevc_common.h      |   3 +-
> > >   drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
> > >   drivers/staging/media/meson/vdec/esparser.c   |   1 +
> > >   drivers/staging/media/meson/vdec/vdec.h       |   1 +
> > >   .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
> > >   .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
> > >   8 files changed, 161 insertions(+), 97 deletions(-)
> > > 
> > > diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
> > > index c61128fc4bb9..d53c9a464bde 100644
> > > --- a/drivers/staging/media/meson/vdec/codec_h264.c
> > > +++ b/drivers/staging/media/meson/vdec/codec_h264.c
> > > @@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
> > >   		frame_width, frame_height, crop_right, crop_bottom);
> > >   
> > >   	codec_h264_set_par(sess);
> > > -	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
> > > +	amvdec_src_change(sess, frame_width, frame_height,
> > > +			  h264->max_refs + 5, 8);
> > >   }
> > >   
> > >   /*
> > > diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
> > > index 0315cc0911cd..1c74b4837dcb 100644
> > > --- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
> > > +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
> > > @@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
> > >   void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
> > >   {
> > >   	struct amvdec_core *core = sess->core;
> > > -	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
> > > -	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
> > > +	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
> > > +					 sess->pixfmt_cap, is_10bit);
> > > +	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
> > > +					       is_10bit, use_mmu);
> > > +	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
> > >   
> > >   	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
> > >   		/* Enable 2-plane reference read mode */
> > > @@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
> > >   		return;
> > >   	}
> > >   
> > > +	/* enable mem saving mode for 8-bit */
> > > +	if (!is_10bit)
> > > +		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
> > > +	else
> > > +		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
> > > +
> > >   	if (codec_hevc_use_mmu(core->platform->revision,
> > >   			       sess->pixfmt_cap, is_10bit))
> > >   		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
> > > +	else if (!is_10bit)
> > > +		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
> > >   	else
> > >   		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
> > >   
> > > @@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
> > >   
> > >   		idx = vb->index;
> > >   
> > > -		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
> > > +		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
> > >   			buf_y_paddr = comm->fbc_buffer_paddr[idx];
> > >   		else
> > >   			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
> > > @@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
> > >   {
> > >   	struct amvdec_core *core = sess->core;
> > >   	struct v4l2_m2m_buffer *buf;
> > > -	u32 revision = core->platform->revision;
> > >   	u32 pixfmt_cap = sess->pixfmt_cap;
> > > +	const u32 revision = core->platform->revision;
> > >   	int i;
> > >   
> > >   	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
> > > @@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
> > >   		dma_addr_t buf_uv_paddr = 0;
> > >   		u32 idx = vb->index;
> > >   
> > > -		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
> > > -			buf_y_paddr = comm->mmu_header_paddr[idx];
> > > -		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
> > > -			buf_y_paddr = comm->fbc_buffer_paddr[idx];
> > > -		else
> > > +		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
> > > +			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
> > > +				buf_y_paddr = comm->mmu_header_paddr[idx];
> > > +			else
> > > +				buf_y_paddr = comm->fbc_buffer_paddr[idx];
> > > +		} else {
> > >   			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
> > > +		}
> > >   
> > >   		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
> > >   				 buf_y_paddr >> 5);
> > > @@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
> > >   		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
> > >   }
> > >   
> > > -void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
> > > +void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
> > >   				 struct codec_hevc_common *comm)
> > >   {
> > >   	struct device *dev = sess->core->dev;
> > > -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
> > >   	int i;
> > >   
> > >   	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
> > > -		if (comm->fbc_buffer_vaddr[i]) {
> > > -			dma_free_coherent(dev, am21_size,
> > > -					  comm->fbc_buffer_vaddr[i],
> > > -					  comm->fbc_buffer_paddr[i]);
> > > -			comm->fbc_buffer_vaddr[i] = NULL;
> > > +		if (comm->mmu_header_vaddr[i]) {
> > > +			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> > > +					  comm->mmu_header_vaddr[i],
> > > +					  comm->mmu_header_paddr[i]);
> > > +			comm->mmu_header_vaddr[i] = NULL;
> > >   		}
> > >   	}
> > >   }
> > > -EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
> > > +EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
> > >   
> > > -static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
> > > +static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
> > >   					struct codec_hevc_common *comm)
> > >   {
> > >   	struct device *dev = sess->core->dev;
> > >   	struct v4l2_m2m_buffer *buf;
> > > -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
> > >   
> > >   	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
> > >   		u32 idx = buf->vb.vb2_buf.index;
> > >   		dma_addr_t paddr;
> > > -		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
> > > -						 GFP_KERNEL);
> > > +		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> > > +						 &paddr, GFP_KERNEL);
> > >   		if (!vaddr) {
> > > -			codec_hevc_free_fbc_buffers(sess, comm);
> > > +			codec_hevc_free_mmu_headers(sess, comm);
> > >   			return -ENOMEM;
> > >   		}
> > >   
> > > -		comm->fbc_buffer_vaddr[idx] = vaddr;
> > > -		comm->fbc_buffer_paddr[idx] = paddr;
> > > +		comm->mmu_header_vaddr[idx] = vaddr;
> > > +		comm->mmu_header_paddr[idx] = paddr;
> > >   	}
> > >   
> > >   	return 0;
> > >   }
> > >   
> > > -void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
> > > +void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
> > >   				 struct codec_hevc_common *comm)
> > >   {
> > >   	struct device *dev = sess->core->dev;
> > > +	u32 use_mmu;
> > > +	u32 am21_size;
> > >   	int i;
> > >   
> > > +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
> > > +				     sess->pixfmt_cap,
> > > +				sess->bitdepth == 10 ? 1 : 0);
> > > +
> > > +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
> > > +				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
> > > +
> > >   	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
> > > -		if (comm->mmu_header_vaddr[i]) {
> > > -			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> > > -					  comm->mmu_header_vaddr[i],
> > > -					  comm->mmu_header_paddr[i]);
> > > -			comm->mmu_header_vaddr[i] = NULL;
> > > +		if (comm->fbc_buffer_vaddr[i]) {
> > > +			dma_free_coherent(dev, am21_size,
> > > +					  comm->fbc_buffer_vaddr[i],
> > > +					  comm->fbc_buffer_paddr[i]);
> > > +			comm->fbc_buffer_vaddr[i] = NULL;
> > >   		}
> > >   	}
> > >   
> > > @@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
> > >   				  comm->mmu_map_paddr);
> > >   		comm->mmu_map_vaddr = NULL;
> > >   	}
> > > +
> > > +	codec_hevc_free_mmu_headers(sess, comm);
> > >   }
> > > -EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
> > > +EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
> > >   
> > > -static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
> > > +static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
> > >   					struct codec_hevc_common *comm)
> > >   {
> > >   	struct device *dev = sess->core->dev;
> > >   	struct v4l2_m2m_buffer *buf;
> > > +	u32 use_mmu;
> > > +	u32 am21_size;
> > > +	const u32 revision = sess->core->platform->revision;
> > > +	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
> > > +	int ret;
> > >   
> > > -	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
> > > -						 &comm->mmu_map_paddr,
> > > -						 GFP_KERNEL);
> > > -	if (!comm->mmu_map_vaddr)
> > > -		return -ENOMEM;
> > > +	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
> > > +				     is_10bit);
> > > +
> > > +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
> > > +				      is_10bit, use_mmu);
> > >   
> > >   	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
> > >   		u32 idx = buf->vb.vb2_buf.index;
> > >   		dma_addr_t paddr;
> > > -		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> > > -						 &paddr, GFP_KERNEL);
> > > +
> > > +		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
> > > +						 GFP_KERNEL);
> > >   		if (!vaddr) {
> > > -			codec_hevc_free_mmu_headers(sess, comm);
> > > +			codec_hevc_free_fbc_buffers(sess, comm);
> > >   			return -ENOMEM;
> > >   		}
> > >   
> > > -		comm->mmu_header_vaddr[idx] = vaddr;
> > > -		comm->mmu_header_paddr[idx] = paddr;
> > > +		comm->fbc_buffer_vaddr[idx] = vaddr;
> > > +		comm->fbc_buffer_paddr[idx] = paddr;
> > > +	}
> > > +
> > > +	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
> > > +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> > > +		ret = codec_hevc_alloc_mmu_headers(sess, comm);
> > > +		if (ret) {
> > > +			codec_hevc_free_fbc_buffers(sess, comm);
> > > +			return ret;
> > > +		}
> > >   	}
> > >   
> > >   	return 0;
> > > @@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
> > >   			     int is_10bit)
> > >   {
> > >   	struct amvdec_core *core = sess->core;
> > > +	struct device *dev = core->dev;
> > >   	int ret;
> > >   
> > > -	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> > > -		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
> > > -		if (ret)
> > > -			return ret;
> > > +	if (codec_hevc_use_mmu(core->platform->revision,
> > > +			       sess->pixfmt_cap, is_10bit)) {
> > > +		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
> > > +							 &comm->mmu_map_paddr,
> > > +							 GFP_KERNEL);
> > > +		if (!comm->mmu_map_vaddr)
> > > +			return -ENOMEM;
> > >   	}
> > >   
> > >   	if (codec_hevc_use_mmu(core->platform->revision,
> > > -			       sess->pixfmt_cap, is_10bit)) {
> > > -		ret = codec_hevc_alloc_mmu_headers(sess, comm);
> > > -		if (ret) {
> > > -			codec_hevc_free_fbc_buffers(sess, comm);
> > > +			       sess->pixfmt_cap, is_10bit) ||
> > > +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> > > +		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
> > > +		if (ret)
> > >   			return ret;
> > > -		}
> > >   	}
> > >   
> > >   	if (core->platform->revision == VDEC_REVISION_GXBB)
> > > @@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
> > >   
> > >   void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
> > >   			     struct codec_hevc_common *comm,
> > > -			     struct vb2_buffer *vb)
> > > +			     struct vb2_buffer *vb,
> > > +			     u32 is_10bit)
> > >   {
> > > -	u32 size = amvdec_am21c_size(sess->width, sess->height);
> > > -	u32 nb_pages = size / PAGE_SIZE;
> > > +	u32 use_mmu;
> > > +	u32 size;
> > > +	u32 nb_pages;
> > >   	u32 *mmu_map = comm->mmu_map_vaddr;
> > >   	u32 first_page;
> > >   	u32 i;
> > >   
> > > -	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
> > > -		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
> > > -	else
> > > -		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
> > > +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
> > > +				     sess->pixfmt_cap, is_10bit);
> > > +
> > > +	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
> > > +				 use_mmu);
> > >   
> > > +	nb_pages = size / PAGE_SIZE;
> > > +	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
> > >   	for (i = 0; i < nb_pages; ++i)
> > >   		mmu_map[i] = first_page + i;
> > >   }
> > > diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
> > > index cf072b8a9da2..13f9f1d90a94 100644
> > > --- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
> > > +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
> > > @@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
> > >   
> > >   void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
> > >   			     struct codec_hevc_common *comm,
> > > -			     struct vb2_buffer *vb);
> > > +			     struct vb2_buffer *vb,
> > > +			     u32 is_10bit);
> > >   
> > >   #endif
> > > diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
> > > index 394df5761556..8e3bbf0db4b3 100644
> > > --- a/drivers/staging/media/meson/vdec/codec_vp9.c
> > > +++ b/drivers/staging/media/meson/vdec/codec_vp9.c
> > > @@ -458,12 +458,6 @@ struct codec_vp9 {
> > >   	struct list_head ref_frames_list;
> > >   	u32 frames_num;
> > >   
> > > -	/* In case of downsampling (decoding with FBC but outputting in NV12M),
> > > -	 * we need to allocate additional buffers for FBC.
> > > -	 */
> > > -	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
> > > -	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
> > > -
> > >   	int ref_frame_map[REF_FRAMES];
> > >   	int next_ref_frame_map[REF_FRAMES];
> > >   	struct vp9_frame *frame_refs[REFS_PER_FRAME];
> > > @@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
> > >   		buf_y_paddr =
> > >   		       vb2_dma_contig_plane_dma_addr(vb, 0);
> > >   
> > > -	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
> > > -		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
> > > -		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
> > > +	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
> > >   		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
> > > -	}
> > >   
> > >   	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
> > >   		buf_y_paddr =
> > > @@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
> > >   
> > >   	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
> > >   			       vp9->is_10bit)) {
> > > -		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
> > > -				 vp9->common.mmu_header_paddr[vb->index]);
> > > +		dma_addr_t header_adr;
> > > +
> > > +		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
> > > +			header_adr = vp9->common.mmu_header_paddr[vb->index];
> > > +		else
> > > +			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
> > > +		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
> > >   		/* use HEVC_CM_HEADER_START_ADDR */
> > >   		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
> > >   	}
> > > @@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
> > >   {
> > >   	struct amvdec_core *core = sess->core;
> > >   	u32 scale = 0;
> > > +	u32 use_mmu;
> > >   	u32 sz;
> > >   	int i;
> > >   
> > > +	use_mmu = codec_hevc_use_mmu(core->platform->revision,
> > > +				     sess->pixfmt_cap, vp9->is_10bit);
> > > +
> > >   	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
> > >   	codec_vp9_set_refs(sess, vp9);
> > >   	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
> > > @@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
> > >   		    vp9->frame_refs[i]->height != vp9->height)
> > >   			scale = 1;
> > >   
> > > -		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
> > > -					    vp9->frame_refs[i]->height);
> > > +		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
> > > +					    vp9->frame_refs[i]->height,
> > > +					    vp9->is_10bit, use_mmu);
> > >   
> > >   		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
> > >   				 vp9->frame_refs[i]->width);
> > > @@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
> > >   	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
> > >   			       vp9->is_10bit))
> > >   		codec_hevc_fill_mmu_map(sess, &vp9->common,
> > > -					&vp9->cur_frame->vbuf->vb2_buf);
> > > +					&vp9->cur_frame->vbuf->vb2_buf,
> > > +					vp9->is_10bit);
> > >   
> > >   	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
> > >   
> > > @@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
> > >   
> > >   	codec_vp9_fetch_rpm(sess);
> > >   	if (codec_vp9_process_rpm(vp9)) {
> > > -		amvdec_src_change(sess, vp9->width, vp9->height, 16);
> > > +		amvdec_src_change(sess, vp9->width, vp9->height, 16,
> > > +				  vp9->is_10bit ? 10 : 8);
> > >   
> > >   		/* No frame is actually processed */
> > >   		vp9->cur_frame = NULL;
> > > diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
> > > index 1904d58875ad..3cd29ab4f979 100644
> > > --- a/drivers/staging/media/meson/vdec/esparser.c
> > > +++ b/drivers/staging/media/meson/vdec/esparser.c
> > > @@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
> > >   		if (esparser_vififo_get_free_space(sess) < payload_size ||
> > >   		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
> > >   			return -EAGAIN;
> > > +
> > >   	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
> > >   		return -EAGAIN;
> > >   	}
> > > diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
> > > index 0906b8fb5cc6..a48170fe4cff 100644
> > > --- a/drivers/staging/media/meson/vdec/vdec.h
> > > +++ b/drivers/staging/media/meson/vdec/vdec.h
> > > @@ -244,6 +244,7 @@ struct amvdec_session {
> > >   	u32 width;
> > >   	u32 height;
> > >   	u32 colorspace;
> > > +	u32 bitdepth;
> > >   	u8 ycbcr_enc;
> > >   	u8 quantization;
> > >   	u8 xfer_func;
> > > diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
> > > index 7d2a75653250..fef76142f0c5 100644
> > > --- a/drivers/staging/media/meson/vdec/vdec_helpers.c
> > > +++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
> > > @@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
> > >   }
> > >   EXPORT_SYMBOL_GPL(amvdec_write_parser);
> > >   
> > > -/* 4 KiB per 64x32 block */
> > > -u32 amvdec_am21c_body_size(u32 width, u32 height)
> > > +/* AMFBC body is made out of 64x32 blocks with varying block size */
> > > +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
> > >   {
> > >   	u32 width_64 = ALIGN(width, 64) / 64;
> > >   	u32 height_32 = ALIGN(height, 32) / 32;
> > > +	u32 blk_size = 4096;
> > >   
> > > -	return SZ_4K * width_64 * height_32;
> > > +	if (!is_10bit) {
> > > +		if (use_mmu)
> > > +			blk_size = 3200;
> > > +		else
> > > +			blk_size = 3072;
> > > +	}
> > > +
> > > +	return blk_size * width_64 * height_32;
> > >   }
> > > -EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
> > > +EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
> > >   
> > >   /* 32 bytes per 128x64 block */
> > > -u32 amvdec_am21c_head_size(u32 width, u32 height)
> > > +u32 amvdec_amfbc_head_size(u32 width, u32 height)
> > >   {
> > >   	u32 width_128 = ALIGN(width, 128) / 128;
> > >   	u32 height_64 = ALIGN(height, 64) / 64;
> > >   
> > >   	return 32 * width_128 * height_64;
> > >   }
> > > -EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
> > > +EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
> > >   
> > > -u32 amvdec_am21c_size(u32 width, u32 height)
> > > +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
> > >   {
> > > -	return ALIGN(amvdec_am21c_body_size(width, height) +
> > > -		     amvdec_am21c_head_size(width, height), SZ_64K);
> > > +	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
> > > +		     amvdec_amfbc_head_size(width, height), SZ_64K);
> > >   }
> > > -EXPORT_SYMBOL_GPL(amvdec_am21c_size);
> > > +EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
> > >   
> > >   static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
> > >   {
> > > @@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
> > >   EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
> > >   
> > >   void amvdec_src_change(struct amvdec_session *sess, u32 width,
> > > -		       u32 height, u32 dpb_size)
> > > +		       u32 height, u32 dpb_size, u32 bitdepth)
> > >   {
> > >   	static const struct v4l2_event ev = {
> > >   		.type = V4L2_EVENT_SOURCE_CHANGE,
> > > @@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
> > >   
> > >   	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
> > >   
> > > +	sess->bitdepth = bitdepth;
> > > +
> > >   	/*
> > >   	 * Check if the capture queue is already configured well for our
> > > -	 * usecase. If so, keep decoding with it and do not send the event
> > > +	 * usecase. If so, keep decoding with it.
> > >   	 */
> > >   	if (sess->streamon_cap &&
> > >   	    sess->width == width &&
> > >   	    sess->height == height &&
> > >   	    dpb_size <= sess->num_dst_bufs) {
> > >   		sess->fmt_out->codec_ops->resume(sess);
> > > -		return;
> > > +	} else {
> > > +		sess->status = STATUS_NEEDS_RESUME;
> > > +		sess->changed_format = 0;
> > >   	}
> > >   
> > > -	sess->changed_format = 0;
> > >   	sess->width = width;
> > >   	sess->height = height;
> > > -	sess->status = STATUS_NEEDS_RESUME;
> > >   
> > > -	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
> > > -		width, height, dpb_size);
> > > +	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
> > > +		width, height, dpb_size, bitdepth);
> > >   	v4l2_event_queue_fh(&sess->fh, &ev);
> > >   }
> > >   EXPORT_SYMBOL_GPL(amvdec_src_change);
> > > diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
> > > index 4bf3e61d081b..1a711679d26a 100644
> > > --- a/drivers/staging/media/meson/vdec/vdec_helpers.h
> > > +++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
> > > @@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
> > >   u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
> > >   void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
> > >   
> > > -u32 amvdec_am21c_body_size(u32 width, u32 height);
> > > -u32 amvdec_am21c_head_size(u32 width, u32 height);
> > > -u32 amvdec_am21c_size(u32 width, u32 height);
> > > +/* Helpers for the Amlogic compressed framebuffer format */
> > > +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
> > > +u32 amvdec_amfbc_head_size(u32 width, u32 height);
> > > +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
> > >   
> > >   /**
> > >    * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
> > > @@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
> > >    * @width: picture width detected by the hardware
> > >    * @height: picture height detected by the hardware
> > >    * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
> > > + * @bitdepth: Bit depth (usually 10 or 8) of the coded content
> > >    */
> > >   void amvdec_src_change(struct amvdec_session *sess, u32 width,
> > > -		       u32 height, u32 dpb_size);
> > > +		       u32 height, u32 dpb_size, u32 bitdepth);
> > >   
> > >   /**
> > >    * amvdec_abort() - Abort the current decoding session
> > 
> 


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Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Nicolas Dufresne]

Le mardi 24 janvier 2023 à 16:26 +0100, Neil Armstrong a écrit :
> On 24/01/2023 16:21, Nicolas Dufresne wrote:
> > Hi,
> > 
> > Le mardi 24 janvier 2023 à 03:40 +0000, Christian Hewitt a écrit :
> > > From: Benjamin Roszak <benjamin545@gmail.com>
> > > 
> > > In order to support 10bit bitstream decoding, buffers and MMU
> > > handling must be cleaned up to support either downscale output
> > > from compressed 10bit decoding to uncompressed 8bit NV12 output
> > > or to compressed 10bit proprietary encoded frame format.
> > 
> > I understand this is step forward, and agree with the patches in general, though
> > I'd like to know if we can expect 10bit secondary buffers in the future ? Or is
> > the AMFBC that only 10bit format supported ? Should be expect the 10bit format
> > definition to be added later ?
> 
> The support exist, but it stopped when nobody aggreed on how to handle the different
> layouts generated by the decoder.
> 
> There's at least 4 possible layouts vs how we represent then in DRM :
> - GX 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
> - GX 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
> - G12 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,AMLOGIC_FBC_OPTION_MEM_SAVING)
> - G12 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC()AMLOGIC_FBC_LAYOUT_SCATTER, AMLOGIC_FBC_OPTION_MEM_SAVING)
> 
> And probably more depending on new SoCs and new codecs.

Thanks, I didn't know. I think V4L2 strategy here would be to pick and expose
just the minimum to make the mainline driver viable for 10bit decoding (unless
again you have a secondary format like P010 available). This would suite better
your users then just waiting for the perfect system to be in place.

p.s AMLOGIC_FBC_OPTION_MEM_SAVING is unlikely a layout from its name. FBC is
generally loss-less for correctness, but loss-less compression always have a
worse case scenerio bigger then the original, so we still need to reserve big
chunk of memory. For memory limited device, ARM came up with lossy compressor,
that guaranty a certain compression ratio. This name sounds like a similar
feature to me.

Nicolas

> 
> Neil
> 
> > 
> > > 
> > > For that, "am21c" name is moved to "amfbc" to reflect the upstream
> > > Amlogic Compressed framebuffer modifier naming.
> > > 
> > > Compressed frame buffers allocation is also cleaned up so it
> > > can be shared with the HEVC decoder implementation.
> > > 
> > > Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
> > > Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
> > > ---
> > >   drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
> > >   .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
> > >   .../media/meson/vdec/codec_hevc_common.h      |   3 +-
> > >   drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
> > >   drivers/staging/media/meson/vdec/esparser.c   |   1 +
> > >   drivers/staging/media/meson/vdec/vdec.h       |   1 +
> > >   .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
> > >   .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
> > >   8 files changed, 161 insertions(+), 97 deletions(-)
> > > 
> > > diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
> > > index c61128fc4bb9..d53c9a464bde 100644
> > > --- a/drivers/staging/media/meson/vdec/codec_h264.c
> > > +++ b/drivers/staging/media/meson/vdec/codec_h264.c
> > > @@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
> > >   		frame_width, frame_height, crop_right, crop_bottom);
> > >   
> > >   	codec_h264_set_par(sess);
> > > -	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
> > > +	amvdec_src_change(sess, frame_width, frame_height,
> > > +			  h264->max_refs + 5, 8);
> > >   }
> > >   
> > >   /*
> > > diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
> > > index 0315cc0911cd..1c74b4837dcb 100644
> > > --- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
> > > +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
> > > @@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
> > >   void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
> > >   {
> > >   	struct amvdec_core *core = sess->core;
> > > -	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
> > > -	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
> > > +	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
> > > +					 sess->pixfmt_cap, is_10bit);
> > > +	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
> > > +					       is_10bit, use_mmu);
> > > +	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
> > >   
> > >   	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
> > >   		/* Enable 2-plane reference read mode */
> > > @@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
> > >   		return;
> > >   	}
> > >   
> > > +	/* enable mem saving mode for 8-bit */
> > > +	if (!is_10bit)
> > > +		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
> > > +	else
> > > +		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
> > > +
> > >   	if (codec_hevc_use_mmu(core->platform->revision,
> > >   			       sess->pixfmt_cap, is_10bit))
> > >   		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
> > > +	else if (!is_10bit)
> > > +		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
> > >   	else
> > >   		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
> > >   
> > > @@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
> > >   
> > >   		idx = vb->index;
> > >   
> > > -		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
> > > +		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
> > >   			buf_y_paddr = comm->fbc_buffer_paddr[idx];
> > >   		else
> > >   			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
> > > @@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
> > >   {
> > >   	struct amvdec_core *core = sess->core;
> > >   	struct v4l2_m2m_buffer *buf;
> > > -	u32 revision = core->platform->revision;
> > >   	u32 pixfmt_cap = sess->pixfmt_cap;
> > > +	const u32 revision = core->platform->revision;
> > >   	int i;
> > >   
> > >   	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
> > > @@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
> > >   		dma_addr_t buf_uv_paddr = 0;
> > >   		u32 idx = vb->index;
> > >   
> > > -		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
> > > -			buf_y_paddr = comm->mmu_header_paddr[idx];
> > > -		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
> > > -			buf_y_paddr = comm->fbc_buffer_paddr[idx];
> > > -		else
> > > +		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
> > > +			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
> > > +				buf_y_paddr = comm->mmu_header_paddr[idx];
> > > +			else
> > > +				buf_y_paddr = comm->fbc_buffer_paddr[idx];
> > > +		} else {
> > >   			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
> > > +		}
> > >   
> > >   		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
> > >   				 buf_y_paddr >> 5);
> > > @@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
> > >   		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
> > >   }
> > >   
> > > -void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
> > > +void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
> > >   				 struct codec_hevc_common *comm)
> > >   {
> > >   	struct device *dev = sess->core->dev;
> > > -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
> > >   	int i;
> > >   
> > >   	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
> > > -		if (comm->fbc_buffer_vaddr[i]) {
> > > -			dma_free_coherent(dev, am21_size,
> > > -					  comm->fbc_buffer_vaddr[i],
> > > -					  comm->fbc_buffer_paddr[i]);
> > > -			comm->fbc_buffer_vaddr[i] = NULL;
> > > +		if (comm->mmu_header_vaddr[i]) {
> > > +			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> > > +					  comm->mmu_header_vaddr[i],
> > > +					  comm->mmu_header_paddr[i]);
> > > +			comm->mmu_header_vaddr[i] = NULL;
> > >   		}
> > >   	}
> > >   }
> > > -EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
> > > +EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
> > >   
> > > -static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
> > > +static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
> > >   					struct codec_hevc_common *comm)
> > >   {
> > >   	struct device *dev = sess->core->dev;
> > >   	struct v4l2_m2m_buffer *buf;
> > > -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
> > >   
> > >   	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
> > >   		u32 idx = buf->vb.vb2_buf.index;
> > >   		dma_addr_t paddr;
> > > -		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
> > > -						 GFP_KERNEL);
> > > +		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> > > +						 &paddr, GFP_KERNEL);
> > >   		if (!vaddr) {
> > > -			codec_hevc_free_fbc_buffers(sess, comm);
> > > +			codec_hevc_free_mmu_headers(sess, comm);
> > >   			return -ENOMEM;
> > >   		}
> > >   
> > > -		comm->fbc_buffer_vaddr[idx] = vaddr;
> > > -		comm->fbc_buffer_paddr[idx] = paddr;
> > > +		comm->mmu_header_vaddr[idx] = vaddr;
> > > +		comm->mmu_header_paddr[idx] = paddr;
> > >   	}
> > >   
> > >   	return 0;
> > >   }
> > >   
> > > -void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
> > > +void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
> > >   				 struct codec_hevc_common *comm)
> > >   {
> > >   	struct device *dev = sess->core->dev;
> > > +	u32 use_mmu;
> > > +	u32 am21_size;
> > >   	int i;
> > >   
> > > +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
> > > +				     sess->pixfmt_cap,
> > > +				sess->bitdepth == 10 ? 1 : 0);
> > > +
> > > +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
> > > +				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
> > > +
> > >   	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
> > > -		if (comm->mmu_header_vaddr[i]) {
> > > -			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> > > -					  comm->mmu_header_vaddr[i],
> > > -					  comm->mmu_header_paddr[i]);
> > > -			comm->mmu_header_vaddr[i] = NULL;
> > > +		if (comm->fbc_buffer_vaddr[i]) {
> > > +			dma_free_coherent(dev, am21_size,
> > > +					  comm->fbc_buffer_vaddr[i],
> > > +					  comm->fbc_buffer_paddr[i]);
> > > +			comm->fbc_buffer_vaddr[i] = NULL;
> > >   		}
> > >   	}
> > >   
> > > @@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
> > >   				  comm->mmu_map_paddr);
> > >   		comm->mmu_map_vaddr = NULL;
> > >   	}
> > > +
> > > +	codec_hevc_free_mmu_headers(sess, comm);
> > >   }
> > > -EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
> > > +EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
> > >   
> > > -static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
> > > +static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
> > >   					struct codec_hevc_common *comm)
> > >   {
> > >   	struct device *dev = sess->core->dev;
> > >   	struct v4l2_m2m_buffer *buf;
> > > +	u32 use_mmu;
> > > +	u32 am21_size;
> > > +	const u32 revision = sess->core->platform->revision;
> > > +	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
> > > +	int ret;
> > >   
> > > -	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
> > > -						 &comm->mmu_map_paddr,
> > > -						 GFP_KERNEL);
> > > -	if (!comm->mmu_map_vaddr)
> > > -		return -ENOMEM;
> > > +	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
> > > +				     is_10bit);
> > > +
> > > +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
> > > +				      is_10bit, use_mmu);
> > >   
> > >   	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
> > >   		u32 idx = buf->vb.vb2_buf.index;
> > >   		dma_addr_t paddr;
> > > -		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
> > > -						 &paddr, GFP_KERNEL);
> > > +
> > > +		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
> > > +						 GFP_KERNEL);
> > >   		if (!vaddr) {
> > > -			codec_hevc_free_mmu_headers(sess, comm);
> > > +			codec_hevc_free_fbc_buffers(sess, comm);
> > >   			return -ENOMEM;
> > >   		}
> > >   
> > > -		comm->mmu_header_vaddr[idx] = vaddr;
> > > -		comm->mmu_header_paddr[idx] = paddr;
> > > +		comm->fbc_buffer_vaddr[idx] = vaddr;
> > > +		comm->fbc_buffer_paddr[idx] = paddr;
> > > +	}
> > > +
> > > +	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
> > > +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> > > +		ret = codec_hevc_alloc_mmu_headers(sess, comm);
> > > +		if (ret) {
> > > +			codec_hevc_free_fbc_buffers(sess, comm);
> > > +			return ret;
> > > +		}
> > >   	}
> > >   
> > >   	return 0;
> > > @@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
> > >   			     int is_10bit)
> > >   {
> > >   	struct amvdec_core *core = sess->core;
> > > +	struct device *dev = core->dev;
> > >   	int ret;
> > >   
> > > -	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> > > -		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
> > > -		if (ret)
> > > -			return ret;
> > > +	if (codec_hevc_use_mmu(core->platform->revision,
> > > +			       sess->pixfmt_cap, is_10bit)) {
> > > +		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
> > > +							 &comm->mmu_map_paddr,
> > > +							 GFP_KERNEL);
> > > +		if (!comm->mmu_map_vaddr)
> > > +			return -ENOMEM;
> > >   	}
> > >   
> > >   	if (codec_hevc_use_mmu(core->platform->revision,
> > > -			       sess->pixfmt_cap, is_10bit)) {
> > > -		ret = codec_hevc_alloc_mmu_headers(sess, comm);
> > > -		if (ret) {
> > > -			codec_hevc_free_fbc_buffers(sess, comm);
> > > +			       sess->pixfmt_cap, is_10bit) ||
> > > +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
> > > +		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
> > > +		if (ret)
> > >   			return ret;
> > > -		}
> > >   	}
> > >   
> > >   	if (core->platform->revision == VDEC_REVISION_GXBB)
> > > @@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
> > >   
> > >   void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
> > >   			     struct codec_hevc_common *comm,
> > > -			     struct vb2_buffer *vb)
> > > +			     struct vb2_buffer *vb,
> > > +			     u32 is_10bit)
> > >   {
> > > -	u32 size = amvdec_am21c_size(sess->width, sess->height);
> > > -	u32 nb_pages = size / PAGE_SIZE;
> > > +	u32 use_mmu;
> > > +	u32 size;
> > > +	u32 nb_pages;
> > >   	u32 *mmu_map = comm->mmu_map_vaddr;
> > >   	u32 first_page;
> > >   	u32 i;
> > >   
> > > -	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
> > > -		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
> > > -	else
> > > -		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
> > > +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
> > > +				     sess->pixfmt_cap, is_10bit);
> > > +
> > > +	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
> > > +				 use_mmu);
> > >   
> > > +	nb_pages = size / PAGE_SIZE;
> > > +	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
> > >   	for (i = 0; i < nb_pages; ++i)
> > >   		mmu_map[i] = first_page + i;
> > >   }
> > > diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
> > > index cf072b8a9da2..13f9f1d90a94 100644
> > > --- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
> > > +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
> > > @@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
> > >   
> > >   void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
> > >   			     struct codec_hevc_common *comm,
> > > -			     struct vb2_buffer *vb);
> > > +			     struct vb2_buffer *vb,
> > > +			     u32 is_10bit);
> > >   
> > >   #endif
> > > diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
> > > index 394df5761556..8e3bbf0db4b3 100644
> > > --- a/drivers/staging/media/meson/vdec/codec_vp9.c
> > > +++ b/drivers/staging/media/meson/vdec/codec_vp9.c
> > > @@ -458,12 +458,6 @@ struct codec_vp9 {
> > >   	struct list_head ref_frames_list;
> > >   	u32 frames_num;
> > >   
> > > -	/* In case of downsampling (decoding with FBC but outputting in NV12M),
> > > -	 * we need to allocate additional buffers for FBC.
> > > -	 */
> > > -	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
> > > -	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
> > > -
> > >   	int ref_frame_map[REF_FRAMES];
> > >   	int next_ref_frame_map[REF_FRAMES];
> > >   	struct vp9_frame *frame_refs[REFS_PER_FRAME];
> > > @@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
> > >   		buf_y_paddr =
> > >   		       vb2_dma_contig_plane_dma_addr(vb, 0);
> > >   
> > > -	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
> > > -		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
> > > -		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
> > > +	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
> > >   		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
> > > -	}
> > >   
> > >   	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
> > >   		buf_y_paddr =
> > > @@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
> > >   
> > >   	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
> > >   			       vp9->is_10bit)) {
> > > -		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
> > > -				 vp9->common.mmu_header_paddr[vb->index]);
> > > +		dma_addr_t header_adr;
> > > +
> > > +		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
> > > +			header_adr = vp9->common.mmu_header_paddr[vb->index];
> > > +		else
> > > +			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
> > > +		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
> > >   		/* use HEVC_CM_HEADER_START_ADDR */
> > >   		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
> > >   	}
> > > @@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
> > >   {
> > >   	struct amvdec_core *core = sess->core;
> > >   	u32 scale = 0;
> > > +	u32 use_mmu;
> > >   	u32 sz;
> > >   	int i;
> > >   
> > > +	use_mmu = codec_hevc_use_mmu(core->platform->revision,
> > > +				     sess->pixfmt_cap, vp9->is_10bit);
> > > +
> > >   	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
> > >   	codec_vp9_set_refs(sess, vp9);
> > >   	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
> > > @@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
> > >   		    vp9->frame_refs[i]->height != vp9->height)
> > >   			scale = 1;
> > >   
> > > -		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
> > > -					    vp9->frame_refs[i]->height);
> > > +		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
> > > +					    vp9->frame_refs[i]->height,
> > > +					    vp9->is_10bit, use_mmu);
> > >   
> > >   		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
> > >   				 vp9->frame_refs[i]->width);
> > > @@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
> > >   	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
> > >   			       vp9->is_10bit))
> > >   		codec_hevc_fill_mmu_map(sess, &vp9->common,
> > > -					&vp9->cur_frame->vbuf->vb2_buf);
> > > +					&vp9->cur_frame->vbuf->vb2_buf,
> > > +					vp9->is_10bit);
> > >   
> > >   	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
> > >   
> > > @@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
> > >   
> > >   	codec_vp9_fetch_rpm(sess);
> > >   	if (codec_vp9_process_rpm(vp9)) {
> > > -		amvdec_src_change(sess, vp9->width, vp9->height, 16);
> > > +		amvdec_src_change(sess, vp9->width, vp9->height, 16,
> > > +				  vp9->is_10bit ? 10 : 8);
> > >   
> > >   		/* No frame is actually processed */
> > >   		vp9->cur_frame = NULL;
> > > diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
> > > index 1904d58875ad..3cd29ab4f979 100644
> > > --- a/drivers/staging/media/meson/vdec/esparser.c
> > > +++ b/drivers/staging/media/meson/vdec/esparser.c
> > > @@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
> > >   		if (esparser_vififo_get_free_space(sess) < payload_size ||
> > >   		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
> > >   			return -EAGAIN;
> > > +
> > >   	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
> > >   		return -EAGAIN;
> > >   	}
> > > diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
> > > index 0906b8fb5cc6..a48170fe4cff 100644
> > > --- a/drivers/staging/media/meson/vdec/vdec.h
> > > +++ b/drivers/staging/media/meson/vdec/vdec.h
> > > @@ -244,6 +244,7 @@ struct amvdec_session {
> > >   	u32 width;
> > >   	u32 height;
> > >   	u32 colorspace;
> > > +	u32 bitdepth;
> > >   	u8 ycbcr_enc;
> > >   	u8 quantization;
> > >   	u8 xfer_func;
> > > diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
> > > index 7d2a75653250..fef76142f0c5 100644
> > > --- a/drivers/staging/media/meson/vdec/vdec_helpers.c
> > > +++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
> > > @@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
> > >   }
> > >   EXPORT_SYMBOL_GPL(amvdec_write_parser);
> > >   
> > > -/* 4 KiB per 64x32 block */
> > > -u32 amvdec_am21c_body_size(u32 width, u32 height)
> > > +/* AMFBC body is made out of 64x32 blocks with varying block size */
> > > +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
> > >   {
> > >   	u32 width_64 = ALIGN(width, 64) / 64;
> > >   	u32 height_32 = ALIGN(height, 32) / 32;
> > > +	u32 blk_size = 4096;
> > >   
> > > -	return SZ_4K * width_64 * height_32;
> > > +	if (!is_10bit) {
> > > +		if (use_mmu)
> > > +			blk_size = 3200;
> > > +		else
> > > +			blk_size = 3072;
> > > +	}
> > > +
> > > +	return blk_size * width_64 * height_32;
> > >   }
> > > -EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
> > > +EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
> > >   
> > >   /* 32 bytes per 128x64 block */
> > > -u32 amvdec_am21c_head_size(u32 width, u32 height)
> > > +u32 amvdec_amfbc_head_size(u32 width, u32 height)
> > >   {
> > >   	u32 width_128 = ALIGN(width, 128) / 128;
> > >   	u32 height_64 = ALIGN(height, 64) / 64;
> > >   
> > >   	return 32 * width_128 * height_64;
> > >   }
> > > -EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
> > > +EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
> > >   
> > > -u32 amvdec_am21c_size(u32 width, u32 height)
> > > +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
> > >   {
> > > -	return ALIGN(amvdec_am21c_body_size(width, height) +
> > > -		     amvdec_am21c_head_size(width, height), SZ_64K);
> > > +	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
> > > +		     amvdec_amfbc_head_size(width, height), SZ_64K);
> > >   }
> > > -EXPORT_SYMBOL_GPL(amvdec_am21c_size);
> > > +EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
> > >   
> > >   static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
> > >   {
> > > @@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
> > >   EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
> > >   
> > >   void amvdec_src_change(struct amvdec_session *sess, u32 width,
> > > -		       u32 height, u32 dpb_size)
> > > +		       u32 height, u32 dpb_size, u32 bitdepth)
> > >   {
> > >   	static const struct v4l2_event ev = {
> > >   		.type = V4L2_EVENT_SOURCE_CHANGE,
> > > @@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
> > >   
> > >   	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
> > >   
> > > +	sess->bitdepth = bitdepth;
> > > +
> > >   	/*
> > >   	 * Check if the capture queue is already configured well for our
> > > -	 * usecase. If so, keep decoding with it and do not send the event
> > > +	 * usecase. If so, keep decoding with it.
> > >   	 */
> > >   	if (sess->streamon_cap &&
> > >   	    sess->width == width &&
> > >   	    sess->height == height &&
> > >   	    dpb_size <= sess->num_dst_bufs) {
> > >   		sess->fmt_out->codec_ops->resume(sess);
> > > -		return;
> > > +	} else {
> > > +		sess->status = STATUS_NEEDS_RESUME;
> > > +		sess->changed_format = 0;
> > >   	}
> > >   
> > > -	sess->changed_format = 0;
> > >   	sess->width = width;
> > >   	sess->height = height;
> > > -	sess->status = STATUS_NEEDS_RESUME;
> > >   
> > > -	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
> > > -		width, height, dpb_size);
> > > +	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
> > > +		width, height, dpb_size, bitdepth);
> > >   	v4l2_event_queue_fh(&sess->fh, &ev);
> > >   }
> > >   EXPORT_SYMBOL_GPL(amvdec_src_change);
> > > diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
> > > index 4bf3e61d081b..1a711679d26a 100644
> > > --- a/drivers/staging/media/meson/vdec/vdec_helpers.h
> > > +++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
> > > @@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
> > >   u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
> > >   void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
> > >   
> > > -u32 amvdec_am21c_body_size(u32 width, u32 height);
> > > -u32 amvdec_am21c_head_size(u32 width, u32 height);
> > > -u32 amvdec_am21c_size(u32 width, u32 height);
> > > +/* Helpers for the Amlogic compressed framebuffer format */
> > > +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
> > > +u32 amvdec_amfbc_head_size(u32 width, u32 height);
> > > +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
> > >   
> > >   /**
> > >    * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
> > > @@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
> > >    * @width: picture width detected by the hardware
> > >    * @height: picture height detected by the hardware
> > >    * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
> > > + * @bitdepth: Bit depth (usually 10 or 8) of the coded content
> > >    */
> > >   void amvdec_src_change(struct amvdec_session *sess, u32 width,
> > > -		       u32 height, u32 dpb_size);
> > > +		       u32 height, u32 dpb_size, u32 bitdepth);
> > >   
> > >   /**
> > >    * amvdec_abort() - Abort the current decoding session
> > 
> 


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Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[neil.armstrong]

On 24/01/2023 17:26, Nicolas Dufresne wrote:
> Le mardi 24 janvier 2023 à 16:26 +0100, Neil Armstrong a écrit :
>> On 24/01/2023 16:21, Nicolas Dufresne wrote:
>>> Hi,
>>>
>>> Le mardi 24 janvier 2023 à 03:40 +0000, Christian Hewitt a écrit :
>>>> From: Benjamin Roszak <benjamin545@gmail.com>
>>>>
>>>> In order to support 10bit bitstream decoding, buffers and MMU
>>>> handling must be cleaned up to support either downscale output
>>>> from compressed 10bit decoding to uncompressed 8bit NV12 output
>>>> or to compressed 10bit proprietary encoded frame format.
>>>
>>> I understand this is step forward, and agree with the patches in general, though
>>> I'd like to know if we can expect 10bit secondary buffers in the future ? Or is
>>> the AMFBC that only 10bit format supported ? Should be expect the 10bit format
>>> definition to be added later ?
>>
>> The support exist, but it stopped when nobody aggreed on how to handle the different
>> layouts generated by the decoder.
>>
>> There's at least 4 possible layouts vs how we represent then in DRM :
>> - GX 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
>> - GX 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
>> - G12 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,AMLOGIC_FBC_OPTION_MEM_SAVING)
>> - G12 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC()AMLOGIC_FBC_LAYOUT_SCATTER, AMLOGIC_FBC_OPTION_MEM_SAVING)
>>
>> And probably more depending on new SoCs and new codecs.
> 
> Thanks, I didn't know. I think V4L2 strategy here would be to pick and expose
> just the minimum to make the mainline driver viable for 10bit decoding (unless
> again you have a secondary format like P010 available). This would suite better
> your users then just waiting for the perfect system to be in place.
> 
> p.s AMLOGIC_FBC_OPTION_MEM_SAVING is unlikely a layout from its name. FBC is
> generally loss-less for correctness, but loss-less compression always have a
> worse case scenerio bigger then the original, so we still need to reserve big
> chunk of memory. For memory limited device, ARM came up with lossy compressor,
> that guaranty a certain compression ratio. This name sounds like a similar
> feature to me.

Ok it's not that simple, seems I need to do a recap of the situation.

The HW decoder is a firmware running on top of a set of propriatery (or perhaps
bought IPS, but hidden behind the firmware) HW.

There's 2 generations:
- the old generation supports only a single decoding at a time, and implements the
"old" codecs (MPEG-1/2, H264, ...)
- the new is build around the "HEVC" core to decode multiple streams with support
of loadable context, and supports H.264, HEVC and VP9 (and VC-1 on new SoCs).

I'll cover only the new core.

The new core supports decoding 8bit and 10bit streams (except for H264), but the
decoder only works on "compressed framebuffers", which is similar to the ARM one
or any other SoC vendor does internally in fact.

But the firmware supports copying the output frames in a non-compressed NV12 double
plane buffers (buffers can't be single, we need to provide 2 buffers with a specific
aligment), but we can also get the compresse buffers and feed them to the display unit.

But between generations, the compressed buffers layout & options generated by the
decoder firmware are different, but on the Display side the IP & the possible options
are the same.

So we *need* to know ther bpp and the compression layout + options on the display
side, and we can't use the SoC name for that, especially from ffmpeg or gstreamer.

But we already upstreamed the DRM modifier a few years ago, so this is done.

So now we need a way from V4L2 to get thoses informations from the /dev/video endpoint to
correctly set the fourcc + modifier for display.

We hoped we could use the same modifier as DRM, but it seems this is now out of scope.

Neil

> 
> Nicolas
> 
>>
>> Neil
>>
>>>
>>>>
>>>> For that, "am21c" name is moved to "amfbc" to reflect the upstream
>>>> Amlogic Compressed framebuffer modifier naming.
>>>>
>>>> Compressed frame buffers allocation is also cleaned up so it
>>>> can be shared with the HEVC decoder implementation.
>>>>
>>>> Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
>>>> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
>>>> ---
>>>>    drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
>>>>    .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
>>>>    .../media/meson/vdec/codec_hevc_common.h      |   3 +-
>>>>    drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
>>>>    drivers/staging/media/meson/vdec/esparser.c   |   1 +
>>>>    drivers/staging/media/meson/vdec/vdec.h       |   1 +
>>>>    .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
>>>>    .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
>>>>    8 files changed, 161 insertions(+), 97 deletions(-)
>>>>
>>>> diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
>>>> index c61128fc4bb9..d53c9a464bde 100644
>>>> --- a/drivers/staging/media/meson/vdec/codec_h264.c
>>>> +++ b/drivers/staging/media/meson/vdec/codec_h264.c
>>>> @@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
>>>>    		frame_width, frame_height, crop_right, crop_bottom);
>>>>    
>>>>    	codec_h264_set_par(sess);
>>>> -	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
>>>> +	amvdec_src_change(sess, frame_width, frame_height,
>>>> +			  h264->max_refs + 5, 8);
>>>>    }
>>>>    
>>>>    /*
>>>> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
>>>> index 0315cc0911cd..1c74b4837dcb 100644
>>>> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
>>>> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
>>>> @@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
>>>>    void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>>>>    {
>>>>    	struct amvdec_core *core = sess->core;
>>>> -	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
>>>> -	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
>>>> +	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
>>>> +					 sess->pixfmt_cap, is_10bit);
>>>> +	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
>>>> +					       is_10bit, use_mmu);
>>>> +	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
>>>>    
>>>>    	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
>>>>    		/* Enable 2-plane reference read mode */
>>>> @@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>>>>    		return;
>>>>    	}
>>>>    
>>>> +	/* enable mem saving mode for 8-bit */
>>>> +	if (!is_10bit)
>>>> +		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
>>>> +	else
>>>> +		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
>>>> +
>>>>    	if (codec_hevc_use_mmu(core->platform->revision,
>>>>    			       sess->pixfmt_cap, is_10bit))
>>>>    		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
>>>> +	else if (!is_10bit)
>>>> +		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
>>>>    	else
>>>>    		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
>>>>    
>>>> @@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
>>>>    
>>>>    		idx = vb->index;
>>>>    
>>>> -		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
>>>> +		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
>>>>    			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>>>>    		else
>>>>    			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
>>>> @@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>>>    {
>>>>    	struct amvdec_core *core = sess->core;
>>>>    	struct v4l2_m2m_buffer *buf;
>>>> -	u32 revision = core->platform->revision;
>>>>    	u32 pixfmt_cap = sess->pixfmt_cap;
>>>> +	const u32 revision = core->platform->revision;
>>>>    	int i;
>>>>    
>>>>    	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
>>>> @@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>>>    		dma_addr_t buf_uv_paddr = 0;
>>>>    		u32 idx = vb->index;
>>>>    
>>>> -		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
>>>> -			buf_y_paddr = comm->mmu_header_paddr[idx];
>>>> -		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
>>>> -			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>>>> -		else
>>>> +		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
>>>> +			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
>>>> +				buf_y_paddr = comm->mmu_header_paddr[idx];
>>>> +			else
>>>> +				buf_y_paddr = comm->fbc_buffer_paddr[idx];
>>>> +		} else {
>>>>    			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
>>>> +		}
>>>>    
>>>>    		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
>>>>    				 buf_y_paddr >> 5);
>>>> @@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>>>    		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
>>>>    }
>>>>    
>>>> -void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>>>> +void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>>>    				 struct codec_hevc_common *comm)
>>>>    {
>>>>    	struct device *dev = sess->core->dev;
>>>> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>>>>    	int i;
>>>>    
>>>>    	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
>>>> -		if (comm->fbc_buffer_vaddr[i]) {
>>>> -			dma_free_coherent(dev, am21_size,
>>>> -					  comm->fbc_buffer_vaddr[i],
>>>> -					  comm->fbc_buffer_paddr[i]);
>>>> -			comm->fbc_buffer_vaddr[i] = NULL;
>>>> +		if (comm->mmu_header_vaddr[i]) {
>>>> +			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>>>> +					  comm->mmu_header_vaddr[i],
>>>> +					  comm->mmu_header_paddr[i]);
>>>> +			comm->mmu_header_vaddr[i] = NULL;
>>>>    		}
>>>>    	}
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>>>> +EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>>>>    
>>>> -static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>>>> +static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>>>>    					struct codec_hevc_common *comm)
>>>>    {
>>>>    	struct device *dev = sess->core->dev;
>>>>    	struct v4l2_m2m_buffer *buf;
>>>> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>>>>    
>>>>    	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>>>>    		u32 idx = buf->vb.vb2_buf.index;
>>>>    		dma_addr_t paddr;
>>>> -		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
>>>> -						 GFP_KERNEL);
>>>> +		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>>>> +						 &paddr, GFP_KERNEL);
>>>>    		if (!vaddr) {
>>>> -			codec_hevc_free_fbc_buffers(sess, comm);
>>>> +			codec_hevc_free_mmu_headers(sess, comm);
>>>>    			return -ENOMEM;
>>>>    		}
>>>>    
>>>> -		comm->fbc_buffer_vaddr[idx] = vaddr;
>>>> -		comm->fbc_buffer_paddr[idx] = paddr;
>>>> +		comm->mmu_header_vaddr[idx] = vaddr;
>>>> +		comm->mmu_header_paddr[idx] = paddr;
>>>>    	}
>>>>    
>>>>    	return 0;
>>>>    }
>>>>    
>>>> -void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>>> +void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>>>>    				 struct codec_hevc_common *comm)
>>>>    {
>>>>    	struct device *dev = sess->core->dev;
>>>> +	u32 use_mmu;
>>>> +	u32 am21_size;
>>>>    	int i;
>>>>    
>>>> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
>>>> +				     sess->pixfmt_cap,
>>>> +				sess->bitdepth == 10 ? 1 : 0);
>>>> +
>>>> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
>>>> +				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
>>>> +
>>>>    	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
>>>> -		if (comm->mmu_header_vaddr[i]) {
>>>> -			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>>>> -					  comm->mmu_header_vaddr[i],
>>>> -					  comm->mmu_header_paddr[i]);
>>>> -			comm->mmu_header_vaddr[i] = NULL;
>>>> +		if (comm->fbc_buffer_vaddr[i]) {
>>>> +			dma_free_coherent(dev, am21_size,
>>>> +					  comm->fbc_buffer_vaddr[i],
>>>> +					  comm->fbc_buffer_paddr[i]);
>>>> +			comm->fbc_buffer_vaddr[i] = NULL;
>>>>    		}
>>>>    	}
>>>>    
>>>> @@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>>>    				  comm->mmu_map_paddr);
>>>>    		comm->mmu_map_vaddr = NULL;
>>>>    	}
>>>> +
>>>> +	codec_hevc_free_mmu_headers(sess, comm);
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>>>> +EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>>>>    
>>>> -static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>>>> +static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>>>>    					struct codec_hevc_common *comm)
>>>>    {
>>>>    	struct device *dev = sess->core->dev;
>>>>    	struct v4l2_m2m_buffer *buf;
>>>> +	u32 use_mmu;
>>>> +	u32 am21_size;
>>>> +	const u32 revision = sess->core->platform->revision;
>>>> +	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
>>>> +	int ret;
>>>>    
>>>> -	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
>>>> -						 &comm->mmu_map_paddr,
>>>> -						 GFP_KERNEL);
>>>> -	if (!comm->mmu_map_vaddr)
>>>> -		return -ENOMEM;
>>>> +	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
>>>> +				     is_10bit);
>>>> +
>>>> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
>>>> +				      is_10bit, use_mmu);
>>>>    
>>>>    	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>>>>    		u32 idx = buf->vb.vb2_buf.index;
>>>>    		dma_addr_t paddr;
>>>> -		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>>>> -						 &paddr, GFP_KERNEL);
>>>> +
>>>> +		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
>>>> +						 GFP_KERNEL);
>>>>    		if (!vaddr) {
>>>> -			codec_hevc_free_mmu_headers(sess, comm);
>>>> +			codec_hevc_free_fbc_buffers(sess, comm);
>>>>    			return -ENOMEM;
>>>>    		}
>>>>    
>>>> -		comm->mmu_header_vaddr[idx] = vaddr;
>>>> -		comm->mmu_header_paddr[idx] = paddr;
>>>> +		comm->fbc_buffer_vaddr[idx] = vaddr;
>>>> +		comm->fbc_buffer_paddr[idx] = paddr;
>>>> +	}
>>>> +
>>>> +	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
>>>> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>>>> +		ret = codec_hevc_alloc_mmu_headers(sess, comm);
>>>> +		if (ret) {
>>>> +			codec_hevc_free_fbc_buffers(sess, comm);
>>>> +			return ret;
>>>> +		}
>>>>    	}
>>>>    
>>>>    	return 0;
>>>> @@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>>>>    			     int is_10bit)
>>>>    {
>>>>    	struct amvdec_core *core = sess->core;
>>>> +	struct device *dev = core->dev;
>>>>    	int ret;
>>>>    
>>>> -	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>>>> -		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
>>>> -		if (ret)
>>>> -			return ret;
>>>> +	if (codec_hevc_use_mmu(core->platform->revision,
>>>> +			       sess->pixfmt_cap, is_10bit)) {
>>>> +		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
>>>> +							 &comm->mmu_map_paddr,
>>>> +							 GFP_KERNEL);
>>>> +		if (!comm->mmu_map_vaddr)
>>>> +			return -ENOMEM;
>>>>    	}
>>>>    
>>>>    	if (codec_hevc_use_mmu(core->platform->revision,
>>>> -			       sess->pixfmt_cap, is_10bit)) {
>>>> -		ret = codec_hevc_alloc_mmu_headers(sess, comm);
>>>> -		if (ret) {
>>>> -			codec_hevc_free_fbc_buffers(sess, comm);
>>>> +			       sess->pixfmt_cap, is_10bit) ||
>>>> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>>>> +		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
>>>> +		if (ret)
>>>>    			return ret;
>>>> -		}
>>>>    	}
>>>>    
>>>>    	if (core->platform->revision == VDEC_REVISION_GXBB)
>>>> @@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
>>>>    
>>>>    void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>>>>    			     struct codec_hevc_common *comm,
>>>> -			     struct vb2_buffer *vb)
>>>> +			     struct vb2_buffer *vb,
>>>> +			     u32 is_10bit)
>>>>    {
>>>> -	u32 size = amvdec_am21c_size(sess->width, sess->height);
>>>> -	u32 nb_pages = size / PAGE_SIZE;
>>>> +	u32 use_mmu;
>>>> +	u32 size;
>>>> +	u32 nb_pages;
>>>>    	u32 *mmu_map = comm->mmu_map_vaddr;
>>>>    	u32 first_page;
>>>>    	u32 i;
>>>>    
>>>> -	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
>>>> -		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>>>> -	else
>>>> -		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
>>>> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
>>>> +				     sess->pixfmt_cap, is_10bit);
>>>> +
>>>> +	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
>>>> +				 use_mmu);
>>>>    
>>>> +	nb_pages = size / PAGE_SIZE;
>>>> +	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>>>>    	for (i = 0; i < nb_pages; ++i)
>>>>    		mmu_map[i] = first_page + i;
>>>>    }
>>>> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
>>>> index cf072b8a9da2..13f9f1d90a94 100644
>>>> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
>>>> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
>>>> @@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>>>>    
>>>>    void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>>>>    			     struct codec_hevc_common *comm,
>>>> -			     struct vb2_buffer *vb);
>>>> +			     struct vb2_buffer *vb,
>>>> +			     u32 is_10bit);
>>>>    
>>>>    #endif
>>>> diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
>>>> index 394df5761556..8e3bbf0db4b3 100644
>>>> --- a/drivers/staging/media/meson/vdec/codec_vp9.c
>>>> +++ b/drivers/staging/media/meson/vdec/codec_vp9.c
>>>> @@ -458,12 +458,6 @@ struct codec_vp9 {
>>>>    	struct list_head ref_frames_list;
>>>>    	u32 frames_num;
>>>>    
>>>> -	/* In case of downsampling (decoding with FBC but outputting in NV12M),
>>>> -	 * we need to allocate additional buffers for FBC.
>>>> -	 */
>>>> -	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
>>>> -	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
>>>> -
>>>>    	int ref_frame_map[REF_FRAMES];
>>>>    	int next_ref_frame_map[REF_FRAMES];
>>>>    	struct vp9_frame *frame_refs[REFS_PER_FRAME];
>>>> @@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>>>>    		buf_y_paddr =
>>>>    		       vb2_dma_contig_plane_dma_addr(vb, 0);
>>>>    
>>>> -	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
>>>> -		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
>>>> -		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
>>>> +	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
>>>>    		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
>>>> -	}
>>>>    
>>>>    	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
>>>>    		buf_y_paddr =
>>>> @@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>>>>    
>>>>    	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>>>>    			       vp9->is_10bit)) {
>>>> -		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
>>>> -				 vp9->common.mmu_header_paddr[vb->index]);
>>>> +		dma_addr_t header_adr;
>>>> +
>>>> +		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
>>>> +			header_adr = vp9->common.mmu_header_paddr[vb->index];
>>>> +		else
>>>> +			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
>>>> +		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
>>>>    		/* use HEVC_CM_HEADER_START_ADDR */
>>>>    		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
>>>>    	}
>>>> @@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>>>>    {
>>>>    	struct amvdec_core *core = sess->core;
>>>>    	u32 scale = 0;
>>>> +	u32 use_mmu;
>>>>    	u32 sz;
>>>>    	int i;
>>>>    
>>>> +	use_mmu = codec_hevc_use_mmu(core->platform->revision,
>>>> +				     sess->pixfmt_cap, vp9->is_10bit);
>>>> +
>>>>    	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
>>>>    	codec_vp9_set_refs(sess, vp9);
>>>>    	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
>>>> @@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>>>>    		    vp9->frame_refs[i]->height != vp9->height)
>>>>    			scale = 1;
>>>>    
>>>> -		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
>>>> -					    vp9->frame_refs[i]->height);
>>>> +		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
>>>> +					    vp9->frame_refs[i]->height,
>>>> +					    vp9->is_10bit, use_mmu);
>>>>    
>>>>    		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
>>>>    				 vp9->frame_refs[i]->width);
>>>> @@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
>>>>    	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>>>>    			       vp9->is_10bit))
>>>>    		codec_hevc_fill_mmu_map(sess, &vp9->common,
>>>> -					&vp9->cur_frame->vbuf->vb2_buf);
>>>> +					&vp9->cur_frame->vbuf->vb2_buf,
>>>> +					vp9->is_10bit);
>>>>    
>>>>    	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
>>>>    
>>>> @@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
>>>>    
>>>>    	codec_vp9_fetch_rpm(sess);
>>>>    	if (codec_vp9_process_rpm(vp9)) {
>>>> -		amvdec_src_change(sess, vp9->width, vp9->height, 16);
>>>> +		amvdec_src_change(sess, vp9->width, vp9->height, 16,
>>>> +				  vp9->is_10bit ? 10 : 8);
>>>>    
>>>>    		/* No frame is actually processed */
>>>>    		vp9->cur_frame = NULL;
>>>> diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
>>>> index 1904d58875ad..3cd29ab4f979 100644
>>>> --- a/drivers/staging/media/meson/vdec/esparser.c
>>>> +++ b/drivers/staging/media/meson/vdec/esparser.c
>>>> @@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
>>>>    		if (esparser_vififo_get_free_space(sess) < payload_size ||
>>>>    		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
>>>>    			return -EAGAIN;
>>>> +
>>>>    	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
>>>>    		return -EAGAIN;
>>>>    	}
>>>> diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
>>>> index 0906b8fb5cc6..a48170fe4cff 100644
>>>> --- a/drivers/staging/media/meson/vdec/vdec.h
>>>> +++ b/drivers/staging/media/meson/vdec/vdec.h
>>>> @@ -244,6 +244,7 @@ struct amvdec_session {
>>>>    	u32 width;
>>>>    	u32 height;
>>>>    	u32 colorspace;
>>>> +	u32 bitdepth;
>>>>    	u8 ycbcr_enc;
>>>>    	u8 quantization;
>>>>    	u8 xfer_func;
>>>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
>>>> index 7d2a75653250..fef76142f0c5 100644
>>>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.c
>>>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
>>>> @@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
>>>>    }
>>>>    EXPORT_SYMBOL_GPL(amvdec_write_parser);
>>>>    
>>>> -/* 4 KiB per 64x32 block */
>>>> -u32 amvdec_am21c_body_size(u32 width, u32 height)
>>>> +/* AMFBC body is made out of 64x32 blocks with varying block size */
>>>> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>>>>    {
>>>>    	u32 width_64 = ALIGN(width, 64) / 64;
>>>>    	u32 height_32 = ALIGN(height, 32) / 32;
>>>> +	u32 blk_size = 4096;
>>>>    
>>>> -	return SZ_4K * width_64 * height_32;
>>>> +	if (!is_10bit) {
>>>> +		if (use_mmu)
>>>> +			blk_size = 3200;
>>>> +		else
>>>> +			blk_size = 3072;
>>>> +	}
>>>> +
>>>> +	return blk_size * width_64 * height_32;
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
>>>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
>>>>    
>>>>    /* 32 bytes per 128x64 block */
>>>> -u32 amvdec_am21c_head_size(u32 width, u32 height)
>>>> +u32 amvdec_amfbc_head_size(u32 width, u32 height)
>>>>    {
>>>>    	u32 width_128 = ALIGN(width, 128) / 128;
>>>>    	u32 height_64 = ALIGN(height, 64) / 64;
>>>>    
>>>>    	return 32 * width_128 * height_64;
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
>>>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
>>>>    
>>>> -u32 amvdec_am21c_size(u32 width, u32 height)
>>>> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>>>>    {
>>>> -	return ALIGN(amvdec_am21c_body_size(width, height) +
>>>> -		     amvdec_am21c_head_size(width, height), SZ_64K);
>>>> +	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
>>>> +		     amvdec_amfbc_head_size(width, height), SZ_64K);
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(amvdec_am21c_size);
>>>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
>>>>    
>>>>    static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
>>>>    {
>>>> @@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>>>>    EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
>>>>    
>>>>    void amvdec_src_change(struct amvdec_session *sess, u32 width,
>>>> -		       u32 height, u32 dpb_size)
>>>> +		       u32 height, u32 dpb_size, u32 bitdepth)
>>>>    {
>>>>    	static const struct v4l2_event ev = {
>>>>    		.type = V4L2_EVENT_SOURCE_CHANGE,
>>>> @@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
>>>>    
>>>>    	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
>>>>    
>>>> +	sess->bitdepth = bitdepth;
>>>> +
>>>>    	/*
>>>>    	 * Check if the capture queue is already configured well for our
>>>> -	 * usecase. If so, keep decoding with it and do not send the event
>>>> +	 * usecase. If so, keep decoding with it.
>>>>    	 */
>>>>    	if (sess->streamon_cap &&
>>>>    	    sess->width == width &&
>>>>    	    sess->height == height &&
>>>>    	    dpb_size <= sess->num_dst_bufs) {
>>>>    		sess->fmt_out->codec_ops->resume(sess);
>>>> -		return;
>>>> +	} else {
>>>> +		sess->status = STATUS_NEEDS_RESUME;
>>>> +		sess->changed_format = 0;
>>>>    	}
>>>>    
>>>> -	sess->changed_format = 0;
>>>>    	sess->width = width;
>>>>    	sess->height = height;
>>>> -	sess->status = STATUS_NEEDS_RESUME;
>>>>    
>>>> -	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
>>>> -		width, height, dpb_size);
>>>> +	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
>>>> +		width, height, dpb_size, bitdepth);
>>>>    	v4l2_event_queue_fh(&sess->fh, &ev);
>>>>    }
>>>>    EXPORT_SYMBOL_GPL(amvdec_src_change);
>>>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
>>>> index 4bf3e61d081b..1a711679d26a 100644
>>>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.h
>>>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
>>>> @@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
>>>>    u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
>>>>    void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
>>>>    
>>>> -u32 amvdec_am21c_body_size(u32 width, u32 height);
>>>> -u32 amvdec_am21c_head_size(u32 width, u32 height);
>>>> -u32 amvdec_am21c_size(u32 width, u32 height);
>>>> +/* Helpers for the Amlogic compressed framebuffer format */
>>>> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>>>> +u32 amvdec_amfbc_head_size(u32 width, u32 height);
>>>> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>>>>    
>>>>    /**
>>>>     * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
>>>> @@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>>>>     * @width: picture width detected by the hardware
>>>>     * @height: picture height detected by the hardware
>>>>     * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
>>>> + * @bitdepth: Bit depth (usually 10 or 8) of the coded content
>>>>     */
>>>>    void amvdec_src_change(struct amvdec_session *sess, u32 width,
>>>> -		       u32 height, u32 dpb_size);
>>>> +		       u32 height, u32 dpb_size, u32 bitdepth);
>>>>    
>>>>    /**
>>>>     * amvdec_abort() - Abort the current decoding session
>>>
>>
> 

Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[neil.armstrong]

On 24/01/2023 17:26, Nicolas Dufresne wrote:
> Le mardi 24 janvier 2023 à 16:26 +0100, Neil Armstrong a écrit :
>> On 24/01/2023 16:21, Nicolas Dufresne wrote:
>>> Hi,
>>>
>>> Le mardi 24 janvier 2023 à 03:40 +0000, Christian Hewitt a écrit :
>>>> From: Benjamin Roszak <benjamin545@gmail.com>
>>>>
>>>> In order to support 10bit bitstream decoding, buffers and MMU
>>>> handling must be cleaned up to support either downscale output
>>>> from compressed 10bit decoding to uncompressed 8bit NV12 output
>>>> or to compressed 10bit proprietary encoded frame format.
>>>
>>> I understand this is step forward, and agree with the patches in general, though
>>> I'd like to know if we can expect 10bit secondary buffers in the future ? Or is
>>> the AMFBC that only 10bit format supported ? Should be expect the 10bit format
>>> definition to be added later ?
>>
>> The support exist, but it stopped when nobody aggreed on how to handle the different
>> layouts generated by the decoder.
>>
>> There's at least 4 possible layouts vs how we represent then in DRM :
>> - GX 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
>> - GX 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
>> - G12 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,AMLOGIC_FBC_OPTION_MEM_SAVING)
>> - G12 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC()AMLOGIC_FBC_LAYOUT_SCATTER, AMLOGIC_FBC_OPTION_MEM_SAVING)
>>
>> And probably more depending on new SoCs and new codecs.
> 
> Thanks, I didn't know. I think V4L2 strategy here would be to pick and expose
> just the minimum to make the mainline driver viable for 10bit decoding (unless
> again you have a secondary format like P010 available). This would suite better
> your users then just waiting for the perfect system to be in place.
> 
> p.s AMLOGIC_FBC_OPTION_MEM_SAVING is unlikely a layout from its name. FBC is
> generally loss-less for correctness, but loss-less compression always have a
> worse case scenerio bigger then the original, so we still need to reserve big
> chunk of memory. For memory limited device, ARM came up with lossy compressor,
> that guaranty a certain compression ratio. This name sounds like a similar
> feature to me.

Ok it's not that simple, seems I need to do a recap of the situation.

The HW decoder is a firmware running on top of a set of propriatery (or perhaps
bought IPS, but hidden behind the firmware) HW.

There's 2 generations:
- the old generation supports only a single decoding at a time, and implements the
"old" codecs (MPEG-1/2, H264, ...)
- the new is build around the "HEVC" core to decode multiple streams with support
of loadable context, and supports H.264, HEVC and VP9 (and VC-1 on new SoCs).

I'll cover only the new core.

The new core supports decoding 8bit and 10bit streams (except for H264), but the
decoder only works on "compressed framebuffers", which is similar to the ARM one
or any other SoC vendor does internally in fact.

But the firmware supports copying the output frames in a non-compressed NV12 double
plane buffers (buffers can't be single, we need to provide 2 buffers with a specific
aligment), but we can also get the compresse buffers and feed them to the display unit.

But between generations, the compressed buffers layout & options generated by the
decoder firmware are different, but on the Display side the IP & the possible options
are the same.

So we *need* to know ther bpp and the compression layout + options on the display
side, and we can't use the SoC name for that, especially from ffmpeg or gstreamer.

But we already upstreamed the DRM modifier a few years ago, so this is done.

So now we need a way from V4L2 to get thoses informations from the /dev/video endpoint to
correctly set the fourcc + modifier for display.

We hoped we could use the same modifier as DRM, but it seems this is now out of scope.

Neil

> 
> Nicolas
> 
>>
>> Neil
>>
>>>
>>>>
>>>> For that, "am21c" name is moved to "amfbc" to reflect the upstream
>>>> Amlogic Compressed framebuffer modifier naming.
>>>>
>>>> Compressed frame buffers allocation is also cleaned up so it
>>>> can be shared with the HEVC decoder implementation.
>>>>
>>>> Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
>>>> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
>>>> ---
>>>>    drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
>>>>    .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
>>>>    .../media/meson/vdec/codec_hevc_common.h      |   3 +-
>>>>    drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
>>>>    drivers/staging/media/meson/vdec/esparser.c   |   1 +
>>>>    drivers/staging/media/meson/vdec/vdec.h       |   1 +
>>>>    .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
>>>>    .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
>>>>    8 files changed, 161 insertions(+), 97 deletions(-)
>>>>
>>>> diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
>>>> index c61128fc4bb9..d53c9a464bde 100644
>>>> --- a/drivers/staging/media/meson/vdec/codec_h264.c
>>>> +++ b/drivers/staging/media/meson/vdec/codec_h264.c
>>>> @@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
>>>>    		frame_width, frame_height, crop_right, crop_bottom);
>>>>    
>>>>    	codec_h264_set_par(sess);
>>>> -	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
>>>> +	amvdec_src_change(sess, frame_width, frame_height,
>>>> +			  h264->max_refs + 5, 8);
>>>>    }
>>>>    
>>>>    /*
>>>> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
>>>> index 0315cc0911cd..1c74b4837dcb 100644
>>>> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
>>>> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
>>>> @@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
>>>>    void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>>>>    {
>>>>    	struct amvdec_core *core = sess->core;
>>>> -	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
>>>> -	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
>>>> +	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
>>>> +					 sess->pixfmt_cap, is_10bit);
>>>> +	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
>>>> +					       is_10bit, use_mmu);
>>>> +	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
>>>>    
>>>>    	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
>>>>    		/* Enable 2-plane reference read mode */
>>>> @@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>>>>    		return;
>>>>    	}
>>>>    
>>>> +	/* enable mem saving mode for 8-bit */
>>>> +	if (!is_10bit)
>>>> +		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
>>>> +	else
>>>> +		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
>>>> +
>>>>    	if (codec_hevc_use_mmu(core->platform->revision,
>>>>    			       sess->pixfmt_cap, is_10bit))
>>>>    		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
>>>> +	else if (!is_10bit)
>>>> +		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
>>>>    	else
>>>>    		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
>>>>    
>>>> @@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
>>>>    
>>>>    		idx = vb->index;
>>>>    
>>>> -		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
>>>> +		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
>>>>    			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>>>>    		else
>>>>    			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
>>>> @@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>>>    {
>>>>    	struct amvdec_core *core = sess->core;
>>>>    	struct v4l2_m2m_buffer *buf;
>>>> -	u32 revision = core->platform->revision;
>>>>    	u32 pixfmt_cap = sess->pixfmt_cap;
>>>> +	const u32 revision = core->platform->revision;
>>>>    	int i;
>>>>    
>>>>    	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
>>>> @@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>>>    		dma_addr_t buf_uv_paddr = 0;
>>>>    		u32 idx = vb->index;
>>>>    
>>>> -		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
>>>> -			buf_y_paddr = comm->mmu_header_paddr[idx];
>>>> -		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
>>>> -			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>>>> -		else
>>>> +		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
>>>> +			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
>>>> +				buf_y_paddr = comm->mmu_header_paddr[idx];
>>>> +			else
>>>> +				buf_y_paddr = comm->fbc_buffer_paddr[idx];
>>>> +		} else {
>>>>    			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
>>>> +		}
>>>>    
>>>>    		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
>>>>    				 buf_y_paddr >> 5);
>>>> @@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>>>    		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
>>>>    }
>>>>    
>>>> -void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>>>> +void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>>>    				 struct codec_hevc_common *comm)
>>>>    {
>>>>    	struct device *dev = sess->core->dev;
>>>> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>>>>    	int i;
>>>>    
>>>>    	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
>>>> -		if (comm->fbc_buffer_vaddr[i]) {
>>>> -			dma_free_coherent(dev, am21_size,
>>>> -					  comm->fbc_buffer_vaddr[i],
>>>> -					  comm->fbc_buffer_paddr[i]);
>>>> -			comm->fbc_buffer_vaddr[i] = NULL;
>>>> +		if (comm->mmu_header_vaddr[i]) {
>>>> +			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>>>> +					  comm->mmu_header_vaddr[i],
>>>> +					  comm->mmu_header_paddr[i]);
>>>> +			comm->mmu_header_vaddr[i] = NULL;
>>>>    		}
>>>>    	}
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>>>> +EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>>>>    
>>>> -static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>>>> +static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>>>>    					struct codec_hevc_common *comm)
>>>>    {
>>>>    	struct device *dev = sess->core->dev;
>>>>    	struct v4l2_m2m_buffer *buf;
>>>> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>>>>    
>>>>    	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>>>>    		u32 idx = buf->vb.vb2_buf.index;
>>>>    		dma_addr_t paddr;
>>>> -		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
>>>> -						 GFP_KERNEL);
>>>> +		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>>>> +						 &paddr, GFP_KERNEL);
>>>>    		if (!vaddr) {
>>>> -			codec_hevc_free_fbc_buffers(sess, comm);
>>>> +			codec_hevc_free_mmu_headers(sess, comm);
>>>>    			return -ENOMEM;
>>>>    		}
>>>>    
>>>> -		comm->fbc_buffer_vaddr[idx] = vaddr;
>>>> -		comm->fbc_buffer_paddr[idx] = paddr;
>>>> +		comm->mmu_header_vaddr[idx] = vaddr;
>>>> +		comm->mmu_header_paddr[idx] = paddr;
>>>>    	}
>>>>    
>>>>    	return 0;
>>>>    }
>>>>    
>>>> -void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>>> +void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>>>>    				 struct codec_hevc_common *comm)
>>>>    {
>>>>    	struct device *dev = sess->core->dev;
>>>> +	u32 use_mmu;
>>>> +	u32 am21_size;
>>>>    	int i;
>>>>    
>>>> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
>>>> +				     sess->pixfmt_cap,
>>>> +				sess->bitdepth == 10 ? 1 : 0);
>>>> +
>>>> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
>>>> +				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
>>>> +
>>>>    	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
>>>> -		if (comm->mmu_header_vaddr[i]) {
>>>> -			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>>>> -					  comm->mmu_header_vaddr[i],
>>>> -					  comm->mmu_header_paddr[i]);
>>>> -			comm->mmu_header_vaddr[i] = NULL;
>>>> +		if (comm->fbc_buffer_vaddr[i]) {
>>>> +			dma_free_coherent(dev, am21_size,
>>>> +					  comm->fbc_buffer_vaddr[i],
>>>> +					  comm->fbc_buffer_paddr[i]);
>>>> +			comm->fbc_buffer_vaddr[i] = NULL;
>>>>    		}
>>>>    	}
>>>>    
>>>> @@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>>>    				  comm->mmu_map_paddr);
>>>>    		comm->mmu_map_vaddr = NULL;
>>>>    	}
>>>> +
>>>> +	codec_hevc_free_mmu_headers(sess, comm);
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>>>> +EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>>>>    
>>>> -static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>>>> +static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>>>>    					struct codec_hevc_common *comm)
>>>>    {
>>>>    	struct device *dev = sess->core->dev;
>>>>    	struct v4l2_m2m_buffer *buf;
>>>> +	u32 use_mmu;
>>>> +	u32 am21_size;
>>>> +	const u32 revision = sess->core->platform->revision;
>>>> +	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
>>>> +	int ret;
>>>>    
>>>> -	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
>>>> -						 &comm->mmu_map_paddr,
>>>> -						 GFP_KERNEL);
>>>> -	if (!comm->mmu_map_vaddr)
>>>> -		return -ENOMEM;
>>>> +	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
>>>> +				     is_10bit);
>>>> +
>>>> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
>>>> +				      is_10bit, use_mmu);
>>>>    
>>>>    	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>>>>    		u32 idx = buf->vb.vb2_buf.index;
>>>>    		dma_addr_t paddr;
>>>> -		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>>>> -						 &paddr, GFP_KERNEL);
>>>> +
>>>> +		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
>>>> +						 GFP_KERNEL);
>>>>    		if (!vaddr) {
>>>> -			codec_hevc_free_mmu_headers(sess, comm);
>>>> +			codec_hevc_free_fbc_buffers(sess, comm);
>>>>    			return -ENOMEM;
>>>>    		}
>>>>    
>>>> -		comm->mmu_header_vaddr[idx] = vaddr;
>>>> -		comm->mmu_header_paddr[idx] = paddr;
>>>> +		comm->fbc_buffer_vaddr[idx] = vaddr;
>>>> +		comm->fbc_buffer_paddr[idx] = paddr;
>>>> +	}
>>>> +
>>>> +	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
>>>> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>>>> +		ret = codec_hevc_alloc_mmu_headers(sess, comm);
>>>> +		if (ret) {
>>>> +			codec_hevc_free_fbc_buffers(sess, comm);
>>>> +			return ret;
>>>> +		}
>>>>    	}
>>>>    
>>>>    	return 0;
>>>> @@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>>>>    			     int is_10bit)
>>>>    {
>>>>    	struct amvdec_core *core = sess->core;
>>>> +	struct device *dev = core->dev;
>>>>    	int ret;
>>>>    
>>>> -	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>>>> -		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
>>>> -		if (ret)
>>>> -			return ret;
>>>> +	if (codec_hevc_use_mmu(core->platform->revision,
>>>> +			       sess->pixfmt_cap, is_10bit)) {
>>>> +		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
>>>> +							 &comm->mmu_map_paddr,
>>>> +							 GFP_KERNEL);
>>>> +		if (!comm->mmu_map_vaddr)
>>>> +			return -ENOMEM;
>>>>    	}
>>>>    
>>>>    	if (codec_hevc_use_mmu(core->platform->revision,
>>>> -			       sess->pixfmt_cap, is_10bit)) {
>>>> -		ret = codec_hevc_alloc_mmu_headers(sess, comm);
>>>> -		if (ret) {
>>>> -			codec_hevc_free_fbc_buffers(sess, comm);
>>>> +			       sess->pixfmt_cap, is_10bit) ||
>>>> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>>>> +		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
>>>> +		if (ret)
>>>>    			return ret;
>>>> -		}
>>>>    	}
>>>>    
>>>>    	if (core->platform->revision == VDEC_REVISION_GXBB)
>>>> @@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
>>>>    
>>>>    void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>>>>    			     struct codec_hevc_common *comm,
>>>> -			     struct vb2_buffer *vb)
>>>> +			     struct vb2_buffer *vb,
>>>> +			     u32 is_10bit)
>>>>    {
>>>> -	u32 size = amvdec_am21c_size(sess->width, sess->height);
>>>> -	u32 nb_pages = size / PAGE_SIZE;
>>>> +	u32 use_mmu;
>>>> +	u32 size;
>>>> +	u32 nb_pages;
>>>>    	u32 *mmu_map = comm->mmu_map_vaddr;
>>>>    	u32 first_page;
>>>>    	u32 i;
>>>>    
>>>> -	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
>>>> -		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>>>> -	else
>>>> -		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
>>>> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
>>>> +				     sess->pixfmt_cap, is_10bit);
>>>> +
>>>> +	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
>>>> +				 use_mmu);
>>>>    
>>>> +	nb_pages = size / PAGE_SIZE;
>>>> +	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>>>>    	for (i = 0; i < nb_pages; ++i)
>>>>    		mmu_map[i] = first_page + i;
>>>>    }
>>>> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
>>>> index cf072b8a9da2..13f9f1d90a94 100644
>>>> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
>>>> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
>>>> @@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>>>>    
>>>>    void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>>>>    			     struct codec_hevc_common *comm,
>>>> -			     struct vb2_buffer *vb);
>>>> +			     struct vb2_buffer *vb,
>>>> +			     u32 is_10bit);
>>>>    
>>>>    #endif
>>>> diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
>>>> index 394df5761556..8e3bbf0db4b3 100644
>>>> --- a/drivers/staging/media/meson/vdec/codec_vp9.c
>>>> +++ b/drivers/staging/media/meson/vdec/codec_vp9.c
>>>> @@ -458,12 +458,6 @@ struct codec_vp9 {
>>>>    	struct list_head ref_frames_list;
>>>>    	u32 frames_num;
>>>>    
>>>> -	/* In case of downsampling (decoding with FBC but outputting in NV12M),
>>>> -	 * we need to allocate additional buffers for FBC.
>>>> -	 */
>>>> -	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
>>>> -	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
>>>> -
>>>>    	int ref_frame_map[REF_FRAMES];
>>>>    	int next_ref_frame_map[REF_FRAMES];
>>>>    	struct vp9_frame *frame_refs[REFS_PER_FRAME];
>>>> @@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>>>>    		buf_y_paddr =
>>>>    		       vb2_dma_contig_plane_dma_addr(vb, 0);
>>>>    
>>>> -	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
>>>> -		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
>>>> -		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
>>>> +	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
>>>>    		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
>>>> -	}
>>>>    
>>>>    	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
>>>>    		buf_y_paddr =
>>>> @@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>>>>    
>>>>    	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>>>>    			       vp9->is_10bit)) {
>>>> -		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
>>>> -				 vp9->common.mmu_header_paddr[vb->index]);
>>>> +		dma_addr_t header_adr;
>>>> +
>>>> +		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
>>>> +			header_adr = vp9->common.mmu_header_paddr[vb->index];
>>>> +		else
>>>> +			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
>>>> +		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
>>>>    		/* use HEVC_CM_HEADER_START_ADDR */
>>>>    		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
>>>>    	}
>>>> @@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>>>>    {
>>>>    	struct amvdec_core *core = sess->core;
>>>>    	u32 scale = 0;
>>>> +	u32 use_mmu;
>>>>    	u32 sz;
>>>>    	int i;
>>>>    
>>>> +	use_mmu = codec_hevc_use_mmu(core->platform->revision,
>>>> +				     sess->pixfmt_cap, vp9->is_10bit);
>>>> +
>>>>    	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
>>>>    	codec_vp9_set_refs(sess, vp9);
>>>>    	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
>>>> @@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>>>>    		    vp9->frame_refs[i]->height != vp9->height)
>>>>    			scale = 1;
>>>>    
>>>> -		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
>>>> -					    vp9->frame_refs[i]->height);
>>>> +		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
>>>> +					    vp9->frame_refs[i]->height,
>>>> +					    vp9->is_10bit, use_mmu);
>>>>    
>>>>    		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
>>>>    				 vp9->frame_refs[i]->width);
>>>> @@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
>>>>    	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>>>>    			       vp9->is_10bit))
>>>>    		codec_hevc_fill_mmu_map(sess, &vp9->common,
>>>> -					&vp9->cur_frame->vbuf->vb2_buf);
>>>> +					&vp9->cur_frame->vbuf->vb2_buf,
>>>> +					vp9->is_10bit);
>>>>    
>>>>    	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
>>>>    
>>>> @@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
>>>>    
>>>>    	codec_vp9_fetch_rpm(sess);
>>>>    	if (codec_vp9_process_rpm(vp9)) {
>>>> -		amvdec_src_change(sess, vp9->width, vp9->height, 16);
>>>> +		amvdec_src_change(sess, vp9->width, vp9->height, 16,
>>>> +				  vp9->is_10bit ? 10 : 8);
>>>>    
>>>>    		/* No frame is actually processed */
>>>>    		vp9->cur_frame = NULL;
>>>> diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
>>>> index 1904d58875ad..3cd29ab4f979 100644
>>>> --- a/drivers/staging/media/meson/vdec/esparser.c
>>>> +++ b/drivers/staging/media/meson/vdec/esparser.c
>>>> @@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
>>>>    		if (esparser_vififo_get_free_space(sess) < payload_size ||
>>>>    		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
>>>>    			return -EAGAIN;
>>>> +
>>>>    	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
>>>>    		return -EAGAIN;
>>>>    	}
>>>> diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
>>>> index 0906b8fb5cc6..a48170fe4cff 100644
>>>> --- a/drivers/staging/media/meson/vdec/vdec.h
>>>> +++ b/drivers/staging/media/meson/vdec/vdec.h
>>>> @@ -244,6 +244,7 @@ struct amvdec_session {
>>>>    	u32 width;
>>>>    	u32 height;
>>>>    	u32 colorspace;
>>>> +	u32 bitdepth;
>>>>    	u8 ycbcr_enc;
>>>>    	u8 quantization;
>>>>    	u8 xfer_func;
>>>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
>>>> index 7d2a75653250..fef76142f0c5 100644
>>>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.c
>>>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
>>>> @@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
>>>>    }
>>>>    EXPORT_SYMBOL_GPL(amvdec_write_parser);
>>>>    
>>>> -/* 4 KiB per 64x32 block */
>>>> -u32 amvdec_am21c_body_size(u32 width, u32 height)
>>>> +/* AMFBC body is made out of 64x32 blocks with varying block size */
>>>> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>>>>    {
>>>>    	u32 width_64 = ALIGN(width, 64) / 64;
>>>>    	u32 height_32 = ALIGN(height, 32) / 32;
>>>> +	u32 blk_size = 4096;
>>>>    
>>>> -	return SZ_4K * width_64 * height_32;
>>>> +	if (!is_10bit) {
>>>> +		if (use_mmu)
>>>> +			blk_size = 3200;
>>>> +		else
>>>> +			blk_size = 3072;
>>>> +	}
>>>> +
>>>> +	return blk_size * width_64 * height_32;
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
>>>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
>>>>    
>>>>    /* 32 bytes per 128x64 block */
>>>> -u32 amvdec_am21c_head_size(u32 width, u32 height)
>>>> +u32 amvdec_amfbc_head_size(u32 width, u32 height)
>>>>    {
>>>>    	u32 width_128 = ALIGN(width, 128) / 128;
>>>>    	u32 height_64 = ALIGN(height, 64) / 64;
>>>>    
>>>>    	return 32 * width_128 * height_64;
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
>>>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
>>>>    
>>>> -u32 amvdec_am21c_size(u32 width, u32 height)
>>>> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>>>>    {
>>>> -	return ALIGN(amvdec_am21c_body_size(width, height) +
>>>> -		     amvdec_am21c_head_size(width, height), SZ_64K);
>>>> +	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
>>>> +		     amvdec_amfbc_head_size(width, height), SZ_64K);
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(amvdec_am21c_size);
>>>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
>>>>    
>>>>    static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
>>>>    {
>>>> @@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>>>>    EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
>>>>    
>>>>    void amvdec_src_change(struct amvdec_session *sess, u32 width,
>>>> -		       u32 height, u32 dpb_size)
>>>> +		       u32 height, u32 dpb_size, u32 bitdepth)
>>>>    {
>>>>    	static const struct v4l2_event ev = {
>>>>    		.type = V4L2_EVENT_SOURCE_CHANGE,
>>>> @@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
>>>>    
>>>>    	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
>>>>    
>>>> +	sess->bitdepth = bitdepth;
>>>> +
>>>>    	/*
>>>>    	 * Check if the capture queue is already configured well for our
>>>> -	 * usecase. If so, keep decoding with it and do not send the event
>>>> +	 * usecase. If so, keep decoding with it.
>>>>    	 */
>>>>    	if (sess->streamon_cap &&
>>>>    	    sess->width == width &&
>>>>    	    sess->height == height &&
>>>>    	    dpb_size <= sess->num_dst_bufs) {
>>>>    		sess->fmt_out->codec_ops->resume(sess);
>>>> -		return;
>>>> +	} else {
>>>> +		sess->status = STATUS_NEEDS_RESUME;
>>>> +		sess->changed_format = 0;
>>>>    	}
>>>>    
>>>> -	sess->changed_format = 0;
>>>>    	sess->width = width;
>>>>    	sess->height = height;
>>>> -	sess->status = STATUS_NEEDS_RESUME;
>>>>    
>>>> -	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
>>>> -		width, height, dpb_size);
>>>> +	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
>>>> +		width, height, dpb_size, bitdepth);
>>>>    	v4l2_event_queue_fh(&sess->fh, &ev);
>>>>    }
>>>>    EXPORT_SYMBOL_GPL(amvdec_src_change);
>>>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
>>>> index 4bf3e61d081b..1a711679d26a 100644
>>>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.h
>>>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
>>>> @@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
>>>>    u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
>>>>    void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
>>>>    
>>>> -u32 amvdec_am21c_body_size(u32 width, u32 height);
>>>> -u32 amvdec_am21c_head_size(u32 width, u32 height);
>>>> -u32 amvdec_am21c_size(u32 width, u32 height);
>>>> +/* Helpers for the Amlogic compressed framebuffer format */
>>>> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>>>> +u32 amvdec_amfbc_head_size(u32 width, u32 height);
>>>> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>>>>    
>>>>    /**
>>>>     * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
>>>> @@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>>>>     * @width: picture width detected by the hardware
>>>>     * @height: picture height detected by the hardware
>>>>     * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
>>>> + * @bitdepth: Bit depth (usually 10 or 8) of the coded content
>>>>     */
>>>>    void amvdec_src_change(struct amvdec_session *sess, u32 width,
>>>> -		       u32 height, u32 dpb_size);
>>>> +		       u32 height, u32 dpb_size, u32 bitdepth);
>>>>    
>>>>    /**
>>>>     * amvdec_abort() - Abort the current decoding session
>>>
>>
> 


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Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[neil.armstrong]

On 24/01/2023 17:26, Nicolas Dufresne wrote:
> Le mardi 24 janvier 2023 à 16:26 +0100, Neil Armstrong a écrit :
>> On 24/01/2023 16:21, Nicolas Dufresne wrote:
>>> Hi,
>>>
>>> Le mardi 24 janvier 2023 à 03:40 +0000, Christian Hewitt a écrit :
>>>> From: Benjamin Roszak <benjamin545@gmail.com>
>>>>
>>>> In order to support 10bit bitstream decoding, buffers and MMU
>>>> handling must be cleaned up to support either downscale output
>>>> from compressed 10bit decoding to uncompressed 8bit NV12 output
>>>> or to compressed 10bit proprietary encoded frame format.
>>>
>>> I understand this is step forward, and agree with the patches in general, though
>>> I'd like to know if we can expect 10bit secondary buffers in the future ? Or is
>>> the AMFBC that only 10bit format supported ? Should be expect the 10bit format
>>> definition to be added later ?
>>
>> The support exist, but it stopped when nobody aggreed on how to handle the different
>> layouts generated by the decoder.
>>
>> There's at least 4 possible layouts vs how we represent then in DRM :
>> - GX 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
>> - GX 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0)
>> - G12 8bit: DRM_FORMAT_YUV420_8BIT | DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,AMLOGIC_FBC_OPTION_MEM_SAVING)
>> - G12 10bit: DRM_FORMAT_YUV420_10BIT | DRM_FORMAT_MOD_AMLOGIC_FBC()AMLOGIC_FBC_LAYOUT_SCATTER, AMLOGIC_FBC_OPTION_MEM_SAVING)
>>
>> And probably more depending on new SoCs and new codecs.
> 
> Thanks, I didn't know. I think V4L2 strategy here would be to pick and expose
> just the minimum to make the mainline driver viable for 10bit decoding (unless
> again you have a secondary format like P010 available). This would suite better
> your users then just waiting for the perfect system to be in place.
> 
> p.s AMLOGIC_FBC_OPTION_MEM_SAVING is unlikely a layout from its name. FBC is
> generally loss-less for correctness, but loss-less compression always have a
> worse case scenerio bigger then the original, so we still need to reserve big
> chunk of memory. For memory limited device, ARM came up with lossy compressor,
> that guaranty a certain compression ratio. This name sounds like a similar
> feature to me.

Ok it's not that simple, seems I need to do a recap of the situation.

The HW decoder is a firmware running on top of a set of propriatery (or perhaps
bought IPS, but hidden behind the firmware) HW.

There's 2 generations:
- the old generation supports only a single decoding at a time, and implements the
"old" codecs (MPEG-1/2, H264, ...)
- the new is build around the "HEVC" core to decode multiple streams with support
of loadable context, and supports H.264, HEVC and VP9 (and VC-1 on new SoCs).

I'll cover only the new core.

The new core supports decoding 8bit and 10bit streams (except for H264), but the
decoder only works on "compressed framebuffers", which is similar to the ARM one
or any other SoC vendor does internally in fact.

But the firmware supports copying the output frames in a non-compressed NV12 double
plane buffers (buffers can't be single, we need to provide 2 buffers with a specific
aligment), but we can also get the compresse buffers and feed them to the display unit.

But between generations, the compressed buffers layout & options generated by the
decoder firmware are different, but on the Display side the IP & the possible options
are the same.

So we *need* to know ther bpp and the compression layout + options on the display
side, and we can't use the SoC name for that, especially from ffmpeg or gstreamer.

But we already upstreamed the DRM modifier a few years ago, so this is done.

So now we need a way from V4L2 to get thoses informations from the /dev/video endpoint to
correctly set the fourcc + modifier for display.

We hoped we could use the same modifier as DRM, but it seems this is now out of scope.

Neil

> 
> Nicolas
> 
>>
>> Neil
>>
>>>
>>>>
>>>> For that, "am21c" name is moved to "amfbc" to reflect the upstream
>>>> Amlogic Compressed framebuffer modifier naming.
>>>>
>>>> Compressed frame buffers allocation is also cleaned up so it
>>>> can be shared with the HEVC decoder implementation.
>>>>
>>>> Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
>>>> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
>>>> ---
>>>>    drivers/staging/media/meson/vdec/codec_h264.c |   3 +-
>>>>    .../media/meson/vdec/codec_hevc_common.c      | 161 +++++++++++-------
>>>>    .../media/meson/vdec/codec_hevc_common.h      |   3 +-
>>>>    drivers/staging/media/meson/vdec/codec_vp9.c  |  35 ++--
>>>>    drivers/staging/media/meson/vdec/esparser.c   |   1 +
>>>>    drivers/staging/media/meson/vdec/vdec.h       |   1 +
>>>>    .../staging/media/meson/vdec/vdec_helpers.c   |  44 +++--
>>>>    .../staging/media/meson/vdec/vdec_helpers.h   |  10 +-
>>>>    8 files changed, 161 insertions(+), 97 deletions(-)
>>>>
>>>> diff --git a/drivers/staging/media/meson/vdec/codec_h264.c b/drivers/staging/media/meson/vdec/codec_h264.c
>>>> index c61128fc4bb9..d53c9a464bde 100644
>>>> --- a/drivers/staging/media/meson/vdec/codec_h264.c
>>>> +++ b/drivers/staging/media/meson/vdec/codec_h264.c
>>>> @@ -353,7 +353,8 @@ static void codec_h264_src_change(struct amvdec_session *sess)
>>>>    		frame_width, frame_height, crop_right, crop_bottom);
>>>>    
>>>>    	codec_h264_set_par(sess);
>>>> -	amvdec_src_change(sess, frame_width, frame_height, h264->max_refs + 5);
>>>> +	amvdec_src_change(sess, frame_width, frame_height,
>>>> +			  h264->max_refs + 5, 8);
>>>>    }
>>>>    
>>>>    /*
>>>> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.c b/drivers/staging/media/meson/vdec/codec_hevc_common.c
>>>> index 0315cc0911cd..1c74b4837dcb 100644
>>>> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.c
>>>> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.c
>>>> @@ -30,8 +30,11 @@ const u16 vdec_hevc_parser_cmd[] = {
>>>>    void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>>>>    {
>>>>    	struct amvdec_core *core = sess->core;
>>>> -	u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
>>>> -	u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
>>>> +	u32 use_mmu = codec_hevc_use_mmu(core->platform->revision,
>>>> +					 sess->pixfmt_cap, is_10bit);
>>>> +	u32 body_size = amvdec_amfbc_body_size(sess->width, sess->height,
>>>> +					       is_10bit, use_mmu);
>>>> +	u32 head_size = amvdec_amfbc_head_size(sess->width, sess->height);
>>>>    
>>>>    	if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
>>>>    		/* Enable 2-plane reference read mode */
>>>> @@ -39,9 +42,17 @@ void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
>>>>    		return;
>>>>    	}
>>>>    
>>>> +	/* enable mem saving mode for 8-bit */
>>>> +	if (!is_10bit)
>>>> +		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
>>>> +	else
>>>> +		amvdec_clear_dos_bits(core, HEVC_SAO_CTRL5, BIT(9));
>>>> +
>>>>    	if (codec_hevc_use_mmu(core->platform->revision,
>>>>    			       sess->pixfmt_cap, is_10bit))
>>>>    		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
>>>> +	else if (!is_10bit)
>>>> +		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(3));
>>>>    	else
>>>>    		amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
>>>>    
>>>> @@ -73,7 +84,7 @@ static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
>>>>    
>>>>    		idx = vb->index;
>>>>    
>>>> -		if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
>>>> +		if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
>>>>    			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>>>>    		else
>>>>    			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
>>>> @@ -114,8 +125,8 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>>>    {
>>>>    	struct amvdec_core *core = sess->core;
>>>>    	struct v4l2_m2m_buffer *buf;
>>>> -	u32 revision = core->platform->revision;
>>>>    	u32 pixfmt_cap = sess->pixfmt_cap;
>>>> +	const u32 revision = core->platform->revision;
>>>>    	int i;
>>>>    
>>>>    	amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
>>>> @@ -127,12 +138,14 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>>>    		dma_addr_t buf_uv_paddr = 0;
>>>>    		u32 idx = vb->index;
>>>>    
>>>> -		if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
>>>> -			buf_y_paddr = comm->mmu_header_paddr[idx];
>>>> -		else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
>>>> -			buf_y_paddr = comm->fbc_buffer_paddr[idx];
>>>> -		else
>>>> +		if (codec_hevc_use_downsample(pixfmt_cap, is_10bit)) {
>>>> +			if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
>>>> +				buf_y_paddr = comm->mmu_header_paddr[idx];
>>>> +			else
>>>> +				buf_y_paddr = comm->fbc_buffer_paddr[idx];
>>>> +		} else {
>>>>    			buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
>>>> +		}
>>>>    
>>>>    		amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
>>>>    				 buf_y_paddr >> 5);
>>>> @@ -150,60 +163,67 @@ static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
>>>>    		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
>>>>    }
>>>>    
>>>> -void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>>>> +void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>>>    				 struct codec_hevc_common *comm)
>>>>    {
>>>>    	struct device *dev = sess->core->dev;
>>>> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>>>>    	int i;
>>>>    
>>>>    	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
>>>> -		if (comm->fbc_buffer_vaddr[i]) {
>>>> -			dma_free_coherent(dev, am21_size,
>>>> -					  comm->fbc_buffer_vaddr[i],
>>>> -					  comm->fbc_buffer_paddr[i]);
>>>> -			comm->fbc_buffer_vaddr[i] = NULL;
>>>> +		if (comm->mmu_header_vaddr[i]) {
>>>> +			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>>>> +					  comm->mmu_header_vaddr[i],
>>>> +					  comm->mmu_header_paddr[i]);
>>>> +			comm->mmu_header_vaddr[i] = NULL;
>>>>    		}
>>>>    	}
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>>>> +EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>>>>    
>>>> -static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>>>> +static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>>>>    					struct codec_hevc_common *comm)
>>>>    {
>>>>    	struct device *dev = sess->core->dev;
>>>>    	struct v4l2_m2m_buffer *buf;
>>>> -	u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
>>>>    
>>>>    	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>>>>    		u32 idx = buf->vb.vb2_buf.index;
>>>>    		dma_addr_t paddr;
>>>> -		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
>>>> -						 GFP_KERNEL);
>>>> +		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>>>> +						 &paddr, GFP_KERNEL);
>>>>    		if (!vaddr) {
>>>> -			codec_hevc_free_fbc_buffers(sess, comm);
>>>> +			codec_hevc_free_mmu_headers(sess, comm);
>>>>    			return -ENOMEM;
>>>>    		}
>>>>    
>>>> -		comm->fbc_buffer_vaddr[idx] = vaddr;
>>>> -		comm->fbc_buffer_paddr[idx] = paddr;
>>>> +		comm->mmu_header_vaddr[idx] = vaddr;
>>>> +		comm->mmu_header_paddr[idx] = paddr;
>>>>    	}
>>>>    
>>>>    	return 0;
>>>>    }
>>>>    
>>>> -void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>>> +void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
>>>>    				 struct codec_hevc_common *comm)
>>>>    {
>>>>    	struct device *dev = sess->core->dev;
>>>> +	u32 use_mmu;
>>>> +	u32 am21_size;
>>>>    	int i;
>>>>    
>>>> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
>>>> +				     sess->pixfmt_cap,
>>>> +				sess->bitdepth == 10 ? 1 : 0);
>>>> +
>>>> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
>>>> +				      sess->bitdepth == 10 ? 1 : 0, use_mmu);
>>>> +
>>>>    	for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
>>>> -		if (comm->mmu_header_vaddr[i]) {
>>>> -			dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>>>> -					  comm->mmu_header_vaddr[i],
>>>> -					  comm->mmu_header_paddr[i]);
>>>> -			comm->mmu_header_vaddr[i] = NULL;
>>>> +		if (comm->fbc_buffer_vaddr[i]) {
>>>> +			dma_free_coherent(dev, am21_size,
>>>> +					  comm->fbc_buffer_vaddr[i],
>>>> +					  comm->fbc_buffer_paddr[i]);
>>>> +			comm->fbc_buffer_vaddr[i] = NULL;
>>>>    		}
>>>>    	}
>>>>    
>>>> @@ -213,33 +233,50 @@ void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
>>>>    				  comm->mmu_map_paddr);
>>>>    		comm->mmu_map_vaddr = NULL;
>>>>    	}
>>>> +
>>>> +	codec_hevc_free_mmu_headers(sess, comm);
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
>>>> +EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
>>>>    
>>>> -static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
>>>> +static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
>>>>    					struct codec_hevc_common *comm)
>>>>    {
>>>>    	struct device *dev = sess->core->dev;
>>>>    	struct v4l2_m2m_buffer *buf;
>>>> +	u32 use_mmu;
>>>> +	u32 am21_size;
>>>> +	const u32 revision = sess->core->platform->revision;
>>>> +	const u32 is_10bit = sess->bitdepth == 10 ? 1 : 0;
>>>> +	int ret;
>>>>    
>>>> -	comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
>>>> -						 &comm->mmu_map_paddr,
>>>> -						 GFP_KERNEL);
>>>> -	if (!comm->mmu_map_vaddr)
>>>> -		return -ENOMEM;
>>>> +	use_mmu = codec_hevc_use_mmu(revision, sess->pixfmt_cap,
>>>> +				     is_10bit);
>>>> +
>>>> +	am21_size = amvdec_amfbc_size(sess->width, sess->height,
>>>> +				      is_10bit, use_mmu);
>>>>    
>>>>    	v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
>>>>    		u32 idx = buf->vb.vb2_buf.index;
>>>>    		dma_addr_t paddr;
>>>> -		void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
>>>> -						 &paddr, GFP_KERNEL);
>>>> +
>>>> +		void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
>>>> +						 GFP_KERNEL);
>>>>    		if (!vaddr) {
>>>> -			codec_hevc_free_mmu_headers(sess, comm);
>>>> +			codec_hevc_free_fbc_buffers(sess, comm);
>>>>    			return -ENOMEM;
>>>>    		}
>>>>    
>>>> -		comm->mmu_header_vaddr[idx] = vaddr;
>>>> -		comm->mmu_header_paddr[idx] = paddr;
>>>> +		comm->fbc_buffer_vaddr[idx] = vaddr;
>>>> +		comm->fbc_buffer_paddr[idx] = paddr;
>>>> +	}
>>>> +
>>>> +	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, is_10bit) &&
>>>> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>>>> +		ret = codec_hevc_alloc_mmu_headers(sess, comm);
>>>> +		if (ret) {
>>>> +			codec_hevc_free_fbc_buffers(sess, comm);
>>>> +			return ret;
>>>> +		}
>>>>    	}
>>>>    
>>>>    	return 0;
>>>> @@ -250,21 +287,24 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>>>>    			     int is_10bit)
>>>>    {
>>>>    	struct amvdec_core *core = sess->core;
>>>> +	struct device *dev = core->dev;
>>>>    	int ret;
>>>>    
>>>> -	if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>>>> -		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
>>>> -		if (ret)
>>>> -			return ret;
>>>> +	if (codec_hevc_use_mmu(core->platform->revision,
>>>> +			       sess->pixfmt_cap, is_10bit)) {
>>>> +		comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
>>>> +							 &comm->mmu_map_paddr,
>>>> +							 GFP_KERNEL);
>>>> +		if (!comm->mmu_map_vaddr)
>>>> +			return -ENOMEM;
>>>>    	}
>>>>    
>>>>    	if (codec_hevc_use_mmu(core->platform->revision,
>>>> -			       sess->pixfmt_cap, is_10bit)) {
>>>> -		ret = codec_hevc_alloc_mmu_headers(sess, comm);
>>>> -		if (ret) {
>>>> -			codec_hevc_free_fbc_buffers(sess, comm);
>>>> +			       sess->pixfmt_cap, is_10bit) ||
>>>> +	    codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
>>>> +		ret = codec_hevc_alloc_fbc_buffers(sess, comm);
>>>> +		if (ret)
>>>>    			return ret;
>>>> -		}
>>>>    	}
>>>>    
>>>>    	if (core->platform->revision == VDEC_REVISION_GXBB)
>>>> @@ -278,19 +318,24 @@ EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
>>>>    
>>>>    void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>>>>    			     struct codec_hevc_common *comm,
>>>> -			     struct vb2_buffer *vb)
>>>> +			     struct vb2_buffer *vb,
>>>> +			     u32 is_10bit)
>>>>    {
>>>> -	u32 size = amvdec_am21c_size(sess->width, sess->height);
>>>> -	u32 nb_pages = size / PAGE_SIZE;
>>>> +	u32 use_mmu;
>>>> +	u32 size;
>>>> +	u32 nb_pages;
>>>>    	u32 *mmu_map = comm->mmu_map_vaddr;
>>>>    	u32 first_page;
>>>>    	u32 i;
>>>>    
>>>> -	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
>>>> -		first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>>>> -	else
>>>> -		first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
>>>> +	use_mmu = codec_hevc_use_mmu(sess->core->platform->revision,
>>>> +				     sess->pixfmt_cap, is_10bit);
>>>> +
>>>> +	size = amvdec_amfbc_size(sess->width, sess->height, is_10bit,
>>>> +				 use_mmu);
>>>>    
>>>> +	nb_pages = size / PAGE_SIZE;
>>>> +	first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
>>>>    	for (i = 0; i < nb_pages; ++i)
>>>>    		mmu_map[i] = first_page + i;
>>>>    }
>>>> diff --git a/drivers/staging/media/meson/vdec/codec_hevc_common.h b/drivers/staging/media/meson/vdec/codec_hevc_common.h
>>>> index cf072b8a9da2..13f9f1d90a94 100644
>>>> --- a/drivers/staging/media/meson/vdec/codec_hevc_common.h
>>>> +++ b/drivers/staging/media/meson/vdec/codec_hevc_common.h
>>>> @@ -64,6 +64,7 @@ int codec_hevc_setup_buffers(struct amvdec_session *sess,
>>>>    
>>>>    void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
>>>>    			     struct codec_hevc_common *comm,
>>>> -			     struct vb2_buffer *vb);
>>>> +			     struct vb2_buffer *vb,
>>>> +			     u32 is_10bit);
>>>>    
>>>>    #endif
>>>> diff --git a/drivers/staging/media/meson/vdec/codec_vp9.c b/drivers/staging/media/meson/vdec/codec_vp9.c
>>>> index 394df5761556..8e3bbf0db4b3 100644
>>>> --- a/drivers/staging/media/meson/vdec/codec_vp9.c
>>>> +++ b/drivers/staging/media/meson/vdec/codec_vp9.c
>>>> @@ -458,12 +458,6 @@ struct codec_vp9 {
>>>>    	struct list_head ref_frames_list;
>>>>    	u32 frames_num;
>>>>    
>>>> -	/* In case of downsampling (decoding with FBC but outputting in NV12M),
>>>> -	 * we need to allocate additional buffers for FBC.
>>>> -	 */
>>>> -	void      *fbc_buffer_vaddr[MAX_REF_PIC_NUM];
>>>> -	dma_addr_t fbc_buffer_paddr[MAX_REF_PIC_NUM];
>>>> -
>>>>    	int ref_frame_map[REF_FRAMES];
>>>>    	int next_ref_frame_map[REF_FRAMES];
>>>>    	struct vp9_frame *frame_refs[REFS_PER_FRAME];
>>>> @@ -901,11 +895,8 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>>>>    		buf_y_paddr =
>>>>    		       vb2_dma_contig_plane_dma_addr(vb, 0);
>>>>    
>>>> -	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit)) {
>>>> -		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
>>>> -		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
>>>> +	if (codec_hevc_use_fbc(sess->pixfmt_cap, vp9->is_10bit))
>>>>    		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
>>>> -	}
>>>>    
>>>>    	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
>>>>    		buf_y_paddr =
>>>> @@ -920,8 +911,13 @@ static void codec_vp9_set_sao(struct amvdec_session *sess,
>>>>    
>>>>    	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>>>>    			       vp9->is_10bit)) {
>>>> -		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
>>>> -				 vp9->common.mmu_header_paddr[vb->index]);
>>>> +		dma_addr_t header_adr;
>>>> +
>>>> +		if (codec_hevc_use_downsample(sess->pixfmt_cap, vp9->is_10bit))
>>>> +			header_adr = vp9->common.mmu_header_paddr[vb->index];
>>>> +		else
>>>> +			header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
>>>> +		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
>>>>    		/* use HEVC_CM_HEADER_START_ADDR */
>>>>    		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
>>>>    	}
>>>> @@ -1148,9 +1144,13 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>>>>    {
>>>>    	struct amvdec_core *core = sess->core;
>>>>    	u32 scale = 0;
>>>> +	u32 use_mmu;
>>>>    	u32 sz;
>>>>    	int i;
>>>>    
>>>> +	use_mmu = codec_hevc_use_mmu(core->platform->revision,
>>>> +				     sess->pixfmt_cap, vp9->is_10bit);
>>>> +
>>>>    	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
>>>>    	codec_vp9_set_refs(sess, vp9);
>>>>    	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
>>>> @@ -1166,8 +1166,9 @@ static void codec_vp9_set_mc(struct amvdec_session *sess,
>>>>    		    vp9->frame_refs[i]->height != vp9->height)
>>>>    			scale = 1;
>>>>    
>>>> -		sz = amvdec_am21c_body_size(vp9->frame_refs[i]->width,
>>>> -					    vp9->frame_refs[i]->height);
>>>> +		sz = amvdec_amfbc_body_size(vp9->frame_refs[i]->width,
>>>> +					    vp9->frame_refs[i]->height,
>>>> +					    vp9->is_10bit, use_mmu);
>>>>    
>>>>    		amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
>>>>    				 vp9->frame_refs[i]->width);
>>>> @@ -1283,7 +1284,8 @@ static void codec_vp9_process_frame(struct amvdec_session *sess)
>>>>    	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
>>>>    			       vp9->is_10bit))
>>>>    		codec_hevc_fill_mmu_map(sess, &vp9->common,
>>>> -					&vp9->cur_frame->vbuf->vb2_buf);
>>>> +					&vp9->cur_frame->vbuf->vb2_buf,
>>>> +					vp9->is_10bit);
>>>>    
>>>>    	intra_only = param->p.show_frame ? 0 : param->p.intra_only;
>>>>    
>>>> @@ -2130,7 +2132,8 @@ static irqreturn_t codec_vp9_threaded_isr(struct amvdec_session *sess)
>>>>    
>>>>    	codec_vp9_fetch_rpm(sess);
>>>>    	if (codec_vp9_process_rpm(vp9)) {
>>>> -		amvdec_src_change(sess, vp9->width, vp9->height, 16);
>>>> +		amvdec_src_change(sess, vp9->width, vp9->height, 16,
>>>> +				  vp9->is_10bit ? 10 : 8);
>>>>    
>>>>    		/* No frame is actually processed */
>>>>    		vp9->cur_frame = NULL;
>>>> diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
>>>> index 1904d58875ad..3cd29ab4f979 100644
>>>> --- a/drivers/staging/media/meson/vdec/esparser.c
>>>> +++ b/drivers/staging/media/meson/vdec/esparser.c
>>>> @@ -320,6 +320,7 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
>>>>    		if (esparser_vififo_get_free_space(sess) < payload_size ||
>>>>    		    atomic_read(&sess->esparser_queued_bufs) >= num_dst_bufs)
>>>>    			return -EAGAIN;
>>>> +
>>>>    	} else if (esparser_vififo_get_free_space(sess) < payload_size) {
>>>>    		return -EAGAIN;
>>>>    	}
>>>> diff --git a/drivers/staging/media/meson/vdec/vdec.h b/drivers/staging/media/meson/vdec/vdec.h
>>>> index 0906b8fb5cc6..a48170fe4cff 100644
>>>> --- a/drivers/staging/media/meson/vdec/vdec.h
>>>> +++ b/drivers/staging/media/meson/vdec/vdec.h
>>>> @@ -244,6 +244,7 @@ struct amvdec_session {
>>>>    	u32 width;
>>>>    	u32 height;
>>>>    	u32 colorspace;
>>>> +	u32 bitdepth;
>>>>    	u8 ycbcr_enc;
>>>>    	u8 quantization;
>>>>    	u8 xfer_func;
>>>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.c b/drivers/staging/media/meson/vdec/vdec_helpers.c
>>>> index 7d2a75653250..fef76142f0c5 100644
>>>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.c
>>>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.c
>>>> @@ -50,32 +50,40 @@ void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val)
>>>>    }
>>>>    EXPORT_SYMBOL_GPL(amvdec_write_parser);
>>>>    
>>>> -/* 4 KiB per 64x32 block */
>>>> -u32 amvdec_am21c_body_size(u32 width, u32 height)
>>>> +/* AMFBC body is made out of 64x32 blocks with varying block size */
>>>> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>>>>    {
>>>>    	u32 width_64 = ALIGN(width, 64) / 64;
>>>>    	u32 height_32 = ALIGN(height, 32) / 32;
>>>> +	u32 blk_size = 4096;
>>>>    
>>>> -	return SZ_4K * width_64 * height_32;
>>>> +	if (!is_10bit) {
>>>> +		if (use_mmu)
>>>> +			blk_size = 3200;
>>>> +		else
>>>> +			blk_size = 3072;
>>>> +	}
>>>> +
>>>> +	return blk_size * width_64 * height_32;
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(amvdec_am21c_body_size);
>>>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_body_size);
>>>>    
>>>>    /* 32 bytes per 128x64 block */
>>>> -u32 amvdec_am21c_head_size(u32 width, u32 height)
>>>> +u32 amvdec_amfbc_head_size(u32 width, u32 height)
>>>>    {
>>>>    	u32 width_128 = ALIGN(width, 128) / 128;
>>>>    	u32 height_64 = ALIGN(height, 64) / 64;
>>>>    
>>>>    	return 32 * width_128 * height_64;
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(amvdec_am21c_head_size);
>>>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_head_size);
>>>>    
>>>> -u32 amvdec_am21c_size(u32 width, u32 height)
>>>> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu)
>>>>    {
>>>> -	return ALIGN(amvdec_am21c_body_size(width, height) +
>>>> -		     amvdec_am21c_head_size(width, height), SZ_64K);
>>>> +	return ALIGN(amvdec_amfbc_body_size(width, height, is_10bit, use_mmu) +
>>>> +		     amvdec_amfbc_head_size(width, height), SZ_64K);
>>>>    }
>>>> -EXPORT_SYMBOL_GPL(amvdec_am21c_size);
>>>> +EXPORT_SYMBOL_GPL(amvdec_amfbc_size);
>>>>    
>>>>    static int canvas_alloc(struct amvdec_session *sess, u8 *canvas_id)
>>>>    {
>>>> @@ -440,7 +448,7 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>>>>    EXPORT_SYMBOL_GPL(amvdec_set_par_from_dar);
>>>>    
>>>>    void amvdec_src_change(struct amvdec_session *sess, u32 width,
>>>> -		       u32 height, u32 dpb_size)
>>>> +		       u32 height, u32 dpb_size, u32 bitdepth)
>>>>    {
>>>>    	static const struct v4l2_event ev = {
>>>>    		.type = V4L2_EVENT_SOURCE_CHANGE,
>>>> @@ -448,25 +456,27 @@ void amvdec_src_change(struct amvdec_session *sess, u32 width,
>>>>    
>>>>    	v4l2_ctrl_s_ctrl(sess->ctrl_min_buf_capture, dpb_size);
>>>>    
>>>> +	sess->bitdepth = bitdepth;
>>>> +
>>>>    	/*
>>>>    	 * Check if the capture queue is already configured well for our
>>>> -	 * usecase. If so, keep decoding with it and do not send the event
>>>> +	 * usecase. If so, keep decoding with it.
>>>>    	 */
>>>>    	if (sess->streamon_cap &&
>>>>    	    sess->width == width &&
>>>>    	    sess->height == height &&
>>>>    	    dpb_size <= sess->num_dst_bufs) {
>>>>    		sess->fmt_out->codec_ops->resume(sess);
>>>> -		return;
>>>> +	} else {
>>>> +		sess->status = STATUS_NEEDS_RESUME;
>>>> +		sess->changed_format = 0;
>>>>    	}
>>>>    
>>>> -	sess->changed_format = 0;
>>>>    	sess->width = width;
>>>>    	sess->height = height;
>>>> -	sess->status = STATUS_NEEDS_RESUME;
>>>>    
>>>> -	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB size %u\n",
>>>> -		width, height, dpb_size);
>>>> +	dev_dbg(sess->core->dev, "Res. changed (%ux%u), DPB %u, bitdepth %u\n",
>>>> +		width, height, dpb_size, bitdepth);
>>>>    	v4l2_event_queue_fh(&sess->fh, &ev);
>>>>    }
>>>>    EXPORT_SYMBOL_GPL(amvdec_src_change);
>>>> diff --git a/drivers/staging/media/meson/vdec/vdec_helpers.h b/drivers/staging/media/meson/vdec/vdec_helpers.h
>>>> index 4bf3e61d081b..1a711679d26a 100644
>>>> --- a/drivers/staging/media/meson/vdec/vdec_helpers.h
>>>> +++ b/drivers/staging/media/meson/vdec/vdec_helpers.h
>>>> @@ -27,9 +27,10 @@ void amvdec_clear_dos_bits(struct amvdec_core *core, u32 reg, u32 val);
>>>>    u32 amvdec_read_parser(struct amvdec_core *core, u32 reg);
>>>>    void amvdec_write_parser(struct amvdec_core *core, u32 reg, u32 val);
>>>>    
>>>> -u32 amvdec_am21c_body_size(u32 width, u32 height);
>>>> -u32 amvdec_am21c_head_size(u32 width, u32 height);
>>>> -u32 amvdec_am21c_size(u32 width, u32 height);
>>>> +/* Helpers for the Amlogic compressed framebuffer format */
>>>> +u32 amvdec_amfbc_body_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>>>> +u32 amvdec_amfbc_head_size(u32 width, u32 height);
>>>> +u32 amvdec_amfbc_size(u32 width, u32 height, u32 is_10bit, u32 use_mmu);
>>>>    
>>>>    /**
>>>>     * amvdec_dst_buf_done_idx() - Signal that a buffer is done decoding
>>>> @@ -77,9 +78,10 @@ void amvdec_set_par_from_dar(struct amvdec_session *sess,
>>>>     * @width: picture width detected by the hardware
>>>>     * @height: picture height detected by the hardware
>>>>     * @dpb_size: Decoded Picture Buffer size (= amount of buffers for decoding)
>>>> + * @bitdepth: Bit depth (usually 10 or 8) of the coded content
>>>>     */
>>>>    void amvdec_src_change(struct amvdec_session *sess, u32 width,
>>>> -		       u32 height, u32 dpb_size);
>>>> +		       u32 height, u32 dpb_size, u32 bitdepth);
>>>>    
>>>>    /**
>>>>     * amvdec_abort() - Abort the current decoding session
>>>
>>
> 


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Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Nicolas Dufresne]

Hi Neil,

Le mardi 24 janvier 2023 à 17:51 +0100, neil.armstrong@linaro.org a écrit :
> We hoped we could use the same modifier as DRM, but it seems this is now out of scope.
> 
> Neil

Its not out of scope, its just not being worked on. There is no infra to support
an extra 64bit modifier in V4L2 atm, or to use DRM formats in general. Folks
form Qualcomm or Mediatek didn't want to do it, so they worked around by adding
their strictly needed subset of compressed formats. If you don't want this, then
fine, but I'm not aware of someone actively working on that today.

I was just curious if there was anything other then NV12 (something 10bit) on
the secondary buffer case, that was my initial question here ;-D.

Nicolas

Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Nicolas Dufresne]

Hi Neil,

Le mardi 24 janvier 2023 à 17:51 +0100, neil.armstrong@linaro.org a écrit :
> We hoped we could use the same modifier as DRM, but it seems this is now out of scope.
> 
> Neil

Its not out of scope, its just not being worked on. There is no infra to support
an extra 64bit modifier in V4L2 atm, or to use DRM formats in general. Folks
form Qualcomm or Mediatek didn't want to do it, so they worked around by adding
their strictly needed subset of compressed formats. If you don't want this, then
fine, but I'm not aware of someone actively working on that today.

I was just curious if there was anything other then NV12 (something 10bit) on
the secondary buffer case, that was my initial question here ;-D.

Nicolas


_______________________________________________
linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v2 1/2] media: meson: vdec: implement 10bit bitstream handling

[Nicolas Dufresne]

Hi Neil,

Le mardi 24 janvier 2023 à 17:51 +0100, neil.armstrong@linaro.org a écrit :
> We hoped we could use the same modifier as DRM, but it seems this is now out of scope.
> 
> Neil

Its not out of scope, its just not being worked on. There is no infra to support
an extra 64bit modifier in V4L2 atm, or to use DRM formats in general. Folks
form Qualcomm or Mediatek didn't want to do it, so they worked around by adding
their strictly needed subset of compressed formats. If you don't want this, then
fine, but I'm not aware of someone actively working on that today.

I was just curious if there was anything other then NV12 (something 10bit) on
the secondary buffer case, that was my initial question here ;-D.

Nicolas


_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

[PATCH v2 2/2] media: meson: vdec: add HEVC decode codec

[Christian Hewitt]

From: Maxime Jourdan <mjourdan@baylibre.com>

Add initial HEVC codec for the Amlogic GXBB/GXL/GXM SoCs using
the common "HEVC" decoder driver.

Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
[codec alignment to upstream changes and frame handling improvements]
Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
 drivers/staging/media/meson/vdec/Makefile     |    2 +-
 drivers/staging/media/meson/vdec/codec_hevc.c | 1462 +++++++++++++++++
 drivers/staging/media/meson/vdec/codec_hevc.h |   13 +
 drivers/staging/media/meson/vdec/esparser.c   |    3 +-
 drivers/staging/media/meson/vdec/hevc_regs.h  |    1 +
 .../staging/media/meson/vdec/vdec_platform.c  |   37 +
 6 files changed, 1516 insertions(+), 2 deletions(-)
 create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.c
 create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.h

diff --git a/drivers/staging/media/meson/vdec/Makefile b/drivers/staging/media/meson/vdec/Makefile
index 6e726af84ac9..16f848e456b9 100644
--- a/drivers/staging/media/meson/vdec/Makefile
+++ b/drivers/staging/media/meson/vdec/Makefile
@@ -3,6 +3,6 @@
 
 meson-vdec-objs = esparser.o vdec.o vdec_helpers.o vdec_platform.o
 meson-vdec-objs += vdec_1.o vdec_hevc.o
-meson-vdec-objs += codec_mpeg12.o codec_h264.o codec_hevc_common.o codec_vp9.o
+meson-vdec-objs += codec_mpeg12.o codec_h264.o codec_hevc_common.o codec_vp9.o codec_hevc.o
 
 obj-$(CONFIG_VIDEO_MESON_VDEC) += meson-vdec.o
diff --git a/drivers/staging/media/meson/vdec/codec_hevc.c b/drivers/staging/media/meson/vdec/codec_hevc.c
new file mode 100644
index 000000000000..fcaaa1ad50b8
--- /dev/null
+++ b/drivers/staging/media/meson/vdec/codec_hevc.c
@@ -0,0 +1,1462 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Maxime Jourdan <mjourdan@baylibre.com>
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ */
+
+#include <media/v4l2-mem2mem.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "codec_hevc.h"
+#include "dos_regs.h"
+#include "hevc_regs.h"
+#include "vdec_helpers.h"
+#include "codec_hevc_common.h"
+
+/* HEVC reg mapping */
+#define HEVC_DEC_STATUS_REG	HEVC_ASSIST_SCRATCH_0
+	#define HEVC_ACTION_DONE	0xff
+#define HEVC_RPM_BUFFER		HEVC_ASSIST_SCRATCH_1
+#define HEVC_SHORT_TERM_RPS	HEVC_ASSIST_SCRATCH_2
+#define HEVC_VPS_BUFFER		HEVC_ASSIST_SCRATCH_3
+#define HEVC_SPS_BUFFER		HEVC_ASSIST_SCRATCH_4
+#define HEVC_PPS_BUFFER		HEVC_ASSIST_SCRATCH_5
+#define HEVC_SAO_UP		HEVC_ASSIST_SCRATCH_6
+#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
+#define H265_MMU_MAP_BUFFER	HEVC_ASSIST_SCRATCH_7
+#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
+#define HEVC_sao_mem_unit	HEVC_ASSIST_SCRATCH_9
+#define HEVC_SAO_ABV		HEVC_ASSIST_SCRATCH_A
+#define HEVC_sao_vb_size	HEVC_ASSIST_SCRATCH_B
+#define HEVC_SAO_VB		HEVC_ASSIST_SCRATCH_C
+#define HEVC_SCALELUT		HEVC_ASSIST_SCRATCH_D
+#define HEVC_WAIT_FLAG		HEVC_ASSIST_SCRATCH_E
+#define RPM_CMD_REG		HEVC_ASSIST_SCRATCH_F
+#define LMEM_DUMP_ADR		HEVC_ASSIST_SCRATCH_F
+#define DEBUG_REG1		HEVC_ASSIST_SCRATCH_G
+#define HEVC_DECODE_MODE2	HEVC_ASSIST_SCRATCH_H
+#define NAL_SEARCH_CTL		HEVC_ASSIST_SCRATCH_I
+#define HEVC_DECODE_MODE	HEVC_ASSIST_SCRATCH_J
+	#define DECODE_MODE_SINGLE 0
+#define DECODE_STOP_POS		HEVC_ASSIST_SCRATCH_K
+#define HEVC_AUX_ADR		HEVC_ASSIST_SCRATCH_L
+#define HEVC_AUX_DATA_SIZE	HEVC_ASSIST_SCRATCH_M
+#define HEVC_DECODE_SIZE	HEVC_ASSIST_SCRATCH_N
+
+#define AMRISC_MAIN_REQ		 0x04
+
+/* HEVC Constants */
+#define MAX_REF_PIC_NUM		24
+#define MAX_REF_ACTIVE		16
+#define MAX_TILE_COL_NUM	10
+#define MAX_TILE_ROW_NUM	20
+#define MAX_SLICE_NUM		800
+#define INVALID_POC		0x80000000
+
+/* HEVC Workspace layout */
+#define MPRED_MV_BUF_SIZE 0x120000
+
+#define IPP_SIZE	0x4000
+#define SAO_ABV_SIZE	0x30000
+#define SAO_VB_SIZE	0x30000
+#define SH_TM_RPS_SIZE	0x800
+#define VPS_SIZE	0x800
+#define SPS_SIZE	0x800
+#define PPS_SIZE	0x2000
+#define SAO_UP_SIZE	0x2800
+#define SWAP_BUF_SIZE	0x800
+#define SWAP_BUF2_SIZE	0x800
+#define SCALELUT_SIZE	0x8000
+#define DBLK_PARA_SIZE	0x20000
+#define DBLK_DATA_SIZE	0x80000
+#define DBLK_DATA2_SIZE	0x80000
+#define MMU_VBH_SIZE	0x5000
+#define MPRED_ABV_SIZE	0x8000
+#define MPRED_MV_SIZE	(MPRED_MV_BUF_SIZE * MAX_REF_PIC_NUM)
+#define RPM_BUF_SIZE	0x100
+#define LMEM_SIZE	0xA00
+
+#define IPP_OFFSET       0x00
+#define SAO_ABV_OFFSET   (IPP_OFFSET + IPP_SIZE)
+#define SAO_VB_OFFSET    (SAO_ABV_OFFSET + SAO_ABV_SIZE)
+#define SH_TM_RPS_OFFSET (SAO_VB_OFFSET + SAO_VB_SIZE)
+#define VPS_OFFSET       (SH_TM_RPS_OFFSET + SH_TM_RPS_SIZE)
+#define SPS_OFFSET       (VPS_OFFSET + VPS_SIZE)
+#define PPS_OFFSET       (SPS_OFFSET + SPS_SIZE)
+#define SAO_UP_OFFSET    (PPS_OFFSET + PPS_SIZE)
+#define SWAP_BUF_OFFSET  (SAO_UP_OFFSET + SAO_UP_SIZE)
+#define SWAP_BUF2_OFFSET (SWAP_BUF_OFFSET + SWAP_BUF_SIZE)
+#define SCALELUT_OFFSET  (SWAP_BUF2_OFFSET + SWAP_BUF2_SIZE)
+#define DBLK_PARA_OFFSET (SCALELUT_OFFSET + SCALELUT_SIZE)
+#define DBLK_DATA_OFFSET (DBLK_PARA_OFFSET + DBLK_PARA_SIZE)
+#define DBLK_DATA2_OFFSET (DBLK_DATA_OFFSET + DBLK_DATA_SIZE)
+#define MMU_VBH_OFFSET   (DBLK_DATA2_OFFSET + DBLK_DATA2_SIZE)
+#define MPRED_ABV_OFFSET (MMU_VBH_OFFSET + MMU_VBH_SIZE)
+#define MPRED_MV_OFFSET  (MPRED_ABV_OFFSET + MPRED_ABV_SIZE)
+#define RPM_OFFSET       (MPRED_MV_OFFSET + MPRED_MV_SIZE)
+#define LMEM_OFFSET      (RPM_OFFSET + RPM_BUF_SIZE)
+
+/* ISR decode status */
+#define HEVC_DEC_IDLE                        0x0
+#define HEVC_NAL_UNIT_VPS                    0x1
+#define HEVC_NAL_UNIT_SPS                    0x2
+#define HEVC_NAL_UNIT_PPS                    0x3
+#define HEVC_NAL_UNIT_CODED_SLICE_SEGMENT    0x4
+#define HEVC_CODED_SLICE_SEGMENT_DAT         0x5
+#define HEVC_SLICE_DECODING                  0x6
+#define HEVC_NAL_UNIT_SEI                    0x7
+#define HEVC_SLICE_SEGMENT_DONE              0x8
+#define HEVC_NAL_SEARCH_DONE                 0x9
+#define HEVC_DECPIC_DATA_DONE                0xa
+#define HEVC_DECPIC_DATA_ERROR               0xb
+#define HEVC_SEI_DAT                         0xc
+#define HEVC_SEI_DAT_DONE                    0xd
+
+/* RPM misc_flag0 */
+#define PCM_LOOP_FILTER_DISABLED_FLAG_BIT		0
+#define PCM_ENABLE_FLAG_BIT				1
+#define LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT	2
+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT	3
+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT	4
+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT		5
+#define DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT		6
+#define SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT	7
+#define SLICE_SAO_LUMA_FLAG_BIT				8
+#define SLICE_SAO_CHROMA_FLAG_BIT			9
+#define SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT 10
+
+/* Constants for HEVC_MPRED_CTRL1 */
+#define AMVP_MAX_NUM_CANDS_MEM	3
+#define AMVP_MAX_NUM_CANDS	2
+#define NUM_CHROMA_MODE		5
+#define DM_CHROMA_IDX		36
+
+/* Buffer sizes */
+#define SIZE_WORKSPACE ALIGN(LMEM_OFFSET + LMEM_SIZE, 64 * SZ_1K)
+#define SIZE_AUX (SZ_1K * 16)
+#define SIZE_FRAME_MMU (0x1200 * 4)
+#define RPM_SIZE 0x80
+#define RPS_USED_BIT 14
+
+/* Data received from the HW in this form, do not rearrange */
+union rpm_param {
+	struct {
+		u16 data[RPM_SIZE];
+	} l;
+	struct {
+		u16 CUR_RPS[MAX_REF_ACTIVE];
+		u16 num_ref_idx_l0_active;
+		u16 num_ref_idx_l1_active;
+		u16 slice_type;
+		u16 slice_temporal_mvp_enable_flag;
+		u16 dependent_slice_segment_flag;
+		u16 slice_segment_address;
+		u16 num_title_rows_minus1;
+		u16 pic_width_in_luma_samples;
+		u16 pic_height_in_luma_samples;
+		u16 log2_min_coding_block_size_minus3;
+		u16 log2_diff_max_min_coding_block_size;
+		u16 log2_max_pic_order_cnt_lsb_minus4;
+		u16 POClsb;
+		u16 collocated_from_l0_flag;
+		u16 collocated_ref_idx;
+		u16 log2_parallel_merge_level;
+		u16 five_minus_max_num_merge_cand;
+		u16 sps_num_reorder_pics_0;
+		u16 modification_flag;
+		u16 tiles_flags;
+		u16 num_tile_columns_minus1;
+		u16 num_tile_rows_minus1;
+		u16 tile_width[8];
+		u16 tile_height[8];
+		u16 misc_flag0;
+		u16 pps_beta_offset_div2;
+		u16 pps_tc_offset_div2;
+		u16 slice_beta_offset_div2;
+		u16 slice_tc_offset_div2;
+		u16 pps_cb_qp_offset;
+		u16 pps_cr_qp_offset;
+		u16 first_slice_segment_in_pic_flag;
+		u16 m_temporalId;
+		u16 m_nalUnitType;
+		u16 vui_num_units_in_tick_hi;
+		u16 vui_num_units_in_tick_lo;
+		u16 vui_time_scale_hi;
+		u16 vui_time_scale_lo;
+		u16 bit_depth;
+		u16 profile_etc;
+		u16 sei_frame_field_info;
+		u16 video_signal_type;
+		u16 modification_list[0x20];
+		u16 conformance_window_flag;
+		u16 conf_win_left_offset;
+		u16 conf_win_right_offset;
+		u16 conf_win_top_offset;
+		u16 conf_win_bottom_offset;
+		u16 chroma_format_idc;
+		u16 color_description;
+		u16 aspect_ratio_idc;
+		u16 sar_width;
+		u16 sar_height;
+	} p;
+};
+
+enum nal_unit_type {
+	NAL_UNIT_CODED_SLICE_BLA	= 16,
+	NAL_UNIT_CODED_SLICE_BLANT	= 17,
+	NAL_UNIT_CODED_SLICE_BLA_N_LP	= 18,
+	NAL_UNIT_CODED_SLICE_IDR	= 19,
+	NAL_UNIT_CODED_SLICE_IDR_N_LP	= 20,
+};
+
+enum slice_type {
+	B_SLICE = 0,
+	P_SLICE = 1,
+	I_SLICE = 2,
+};
+
+/* A frame being decoded */
+struct hevc_frame {
+	struct list_head list;
+	struct vb2_v4l2_buffer *vbuf;
+	u32 offset;
+	u32 poc;
+
+	int referenced;
+	int show;
+	u32 num_reorder_pic;
+
+	u32 cur_slice_idx;
+	u32 cur_slice_type;
+
+	/* 2 lists (L0/L1) ; 800 slices ; 16 refs */
+	u32 ref_poc_list[2][MAX_SLICE_NUM][MAX_REF_ACTIVE];
+	u32 ref_num[2];
+};
+
+struct codec_hevc {
+	/* Protect the data structure */
+	struct mutex lock;
+
+	/* Common part of the HEVC decoder */
+	struct codec_hevc_common common;
+
+	/* Buffer for the HEVC Workspace */
+	void      *workspace_vaddr;
+	dma_addr_t workspace_paddr;
+
+	/* AUX buffer */
+	void      *aux_vaddr;
+	dma_addr_t aux_paddr;
+
+	/* Contains many information parsed from the bitstream */
+	union rpm_param rpm_param;
+
+	/* Information computed from the RPM */
+	u32 lcu_size; // Largest Coding Unit
+	u32 lcu_x_num;
+	u32 lcu_y_num;
+	u32 lcu_total;
+
+	/* Current Frame being handled */
+	struct hevc_frame *cur_frame;
+	u32 curr_poc;
+	/* Collocated Reference Picture */
+	struct hevc_frame *col_frame;
+	u32 col_poc;
+
+	/* All ref frames used by the HW at a given time */
+	struct list_head ref_frames_list;
+	u32 frames_num;
+
+	/* Coded resolution reported by the hardware */
+	u32 width, height;
+	/* Resolution minus the conformance window offsets */
+	u32 dst_width, dst_height;
+
+	u32 prev_tid0_poc;
+	u32 slice_segment_addr;
+	u32 slice_addr;
+	u32 ldc_flag;
+
+	/* Whether we detected the bitstream as 10-bit */
+	int is_10bit;
+};
+
+static u32 codec_hevc_num_pending_bufs(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc;
+	u32 ret;
+
+	hevc = sess->priv;
+	if (!hevc)
+		return 0;
+
+	mutex_lock(&hevc->lock);
+	ret = hevc->frames_num;
+	mutex_unlock(&hevc->lock);
+
+	return ret;
+}
+
+/* Update the L0 and L1 reference lists for a given frame */
+static void codec_hevc_update_frame_refs(struct amvdec_session *sess,
+					 struct hevc_frame *frame)
+{
+	struct codec_hevc *hevc = sess->priv;
+	union rpm_param *params = &hevc->rpm_param;
+	int num_ref_idx_l0_active =
+		(params->p.num_ref_idx_l0_active > MAX_REF_ACTIVE) ?
+		MAX_REF_ACTIVE : params->p.num_ref_idx_l0_active;
+	int num_ref_idx_l1_active =
+		(params->p.num_ref_idx_l1_active > MAX_REF_ACTIVE) ?
+		MAX_REF_ACTIVE : params->p.num_ref_idx_l1_active;
+	int ref_picset0[MAX_REF_ACTIVE] = { 0 };
+	int ref_picset1[MAX_REF_ACTIVE] = { 0 };
+	u16 *mod_list = params->p.modification_list;
+	int num_neg = 0;
+	int num_pos = 0;
+	int total_num;
+	int i;
+
+	for (i = 0; i < MAX_REF_ACTIVE; i++) {
+		frame->ref_poc_list[0][frame->cur_slice_idx][i] = 0;
+		frame->ref_poc_list[1][frame->cur_slice_idx][i] = 0;
+	}
+
+	for (i = 0; i < MAX_REF_ACTIVE; i++) {
+		u16 cur_rps = params->p.CUR_RPS[i];
+		int delt = cur_rps & ((1 << (RPS_USED_BIT - 1)) - 1);
+
+		if (cur_rps & 0x8000)
+			break;
+
+		if (!((cur_rps >> RPS_USED_BIT) & 1))
+			continue;
+
+		if ((cur_rps >> (RPS_USED_BIT - 1)) & 1) {
+			ref_picset0[num_neg] =
+			       frame->poc - ((1 << (RPS_USED_BIT - 1)) - delt);
+			num_neg++;
+		} else {
+			ref_picset1[num_pos] = frame->poc + delt;
+			num_pos++;
+		}
+	}
+
+	total_num = num_neg + num_pos;
+
+	if (total_num <= 0)
+		goto end;
+
+	for (i = 0; i < num_ref_idx_l0_active; i++) {
+		int cidx;
+
+		if (params->p.modification_flag & 0x1)
+			cidx = mod_list[i];
+		else
+			cidx = i % total_num;
+
+		frame->ref_poc_list[0][frame->cur_slice_idx][i] =
+			cidx >= num_neg ? ref_picset1[cidx - num_neg] :
+			ref_picset0[cidx];
+	}
+
+	if (params->p.slice_type != B_SLICE)
+		goto end;
+
+	if (params->p.modification_flag & 0x2) {
+		for (i = 0; i < num_ref_idx_l1_active; i++) {
+			int cidx;
+
+			if (params->p.modification_flag & 0x1)
+				cidx = mod_list[num_ref_idx_l0_active + i];
+			else
+				cidx = mod_list[i];
+
+			frame->ref_poc_list[1][frame->cur_slice_idx][i] =
+				(cidx >= num_pos) ? ref_picset0[cidx - num_pos]
+				: ref_picset1[cidx];
+		}
+	} else {
+		for (i = 0; i < num_ref_idx_l1_active; i++) {
+			int cidx = i % total_num;
+
+			frame->ref_poc_list[1][frame->cur_slice_idx][i] =
+				cidx >= num_pos ? ref_picset0[cidx - num_pos] :
+				ref_picset1[cidx];
+		}
+	}
+
+end:
+	frame->ref_num[0] = num_ref_idx_l0_active;
+	frame->ref_num[1] = num_ref_idx_l1_active;
+
+	dev_dbg(sess->core->dev,
+		"Frame %u; slice %u; slice_type %u; num_l0 %u; num_l1 %u\n",
+		frame->poc, frame->cur_slice_idx, params->p.slice_type,
+		frame->ref_num[0], frame->ref_num[1]);
+}
+
+static void codec_hevc_update_ldc_flag(struct codec_hevc *hevc)
+{
+	struct hevc_frame *frame = hevc->cur_frame;
+	u32 slice_type = frame->cur_slice_type;
+	u32 slice_idx = frame->cur_slice_idx;
+	int i;
+
+	hevc->ldc_flag = 0;
+
+	if (slice_type == I_SLICE)
+		return;
+
+	hevc->ldc_flag = 1;
+	for (i = 0; (i < frame->ref_num[0]) && hevc->ldc_flag; i++) {
+		if (frame->ref_poc_list[0][slice_idx][i] > frame->poc) {
+			hevc->ldc_flag = 0;
+			break;
+		}
+	}
+
+	if (slice_type == P_SLICE)
+		return;
+
+	for (i = 0; (i < frame->ref_num[1]) && hevc->ldc_flag; i++) {
+		if (frame->ref_poc_list[1][slice_idx][i] > frame->poc) {
+			hevc->ldc_flag = 0;
+			break;
+		}
+	}
+}
+
+/* Tag "old" frames that are no longer referenced */
+static void codec_hevc_update_referenced(struct codec_hevc *hevc)
+{
+	union rpm_param *param = &hevc->rpm_param;
+	struct hevc_frame *frame;
+	int i;
+	u32 curr_poc = hevc->curr_poc;
+
+	list_for_each_entry(frame, &hevc->ref_frames_list, list) {
+		int is_referenced = 0;
+		u32 poc_tmp;
+
+		if (!frame->referenced)
+			continue;
+
+		for (i = 0; i < MAX_REF_ACTIVE; i++) {
+			int delt;
+
+			if (param->p.CUR_RPS[i] & 0x8000)
+				break;
+
+			delt = param->p.CUR_RPS[i] &
+			       ((1 << (RPS_USED_BIT - 1)) - 1);
+			if (param->p.CUR_RPS[i] & (1 << (RPS_USED_BIT - 1))) {
+				poc_tmp = curr_poc -
+				      ((1 << (RPS_USED_BIT - 1)) - delt);
+			} else {
+				poc_tmp = curr_poc + delt;
+			}
+
+			if (poc_tmp == frame->poc) {
+				is_referenced = 1;
+				break;
+			}
+		}
+
+		frame->referenced = is_referenced;
+	}
+}
+
+static struct hevc_frame *
+codec_hevc_get_next_ready_frame(struct codec_hevc *hevc)
+{
+	struct hevc_frame *tmp, *ret = NULL;
+	u32 poc = INT_MAX;
+
+	list_for_each_entry(tmp, &hevc->ref_frames_list, list) {
+		if ((tmp->poc < poc) && tmp->show) {
+			ret = tmp;
+			poc = tmp->poc;
+		}
+	}
+
+	return ret;
+}
+
+/* Try to output as many frames as possible */
+static void codec_hevc_show_frames(struct amvdec_session *sess)
+{
+	struct hevc_frame *tmp, *n;
+	struct codec_hevc *hevc = sess->priv;
+
+	while ((tmp = codec_hevc_get_next_ready_frame(hevc))) {
+		if (hevc->curr_poc &&
+		    (hevc->frames_num <= tmp->num_reorder_pic))
+			break;
+
+		dev_dbg(sess->core->dev, "DONE frame poc %u; vbuf %u\n",
+			tmp->poc, tmp->vbuf->vb2_buf.index);
+		amvdec_dst_buf_done_offset(sess, tmp->vbuf, tmp->offset,
+					   V4L2_FIELD_NONE, false);
+
+		tmp->show = 0;
+		hevc->frames_num--;
+	}
+
+	/* clean output frame buffer */
+	list_for_each_entry_safe(tmp, n, &hevc->ref_frames_list, list) {
+		if (tmp->referenced || tmp->show)
+			continue;
+
+		list_del(&tmp->list);
+		kfree(tmp);
+	}
+}
+
+static int
+codec_hevc_setup_workspace(struct amvdec_session *sess,
+			   struct codec_hevc *hevc)
+{
+	struct amvdec_core *core = sess->core;
+	u32 revision = core->platform->revision;
+	dma_addr_t wkaddr;
+
+	/* Allocate some memory for the HEVC decoder's state */
+	hevc->workspace_vaddr = dma_alloc_coherent(core->dev, SIZE_WORKSPACE,
+						   &wkaddr, GFP_KERNEL);
+	if (!hevc->workspace_vaddr)
+		return -ENOMEM;
+
+	hevc->workspace_paddr = wkaddr;
+
+	amvdec_write_dos(core, HEVCD_IPP_LINEBUFF_BASE, wkaddr + IPP_OFFSET);
+	amvdec_write_dos(core, HEVC_RPM_BUFFER, wkaddr + RPM_OFFSET);
+	amvdec_write_dos(core, HEVC_SHORT_TERM_RPS, wkaddr + SH_TM_RPS_OFFSET);
+	amvdec_write_dos(core, HEVC_VPS_BUFFER, wkaddr + VPS_OFFSET);
+	amvdec_write_dos(core, HEVC_SPS_BUFFER, wkaddr + SPS_OFFSET);
+	amvdec_write_dos(core, HEVC_PPS_BUFFER, wkaddr + PPS_OFFSET);
+	amvdec_write_dos(core, HEVC_SAO_UP, wkaddr + SAO_UP_OFFSET);
+
+	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, hevc->is_10bit)) {
+		amvdec_write_dos(core, HEVC_SAO_MMU_VH0_ADDR,
+				 wkaddr + MMU_VBH_OFFSET);
+		amvdec_write_dos(core, HEVC_SAO_MMU_VH1_ADDR,
+				 wkaddr + MMU_VBH_OFFSET + (MMU_VBH_SIZE / 2));
+
+		if (revision >= VDEC_REVISION_G12A)
+			amvdec_write_dos(core, HEVC_ASSIST_MMU_MAP_ADDR,
+					 hevc->common.mmu_map_paddr);
+		else
+			amvdec_write_dos(core, H265_MMU_MAP_BUFFER,
+					 hevc->common.mmu_map_paddr);
+	} else if (revision < VDEC_REVISION_G12A) {
+		amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER,
+				 wkaddr + SWAP_BUF_OFFSET);
+		amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER2,
+				 wkaddr + SWAP_BUF2_OFFSET);
+	}
+
+	amvdec_write_dos(core, HEVC_SCALELUT, wkaddr + SCALELUT_OFFSET);
+	amvdec_write_dos(core, HEVC_DBLK_CFG4, wkaddr + DBLK_PARA_OFFSET);
+	amvdec_write_dos(core, HEVC_DBLK_CFG5, wkaddr + DBLK_DATA_OFFSET);
+	if (revision >= VDEC_REVISION_G12A)
+		amvdec_write_dos(core, HEVC_DBLK_CFGE,
+				 wkaddr + DBLK_DATA2_OFFSET);
+
+	amvdec_write_dos(core, LMEM_DUMP_ADR, wkaddr + LMEM_OFFSET);
+
+	return 0;
+}
+
+static int codec_hevc_start(struct amvdec_session *sess)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc;
+	u32 val;
+	int i;
+	int ret;
+
+	hevc = kzalloc(sizeof(*hevc), GFP_KERNEL);
+	if (!hevc)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&hevc->ref_frames_list);
+	hevc->curr_poc = INVALID_POC;
+
+	ret = codec_hevc_setup_workspace(sess, hevc);
+	if (ret)
+		goto free_hevc;
+
+	val = BIT(0); /* stream_fetch_enable */
+	if (core->platform->revision >= VDEC_REVISION_G12A)
+		val |= (0xf << 25); /* arwlen_axi_max */
+	amvdec_write_dos_bits(core, HEVC_STREAM_CONTROL, val);
+
+	val = amvdec_read_dos(core, HEVC_PARSER_INT_CONTROL) & 0x03ffffff;
+	val |= (3 << 29) | BIT(27) | BIT(24) | BIT(22) | BIT(7) | BIT(4) |
+	       BIT(0);
+	amvdec_write_dos(core, HEVC_PARSER_INT_CONTROL, val);
+	amvdec_write_dos_bits(core, HEVC_SHIFT_STATUS, BIT(1) | BIT(0));
+	amvdec_write_dos(core, HEVC_SHIFT_CONTROL,
+			 (3 << 6) | BIT(5) | BIT(2) | BIT(0));
+	amvdec_write_dos(core, HEVC_CABAC_CONTROL, 1);
+	amvdec_write_dos(core, HEVC_PARSER_CORE_CONTROL, 1);
+	amvdec_write_dos(core, HEVC_DEC_STATUS_REG, 0);
+
+	amvdec_write_dos(core, HEVC_IQIT_SCALELUT_WR_ADDR, 0);
+	for (i = 0; i < 1024; ++i)
+		amvdec_write_dos(core, HEVC_IQIT_SCALELUT_DATA, 0);
+
+	amvdec_write_dos(core, HEVC_DECODE_SIZE, 0);
+
+	amvdec_write_dos(core, HEVC_PARSER_CMD_WRITE, BIT(16));
+	for (i = 0; i < ARRAY_SIZE(vdec_hevc_parser_cmd); ++i)
+		amvdec_write_dos(core, HEVC_PARSER_CMD_WRITE,
+				 vdec_hevc_parser_cmd[i]);
+
+	amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
+	amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
+	amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
+	amvdec_write_dos(core, HEVC_PARSER_IF_CONTROL,
+			 BIT(5) | BIT(2) | BIT(0));
+
+	amvdec_write_dos(core, HEVCD_IPP_TOP_CNTL, BIT(0));
+	amvdec_write_dos(core, HEVCD_IPP_TOP_CNTL, BIT(1));
+
+	amvdec_write_dos(core, HEVC_WAIT_FLAG, 1);
+
+	/* clear mailbox interrupt */
+	amvdec_write_dos(core, HEVC_ASSIST_MBOX1_CLR_REG, 1);
+	/* enable mailbox interrupt */
+	amvdec_write_dos(core, HEVC_ASSIST_MBOX1_MASK, 1);
+	/* disable PSCALE for hardware sharing */
+	amvdec_write_dos(core, HEVC_PSCALE_CTRL, 0);
+	/* Let the uCode do all the parsing */
+	amvdec_write_dos(core, NAL_SEARCH_CTL, 0xc);
+
+	amvdec_write_dos(core, DECODE_STOP_POS, 0);
+	amvdec_write_dos(core, HEVC_DECODE_MODE, DECODE_MODE_SINGLE);
+	amvdec_write_dos(core, HEVC_DECODE_MODE2, 0);
+
+	/* AUX buffers */
+	hevc->aux_vaddr = dma_alloc_coherent(core->dev, SIZE_AUX,
+					     &hevc->aux_paddr, GFP_KERNEL);
+	if (!hevc->aux_vaddr) {
+		ret = -ENOMEM;
+		goto free_hevc;
+	}
+
+	amvdec_write_dos(core, HEVC_AUX_ADR, hevc->aux_paddr);
+	amvdec_write_dos(core, HEVC_AUX_DATA_SIZE,
+			 (((SIZE_AUX) >> 4) << 16) | 0);
+	mutex_init(&hevc->lock);
+	sess->priv = hevc;
+
+	return 0;
+
+free_hevc:
+	kfree(hevc);
+	return ret;
+}
+
+static void codec_hevc_flush_output(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	struct hevc_frame *tmp, *n;
+
+	while ((tmp = codec_hevc_get_next_ready_frame(hevc))) {
+		amvdec_dst_buf_done(sess, tmp->vbuf, V4L2_FIELD_NONE);
+		tmp->show = 0;
+		hevc->frames_num--;
+	}
+
+	list_for_each_entry_safe(tmp, n, &hevc->ref_frames_list, list) {
+		list_del(&tmp->list);
+		kfree(tmp);
+	}
+}
+
+static int codec_hevc_stop(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	struct amvdec_core *core = sess->core;
+
+	mutex_lock(&hevc->lock);
+	codec_hevc_flush_output(sess);
+
+	if (hevc->workspace_vaddr)
+		dma_free_coherent(core->dev, SIZE_WORKSPACE,
+				  hevc->workspace_vaddr,
+				  hevc->workspace_paddr);
+
+	if (hevc->aux_vaddr)
+		dma_free_coherent(core->dev, SIZE_AUX,
+				  hevc->aux_vaddr, hevc->aux_paddr);
+
+	codec_hevc_free_fbc_buffers(sess, &hevc->common);
+	mutex_unlock(&hevc->lock);
+	mutex_destroy(&hevc->lock);
+
+	return 0;
+}
+
+static struct hevc_frame *
+codec_hevc_get_frame_by_poc(struct codec_hevc *hevc, u32 poc)
+{
+	struct hevc_frame *tmp;
+
+	list_for_each_entry(tmp, &hevc->ref_frames_list, list) {
+		if (tmp->poc == poc)
+			return tmp;
+	}
+
+	return NULL;
+}
+
+static struct hevc_frame *
+codec_hevc_prepare_new_frame(struct amvdec_session *sess)
+{
+	struct amvdec_core *core = sess->core;
+	struct hevc_frame *new_frame = NULL;
+	struct codec_hevc *hevc = sess->priv;
+	struct vb2_v4l2_buffer *vbuf;
+	union rpm_param *params = &hevc->rpm_param;
+
+	new_frame = kzalloc(sizeof(*new_frame), GFP_KERNEL);
+	if (!new_frame)
+		return NULL;
+
+	vbuf = v4l2_m2m_dst_buf_remove(sess->m2m_ctx);
+	if (!vbuf) {
+		dev_err(sess->core->dev, "No dst buffer available\n");
+		return NULL;
+	}
+
+	new_frame->vbuf = vbuf;
+	new_frame->referenced = 1;
+	new_frame->show = 1;
+	new_frame->poc = hevc->curr_poc;
+	new_frame->cur_slice_type = params->p.slice_type;
+	new_frame->num_reorder_pic = params->p.sps_num_reorder_pics_0;
+	new_frame->offset = amvdec_read_dos(core, HEVC_SHIFT_BYTE_COUNT);
+
+	list_add_tail(&new_frame->list, &hevc->ref_frames_list);
+	hevc->frames_num++;
+
+	return new_frame;
+}
+
+static void
+codec_hevc_set_sao(struct amvdec_session *sess, struct hevc_frame *frame)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc = sess->priv;
+	struct vb2_buffer *vb = &frame->vbuf->vb2_buf;
+	union rpm_param *param = &hevc->rpm_param;
+	u32 pic_height_cu =
+		(hevc->height + hevc->lcu_size - 1) / hevc->lcu_size;
+	u32 sao_mem_unit = (hevc->lcu_size == 16 ? 9 :
+			   hevc->lcu_size == 32 ? 14 : 24) << 4;
+	u32 sao_vb_size = (sao_mem_unit + (2 << 4)) * pic_height_cu;
+	u32 misc_flag0 = param->p.misc_flag0;
+	dma_addr_t buf_y_paddr;
+	dma_addr_t buf_u_v_paddr;
+	u32 slice_deblocking_filter_disabled_flag;
+	u32 val, val_2;
+
+	val = (amvdec_read_dos(core, HEVC_SAO_CTRL0) & ~0xf) |
+	      ilog2(hevc->lcu_size);
+	amvdec_write_dos(core, HEVC_SAO_CTRL0, val);
+
+	amvdec_write_dos(core, HEVC_SAO_PIC_SIZE,
+			 hevc->width | (hevc->height << 16));
+	amvdec_write_dos(core, HEVC_SAO_PIC_SIZE_LCU,
+			 (hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16);
+
+	if (codec_hevc_use_downsample(sess->pixfmt_cap, hevc->is_10bit) ||
+	    codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
+			       hevc->is_10bit))
+		buf_y_paddr =
+		     hevc->common.fbc_buffer_paddr[vb->index];
+	else
+		buf_y_paddr =
+		       vb2_dma_contig_plane_dma_addr(vb, 0);
+
+	if (codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
+		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0000;
+		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
+		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
+	}
+
+	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
+		buf_y_paddr =
+		       vb2_dma_contig_plane_dma_addr(vb, 0);
+		buf_u_v_paddr =
+		       vb2_dma_contig_plane_dma_addr(vb, 1);
+		amvdec_write_dos(core, HEVC_SAO_Y_START_ADDR, buf_y_paddr);
+		amvdec_write_dos(core, HEVC_SAO_C_START_ADDR, buf_u_v_paddr);
+		amvdec_write_dos(core, HEVC_SAO_Y_WPTR, buf_y_paddr);
+		amvdec_write_dos(core, HEVC_SAO_C_WPTR, buf_u_v_paddr);
+	}
+
+	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
+			       hevc->is_10bit)) {
+		dma_addr_t header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
+
+		if (codec_hevc_use_downsample(sess->pixfmt_cap, hevc->is_10bit))
+			header_adr = hevc->common.mmu_header_paddr[vb->index];
+		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
+		/* use HEVC_CM_HEADER_START_ADDR */
+		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
+		amvdec_write_dos_bits(core, HEVC_SAO_CTRL9, BIT(0));
+	}
+
+	amvdec_write_dos(core, HEVC_SAO_Y_LENGTH,
+			 amvdec_get_output_size(sess));
+	amvdec_write_dos(core, HEVC_SAO_C_LENGTH,
+			 (amvdec_get_output_size(sess) / 2));
+
+	if (frame->cur_slice_idx == 0) {
+		if (core->platform->revision >= VDEC_REVISION_G12A) {
+			if (core->platform->revision >= VDEC_REVISION_SM1)
+				val = 0xfc << 8;
+			else
+				val = 0x54 << 8;
+
+			/* enable first, compressed write */
+			if (codec_hevc_use_fbc(sess->pixfmt_cap,
+					       hevc->is_10bit))
+				val |= BIT(8);
+
+			/* enable second, uncompressed write */
+			if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
+				val |= BIT(9);
+
+			/* dblk pipeline mode=1 for performance */
+			if (hevc->width >= 1280)
+				val |= BIT(4);
+
+			amvdec_write_dos(core, HEVC_DBLK_CFGB, val);
+			amvdec_write_dos(core, HEVC_DBLK_STS1 + 16, BIT(28));
+		}
+
+		amvdec_write_dos(core, HEVC_DBLK_CFG2,
+				 hevc->width | (hevc->height << 16));
+
+		val = 0;
+		if ((misc_flag0 >> PCM_ENABLE_FLAG_BIT) & 0x1)
+			val |= ((misc_flag0 >>
+				 PCM_LOOP_FILTER_DISABLED_FLAG_BIT) & 0x1) << 3;
+
+		val |= (param->p.pps_cb_qp_offset & 0x1f) << 4;
+		val |= (param->p.pps_cr_qp_offset & 0x1f) << 9;
+		val |= (hevc->lcu_size == 64) ? 0 :
+		       ((hevc->lcu_size == 32) ? 1 : 2);
+		amvdec_write_dos(core, HEVC_DBLK_CFG1, val);
+	}
+
+	val = amvdec_read_dos(core, HEVC_SAO_CTRL1) & ~0x3ff3;
+	val |= 0xff0; /* Set endianness for 2-bytes swaps (nv12) */
+	if (core->platform->revision < VDEC_REVISION_G12A) {
+		if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit))
+			val |= BIT(0); /* disable cm compression */
+		/* TOFIX: Handle Amlogic Framebuffer compression */
+	}
+
+	amvdec_write_dos(core, HEVC_SAO_CTRL1, val);
+
+	if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
+		/* no downscale for NV12 */
+		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0000;
+		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
+	}
+
+	val = amvdec_read_dos(core, HEVCD_IPP_AXIIF_CONFIG) & ~0x30;
+	val |= 0xf;
+	amvdec_write_dos(core, HEVCD_IPP_AXIIF_CONFIG, val);
+
+	val = 0;
+	val_2 = amvdec_read_dos(core, HEVC_SAO_CTRL0);
+	val_2 &= (~0x300);
+
+	slice_deblocking_filter_disabled_flag = (misc_flag0 >>
+			SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & 0x1;
+	if ((misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT)) &&
+	    (misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT))) {
+		val |= slice_deblocking_filter_disabled_flag << 2;
+
+		if (!slice_deblocking_filter_disabled_flag) {
+			val |= (param->p.slice_beta_offset_div2 & 0xf) << 3;
+			val |= (param->p.slice_tc_offset_div2 & 0xf) << 7;
+		}
+	} else {
+		val |=
+			((misc_flag0 >>
+			  PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & 0x1) << 2;
+
+		if (((misc_flag0 >> PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) &
+			0x1) == 0) {
+			val |= (param->p.pps_beta_offset_div2 & 0xf) << 3;
+			val |= (param->p.pps_tc_offset_div2 & 0xf) << 7;
+		}
+	}
+	if ((misc_flag0 & (1 << PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)) &&
+	    ((misc_flag0 & (1 << SLICE_SAO_LUMA_FLAG_BIT)) ||
+	   (misc_flag0 & (1 << SLICE_SAO_CHROMA_FLAG_BIT)) ||
+	   (!slice_deblocking_filter_disabled_flag))) {
+		val |=
+			((misc_flag0 >>
+			  SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
+			 & 0x1)	<< 1;
+		val_2 |=
+			((misc_flag0 >>
+			  SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
+			& 0x1) << 9;
+	} else {
+		val |=
+			((misc_flag0 >>
+			  PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
+			 & 0x1) << 1;
+		val_2 |=
+			((misc_flag0 >>
+			  PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
+			 & 0x1) << 9;
+	}
+
+	amvdec_write_dos(core, HEVC_DBLK_CFG9, val);
+	amvdec_write_dos(core, HEVC_SAO_CTRL0, val_2);
+
+	amvdec_write_dos(core, HEVC_sao_mem_unit, sao_mem_unit);
+	amvdec_write_dos(core, HEVC_SAO_ABV,
+			 hevc->workspace_paddr + SAO_ABV_OFFSET);
+	amvdec_write_dos(core, HEVC_sao_vb_size, sao_vb_size);
+	amvdec_write_dos(core, HEVC_SAO_VB,
+			 hevc->workspace_paddr + SAO_VB_OFFSET);
+}
+
+static dma_addr_t codec_hevc_get_frame_mv_paddr(struct codec_hevc *hevc,
+						struct hevc_frame *frame)
+{
+	return hevc->workspace_paddr + MPRED_MV_OFFSET +
+		(frame->vbuf->vb2_buf.index * MPRED_MV_BUF_SIZE);
+}
+
+static void
+codec_hevc_set_mpred_ctrl(struct amvdec_core *core, struct codec_hevc *hevc)
+{
+	union rpm_param *param = &hevc->rpm_param;
+	u32 slice_type = param->p.slice_type;
+	u32 lcu_size_log2 = ilog2(hevc->lcu_size);
+	u32 val;
+
+	val = slice_type |
+	      MPRED_CTRL0_ABOVE_EN |
+	      MPRED_CTRL0_MV_WR_EN |
+	      MPRED_CTRL0_BUF_LINEAR |
+	      (lcu_size_log2 << 16) |
+	      (3 << 20) | /* cu_size_log2 */
+	      (param->p.log2_parallel_merge_level << 24);
+
+	if (slice_type != I_SLICE)
+		val |= MPRED_CTRL0_MV_RD_EN;
+
+	if (param->p.collocated_from_l0_flag)
+		val |= MPRED_CTRL0_COL_FROM_L0;
+
+	if (param->p.slice_temporal_mvp_enable_flag)
+		val |= MPRED_CTRL0_TMVP;
+
+	if (hevc->ldc_flag)
+		val |= MPRED_CTRL0_LDC;
+
+	if (param->p.dependent_slice_segment_flag)
+		val |= MPRED_CTRL0_NEW_SLI_SEG;
+
+	if (param->p.slice_segment_address == 0)
+		val |= MPRED_CTRL0_NEW_PIC |
+		       MPRED_CTRL0_NEW_TILE;
+
+	amvdec_write_dos(core, HEVC_MPRED_CTRL0, val);
+
+	val = (5 - param->p.five_minus_max_num_merge_cand) |
+	      (AMVP_MAX_NUM_CANDS << 4) |
+	      (AMVP_MAX_NUM_CANDS_MEM << 8) |
+	      (NUM_CHROMA_MODE << 12) |
+	      (DM_CHROMA_IDX << 16);
+	amvdec_write_dos(core, HEVC_MPRED_CTRL1, val);
+}
+
+static void codec_hevc_set_mpred_mv(struct amvdec_core *core,
+				    struct codec_hevc *hevc,
+				    struct hevc_frame *frame,
+				    struct hevc_frame *col_frame)
+{
+	union rpm_param *param = &hevc->rpm_param;
+	u32 lcu_size_log2 = ilog2(hevc->lcu_size);
+	u32 mv_mem_unit = lcu_size_log2 == 6 ? 0x200 :
+			  lcu_size_log2 == 5 ? 0x80 : 0x20;
+	dma_addr_t col_mv_rd_start_addr, col_mv_rd_ptr, col_mv_rd_end_addr;
+	dma_addr_t mpred_mv_wr_ptr;
+
+	amvdec_read_dos(core, HEVC_MPRED_CURR_LCU);
+
+	col_mv_rd_start_addr = codec_hevc_get_frame_mv_paddr(hevc, col_frame);
+	mpred_mv_wr_ptr = codec_hevc_get_frame_mv_paddr(hevc, frame) +
+			  (hevc->slice_addr * mv_mem_unit);
+	col_mv_rd_ptr = col_mv_rd_start_addr +
+			(hevc->slice_addr * mv_mem_unit);
+	col_mv_rd_end_addr = col_mv_rd_start_addr +
+			     (hevc->lcu_total * mv_mem_unit);
+
+	amvdec_write_dos(core, HEVC_MPRED_MV_WR_START_ADDR,
+			 codec_hevc_get_frame_mv_paddr(hevc, frame));
+	amvdec_write_dos(core, HEVC_MPRED_MV_RD_START_ADDR,
+			 col_mv_rd_start_addr);
+
+	if (param->p.slice_segment_address == 0) {
+		amvdec_write_dos(core, HEVC_MPRED_ABV_START_ADDR,
+				 hevc->workspace_paddr + MPRED_ABV_OFFSET);
+		amvdec_write_dos(core, HEVC_MPRED_MV_WPTR, mpred_mv_wr_ptr);
+		amvdec_write_dos(core, HEVC_MPRED_MV_RPTR,
+				 col_mv_rd_start_addr);
+	} else {
+		amvdec_write_dos(core, HEVC_MPRED_MV_RPTR, col_mv_rd_ptr);
+	}
+
+	amvdec_write_dos(core, HEVC_MPRED_MV_RD_END_ADDR, col_mv_rd_end_addr);
+}
+
+/* Update motion prediction with the current slice */
+static void codec_hevc_set_mpred(struct amvdec_session *sess,
+				 struct hevc_frame *frame,
+				 struct hevc_frame *col_frame)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc = sess->priv;
+	u32 *ref_num = frame->ref_num;
+	u32 *ref_poc_l0 = frame->ref_poc_list[0][frame->cur_slice_idx];
+	u32 *ref_poc_l1 = frame->ref_poc_list[1][frame->cur_slice_idx];
+	u32 val;
+	int i;
+
+	codec_hevc_set_mpred_ctrl(core, hevc);
+	codec_hevc_set_mpred_mv(core, hevc, frame, col_frame);
+
+	amvdec_write_dos(core, HEVC_MPRED_PIC_SIZE,
+			 hevc->width | (hevc->height << 16));
+
+	val = ((hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16);
+	amvdec_write_dos(core, HEVC_MPRED_PIC_SIZE_LCU, val);
+
+	amvdec_write_dos(core, HEVC_MPRED_REF_NUM,
+			 (ref_num[1] << 8) | ref_num[0]);
+	amvdec_write_dos(core, HEVC_MPRED_REF_EN_L0, (1 << ref_num[0]) - 1);
+	amvdec_write_dos(core, HEVC_MPRED_REF_EN_L1, (1 << ref_num[1]) - 1);
+
+	amvdec_write_dos(core, HEVC_MPRED_CUR_POC, hevc->curr_poc);
+	amvdec_write_dos(core, HEVC_MPRED_COL_POC, hevc->col_poc);
+
+	for (i = 0; i < MAX_REF_ACTIVE; ++i) {
+		amvdec_write_dos(core, HEVC_MPRED_L0_REF00_POC + i * 4,
+				 ref_poc_l0[i]);
+		amvdec_write_dos(core, HEVC_MPRED_L1_REF00_POC + i * 4,
+				 ref_poc_l1[i]);
+	}
+}
+
+/*  motion compensation reference cache controller */
+static void codec_hevc_set_mcrcc(struct amvdec_session *sess)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc = sess->priv;
+	u32 val, val_2;
+	int l0_cnt = 0;
+	int l1_cnt = 0x7fff;
+
+	if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
+		l0_cnt = hevc->cur_frame->ref_num[0];
+		l1_cnt = hevc->cur_frame->ref_num[1];
+	}
+
+	if (hevc->cur_frame->cur_slice_type == I_SLICE) {
+		amvdec_write_dos(core, HEVCD_MCRCC_CTL1, 0);
+		return;
+	}
+
+	if (hevc->cur_frame->cur_slice_type == P_SLICE) {
+		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+				 BIT(1));
+		val = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+		val &= 0xffff;
+		val |= (val << 16);
+		amvdec_write_dos(core, HEVCD_MCRCC_CTL2, val);
+
+		if (l0_cnt == 1) {
+			amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val);
+		} else {
+			val = amvdec_read_dos(core,
+					      HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+			val &= 0xffff;
+			val |= (val << 16);
+			amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val);
+		}
+	} else { /* B_SLICE */
+		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 0);
+		val = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+		val &= 0xffff;
+		val |= (val << 16);
+		amvdec_write_dos(core, HEVCD_MCRCC_CTL2, val);
+
+		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+				 BIT(12) | BIT(1));
+		val_2 = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+		val_2 &= 0xffff;
+		val_2 |= (val_2 << 16);
+		if (val == val_2 && l1_cnt > 1) {
+			val_2 = amvdec_read_dos(core,
+						HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+			val_2 &= 0xffff;
+			val_2 |= (val_2 << 16);
+		}
+		amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val);
+	}
+
+	/* enable mcrcc progressive-mode */
+	amvdec_write_dos(core, HEVCD_MCRCC_CTL1, 0xff0);
+}
+
+static void codec_hevc_set_ref_list(struct amvdec_session *sess,
+				    u32 ref_num, u32 *ref_poc_list)
+{
+	struct codec_hevc *hevc = sess->priv;
+	struct hevc_frame *ref_frame;
+	struct amvdec_core *core = sess->core;
+	int i;
+	u32 buf_id_y;
+	u32 buf_id_uv;
+
+	for (i = 0; i < ref_num; i++) {
+		ref_frame = codec_hevc_get_frame_by_poc(hevc, ref_poc_list[i]);
+
+		if (!ref_frame) {
+			dev_warn(core->dev, "Couldn't find ref. frame %u\n",
+				 ref_poc_list[i]);
+			continue;
+		}
+
+		if (codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
+			buf_id_y = ref_frame->vbuf->vb2_buf.index;
+			buf_id_uv = buf_id_y;
+		} else {
+			buf_id_y = ref_frame->vbuf->vb2_buf.index * 2;
+			buf_id_uv = buf_id_y + 1;
+		}
+
+		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
+				 (buf_id_uv << 16) |
+				 (buf_id_uv << 8) |
+				 buf_id_y);
+	}
+}
+
+static void codec_hevc_set_mc(struct amvdec_session *sess,
+			      struct hevc_frame *frame)
+{
+	struct amvdec_core *core = sess->core;
+
+	if (frame->cur_slice_type == I_SLICE)
+		return;
+
+	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
+	codec_hevc_set_ref_list(sess, frame->ref_num[0],
+				frame->ref_poc_list[0][frame->cur_slice_idx]);
+
+	if (frame->cur_slice_type == P_SLICE)
+		return;
+
+	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+			 BIT(12) | BIT(0));
+	codec_hevc_set_ref_list(sess, frame->ref_num[1],
+				frame->ref_poc_list[1][frame->cur_slice_idx]);
+}
+
+static void codec_hevc_update_col_frame(struct codec_hevc *hevc)
+{
+	struct hevc_frame *cur_frame = hevc->cur_frame;
+	union rpm_param *param = &hevc->rpm_param;
+	u32 list_no = 0;
+	u32 col_ref = param->p.collocated_ref_idx;
+	u32 col_from_l0 = param->p.collocated_from_l0_flag;
+	u32 cur_slice_idx = cur_frame->cur_slice_idx;
+
+	if (cur_frame->cur_slice_type == B_SLICE)
+		list_no = 1 - col_from_l0;
+
+	if (col_ref >= cur_frame->ref_num[list_no])
+		hevc->col_poc = INVALID_POC;
+	else
+		hevc->col_poc = cur_frame->ref_poc_list[list_no]
+						       [cur_slice_idx]
+						       [col_ref];
+
+	if (cur_frame->cur_slice_type == I_SLICE)
+		goto end;
+
+	if (hevc->col_poc != INVALID_POC)
+		hevc->col_frame = codec_hevc_get_frame_by_poc(hevc,
+							      hevc->col_poc);
+	else
+		hevc->col_frame = hevc->cur_frame;
+
+end:
+	if (!hevc->col_frame)
+		hevc->col_frame = hevc->cur_frame;
+}
+
+static void codec_hevc_update_pocs(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	union rpm_param *param = &hevc->rpm_param;
+	u32 nal_unit_type = param->p.m_nalUnitType;
+	u32 temporal_id = param->p.m_temporalId & 0x7;
+	int max_poc_lsb =
+		1 << (param->p.log2_max_pic_order_cnt_lsb_minus4 + 4);
+	int prev_poc_lsb;
+	int prev_poc_msb;
+	int poc_msb;
+	int poc_lsb = param->p.POClsb;
+
+	if (nal_unit_type == NAL_UNIT_CODED_SLICE_IDR ||
+	    nal_unit_type == NAL_UNIT_CODED_SLICE_IDR_N_LP) {
+		hevc->curr_poc = 0;
+		if ((temporal_id - 1) == 0)
+			hevc->prev_tid0_poc = hevc->curr_poc;
+
+		return;
+	}
+
+	prev_poc_lsb = hevc->prev_tid0_poc % max_poc_lsb;
+	prev_poc_msb = hevc->prev_tid0_poc - prev_poc_lsb;
+
+	if ((poc_lsb < prev_poc_lsb) &&
+	    ((prev_poc_lsb - poc_lsb) >= (max_poc_lsb / 2)))
+		poc_msb = prev_poc_msb + max_poc_lsb;
+	else if ((poc_lsb > prev_poc_lsb) &&
+		 ((poc_lsb - prev_poc_lsb) > (max_poc_lsb / 2)))
+		poc_msb = prev_poc_msb - max_poc_lsb;
+	else
+		poc_msb = prev_poc_msb;
+
+	if (nal_unit_type == NAL_UNIT_CODED_SLICE_BLA   ||
+	    nal_unit_type == NAL_UNIT_CODED_SLICE_BLANT ||
+	    nal_unit_type == NAL_UNIT_CODED_SLICE_BLA_N_LP)
+		poc_msb = 0;
+
+	hevc->curr_poc = (poc_msb + poc_lsb);
+	if ((temporal_id - 1) == 0)
+		hevc->prev_tid0_poc = hevc->curr_poc;
+}
+
+static void codec_hevc_process_segment_header(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	union rpm_param *param = &hevc->rpm_param;
+
+	if (param->p.first_slice_segment_in_pic_flag == 0) {
+		hevc->slice_segment_addr = param->p.slice_segment_address;
+		if (!param->p.dependent_slice_segment_flag)
+			hevc->slice_addr = hevc->slice_segment_addr;
+	} else {
+		hevc->slice_segment_addr = 0;
+		hevc->slice_addr = 0;
+	}
+
+	codec_hevc_update_pocs(sess);
+}
+
+static int codec_hevc_process_segment(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	struct amvdec_core *core = sess->core;
+	union rpm_param *param = &hevc->rpm_param;
+	u32 slice_segment_address = param->p.slice_segment_address;
+
+	/* First slice: new frame */
+	if (slice_segment_address == 0) {
+		codec_hevc_update_referenced(hevc);
+		codec_hevc_show_frames(sess);
+
+		hevc->cur_frame = codec_hevc_prepare_new_frame(sess);
+		if (!hevc->cur_frame)
+			return -1;
+	} else {
+		hevc->cur_frame->cur_slice_idx++;
+	}
+
+	codec_hevc_update_frame_refs(sess, hevc->cur_frame);
+	codec_hevc_update_col_frame(hevc);
+	codec_hevc_update_ldc_flag(hevc);
+	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
+			       hevc->is_10bit))
+		codec_hevc_fill_mmu_map(sess, &hevc->common,
+					&hevc->cur_frame->vbuf->vb2_buf,
+					hevc->is_10bit);
+	codec_hevc_set_mc(sess, hevc->cur_frame);
+	codec_hevc_set_mcrcc(sess);
+	codec_hevc_set_mpred(sess, hevc->cur_frame, hevc->col_frame);
+	codec_hevc_set_sao(sess, hevc->cur_frame);
+
+	amvdec_write_dos_bits(core, HEVC_WAIT_FLAG, BIT(1));
+	amvdec_write_dos(core, HEVC_DEC_STATUS_REG,
+			 HEVC_CODED_SLICE_SEGMENT_DAT);
+
+	/* Interrupt the firmware's processor */
+	amvdec_write_dos(core, HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
+
+	return 0;
+}
+
+static int codec_hevc_process_rpm(struct codec_hevc *hevc)
+{
+	union rpm_param *param = &hevc->rpm_param;
+	int src_changed = 0;
+	u32 dst_width, dst_height;
+	u32 lcu_size;
+	u32 is_10bit = 0;
+
+	if (param->p.slice_segment_address	||
+	    !param->p.pic_width_in_luma_samples	||
+	    !param->p.pic_height_in_luma_samples)
+		return 0;
+
+	if (param->p.bit_depth)
+		is_10bit = 1;
+
+	hevc->width = param->p.pic_width_in_luma_samples;
+	hevc->height = param->p.pic_height_in_luma_samples;
+	dst_width = hevc->width;
+	dst_height = hevc->height;
+
+	lcu_size = 1 << (param->p.log2_min_coding_block_size_minus3 +
+		   3 + param->p.log2_diff_max_min_coding_block_size);
+
+	hevc->lcu_x_num = (hevc->width + lcu_size - 1) / lcu_size;
+	hevc->lcu_y_num = (hevc->height + lcu_size - 1) / lcu_size;
+	hevc->lcu_total = hevc->lcu_x_num * hevc->lcu_y_num;
+
+	if (param->p.conformance_window_flag) {
+		u32 sub_width = 1, sub_height = 1;
+
+		switch (param->p.chroma_format_idc) {
+		case 1:
+			sub_height = 2;
+			fallthrough;
+		case 2:
+			sub_width = 2;
+			break;
+		}
+
+		dst_width -= sub_width *
+			     (param->p.conf_win_left_offset +
+			      param->p.conf_win_right_offset);
+		dst_height -= sub_height *
+			      (param->p.conf_win_top_offset +
+			       param->p.conf_win_bottom_offset);
+	}
+
+	if (dst_width != hevc->dst_width ||
+	    dst_height != hevc->dst_height ||
+	    lcu_size != hevc->lcu_size ||
+	    is_10bit != hevc->is_10bit)
+		src_changed = 1;
+
+	hevc->dst_width = dst_width;
+	hevc->dst_height = dst_height;
+	hevc->lcu_size = lcu_size;
+	hevc->is_10bit = is_10bit;
+
+	return src_changed;
+}
+
+/*
+ * The RPM section within the workspace contains
+ * many information regarding the parsed bitstream
+ */
+static void codec_hevc_fetch_rpm(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	u16 *rpm_vaddr = hevc->workspace_vaddr + RPM_OFFSET;
+	int i, j;
+
+	for (i = 0; i < RPM_SIZE; i += 4) {
+		for (j = 0; j < 4; j++)
+			hevc->rpm_param.l.data[i + j] =
+				rpm_vaddr[i + 3 - j];
+	}
+}
+
+static void codec_hevc_resume(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+
+	if (codec_hevc_setup_buffers(sess, &hevc->common, hevc->is_10bit)) {
+		amvdec_abort(sess);
+		return;
+	}
+
+	codec_hevc_setup_decode_head(sess, hevc->is_10bit);
+	codec_hevc_process_segment_header(sess);
+	if (codec_hevc_process_segment(sess))
+		amvdec_abort(sess);
+}
+
+static irqreturn_t codec_hevc_threaded_isr(struct amvdec_session *sess)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc = sess->priv;
+	u32 dec_status = amvdec_read_dos(core, HEVC_DEC_STATUS_REG);
+
+	if (!hevc)
+		return IRQ_HANDLED;
+
+	mutex_lock(&hevc->lock);
+	if (dec_status != HEVC_SLICE_SEGMENT_DONE) {
+		dev_err(core->dev_dec, "Unrecognized dec_status: %08X\n",
+			dec_status);
+		amvdec_abort(sess);
+		goto unlock;
+	}
+
+	sess->keyframe_found = 1;
+	codec_hevc_fetch_rpm(sess);
+	if (codec_hevc_process_rpm(hevc)) {
+		amvdec_src_change(sess, hevc->dst_width, hevc->dst_height, 16,
+				  hevc->is_10bit ? 10 : 8);
+		goto unlock;
+	}
+
+	codec_hevc_process_segment_header(sess);
+	if (codec_hevc_process_segment(sess))
+		amvdec_abort(sess);
+
+unlock:
+	mutex_unlock(&hevc->lock);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t codec_hevc_isr(struct amvdec_session *sess)
+{
+	return IRQ_WAKE_THREAD;
+}
+
+struct amvdec_codec_ops codec_hevc_ops = {
+	.start = codec_hevc_start,
+	.stop = codec_hevc_stop,
+	.isr = codec_hevc_isr,
+	.threaded_isr = codec_hevc_threaded_isr,
+	.num_pending_bufs = codec_hevc_num_pending_bufs,
+	.drain = codec_hevc_flush_output,
+	.resume = codec_hevc_resume,
+};
diff --git a/drivers/staging/media/meson/vdec/codec_hevc.h b/drivers/staging/media/meson/vdec/codec_hevc.h
new file mode 100644
index 000000000000..f2f9b2464df1
--- /dev/null
+++ b/drivers/staging/media/meson/vdec/codec_hevc.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Maxime Jourdan <maxi.jourdan@wanadoo.fr>
+ */
+
+#ifndef __MESON_VDEC_CODEC_HEVC_H_
+#define __MESON_VDEC_CODEC_HEVC_H_
+
+#include "vdec.h"
+
+extern struct amvdec_codec_ops codec_hevc_ops;
+
+#endif
diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
index 3cd29ab4f979..6988348ce714 100644
--- a/drivers/staging/media/meson/vdec/esparser.c
+++ b/drivers/staging/media/meson/vdec/esparser.c
@@ -310,7 +310,8 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
 	 * they could pause when there is no capture buffer available and
 	 * resume on this notification.
 	 */
-	if (sess->fmt_out->pixfmt == V4L2_PIX_FMT_VP9) {
+	if (sess->fmt_out->pixfmt == V4L2_PIX_FMT_VP9 ||
+	    sess->fmt_out->pixfmt == V4L2_PIX_FMT_HEVC) {
 		if (codec_ops->num_pending_bufs)
 			num_dst_bufs = codec_ops->num_pending_bufs(sess);
 
diff --git a/drivers/staging/media/meson/vdec/hevc_regs.h b/drivers/staging/media/meson/vdec/hevc_regs.h
index 0392f41a1eed..e7eabdd2b119 100644
--- a/drivers/staging/media/meson/vdec/hevc_regs.h
+++ b/drivers/staging/media/meson/vdec/hevc_regs.h
@@ -205,6 +205,7 @@
 #define HEVC_CM_HEADER_START_ADDR 0xd8a0
 #define HEVC_CM_HEADER_LENGTH 0xd8a4
 #define HEVC_CM_HEADER_OFFSET 0xd8ac
+#define HEVC_SAO_CTRL9 0xd8b4
 #define HEVC_SAO_MMU_VH0_ADDR 0xd8e8
 #define HEVC_SAO_MMU_VH1_ADDR 0xd8ec
 
diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c
index 88c9d72e1c83..ea2aa0e8cf0b 100644
--- a/drivers/staging/media/meson/vdec/vdec_platform.c
+++ b/drivers/staging/media/meson/vdec/vdec_platform.c
@@ -11,10 +11,23 @@
 #include "vdec_hevc.h"
 #include "codec_mpeg12.h"
 #include "codec_h264.h"
+#include "codec_hevc.h"
 #include "codec_vp9.h"
 
 static const struct amvdec_format vdec_formats_gxbb[] = {
 	{
+		.pixfmt = V4L2_PIX_FMT_HEVC,
+		.min_buffers = 4,
+		.max_buffers = 24,
+		.max_width = 3840,
+		.max_height = 2160,
+		.vdec_ops = &vdec_hevc_ops,
+		.codec_ops = &codec_hevc_ops,
+		.firmware_path = "meson/vdec/gxl_hevc.bin",
+		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+		.flags = V4L2_FMT_FLAG_COMPRESSED |
+			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+	}, {
 		.pixfmt = V4L2_PIX_FMT_H264,
 		.min_buffers = 2,
 		.max_buffers = 24,
@@ -64,6 +77,18 @@ static const struct amvdec_format vdec_formats_gxl[] = {
 		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
 		.flags = V4L2_FMT_FLAG_COMPRESSED |
 			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+	}, {
+		.pixfmt = V4L2_PIX_FMT_HEVC,
+		.min_buffers = 4,
+		.max_buffers = 24,
+		.max_width = 3840,
+		.max_height = 2160,
+		.vdec_ops = &vdec_hevc_ops,
+		.codec_ops = &codec_hevc_ops,
+		.firmware_path = "meson/vdec/gxl_hevc.bin",
+		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+		.flags = V4L2_FMT_FLAG_COMPRESSED |
+			 V4L2_FMT_FLAG_DYN_RESOLUTION,
 	}, {
 		.pixfmt = V4L2_PIX_FMT_H264,
 		.min_buffers = 2,
@@ -114,6 +139,18 @@ static const struct amvdec_format vdec_formats_gxm[] = {
 		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
 		.flags = V4L2_FMT_FLAG_COMPRESSED |
 			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+	}, {
+		.pixfmt = V4L2_PIX_FMT_HEVC,
+		.min_buffers = 4,
+		.max_buffers = 24,
+		.max_width = 3840,
+		.max_height = 2160,
+		.vdec_ops = &vdec_hevc_ops,
+		.codec_ops = &codec_hevc_ops,
+		.firmware_path = "meson/vdec/gxl_hevc.bin",
+		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+		.flags = V4L2_FMT_FLAG_COMPRESSED |
+			 V4L2_FMT_FLAG_DYN_RESOLUTION,
 	}, {
 		.pixfmt = V4L2_PIX_FMT_H264,
 		.min_buffers = 2,
-- 
2.34.1

[PATCH v2 2/2] media: meson: vdec: add HEVC decode codec

[Christian Hewitt]

From: Maxime Jourdan <mjourdan@baylibre.com>

Add initial HEVC codec for the Amlogic GXBB/GXL/GXM SoCs using
the common "HEVC" decoder driver.

Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
[codec alignment to upstream changes and frame handling improvements]
Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
 drivers/staging/media/meson/vdec/Makefile     |    2 +-
 drivers/staging/media/meson/vdec/codec_hevc.c | 1462 +++++++++++++++++
 drivers/staging/media/meson/vdec/codec_hevc.h |   13 +
 drivers/staging/media/meson/vdec/esparser.c   |    3 +-
 drivers/staging/media/meson/vdec/hevc_regs.h  |    1 +
 .../staging/media/meson/vdec/vdec_platform.c  |   37 +
 6 files changed, 1516 insertions(+), 2 deletions(-)
 create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.c
 create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.h

diff --git a/drivers/staging/media/meson/vdec/Makefile b/drivers/staging/media/meson/vdec/Makefile
index 6e726af84ac9..16f848e456b9 100644
--- a/drivers/staging/media/meson/vdec/Makefile
+++ b/drivers/staging/media/meson/vdec/Makefile
@@ -3,6 +3,6 @@
 
 meson-vdec-objs = esparser.o vdec.o vdec_helpers.o vdec_platform.o
 meson-vdec-objs += vdec_1.o vdec_hevc.o
-meson-vdec-objs += codec_mpeg12.o codec_h264.o codec_hevc_common.o codec_vp9.o
+meson-vdec-objs += codec_mpeg12.o codec_h264.o codec_hevc_common.o codec_vp9.o codec_hevc.o
 
 obj-$(CONFIG_VIDEO_MESON_VDEC) += meson-vdec.o
diff --git a/drivers/staging/media/meson/vdec/codec_hevc.c b/drivers/staging/media/meson/vdec/codec_hevc.c
new file mode 100644
index 000000000000..fcaaa1ad50b8
--- /dev/null
+++ b/drivers/staging/media/meson/vdec/codec_hevc.c
@@ -0,0 +1,1462 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Maxime Jourdan <mjourdan@baylibre.com>
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ */
+
+#include <media/v4l2-mem2mem.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "codec_hevc.h"
+#include "dos_regs.h"
+#include "hevc_regs.h"
+#include "vdec_helpers.h"
+#include "codec_hevc_common.h"
+
+/* HEVC reg mapping */
+#define HEVC_DEC_STATUS_REG	HEVC_ASSIST_SCRATCH_0
+	#define HEVC_ACTION_DONE	0xff
+#define HEVC_RPM_BUFFER		HEVC_ASSIST_SCRATCH_1
+#define HEVC_SHORT_TERM_RPS	HEVC_ASSIST_SCRATCH_2
+#define HEVC_VPS_BUFFER		HEVC_ASSIST_SCRATCH_3
+#define HEVC_SPS_BUFFER		HEVC_ASSIST_SCRATCH_4
+#define HEVC_PPS_BUFFER		HEVC_ASSIST_SCRATCH_5
+#define HEVC_SAO_UP		HEVC_ASSIST_SCRATCH_6
+#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
+#define H265_MMU_MAP_BUFFER	HEVC_ASSIST_SCRATCH_7
+#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
+#define HEVC_sao_mem_unit	HEVC_ASSIST_SCRATCH_9
+#define HEVC_SAO_ABV		HEVC_ASSIST_SCRATCH_A
+#define HEVC_sao_vb_size	HEVC_ASSIST_SCRATCH_B
+#define HEVC_SAO_VB		HEVC_ASSIST_SCRATCH_C
+#define HEVC_SCALELUT		HEVC_ASSIST_SCRATCH_D
+#define HEVC_WAIT_FLAG		HEVC_ASSIST_SCRATCH_E
+#define RPM_CMD_REG		HEVC_ASSIST_SCRATCH_F
+#define LMEM_DUMP_ADR		HEVC_ASSIST_SCRATCH_F
+#define DEBUG_REG1		HEVC_ASSIST_SCRATCH_G
+#define HEVC_DECODE_MODE2	HEVC_ASSIST_SCRATCH_H
+#define NAL_SEARCH_CTL		HEVC_ASSIST_SCRATCH_I
+#define HEVC_DECODE_MODE	HEVC_ASSIST_SCRATCH_J
+	#define DECODE_MODE_SINGLE 0
+#define DECODE_STOP_POS		HEVC_ASSIST_SCRATCH_K
+#define HEVC_AUX_ADR		HEVC_ASSIST_SCRATCH_L
+#define HEVC_AUX_DATA_SIZE	HEVC_ASSIST_SCRATCH_M
+#define HEVC_DECODE_SIZE	HEVC_ASSIST_SCRATCH_N
+
+#define AMRISC_MAIN_REQ		 0x04
+
+/* HEVC Constants */
+#define MAX_REF_PIC_NUM		24
+#define MAX_REF_ACTIVE		16
+#define MAX_TILE_COL_NUM	10
+#define MAX_TILE_ROW_NUM	20
+#define MAX_SLICE_NUM		800
+#define INVALID_POC		0x80000000
+
+/* HEVC Workspace layout */
+#define MPRED_MV_BUF_SIZE 0x120000
+
+#define IPP_SIZE	0x4000
+#define SAO_ABV_SIZE	0x30000
+#define SAO_VB_SIZE	0x30000
+#define SH_TM_RPS_SIZE	0x800
+#define VPS_SIZE	0x800
+#define SPS_SIZE	0x800
+#define PPS_SIZE	0x2000
+#define SAO_UP_SIZE	0x2800
+#define SWAP_BUF_SIZE	0x800
+#define SWAP_BUF2_SIZE	0x800
+#define SCALELUT_SIZE	0x8000
+#define DBLK_PARA_SIZE	0x20000
+#define DBLK_DATA_SIZE	0x80000
+#define DBLK_DATA2_SIZE	0x80000
+#define MMU_VBH_SIZE	0x5000
+#define MPRED_ABV_SIZE	0x8000
+#define MPRED_MV_SIZE	(MPRED_MV_BUF_SIZE * MAX_REF_PIC_NUM)
+#define RPM_BUF_SIZE	0x100
+#define LMEM_SIZE	0xA00
+
+#define IPP_OFFSET       0x00
+#define SAO_ABV_OFFSET   (IPP_OFFSET + IPP_SIZE)
+#define SAO_VB_OFFSET    (SAO_ABV_OFFSET + SAO_ABV_SIZE)
+#define SH_TM_RPS_OFFSET (SAO_VB_OFFSET + SAO_VB_SIZE)
+#define VPS_OFFSET       (SH_TM_RPS_OFFSET + SH_TM_RPS_SIZE)
+#define SPS_OFFSET       (VPS_OFFSET + VPS_SIZE)
+#define PPS_OFFSET       (SPS_OFFSET + SPS_SIZE)
+#define SAO_UP_OFFSET    (PPS_OFFSET + PPS_SIZE)
+#define SWAP_BUF_OFFSET  (SAO_UP_OFFSET + SAO_UP_SIZE)
+#define SWAP_BUF2_OFFSET (SWAP_BUF_OFFSET + SWAP_BUF_SIZE)
+#define SCALELUT_OFFSET  (SWAP_BUF2_OFFSET + SWAP_BUF2_SIZE)
+#define DBLK_PARA_OFFSET (SCALELUT_OFFSET + SCALELUT_SIZE)
+#define DBLK_DATA_OFFSET (DBLK_PARA_OFFSET + DBLK_PARA_SIZE)
+#define DBLK_DATA2_OFFSET (DBLK_DATA_OFFSET + DBLK_DATA_SIZE)
+#define MMU_VBH_OFFSET   (DBLK_DATA2_OFFSET + DBLK_DATA2_SIZE)
+#define MPRED_ABV_OFFSET (MMU_VBH_OFFSET + MMU_VBH_SIZE)
+#define MPRED_MV_OFFSET  (MPRED_ABV_OFFSET + MPRED_ABV_SIZE)
+#define RPM_OFFSET       (MPRED_MV_OFFSET + MPRED_MV_SIZE)
+#define LMEM_OFFSET      (RPM_OFFSET + RPM_BUF_SIZE)
+
+/* ISR decode status */
+#define HEVC_DEC_IDLE                        0x0
+#define HEVC_NAL_UNIT_VPS                    0x1
+#define HEVC_NAL_UNIT_SPS                    0x2
+#define HEVC_NAL_UNIT_PPS                    0x3
+#define HEVC_NAL_UNIT_CODED_SLICE_SEGMENT    0x4
+#define HEVC_CODED_SLICE_SEGMENT_DAT         0x5
+#define HEVC_SLICE_DECODING                  0x6
+#define HEVC_NAL_UNIT_SEI                    0x7
+#define HEVC_SLICE_SEGMENT_DONE              0x8
+#define HEVC_NAL_SEARCH_DONE                 0x9
+#define HEVC_DECPIC_DATA_DONE                0xa
+#define HEVC_DECPIC_DATA_ERROR               0xb
+#define HEVC_SEI_DAT                         0xc
+#define HEVC_SEI_DAT_DONE                    0xd
+
+/* RPM misc_flag0 */
+#define PCM_LOOP_FILTER_DISABLED_FLAG_BIT		0
+#define PCM_ENABLE_FLAG_BIT				1
+#define LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT	2
+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT	3
+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT	4
+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT		5
+#define DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT		6
+#define SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT	7
+#define SLICE_SAO_LUMA_FLAG_BIT				8
+#define SLICE_SAO_CHROMA_FLAG_BIT			9
+#define SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT 10
+
+/* Constants for HEVC_MPRED_CTRL1 */
+#define AMVP_MAX_NUM_CANDS_MEM	3
+#define AMVP_MAX_NUM_CANDS	2
+#define NUM_CHROMA_MODE		5
+#define DM_CHROMA_IDX		36
+
+/* Buffer sizes */
+#define SIZE_WORKSPACE ALIGN(LMEM_OFFSET + LMEM_SIZE, 64 * SZ_1K)
+#define SIZE_AUX (SZ_1K * 16)
+#define SIZE_FRAME_MMU (0x1200 * 4)
+#define RPM_SIZE 0x80
+#define RPS_USED_BIT 14
+
+/* Data received from the HW in this form, do not rearrange */
+union rpm_param {
+	struct {
+		u16 data[RPM_SIZE];
+	} l;
+	struct {
+		u16 CUR_RPS[MAX_REF_ACTIVE];
+		u16 num_ref_idx_l0_active;
+		u16 num_ref_idx_l1_active;
+		u16 slice_type;
+		u16 slice_temporal_mvp_enable_flag;
+		u16 dependent_slice_segment_flag;
+		u16 slice_segment_address;
+		u16 num_title_rows_minus1;
+		u16 pic_width_in_luma_samples;
+		u16 pic_height_in_luma_samples;
+		u16 log2_min_coding_block_size_minus3;
+		u16 log2_diff_max_min_coding_block_size;
+		u16 log2_max_pic_order_cnt_lsb_minus4;
+		u16 POClsb;
+		u16 collocated_from_l0_flag;
+		u16 collocated_ref_idx;
+		u16 log2_parallel_merge_level;
+		u16 five_minus_max_num_merge_cand;
+		u16 sps_num_reorder_pics_0;
+		u16 modification_flag;
+		u16 tiles_flags;
+		u16 num_tile_columns_minus1;
+		u16 num_tile_rows_minus1;
+		u16 tile_width[8];
+		u16 tile_height[8];
+		u16 misc_flag0;
+		u16 pps_beta_offset_div2;
+		u16 pps_tc_offset_div2;
+		u16 slice_beta_offset_div2;
+		u16 slice_tc_offset_div2;
+		u16 pps_cb_qp_offset;
+		u16 pps_cr_qp_offset;
+		u16 first_slice_segment_in_pic_flag;
+		u16 m_temporalId;
+		u16 m_nalUnitType;
+		u16 vui_num_units_in_tick_hi;
+		u16 vui_num_units_in_tick_lo;
+		u16 vui_time_scale_hi;
+		u16 vui_time_scale_lo;
+		u16 bit_depth;
+		u16 profile_etc;
+		u16 sei_frame_field_info;
+		u16 video_signal_type;
+		u16 modification_list[0x20];
+		u16 conformance_window_flag;
+		u16 conf_win_left_offset;
+		u16 conf_win_right_offset;
+		u16 conf_win_top_offset;
+		u16 conf_win_bottom_offset;
+		u16 chroma_format_idc;
+		u16 color_description;
+		u16 aspect_ratio_idc;
+		u16 sar_width;
+		u16 sar_height;
+	} p;
+};
+
+enum nal_unit_type {
+	NAL_UNIT_CODED_SLICE_BLA	= 16,
+	NAL_UNIT_CODED_SLICE_BLANT	= 17,
+	NAL_UNIT_CODED_SLICE_BLA_N_LP	= 18,
+	NAL_UNIT_CODED_SLICE_IDR	= 19,
+	NAL_UNIT_CODED_SLICE_IDR_N_LP	= 20,
+};
+
+enum slice_type {
+	B_SLICE = 0,
+	P_SLICE = 1,
+	I_SLICE = 2,
+};
+
+/* A frame being decoded */
+struct hevc_frame {
+	struct list_head list;
+	struct vb2_v4l2_buffer *vbuf;
+	u32 offset;
+	u32 poc;
+
+	int referenced;
+	int show;
+	u32 num_reorder_pic;
+
+	u32 cur_slice_idx;
+	u32 cur_slice_type;
+
+	/* 2 lists (L0/L1) ; 800 slices ; 16 refs */
+	u32 ref_poc_list[2][MAX_SLICE_NUM][MAX_REF_ACTIVE];
+	u32 ref_num[2];
+};
+
+struct codec_hevc {
+	/* Protect the data structure */
+	struct mutex lock;
+
+	/* Common part of the HEVC decoder */
+	struct codec_hevc_common common;
+
+	/* Buffer for the HEVC Workspace */
+	void      *workspace_vaddr;
+	dma_addr_t workspace_paddr;
+
+	/* AUX buffer */
+	void      *aux_vaddr;
+	dma_addr_t aux_paddr;
+
+	/* Contains many information parsed from the bitstream */
+	union rpm_param rpm_param;
+
+	/* Information computed from the RPM */
+	u32 lcu_size; // Largest Coding Unit
+	u32 lcu_x_num;
+	u32 lcu_y_num;
+	u32 lcu_total;
+
+	/* Current Frame being handled */
+	struct hevc_frame *cur_frame;
+	u32 curr_poc;
+	/* Collocated Reference Picture */
+	struct hevc_frame *col_frame;
+	u32 col_poc;
+
+	/* All ref frames used by the HW at a given time */
+	struct list_head ref_frames_list;
+	u32 frames_num;
+
+	/* Coded resolution reported by the hardware */
+	u32 width, height;
+	/* Resolution minus the conformance window offsets */
+	u32 dst_width, dst_height;
+
+	u32 prev_tid0_poc;
+	u32 slice_segment_addr;
+	u32 slice_addr;
+	u32 ldc_flag;
+
+	/* Whether we detected the bitstream as 10-bit */
+	int is_10bit;
+};
+
+static u32 codec_hevc_num_pending_bufs(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc;
+	u32 ret;
+
+	hevc = sess->priv;
+	if (!hevc)
+		return 0;
+
+	mutex_lock(&hevc->lock);
+	ret = hevc->frames_num;
+	mutex_unlock(&hevc->lock);
+
+	return ret;
+}
+
+/* Update the L0 and L1 reference lists for a given frame */
+static void codec_hevc_update_frame_refs(struct amvdec_session *sess,
+					 struct hevc_frame *frame)
+{
+	struct codec_hevc *hevc = sess->priv;
+	union rpm_param *params = &hevc->rpm_param;
+	int num_ref_idx_l0_active =
+		(params->p.num_ref_idx_l0_active > MAX_REF_ACTIVE) ?
+		MAX_REF_ACTIVE : params->p.num_ref_idx_l0_active;
+	int num_ref_idx_l1_active =
+		(params->p.num_ref_idx_l1_active > MAX_REF_ACTIVE) ?
+		MAX_REF_ACTIVE : params->p.num_ref_idx_l1_active;
+	int ref_picset0[MAX_REF_ACTIVE] = { 0 };
+	int ref_picset1[MAX_REF_ACTIVE] = { 0 };
+	u16 *mod_list = params->p.modification_list;
+	int num_neg = 0;
+	int num_pos = 0;
+	int total_num;
+	int i;
+
+	for (i = 0; i < MAX_REF_ACTIVE; i++) {
+		frame->ref_poc_list[0][frame->cur_slice_idx][i] = 0;
+		frame->ref_poc_list[1][frame->cur_slice_idx][i] = 0;
+	}
+
+	for (i = 0; i < MAX_REF_ACTIVE; i++) {
+		u16 cur_rps = params->p.CUR_RPS[i];
+		int delt = cur_rps & ((1 << (RPS_USED_BIT - 1)) - 1);
+
+		if (cur_rps & 0x8000)
+			break;
+
+		if (!((cur_rps >> RPS_USED_BIT) & 1))
+			continue;
+
+		if ((cur_rps >> (RPS_USED_BIT - 1)) & 1) {
+			ref_picset0[num_neg] =
+			       frame->poc - ((1 << (RPS_USED_BIT - 1)) - delt);
+			num_neg++;
+		} else {
+			ref_picset1[num_pos] = frame->poc + delt;
+			num_pos++;
+		}
+	}
+
+	total_num = num_neg + num_pos;
+
+	if (total_num <= 0)
+		goto end;
+
+	for (i = 0; i < num_ref_idx_l0_active; i++) {
+		int cidx;
+
+		if (params->p.modification_flag & 0x1)
+			cidx = mod_list[i];
+		else
+			cidx = i % total_num;
+
+		frame->ref_poc_list[0][frame->cur_slice_idx][i] =
+			cidx >= num_neg ? ref_picset1[cidx - num_neg] :
+			ref_picset0[cidx];
+	}
+
+	if (params->p.slice_type != B_SLICE)
+		goto end;
+
+	if (params->p.modification_flag & 0x2) {
+		for (i = 0; i < num_ref_idx_l1_active; i++) {
+			int cidx;
+
+			if (params->p.modification_flag & 0x1)
+				cidx = mod_list[num_ref_idx_l0_active + i];
+			else
+				cidx = mod_list[i];
+
+			frame->ref_poc_list[1][frame->cur_slice_idx][i] =
+				(cidx >= num_pos) ? ref_picset0[cidx - num_pos]
+				: ref_picset1[cidx];
+		}
+	} else {
+		for (i = 0; i < num_ref_idx_l1_active; i++) {
+			int cidx = i % total_num;
+
+			frame->ref_poc_list[1][frame->cur_slice_idx][i] =
+				cidx >= num_pos ? ref_picset0[cidx - num_pos] :
+				ref_picset1[cidx];
+		}
+	}
+
+end:
+	frame->ref_num[0] = num_ref_idx_l0_active;
+	frame->ref_num[1] = num_ref_idx_l1_active;
+
+	dev_dbg(sess->core->dev,
+		"Frame %u; slice %u; slice_type %u; num_l0 %u; num_l1 %u\n",
+		frame->poc, frame->cur_slice_idx, params->p.slice_type,
+		frame->ref_num[0], frame->ref_num[1]);
+}
+
+static void codec_hevc_update_ldc_flag(struct codec_hevc *hevc)
+{
+	struct hevc_frame *frame = hevc->cur_frame;
+	u32 slice_type = frame->cur_slice_type;
+	u32 slice_idx = frame->cur_slice_idx;
+	int i;
+
+	hevc->ldc_flag = 0;
+
+	if (slice_type == I_SLICE)
+		return;
+
+	hevc->ldc_flag = 1;
+	for (i = 0; (i < frame->ref_num[0]) && hevc->ldc_flag; i++) {
+		if (frame->ref_poc_list[0][slice_idx][i] > frame->poc) {
+			hevc->ldc_flag = 0;
+			break;
+		}
+	}
+
+	if (slice_type == P_SLICE)
+		return;
+
+	for (i = 0; (i < frame->ref_num[1]) && hevc->ldc_flag; i++) {
+		if (frame->ref_poc_list[1][slice_idx][i] > frame->poc) {
+			hevc->ldc_flag = 0;
+			break;
+		}
+	}
+}
+
+/* Tag "old" frames that are no longer referenced */
+static void codec_hevc_update_referenced(struct codec_hevc *hevc)
+{
+	union rpm_param *param = &hevc->rpm_param;
+	struct hevc_frame *frame;
+	int i;
+	u32 curr_poc = hevc->curr_poc;
+
+	list_for_each_entry(frame, &hevc->ref_frames_list, list) {
+		int is_referenced = 0;
+		u32 poc_tmp;
+
+		if (!frame->referenced)
+			continue;
+
+		for (i = 0; i < MAX_REF_ACTIVE; i++) {
+			int delt;
+
+			if (param->p.CUR_RPS[i] & 0x8000)
+				break;
+
+			delt = param->p.CUR_RPS[i] &
+			       ((1 << (RPS_USED_BIT - 1)) - 1);
+			if (param->p.CUR_RPS[i] & (1 << (RPS_USED_BIT - 1))) {
+				poc_tmp = curr_poc -
+				      ((1 << (RPS_USED_BIT - 1)) - delt);
+			} else {
+				poc_tmp = curr_poc + delt;
+			}
+
+			if (poc_tmp == frame->poc) {
+				is_referenced = 1;
+				break;
+			}
+		}
+
+		frame->referenced = is_referenced;
+	}
+}
+
+static struct hevc_frame *
+codec_hevc_get_next_ready_frame(struct codec_hevc *hevc)
+{
+	struct hevc_frame *tmp, *ret = NULL;
+	u32 poc = INT_MAX;
+
+	list_for_each_entry(tmp, &hevc->ref_frames_list, list) {
+		if ((tmp->poc < poc) && tmp->show) {
+			ret = tmp;
+			poc = tmp->poc;
+		}
+	}
+
+	return ret;
+}
+
+/* Try to output as many frames as possible */
+static void codec_hevc_show_frames(struct amvdec_session *sess)
+{
+	struct hevc_frame *tmp, *n;
+	struct codec_hevc *hevc = sess->priv;
+
+	while ((tmp = codec_hevc_get_next_ready_frame(hevc))) {
+		if (hevc->curr_poc &&
+		    (hevc->frames_num <= tmp->num_reorder_pic))
+			break;
+
+		dev_dbg(sess->core->dev, "DONE frame poc %u; vbuf %u\n",
+			tmp->poc, tmp->vbuf->vb2_buf.index);
+		amvdec_dst_buf_done_offset(sess, tmp->vbuf, tmp->offset,
+					   V4L2_FIELD_NONE, false);
+
+		tmp->show = 0;
+		hevc->frames_num--;
+	}
+
+	/* clean output frame buffer */
+	list_for_each_entry_safe(tmp, n, &hevc->ref_frames_list, list) {
+		if (tmp->referenced || tmp->show)
+			continue;
+
+		list_del(&tmp->list);
+		kfree(tmp);
+	}
+}
+
+static int
+codec_hevc_setup_workspace(struct amvdec_session *sess,
+			   struct codec_hevc *hevc)
+{
+	struct amvdec_core *core = sess->core;
+	u32 revision = core->platform->revision;
+	dma_addr_t wkaddr;
+
+	/* Allocate some memory for the HEVC decoder's state */
+	hevc->workspace_vaddr = dma_alloc_coherent(core->dev, SIZE_WORKSPACE,
+						   &wkaddr, GFP_KERNEL);
+	if (!hevc->workspace_vaddr)
+		return -ENOMEM;
+
+	hevc->workspace_paddr = wkaddr;
+
+	amvdec_write_dos(core, HEVCD_IPP_LINEBUFF_BASE, wkaddr + IPP_OFFSET);
+	amvdec_write_dos(core, HEVC_RPM_BUFFER, wkaddr + RPM_OFFSET);
+	amvdec_write_dos(core, HEVC_SHORT_TERM_RPS, wkaddr + SH_TM_RPS_OFFSET);
+	amvdec_write_dos(core, HEVC_VPS_BUFFER, wkaddr + VPS_OFFSET);
+	amvdec_write_dos(core, HEVC_SPS_BUFFER, wkaddr + SPS_OFFSET);
+	amvdec_write_dos(core, HEVC_PPS_BUFFER, wkaddr + PPS_OFFSET);
+	amvdec_write_dos(core, HEVC_SAO_UP, wkaddr + SAO_UP_OFFSET);
+
+	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, hevc->is_10bit)) {
+		amvdec_write_dos(core, HEVC_SAO_MMU_VH0_ADDR,
+				 wkaddr + MMU_VBH_OFFSET);
+		amvdec_write_dos(core, HEVC_SAO_MMU_VH1_ADDR,
+				 wkaddr + MMU_VBH_OFFSET + (MMU_VBH_SIZE / 2));
+
+		if (revision >= VDEC_REVISION_G12A)
+			amvdec_write_dos(core, HEVC_ASSIST_MMU_MAP_ADDR,
+					 hevc->common.mmu_map_paddr);
+		else
+			amvdec_write_dos(core, H265_MMU_MAP_BUFFER,
+					 hevc->common.mmu_map_paddr);
+	} else if (revision < VDEC_REVISION_G12A) {
+		amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER,
+				 wkaddr + SWAP_BUF_OFFSET);
+		amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER2,
+				 wkaddr + SWAP_BUF2_OFFSET);
+	}
+
+	amvdec_write_dos(core, HEVC_SCALELUT, wkaddr + SCALELUT_OFFSET);
+	amvdec_write_dos(core, HEVC_DBLK_CFG4, wkaddr + DBLK_PARA_OFFSET);
+	amvdec_write_dos(core, HEVC_DBLK_CFG5, wkaddr + DBLK_DATA_OFFSET);
+	if (revision >= VDEC_REVISION_G12A)
+		amvdec_write_dos(core, HEVC_DBLK_CFGE,
+				 wkaddr + DBLK_DATA2_OFFSET);
+
+	amvdec_write_dos(core, LMEM_DUMP_ADR, wkaddr + LMEM_OFFSET);
+
+	return 0;
+}
+
+static int codec_hevc_start(struct amvdec_session *sess)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc;
+	u32 val;
+	int i;
+	int ret;
+
+	hevc = kzalloc(sizeof(*hevc), GFP_KERNEL);
+	if (!hevc)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&hevc->ref_frames_list);
+	hevc->curr_poc = INVALID_POC;
+
+	ret = codec_hevc_setup_workspace(sess, hevc);
+	if (ret)
+		goto free_hevc;
+
+	val = BIT(0); /* stream_fetch_enable */
+	if (core->platform->revision >= VDEC_REVISION_G12A)
+		val |= (0xf << 25); /* arwlen_axi_max */
+	amvdec_write_dos_bits(core, HEVC_STREAM_CONTROL, val);
+
+	val = amvdec_read_dos(core, HEVC_PARSER_INT_CONTROL) & 0x03ffffff;
+	val |= (3 << 29) | BIT(27) | BIT(24) | BIT(22) | BIT(7) | BIT(4) |
+	       BIT(0);
+	amvdec_write_dos(core, HEVC_PARSER_INT_CONTROL, val);
+	amvdec_write_dos_bits(core, HEVC_SHIFT_STATUS, BIT(1) | BIT(0));
+	amvdec_write_dos(core, HEVC_SHIFT_CONTROL,
+			 (3 << 6) | BIT(5) | BIT(2) | BIT(0));
+	amvdec_write_dos(core, HEVC_CABAC_CONTROL, 1);
+	amvdec_write_dos(core, HEVC_PARSER_CORE_CONTROL, 1);
+	amvdec_write_dos(core, HEVC_DEC_STATUS_REG, 0);
+
+	amvdec_write_dos(core, HEVC_IQIT_SCALELUT_WR_ADDR, 0);
+	for (i = 0; i < 1024; ++i)
+		amvdec_write_dos(core, HEVC_IQIT_SCALELUT_DATA, 0);
+
+	amvdec_write_dos(core, HEVC_DECODE_SIZE, 0);
+
+	amvdec_write_dos(core, HEVC_PARSER_CMD_WRITE, BIT(16));
+	for (i = 0; i < ARRAY_SIZE(vdec_hevc_parser_cmd); ++i)
+		amvdec_write_dos(core, HEVC_PARSER_CMD_WRITE,
+				 vdec_hevc_parser_cmd[i]);
+
+	amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
+	amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
+	amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
+	amvdec_write_dos(core, HEVC_PARSER_IF_CONTROL,
+			 BIT(5) | BIT(2) | BIT(0));
+
+	amvdec_write_dos(core, HEVCD_IPP_TOP_CNTL, BIT(0));
+	amvdec_write_dos(core, HEVCD_IPP_TOP_CNTL, BIT(1));
+
+	amvdec_write_dos(core, HEVC_WAIT_FLAG, 1);
+
+	/* clear mailbox interrupt */
+	amvdec_write_dos(core, HEVC_ASSIST_MBOX1_CLR_REG, 1);
+	/* enable mailbox interrupt */
+	amvdec_write_dos(core, HEVC_ASSIST_MBOX1_MASK, 1);
+	/* disable PSCALE for hardware sharing */
+	amvdec_write_dos(core, HEVC_PSCALE_CTRL, 0);
+	/* Let the uCode do all the parsing */
+	amvdec_write_dos(core, NAL_SEARCH_CTL, 0xc);
+
+	amvdec_write_dos(core, DECODE_STOP_POS, 0);
+	amvdec_write_dos(core, HEVC_DECODE_MODE, DECODE_MODE_SINGLE);
+	amvdec_write_dos(core, HEVC_DECODE_MODE2, 0);
+
+	/* AUX buffers */
+	hevc->aux_vaddr = dma_alloc_coherent(core->dev, SIZE_AUX,
+					     &hevc->aux_paddr, GFP_KERNEL);
+	if (!hevc->aux_vaddr) {
+		ret = -ENOMEM;
+		goto free_hevc;
+	}
+
+	amvdec_write_dos(core, HEVC_AUX_ADR, hevc->aux_paddr);
+	amvdec_write_dos(core, HEVC_AUX_DATA_SIZE,
+			 (((SIZE_AUX) >> 4) << 16) | 0);
+	mutex_init(&hevc->lock);
+	sess->priv = hevc;
+
+	return 0;
+
+free_hevc:
+	kfree(hevc);
+	return ret;
+}
+
+static void codec_hevc_flush_output(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	struct hevc_frame *tmp, *n;
+
+	while ((tmp = codec_hevc_get_next_ready_frame(hevc))) {
+		amvdec_dst_buf_done(sess, tmp->vbuf, V4L2_FIELD_NONE);
+		tmp->show = 0;
+		hevc->frames_num--;
+	}
+
+	list_for_each_entry_safe(tmp, n, &hevc->ref_frames_list, list) {
+		list_del(&tmp->list);
+		kfree(tmp);
+	}
+}
+
+static int codec_hevc_stop(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	struct amvdec_core *core = sess->core;
+
+	mutex_lock(&hevc->lock);
+	codec_hevc_flush_output(sess);
+
+	if (hevc->workspace_vaddr)
+		dma_free_coherent(core->dev, SIZE_WORKSPACE,
+				  hevc->workspace_vaddr,
+				  hevc->workspace_paddr);
+
+	if (hevc->aux_vaddr)
+		dma_free_coherent(core->dev, SIZE_AUX,
+				  hevc->aux_vaddr, hevc->aux_paddr);
+
+	codec_hevc_free_fbc_buffers(sess, &hevc->common);
+	mutex_unlock(&hevc->lock);
+	mutex_destroy(&hevc->lock);
+
+	return 0;
+}
+
+static struct hevc_frame *
+codec_hevc_get_frame_by_poc(struct codec_hevc *hevc, u32 poc)
+{
+	struct hevc_frame *tmp;
+
+	list_for_each_entry(tmp, &hevc->ref_frames_list, list) {
+		if (tmp->poc == poc)
+			return tmp;
+	}
+
+	return NULL;
+}
+
+static struct hevc_frame *
+codec_hevc_prepare_new_frame(struct amvdec_session *sess)
+{
+	struct amvdec_core *core = sess->core;
+	struct hevc_frame *new_frame = NULL;
+	struct codec_hevc *hevc = sess->priv;
+	struct vb2_v4l2_buffer *vbuf;
+	union rpm_param *params = &hevc->rpm_param;
+
+	new_frame = kzalloc(sizeof(*new_frame), GFP_KERNEL);
+	if (!new_frame)
+		return NULL;
+
+	vbuf = v4l2_m2m_dst_buf_remove(sess->m2m_ctx);
+	if (!vbuf) {
+		dev_err(sess->core->dev, "No dst buffer available\n");
+		return NULL;
+	}
+
+	new_frame->vbuf = vbuf;
+	new_frame->referenced = 1;
+	new_frame->show = 1;
+	new_frame->poc = hevc->curr_poc;
+	new_frame->cur_slice_type = params->p.slice_type;
+	new_frame->num_reorder_pic = params->p.sps_num_reorder_pics_0;
+	new_frame->offset = amvdec_read_dos(core, HEVC_SHIFT_BYTE_COUNT);
+
+	list_add_tail(&new_frame->list, &hevc->ref_frames_list);
+	hevc->frames_num++;
+
+	return new_frame;
+}
+
+static void
+codec_hevc_set_sao(struct amvdec_session *sess, struct hevc_frame *frame)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc = sess->priv;
+	struct vb2_buffer *vb = &frame->vbuf->vb2_buf;
+	union rpm_param *param = &hevc->rpm_param;
+	u32 pic_height_cu =
+		(hevc->height + hevc->lcu_size - 1) / hevc->lcu_size;
+	u32 sao_mem_unit = (hevc->lcu_size == 16 ? 9 :
+			   hevc->lcu_size == 32 ? 14 : 24) << 4;
+	u32 sao_vb_size = (sao_mem_unit + (2 << 4)) * pic_height_cu;
+	u32 misc_flag0 = param->p.misc_flag0;
+	dma_addr_t buf_y_paddr;
+	dma_addr_t buf_u_v_paddr;
+	u32 slice_deblocking_filter_disabled_flag;
+	u32 val, val_2;
+
+	val = (amvdec_read_dos(core, HEVC_SAO_CTRL0) & ~0xf) |
+	      ilog2(hevc->lcu_size);
+	amvdec_write_dos(core, HEVC_SAO_CTRL0, val);
+
+	amvdec_write_dos(core, HEVC_SAO_PIC_SIZE,
+			 hevc->width | (hevc->height << 16));
+	amvdec_write_dos(core, HEVC_SAO_PIC_SIZE_LCU,
+			 (hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16);
+
+	if (codec_hevc_use_downsample(sess->pixfmt_cap, hevc->is_10bit) ||
+	    codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
+			       hevc->is_10bit))
+		buf_y_paddr =
+		     hevc->common.fbc_buffer_paddr[vb->index];
+	else
+		buf_y_paddr =
+		       vb2_dma_contig_plane_dma_addr(vb, 0);
+
+	if (codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
+		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0000;
+		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
+		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
+	}
+
+	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
+		buf_y_paddr =
+		       vb2_dma_contig_plane_dma_addr(vb, 0);
+		buf_u_v_paddr =
+		       vb2_dma_contig_plane_dma_addr(vb, 1);
+		amvdec_write_dos(core, HEVC_SAO_Y_START_ADDR, buf_y_paddr);
+		amvdec_write_dos(core, HEVC_SAO_C_START_ADDR, buf_u_v_paddr);
+		amvdec_write_dos(core, HEVC_SAO_Y_WPTR, buf_y_paddr);
+		amvdec_write_dos(core, HEVC_SAO_C_WPTR, buf_u_v_paddr);
+	}
+
+	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
+			       hevc->is_10bit)) {
+		dma_addr_t header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
+
+		if (codec_hevc_use_downsample(sess->pixfmt_cap, hevc->is_10bit))
+			header_adr = hevc->common.mmu_header_paddr[vb->index];
+		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
+		/* use HEVC_CM_HEADER_START_ADDR */
+		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
+		amvdec_write_dos_bits(core, HEVC_SAO_CTRL9, BIT(0));
+	}
+
+	amvdec_write_dos(core, HEVC_SAO_Y_LENGTH,
+			 amvdec_get_output_size(sess));
+	amvdec_write_dos(core, HEVC_SAO_C_LENGTH,
+			 (amvdec_get_output_size(sess) / 2));
+
+	if (frame->cur_slice_idx == 0) {
+		if (core->platform->revision >= VDEC_REVISION_G12A) {
+			if (core->platform->revision >= VDEC_REVISION_SM1)
+				val = 0xfc << 8;
+			else
+				val = 0x54 << 8;
+
+			/* enable first, compressed write */
+			if (codec_hevc_use_fbc(sess->pixfmt_cap,
+					       hevc->is_10bit))
+				val |= BIT(8);
+
+			/* enable second, uncompressed write */
+			if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
+				val |= BIT(9);
+
+			/* dblk pipeline mode=1 for performance */
+			if (hevc->width >= 1280)
+				val |= BIT(4);
+
+			amvdec_write_dos(core, HEVC_DBLK_CFGB, val);
+			amvdec_write_dos(core, HEVC_DBLK_STS1 + 16, BIT(28));
+		}
+
+		amvdec_write_dos(core, HEVC_DBLK_CFG2,
+				 hevc->width | (hevc->height << 16));
+
+		val = 0;
+		if ((misc_flag0 >> PCM_ENABLE_FLAG_BIT) & 0x1)
+			val |= ((misc_flag0 >>
+				 PCM_LOOP_FILTER_DISABLED_FLAG_BIT) & 0x1) << 3;
+
+		val |= (param->p.pps_cb_qp_offset & 0x1f) << 4;
+		val |= (param->p.pps_cr_qp_offset & 0x1f) << 9;
+		val |= (hevc->lcu_size == 64) ? 0 :
+		       ((hevc->lcu_size == 32) ? 1 : 2);
+		amvdec_write_dos(core, HEVC_DBLK_CFG1, val);
+	}
+
+	val = amvdec_read_dos(core, HEVC_SAO_CTRL1) & ~0x3ff3;
+	val |= 0xff0; /* Set endianness for 2-bytes swaps (nv12) */
+	if (core->platform->revision < VDEC_REVISION_G12A) {
+		if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit))
+			val |= BIT(0); /* disable cm compression */
+		/* TOFIX: Handle Amlogic Framebuffer compression */
+	}
+
+	amvdec_write_dos(core, HEVC_SAO_CTRL1, val);
+
+	if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
+		/* no downscale for NV12 */
+		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0000;
+		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
+	}
+
+	val = amvdec_read_dos(core, HEVCD_IPP_AXIIF_CONFIG) & ~0x30;
+	val |= 0xf;
+	amvdec_write_dos(core, HEVCD_IPP_AXIIF_CONFIG, val);
+
+	val = 0;
+	val_2 = amvdec_read_dos(core, HEVC_SAO_CTRL0);
+	val_2 &= (~0x300);
+
+	slice_deblocking_filter_disabled_flag = (misc_flag0 >>
+			SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & 0x1;
+	if ((misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT)) &&
+	    (misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT))) {
+		val |= slice_deblocking_filter_disabled_flag << 2;
+
+		if (!slice_deblocking_filter_disabled_flag) {
+			val |= (param->p.slice_beta_offset_div2 & 0xf) << 3;
+			val |= (param->p.slice_tc_offset_div2 & 0xf) << 7;
+		}
+	} else {
+		val |=
+			((misc_flag0 >>
+			  PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & 0x1) << 2;
+
+		if (((misc_flag0 >> PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) &
+			0x1) == 0) {
+			val |= (param->p.pps_beta_offset_div2 & 0xf) << 3;
+			val |= (param->p.pps_tc_offset_div2 & 0xf) << 7;
+		}
+	}
+	if ((misc_flag0 & (1 << PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)) &&
+	    ((misc_flag0 & (1 << SLICE_SAO_LUMA_FLAG_BIT)) ||
+	   (misc_flag0 & (1 << SLICE_SAO_CHROMA_FLAG_BIT)) ||
+	   (!slice_deblocking_filter_disabled_flag))) {
+		val |=
+			((misc_flag0 >>
+			  SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
+			 & 0x1)	<< 1;
+		val_2 |=
+			((misc_flag0 >>
+			  SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
+			& 0x1) << 9;
+	} else {
+		val |=
+			((misc_flag0 >>
+			  PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
+			 & 0x1) << 1;
+		val_2 |=
+			((misc_flag0 >>
+			  PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
+			 & 0x1) << 9;
+	}
+
+	amvdec_write_dos(core, HEVC_DBLK_CFG9, val);
+	amvdec_write_dos(core, HEVC_SAO_CTRL0, val_2);
+
+	amvdec_write_dos(core, HEVC_sao_mem_unit, sao_mem_unit);
+	amvdec_write_dos(core, HEVC_SAO_ABV,
+			 hevc->workspace_paddr + SAO_ABV_OFFSET);
+	amvdec_write_dos(core, HEVC_sao_vb_size, sao_vb_size);
+	amvdec_write_dos(core, HEVC_SAO_VB,
+			 hevc->workspace_paddr + SAO_VB_OFFSET);
+}
+
+static dma_addr_t codec_hevc_get_frame_mv_paddr(struct codec_hevc *hevc,
+						struct hevc_frame *frame)
+{
+	return hevc->workspace_paddr + MPRED_MV_OFFSET +
+		(frame->vbuf->vb2_buf.index * MPRED_MV_BUF_SIZE);
+}
+
+static void
+codec_hevc_set_mpred_ctrl(struct amvdec_core *core, struct codec_hevc *hevc)
+{
+	union rpm_param *param = &hevc->rpm_param;
+	u32 slice_type = param->p.slice_type;
+	u32 lcu_size_log2 = ilog2(hevc->lcu_size);
+	u32 val;
+
+	val = slice_type |
+	      MPRED_CTRL0_ABOVE_EN |
+	      MPRED_CTRL0_MV_WR_EN |
+	      MPRED_CTRL0_BUF_LINEAR |
+	      (lcu_size_log2 << 16) |
+	      (3 << 20) | /* cu_size_log2 */
+	      (param->p.log2_parallel_merge_level << 24);
+
+	if (slice_type != I_SLICE)
+		val |= MPRED_CTRL0_MV_RD_EN;
+
+	if (param->p.collocated_from_l0_flag)
+		val |= MPRED_CTRL0_COL_FROM_L0;
+
+	if (param->p.slice_temporal_mvp_enable_flag)
+		val |= MPRED_CTRL0_TMVP;
+
+	if (hevc->ldc_flag)
+		val |= MPRED_CTRL0_LDC;
+
+	if (param->p.dependent_slice_segment_flag)
+		val |= MPRED_CTRL0_NEW_SLI_SEG;
+
+	if (param->p.slice_segment_address == 0)
+		val |= MPRED_CTRL0_NEW_PIC |
+		       MPRED_CTRL0_NEW_TILE;
+
+	amvdec_write_dos(core, HEVC_MPRED_CTRL0, val);
+
+	val = (5 - param->p.five_minus_max_num_merge_cand) |
+	      (AMVP_MAX_NUM_CANDS << 4) |
+	      (AMVP_MAX_NUM_CANDS_MEM << 8) |
+	      (NUM_CHROMA_MODE << 12) |
+	      (DM_CHROMA_IDX << 16);
+	amvdec_write_dos(core, HEVC_MPRED_CTRL1, val);
+}
+
+static void codec_hevc_set_mpred_mv(struct amvdec_core *core,
+				    struct codec_hevc *hevc,
+				    struct hevc_frame *frame,
+				    struct hevc_frame *col_frame)
+{
+	union rpm_param *param = &hevc->rpm_param;
+	u32 lcu_size_log2 = ilog2(hevc->lcu_size);
+	u32 mv_mem_unit = lcu_size_log2 == 6 ? 0x200 :
+			  lcu_size_log2 == 5 ? 0x80 : 0x20;
+	dma_addr_t col_mv_rd_start_addr, col_mv_rd_ptr, col_mv_rd_end_addr;
+	dma_addr_t mpred_mv_wr_ptr;
+
+	amvdec_read_dos(core, HEVC_MPRED_CURR_LCU);
+
+	col_mv_rd_start_addr = codec_hevc_get_frame_mv_paddr(hevc, col_frame);
+	mpred_mv_wr_ptr = codec_hevc_get_frame_mv_paddr(hevc, frame) +
+			  (hevc->slice_addr * mv_mem_unit);
+	col_mv_rd_ptr = col_mv_rd_start_addr +
+			(hevc->slice_addr * mv_mem_unit);
+	col_mv_rd_end_addr = col_mv_rd_start_addr +
+			     (hevc->lcu_total * mv_mem_unit);
+
+	amvdec_write_dos(core, HEVC_MPRED_MV_WR_START_ADDR,
+			 codec_hevc_get_frame_mv_paddr(hevc, frame));
+	amvdec_write_dos(core, HEVC_MPRED_MV_RD_START_ADDR,
+			 col_mv_rd_start_addr);
+
+	if (param->p.slice_segment_address == 0) {
+		amvdec_write_dos(core, HEVC_MPRED_ABV_START_ADDR,
+				 hevc->workspace_paddr + MPRED_ABV_OFFSET);
+		amvdec_write_dos(core, HEVC_MPRED_MV_WPTR, mpred_mv_wr_ptr);
+		amvdec_write_dos(core, HEVC_MPRED_MV_RPTR,
+				 col_mv_rd_start_addr);
+	} else {
+		amvdec_write_dos(core, HEVC_MPRED_MV_RPTR, col_mv_rd_ptr);
+	}
+
+	amvdec_write_dos(core, HEVC_MPRED_MV_RD_END_ADDR, col_mv_rd_end_addr);
+}
+
+/* Update motion prediction with the current slice */
+static void codec_hevc_set_mpred(struct amvdec_session *sess,
+				 struct hevc_frame *frame,
+				 struct hevc_frame *col_frame)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc = sess->priv;
+	u32 *ref_num = frame->ref_num;
+	u32 *ref_poc_l0 = frame->ref_poc_list[0][frame->cur_slice_idx];
+	u32 *ref_poc_l1 = frame->ref_poc_list[1][frame->cur_slice_idx];
+	u32 val;
+	int i;
+
+	codec_hevc_set_mpred_ctrl(core, hevc);
+	codec_hevc_set_mpred_mv(core, hevc, frame, col_frame);
+
+	amvdec_write_dos(core, HEVC_MPRED_PIC_SIZE,
+			 hevc->width | (hevc->height << 16));
+
+	val = ((hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16);
+	amvdec_write_dos(core, HEVC_MPRED_PIC_SIZE_LCU, val);
+
+	amvdec_write_dos(core, HEVC_MPRED_REF_NUM,
+			 (ref_num[1] << 8) | ref_num[0]);
+	amvdec_write_dos(core, HEVC_MPRED_REF_EN_L0, (1 << ref_num[0]) - 1);
+	amvdec_write_dos(core, HEVC_MPRED_REF_EN_L1, (1 << ref_num[1]) - 1);
+
+	amvdec_write_dos(core, HEVC_MPRED_CUR_POC, hevc->curr_poc);
+	amvdec_write_dos(core, HEVC_MPRED_COL_POC, hevc->col_poc);
+
+	for (i = 0; i < MAX_REF_ACTIVE; ++i) {
+		amvdec_write_dos(core, HEVC_MPRED_L0_REF00_POC + i * 4,
+				 ref_poc_l0[i]);
+		amvdec_write_dos(core, HEVC_MPRED_L1_REF00_POC + i * 4,
+				 ref_poc_l1[i]);
+	}
+}
+
+/*  motion compensation reference cache controller */
+static void codec_hevc_set_mcrcc(struct amvdec_session *sess)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc = sess->priv;
+	u32 val, val_2;
+	int l0_cnt = 0;
+	int l1_cnt = 0x7fff;
+
+	if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
+		l0_cnt = hevc->cur_frame->ref_num[0];
+		l1_cnt = hevc->cur_frame->ref_num[1];
+	}
+
+	if (hevc->cur_frame->cur_slice_type == I_SLICE) {
+		amvdec_write_dos(core, HEVCD_MCRCC_CTL1, 0);
+		return;
+	}
+
+	if (hevc->cur_frame->cur_slice_type == P_SLICE) {
+		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+				 BIT(1));
+		val = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+		val &= 0xffff;
+		val |= (val << 16);
+		amvdec_write_dos(core, HEVCD_MCRCC_CTL2, val);
+
+		if (l0_cnt == 1) {
+			amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val);
+		} else {
+			val = amvdec_read_dos(core,
+					      HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+			val &= 0xffff;
+			val |= (val << 16);
+			amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val);
+		}
+	} else { /* B_SLICE */
+		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 0);
+		val = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+		val &= 0xffff;
+		val |= (val << 16);
+		amvdec_write_dos(core, HEVCD_MCRCC_CTL2, val);
+
+		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+				 BIT(12) | BIT(1));
+		val_2 = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+		val_2 &= 0xffff;
+		val_2 |= (val_2 << 16);
+		if (val == val_2 && l1_cnt > 1) {
+			val_2 = amvdec_read_dos(core,
+						HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+			val_2 &= 0xffff;
+			val_2 |= (val_2 << 16);
+		}
+		amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val);
+	}
+
+	/* enable mcrcc progressive-mode */
+	amvdec_write_dos(core, HEVCD_MCRCC_CTL1, 0xff0);
+}
+
+static void codec_hevc_set_ref_list(struct amvdec_session *sess,
+				    u32 ref_num, u32 *ref_poc_list)
+{
+	struct codec_hevc *hevc = sess->priv;
+	struct hevc_frame *ref_frame;
+	struct amvdec_core *core = sess->core;
+	int i;
+	u32 buf_id_y;
+	u32 buf_id_uv;
+
+	for (i = 0; i < ref_num; i++) {
+		ref_frame = codec_hevc_get_frame_by_poc(hevc, ref_poc_list[i]);
+
+		if (!ref_frame) {
+			dev_warn(core->dev, "Couldn't find ref. frame %u\n",
+				 ref_poc_list[i]);
+			continue;
+		}
+
+		if (codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
+			buf_id_y = ref_frame->vbuf->vb2_buf.index;
+			buf_id_uv = buf_id_y;
+		} else {
+			buf_id_y = ref_frame->vbuf->vb2_buf.index * 2;
+			buf_id_uv = buf_id_y + 1;
+		}
+
+		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
+				 (buf_id_uv << 16) |
+				 (buf_id_uv << 8) |
+				 buf_id_y);
+	}
+}
+
+static void codec_hevc_set_mc(struct amvdec_session *sess,
+			      struct hevc_frame *frame)
+{
+	struct amvdec_core *core = sess->core;
+
+	if (frame->cur_slice_type == I_SLICE)
+		return;
+
+	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
+	codec_hevc_set_ref_list(sess, frame->ref_num[0],
+				frame->ref_poc_list[0][frame->cur_slice_idx]);
+
+	if (frame->cur_slice_type == P_SLICE)
+		return;
+
+	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+			 BIT(12) | BIT(0));
+	codec_hevc_set_ref_list(sess, frame->ref_num[1],
+				frame->ref_poc_list[1][frame->cur_slice_idx]);
+}
+
+static void codec_hevc_update_col_frame(struct codec_hevc *hevc)
+{
+	struct hevc_frame *cur_frame = hevc->cur_frame;
+	union rpm_param *param = &hevc->rpm_param;
+	u32 list_no = 0;
+	u32 col_ref = param->p.collocated_ref_idx;
+	u32 col_from_l0 = param->p.collocated_from_l0_flag;
+	u32 cur_slice_idx = cur_frame->cur_slice_idx;
+
+	if (cur_frame->cur_slice_type == B_SLICE)
+		list_no = 1 - col_from_l0;
+
+	if (col_ref >= cur_frame->ref_num[list_no])
+		hevc->col_poc = INVALID_POC;
+	else
+		hevc->col_poc = cur_frame->ref_poc_list[list_no]
+						       [cur_slice_idx]
+						       [col_ref];
+
+	if (cur_frame->cur_slice_type == I_SLICE)
+		goto end;
+
+	if (hevc->col_poc != INVALID_POC)
+		hevc->col_frame = codec_hevc_get_frame_by_poc(hevc,
+							      hevc->col_poc);
+	else
+		hevc->col_frame = hevc->cur_frame;
+
+end:
+	if (!hevc->col_frame)
+		hevc->col_frame = hevc->cur_frame;
+}
+
+static void codec_hevc_update_pocs(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	union rpm_param *param = &hevc->rpm_param;
+	u32 nal_unit_type = param->p.m_nalUnitType;
+	u32 temporal_id = param->p.m_temporalId & 0x7;
+	int max_poc_lsb =
+		1 << (param->p.log2_max_pic_order_cnt_lsb_minus4 + 4);
+	int prev_poc_lsb;
+	int prev_poc_msb;
+	int poc_msb;
+	int poc_lsb = param->p.POClsb;
+
+	if (nal_unit_type == NAL_UNIT_CODED_SLICE_IDR ||
+	    nal_unit_type == NAL_UNIT_CODED_SLICE_IDR_N_LP) {
+		hevc->curr_poc = 0;
+		if ((temporal_id - 1) == 0)
+			hevc->prev_tid0_poc = hevc->curr_poc;
+
+		return;
+	}
+
+	prev_poc_lsb = hevc->prev_tid0_poc % max_poc_lsb;
+	prev_poc_msb = hevc->prev_tid0_poc - prev_poc_lsb;
+
+	if ((poc_lsb < prev_poc_lsb) &&
+	    ((prev_poc_lsb - poc_lsb) >= (max_poc_lsb / 2)))
+		poc_msb = prev_poc_msb + max_poc_lsb;
+	else if ((poc_lsb > prev_poc_lsb) &&
+		 ((poc_lsb - prev_poc_lsb) > (max_poc_lsb / 2)))
+		poc_msb = prev_poc_msb - max_poc_lsb;
+	else
+		poc_msb = prev_poc_msb;
+
+	if (nal_unit_type == NAL_UNIT_CODED_SLICE_BLA   ||
+	    nal_unit_type == NAL_UNIT_CODED_SLICE_BLANT ||
+	    nal_unit_type == NAL_UNIT_CODED_SLICE_BLA_N_LP)
+		poc_msb = 0;
+
+	hevc->curr_poc = (poc_msb + poc_lsb);
+	if ((temporal_id - 1) == 0)
+		hevc->prev_tid0_poc = hevc->curr_poc;
+}
+
+static void codec_hevc_process_segment_header(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	union rpm_param *param = &hevc->rpm_param;
+
+	if (param->p.first_slice_segment_in_pic_flag == 0) {
+		hevc->slice_segment_addr = param->p.slice_segment_address;
+		if (!param->p.dependent_slice_segment_flag)
+			hevc->slice_addr = hevc->slice_segment_addr;
+	} else {
+		hevc->slice_segment_addr = 0;
+		hevc->slice_addr = 0;
+	}
+
+	codec_hevc_update_pocs(sess);
+}
+
+static int codec_hevc_process_segment(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	struct amvdec_core *core = sess->core;
+	union rpm_param *param = &hevc->rpm_param;
+	u32 slice_segment_address = param->p.slice_segment_address;
+
+	/* First slice: new frame */
+	if (slice_segment_address == 0) {
+		codec_hevc_update_referenced(hevc);
+		codec_hevc_show_frames(sess);
+
+		hevc->cur_frame = codec_hevc_prepare_new_frame(sess);
+		if (!hevc->cur_frame)
+			return -1;
+	} else {
+		hevc->cur_frame->cur_slice_idx++;
+	}
+
+	codec_hevc_update_frame_refs(sess, hevc->cur_frame);
+	codec_hevc_update_col_frame(hevc);
+	codec_hevc_update_ldc_flag(hevc);
+	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
+			       hevc->is_10bit))
+		codec_hevc_fill_mmu_map(sess, &hevc->common,
+					&hevc->cur_frame->vbuf->vb2_buf,
+					hevc->is_10bit);
+	codec_hevc_set_mc(sess, hevc->cur_frame);
+	codec_hevc_set_mcrcc(sess);
+	codec_hevc_set_mpred(sess, hevc->cur_frame, hevc->col_frame);
+	codec_hevc_set_sao(sess, hevc->cur_frame);
+
+	amvdec_write_dos_bits(core, HEVC_WAIT_FLAG, BIT(1));
+	amvdec_write_dos(core, HEVC_DEC_STATUS_REG,
+			 HEVC_CODED_SLICE_SEGMENT_DAT);
+
+	/* Interrupt the firmware's processor */
+	amvdec_write_dos(core, HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
+
+	return 0;
+}
+
+static int codec_hevc_process_rpm(struct codec_hevc *hevc)
+{
+	union rpm_param *param = &hevc->rpm_param;
+	int src_changed = 0;
+	u32 dst_width, dst_height;
+	u32 lcu_size;
+	u32 is_10bit = 0;
+
+	if (param->p.slice_segment_address	||
+	    !param->p.pic_width_in_luma_samples	||
+	    !param->p.pic_height_in_luma_samples)
+		return 0;
+
+	if (param->p.bit_depth)
+		is_10bit = 1;
+
+	hevc->width = param->p.pic_width_in_luma_samples;
+	hevc->height = param->p.pic_height_in_luma_samples;
+	dst_width = hevc->width;
+	dst_height = hevc->height;
+
+	lcu_size = 1 << (param->p.log2_min_coding_block_size_minus3 +
+		   3 + param->p.log2_diff_max_min_coding_block_size);
+
+	hevc->lcu_x_num = (hevc->width + lcu_size - 1) / lcu_size;
+	hevc->lcu_y_num = (hevc->height + lcu_size - 1) / lcu_size;
+	hevc->lcu_total = hevc->lcu_x_num * hevc->lcu_y_num;
+
+	if (param->p.conformance_window_flag) {
+		u32 sub_width = 1, sub_height = 1;
+
+		switch (param->p.chroma_format_idc) {
+		case 1:
+			sub_height = 2;
+			fallthrough;
+		case 2:
+			sub_width = 2;
+			break;
+		}
+
+		dst_width -= sub_width *
+			     (param->p.conf_win_left_offset +
+			      param->p.conf_win_right_offset);
+		dst_height -= sub_height *
+			      (param->p.conf_win_top_offset +
+			       param->p.conf_win_bottom_offset);
+	}
+
+	if (dst_width != hevc->dst_width ||
+	    dst_height != hevc->dst_height ||
+	    lcu_size != hevc->lcu_size ||
+	    is_10bit != hevc->is_10bit)
+		src_changed = 1;
+
+	hevc->dst_width = dst_width;
+	hevc->dst_height = dst_height;
+	hevc->lcu_size = lcu_size;
+	hevc->is_10bit = is_10bit;
+
+	return src_changed;
+}
+
+/*
+ * The RPM section within the workspace contains
+ * many information regarding the parsed bitstream
+ */
+static void codec_hevc_fetch_rpm(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	u16 *rpm_vaddr = hevc->workspace_vaddr + RPM_OFFSET;
+	int i, j;
+
+	for (i = 0; i < RPM_SIZE; i += 4) {
+		for (j = 0; j < 4; j++)
+			hevc->rpm_param.l.data[i + j] =
+				rpm_vaddr[i + 3 - j];
+	}
+}
+
+static void codec_hevc_resume(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+
+	if (codec_hevc_setup_buffers(sess, &hevc->common, hevc->is_10bit)) {
+		amvdec_abort(sess);
+		return;
+	}
+
+	codec_hevc_setup_decode_head(sess, hevc->is_10bit);
+	codec_hevc_process_segment_header(sess);
+	if (codec_hevc_process_segment(sess))
+		amvdec_abort(sess);
+}
+
+static irqreturn_t codec_hevc_threaded_isr(struct amvdec_session *sess)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc = sess->priv;
+	u32 dec_status = amvdec_read_dos(core, HEVC_DEC_STATUS_REG);
+
+	if (!hevc)
+		return IRQ_HANDLED;
+
+	mutex_lock(&hevc->lock);
+	if (dec_status != HEVC_SLICE_SEGMENT_DONE) {
+		dev_err(core->dev_dec, "Unrecognized dec_status: %08X\n",
+			dec_status);
+		amvdec_abort(sess);
+		goto unlock;
+	}
+
+	sess->keyframe_found = 1;
+	codec_hevc_fetch_rpm(sess);
+	if (codec_hevc_process_rpm(hevc)) {
+		amvdec_src_change(sess, hevc->dst_width, hevc->dst_height, 16,
+				  hevc->is_10bit ? 10 : 8);
+		goto unlock;
+	}
+
+	codec_hevc_process_segment_header(sess);
+	if (codec_hevc_process_segment(sess))
+		amvdec_abort(sess);
+
+unlock:
+	mutex_unlock(&hevc->lock);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t codec_hevc_isr(struct amvdec_session *sess)
+{
+	return IRQ_WAKE_THREAD;
+}
+
+struct amvdec_codec_ops codec_hevc_ops = {
+	.start = codec_hevc_start,
+	.stop = codec_hevc_stop,
+	.isr = codec_hevc_isr,
+	.threaded_isr = codec_hevc_threaded_isr,
+	.num_pending_bufs = codec_hevc_num_pending_bufs,
+	.drain = codec_hevc_flush_output,
+	.resume = codec_hevc_resume,
+};
diff --git a/drivers/staging/media/meson/vdec/codec_hevc.h b/drivers/staging/media/meson/vdec/codec_hevc.h
new file mode 100644
index 000000000000..f2f9b2464df1
--- /dev/null
+++ b/drivers/staging/media/meson/vdec/codec_hevc.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Maxime Jourdan <maxi.jourdan@wanadoo.fr>
+ */
+
+#ifndef __MESON_VDEC_CODEC_HEVC_H_
+#define __MESON_VDEC_CODEC_HEVC_H_
+
+#include "vdec.h"
+
+extern struct amvdec_codec_ops codec_hevc_ops;
+
+#endif
diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
index 3cd29ab4f979..6988348ce714 100644
--- a/drivers/staging/media/meson/vdec/esparser.c
+++ b/drivers/staging/media/meson/vdec/esparser.c
@@ -310,7 +310,8 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
 	 * they could pause when there is no capture buffer available and
 	 * resume on this notification.
 	 */
-	if (sess->fmt_out->pixfmt == V4L2_PIX_FMT_VP9) {
+	if (sess->fmt_out->pixfmt == V4L2_PIX_FMT_VP9 ||
+	    sess->fmt_out->pixfmt == V4L2_PIX_FMT_HEVC) {
 		if (codec_ops->num_pending_bufs)
 			num_dst_bufs = codec_ops->num_pending_bufs(sess);
 
diff --git a/drivers/staging/media/meson/vdec/hevc_regs.h b/drivers/staging/media/meson/vdec/hevc_regs.h
index 0392f41a1eed..e7eabdd2b119 100644
--- a/drivers/staging/media/meson/vdec/hevc_regs.h
+++ b/drivers/staging/media/meson/vdec/hevc_regs.h
@@ -205,6 +205,7 @@
 #define HEVC_CM_HEADER_START_ADDR 0xd8a0
 #define HEVC_CM_HEADER_LENGTH 0xd8a4
 #define HEVC_CM_HEADER_OFFSET 0xd8ac
+#define HEVC_SAO_CTRL9 0xd8b4
 #define HEVC_SAO_MMU_VH0_ADDR 0xd8e8
 #define HEVC_SAO_MMU_VH1_ADDR 0xd8ec
 
diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c
index 88c9d72e1c83..ea2aa0e8cf0b 100644
--- a/drivers/staging/media/meson/vdec/vdec_platform.c
+++ b/drivers/staging/media/meson/vdec/vdec_platform.c
@@ -11,10 +11,23 @@
 #include "vdec_hevc.h"
 #include "codec_mpeg12.h"
 #include "codec_h264.h"
+#include "codec_hevc.h"
 #include "codec_vp9.h"
 
 static const struct amvdec_format vdec_formats_gxbb[] = {
 	{
+		.pixfmt = V4L2_PIX_FMT_HEVC,
+		.min_buffers = 4,
+		.max_buffers = 24,
+		.max_width = 3840,
+		.max_height = 2160,
+		.vdec_ops = &vdec_hevc_ops,
+		.codec_ops = &codec_hevc_ops,
+		.firmware_path = "meson/vdec/gxl_hevc.bin",
+		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+		.flags = V4L2_FMT_FLAG_COMPRESSED |
+			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+	}, {
 		.pixfmt = V4L2_PIX_FMT_H264,
 		.min_buffers = 2,
 		.max_buffers = 24,
@@ -64,6 +77,18 @@ static const struct amvdec_format vdec_formats_gxl[] = {
 		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
 		.flags = V4L2_FMT_FLAG_COMPRESSED |
 			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+	}, {
+		.pixfmt = V4L2_PIX_FMT_HEVC,
+		.min_buffers = 4,
+		.max_buffers = 24,
+		.max_width = 3840,
+		.max_height = 2160,
+		.vdec_ops = &vdec_hevc_ops,
+		.codec_ops = &codec_hevc_ops,
+		.firmware_path = "meson/vdec/gxl_hevc.bin",
+		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+		.flags = V4L2_FMT_FLAG_COMPRESSED |
+			 V4L2_FMT_FLAG_DYN_RESOLUTION,
 	}, {
 		.pixfmt = V4L2_PIX_FMT_H264,
 		.min_buffers = 2,
@@ -114,6 +139,18 @@ static const struct amvdec_format vdec_formats_gxm[] = {
 		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
 		.flags = V4L2_FMT_FLAG_COMPRESSED |
 			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+	}, {
+		.pixfmt = V4L2_PIX_FMT_HEVC,
+		.min_buffers = 4,
+		.max_buffers = 24,
+		.max_width = 3840,
+		.max_height = 2160,
+		.vdec_ops = &vdec_hevc_ops,
+		.codec_ops = &codec_hevc_ops,
+		.firmware_path = "meson/vdec/gxl_hevc.bin",
+		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+		.flags = V4L2_FMT_FLAG_COMPRESSED |
+			 V4L2_FMT_FLAG_DYN_RESOLUTION,
 	}, {
 		.pixfmt = V4L2_PIX_FMT_H264,
 		.min_buffers = 2,
-- 
2.34.1


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[PATCH v2 2/2] media: meson: vdec: add HEVC decode codec

[Christian Hewitt]

From: Maxime Jourdan <mjourdan@baylibre.com>

Add initial HEVC codec for the Amlogic GXBB/GXL/GXM SoCs using
the common "HEVC" decoder driver.

Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
[codec alignment to upstream changes and frame handling improvements]
Signed-off-by: Benjamin Roszak <benjamin545@gmail.com>
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
---
 drivers/staging/media/meson/vdec/Makefile     |    2 +-
 drivers/staging/media/meson/vdec/codec_hevc.c | 1462 +++++++++++++++++
 drivers/staging/media/meson/vdec/codec_hevc.h |   13 +
 drivers/staging/media/meson/vdec/esparser.c   |    3 +-
 drivers/staging/media/meson/vdec/hevc_regs.h  |    1 +
 .../staging/media/meson/vdec/vdec_platform.c  |   37 +
 6 files changed, 1516 insertions(+), 2 deletions(-)
 create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.c
 create mode 100644 drivers/staging/media/meson/vdec/codec_hevc.h

diff --git a/drivers/staging/media/meson/vdec/Makefile b/drivers/staging/media/meson/vdec/Makefile
index 6e726af84ac9..16f848e456b9 100644
--- a/drivers/staging/media/meson/vdec/Makefile
+++ b/drivers/staging/media/meson/vdec/Makefile
@@ -3,6 +3,6 @@
 
 meson-vdec-objs = esparser.o vdec.o vdec_helpers.o vdec_platform.o
 meson-vdec-objs += vdec_1.o vdec_hevc.o
-meson-vdec-objs += codec_mpeg12.o codec_h264.o codec_hevc_common.o codec_vp9.o
+meson-vdec-objs += codec_mpeg12.o codec_h264.o codec_hevc_common.o codec_vp9.o codec_hevc.o
 
 obj-$(CONFIG_VIDEO_MESON_VDEC) += meson-vdec.o
diff --git a/drivers/staging/media/meson/vdec/codec_hevc.c b/drivers/staging/media/meson/vdec/codec_hevc.c
new file mode 100644
index 000000000000..fcaaa1ad50b8
--- /dev/null
+++ b/drivers/staging/media/meson/vdec/codec_hevc.c
@@ -0,0 +1,1462 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Maxime Jourdan <mjourdan@baylibre.com>
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ */
+
+#include <media/v4l2-mem2mem.h>
+#include <media/videobuf2-dma-contig.h>
+
+#include "codec_hevc.h"
+#include "dos_regs.h"
+#include "hevc_regs.h"
+#include "vdec_helpers.h"
+#include "codec_hevc_common.h"
+
+/* HEVC reg mapping */
+#define HEVC_DEC_STATUS_REG	HEVC_ASSIST_SCRATCH_0
+	#define HEVC_ACTION_DONE	0xff
+#define HEVC_RPM_BUFFER		HEVC_ASSIST_SCRATCH_1
+#define HEVC_SHORT_TERM_RPS	HEVC_ASSIST_SCRATCH_2
+#define HEVC_VPS_BUFFER		HEVC_ASSIST_SCRATCH_3
+#define HEVC_SPS_BUFFER		HEVC_ASSIST_SCRATCH_4
+#define HEVC_PPS_BUFFER		HEVC_ASSIST_SCRATCH_5
+#define HEVC_SAO_UP		HEVC_ASSIST_SCRATCH_6
+#define HEVC_STREAM_SWAP_BUFFER HEVC_ASSIST_SCRATCH_7
+#define H265_MMU_MAP_BUFFER	HEVC_ASSIST_SCRATCH_7
+#define HEVC_STREAM_SWAP_BUFFER2 HEVC_ASSIST_SCRATCH_8
+#define HEVC_sao_mem_unit	HEVC_ASSIST_SCRATCH_9
+#define HEVC_SAO_ABV		HEVC_ASSIST_SCRATCH_A
+#define HEVC_sao_vb_size	HEVC_ASSIST_SCRATCH_B
+#define HEVC_SAO_VB		HEVC_ASSIST_SCRATCH_C
+#define HEVC_SCALELUT		HEVC_ASSIST_SCRATCH_D
+#define HEVC_WAIT_FLAG		HEVC_ASSIST_SCRATCH_E
+#define RPM_CMD_REG		HEVC_ASSIST_SCRATCH_F
+#define LMEM_DUMP_ADR		HEVC_ASSIST_SCRATCH_F
+#define DEBUG_REG1		HEVC_ASSIST_SCRATCH_G
+#define HEVC_DECODE_MODE2	HEVC_ASSIST_SCRATCH_H
+#define NAL_SEARCH_CTL		HEVC_ASSIST_SCRATCH_I
+#define HEVC_DECODE_MODE	HEVC_ASSIST_SCRATCH_J
+	#define DECODE_MODE_SINGLE 0
+#define DECODE_STOP_POS		HEVC_ASSIST_SCRATCH_K
+#define HEVC_AUX_ADR		HEVC_ASSIST_SCRATCH_L
+#define HEVC_AUX_DATA_SIZE	HEVC_ASSIST_SCRATCH_M
+#define HEVC_DECODE_SIZE	HEVC_ASSIST_SCRATCH_N
+
+#define AMRISC_MAIN_REQ		 0x04
+
+/* HEVC Constants */
+#define MAX_REF_PIC_NUM		24
+#define MAX_REF_ACTIVE		16
+#define MAX_TILE_COL_NUM	10
+#define MAX_TILE_ROW_NUM	20
+#define MAX_SLICE_NUM		800
+#define INVALID_POC		0x80000000
+
+/* HEVC Workspace layout */
+#define MPRED_MV_BUF_SIZE 0x120000
+
+#define IPP_SIZE	0x4000
+#define SAO_ABV_SIZE	0x30000
+#define SAO_VB_SIZE	0x30000
+#define SH_TM_RPS_SIZE	0x800
+#define VPS_SIZE	0x800
+#define SPS_SIZE	0x800
+#define PPS_SIZE	0x2000
+#define SAO_UP_SIZE	0x2800
+#define SWAP_BUF_SIZE	0x800
+#define SWAP_BUF2_SIZE	0x800
+#define SCALELUT_SIZE	0x8000
+#define DBLK_PARA_SIZE	0x20000
+#define DBLK_DATA_SIZE	0x80000
+#define DBLK_DATA2_SIZE	0x80000
+#define MMU_VBH_SIZE	0x5000
+#define MPRED_ABV_SIZE	0x8000
+#define MPRED_MV_SIZE	(MPRED_MV_BUF_SIZE * MAX_REF_PIC_NUM)
+#define RPM_BUF_SIZE	0x100
+#define LMEM_SIZE	0xA00
+
+#define IPP_OFFSET       0x00
+#define SAO_ABV_OFFSET   (IPP_OFFSET + IPP_SIZE)
+#define SAO_VB_OFFSET    (SAO_ABV_OFFSET + SAO_ABV_SIZE)
+#define SH_TM_RPS_OFFSET (SAO_VB_OFFSET + SAO_VB_SIZE)
+#define VPS_OFFSET       (SH_TM_RPS_OFFSET + SH_TM_RPS_SIZE)
+#define SPS_OFFSET       (VPS_OFFSET + VPS_SIZE)
+#define PPS_OFFSET       (SPS_OFFSET + SPS_SIZE)
+#define SAO_UP_OFFSET    (PPS_OFFSET + PPS_SIZE)
+#define SWAP_BUF_OFFSET  (SAO_UP_OFFSET + SAO_UP_SIZE)
+#define SWAP_BUF2_OFFSET (SWAP_BUF_OFFSET + SWAP_BUF_SIZE)
+#define SCALELUT_OFFSET  (SWAP_BUF2_OFFSET + SWAP_BUF2_SIZE)
+#define DBLK_PARA_OFFSET (SCALELUT_OFFSET + SCALELUT_SIZE)
+#define DBLK_DATA_OFFSET (DBLK_PARA_OFFSET + DBLK_PARA_SIZE)
+#define DBLK_DATA2_OFFSET (DBLK_DATA_OFFSET + DBLK_DATA_SIZE)
+#define MMU_VBH_OFFSET   (DBLK_DATA2_OFFSET + DBLK_DATA2_SIZE)
+#define MPRED_ABV_OFFSET (MMU_VBH_OFFSET + MMU_VBH_SIZE)
+#define MPRED_MV_OFFSET  (MPRED_ABV_OFFSET + MPRED_ABV_SIZE)
+#define RPM_OFFSET       (MPRED_MV_OFFSET + MPRED_MV_SIZE)
+#define LMEM_OFFSET      (RPM_OFFSET + RPM_BUF_SIZE)
+
+/* ISR decode status */
+#define HEVC_DEC_IDLE                        0x0
+#define HEVC_NAL_UNIT_VPS                    0x1
+#define HEVC_NAL_UNIT_SPS                    0x2
+#define HEVC_NAL_UNIT_PPS                    0x3
+#define HEVC_NAL_UNIT_CODED_SLICE_SEGMENT    0x4
+#define HEVC_CODED_SLICE_SEGMENT_DAT         0x5
+#define HEVC_SLICE_DECODING                  0x6
+#define HEVC_NAL_UNIT_SEI                    0x7
+#define HEVC_SLICE_SEGMENT_DONE              0x8
+#define HEVC_NAL_SEARCH_DONE                 0x9
+#define HEVC_DECPIC_DATA_DONE                0xa
+#define HEVC_DECPIC_DATA_ERROR               0xb
+#define HEVC_SEI_DAT                         0xc
+#define HEVC_SEI_DAT_DONE                    0xd
+
+/* RPM misc_flag0 */
+#define PCM_LOOP_FILTER_DISABLED_FLAG_BIT		0
+#define PCM_ENABLE_FLAG_BIT				1
+#define LOOP_FILER_ACROSS_TILES_ENABLED_FLAG_BIT	2
+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT	3
+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT	4
+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT		5
+#define DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT		6
+#define SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT	7
+#define SLICE_SAO_LUMA_FLAG_BIT				8
+#define SLICE_SAO_CHROMA_FLAG_BIT			9
+#define SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT 10
+
+/* Constants for HEVC_MPRED_CTRL1 */
+#define AMVP_MAX_NUM_CANDS_MEM	3
+#define AMVP_MAX_NUM_CANDS	2
+#define NUM_CHROMA_MODE		5
+#define DM_CHROMA_IDX		36
+
+/* Buffer sizes */
+#define SIZE_WORKSPACE ALIGN(LMEM_OFFSET + LMEM_SIZE, 64 * SZ_1K)
+#define SIZE_AUX (SZ_1K * 16)
+#define SIZE_FRAME_MMU (0x1200 * 4)
+#define RPM_SIZE 0x80
+#define RPS_USED_BIT 14
+
+/* Data received from the HW in this form, do not rearrange */
+union rpm_param {
+	struct {
+		u16 data[RPM_SIZE];
+	} l;
+	struct {
+		u16 CUR_RPS[MAX_REF_ACTIVE];
+		u16 num_ref_idx_l0_active;
+		u16 num_ref_idx_l1_active;
+		u16 slice_type;
+		u16 slice_temporal_mvp_enable_flag;
+		u16 dependent_slice_segment_flag;
+		u16 slice_segment_address;
+		u16 num_title_rows_minus1;
+		u16 pic_width_in_luma_samples;
+		u16 pic_height_in_luma_samples;
+		u16 log2_min_coding_block_size_minus3;
+		u16 log2_diff_max_min_coding_block_size;
+		u16 log2_max_pic_order_cnt_lsb_minus4;
+		u16 POClsb;
+		u16 collocated_from_l0_flag;
+		u16 collocated_ref_idx;
+		u16 log2_parallel_merge_level;
+		u16 five_minus_max_num_merge_cand;
+		u16 sps_num_reorder_pics_0;
+		u16 modification_flag;
+		u16 tiles_flags;
+		u16 num_tile_columns_minus1;
+		u16 num_tile_rows_minus1;
+		u16 tile_width[8];
+		u16 tile_height[8];
+		u16 misc_flag0;
+		u16 pps_beta_offset_div2;
+		u16 pps_tc_offset_div2;
+		u16 slice_beta_offset_div2;
+		u16 slice_tc_offset_div2;
+		u16 pps_cb_qp_offset;
+		u16 pps_cr_qp_offset;
+		u16 first_slice_segment_in_pic_flag;
+		u16 m_temporalId;
+		u16 m_nalUnitType;
+		u16 vui_num_units_in_tick_hi;
+		u16 vui_num_units_in_tick_lo;
+		u16 vui_time_scale_hi;
+		u16 vui_time_scale_lo;
+		u16 bit_depth;
+		u16 profile_etc;
+		u16 sei_frame_field_info;
+		u16 video_signal_type;
+		u16 modification_list[0x20];
+		u16 conformance_window_flag;
+		u16 conf_win_left_offset;
+		u16 conf_win_right_offset;
+		u16 conf_win_top_offset;
+		u16 conf_win_bottom_offset;
+		u16 chroma_format_idc;
+		u16 color_description;
+		u16 aspect_ratio_idc;
+		u16 sar_width;
+		u16 sar_height;
+	} p;
+};
+
+enum nal_unit_type {
+	NAL_UNIT_CODED_SLICE_BLA	= 16,
+	NAL_UNIT_CODED_SLICE_BLANT	= 17,
+	NAL_UNIT_CODED_SLICE_BLA_N_LP	= 18,
+	NAL_UNIT_CODED_SLICE_IDR	= 19,
+	NAL_UNIT_CODED_SLICE_IDR_N_LP	= 20,
+};
+
+enum slice_type {
+	B_SLICE = 0,
+	P_SLICE = 1,
+	I_SLICE = 2,
+};
+
+/* A frame being decoded */
+struct hevc_frame {
+	struct list_head list;
+	struct vb2_v4l2_buffer *vbuf;
+	u32 offset;
+	u32 poc;
+
+	int referenced;
+	int show;
+	u32 num_reorder_pic;
+
+	u32 cur_slice_idx;
+	u32 cur_slice_type;
+
+	/* 2 lists (L0/L1) ; 800 slices ; 16 refs */
+	u32 ref_poc_list[2][MAX_SLICE_NUM][MAX_REF_ACTIVE];
+	u32 ref_num[2];
+};
+
+struct codec_hevc {
+	/* Protect the data structure */
+	struct mutex lock;
+
+	/* Common part of the HEVC decoder */
+	struct codec_hevc_common common;
+
+	/* Buffer for the HEVC Workspace */
+	void      *workspace_vaddr;
+	dma_addr_t workspace_paddr;
+
+	/* AUX buffer */
+	void      *aux_vaddr;
+	dma_addr_t aux_paddr;
+
+	/* Contains many information parsed from the bitstream */
+	union rpm_param rpm_param;
+
+	/* Information computed from the RPM */
+	u32 lcu_size; // Largest Coding Unit
+	u32 lcu_x_num;
+	u32 lcu_y_num;
+	u32 lcu_total;
+
+	/* Current Frame being handled */
+	struct hevc_frame *cur_frame;
+	u32 curr_poc;
+	/* Collocated Reference Picture */
+	struct hevc_frame *col_frame;
+	u32 col_poc;
+
+	/* All ref frames used by the HW at a given time */
+	struct list_head ref_frames_list;
+	u32 frames_num;
+
+	/* Coded resolution reported by the hardware */
+	u32 width, height;
+	/* Resolution minus the conformance window offsets */
+	u32 dst_width, dst_height;
+
+	u32 prev_tid0_poc;
+	u32 slice_segment_addr;
+	u32 slice_addr;
+	u32 ldc_flag;
+
+	/* Whether we detected the bitstream as 10-bit */
+	int is_10bit;
+};
+
+static u32 codec_hevc_num_pending_bufs(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc;
+	u32 ret;
+
+	hevc = sess->priv;
+	if (!hevc)
+		return 0;
+
+	mutex_lock(&hevc->lock);
+	ret = hevc->frames_num;
+	mutex_unlock(&hevc->lock);
+
+	return ret;
+}
+
+/* Update the L0 and L1 reference lists for a given frame */
+static void codec_hevc_update_frame_refs(struct amvdec_session *sess,
+					 struct hevc_frame *frame)
+{
+	struct codec_hevc *hevc = sess->priv;
+	union rpm_param *params = &hevc->rpm_param;
+	int num_ref_idx_l0_active =
+		(params->p.num_ref_idx_l0_active > MAX_REF_ACTIVE) ?
+		MAX_REF_ACTIVE : params->p.num_ref_idx_l0_active;
+	int num_ref_idx_l1_active =
+		(params->p.num_ref_idx_l1_active > MAX_REF_ACTIVE) ?
+		MAX_REF_ACTIVE : params->p.num_ref_idx_l1_active;
+	int ref_picset0[MAX_REF_ACTIVE] = { 0 };
+	int ref_picset1[MAX_REF_ACTIVE] = { 0 };
+	u16 *mod_list = params->p.modification_list;
+	int num_neg = 0;
+	int num_pos = 0;
+	int total_num;
+	int i;
+
+	for (i = 0; i < MAX_REF_ACTIVE; i++) {
+		frame->ref_poc_list[0][frame->cur_slice_idx][i] = 0;
+		frame->ref_poc_list[1][frame->cur_slice_idx][i] = 0;
+	}
+
+	for (i = 0; i < MAX_REF_ACTIVE; i++) {
+		u16 cur_rps = params->p.CUR_RPS[i];
+		int delt = cur_rps & ((1 << (RPS_USED_BIT - 1)) - 1);
+
+		if (cur_rps & 0x8000)
+			break;
+
+		if (!((cur_rps >> RPS_USED_BIT) & 1))
+			continue;
+
+		if ((cur_rps >> (RPS_USED_BIT - 1)) & 1) {
+			ref_picset0[num_neg] =
+			       frame->poc - ((1 << (RPS_USED_BIT - 1)) - delt);
+			num_neg++;
+		} else {
+			ref_picset1[num_pos] = frame->poc + delt;
+			num_pos++;
+		}
+	}
+
+	total_num = num_neg + num_pos;
+
+	if (total_num <= 0)
+		goto end;
+
+	for (i = 0; i < num_ref_idx_l0_active; i++) {
+		int cidx;
+
+		if (params->p.modification_flag & 0x1)
+			cidx = mod_list[i];
+		else
+			cidx = i % total_num;
+
+		frame->ref_poc_list[0][frame->cur_slice_idx][i] =
+			cidx >= num_neg ? ref_picset1[cidx - num_neg] :
+			ref_picset0[cidx];
+	}
+
+	if (params->p.slice_type != B_SLICE)
+		goto end;
+
+	if (params->p.modification_flag & 0x2) {
+		for (i = 0; i < num_ref_idx_l1_active; i++) {
+			int cidx;
+
+			if (params->p.modification_flag & 0x1)
+				cidx = mod_list[num_ref_idx_l0_active + i];
+			else
+				cidx = mod_list[i];
+
+			frame->ref_poc_list[1][frame->cur_slice_idx][i] =
+				(cidx >= num_pos) ? ref_picset0[cidx - num_pos]
+				: ref_picset1[cidx];
+		}
+	} else {
+		for (i = 0; i < num_ref_idx_l1_active; i++) {
+			int cidx = i % total_num;
+
+			frame->ref_poc_list[1][frame->cur_slice_idx][i] =
+				cidx >= num_pos ? ref_picset0[cidx - num_pos] :
+				ref_picset1[cidx];
+		}
+	}
+
+end:
+	frame->ref_num[0] = num_ref_idx_l0_active;
+	frame->ref_num[1] = num_ref_idx_l1_active;
+
+	dev_dbg(sess->core->dev,
+		"Frame %u; slice %u; slice_type %u; num_l0 %u; num_l1 %u\n",
+		frame->poc, frame->cur_slice_idx, params->p.slice_type,
+		frame->ref_num[0], frame->ref_num[1]);
+}
+
+static void codec_hevc_update_ldc_flag(struct codec_hevc *hevc)
+{
+	struct hevc_frame *frame = hevc->cur_frame;
+	u32 slice_type = frame->cur_slice_type;
+	u32 slice_idx = frame->cur_slice_idx;
+	int i;
+
+	hevc->ldc_flag = 0;
+
+	if (slice_type == I_SLICE)
+		return;
+
+	hevc->ldc_flag = 1;
+	for (i = 0; (i < frame->ref_num[0]) && hevc->ldc_flag; i++) {
+		if (frame->ref_poc_list[0][slice_idx][i] > frame->poc) {
+			hevc->ldc_flag = 0;
+			break;
+		}
+	}
+
+	if (slice_type == P_SLICE)
+		return;
+
+	for (i = 0; (i < frame->ref_num[1]) && hevc->ldc_flag; i++) {
+		if (frame->ref_poc_list[1][slice_idx][i] > frame->poc) {
+			hevc->ldc_flag = 0;
+			break;
+		}
+	}
+}
+
+/* Tag "old" frames that are no longer referenced */
+static void codec_hevc_update_referenced(struct codec_hevc *hevc)
+{
+	union rpm_param *param = &hevc->rpm_param;
+	struct hevc_frame *frame;
+	int i;
+	u32 curr_poc = hevc->curr_poc;
+
+	list_for_each_entry(frame, &hevc->ref_frames_list, list) {
+		int is_referenced = 0;
+		u32 poc_tmp;
+
+		if (!frame->referenced)
+			continue;
+
+		for (i = 0; i < MAX_REF_ACTIVE; i++) {
+			int delt;
+
+			if (param->p.CUR_RPS[i] & 0x8000)
+				break;
+
+			delt = param->p.CUR_RPS[i] &
+			       ((1 << (RPS_USED_BIT - 1)) - 1);
+			if (param->p.CUR_RPS[i] & (1 << (RPS_USED_BIT - 1))) {
+				poc_tmp = curr_poc -
+				      ((1 << (RPS_USED_BIT - 1)) - delt);
+			} else {
+				poc_tmp = curr_poc + delt;
+			}
+
+			if (poc_tmp == frame->poc) {
+				is_referenced = 1;
+				break;
+			}
+		}
+
+		frame->referenced = is_referenced;
+	}
+}
+
+static struct hevc_frame *
+codec_hevc_get_next_ready_frame(struct codec_hevc *hevc)
+{
+	struct hevc_frame *tmp, *ret = NULL;
+	u32 poc = INT_MAX;
+
+	list_for_each_entry(tmp, &hevc->ref_frames_list, list) {
+		if ((tmp->poc < poc) && tmp->show) {
+			ret = tmp;
+			poc = tmp->poc;
+		}
+	}
+
+	return ret;
+}
+
+/* Try to output as many frames as possible */
+static void codec_hevc_show_frames(struct amvdec_session *sess)
+{
+	struct hevc_frame *tmp, *n;
+	struct codec_hevc *hevc = sess->priv;
+
+	while ((tmp = codec_hevc_get_next_ready_frame(hevc))) {
+		if (hevc->curr_poc &&
+		    (hevc->frames_num <= tmp->num_reorder_pic))
+			break;
+
+		dev_dbg(sess->core->dev, "DONE frame poc %u; vbuf %u\n",
+			tmp->poc, tmp->vbuf->vb2_buf.index);
+		amvdec_dst_buf_done_offset(sess, tmp->vbuf, tmp->offset,
+					   V4L2_FIELD_NONE, false);
+
+		tmp->show = 0;
+		hevc->frames_num--;
+	}
+
+	/* clean output frame buffer */
+	list_for_each_entry_safe(tmp, n, &hevc->ref_frames_list, list) {
+		if (tmp->referenced || tmp->show)
+			continue;
+
+		list_del(&tmp->list);
+		kfree(tmp);
+	}
+}
+
+static int
+codec_hevc_setup_workspace(struct amvdec_session *sess,
+			   struct codec_hevc *hevc)
+{
+	struct amvdec_core *core = sess->core;
+	u32 revision = core->platform->revision;
+	dma_addr_t wkaddr;
+
+	/* Allocate some memory for the HEVC decoder's state */
+	hevc->workspace_vaddr = dma_alloc_coherent(core->dev, SIZE_WORKSPACE,
+						   &wkaddr, GFP_KERNEL);
+	if (!hevc->workspace_vaddr)
+		return -ENOMEM;
+
+	hevc->workspace_paddr = wkaddr;
+
+	amvdec_write_dos(core, HEVCD_IPP_LINEBUFF_BASE, wkaddr + IPP_OFFSET);
+	amvdec_write_dos(core, HEVC_RPM_BUFFER, wkaddr + RPM_OFFSET);
+	amvdec_write_dos(core, HEVC_SHORT_TERM_RPS, wkaddr + SH_TM_RPS_OFFSET);
+	amvdec_write_dos(core, HEVC_VPS_BUFFER, wkaddr + VPS_OFFSET);
+	amvdec_write_dos(core, HEVC_SPS_BUFFER, wkaddr + SPS_OFFSET);
+	amvdec_write_dos(core, HEVC_PPS_BUFFER, wkaddr + PPS_OFFSET);
+	amvdec_write_dos(core, HEVC_SAO_UP, wkaddr + SAO_UP_OFFSET);
+
+	if (codec_hevc_use_mmu(revision, sess->pixfmt_cap, hevc->is_10bit)) {
+		amvdec_write_dos(core, HEVC_SAO_MMU_VH0_ADDR,
+				 wkaddr + MMU_VBH_OFFSET);
+		amvdec_write_dos(core, HEVC_SAO_MMU_VH1_ADDR,
+				 wkaddr + MMU_VBH_OFFSET + (MMU_VBH_SIZE / 2));
+
+		if (revision >= VDEC_REVISION_G12A)
+			amvdec_write_dos(core, HEVC_ASSIST_MMU_MAP_ADDR,
+					 hevc->common.mmu_map_paddr);
+		else
+			amvdec_write_dos(core, H265_MMU_MAP_BUFFER,
+					 hevc->common.mmu_map_paddr);
+	} else if (revision < VDEC_REVISION_G12A) {
+		amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER,
+				 wkaddr + SWAP_BUF_OFFSET);
+		amvdec_write_dos(core, HEVC_STREAM_SWAP_BUFFER2,
+				 wkaddr + SWAP_BUF2_OFFSET);
+	}
+
+	amvdec_write_dos(core, HEVC_SCALELUT, wkaddr + SCALELUT_OFFSET);
+	amvdec_write_dos(core, HEVC_DBLK_CFG4, wkaddr + DBLK_PARA_OFFSET);
+	amvdec_write_dos(core, HEVC_DBLK_CFG5, wkaddr + DBLK_DATA_OFFSET);
+	if (revision >= VDEC_REVISION_G12A)
+		amvdec_write_dos(core, HEVC_DBLK_CFGE,
+				 wkaddr + DBLK_DATA2_OFFSET);
+
+	amvdec_write_dos(core, LMEM_DUMP_ADR, wkaddr + LMEM_OFFSET);
+
+	return 0;
+}
+
+static int codec_hevc_start(struct amvdec_session *sess)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc;
+	u32 val;
+	int i;
+	int ret;
+
+	hevc = kzalloc(sizeof(*hevc), GFP_KERNEL);
+	if (!hevc)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&hevc->ref_frames_list);
+	hevc->curr_poc = INVALID_POC;
+
+	ret = codec_hevc_setup_workspace(sess, hevc);
+	if (ret)
+		goto free_hevc;
+
+	val = BIT(0); /* stream_fetch_enable */
+	if (core->platform->revision >= VDEC_REVISION_G12A)
+		val |= (0xf << 25); /* arwlen_axi_max */
+	amvdec_write_dos_bits(core, HEVC_STREAM_CONTROL, val);
+
+	val = amvdec_read_dos(core, HEVC_PARSER_INT_CONTROL) & 0x03ffffff;
+	val |= (3 << 29) | BIT(27) | BIT(24) | BIT(22) | BIT(7) | BIT(4) |
+	       BIT(0);
+	amvdec_write_dos(core, HEVC_PARSER_INT_CONTROL, val);
+	amvdec_write_dos_bits(core, HEVC_SHIFT_STATUS, BIT(1) | BIT(0));
+	amvdec_write_dos(core, HEVC_SHIFT_CONTROL,
+			 (3 << 6) | BIT(5) | BIT(2) | BIT(0));
+	amvdec_write_dos(core, HEVC_CABAC_CONTROL, 1);
+	amvdec_write_dos(core, HEVC_PARSER_CORE_CONTROL, 1);
+	amvdec_write_dos(core, HEVC_DEC_STATUS_REG, 0);
+
+	amvdec_write_dos(core, HEVC_IQIT_SCALELUT_WR_ADDR, 0);
+	for (i = 0; i < 1024; ++i)
+		amvdec_write_dos(core, HEVC_IQIT_SCALELUT_DATA, 0);
+
+	amvdec_write_dos(core, HEVC_DECODE_SIZE, 0);
+
+	amvdec_write_dos(core, HEVC_PARSER_CMD_WRITE, BIT(16));
+	for (i = 0; i < ARRAY_SIZE(vdec_hevc_parser_cmd); ++i)
+		amvdec_write_dos(core, HEVC_PARSER_CMD_WRITE,
+				 vdec_hevc_parser_cmd[i]);
+
+	amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
+	amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
+	amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
+	amvdec_write_dos(core, HEVC_PARSER_IF_CONTROL,
+			 BIT(5) | BIT(2) | BIT(0));
+
+	amvdec_write_dos(core, HEVCD_IPP_TOP_CNTL, BIT(0));
+	amvdec_write_dos(core, HEVCD_IPP_TOP_CNTL, BIT(1));
+
+	amvdec_write_dos(core, HEVC_WAIT_FLAG, 1);
+
+	/* clear mailbox interrupt */
+	amvdec_write_dos(core, HEVC_ASSIST_MBOX1_CLR_REG, 1);
+	/* enable mailbox interrupt */
+	amvdec_write_dos(core, HEVC_ASSIST_MBOX1_MASK, 1);
+	/* disable PSCALE for hardware sharing */
+	amvdec_write_dos(core, HEVC_PSCALE_CTRL, 0);
+	/* Let the uCode do all the parsing */
+	amvdec_write_dos(core, NAL_SEARCH_CTL, 0xc);
+
+	amvdec_write_dos(core, DECODE_STOP_POS, 0);
+	amvdec_write_dos(core, HEVC_DECODE_MODE, DECODE_MODE_SINGLE);
+	amvdec_write_dos(core, HEVC_DECODE_MODE2, 0);
+
+	/* AUX buffers */
+	hevc->aux_vaddr = dma_alloc_coherent(core->dev, SIZE_AUX,
+					     &hevc->aux_paddr, GFP_KERNEL);
+	if (!hevc->aux_vaddr) {
+		ret = -ENOMEM;
+		goto free_hevc;
+	}
+
+	amvdec_write_dos(core, HEVC_AUX_ADR, hevc->aux_paddr);
+	amvdec_write_dos(core, HEVC_AUX_DATA_SIZE,
+			 (((SIZE_AUX) >> 4) << 16) | 0);
+	mutex_init(&hevc->lock);
+	sess->priv = hevc;
+
+	return 0;
+
+free_hevc:
+	kfree(hevc);
+	return ret;
+}
+
+static void codec_hevc_flush_output(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	struct hevc_frame *tmp, *n;
+
+	while ((tmp = codec_hevc_get_next_ready_frame(hevc))) {
+		amvdec_dst_buf_done(sess, tmp->vbuf, V4L2_FIELD_NONE);
+		tmp->show = 0;
+		hevc->frames_num--;
+	}
+
+	list_for_each_entry_safe(tmp, n, &hevc->ref_frames_list, list) {
+		list_del(&tmp->list);
+		kfree(tmp);
+	}
+}
+
+static int codec_hevc_stop(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	struct amvdec_core *core = sess->core;
+
+	mutex_lock(&hevc->lock);
+	codec_hevc_flush_output(sess);
+
+	if (hevc->workspace_vaddr)
+		dma_free_coherent(core->dev, SIZE_WORKSPACE,
+				  hevc->workspace_vaddr,
+				  hevc->workspace_paddr);
+
+	if (hevc->aux_vaddr)
+		dma_free_coherent(core->dev, SIZE_AUX,
+				  hevc->aux_vaddr, hevc->aux_paddr);
+
+	codec_hevc_free_fbc_buffers(sess, &hevc->common);
+	mutex_unlock(&hevc->lock);
+	mutex_destroy(&hevc->lock);
+
+	return 0;
+}
+
+static struct hevc_frame *
+codec_hevc_get_frame_by_poc(struct codec_hevc *hevc, u32 poc)
+{
+	struct hevc_frame *tmp;
+
+	list_for_each_entry(tmp, &hevc->ref_frames_list, list) {
+		if (tmp->poc == poc)
+			return tmp;
+	}
+
+	return NULL;
+}
+
+static struct hevc_frame *
+codec_hevc_prepare_new_frame(struct amvdec_session *sess)
+{
+	struct amvdec_core *core = sess->core;
+	struct hevc_frame *new_frame = NULL;
+	struct codec_hevc *hevc = sess->priv;
+	struct vb2_v4l2_buffer *vbuf;
+	union rpm_param *params = &hevc->rpm_param;
+
+	new_frame = kzalloc(sizeof(*new_frame), GFP_KERNEL);
+	if (!new_frame)
+		return NULL;
+
+	vbuf = v4l2_m2m_dst_buf_remove(sess->m2m_ctx);
+	if (!vbuf) {
+		dev_err(sess->core->dev, "No dst buffer available\n");
+		return NULL;
+	}
+
+	new_frame->vbuf = vbuf;
+	new_frame->referenced = 1;
+	new_frame->show = 1;
+	new_frame->poc = hevc->curr_poc;
+	new_frame->cur_slice_type = params->p.slice_type;
+	new_frame->num_reorder_pic = params->p.sps_num_reorder_pics_0;
+	new_frame->offset = amvdec_read_dos(core, HEVC_SHIFT_BYTE_COUNT);
+
+	list_add_tail(&new_frame->list, &hevc->ref_frames_list);
+	hevc->frames_num++;
+
+	return new_frame;
+}
+
+static void
+codec_hevc_set_sao(struct amvdec_session *sess, struct hevc_frame *frame)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc = sess->priv;
+	struct vb2_buffer *vb = &frame->vbuf->vb2_buf;
+	union rpm_param *param = &hevc->rpm_param;
+	u32 pic_height_cu =
+		(hevc->height + hevc->lcu_size - 1) / hevc->lcu_size;
+	u32 sao_mem_unit = (hevc->lcu_size == 16 ? 9 :
+			   hevc->lcu_size == 32 ? 14 : 24) << 4;
+	u32 sao_vb_size = (sao_mem_unit + (2 << 4)) * pic_height_cu;
+	u32 misc_flag0 = param->p.misc_flag0;
+	dma_addr_t buf_y_paddr;
+	dma_addr_t buf_u_v_paddr;
+	u32 slice_deblocking_filter_disabled_flag;
+	u32 val, val_2;
+
+	val = (amvdec_read_dos(core, HEVC_SAO_CTRL0) & ~0xf) |
+	      ilog2(hevc->lcu_size);
+	amvdec_write_dos(core, HEVC_SAO_CTRL0, val);
+
+	amvdec_write_dos(core, HEVC_SAO_PIC_SIZE,
+			 hevc->width | (hevc->height << 16));
+	amvdec_write_dos(core, HEVC_SAO_PIC_SIZE_LCU,
+			 (hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16);
+
+	if (codec_hevc_use_downsample(sess->pixfmt_cap, hevc->is_10bit) ||
+	    codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
+			       hevc->is_10bit))
+		buf_y_paddr =
+		     hevc->common.fbc_buffer_paddr[vb->index];
+	else
+		buf_y_paddr =
+		       vb2_dma_contig_plane_dma_addr(vb, 0);
+
+	if (codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
+		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0000;
+		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
+		amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
+	}
+
+	if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M) {
+		buf_y_paddr =
+		       vb2_dma_contig_plane_dma_addr(vb, 0);
+		buf_u_v_paddr =
+		       vb2_dma_contig_plane_dma_addr(vb, 1);
+		amvdec_write_dos(core, HEVC_SAO_Y_START_ADDR, buf_y_paddr);
+		amvdec_write_dos(core, HEVC_SAO_C_START_ADDR, buf_u_v_paddr);
+		amvdec_write_dos(core, HEVC_SAO_Y_WPTR, buf_y_paddr);
+		amvdec_write_dos(core, HEVC_SAO_C_WPTR, buf_u_v_paddr);
+	}
+
+	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
+			       hevc->is_10bit)) {
+		dma_addr_t header_adr = vb2_dma_contig_plane_dma_addr(vb, 0);
+
+		if (codec_hevc_use_downsample(sess->pixfmt_cap, hevc->is_10bit))
+			header_adr = hevc->common.mmu_header_paddr[vb->index];
+		amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR, header_adr);
+		/* use HEVC_CM_HEADER_START_ADDR */
+		amvdec_write_dos_bits(core, HEVC_SAO_CTRL5, BIT(10));
+		amvdec_write_dos_bits(core, HEVC_SAO_CTRL9, BIT(0));
+	}
+
+	amvdec_write_dos(core, HEVC_SAO_Y_LENGTH,
+			 amvdec_get_output_size(sess));
+	amvdec_write_dos(core, HEVC_SAO_C_LENGTH,
+			 (amvdec_get_output_size(sess) / 2));
+
+	if (frame->cur_slice_idx == 0) {
+		if (core->platform->revision >= VDEC_REVISION_G12A) {
+			if (core->platform->revision >= VDEC_REVISION_SM1)
+				val = 0xfc << 8;
+			else
+				val = 0x54 << 8;
+
+			/* enable first, compressed write */
+			if (codec_hevc_use_fbc(sess->pixfmt_cap,
+					       hevc->is_10bit))
+				val |= BIT(8);
+
+			/* enable second, uncompressed write */
+			if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
+				val |= BIT(9);
+
+			/* dblk pipeline mode=1 for performance */
+			if (hevc->width >= 1280)
+				val |= BIT(4);
+
+			amvdec_write_dos(core, HEVC_DBLK_CFGB, val);
+			amvdec_write_dos(core, HEVC_DBLK_STS1 + 16, BIT(28));
+		}
+
+		amvdec_write_dos(core, HEVC_DBLK_CFG2,
+				 hevc->width | (hevc->height << 16));
+
+		val = 0;
+		if ((misc_flag0 >> PCM_ENABLE_FLAG_BIT) & 0x1)
+			val |= ((misc_flag0 >>
+				 PCM_LOOP_FILTER_DISABLED_FLAG_BIT) & 0x1) << 3;
+
+		val |= (param->p.pps_cb_qp_offset & 0x1f) << 4;
+		val |= (param->p.pps_cr_qp_offset & 0x1f) << 9;
+		val |= (hevc->lcu_size == 64) ? 0 :
+		       ((hevc->lcu_size == 32) ? 1 : 2);
+		amvdec_write_dos(core, HEVC_DBLK_CFG1, val);
+	}
+
+	val = amvdec_read_dos(core, HEVC_SAO_CTRL1) & ~0x3ff3;
+	val |= 0xff0; /* Set endianness for 2-bytes swaps (nv12) */
+	if (core->platform->revision < VDEC_REVISION_G12A) {
+		if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit))
+			val |= BIT(0); /* disable cm compression */
+		/* TOFIX: Handle Amlogic Framebuffer compression */
+	}
+
+	amvdec_write_dos(core, HEVC_SAO_CTRL1, val);
+
+	if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
+		/* no downscale for NV12 */
+		val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0000;
+		amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
+	}
+
+	val = amvdec_read_dos(core, HEVCD_IPP_AXIIF_CONFIG) & ~0x30;
+	val |= 0xf;
+	amvdec_write_dos(core, HEVCD_IPP_AXIIF_CONFIG, val);
+
+	val = 0;
+	val_2 = amvdec_read_dos(core, HEVC_SAO_CTRL0);
+	val_2 &= (~0x300);
+
+	slice_deblocking_filter_disabled_flag = (misc_flag0 >>
+			SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & 0x1;
+	if ((misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_BIT)) &&
+	    (misc_flag0 & (1 << DEBLOCKING_FILTER_OVERRIDE_FLAG_BIT))) {
+		val |= slice_deblocking_filter_disabled_flag << 2;
+
+		if (!slice_deblocking_filter_disabled_flag) {
+			val |= (param->p.slice_beta_offset_div2 & 0xf) << 3;
+			val |= (param->p.slice_tc_offset_div2 & 0xf) << 7;
+		}
+	} else {
+		val |=
+			((misc_flag0 >>
+			  PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) & 0x1) << 2;
+
+		if (((misc_flag0 >> PPS_DEBLOCKING_FILTER_DISABLED_FLAG_BIT) &
+			0x1) == 0) {
+			val |= (param->p.pps_beta_offset_div2 & 0xf) << 3;
+			val |= (param->p.pps_tc_offset_div2 & 0xf) << 7;
+		}
+	}
+	if ((misc_flag0 & (1 << PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)) &&
+	    ((misc_flag0 & (1 << SLICE_SAO_LUMA_FLAG_BIT)) ||
+	   (misc_flag0 & (1 << SLICE_SAO_CHROMA_FLAG_BIT)) ||
+	   (!slice_deblocking_filter_disabled_flag))) {
+		val |=
+			((misc_flag0 >>
+			  SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
+			 & 0x1)	<< 1;
+		val_2 |=
+			((misc_flag0 >>
+			  SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
+			& 0x1) << 9;
+	} else {
+		val |=
+			((misc_flag0 >>
+			  PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
+			 & 0x1) << 1;
+		val_2 |=
+			((misc_flag0 >>
+			  PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_BIT)
+			 & 0x1) << 9;
+	}
+
+	amvdec_write_dos(core, HEVC_DBLK_CFG9, val);
+	amvdec_write_dos(core, HEVC_SAO_CTRL0, val_2);
+
+	amvdec_write_dos(core, HEVC_sao_mem_unit, sao_mem_unit);
+	amvdec_write_dos(core, HEVC_SAO_ABV,
+			 hevc->workspace_paddr + SAO_ABV_OFFSET);
+	amvdec_write_dos(core, HEVC_sao_vb_size, sao_vb_size);
+	amvdec_write_dos(core, HEVC_SAO_VB,
+			 hevc->workspace_paddr + SAO_VB_OFFSET);
+}
+
+static dma_addr_t codec_hevc_get_frame_mv_paddr(struct codec_hevc *hevc,
+						struct hevc_frame *frame)
+{
+	return hevc->workspace_paddr + MPRED_MV_OFFSET +
+		(frame->vbuf->vb2_buf.index * MPRED_MV_BUF_SIZE);
+}
+
+static void
+codec_hevc_set_mpred_ctrl(struct amvdec_core *core, struct codec_hevc *hevc)
+{
+	union rpm_param *param = &hevc->rpm_param;
+	u32 slice_type = param->p.slice_type;
+	u32 lcu_size_log2 = ilog2(hevc->lcu_size);
+	u32 val;
+
+	val = slice_type |
+	      MPRED_CTRL0_ABOVE_EN |
+	      MPRED_CTRL0_MV_WR_EN |
+	      MPRED_CTRL0_BUF_LINEAR |
+	      (lcu_size_log2 << 16) |
+	      (3 << 20) | /* cu_size_log2 */
+	      (param->p.log2_parallel_merge_level << 24);
+
+	if (slice_type != I_SLICE)
+		val |= MPRED_CTRL0_MV_RD_EN;
+
+	if (param->p.collocated_from_l0_flag)
+		val |= MPRED_CTRL0_COL_FROM_L0;
+
+	if (param->p.slice_temporal_mvp_enable_flag)
+		val |= MPRED_CTRL0_TMVP;
+
+	if (hevc->ldc_flag)
+		val |= MPRED_CTRL0_LDC;
+
+	if (param->p.dependent_slice_segment_flag)
+		val |= MPRED_CTRL0_NEW_SLI_SEG;
+
+	if (param->p.slice_segment_address == 0)
+		val |= MPRED_CTRL0_NEW_PIC |
+		       MPRED_CTRL0_NEW_TILE;
+
+	amvdec_write_dos(core, HEVC_MPRED_CTRL0, val);
+
+	val = (5 - param->p.five_minus_max_num_merge_cand) |
+	      (AMVP_MAX_NUM_CANDS << 4) |
+	      (AMVP_MAX_NUM_CANDS_MEM << 8) |
+	      (NUM_CHROMA_MODE << 12) |
+	      (DM_CHROMA_IDX << 16);
+	amvdec_write_dos(core, HEVC_MPRED_CTRL1, val);
+}
+
+static void codec_hevc_set_mpred_mv(struct amvdec_core *core,
+				    struct codec_hevc *hevc,
+				    struct hevc_frame *frame,
+				    struct hevc_frame *col_frame)
+{
+	union rpm_param *param = &hevc->rpm_param;
+	u32 lcu_size_log2 = ilog2(hevc->lcu_size);
+	u32 mv_mem_unit = lcu_size_log2 == 6 ? 0x200 :
+			  lcu_size_log2 == 5 ? 0x80 : 0x20;
+	dma_addr_t col_mv_rd_start_addr, col_mv_rd_ptr, col_mv_rd_end_addr;
+	dma_addr_t mpred_mv_wr_ptr;
+
+	amvdec_read_dos(core, HEVC_MPRED_CURR_LCU);
+
+	col_mv_rd_start_addr = codec_hevc_get_frame_mv_paddr(hevc, col_frame);
+	mpred_mv_wr_ptr = codec_hevc_get_frame_mv_paddr(hevc, frame) +
+			  (hevc->slice_addr * mv_mem_unit);
+	col_mv_rd_ptr = col_mv_rd_start_addr +
+			(hevc->slice_addr * mv_mem_unit);
+	col_mv_rd_end_addr = col_mv_rd_start_addr +
+			     (hevc->lcu_total * mv_mem_unit);
+
+	amvdec_write_dos(core, HEVC_MPRED_MV_WR_START_ADDR,
+			 codec_hevc_get_frame_mv_paddr(hevc, frame));
+	amvdec_write_dos(core, HEVC_MPRED_MV_RD_START_ADDR,
+			 col_mv_rd_start_addr);
+
+	if (param->p.slice_segment_address == 0) {
+		amvdec_write_dos(core, HEVC_MPRED_ABV_START_ADDR,
+				 hevc->workspace_paddr + MPRED_ABV_OFFSET);
+		amvdec_write_dos(core, HEVC_MPRED_MV_WPTR, mpred_mv_wr_ptr);
+		amvdec_write_dos(core, HEVC_MPRED_MV_RPTR,
+				 col_mv_rd_start_addr);
+	} else {
+		amvdec_write_dos(core, HEVC_MPRED_MV_RPTR, col_mv_rd_ptr);
+	}
+
+	amvdec_write_dos(core, HEVC_MPRED_MV_RD_END_ADDR, col_mv_rd_end_addr);
+}
+
+/* Update motion prediction with the current slice */
+static void codec_hevc_set_mpred(struct amvdec_session *sess,
+				 struct hevc_frame *frame,
+				 struct hevc_frame *col_frame)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc = sess->priv;
+	u32 *ref_num = frame->ref_num;
+	u32 *ref_poc_l0 = frame->ref_poc_list[0][frame->cur_slice_idx];
+	u32 *ref_poc_l1 = frame->ref_poc_list[1][frame->cur_slice_idx];
+	u32 val;
+	int i;
+
+	codec_hevc_set_mpred_ctrl(core, hevc);
+	codec_hevc_set_mpred_mv(core, hevc, frame, col_frame);
+
+	amvdec_write_dos(core, HEVC_MPRED_PIC_SIZE,
+			 hevc->width | (hevc->height << 16));
+
+	val = ((hevc->lcu_x_num - 1) | (hevc->lcu_y_num - 1) << 16);
+	amvdec_write_dos(core, HEVC_MPRED_PIC_SIZE_LCU, val);
+
+	amvdec_write_dos(core, HEVC_MPRED_REF_NUM,
+			 (ref_num[1] << 8) | ref_num[0]);
+	amvdec_write_dos(core, HEVC_MPRED_REF_EN_L0, (1 << ref_num[0]) - 1);
+	amvdec_write_dos(core, HEVC_MPRED_REF_EN_L1, (1 << ref_num[1]) - 1);
+
+	amvdec_write_dos(core, HEVC_MPRED_CUR_POC, hevc->curr_poc);
+	amvdec_write_dos(core, HEVC_MPRED_COL_POC, hevc->col_poc);
+
+	for (i = 0; i < MAX_REF_ACTIVE; ++i) {
+		amvdec_write_dos(core, HEVC_MPRED_L0_REF00_POC + i * 4,
+				 ref_poc_l0[i]);
+		amvdec_write_dos(core, HEVC_MPRED_L1_REF00_POC + i * 4,
+				 ref_poc_l1[i]);
+	}
+}
+
+/*  motion compensation reference cache controller */
+static void codec_hevc_set_mcrcc(struct amvdec_session *sess)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc = sess->priv;
+	u32 val, val_2;
+	int l0_cnt = 0;
+	int l1_cnt = 0x7fff;
+
+	if (!codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
+		l0_cnt = hevc->cur_frame->ref_num[0];
+		l1_cnt = hevc->cur_frame->ref_num[1];
+	}
+
+	if (hevc->cur_frame->cur_slice_type == I_SLICE) {
+		amvdec_write_dos(core, HEVCD_MCRCC_CTL1, 0);
+		return;
+	}
+
+	if (hevc->cur_frame->cur_slice_type == P_SLICE) {
+		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+				 BIT(1));
+		val = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+		val &= 0xffff;
+		val |= (val << 16);
+		amvdec_write_dos(core, HEVCD_MCRCC_CTL2, val);
+
+		if (l0_cnt == 1) {
+			amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val);
+		} else {
+			val = amvdec_read_dos(core,
+					      HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+			val &= 0xffff;
+			val |= (val << 16);
+			amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val);
+		}
+	} else { /* B_SLICE */
+		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 0);
+		val = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+		val &= 0xffff;
+		val |= (val << 16);
+		amvdec_write_dos(core, HEVCD_MCRCC_CTL2, val);
+
+		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+				 BIT(12) | BIT(1));
+		val_2 = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+		val_2 &= 0xffff;
+		val_2 |= (val_2 << 16);
+		if (val == val_2 && l1_cnt > 1) {
+			val_2 = amvdec_read_dos(core,
+						HEVCD_MPP_ANC_CANVAS_DATA_ADDR);
+			val_2 &= 0xffff;
+			val_2 |= (val_2 << 16);
+		}
+		amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val);
+	}
+
+	/* enable mcrcc progressive-mode */
+	amvdec_write_dos(core, HEVCD_MCRCC_CTL1, 0xff0);
+}
+
+static void codec_hevc_set_ref_list(struct amvdec_session *sess,
+				    u32 ref_num, u32 *ref_poc_list)
+{
+	struct codec_hevc *hevc = sess->priv;
+	struct hevc_frame *ref_frame;
+	struct amvdec_core *core = sess->core;
+	int i;
+	u32 buf_id_y;
+	u32 buf_id_uv;
+
+	for (i = 0; i < ref_num; i++) {
+		ref_frame = codec_hevc_get_frame_by_poc(hevc, ref_poc_list[i]);
+
+		if (!ref_frame) {
+			dev_warn(core->dev, "Couldn't find ref. frame %u\n",
+				 ref_poc_list[i]);
+			continue;
+		}
+
+		if (codec_hevc_use_fbc(sess->pixfmt_cap, hevc->is_10bit)) {
+			buf_id_y = ref_frame->vbuf->vb2_buf.index;
+			buf_id_uv = buf_id_y;
+		} else {
+			buf_id_y = ref_frame->vbuf->vb2_buf.index * 2;
+			buf_id_uv = buf_id_y + 1;
+		}
+
+		amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
+				 (buf_id_uv << 16) |
+				 (buf_id_uv << 8) |
+				 buf_id_y);
+	}
+}
+
+static void codec_hevc_set_mc(struct amvdec_session *sess,
+			      struct hevc_frame *frame)
+{
+	struct amvdec_core *core = sess->core;
+
+	if (frame->cur_slice_type == I_SLICE)
+		return;
+
+	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
+	codec_hevc_set_ref_list(sess, frame->ref_num[0],
+				frame->ref_poc_list[0][frame->cur_slice_idx]);
+
+	if (frame->cur_slice_type == P_SLICE)
+		return;
+
+	amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
+			 BIT(12) | BIT(0));
+	codec_hevc_set_ref_list(sess, frame->ref_num[1],
+				frame->ref_poc_list[1][frame->cur_slice_idx]);
+}
+
+static void codec_hevc_update_col_frame(struct codec_hevc *hevc)
+{
+	struct hevc_frame *cur_frame = hevc->cur_frame;
+	union rpm_param *param = &hevc->rpm_param;
+	u32 list_no = 0;
+	u32 col_ref = param->p.collocated_ref_idx;
+	u32 col_from_l0 = param->p.collocated_from_l0_flag;
+	u32 cur_slice_idx = cur_frame->cur_slice_idx;
+
+	if (cur_frame->cur_slice_type == B_SLICE)
+		list_no = 1 - col_from_l0;
+
+	if (col_ref >= cur_frame->ref_num[list_no])
+		hevc->col_poc = INVALID_POC;
+	else
+		hevc->col_poc = cur_frame->ref_poc_list[list_no]
+						       [cur_slice_idx]
+						       [col_ref];
+
+	if (cur_frame->cur_slice_type == I_SLICE)
+		goto end;
+
+	if (hevc->col_poc != INVALID_POC)
+		hevc->col_frame = codec_hevc_get_frame_by_poc(hevc,
+							      hevc->col_poc);
+	else
+		hevc->col_frame = hevc->cur_frame;
+
+end:
+	if (!hevc->col_frame)
+		hevc->col_frame = hevc->cur_frame;
+}
+
+static void codec_hevc_update_pocs(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	union rpm_param *param = &hevc->rpm_param;
+	u32 nal_unit_type = param->p.m_nalUnitType;
+	u32 temporal_id = param->p.m_temporalId & 0x7;
+	int max_poc_lsb =
+		1 << (param->p.log2_max_pic_order_cnt_lsb_minus4 + 4);
+	int prev_poc_lsb;
+	int prev_poc_msb;
+	int poc_msb;
+	int poc_lsb = param->p.POClsb;
+
+	if (nal_unit_type == NAL_UNIT_CODED_SLICE_IDR ||
+	    nal_unit_type == NAL_UNIT_CODED_SLICE_IDR_N_LP) {
+		hevc->curr_poc = 0;
+		if ((temporal_id - 1) == 0)
+			hevc->prev_tid0_poc = hevc->curr_poc;
+
+		return;
+	}
+
+	prev_poc_lsb = hevc->prev_tid0_poc % max_poc_lsb;
+	prev_poc_msb = hevc->prev_tid0_poc - prev_poc_lsb;
+
+	if ((poc_lsb < prev_poc_lsb) &&
+	    ((prev_poc_lsb - poc_lsb) >= (max_poc_lsb / 2)))
+		poc_msb = prev_poc_msb + max_poc_lsb;
+	else if ((poc_lsb > prev_poc_lsb) &&
+		 ((poc_lsb - prev_poc_lsb) > (max_poc_lsb / 2)))
+		poc_msb = prev_poc_msb - max_poc_lsb;
+	else
+		poc_msb = prev_poc_msb;
+
+	if (nal_unit_type == NAL_UNIT_CODED_SLICE_BLA   ||
+	    nal_unit_type == NAL_UNIT_CODED_SLICE_BLANT ||
+	    nal_unit_type == NAL_UNIT_CODED_SLICE_BLA_N_LP)
+		poc_msb = 0;
+
+	hevc->curr_poc = (poc_msb + poc_lsb);
+	if ((temporal_id - 1) == 0)
+		hevc->prev_tid0_poc = hevc->curr_poc;
+}
+
+static void codec_hevc_process_segment_header(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	union rpm_param *param = &hevc->rpm_param;
+
+	if (param->p.first_slice_segment_in_pic_flag == 0) {
+		hevc->slice_segment_addr = param->p.slice_segment_address;
+		if (!param->p.dependent_slice_segment_flag)
+			hevc->slice_addr = hevc->slice_segment_addr;
+	} else {
+		hevc->slice_segment_addr = 0;
+		hevc->slice_addr = 0;
+	}
+
+	codec_hevc_update_pocs(sess);
+}
+
+static int codec_hevc_process_segment(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	struct amvdec_core *core = sess->core;
+	union rpm_param *param = &hevc->rpm_param;
+	u32 slice_segment_address = param->p.slice_segment_address;
+
+	/* First slice: new frame */
+	if (slice_segment_address == 0) {
+		codec_hevc_update_referenced(hevc);
+		codec_hevc_show_frames(sess);
+
+		hevc->cur_frame = codec_hevc_prepare_new_frame(sess);
+		if (!hevc->cur_frame)
+			return -1;
+	} else {
+		hevc->cur_frame->cur_slice_idx++;
+	}
+
+	codec_hevc_update_frame_refs(sess, hevc->cur_frame);
+	codec_hevc_update_col_frame(hevc);
+	codec_hevc_update_ldc_flag(hevc);
+	if (codec_hevc_use_mmu(core->platform->revision, sess->pixfmt_cap,
+			       hevc->is_10bit))
+		codec_hevc_fill_mmu_map(sess, &hevc->common,
+					&hevc->cur_frame->vbuf->vb2_buf,
+					hevc->is_10bit);
+	codec_hevc_set_mc(sess, hevc->cur_frame);
+	codec_hevc_set_mcrcc(sess);
+	codec_hevc_set_mpred(sess, hevc->cur_frame, hevc->col_frame);
+	codec_hevc_set_sao(sess, hevc->cur_frame);
+
+	amvdec_write_dos_bits(core, HEVC_WAIT_FLAG, BIT(1));
+	amvdec_write_dos(core, HEVC_DEC_STATUS_REG,
+			 HEVC_CODED_SLICE_SEGMENT_DAT);
+
+	/* Interrupt the firmware's processor */
+	amvdec_write_dos(core, HEVC_MCPU_INTR_REQ, AMRISC_MAIN_REQ);
+
+	return 0;
+}
+
+static int codec_hevc_process_rpm(struct codec_hevc *hevc)
+{
+	union rpm_param *param = &hevc->rpm_param;
+	int src_changed = 0;
+	u32 dst_width, dst_height;
+	u32 lcu_size;
+	u32 is_10bit = 0;
+
+	if (param->p.slice_segment_address	||
+	    !param->p.pic_width_in_luma_samples	||
+	    !param->p.pic_height_in_luma_samples)
+		return 0;
+
+	if (param->p.bit_depth)
+		is_10bit = 1;
+
+	hevc->width = param->p.pic_width_in_luma_samples;
+	hevc->height = param->p.pic_height_in_luma_samples;
+	dst_width = hevc->width;
+	dst_height = hevc->height;
+
+	lcu_size = 1 << (param->p.log2_min_coding_block_size_minus3 +
+		   3 + param->p.log2_diff_max_min_coding_block_size);
+
+	hevc->lcu_x_num = (hevc->width + lcu_size - 1) / lcu_size;
+	hevc->lcu_y_num = (hevc->height + lcu_size - 1) / lcu_size;
+	hevc->lcu_total = hevc->lcu_x_num * hevc->lcu_y_num;
+
+	if (param->p.conformance_window_flag) {
+		u32 sub_width = 1, sub_height = 1;
+
+		switch (param->p.chroma_format_idc) {
+		case 1:
+			sub_height = 2;
+			fallthrough;
+		case 2:
+			sub_width = 2;
+			break;
+		}
+
+		dst_width -= sub_width *
+			     (param->p.conf_win_left_offset +
+			      param->p.conf_win_right_offset);
+		dst_height -= sub_height *
+			      (param->p.conf_win_top_offset +
+			       param->p.conf_win_bottom_offset);
+	}
+
+	if (dst_width != hevc->dst_width ||
+	    dst_height != hevc->dst_height ||
+	    lcu_size != hevc->lcu_size ||
+	    is_10bit != hevc->is_10bit)
+		src_changed = 1;
+
+	hevc->dst_width = dst_width;
+	hevc->dst_height = dst_height;
+	hevc->lcu_size = lcu_size;
+	hevc->is_10bit = is_10bit;
+
+	return src_changed;
+}
+
+/*
+ * The RPM section within the workspace contains
+ * many information regarding the parsed bitstream
+ */
+static void codec_hevc_fetch_rpm(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+	u16 *rpm_vaddr = hevc->workspace_vaddr + RPM_OFFSET;
+	int i, j;
+
+	for (i = 0; i < RPM_SIZE; i += 4) {
+		for (j = 0; j < 4; j++)
+			hevc->rpm_param.l.data[i + j] =
+				rpm_vaddr[i + 3 - j];
+	}
+}
+
+static void codec_hevc_resume(struct amvdec_session *sess)
+{
+	struct codec_hevc *hevc = sess->priv;
+
+	if (codec_hevc_setup_buffers(sess, &hevc->common, hevc->is_10bit)) {
+		amvdec_abort(sess);
+		return;
+	}
+
+	codec_hevc_setup_decode_head(sess, hevc->is_10bit);
+	codec_hevc_process_segment_header(sess);
+	if (codec_hevc_process_segment(sess))
+		amvdec_abort(sess);
+}
+
+static irqreturn_t codec_hevc_threaded_isr(struct amvdec_session *sess)
+{
+	struct amvdec_core *core = sess->core;
+	struct codec_hevc *hevc = sess->priv;
+	u32 dec_status = amvdec_read_dos(core, HEVC_DEC_STATUS_REG);
+
+	if (!hevc)
+		return IRQ_HANDLED;
+
+	mutex_lock(&hevc->lock);
+	if (dec_status != HEVC_SLICE_SEGMENT_DONE) {
+		dev_err(core->dev_dec, "Unrecognized dec_status: %08X\n",
+			dec_status);
+		amvdec_abort(sess);
+		goto unlock;
+	}
+
+	sess->keyframe_found = 1;
+	codec_hevc_fetch_rpm(sess);
+	if (codec_hevc_process_rpm(hevc)) {
+		amvdec_src_change(sess, hevc->dst_width, hevc->dst_height, 16,
+				  hevc->is_10bit ? 10 : 8);
+		goto unlock;
+	}
+
+	codec_hevc_process_segment_header(sess);
+	if (codec_hevc_process_segment(sess))
+		amvdec_abort(sess);
+
+unlock:
+	mutex_unlock(&hevc->lock);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t codec_hevc_isr(struct amvdec_session *sess)
+{
+	return IRQ_WAKE_THREAD;
+}
+
+struct amvdec_codec_ops codec_hevc_ops = {
+	.start = codec_hevc_start,
+	.stop = codec_hevc_stop,
+	.isr = codec_hevc_isr,
+	.threaded_isr = codec_hevc_threaded_isr,
+	.num_pending_bufs = codec_hevc_num_pending_bufs,
+	.drain = codec_hevc_flush_output,
+	.resume = codec_hevc_resume,
+};
diff --git a/drivers/staging/media/meson/vdec/codec_hevc.h b/drivers/staging/media/meson/vdec/codec_hevc.h
new file mode 100644
index 000000000000..f2f9b2464df1
--- /dev/null
+++ b/drivers/staging/media/meson/vdec/codec_hevc.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Maxime Jourdan <maxi.jourdan@wanadoo.fr>
+ */
+
+#ifndef __MESON_VDEC_CODEC_HEVC_H_
+#define __MESON_VDEC_CODEC_HEVC_H_
+
+#include "vdec.h"
+
+extern struct amvdec_codec_ops codec_hevc_ops;
+
+#endif
diff --git a/drivers/staging/media/meson/vdec/esparser.c b/drivers/staging/media/meson/vdec/esparser.c
index 3cd29ab4f979..6988348ce714 100644
--- a/drivers/staging/media/meson/vdec/esparser.c
+++ b/drivers/staging/media/meson/vdec/esparser.c
@@ -310,7 +310,8 @@ esparser_queue(struct amvdec_session *sess, struct vb2_v4l2_buffer *vbuf)
 	 * they could pause when there is no capture buffer available and
 	 * resume on this notification.
 	 */
-	if (sess->fmt_out->pixfmt == V4L2_PIX_FMT_VP9) {
+	if (sess->fmt_out->pixfmt == V4L2_PIX_FMT_VP9 ||
+	    sess->fmt_out->pixfmt == V4L2_PIX_FMT_HEVC) {
 		if (codec_ops->num_pending_bufs)
 			num_dst_bufs = codec_ops->num_pending_bufs(sess);
 
diff --git a/drivers/staging/media/meson/vdec/hevc_regs.h b/drivers/staging/media/meson/vdec/hevc_regs.h
index 0392f41a1eed..e7eabdd2b119 100644
--- a/drivers/staging/media/meson/vdec/hevc_regs.h
+++ b/drivers/staging/media/meson/vdec/hevc_regs.h
@@ -205,6 +205,7 @@
 #define HEVC_CM_HEADER_START_ADDR 0xd8a0
 #define HEVC_CM_HEADER_LENGTH 0xd8a4
 #define HEVC_CM_HEADER_OFFSET 0xd8ac
+#define HEVC_SAO_CTRL9 0xd8b4
 #define HEVC_SAO_MMU_VH0_ADDR 0xd8e8
 #define HEVC_SAO_MMU_VH1_ADDR 0xd8ec
 
diff --git a/drivers/staging/media/meson/vdec/vdec_platform.c b/drivers/staging/media/meson/vdec/vdec_platform.c
index 88c9d72e1c83..ea2aa0e8cf0b 100644
--- a/drivers/staging/media/meson/vdec/vdec_platform.c
+++ b/drivers/staging/media/meson/vdec/vdec_platform.c
@@ -11,10 +11,23 @@
 #include "vdec_hevc.h"
 #include "codec_mpeg12.h"
 #include "codec_h264.h"
+#include "codec_hevc.h"
 #include "codec_vp9.h"
 
 static const struct amvdec_format vdec_formats_gxbb[] = {
 	{
+		.pixfmt = V4L2_PIX_FMT_HEVC,
+		.min_buffers = 4,
+		.max_buffers = 24,
+		.max_width = 3840,
+		.max_height = 2160,
+		.vdec_ops = &vdec_hevc_ops,
+		.codec_ops = &codec_hevc_ops,
+		.firmware_path = "meson/vdec/gxl_hevc.bin",
+		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+		.flags = V4L2_FMT_FLAG_COMPRESSED |
+			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+	}, {
 		.pixfmt = V4L2_PIX_FMT_H264,
 		.min_buffers = 2,
 		.max_buffers = 24,
@@ -64,6 +77,18 @@ static const struct amvdec_format vdec_formats_gxl[] = {
 		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
 		.flags = V4L2_FMT_FLAG_COMPRESSED |
 			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+	}, {
+		.pixfmt = V4L2_PIX_FMT_HEVC,
+		.min_buffers = 4,
+		.max_buffers = 24,
+		.max_width = 3840,
+		.max_height = 2160,
+		.vdec_ops = &vdec_hevc_ops,
+		.codec_ops = &codec_hevc_ops,
+		.firmware_path = "meson/vdec/gxl_hevc.bin",
+		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+		.flags = V4L2_FMT_FLAG_COMPRESSED |
+			 V4L2_FMT_FLAG_DYN_RESOLUTION,
 	}, {
 		.pixfmt = V4L2_PIX_FMT_H264,
 		.min_buffers = 2,
@@ -114,6 +139,18 @@ static const struct amvdec_format vdec_formats_gxm[] = {
 		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
 		.flags = V4L2_FMT_FLAG_COMPRESSED |
 			 V4L2_FMT_FLAG_DYN_RESOLUTION,
+	}, {
+		.pixfmt = V4L2_PIX_FMT_HEVC,
+		.min_buffers = 4,
+		.max_buffers = 24,
+		.max_width = 3840,
+		.max_height = 2160,
+		.vdec_ops = &vdec_hevc_ops,
+		.codec_ops = &codec_hevc_ops,
+		.firmware_path = "meson/vdec/gxl_hevc.bin",
+		.pixfmts_cap = { V4L2_PIX_FMT_NV12M, 0 },
+		.flags = V4L2_FMT_FLAG_COMPRESSED |
+			 V4L2_FMT_FLAG_DYN_RESOLUTION,
 	}, {
 		.pixfmt = V4L2_PIX_FMT_H264,
 		.min_buffers = 2,
-- 
2.34.1


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Re: [PATCH v2 2/2] media: meson: vdec: add HEVC decode codec

[Dan Carpenter]

Hi Christian,

https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Christian-Hewitt/media-meson-vdec-implement-10bit-bitstream-handling/20230124-114201
base:   git://linuxtv.org/media_tree.git master
patch link:    https://lore.kernel.org/r/20230124034058.3407235-3-christianshewitt%40gmail.com
patch subject: [PATCH v2 2/2] media: meson: vdec: add HEVC decode codec
config: s390-randconfig-m031-20230310 (https://download.01.org/0day-ci/archive/20230312/202303120441.YFGHDOya-lkp@intel.com/config)
compiler: s390-linux-gcc (GCC) 12.1.0

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Link: https://lore.kernel.org/r/202303120441.YFGHDOya-lkp@intel.com/

smatch warnings:
drivers/staging/media/meson/vdec/codec_hevc.c:734 codec_hevc_prepare_new_frame() warn: possible memory leak of 'new_frame'

vim +/new_frame +734 drivers/staging/media/meson/vdec/codec_hevc.c

015f7814a5a991 Maxime Jourdan 2023-01-24  718  static struct hevc_frame *
015f7814a5a991 Maxime Jourdan 2023-01-24  719  codec_hevc_prepare_new_frame(struct amvdec_session *sess)
015f7814a5a991 Maxime Jourdan 2023-01-24  720  {
015f7814a5a991 Maxime Jourdan 2023-01-24  721  	struct amvdec_core *core = sess->core;
015f7814a5a991 Maxime Jourdan 2023-01-24  722  	struct hevc_frame *new_frame = NULL;
015f7814a5a991 Maxime Jourdan 2023-01-24  723  	struct codec_hevc *hevc = sess->priv;
015f7814a5a991 Maxime Jourdan 2023-01-24  724  	struct vb2_v4l2_buffer *vbuf;
015f7814a5a991 Maxime Jourdan 2023-01-24  725  	union rpm_param *params = &hevc->rpm_param;
015f7814a5a991 Maxime Jourdan 2023-01-24  726  
015f7814a5a991 Maxime Jourdan 2023-01-24  727  	new_frame = kzalloc(sizeof(*new_frame), GFP_KERNEL);
015f7814a5a991 Maxime Jourdan 2023-01-24  728  	if (!new_frame)
015f7814a5a991 Maxime Jourdan 2023-01-24  729  		return NULL;
015f7814a5a991 Maxime Jourdan 2023-01-24  730  
015f7814a5a991 Maxime Jourdan 2023-01-24  731  	vbuf = v4l2_m2m_dst_buf_remove(sess->m2m_ctx);
015f7814a5a991 Maxime Jourdan 2023-01-24  732  	if (!vbuf) {
015f7814a5a991 Maxime Jourdan 2023-01-24  733  		dev_err(sess->core->dev, "No dst buffer available\n");
015f7814a5a991 Maxime Jourdan 2023-01-24 @734  		return NULL;

kfree(new_frame);

015f7814a5a991 Maxime Jourdan 2023-01-24  735  	}
015f7814a5a991 Maxime Jourdan 2023-01-24  736  
015f7814a5a991 Maxime Jourdan 2023-01-24  737  	new_frame->vbuf = vbuf;
015f7814a5a991 Maxime Jourdan 2023-01-24  738  	new_frame->referenced = 1;
015f7814a5a991 Maxime Jourdan 2023-01-24  739  	new_frame->show = 1;
015f7814a5a991 Maxime Jourdan 2023-01-24  740  	new_frame->poc = hevc->curr_poc;
015f7814a5a991 Maxime Jourdan 2023-01-24  741  	new_frame->cur_slice_type = params->p.slice_type;
015f7814a5a991 Maxime Jourdan 2023-01-24  742  	new_frame->num_reorder_pic = params->p.sps_num_reorder_pics_0;
015f7814a5a991 Maxime Jourdan 2023-01-24  743  	new_frame->offset = amvdec_read_dos(core, HEVC_SHIFT_BYTE_COUNT);
015f7814a5a991 Maxime Jourdan 2023-01-24  744  
015f7814a5a991 Maxime Jourdan 2023-01-24  745  	list_add_tail(&new_frame->list, &hevc->ref_frames_list);
015f7814a5a991 Maxime Jourdan 2023-01-24  746  	hevc->frames_num++;
015f7814a5a991 Maxime Jourdan 2023-01-24  747  
015f7814a5a991 Maxime Jourdan 2023-01-24  748  	return new_frame;
015f7814a5a991 Maxime Jourdan 2023-01-24  749  }

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests

Re: [PATCH v2 2/2] media: meson: vdec: add HEVC decode codec

[Dan Carpenter]

Hi Christian,

https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Christian-Hewitt/media-meson-vdec-implement-10bit-bitstream-handling/20230124-114201
base:   git://linuxtv.org/media_tree.git master
patch link:    https://lore.kernel.org/r/20230124034058.3407235-3-christianshewitt%40gmail.com
patch subject: [PATCH v2 2/2] media: meson: vdec: add HEVC decode codec
config: s390-randconfig-m031-20230310 (https://download.01.org/0day-ci/archive/20230312/202303120441.YFGHDOya-lkp@intel.com/config)
compiler: s390-linux-gcc (GCC) 12.1.0

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Link: https://lore.kernel.org/r/202303120441.YFGHDOya-lkp@intel.com/

smatch warnings:
drivers/staging/media/meson/vdec/codec_hevc.c:734 codec_hevc_prepare_new_frame() warn: possible memory leak of 'new_frame'

vim +/new_frame +734 drivers/staging/media/meson/vdec/codec_hevc.c

015f7814a5a991 Maxime Jourdan 2023-01-24  718  static struct hevc_frame *
015f7814a5a991 Maxime Jourdan 2023-01-24  719  codec_hevc_prepare_new_frame(struct amvdec_session *sess)
015f7814a5a991 Maxime Jourdan 2023-01-24  720  {
015f7814a5a991 Maxime Jourdan 2023-01-24  721  	struct amvdec_core *core = sess->core;
015f7814a5a991 Maxime Jourdan 2023-01-24  722  	struct hevc_frame *new_frame = NULL;
015f7814a5a991 Maxime Jourdan 2023-01-24  723  	struct codec_hevc *hevc = sess->priv;
015f7814a5a991 Maxime Jourdan 2023-01-24  724  	struct vb2_v4l2_buffer *vbuf;
015f7814a5a991 Maxime Jourdan 2023-01-24  725  	union rpm_param *params = &hevc->rpm_param;
015f7814a5a991 Maxime Jourdan 2023-01-24  726  
015f7814a5a991 Maxime Jourdan 2023-01-24  727  	new_frame = kzalloc(sizeof(*new_frame), GFP_KERNEL);
015f7814a5a991 Maxime Jourdan 2023-01-24  728  	if (!new_frame)
015f7814a5a991 Maxime Jourdan 2023-01-24  729  		return NULL;
015f7814a5a991 Maxime Jourdan 2023-01-24  730  
015f7814a5a991 Maxime Jourdan 2023-01-24  731  	vbuf = v4l2_m2m_dst_buf_remove(sess->m2m_ctx);
015f7814a5a991 Maxime Jourdan 2023-01-24  732  	if (!vbuf) {
015f7814a5a991 Maxime Jourdan 2023-01-24  733  		dev_err(sess->core->dev, "No dst buffer available\n");
015f7814a5a991 Maxime Jourdan 2023-01-24 @734  		return NULL;

kfree(new_frame);

015f7814a5a991 Maxime Jourdan 2023-01-24  735  	}
015f7814a5a991 Maxime Jourdan 2023-01-24  736  
015f7814a5a991 Maxime Jourdan 2023-01-24  737  	new_frame->vbuf = vbuf;
015f7814a5a991 Maxime Jourdan 2023-01-24  738  	new_frame->referenced = 1;
015f7814a5a991 Maxime Jourdan 2023-01-24  739  	new_frame->show = 1;
015f7814a5a991 Maxime Jourdan 2023-01-24  740  	new_frame->poc = hevc->curr_poc;
015f7814a5a991 Maxime Jourdan 2023-01-24  741  	new_frame->cur_slice_type = params->p.slice_type;
015f7814a5a991 Maxime Jourdan 2023-01-24  742  	new_frame->num_reorder_pic = params->p.sps_num_reorder_pics_0;
015f7814a5a991 Maxime Jourdan 2023-01-24  743  	new_frame->offset = amvdec_read_dos(core, HEVC_SHIFT_BYTE_COUNT);
015f7814a5a991 Maxime Jourdan 2023-01-24  744  
015f7814a5a991 Maxime Jourdan 2023-01-24  745  	list_add_tail(&new_frame->list, &hevc->ref_frames_list);
015f7814a5a991 Maxime Jourdan 2023-01-24  746  	hevc->frames_num++;
015f7814a5a991 Maxime Jourdan 2023-01-24  747  
015f7814a5a991 Maxime Jourdan 2023-01-24  748  	return new_frame;
015f7814a5a991 Maxime Jourdan 2023-01-24  749  }

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v2 2/2] media: meson: vdec: add HEVC decode codec

[Dan Carpenter]

Hi Christian,

https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Christian-Hewitt/media-meson-vdec-implement-10bit-bitstream-handling/20230124-114201
base:   git://linuxtv.org/media_tree.git master
patch link:    https://lore.kernel.org/r/20230124034058.3407235-3-christianshewitt%40gmail.com
patch subject: [PATCH v2 2/2] media: meson: vdec: add HEVC decode codec
config: s390-randconfig-m031-20230310 (https://download.01.org/0day-ci/archive/20230312/202303120441.YFGHDOya-lkp@intel.com/config)
compiler: s390-linux-gcc (GCC) 12.1.0

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <error27@gmail.com>
| Link: https://lore.kernel.org/r/202303120441.YFGHDOya-lkp@intel.com/

smatch warnings:
drivers/staging/media/meson/vdec/codec_hevc.c:734 codec_hevc_prepare_new_frame() warn: possible memory leak of 'new_frame'

vim +/new_frame +734 drivers/staging/media/meson/vdec/codec_hevc.c

015f7814a5a991 Maxime Jourdan 2023-01-24  718  static struct hevc_frame *
015f7814a5a991 Maxime Jourdan 2023-01-24  719  codec_hevc_prepare_new_frame(struct amvdec_session *sess)
015f7814a5a991 Maxime Jourdan 2023-01-24  720  {
015f7814a5a991 Maxime Jourdan 2023-01-24  721  	struct amvdec_core *core = sess->core;
015f7814a5a991 Maxime Jourdan 2023-01-24  722  	struct hevc_frame *new_frame = NULL;
015f7814a5a991 Maxime Jourdan 2023-01-24  723  	struct codec_hevc *hevc = sess->priv;
015f7814a5a991 Maxime Jourdan 2023-01-24  724  	struct vb2_v4l2_buffer *vbuf;
015f7814a5a991 Maxime Jourdan 2023-01-24  725  	union rpm_param *params = &hevc->rpm_param;
015f7814a5a991 Maxime Jourdan 2023-01-24  726  
015f7814a5a991 Maxime Jourdan 2023-01-24  727  	new_frame = kzalloc(sizeof(*new_frame), GFP_KERNEL);
015f7814a5a991 Maxime Jourdan 2023-01-24  728  	if (!new_frame)
015f7814a5a991 Maxime Jourdan 2023-01-24  729  		return NULL;
015f7814a5a991 Maxime Jourdan 2023-01-24  730  
015f7814a5a991 Maxime Jourdan 2023-01-24  731  	vbuf = v4l2_m2m_dst_buf_remove(sess->m2m_ctx);
015f7814a5a991 Maxime Jourdan 2023-01-24  732  	if (!vbuf) {
015f7814a5a991 Maxime Jourdan 2023-01-24  733  		dev_err(sess->core->dev, "No dst buffer available\n");
015f7814a5a991 Maxime Jourdan 2023-01-24 @734  		return NULL;

kfree(new_frame);

015f7814a5a991 Maxime Jourdan 2023-01-24  735  	}
015f7814a5a991 Maxime Jourdan 2023-01-24  736  
015f7814a5a991 Maxime Jourdan 2023-01-24  737  	new_frame->vbuf = vbuf;
015f7814a5a991 Maxime Jourdan 2023-01-24  738  	new_frame->referenced = 1;
015f7814a5a991 Maxime Jourdan 2023-01-24  739  	new_frame->show = 1;
015f7814a5a991 Maxime Jourdan 2023-01-24  740  	new_frame->poc = hevc->curr_poc;
015f7814a5a991 Maxime Jourdan 2023-01-24  741  	new_frame->cur_slice_type = params->p.slice_type;
015f7814a5a991 Maxime Jourdan 2023-01-24  742  	new_frame->num_reorder_pic = params->p.sps_num_reorder_pics_0;
015f7814a5a991 Maxime Jourdan 2023-01-24  743  	new_frame->offset = amvdec_read_dos(core, HEVC_SHIFT_BYTE_COUNT);
015f7814a5a991 Maxime Jourdan 2023-01-24  744  
015f7814a5a991 Maxime Jourdan 2023-01-24  745  	list_add_tail(&new_frame->list, &hevc->ref_frames_list);
015f7814a5a991 Maxime Jourdan 2023-01-24  746  	hevc->frames_num++;
015f7814a5a991 Maxime Jourdan 2023-01-24  747  
015f7814a5a991 Maxime Jourdan 2023-01-24  748  	return new_frame;
015f7814a5a991 Maxime Jourdan 2023-01-24  749  }

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests


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