* [Intel-gfx] [PATCH 0/3] Drop TGL/DG1 workarounds for pre-prod steppings
@ 2023-01-27 22:43 Matt Roper
2023-01-27 22:43 ` [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings Matt Roper
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Matt Roper @ 2023-01-27 22:43 UTC (permalink / raw)
To: intel-gfx
As described in the comment on intel_detect_preproduction_hw(),
Our policy for removing pre-production workarounds is to keep the
current gen workarounds as a guide to the bring-up of the next gen
(workarounds have a habit of persisting!). Anything older than that
should be removed along with the complications they introduce.
TGL and DG1 are well past the point where we should move forward with
removing the hardware workarounds specific to internal/pre-production
hardware.
JSL/EHL appear to have productized A0 hardware, so all workarounds for
those platforms will stay in the driver forever. We can probably remove
some pre-production workarounds for RKL and ADL at this point as well,
but the bspec doesn't have details about which steppings were only used
in pre-production, so we'll need to track down that information later.
Matt Roper (3):
drm/i915/tgl: Drop support for pre-production steppings
drm/i915/dg1: Drop support for pre-production steppings
drm/i915/dg1: Drop final use of IS_DG1_GRAPHICS_STEP
.../drm/i915/display/intel_display_power.c | 6 +-
drivers/gpu/drm/i915/display/intel_psr.c | 26 ------
.../drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 86 +------------------
drivers/gpu/drm/i915/i915_driver.c | 2 +
drivers/gpu/drm/i915/i915_drv.h | 13 ---
drivers/gpu/drm/i915/intel_pm.c | 16 ----
8 files changed, 10 insertions(+), 143 deletions(-)
--
2.39.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings
2023-01-27 22:43 [Intel-gfx] [PATCH 0/3] Drop TGL/DG1 workarounds for pre-prod steppings Matt Roper
@ 2023-01-27 22:43 ` Matt Roper
2023-01-30 15:46 ` Rodrigo Vivi
2023-01-27 22:43 ` [Intel-gfx] [PATCH 2/3] drm/i915/dg1: " Matt Roper
` (3 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Matt Roper @ 2023-01-27 22:43 UTC (permalink / raw)
To: intel-gfx
Several post-TGL platforms have been brought up now, so we're well past
the point where we usually drop the workarounds that are only applicable
to internal/pre-production hardware.
Production TGL hardware always has display stepping C0 or later and GT
stepping B0 or later (this is true for both the original TGL and the U/Y
subplatform).
Bspec 44455
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../drm/i915/display/intel_display_power.c | 5 +--
drivers/gpu/drm/i915/display/intel_psr.c | 26 -----------
.../drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 ++-----------------
drivers/gpu/drm/i915/i915_driver.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 8 ----
drivers/gpu/drm/i915/intel_pm.c | 4 --
7 files changed, 7 insertions(+), 83 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1a23ecd4623a..1dc31f0f5e0a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1581,9 +1581,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
if (IS_ALDERLAKE_S(dev_priv) ||
IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
- IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
- IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
- /* Wa_1409767108:tgl,dg1,adl-s */
+ IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ /* Wa_1409767108 */
table = wa_1409767108_buddy_page_masks;
else
table = tgl_buddy_page_masks;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7d4a15a283a0..5dca58dd97a9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -591,12 +591,6 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
if (intel_dp->psr.psr2_sel_fetch_enabled) {
u32 tmp;
- /* Wa_1408330847 */
- if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
- DIS_RAM_BYPASS_PSR2_MAN_TRACK,
- DIS_RAM_BYPASS_PSR2_MAN_TRACK);
-
tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
} else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
@@ -765,13 +759,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
return false;
}
- /* Wa_14010254185 Wa_14010103792 */
- if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
- drm_dbg_kms(&dev_priv->drm,
- "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
- return false;
- }
-
return crtc_state->enable_psr2_sel_fetch = true;
}
@@ -945,13 +932,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
}
}
- /* Wa_2209313811 */
- if (!crtc_state->enable_psr2_sel_fetch &&
- IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
- drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
- goto unsupported;
- }
-
if (!psr2_granularity_check(intel_dp, crtc_state)) {
drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
goto unsupported;
@@ -1360,12 +1340,6 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
intel_psr_exit(intel_dp);
intel_psr_wait_exit_locked(intel_dp);
- /* Wa_1408330847 */
- if (intel_dp->psr.psr2_sel_fetch_enabled &&
- IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
- DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
-
/*
* Wa_16013835468
* Wa_14015648006
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 9b172a1e90de..e956edb87398 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2180,7 +2180,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
if (DISPLAY_VER(i915) < 12)
return false;
- /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
+ /* Wa_14010477008 */
if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
return false;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4efc1a532982..82a8f372bde6 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1456,31 +1456,6 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
}
-static void
-tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
-{
- struct drm_i915_private *i915 = gt->i915;
-
- gen12_gt_workarounds_init(gt, wal);
-
- /* Wa_1409420604:tgl */
- if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
- wa_mcr_write_or(wal,
- SUBSLICE_UNIT_LEVEL_CLKGATE2,
- CPSSUNIT_CLKGATE_DIS);
-
- /* Wa_1607087056:tgl also know as BUG:1409180338 */
- if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
- wa_write_or(wal,
- GEN11_SLICE_UNIT_LEVEL_CLKGATE,
- L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
-
- /* Wa_1408615072:tgl[a0] */
- if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
- wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
- VSUNIT_CLKGATE_DIS_TGL);
-}
-
static void
dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
{
@@ -1716,8 +1691,6 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
xehpsdv_gt_workarounds_init(gt, wal);
else if (IS_DG1(i915))
dg1_gt_workarounds_init(gt, wal);
- else if (IS_TIGERLAKE(i915))
- tgl_gt_workarounds_init(gt, wal);
else if (GRAPHICS_VER(i915) == 12)
gen12_gt_workarounds_init(gt, wal);
else if (GRAPHICS_VER(i915) == 11)
@@ -2437,27 +2410,16 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
true);
}
- if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
- IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
+ if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
/*
- * Wa_1607138336:tgl[a0],dg1[a0]
- * Wa_1607063988:tgl[a0],dg1[a0]
+ * Wa_1607138336
+ * Wa_1607063988
*/
wa_write_or(wal,
GEN9_CTX_PREEMPT_REG,
GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
}
- if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
- /*
- * Wa_1606679103:tgl
- * (see also Wa_1606682166:icl)
- */
- wa_write_or(wal,
- GEN7_SARCHKMD,
- GEN7_DISABLE_SAMPLER_PREFETCH);
- }
-
if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index cf1c0970ecb4..879ab4ed42af 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -167,6 +167,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
+ pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
if (pre) {
drm_err(&dev_priv->drm, "This is a pre-production stepping. "
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 48c838b4ea62..62cc0f76c583 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -653,14 +653,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_TIGERLAKE(__i915) && \
IS_DISPLAY_STEP(__i915, since, until))
-#define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
- (IS_TGL_UY(__i915) && \
- IS_GRAPHICS_STEP(__i915, since, until))
-
-#define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
- (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
- IS_GRAPHICS_STEP(__i915, since, until))
-
#define IS_RKL_DISPLAY_STEP(p, since, until) \
(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3fc65bd12cc1..c6676f1a9c6f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4336,10 +4336,6 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
DPFC_CHICKEN_COMP_DUMMY_PIXEL);
- /* Wa_1409825376:tgl (pre-prod)*/
- if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
- intel_uncore_rmw(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, 0, TGL_VRH_GATING_DIS);
-
/* Wa_14013723622:tgl,rkl,dg1,adl-s */
if (DISPLAY_VER(dev_priv) == 12)
intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY,
--
2.39.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/dg1: Drop support for pre-production steppings
2023-01-27 22:43 [Intel-gfx] [PATCH 0/3] Drop TGL/DG1 workarounds for pre-prod steppings Matt Roper
2023-01-27 22:43 ` [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings Matt Roper
@ 2023-01-27 22:43 ` Matt Roper
2023-01-30 17:19 ` Rodrigo Vivi
2023-01-27 22:43 ` [Intel-gfx] [PATCH 3/3] drm/i915/dg1: Drop final use of IS_DG1_GRAPHICS_STEP Matt Roper
` (2 subsequent siblings)
4 siblings, 1 reply; 16+ messages in thread
From: Matt Roper @ 2023-01-27 22:43 UTC (permalink / raw)
To: intel-gfx
Several post-DG1 platforms have been brought up now, so we're well past
the point where we usually drop the workarounds that are only applicable
to internal/pre-production hardware.
Production DG1 hardware always has a B0 stepping for both display and
GT.
Bspec: 44463
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../drm/i915/display/intel_display_power.c | 1 -
drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++-----------------
drivers/gpu/drm/i915/i915_driver.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/intel_pm.c | 12 -----
5 files changed, 5 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1dc31f0f5e0a..7222502a760c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1580,7 +1580,6 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
return;
if (IS_ALDERLAKE_S(dev_priv) ||
- IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
/* Wa_1409767108 */
table = wa_1409767108_buddy_page_masks;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 82a8f372bde6..648fceba5bb6 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1463,12 +1463,6 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
gen12_gt_workarounds_init(gt, wal);
- /* Wa_1607087056:dg1 */
- if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
- wa_write_or(wal,
- GEN11_SLICE_UNIT_LEVEL_CLKGATE,
- L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
-
/* Wa_1409420604:dg1 */
if (IS_DG1(i915))
wa_mcr_write_or(wal,
@@ -2103,20 +2097,6 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
}
}
-static void dg1_whitelist_build(struct intel_engine_cs *engine)
-{
- struct i915_wa_list *w = &engine->whitelist;
-
- tgl_whitelist_build(engine);
-
- /* GEN:BUG:1409280441:dg1 */
- if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) &&
- (engine->class == RENDER_CLASS ||
- engine->class == COPY_ENGINE_CLASS))
- whitelist_reg_ext(w, RING_ID(engine->mmio_base),
- RING_FORCE_TO_NONPRIV_ACCESS_RD);
-}
-
static void xehpsdv_whitelist_build(struct intel_engine_cs *engine)
{
allow_read_ctx_timestamp(engine);
@@ -2196,8 +2176,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
dg2_whitelist_build(engine);
else if (IS_XEHPSDV(i915))
xehpsdv_whitelist_build(engine);
- else if (IS_DG1(i915))
- dg1_whitelist_build(engine);
else if (GRAPHICS_VER(i915) == 12)
tgl_whitelist_build(engine);
else if (GRAPHICS_VER(i915) == 11)
@@ -2410,16 +2388,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
true);
}
- if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
- /*
- * Wa_1607138336
- * Wa_1607063988
- */
- wa_write_or(wal,
- GEN9_CTX_PREEMPT_REG,
- GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
- }
-
if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
@@ -2449,30 +2417,22 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
}
if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
- IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
- /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
+ /* Wa_1409804808 */
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
GEN12_PUSH_CONST_DEREF_HOLD_DIS);
- /*
- * Wa_1409085225:tgl
- * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p
- */
+ /* Wa_14010229206 */
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
}
- if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
- IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
+ if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
/*
- * Wa_1607030317:tgl
- * Wa_1607186500:tgl
- * Wa_1607297627:tgl,rkl,dg1[a0],adlp
+ * Wa_1607297627
*
* On TGL and RKL there are multiple entries for this WA in the
* BSpec; some indicate this is an A0-only WA, others indicate
* it applies to all steppings so we trust the "all steppings."
- * For DG1 this only applies to A0.
*/
wa_masked_en(wal,
RING_PSMI_CTL(RENDER_RING_BASE),
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 879ab4ed42af..397a2159fe12 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -168,6 +168,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
+ pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
if (pre) {
drm_err(&dev_priv->drm, "This is a pre-production stepping. "
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 62cc0f76c583..57b84dbca084 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -658,8 +658,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_DG1_GRAPHICS_STEP(p, since, until) \
(IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
-#define IS_DG1_DISPLAY_STEP(p, since, until) \
- (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
(IS_ALDERLAKE_S(__i915) && \
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c6676f1a9c6f..e0364c4141b8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4353,15 +4353,6 @@ static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
}
-static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
-{
- gen12lp_init_clock_gating(dev_priv);
-
- /* Wa_1409836686:dg1[a0] */
- if (IS_DG1_GRAPHICS_STEP(dev_priv, STEP_A0, STEP_B0))
- intel_uncore_rmw(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, 0, DPT_GATING_DIS);
-}
-
static void xehpsdv_init_clock_gating(struct drm_i915_private *dev_priv)
{
/* Wa_22010146351:xehpsdv */
@@ -4781,7 +4772,6 @@ CG_FUNCS(pvc);
CG_FUNCS(dg2);
CG_FUNCS(xehpsdv);
CG_FUNCS(adlp);
-CG_FUNCS(dg1);
CG_FUNCS(gen12lp);
CG_FUNCS(icl);
CG_FUNCS(cfl);
@@ -4824,8 +4814,6 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
dev_priv->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
else if (IS_ALDERLAKE_P(dev_priv))
dev_priv->clock_gating_funcs = &adlp_clock_gating_funcs;
- else if (IS_DG1(dev_priv))
- dev_priv->clock_gating_funcs = &dg1_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 12)
dev_priv->clock_gating_funcs = &gen12lp_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 11)
--
2.39.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/dg1: Drop final use of IS_DG1_GRAPHICS_STEP
2023-01-27 22:43 [Intel-gfx] [PATCH 0/3] Drop TGL/DG1 workarounds for pre-prod steppings Matt Roper
2023-01-27 22:43 ` [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings Matt Roper
2023-01-27 22:43 ` [Intel-gfx] [PATCH 2/3] drm/i915/dg1: " Matt Roper
@ 2023-01-27 22:43 ` Matt Roper
2023-01-30 17:20 ` Rodrigo Vivi
2023-01-27 23:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Drop TGL/DG1 workarounds for pre-prod steppings Patchwork
2023-01-28 6:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 1 reply; 16+ messages in thread
From: Matt Roper @ 2023-01-27 22:43 UTC (permalink / raw)
To: intel-gfx
All production DG1 hardware has graphics stepping B0; there is no such
thing as C0. As such, we can simplify
IS_DG1_GRAPHICS_STEP(uncore->i915, STEP_A0, STEP_C0)
to just match DG1 in general.
Bspec: 44463
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 ---
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index f3ad93db0b21..89fdfc67f8d1 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -158,7 +158,7 @@ static const struct intel_memory_region_ops intel_region_lmem_ops = {
static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
u64 *start, u32 *size)
{
- if (!IS_DG1_GRAPHICS_STEP(uncore->i915, STEP_A0, STEP_C0))
+ if (!IS_DG1(uncore->i915))
return false;
*start = 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 57b84dbca084..495788e18b77 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -656,9 +656,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_RKL_DISPLAY_STEP(p, since, until) \
(IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
-#define IS_DG1_GRAPHICS_STEP(p, since, until) \
- (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
-
#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
(IS_ALDERLAKE_S(__i915) && \
IS_DISPLAY_STEP(__i915, since, until))
--
2.39.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Drop TGL/DG1 workarounds for pre-prod steppings
2023-01-27 22:43 [Intel-gfx] [PATCH 0/3] Drop TGL/DG1 workarounds for pre-prod steppings Matt Roper
` (2 preceding siblings ...)
2023-01-27 22:43 ` [Intel-gfx] [PATCH 3/3] drm/i915/dg1: Drop final use of IS_DG1_GRAPHICS_STEP Matt Roper
@ 2023-01-27 23:53 ` Patchwork
2023-01-28 6:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2023-01-27 23:53 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5271 bytes --]
== Series Details ==
Series: Drop TGL/DG1 workarounds for pre-prod steppings
URL : https://patchwork.freedesktop.org/series/113453/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12658 -> Patchwork_113453v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/index.html
Participating hosts (24 -> 23)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_113453v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@requests:
- {bat-rplp-1}: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/bat-rplp-1/igt@i915_selftest@live@requests.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/bat-rplp-1/igt@i915_selftest@live@requests.html
Known issues
------------
Here are the changes found in Patchwork_113453v1 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- {bat-dg2-11}: [DMESG-WARN][3] ([i915#1982]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/bat-dg2-11/igt@core_hotunplug@unbind-rebind.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/bat-dg2-11/igt@core_hotunplug@unbind-rebind.html
* igt@i915_pm_rpm@basic-rte:
- {bat-adlp-6}: [ABORT][5] -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/bat-adlp-6/igt@i915_pm_rpm@basic-rte.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/bat-adlp-6/igt@i915_pm_rpm@basic-rte.html
* igt@i915_pm_rpm@module-reload:
- {bat-dg2-11}: [DMESG-WARN][7] -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/bat-dg2-11/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/bat-dg2-11/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [DMESG-FAIL][9] ([i915#5334]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@migrate:
- {bat-dg2-11}: [DMESG-WARN][11] ([i915#2867]) -> [PASS][12] +5 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/bat-dg2-11/igt@i915_selftest@live@migrate.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/bat-dg2-11/igt@i915_selftest@live@migrate.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-n3050: [FAIL][13] ([i915#6298]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4137]: https://gitlab.freedesktop.org/drm/intel/issues/4137
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
Build changes
-------------
* Linux: CI_DRM_12658 -> Patchwork_113453v1
CI-20190529: 20190529
CI_DRM_12658: a9e72f4e0baf2e3e306da0063f98099044d85285 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7141: a978df7912acda18eada1b1d2ae4b438ed3e940b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113453v1: a9e72f4e0baf2e3e306da0063f98099044d85285 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
7fb70302790c drm/i915/dg1: Drop final use of IS_DG1_GRAPHICS_STEP
ea47c28431c9 drm/i915/dg1: Drop support for pre-production steppings
ea63c4cec9f1 drm/i915/tgl: Drop support for pre-production steppings
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/index.html
[-- Attachment #2: Type: text/html, Size: 5389 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Drop TGL/DG1 workarounds for pre-prod steppings
2023-01-27 22:43 [Intel-gfx] [PATCH 0/3] Drop TGL/DG1 workarounds for pre-prod steppings Matt Roper
` (3 preceding siblings ...)
2023-01-27 23:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Drop TGL/DG1 workarounds for pre-prod steppings Patchwork
@ 2023-01-28 6:28 ` Patchwork
2023-01-30 18:18 ` Matt Roper
4 siblings, 1 reply; 16+ messages in thread
From: Patchwork @ 2023-01-28 6:28 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 21659 bytes --]
== Series Details ==
Series: Drop TGL/DG1 workarounds for pre-prod steppings
URL : https://patchwork.freedesktop.org/series/113453/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12658_full -> Patchwork_113453v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/index.html
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_113453v1_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s3-devices@smem:
- {shard-rkl}: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-6/igt@gem_exec_suspend@basic-s3-devices@smem.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-4/igt@gem_exec_suspend@basic-s3-devices@smem.html
Known issues
------------
Here are the changes found in Patchwork_113453v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-glk3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-glk5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@perf@stress-open-close:
- shard-glk: [PASS][5] -> [ABORT][6] ([i915#5213])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-glk5/igt@perf@stress-open-close.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-glk9/igt@perf@stress-open-close.html
#### Possible fixes ####
* igt@drm_fdinfo@idle@rcs0:
- {shard-rkl}: [FAIL][7] ([i915#7742]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-4/igt@drm_fdinfo@idle@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@drm_fdinfo@idle@rcs0.html
* igt@drm_read@empty-block:
- {shard-rkl}: [SKIP][9] ([i915#4098]) -> [PASS][10] +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@drm_read@empty-block.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@drm_read@empty-block.html
* igt@fbdev@unaligned-read:
- {shard-rkl}: [SKIP][11] ([i915#2582]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-2/igt@fbdev@unaligned-read.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@fbdev@unaligned-read.html
* igt@gem_eio@in-flight-suspend:
- {shard-rkl}: [FAIL][13] ([fdo#103375]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@gem_eio@in-flight-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_capture@pi@vcs0:
- {shard-rkl}: [ABORT][15] -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-6/igt@gem_exec_capture@pi@vcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@gem_exec_capture@pi@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-tglu}: [FAIL][17] ([i915#2842]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-tglu-7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
- {shard-rkl}: [SKIP][19] ([i915#3281]) -> [PASS][20] +4 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
* igt@gem_mmap_wc@set-cache-level:
- {shard-rkl}: [SKIP][21] ([i915#1850]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-4/igt@gem_mmap_wc@set-cache-level.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@gem_mmap_wc@set-cache-level.html
* igt@gem_pwrite@basic-self:
- {shard-rkl}: [SKIP][23] ([i915#3282]) -> [PASS][24] +4 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@gem_pwrite@basic-self.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@gem_pwrite@basic-self.html
* igt@gem_sync@basic-all:
- shard-glk: [DMESG-WARN][25] ([i915#118]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-glk4/igt@gem_sync@basic-all.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-glk1/igt@gem_sync@basic-all.html
* igt@gen9_exec_parse@batch-invalid-length:
- {shard-rkl}: [SKIP][27] ([i915#2527]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@gen9_exec_parse@batch-invalid-length.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@gen9_exec_parse@batch-invalid-length.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-rkl}: [SKIP][29] ([i915#3361]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-5/igt@i915_pm_dc@dc9-dpms.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-2/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- {shard-rkl}: [WARN][31] ([i915#2681]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-2/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rpm@i2c:
- {shard-rkl}: [SKIP][33] ([fdo#109308]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@i915_pm_rpm@i2c.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@i915_pm_rpm@i2c.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- {shard-rkl}: [SKIP][35] ([i915#1845] / [i915#4098]) -> [PASS][36] +28 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][37] ([i915#79]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
- {shard-rkl}: [SKIP][39] ([i915#1849] / [i915#4098]) -> [PASS][40] +21 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_plane@plane-position-hole@pipe-b-planes:
- {shard-rkl}: [SKIP][41] ([i915#1849]) -> [PASS][42] +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-4/igt@kms_plane@plane-position-hole@pipe-b-planes.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@kms_plane@plane-position-hole@pipe-b-planes.html
* igt@kms_psr@no_drrs:
- {shard-rkl}: [SKIP][43] ([i915#1072]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-4/igt@kms_psr@no_drrs.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@kms_psr@no_drrs.html
* igt@kms_universal_plane@universal-plane-pipe-a-sanity:
- {shard-rkl}: [SKIP][45] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-2/igt@kms_universal_plane@universal-plane-pipe-a-sanity.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-a-sanity.html
* igt@perf@mi-rpc:
- {shard-rkl}: [SKIP][47] ([i915#2434]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@perf@mi-rpc.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@perf@mi-rpc.html
* igt@perf_pmu@most-busy-idle-check-all@rcs0:
- {shard-rkl}: [FAIL][49] ([i915#4349]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-4/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-2/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
* igt@prime_vgem@basic-write:
- {shard-rkl}: [SKIP][51] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@prime_vgem@basic-write.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@prime_vgem@basic-write.html
* igt@prime_vgem@coherency-gtt:
- {shard-rkl}: [SKIP][53] ([fdo#109295] / [fdo#111656] / [i915#3708]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@prime_vgem@coherency-gtt.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@prime_vgem@coherency-gtt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
Build changes
-------------
* Linux: CI_DRM_12658 -> Patchwork_113453v1
CI-20190529: 20190529
CI_DRM_12658: a9e72f4e0baf2e3e306da0063f98099044d85285 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7141: a978df7912acda18eada1b1d2ae4b438ed3e940b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113453v1: a9e72f4e0baf2e3e306da0063f98099044d85285 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/index.html
[-- Attachment #2: Type: text/html, Size: 14695 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings
2023-01-27 22:43 ` [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings Matt Roper
@ 2023-01-30 15:46 ` Rodrigo Vivi
2023-01-30 15:51 ` Matt Roper
0 siblings, 1 reply; 16+ messages in thread
From: Rodrigo Vivi @ 2023-01-30 15:46 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Fri, Jan 27, 2023 at 02:43:11PM -0800, Matt Roper wrote:
> Several post-TGL platforms have been brought up now, so we're well past
> the point where we usually drop the workarounds that are only applicable
> to internal/pre-production hardware.
>
> Production TGL hardware always has display stepping C0 or later and GT
> stepping B0 or later (this is true for both the original TGL and the U/Y
> subplatform).
>
> Bspec 44455
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 5 +--
> drivers/gpu/drm/i915/display/intel_psr.c | 26 -----------
> .../drm/i915/display/skl_universal_plane.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 ++-----------------
> drivers/gpu/drm/i915/i915_driver.c | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 8 ----
> drivers/gpu/drm/i915/intel_pm.c | 4 --
> 7 files changed, 7 insertions(+), 83 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 1a23ecd4623a..1dc31f0f5e0a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1581,9 +1581,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
>
> if (IS_ALDERLAKE_S(dev_priv) ||
> IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> - IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> - /* Wa_1409767108:tgl,dg1,adl-s */
> + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
I believe we should go ahead and also remove the RKL ones like this.
After all we have ADL and MTL and none needed this for instance.
> + /* Wa_1409767108 */
> table = wa_1409767108_buddy_page_masks;
> else
> table = tgl_buddy_page_masks;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7d4a15a283a0..5dca58dd97a9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -591,12 +591,6 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> if (intel_dp->psr.psr2_sel_fetch_enabled) {
> u32 tmp;
>
> - /* Wa_1408330847 */
> - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> - DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> - DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> -
> tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
> drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
> } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> @@ -765,13 +759,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> return false;
> }
>
> - /* Wa_14010254185 Wa_14010103792 */
> - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> - drm_dbg_kms(&dev_priv->drm,
> - "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
> - return false;
> - }
> -
> return crtc_state->enable_psr2_sel_fetch = true;
> }
>
> @@ -945,13 +932,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> }
> }
>
> - /* Wa_2209313811 */
> - if (!crtc_state->enable_psr2_sel_fetch &&
> - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> - drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
> - goto unsupported;
> - }
> -
> if (!psr2_granularity_check(intel_dp, crtc_state)) {
> drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
> goto unsupported;
> @@ -1360,12 +1340,6 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> intel_psr_exit(intel_dp);
> intel_psr_wait_exit_locked(intel_dp);
>
> - /* Wa_1408330847 */
> - if (intel_dp->psr.psr2_sel_fetch_enabled &&
> - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> - DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> -
> /*
> * Wa_16013835468
> * Wa_14015648006
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 9b172a1e90de..e956edb87398 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2180,7 +2180,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
> if (DISPLAY_VER(i915) < 12)
> return false;
>
> - /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> + /* Wa_14010477008 */
> if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
> IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
> return false;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 4efc1a532982..82a8f372bde6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1456,31 +1456,6 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
> }
>
> -static void
> -tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> -{
> - struct drm_i915_private *i915 = gt->i915;
> -
> - gen12_gt_workarounds_init(gt, wal);
> -
> - /* Wa_1409420604:tgl */
> - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> - wa_mcr_write_or(wal,
> - SUBSLICE_UNIT_LEVEL_CLKGATE2,
> - CPSSUNIT_CLKGATE_DIS);
> -
> - /* Wa_1607087056:tgl also know as BUG:1409180338 */
> - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> - wa_write_or(wal,
> - GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> - L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> -
> - /* Wa_1408615072:tgl[a0] */
> - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> - VSUNIT_CLKGATE_DIS_TGL);
> -}
> -
> static void
> dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> @@ -1716,8 +1691,6 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
> xehpsdv_gt_workarounds_init(gt, wal);
> else if (IS_DG1(i915))
> dg1_gt_workarounds_init(gt, wal);
> - else if (IS_TIGERLAKE(i915))
> - tgl_gt_workarounds_init(gt, wal);
> else if (GRAPHICS_VER(i915) == 12)
> gen12_gt_workarounds_init(gt, wal);
> else if (GRAPHICS_VER(i915) == 11)
> @@ -2437,27 +2410,16 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> true);
> }
>
> - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> - IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> + if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> /*
> - * Wa_1607138336:tgl[a0],dg1[a0]
> - * Wa_1607063988:tgl[a0],dg1[a0]
> + * Wa_1607138336
> + * Wa_1607063988
> */
> wa_write_or(wal,
> GEN9_CTX_PREEMPT_REG,
> GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> }
>
> - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> - /*
> - * Wa_1606679103:tgl
> - * (see also Wa_1606682166:icl)
> - */
> - wa_write_or(wal,
> - GEN7_SARCHKMD,
> - GEN7_DISABLE_SAMPLER_PREFETCH);
> - }
> -
> if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index cf1c0970ecb4..879ab4ed42af 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -167,6 +167,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
> pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
> pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
> + pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
>
> if (pre) {
> drm_err(&dev_priv->drm, "This is a pre-production stepping. "
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 48c838b4ea62..62cc0f76c583 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -653,14 +653,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> (IS_TIGERLAKE(__i915) && \
> IS_DISPLAY_STEP(__i915, since, until))
>
> -#define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
> - (IS_TGL_UY(__i915) && \
> - IS_GRAPHICS_STEP(__i915, since, until))
> -
> -#define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
> - (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
> - IS_GRAPHICS_STEP(__i915, since, until))
> -
> #define IS_RKL_DISPLAY_STEP(p, since, until) \
> (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3fc65bd12cc1..c6676f1a9c6f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4336,10 +4336,6 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
> intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>
> - /* Wa_1409825376:tgl (pre-prod)*/
> - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> - intel_uncore_rmw(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, 0, TGL_VRH_GATING_DIS);
> -
> /* Wa_14013723622:tgl,rkl,dg1,adl-s */
> if (DISPLAY_VER(dev_priv) == 12)
> intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY,
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings
2023-01-30 15:46 ` Rodrigo Vivi
@ 2023-01-30 15:51 ` Matt Roper
2023-01-30 16:42 ` Rodrigo Vivi
0 siblings, 1 reply; 16+ messages in thread
From: Matt Roper @ 2023-01-30 15:51 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Mon, Jan 30, 2023 at 10:46:16AM -0500, Rodrigo Vivi wrote:
> On Fri, Jan 27, 2023 at 02:43:11PM -0800, Matt Roper wrote:
> > Several post-TGL platforms have been brought up now, so we're well past
> > the point where we usually drop the workarounds that are only applicable
> > to internal/pre-production hardware.
> >
> > Production TGL hardware always has display stepping C0 or later and GT
> > stepping B0 or later (this is true for both the original TGL and the U/Y
> > subplatform).
> >
> > Bspec 44455
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > .../drm/i915/display/intel_display_power.c | 5 +--
> > drivers/gpu/drm/i915/display/intel_psr.c | 26 -----------
> > .../drm/i915/display/skl_universal_plane.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 ++-----------------
> > drivers/gpu/drm/i915/i915_driver.c | 1 +
> > drivers/gpu/drm/i915/i915_drv.h | 8 ----
> > drivers/gpu/drm/i915/intel_pm.c | 4 --
> > 7 files changed, 7 insertions(+), 83 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 1a23ecd4623a..1dc31f0f5e0a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -1581,9 +1581,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> >
> > if (IS_ALDERLAKE_S(dev_priv) ||
> > IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > - IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > - /* Wa_1409767108:tgl,dg1,adl-s */
> > + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>
> I believe we should go ahead and also remove the RKL ones like this.
> After all we have ADL and MTL and none needed this for instance.
Do we know for sure that A0 RKL wasn't productized? I can't find the
details about which stepping(s) were pre-prod-only in the bspec, so I've
left RKL and ADL workarounds alone for the time being.
Matt
>
> > + /* Wa_1409767108 */
> > table = wa_1409767108_buddy_page_masks;
> > else
> > table = tgl_buddy_page_masks;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 7d4a15a283a0..5dca58dd97a9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -591,12 +591,6 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> > if (intel_dp->psr.psr2_sel_fetch_enabled) {
> > u32 tmp;
> >
> > - /* Wa_1408330847 */
> > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > - DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > - DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> > -
> > tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
> > drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
> > } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> > @@ -765,13 +759,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > return false;
> > }
> >
> > - /* Wa_14010254185 Wa_14010103792 */
> > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > - drm_dbg_kms(&dev_priv->drm,
> > - "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
> > - return false;
> > - }
> > -
> > return crtc_state->enable_psr2_sel_fetch = true;
> > }
> >
> > @@ -945,13 +932,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> > }
> > }
> >
> > - /* Wa_2209313811 */
> > - if (!crtc_state->enable_psr2_sel_fetch &&
> > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > - drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
> > - goto unsupported;
> > - }
> > -
> > if (!psr2_granularity_check(intel_dp, crtc_state)) {
> > drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
> > goto unsupported;
> > @@ -1360,12 +1340,6 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> > intel_psr_exit(intel_dp);
> > intel_psr_wait_exit_locked(intel_dp);
> >
> > - /* Wa_1408330847 */
> > - if (intel_dp->psr.psr2_sel_fetch_enabled &&
> > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > - DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> > -
> > /*
> > * Wa_16013835468
> > * Wa_14015648006
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 9b172a1e90de..e956edb87398 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -2180,7 +2180,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
> > if (DISPLAY_VER(i915) < 12)
> > return false;
> >
> > - /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> > + /* Wa_14010477008 */
> > if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
> > IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
> > return false;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 4efc1a532982..82a8f372bde6 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -1456,31 +1456,6 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
> > }
> >
> > -static void
> > -tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > -{
> > - struct drm_i915_private *i915 = gt->i915;
> > -
> > - gen12_gt_workarounds_init(gt, wal);
> > -
> > - /* Wa_1409420604:tgl */
> > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > - wa_mcr_write_or(wal,
> > - SUBSLICE_UNIT_LEVEL_CLKGATE2,
> > - CPSSUNIT_CLKGATE_DIS);
> > -
> > - /* Wa_1607087056:tgl also know as BUG:1409180338 */
> > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > - wa_write_or(wal,
> > - GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > - L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> > -
> > - /* Wa_1408615072:tgl[a0] */
> > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> > - VSUNIT_CLKGATE_DIS_TGL);
> > -}
> > -
> > static void
> > dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > {
> > @@ -1716,8 +1691,6 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
> > xehpsdv_gt_workarounds_init(gt, wal);
> > else if (IS_DG1(i915))
> > dg1_gt_workarounds_init(gt, wal);
> > - else if (IS_TIGERLAKE(i915))
> > - tgl_gt_workarounds_init(gt, wal);
> > else if (GRAPHICS_VER(i915) == 12)
> > gen12_gt_workarounds_init(gt, wal);
> > else if (GRAPHICS_VER(i915) == 11)
> > @@ -2437,27 +2410,16 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > true);
> > }
> >
> > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > - IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > + if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > /*
> > - * Wa_1607138336:tgl[a0],dg1[a0]
> > - * Wa_1607063988:tgl[a0],dg1[a0]
> > + * Wa_1607138336
> > + * Wa_1607063988
> > */
> > wa_write_or(wal,
> > GEN9_CTX_PREEMPT_REG,
> > GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> > }
> >
> > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > - /*
> > - * Wa_1606679103:tgl
> > - * (see also Wa_1606682166:icl)
> > - */
> > - wa_write_or(wal,
> > - GEN7_SARCHKMD,
> > - GEN7_DISABLE_SAMPLER_PREFETCH);
> > - }
> > -
> > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> > index cf1c0970ecb4..879ab4ed42af 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -167,6 +167,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
> > pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> > pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
> > pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
> > + pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> >
> > if (pre) {
> > drm_err(&dev_priv->drm, "This is a pre-production stepping. "
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 48c838b4ea62..62cc0f76c583 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -653,14 +653,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > (IS_TIGERLAKE(__i915) && \
> > IS_DISPLAY_STEP(__i915, since, until))
> >
> > -#define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
> > - (IS_TGL_UY(__i915) && \
> > - IS_GRAPHICS_STEP(__i915, since, until))
> > -
> > -#define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
> > - (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
> > - IS_GRAPHICS_STEP(__i915, since, until))
> > -
> > #define IS_RKL_DISPLAY_STEP(p, since, until) \
> > (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 3fc65bd12cc1..c6676f1a9c6f 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4336,10 +4336,6 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
> > intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> > DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> >
> > - /* Wa_1409825376:tgl (pre-prod)*/
> > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > - intel_uncore_rmw(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, 0, TGL_VRH_GATING_DIS);
> > -
> > /* Wa_14013723622:tgl,rkl,dg1,adl-s */
> > if (DISPLAY_VER(dev_priv) == 12)
> > intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY,
> > --
> > 2.39.1
> >
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings
2023-01-30 15:51 ` Matt Roper
@ 2023-01-30 16:42 ` Rodrigo Vivi
2023-01-30 17:03 ` Matt Roper
0 siblings, 1 reply; 16+ messages in thread
From: Rodrigo Vivi @ 2023-01-30 16:42 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Mon, Jan 30, 2023 at 07:51:51AM -0800, Matt Roper wrote:
> On Mon, Jan 30, 2023 at 10:46:16AM -0500, Rodrigo Vivi wrote:
> > On Fri, Jan 27, 2023 at 02:43:11PM -0800, Matt Roper wrote:
> > > Several post-TGL platforms have been brought up now, so we're well past
> > > the point where we usually drop the workarounds that are only applicable
> > > to internal/pre-production hardware.
> > >
> > > Production TGL hardware always has display stepping C0 or later and GT
> > > stepping B0 or later (this is true for both the original TGL and the U/Y
> > > subplatform).
> > >
> > > Bspec 44455
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_power.c | 5 +--
> > > drivers/gpu/drm/i915/display/intel_psr.c | 26 -----------
> > > .../drm/i915/display/skl_universal_plane.c | 2 +-
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 ++-----------------
> > > drivers/gpu/drm/i915/i915_driver.c | 1 +
> > > drivers/gpu/drm/i915/i915_drv.h | 8 ----
> > > drivers/gpu/drm/i915/intel_pm.c | 4 --
> > > 7 files changed, 7 insertions(+), 83 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 1a23ecd4623a..1dc31f0f5e0a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -1581,9 +1581,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> > >
> > > if (IS_ALDERLAKE_S(dev_priv) ||
> > > IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > - IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > > - /* Wa_1409767108:tgl,dg1,adl-s */
> > > + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> >
> > I believe we should go ahead and also remove the RKL ones like this.
> > After all we have ADL and MTL and none needed this for instance.
>
> Do we know for sure that A0 RKL wasn't productized? I can't find the
> details about which stepping(s) were pre-prod-only in the bspec, so I've
> left RKL and ADL workarounds alone for the time being.
Very good point. However this point may be against this patch,
or at least part of it, since there are some TGL GT2 B0
not marked as pre-production.
>
>
> Matt
>
> >
> > > + /* Wa_1409767108 */
> > > table = wa_1409767108_buddy_page_masks;
> > > else
> > > table = tgl_buddy_page_masks;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 7d4a15a283a0..5dca58dd97a9 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -591,12 +591,6 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> > > if (intel_dp->psr.psr2_sel_fetch_enabled) {
> > > u32 tmp;
> > >
> > > - /* Wa_1408330847 */
> > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > > - DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > > - DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> > > -
> > > tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
> > > drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
> > > } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> > > @@ -765,13 +759,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > > return false;
> > > }
> > >
> > > - /* Wa_14010254185 Wa_14010103792 */
> > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > - drm_dbg_kms(&dev_priv->drm,
> > > - "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
> > > - return false;
> > > - }
> > > -
> > > return crtc_state->enable_psr2_sel_fetch = true;
> > > }
> > >
> > > @@ -945,13 +932,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> > > }
> > > }
> > >
> > > - /* Wa_2209313811 */
> > > - if (!crtc_state->enable_psr2_sel_fetch &&
> > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > - drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
> > > - goto unsupported;
> > > - }
> > > -
> > > if (!psr2_granularity_check(intel_dp, crtc_state)) {
> > > drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
> > > goto unsupported;
> > > @@ -1360,12 +1340,6 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> > > intel_psr_exit(intel_dp);
> > > intel_psr_wait_exit_locked(intel_dp);
> > >
> > > - /* Wa_1408330847 */
> > > - if (intel_dp->psr.psr2_sel_fetch_enabled &&
> > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > > - DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> > > -
> > > /*
> > > * Wa_16013835468
> > > * Wa_14015648006
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 9b172a1e90de..e956edb87398 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -2180,7 +2180,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
> > > if (DISPLAY_VER(i915) < 12)
> > > return false;
> > >
> > > - /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> > > + /* Wa_14010477008 */
> > > if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
> > > IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
> > > return false;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index 4efc1a532982..82a8f372bde6 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -1456,31 +1456,6 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > > wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
> > > }
> > >
> > > -static void
> > > -tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > > -{
> > > - struct drm_i915_private *i915 = gt->i915;
> > > -
> > > - gen12_gt_workarounds_init(gt, wal);
> > > -
> > > - /* Wa_1409420604:tgl */
> > > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > > - wa_mcr_write_or(wal,
> > > - SUBSLICE_UNIT_LEVEL_CLKGATE2,
> > > - CPSSUNIT_CLKGATE_DIS);
> > > -
> > > - /* Wa_1607087056:tgl also know as BUG:1409180338 */
> > > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > > - wa_write_or(wal,
> > > - GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > > - L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> > > -
> > > - /* Wa_1408615072:tgl[a0] */
> > > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > > - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> > > - VSUNIT_CLKGATE_DIS_TGL);
> > > -}
> > > -
> > > static void
> > > dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > > {
> > > @@ -1716,8 +1691,6 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
> > > xehpsdv_gt_workarounds_init(gt, wal);
> > > else if (IS_DG1(i915))
> > > dg1_gt_workarounds_init(gt, wal);
> > > - else if (IS_TIGERLAKE(i915))
> > > - tgl_gt_workarounds_init(gt, wal);
> > > else if (GRAPHICS_VER(i915) == 12)
> > > gen12_gt_workarounds_init(gt, wal);
> > > else if (GRAPHICS_VER(i915) == 11)
> > > @@ -2437,27 +2410,16 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > true);
> > > }
> > >
> > > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > > - IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > > + if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > > /*
> > > - * Wa_1607138336:tgl[a0],dg1[a0]
> > > - * Wa_1607063988:tgl[a0],dg1[a0]
> > > + * Wa_1607138336
> > > + * Wa_1607063988
> > > */
> > > wa_write_or(wal,
> > > GEN9_CTX_PREEMPT_REG,
> > > GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> > > }
> > >
> > > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > > - /*
> > > - * Wa_1606679103:tgl
> > > - * (see also Wa_1606682166:icl)
> > > - */
> > > - wa_write_or(wal,
> > > - GEN7_SARCHKMD,
> > > - GEN7_DISABLE_SAMPLER_PREFETCH);
> > > - }
> > > -
> > > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> > > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > > /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> > > index cf1c0970ecb4..879ab4ed42af 100644
> > > --- a/drivers/gpu/drm/i915/i915_driver.c
> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > > @@ -167,6 +167,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
> > > pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> > > pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
> > > pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
> > > + pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> > >
> > > if (pre) {
> > > drm_err(&dev_priv->drm, "This is a pre-production stepping. "
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index 48c838b4ea62..62cc0f76c583 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -653,14 +653,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > > (IS_TIGERLAKE(__i915) && \
> > > IS_DISPLAY_STEP(__i915, since, until))
> > >
> > > -#define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
> > > - (IS_TGL_UY(__i915) && \
> > > - IS_GRAPHICS_STEP(__i915, since, until))
> > > -
> > > -#define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
> > > - (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
> > > - IS_GRAPHICS_STEP(__i915, since, until))
> > > -
> > > #define IS_RKL_DISPLAY_STEP(p, since, until) \
> > > (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 3fc65bd12cc1..c6676f1a9c6f 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4336,10 +4336,6 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
> > > intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> > > DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> > >
> > > - /* Wa_1409825376:tgl (pre-prod)*/
> > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > > - intel_uncore_rmw(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, 0, TGL_VRH_GATING_DIS);
> > > -
> > > /* Wa_14013723622:tgl,rkl,dg1,adl-s */
> > > if (DISPLAY_VER(dev_priv) == 12)
> > > intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY,
> > > --
> > > 2.39.1
> > >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings
2023-01-30 16:42 ` Rodrigo Vivi
@ 2023-01-30 17:03 ` Matt Roper
2023-01-30 17:19 ` Rodrigo Vivi
0 siblings, 1 reply; 16+ messages in thread
From: Matt Roper @ 2023-01-30 17:03 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Mon, Jan 30, 2023 at 11:42:41AM -0500, Rodrigo Vivi wrote:
> On Mon, Jan 30, 2023 at 07:51:51AM -0800, Matt Roper wrote:
> > On Mon, Jan 30, 2023 at 10:46:16AM -0500, Rodrigo Vivi wrote:
> > > On Fri, Jan 27, 2023 at 02:43:11PM -0800, Matt Roper wrote:
> > > > Several post-TGL platforms have been brought up now, so we're well past
> > > > the point where we usually drop the workarounds that are only applicable
> > > > to internal/pre-production hardware.
> > > >
> > > > Production TGL hardware always has display stepping C0 or later and GT
> > > > stepping B0 or later (this is true for both the original TGL and the U/Y
> > > > subplatform).
> > > >
> > > > Bspec 44455
> > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > ---
> > > > .../drm/i915/display/intel_display_power.c | 5 +--
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 26 -----------
> > > > .../drm/i915/display/skl_universal_plane.c | 2 +-
> > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 ++-----------------
> > > > drivers/gpu/drm/i915/i915_driver.c | 1 +
> > > > drivers/gpu/drm/i915/i915_drv.h | 8 ----
> > > > drivers/gpu/drm/i915/intel_pm.c | 4 --
> > > > 7 files changed, 7 insertions(+), 83 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > index 1a23ecd4623a..1dc31f0f5e0a 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > @@ -1581,9 +1581,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> > > >
> > > > if (IS_ALDERLAKE_S(dev_priv) ||
> > > > IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > > - IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > > > - /* Wa_1409767108:tgl,dg1,adl-s */
> > > > + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > >
> > > I believe we should go ahead and also remove the RKL ones like this.
> > > After all we have ADL and MTL and none needed this for instance.
> >
> > Do we know for sure that A0 RKL wasn't productized? I can't find the
> > details about which stepping(s) were pre-prod-only in the bspec, so I've
> > left RKL and ADL workarounds alone for the time being.
>
> Very good point. However this point may be against this patch,
> or at least part of it, since there are some TGL GT2 B0
> not marked as pre-production.
The CPU, GT, and display stepping are all independent of each other.
According to bspec 44455, all production steppings of TGL have either
display stepping C0 or D0.
Matt
>
> >
> >
> > Matt
> >
> > >
> > > > + /* Wa_1409767108 */
> > > > table = wa_1409767108_buddy_page_masks;
> > > > else
> > > > table = tgl_buddy_page_masks;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 7d4a15a283a0..5dca58dd97a9 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -591,12 +591,6 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> > > > if (intel_dp->psr.psr2_sel_fetch_enabled) {
> > > > u32 tmp;
> > > >
> > > > - /* Wa_1408330847 */
> > > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > > - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > > > - DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > > > - DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> > > > -
> > > > tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
> > > > drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
> > > > } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> > > > @@ -765,13 +759,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > > > return false;
> > > > }
> > > >
> > > > - /* Wa_14010254185 Wa_14010103792 */
> > > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > > - drm_dbg_kms(&dev_priv->drm,
> > > > - "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
> > > > - return false;
> > > > - }
> > > > -
> > > > return crtc_state->enable_psr2_sel_fetch = true;
> > > > }
> > > >
> > > > @@ -945,13 +932,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> > > > }
> > > > }
> > > >
> > > > - /* Wa_2209313811 */
> > > > - if (!crtc_state->enable_psr2_sel_fetch &&
> > > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > > - drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
> > > > - goto unsupported;
> > > > - }
> > > > -
> > > > if (!psr2_granularity_check(intel_dp, crtc_state)) {
> > > > drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
> > > > goto unsupported;
> > > > @@ -1360,12 +1340,6 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> > > > intel_psr_exit(intel_dp);
> > > > intel_psr_wait_exit_locked(intel_dp);
> > > >
> > > > - /* Wa_1408330847 */
> > > > - if (intel_dp->psr.psr2_sel_fetch_enabled &&
> > > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > > - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > > > - DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> > > > -
> > > > /*
> > > > * Wa_16013835468
> > > > * Wa_14015648006
> > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > index 9b172a1e90de..e956edb87398 100644
> > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > @@ -2180,7 +2180,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
> > > > if (DISPLAY_VER(i915) < 12)
> > > > return false;
> > > >
> > > > - /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> > > > + /* Wa_14010477008 */
> > > > if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
> > > > IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
> > > > return false;
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > index 4efc1a532982..82a8f372bde6 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > @@ -1456,31 +1456,6 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > > > wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
> > > > }
> > > >
> > > > -static void
> > > > -tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > > > -{
> > > > - struct drm_i915_private *i915 = gt->i915;
> > > > -
> > > > - gen12_gt_workarounds_init(gt, wal);
> > > > -
> > > > - /* Wa_1409420604:tgl */
> > > > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > > > - wa_mcr_write_or(wal,
> > > > - SUBSLICE_UNIT_LEVEL_CLKGATE2,
> > > > - CPSSUNIT_CLKGATE_DIS);
> > > > -
> > > > - /* Wa_1607087056:tgl also know as BUG:1409180338 */
> > > > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > > > - wa_write_or(wal,
> > > > - GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > > > - L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> > > > -
> > > > - /* Wa_1408615072:tgl[a0] */
> > > > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > > > - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> > > > - VSUNIT_CLKGATE_DIS_TGL);
> > > > -}
> > > > -
> > > > static void
> > > > dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > > > {
> > > > @@ -1716,8 +1691,6 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
> > > > xehpsdv_gt_workarounds_init(gt, wal);
> > > > else if (IS_DG1(i915))
> > > > dg1_gt_workarounds_init(gt, wal);
> > > > - else if (IS_TIGERLAKE(i915))
> > > > - tgl_gt_workarounds_init(gt, wal);
> > > > else if (GRAPHICS_VER(i915) == 12)
> > > > gen12_gt_workarounds_init(gt, wal);
> > > > else if (GRAPHICS_VER(i915) == 11)
> > > > @@ -2437,27 +2410,16 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > true);
> > > > }
> > > >
> > > > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > > > - IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > > > + if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > > > /*
> > > > - * Wa_1607138336:tgl[a0],dg1[a0]
> > > > - * Wa_1607063988:tgl[a0],dg1[a0]
> > > > + * Wa_1607138336
> > > > + * Wa_1607063988
> > > > */
> > > > wa_write_or(wal,
> > > > GEN9_CTX_PREEMPT_REG,
> > > > GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> > > > }
> > > >
> > > > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > > > - /*
> > > > - * Wa_1606679103:tgl
> > > > - * (see also Wa_1606682166:icl)
> > > > - */
> > > > - wa_write_or(wal,
> > > > - GEN7_SARCHKMD,
> > > > - GEN7_DISABLE_SAMPLER_PREFETCH);
> > > > - }
> > > > -
> > > > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> > > > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > > > /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> > > > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> > > > index cf1c0970ecb4..879ab4ed42af 100644
> > > > --- a/drivers/gpu/drm/i915/i915_driver.c
> > > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > > > @@ -167,6 +167,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
> > > > pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> > > > pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
> > > > pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
> > > > + pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> > > >
> > > > if (pre) {
> > > > drm_err(&dev_priv->drm, "This is a pre-production stepping. "
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > > index 48c838b4ea62..62cc0f76c583 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > @@ -653,14 +653,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > > > (IS_TIGERLAKE(__i915) && \
> > > > IS_DISPLAY_STEP(__i915, since, until))
> > > >
> > > > -#define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
> > > > - (IS_TGL_UY(__i915) && \
> > > > - IS_GRAPHICS_STEP(__i915, since, until))
> > > > -
> > > > -#define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
> > > > - (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
> > > > - IS_GRAPHICS_STEP(__i915, since, until))
> > > > -
> > > > #define IS_RKL_DISPLAY_STEP(p, since, until) \
> > > > (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > index 3fc65bd12cc1..c6676f1a9c6f 100644
> > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > @@ -4336,10 +4336,6 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
> > > > intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> > > > DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> > > >
> > > > - /* Wa_1409825376:tgl (pre-prod)*/
> > > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > > > - intel_uncore_rmw(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, 0, TGL_VRH_GATING_DIS);
> > > > -
> > > > /* Wa_14013723622:tgl,rkl,dg1,adl-s */
> > > > if (DISPLAY_VER(dev_priv) == 12)
> > > > intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY,
> > > > --
> > > > 2.39.1
> > > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings
2023-01-30 17:03 ` Matt Roper
@ 2023-01-30 17:19 ` Rodrigo Vivi
0 siblings, 0 replies; 16+ messages in thread
From: Rodrigo Vivi @ 2023-01-30 17:19 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Mon, Jan 30, 2023 at 09:03:17AM -0800, Matt Roper wrote:
> On Mon, Jan 30, 2023 at 11:42:41AM -0500, Rodrigo Vivi wrote:
> > On Mon, Jan 30, 2023 at 07:51:51AM -0800, Matt Roper wrote:
> > > On Mon, Jan 30, 2023 at 10:46:16AM -0500, Rodrigo Vivi wrote:
> > > > On Fri, Jan 27, 2023 at 02:43:11PM -0800, Matt Roper wrote:
> > > > > Several post-TGL platforms have been brought up now, so we're well past
> > > > > the point where we usually drop the workarounds that are only applicable
> > > > > to internal/pre-production hardware.
> > > > >
> > > > > Production TGL hardware always has display stepping C0 or later and GT
> > > > > stepping B0 or later (this is true for both the original TGL and the U/Y
> > > > > subplatform).
> > > > >
> > > > > Bspec 44455
> > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > > ---
> > > > > .../drm/i915/display/intel_display_power.c | 5 +--
> > > > > drivers/gpu/drm/i915/display/intel_psr.c | 26 -----------
> > > > > .../drm/i915/display/skl_universal_plane.c | 2 +-
> > > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 ++-----------------
> > > > > drivers/gpu/drm/i915/i915_driver.c | 1 +
> > > > > drivers/gpu/drm/i915/i915_drv.h | 8 ----
> > > > > drivers/gpu/drm/i915/intel_pm.c | 4 --
> > > > > 7 files changed, 7 insertions(+), 83 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > index 1a23ecd4623a..1dc31f0f5e0a 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > > > @@ -1581,9 +1581,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> > > > >
> > > > > if (IS_ALDERLAKE_S(dev_priv) ||
> > > > > IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > > > - IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > > > > - /* Wa_1409767108:tgl,dg1,adl-s */
> > > > > + IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > >
> > > > I believe we should go ahead and also remove the RKL ones like this.
> > > > After all we have ADL and MTL and none needed this for instance.
> > >
> > > Do we know for sure that A0 RKL wasn't productized? I can't find the
> > > details about which stepping(s) were pre-prod-only in the bspec, so I've
> > > left RKL and ADL workarounds alone for the time being.
> >
> > Very good point. However this point may be against this patch,
> > or at least part of it, since there are some TGL GT2 B0
> > not marked as pre-production.
>
> The CPU, GT, and display stepping are all independent of each other.
> According to bspec 44455, all production steppings of TGL have either
> display stepping C0 or D0.
oh, indeed!
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
>
> Matt
>
> >
> > >
> > >
> > > Matt
> > >
> > > >
> > > > > + /* Wa_1409767108 */
> > > > > table = wa_1409767108_buddy_page_masks;
> > > > > else
> > > > > table = tgl_buddy_page_masks;
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > index 7d4a15a283a0..5dca58dd97a9 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > @@ -591,12 +591,6 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> > > > > if (intel_dp->psr.psr2_sel_fetch_enabled) {
> > > > > u32 tmp;
> > > > >
> > > > > - /* Wa_1408330847 */
> > > > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > > > - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > > > > - DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> > > > > - DIS_RAM_BYPASS_PSR2_MAN_TRACK);
> > > > > -
> > > > > tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
> > > > > drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE));
> > > > > } else if (HAS_PSR2_SEL_FETCH(dev_priv)) {
> > > > > @@ -765,13 +759,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
> > > > > return false;
> > > > > }
> > > > >
> > > > > - /* Wa_14010254185 Wa_14010103792 */
> > > > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > > > - drm_dbg_kms(&dev_priv->drm,
> > > > > - "PSR2 sel fetch not enabled, missing the implementation of WAs\n");
> > > > > - return false;
> > > > > - }
> > > > > -
> > > > > return crtc_state->enable_psr2_sel_fetch = true;
> > > > > }
> > > > >
> > > > > @@ -945,13 +932,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> > > > > }
> > > > > }
> > > > >
> > > > > - /* Wa_2209313811 */
> > > > > - if (!crtc_state->enable_psr2_sel_fetch &&
> > > > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {
> > > > > - drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");
> > > > > - goto unsupported;
> > > > > - }
> > > > > -
> > > > > if (!psr2_granularity_check(intel_dp, crtc_state)) {
> > > > > drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");
> > > > > goto unsupported;
> > > > > @@ -1360,12 +1340,6 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
> > > > > intel_psr_exit(intel_dp);
> > > > > intel_psr_wait_exit_locked(intel_dp);
> > > > >
> > > > > - /* Wa_1408330847 */
> > > > > - if (intel_dp->psr.psr2_sel_fetch_enabled &&
> > > > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > > > - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> > > > > - DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> > > > > -
> > > > > /*
> > > > > * Wa_16013835468
> > > > > * Wa_14015648006
> > > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > index 9b172a1e90de..e956edb87398 100644
> > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > @@ -2180,7 +2180,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
> > > > > if (DISPLAY_VER(i915) < 12)
> > > > > return false;
> > > > >
> > > > > - /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> > > > > + /* Wa_14010477008 */
> > > > > if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
> > > > > IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
> > > > > return false;
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > index 4efc1a532982..82a8f372bde6 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > @@ -1456,31 +1456,6 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > > > > wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
> > > > > }
> > > > >
> > > > > -static void
> > > > > -tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > > > > -{
> > > > > - struct drm_i915_private *i915 = gt->i915;
> > > > > -
> > > > > - gen12_gt_workarounds_init(gt, wal);
> > > > > -
> > > > > - /* Wa_1409420604:tgl */
> > > > > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > > > > - wa_mcr_write_or(wal,
> > > > > - SUBSLICE_UNIT_LEVEL_CLKGATE2,
> > > > > - CPSSUNIT_CLKGATE_DIS);
> > > > > -
> > > > > - /* Wa_1607087056:tgl also know as BUG:1409180338 */
> > > > > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > > > > - wa_write_or(wal,
> > > > > - GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > > > > - L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> > > > > -
> > > > > - /* Wa_1408615072:tgl[a0] */
> > > > > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > > > > - wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> > > > > - VSUNIT_CLKGATE_DIS_TGL);
> > > > > -}
> > > > > -
> > > > > static void
> > > > > dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > > > > {
> > > > > @@ -1716,8 +1691,6 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
> > > > > xehpsdv_gt_workarounds_init(gt, wal);
> > > > > else if (IS_DG1(i915))
> > > > > dg1_gt_workarounds_init(gt, wal);
> > > > > - else if (IS_TIGERLAKE(i915))
> > > > > - tgl_gt_workarounds_init(gt, wal);
> > > > > else if (GRAPHICS_VER(i915) == 12)
> > > > > gen12_gt_workarounds_init(gt, wal);
> > > > > else if (GRAPHICS_VER(i915) == 11)
> > > > > @@ -2437,27 +2410,16 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > > true);
> > > > > }
> > > > >
> > > > > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > > > > - IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > > > > + if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > > > > /*
> > > > > - * Wa_1607138336:tgl[a0],dg1[a0]
> > > > > - * Wa_1607063988:tgl[a0],dg1[a0]
> > > > > + * Wa_1607138336
> > > > > + * Wa_1607063988
> > > > > */
> > > > > wa_write_or(wal,
> > > > > GEN9_CTX_PREEMPT_REG,
> > > > > GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> > > > > }
> > > > >
> > > > > - if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > > > > - /*
> > > > > - * Wa_1606679103:tgl
> > > > > - * (see also Wa_1606682166:icl)
> > > > > - */
> > > > > - wa_write_or(wal,
> > > > > - GEN7_SARCHKMD,
> > > > > - GEN7_DISABLE_SAMPLER_PREFETCH);
> > > > > - }
> > > > > -
> > > > > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> > > > > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > > > > /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> > > > > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> > > > > index cf1c0970ecb4..879ab4ed42af 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_driver.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > > > > @@ -167,6 +167,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
> > > > > pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> > > > > pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
> > > > > pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
> > > > > + pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> > > > >
> > > > > if (pre) {
> > > > > drm_err(&dev_priv->drm, "This is a pre-production stepping. "
> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > > > index 48c838b4ea62..62cc0f76c583 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > > @@ -653,14 +653,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > > > > (IS_TIGERLAKE(__i915) && \
> > > > > IS_DISPLAY_STEP(__i915, since, until))
> > > > >
> > > > > -#define IS_TGL_UY_GRAPHICS_STEP(__i915, since, until) \
> > > > > - (IS_TGL_UY(__i915) && \
> > > > > - IS_GRAPHICS_STEP(__i915, since, until))
> > > > > -
> > > > > -#define IS_TGL_GRAPHICS_STEP(__i915, since, until) \
> > > > > - (IS_TIGERLAKE(__i915) && !IS_TGL_UY(__i915)) && \
> > > > > - IS_GRAPHICS_STEP(__i915, since, until))
> > > > > -
> > > > > #define IS_RKL_DISPLAY_STEP(p, since, until) \
> > > > > (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > > > index 3fc65bd12cc1..c6676f1a9c6f 100644
> > > > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > > > @@ -4336,10 +4336,6 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
> > > > > intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> > > > > DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> > > > >
> > > > > - /* Wa_1409825376:tgl (pre-prod)*/
> > > > > - if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0))
> > > > > - intel_uncore_rmw(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, 0, TGL_VRH_GATING_DIS);
> > > > > -
> > > > > /* Wa_14013723622:tgl,rkl,dg1,adl-s */
> > > > > if (DISPLAY_VER(dev_priv) == 12)
> > > > > intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY,
> > > > > --
> > > > > 2.39.1
> > > > >
> > >
> > > --
> > > Matt Roper
> > > Graphics Software Engineer
> > > Linux GPU Platform Enablement
> > > Intel Corporation
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg1: Drop support for pre-production steppings
2023-01-27 22:43 ` [Intel-gfx] [PATCH 2/3] drm/i915/dg1: " Matt Roper
@ 2023-01-30 17:19 ` Rodrigo Vivi
2023-01-30 17:34 ` Matt Roper
0 siblings, 1 reply; 16+ messages in thread
From: Rodrigo Vivi @ 2023-01-30 17:19 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Fri, Jan 27, 2023 at 02:43:12PM -0800, Matt Roper wrote:
> Several post-DG1 platforms have been brought up now, so we're well past
> the point where we usually drop the workarounds that are only applicable
> to internal/pre-production hardware.
>
> Production DG1 hardware always has a B0 stepping for both display and
> GT.
>
> Bspec: 44463
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 1 -
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++-----------------
> drivers/gpu/drm/i915/i915_driver.c | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 2 -
> drivers/gpu/drm/i915/intel_pm.c | 12 -----
> 5 files changed, 5 insertions(+), 59 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 1dc31f0f5e0a..7222502a760c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1580,7 +1580,6 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> return;
>
> if (IS_ALDERLAKE_S(dev_priv) ||
> - IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> /* Wa_1409767108 */
> table = wa_1409767108_buddy_page_masks;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 82a8f372bde6..648fceba5bb6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1463,12 +1463,6 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>
> gen12_gt_workarounds_init(gt, wal);
>
> - /* Wa_1607087056:dg1 */
> - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> - wa_write_or(wal,
> - GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> - L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> -
> /* Wa_1409420604:dg1 */
> if (IS_DG1(i915))
> wa_mcr_write_or(wal,
> @@ -2103,20 +2097,6 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
> }
> }
>
> -static void dg1_whitelist_build(struct intel_engine_cs *engine)
> -{
> - struct i915_wa_list *w = &engine->whitelist;
> -
> - tgl_whitelist_build(engine);
> -
> - /* GEN:BUG:1409280441:dg1 */
> - if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) &&
> - (engine->class == RENDER_CLASS ||
> - engine->class == COPY_ENGINE_CLASS))
> - whitelist_reg_ext(w, RING_ID(engine->mmio_base),
> - RING_FORCE_TO_NONPRIV_ACCESS_RD);
> -}
> -
> static void xehpsdv_whitelist_build(struct intel_engine_cs *engine)
> {
> allow_read_ctx_timestamp(engine);
> @@ -2196,8 +2176,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> dg2_whitelist_build(engine);
> else if (IS_XEHPSDV(i915))
> xehpsdv_whitelist_build(engine);
> - else if (IS_DG1(i915))
> - dg1_whitelist_build(engine);
> else if (GRAPHICS_VER(i915) == 12)
> tgl_whitelist_build(engine);
> else if (GRAPHICS_VER(i915) == 11)
> @@ -2410,16 +2388,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> true);
> }
>
> - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> - /*
> - * Wa_1607138336
> - * Wa_1607063988
> - */
> - wa_write_or(wal,
> - GEN9_CTX_PREEMPT_REG,
> - GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> - }
> -
> if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> @@ -2449,30 +2417,22 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> }
>
> if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
> - IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> - /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
> + /* Wa_1409804808 */
> wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> GEN12_PUSH_CONST_DEREF_HOLD_DIS);
>
> - /*
> - * Wa_1409085225:tgl
> - * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p
> - */
> + /* Wa_14010229206 */
> wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
> }
>
> - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> - IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
> + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
> /*
> - * Wa_1607030317:tgl
> - * Wa_1607186500:tgl
> - * Wa_1607297627:tgl,rkl,dg1[a0],adlp
> + * Wa_1607297627
> *
> * On TGL and RKL there are multiple entries for this WA in the
> * BSpec; some indicate this is an A0-only WA, others indicate
> * it applies to all steppings so we trust the "all steppings."
> - * For DG1 this only applies to A0.
> */
> wa_masked_en(wal,
> RING_PSMI_CTL(RENDER_RING_BASE),
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 879ab4ed42af..397a2159fe12 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -168,6 +168,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
> pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
> pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
> pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> + pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
>
> if (pre) {
> drm_err(&dev_priv->drm, "This is a pre-production stepping. "
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 62cc0f76c583..57b84dbca084 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -658,8 +658,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define IS_DG1_GRAPHICS_STEP(p, since, until) \
> (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
> -#define IS_DG1_DISPLAY_STEP(p, since, until) \
> - (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
>
> #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
> (IS_ALDERLAKE_S(__i915) && \
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c6676f1a9c6f..e0364c4141b8 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4353,15 +4353,6 @@ static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
> intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
> }
>
> -static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
> -{
> - gen12lp_init_clock_gating(dev_priv);
> -
> - /* Wa_1409836686:dg1[a0] */
> - if (IS_DG1_GRAPHICS_STEP(dev_priv, STEP_A0, STEP_B0))
> - intel_uncore_rmw(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, 0, DPT_GATING_DIS);
> -}
> -
> static void xehpsdv_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> /* Wa_22010146351:xehpsdv */
> @@ -4781,7 +4772,6 @@ CG_FUNCS(pvc);
> CG_FUNCS(dg2);
> CG_FUNCS(xehpsdv);
> CG_FUNCS(adlp);
> -CG_FUNCS(dg1);
> CG_FUNCS(gen12lp);
> CG_FUNCS(icl);
> CG_FUNCS(cfl);
> @@ -4824,8 +4814,6 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> dev_priv->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
> else if (IS_ALDERLAKE_P(dev_priv))
> dev_priv->clock_gating_funcs = &adlp_clock_gating_funcs;
> - else if (IS_DG1(dev_priv))
> - dev_priv->clock_gating_funcs = &dg1_clock_gating_funcs;
This will create warnings:
MISSING_CASE down below...
> else if (GRAPHICS_VER(dev_priv) == 12)
> dev_priv->clock_gating_funcs = &gen12lp_clock_gating_funcs;
> else if (GRAPHICS_VER(dev_priv) == 11)
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 3/3] drm/i915/dg1: Drop final use of IS_DG1_GRAPHICS_STEP
2023-01-27 22:43 ` [Intel-gfx] [PATCH 3/3] drm/i915/dg1: Drop final use of IS_DG1_GRAPHICS_STEP Matt Roper
@ 2023-01-30 17:20 ` Rodrigo Vivi
0 siblings, 0 replies; 16+ messages in thread
From: Rodrigo Vivi @ 2023-01-30 17:20 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Fri, Jan 27, 2023 at 02:43:13PM -0800, Matt Roper wrote:
> All production DG1 hardware has graphics stepping B0; there is no such
> thing as C0. As such, we can simplify
>
> IS_DG1_GRAPHICS_STEP(uncore->i915, STEP_A0, STEP_C0)
>
> to just match DG1 in general.
>
> Bspec: 44463
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 ---
> 2 files changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index f3ad93db0b21..89fdfc67f8d1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -158,7 +158,7 @@ static const struct intel_memory_region_ops intel_region_lmem_ops = {
> static bool get_legacy_lowmem_region(struct intel_uncore *uncore,
> u64 *start, u32 *size)
> {
> - if (!IS_DG1_GRAPHICS_STEP(uncore->i915, STEP_A0, STEP_C0))
> + if (!IS_DG1(uncore->i915))
> return false;
>
> *start = 0;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 57b84dbca084..495788e18b77 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -656,9 +656,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_RKL_DISPLAY_STEP(p, since, until) \
> (IS_ROCKETLAKE(p) && IS_DISPLAY_STEP(p, since, until))
>
> -#define IS_DG1_GRAPHICS_STEP(p, since, until) \
> - (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
> -
> #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
> (IS_ALDERLAKE_S(__i915) && \
> IS_DISPLAY_STEP(__i915, since, until))
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg1: Drop support for pre-production steppings
2023-01-30 17:19 ` Rodrigo Vivi
@ 2023-01-30 17:34 ` Matt Roper
2023-01-30 18:03 ` Rodrigo Vivi
0 siblings, 1 reply; 16+ messages in thread
From: Matt Roper @ 2023-01-30 17:34 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Mon, Jan 30, 2023 at 12:19:48PM -0500, Rodrigo Vivi wrote:
> On Fri, Jan 27, 2023 at 02:43:12PM -0800, Matt Roper wrote:
> > Several post-DG1 platforms have been brought up now, so we're well past
> > the point where we usually drop the workarounds that are only applicable
> > to internal/pre-production hardware.
> >
> > Production DG1 hardware always has a B0 stepping for both display and
> > GT.
> >
> > Bspec: 44463
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > .../drm/i915/display/intel_display_power.c | 1 -
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++-----------------
> > drivers/gpu/drm/i915/i915_driver.c | 1 +
> > drivers/gpu/drm/i915/i915_drv.h | 2 -
> > drivers/gpu/drm/i915/intel_pm.c | 12 -----
> > 5 files changed, 5 insertions(+), 59 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 1dc31f0f5e0a..7222502a760c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -1580,7 +1580,6 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> > return;
> >
> > if (IS_ALDERLAKE_S(dev_priv) ||
> > - IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > /* Wa_1409767108 */
> > table = wa_1409767108_buddy_page_masks;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 82a8f372bde6..648fceba5bb6 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -1463,12 +1463,6 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> >
> > gen12_gt_workarounds_init(gt, wal);
> >
> > - /* Wa_1607087056:dg1 */
> > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > - wa_write_or(wal,
> > - GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > - L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> > -
> > /* Wa_1409420604:dg1 */
> > if (IS_DG1(i915))
> > wa_mcr_write_or(wal,
> > @@ -2103,20 +2097,6 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
> > }
> > }
> >
> > -static void dg1_whitelist_build(struct intel_engine_cs *engine)
> > -{
> > - struct i915_wa_list *w = &engine->whitelist;
> > -
> > - tgl_whitelist_build(engine);
> > -
> > - /* GEN:BUG:1409280441:dg1 */
> > - if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) &&
> > - (engine->class == RENDER_CLASS ||
> > - engine->class == COPY_ENGINE_CLASS))
> > - whitelist_reg_ext(w, RING_ID(engine->mmio_base),
> > - RING_FORCE_TO_NONPRIV_ACCESS_RD);
> > -}
> > -
> > static void xehpsdv_whitelist_build(struct intel_engine_cs *engine)
> > {
> > allow_read_ctx_timestamp(engine);
> > @@ -2196,8 +2176,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> > dg2_whitelist_build(engine);
> > else if (IS_XEHPSDV(i915))
> > xehpsdv_whitelist_build(engine);
> > - else if (IS_DG1(i915))
> > - dg1_whitelist_build(engine);
> > else if (GRAPHICS_VER(i915) == 12)
> > tgl_whitelist_build(engine);
> > else if (GRAPHICS_VER(i915) == 11)
> > @@ -2410,16 +2388,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > true);
> > }
> >
> > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > - /*
> > - * Wa_1607138336
> > - * Wa_1607063988
> > - */
> > - wa_write_or(wal,
> > - GEN9_CTX_PREEMPT_REG,
> > - GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> > - }
> > -
> > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> > @@ -2449,30 +2417,22 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > }
> >
> > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
> > - IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > - /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
> > + /* Wa_1409804808 */
> > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> > GEN12_PUSH_CONST_DEREF_HOLD_DIS);
> >
> > - /*
> > - * Wa_1409085225:tgl
> > - * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p
> > - */
> > + /* Wa_14010229206 */
> > wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
> > }
> >
> > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > - IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
> > + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
> > /*
> > - * Wa_1607030317:tgl
> > - * Wa_1607186500:tgl
> > - * Wa_1607297627:tgl,rkl,dg1[a0],adlp
> > + * Wa_1607297627
> > *
> > * On TGL and RKL there are multiple entries for this WA in the
> > * BSpec; some indicate this is an A0-only WA, others indicate
> > * it applies to all steppings so we trust the "all steppings."
> > - * For DG1 this only applies to A0.
> > */
> > wa_masked_en(wal,
> > RING_PSMI_CTL(RENDER_RING_BASE),
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> > index 879ab4ed42af..397a2159fe12 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -168,6 +168,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
> > pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
> > pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
> > pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> > + pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> >
> > if (pre) {
> > drm_err(&dev_priv->drm, "This is a pre-production stepping. "
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 62cc0f76c583..57b84dbca084 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -658,8 +658,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> >
> > #define IS_DG1_GRAPHICS_STEP(p, since, until) \
> > (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
> > -#define IS_DG1_DISPLAY_STEP(p, since, until) \
> > - (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
> >
> > #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
> > (IS_ALDERLAKE_S(__i915) && \
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index c6676f1a9c6f..e0364c4141b8 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -4353,15 +4353,6 @@ static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
> > intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
> > }
> >
> > -static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
> > -{
> > - gen12lp_init_clock_gating(dev_priv);
> > -
> > - /* Wa_1409836686:dg1[a0] */
> > - if (IS_DG1_GRAPHICS_STEP(dev_priv, STEP_A0, STEP_B0))
> > - intel_uncore_rmw(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, 0, DPT_GATING_DIS);
> > -}
> > -
> > static void xehpsdv_init_clock_gating(struct drm_i915_private *dev_priv)
> > {
> > /* Wa_22010146351:xehpsdv */
> > @@ -4781,7 +4772,6 @@ CG_FUNCS(pvc);
> > CG_FUNCS(dg2);
> > CG_FUNCS(xehpsdv);
> > CG_FUNCS(adlp);
> > -CG_FUNCS(dg1);
> > CG_FUNCS(gen12lp);
> > CG_FUNCS(icl);
> > CG_FUNCS(cfl);
> > @@ -4824,8 +4814,6 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> > dev_priv->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
> > else if (IS_ALDERLAKE_P(dev_priv))
> > dev_priv->clock_gating_funcs = &adlp_clock_gating_funcs;
> > - else if (IS_DG1(dev_priv))
> > - dev_priv->clock_gating_funcs = &dg1_clock_gating_funcs;
>
> This will create warnings:
>
> MISSING_CASE down below...
It shouldn't make it down that far since:
> > else if (GRAPHICS_VER(dev_priv) == 12)
will now match for DG1.
Matt
> > dev_priv->clock_gating_funcs = &gen12lp_clock_gating_funcs;
> > else if (GRAPHICS_VER(dev_priv) == 11)
> > --
> > 2.39.1
> >
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/dg1: Drop support for pre-production steppings
2023-01-30 17:34 ` Matt Roper
@ 2023-01-30 18:03 ` Rodrigo Vivi
0 siblings, 0 replies; 16+ messages in thread
From: Rodrigo Vivi @ 2023-01-30 18:03 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Mon, Jan 30, 2023 at 09:34:22AM -0800, Matt Roper wrote:
> On Mon, Jan 30, 2023 at 12:19:48PM -0500, Rodrigo Vivi wrote:
> > On Fri, Jan 27, 2023 at 02:43:12PM -0800, Matt Roper wrote:
> > > Several post-DG1 platforms have been brought up now, so we're well past
> > > the point where we usually drop the workarounds that are only applicable
> > > to internal/pre-production hardware.
> > >
> > > Production DG1 hardware always has a B0 stepping for both display and
> > > GT.
> > >
> > > Bspec: 44463
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_power.c | 1 -
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 48 ++-----------------
> > > drivers/gpu/drm/i915/i915_driver.c | 1 +
> > > drivers/gpu/drm/i915/i915_drv.h | 2 -
> > > drivers/gpu/drm/i915/intel_pm.c | 12 -----
> > > 5 files changed, 5 insertions(+), 59 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 1dc31f0f5e0a..7222502a760c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -1580,7 +1580,6 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
> > > return;
> > >
> > > if (IS_ALDERLAKE_S(dev_priv) ||
> > > - IS_DG1_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > > IS_RKL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > > /* Wa_1409767108 */
> > > table = wa_1409767108_buddy_page_masks;
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index 82a8f372bde6..648fceba5bb6 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -1463,12 +1463,6 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > >
> > > gen12_gt_workarounds_init(gt, wal);
> > >
> > > - /* Wa_1607087056:dg1 */
> > > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > > - wa_write_or(wal,
> > > - GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > > - L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> > > -
> > > /* Wa_1409420604:dg1 */
> > > if (IS_DG1(i915))
> > > wa_mcr_write_or(wal,
> > > @@ -2103,20 +2097,6 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
> > > }
> > > }
> > >
> > > -static void dg1_whitelist_build(struct intel_engine_cs *engine)
> > > -{
> > > - struct i915_wa_list *w = &engine->whitelist;
> > > -
> > > - tgl_whitelist_build(engine);
> > > -
> > > - /* GEN:BUG:1409280441:dg1 */
> > > - if (IS_DG1_GRAPHICS_STEP(engine->i915, STEP_A0, STEP_B0) &&
> > > - (engine->class == RENDER_CLASS ||
> > > - engine->class == COPY_ENGINE_CLASS))
> > > - whitelist_reg_ext(w, RING_ID(engine->mmio_base),
> > > - RING_FORCE_TO_NONPRIV_ACCESS_RD);
> > > -}
> > > -
> > > static void xehpsdv_whitelist_build(struct intel_engine_cs *engine)
> > > {
> > > allow_read_ctx_timestamp(engine);
> > > @@ -2196,8 +2176,6 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
> > > dg2_whitelist_build(engine);
> > > else if (IS_XEHPSDV(i915))
> > > xehpsdv_whitelist_build(engine);
> > > - else if (IS_DG1(i915))
> > > - dg1_whitelist_build(engine);
> > > else if (GRAPHICS_VER(i915) == 12)
> > > tgl_whitelist_build(engine);
> > > else if (GRAPHICS_VER(i915) == 11)
> > > @@ -2410,16 +2388,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > true);
> > > }
> > >
> > > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
> > > - /*
> > > - * Wa_1607138336
> > > - * Wa_1607063988
> > > - */
> > > - wa_write_or(wal,
> > > - GEN9_CTX_PREEMPT_REG,
> > > - GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> > > - }
> > > -
> > > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> > > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > > /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> > > @@ -2449,30 +2417,22 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > }
> > >
> > > if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) ||
> > > - IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > > IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> > > - /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
> > > + /* Wa_1409804808 */
> > > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> > > GEN12_PUSH_CONST_DEREF_HOLD_DIS);
> > >
> > > - /*
> > > - * Wa_1409085225:tgl
> > > - * Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p
> > > - */
> > > + /* Wa_14010229206 */
> > > wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
> > > }
> > >
> > > - if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> > > - IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
> > > + if (IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) {
> > > /*
> > > - * Wa_1607030317:tgl
> > > - * Wa_1607186500:tgl
> > > - * Wa_1607297627:tgl,rkl,dg1[a0],adlp
> > > + * Wa_1607297627
> > > *
> > > * On TGL and RKL there are multiple entries for this WA in the
> > > * BSpec; some indicate this is an A0-only WA, others indicate
> > > * it applies to all steppings so we trust the "all steppings."
> > > - * For DG1 this only applies to A0.
> > > */
> > > wa_masked_en(wal,
> > > RING_PSMI_CTL(RENDER_RING_BASE),
> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> > > index 879ab4ed42af..397a2159fe12 100644
> > > --- a/drivers/gpu/drm/i915/i915_driver.c
> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > > @@ -168,6 +168,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
> > > pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
> > > pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
> > > pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> > > + pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
> > >
> > > if (pre) {
> > > drm_err(&dev_priv->drm, "This is a pre-production stepping. "
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index 62cc0f76c583..57b84dbca084 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -658,8 +658,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > >
> > > #define IS_DG1_GRAPHICS_STEP(p, since, until) \
> > > (IS_DG1(p) && IS_GRAPHICS_STEP(p, since, until))
> > > -#define IS_DG1_DISPLAY_STEP(p, since, until) \
> > > - (IS_DG1(p) && IS_DISPLAY_STEP(p, since, until))
> > >
> > > #define IS_ADLS_DISPLAY_STEP(__i915, since, until) \
> > > (IS_ALDERLAKE_S(__i915) && \
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index c6676f1a9c6f..e0364c4141b8 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4353,15 +4353,6 @@ static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
> > > intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
> > > }
> > >
> > > -static void dg1_init_clock_gating(struct drm_i915_private *dev_priv)
> > > -{
> > > - gen12lp_init_clock_gating(dev_priv);
> > > -
> > > - /* Wa_1409836686:dg1[a0] */
> > > - if (IS_DG1_GRAPHICS_STEP(dev_priv, STEP_A0, STEP_B0))
> > > - intel_uncore_rmw(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, 0, DPT_GATING_DIS);
> > > -}
> > > -
> > > static void xehpsdv_init_clock_gating(struct drm_i915_private *dev_priv)
> > > {
> > > /* Wa_22010146351:xehpsdv */
> > > @@ -4781,7 +4772,6 @@ CG_FUNCS(pvc);
> > > CG_FUNCS(dg2);
> > > CG_FUNCS(xehpsdv);
> > > CG_FUNCS(adlp);
> > > -CG_FUNCS(dg1);
> > > CG_FUNCS(gen12lp);
> > > CG_FUNCS(icl);
> > > CG_FUNCS(cfl);
> > > @@ -4824,8 +4814,6 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> > > dev_priv->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
> > > else if (IS_ALDERLAKE_P(dev_priv))
> > > dev_priv->clock_gating_funcs = &adlp_clock_gating_funcs;
> > > - else if (IS_DG1(dev_priv))
> > > - dev_priv->clock_gating_funcs = &dg1_clock_gating_funcs;
> >
> > This will create warnings:
> >
> > MISSING_CASE down below...
>
> It shouldn't make it down that far since:
>
> > > else if (GRAPHICS_VER(dev_priv) == 12)
>
> will now match for DG1.
doh! indeed what we want...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
>
> Matt
>
> > > dev_priv->clock_gating_funcs = &gen12lp_clock_gating_funcs;
> > > else if (GRAPHICS_VER(dev_priv) == 11)
> > > --
> > > 2.39.1
> > >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] ✓ Fi.CI.IGT: success for Drop TGL/DG1 workarounds for pre-prod steppings
2023-01-28 6:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-01-30 18:18 ` Matt Roper
0 siblings, 0 replies; 16+ messages in thread
From: Matt Roper @ 2023-01-30 18:18 UTC (permalink / raw)
To: intel-gfx
On Sat, Jan 28, 2023 at 06:28:35AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: Drop TGL/DG1 workarounds for pre-prod steppings
> URL : https://patchwork.freedesktop.org/series/113453/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_12658_full -> Patchwork_113453v1_full
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
Applied to di-next. Thanks Rodrigo for the reviews.
Matt
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/index.html
>
> Participating hosts (10 -> 10)
> ------------------------------
>
> No changes in participating hosts
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_113453v1_full:
>
> ### IGT changes ###
>
> #### Suppressed ####
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_exec_suspend@basic-s3-devices@smem:
> - {shard-rkl}: [PASS][1] -> [FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-6/igt@gem_exec_suspend@basic-s3-devices@smem.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-4/igt@gem_exec_suspend@basic-s3-devices@smem.html
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_113453v1_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_exec_fair@basic-pace-solo@rcs0:
> - shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-glk3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-glk5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
>
> * igt@perf@stress-open-close:
> - shard-glk: [PASS][5] -> [ABORT][6] ([i915#5213])
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-glk5/igt@perf@stress-open-close.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-glk9/igt@perf@stress-open-close.html
>
>
> #### Possible fixes ####
>
> * igt@drm_fdinfo@idle@rcs0:
> - {shard-rkl}: [FAIL][7] ([i915#7742]) -> [PASS][8]
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-4/igt@drm_fdinfo@idle@rcs0.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@drm_fdinfo@idle@rcs0.html
>
> * igt@drm_read@empty-block:
> - {shard-rkl}: [SKIP][9] ([i915#4098]) -> [PASS][10] +2 similar issues
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@drm_read@empty-block.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@drm_read@empty-block.html
>
> * igt@fbdev@unaligned-read:
> - {shard-rkl}: [SKIP][11] ([i915#2582]) -> [PASS][12]
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-2/igt@fbdev@unaligned-read.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@fbdev@unaligned-read.html
>
> * igt@gem_eio@in-flight-suspend:
> - {shard-rkl}: [FAIL][13] ([fdo#103375]) -> [PASS][14]
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@gem_eio@in-flight-suspend.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@gem_eio@in-flight-suspend.html
>
> * igt@gem_exec_capture@pi@vcs0:
> - {shard-rkl}: [ABORT][15] -> [PASS][16]
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-6/igt@gem_exec_capture@pi@vcs0.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@gem_exec_capture@pi@vcs0.html
>
> * igt@gem_exec_fair@basic-pace-share@rcs0:
> - {shard-tglu}: [FAIL][17] ([i915#2842]) -> [PASS][18]
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-tglu-7/igt@gem_exec_fair@basic-pace-share@rcs0.html
>
> * igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
> - {shard-rkl}: [SKIP][19] ([i915#3281]) -> [PASS][20] +4 similar issues
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
>
> * igt@gem_mmap_wc@set-cache-level:
> - {shard-rkl}: [SKIP][21] ([i915#1850]) -> [PASS][22]
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-4/igt@gem_mmap_wc@set-cache-level.html
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@gem_mmap_wc@set-cache-level.html
>
> * igt@gem_pwrite@basic-self:
> - {shard-rkl}: [SKIP][23] ([i915#3282]) -> [PASS][24] +4 similar issues
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@gem_pwrite@basic-self.html
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@gem_pwrite@basic-self.html
>
> * igt@gem_sync@basic-all:
> - shard-glk: [DMESG-WARN][25] ([i915#118]) -> [PASS][26]
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-glk4/igt@gem_sync@basic-all.html
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-glk1/igt@gem_sync@basic-all.html
>
> * igt@gen9_exec_parse@batch-invalid-length:
> - {shard-rkl}: [SKIP][27] ([i915#2527]) -> [PASS][28]
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@gen9_exec_parse@batch-invalid-length.html
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@gen9_exec_parse@batch-invalid-length.html
>
> * igt@i915_pm_dc@dc9-dpms:
> - {shard-rkl}: [SKIP][29] ([i915#3361]) -> [PASS][30]
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-5/igt@i915_pm_dc@dc9-dpms.html
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-2/igt@i915_pm_dc@dc9-dpms.html
>
> * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
> - {shard-rkl}: [WARN][31] ([i915#2681]) -> [PASS][32]
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-2/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
>
> * igt@i915_pm_rpm@i2c:
> - {shard-rkl}: [SKIP][33] ([fdo#109308]) -> [PASS][34]
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@i915_pm_rpm@i2c.html
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@i915_pm_rpm@i2c.html
>
> * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
> - {shard-rkl}: [SKIP][35] ([i915#1845] / [i915#4098]) -> [PASS][36] +28 similar issues
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
>
> * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
> - shard-glk: [FAIL][37] ([i915#79]) -> [PASS][38]
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
>
> * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
> - {shard-rkl}: [SKIP][39] ([i915#1849] / [i915#4098]) -> [PASS][40] +21 similar issues
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
>
> * igt@kms_plane@plane-position-hole@pipe-b-planes:
> - {shard-rkl}: [SKIP][41] ([i915#1849]) -> [PASS][42] +2 similar issues
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-4/igt@kms_plane@plane-position-hole@pipe-b-planes.html
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@kms_plane@plane-position-hole@pipe-b-planes.html
>
> * igt@kms_psr@no_drrs:
> - {shard-rkl}: [SKIP][43] ([i915#1072]) -> [PASS][44] +1 similar issue
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-4/igt@kms_psr@no_drrs.html
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@kms_psr@no_drrs.html
>
> * igt@kms_universal_plane@universal-plane-pipe-a-sanity:
> - {shard-rkl}: [SKIP][45] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][46]
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-2/igt@kms_universal_plane@universal-plane-pipe-a-sanity.html
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-a-sanity.html
>
> * igt@perf@mi-rpc:
> - {shard-rkl}: [SKIP][47] ([i915#2434]) -> [PASS][48]
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@perf@mi-rpc.html
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@perf@mi-rpc.html
>
> * igt@perf_pmu@most-busy-idle-check-all@rcs0:
> - {shard-rkl}: [FAIL][49] ([i915#4349]) -> [PASS][50]
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-4/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-2/igt@perf_pmu@most-busy-idle-check-all@rcs0.html
>
> * igt@prime_vgem@basic-write:
> - {shard-rkl}: [SKIP][51] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][52]
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@prime_vgem@basic-write.html
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@prime_vgem@basic-write.html
>
> * igt@prime_vgem@coherency-gtt:
> - {shard-rkl}: [SKIP][53] ([fdo#109295] / [fdo#111656] / [i915#3708]) -> [PASS][54]
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12658/shard-rkl-3/igt@prime_vgem@coherency-gtt.html
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/shard-rkl-5/igt@prime_vgem@coherency-gtt.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
> [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
> [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
> [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
> [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
> [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
> [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
> [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
> [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
> [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
> [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
> [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
> [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
> [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
> [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
> [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
> [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
> [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
> [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
> [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
> [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
> [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
> [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
> [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
> [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
> [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
> [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
> [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
> [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
> [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
> [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
> [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
> [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
> [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
> [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
> [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
> [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
> [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
> [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
> [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
> [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
> [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
> [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
> [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
> [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
> [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
> [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
> [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
> [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
> [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
> [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
> [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
> [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
> [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
> [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
> [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
> [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
> [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
> [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
> [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
> [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
> [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
> [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
> [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
> [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
> [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
> [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
> [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
> [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
> [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
> [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
> [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
> [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
> [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
> [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
> [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
> [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
> [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
> [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
> [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
> [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
> [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
> [i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
> [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
> [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
> [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
> [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
> [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
> [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
> [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
> [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
> [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
> [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
> [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
> [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
> [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
> [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
> [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
> [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
> [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
> [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
> [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
> [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
> [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
> [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
> [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
> [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
> [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
> [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
> [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
> [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
> [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
> [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
> [i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
> [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
> [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
> [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
> [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
> [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
> [i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
> [i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
> [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
> [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
> [i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
> [i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
> [i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
> [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
> [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
> [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
> [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
> [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
> [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
> [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
> [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
> [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
> [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
> [i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
> [i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_12658 -> Patchwork_113453v1
>
> CI-20190529: 20190529
> CI_DRM_12658: a9e72f4e0baf2e3e306da0063f98099044d85285 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_7141: a978df7912acda18eada1b1d2ae4b438ed3e940b @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_113453v1: a9e72f4e0baf2e3e306da0063f98099044d85285 @ git://anongit.freedesktop.org/gfx-ci/linux
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113453v1/index.html
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-01-30 18:19 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-27 22:43 [Intel-gfx] [PATCH 0/3] Drop TGL/DG1 workarounds for pre-prod steppings Matt Roper
2023-01-27 22:43 ` [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Drop support for pre-production steppings Matt Roper
2023-01-30 15:46 ` Rodrigo Vivi
2023-01-30 15:51 ` Matt Roper
2023-01-30 16:42 ` Rodrigo Vivi
2023-01-30 17:03 ` Matt Roper
2023-01-30 17:19 ` Rodrigo Vivi
2023-01-27 22:43 ` [Intel-gfx] [PATCH 2/3] drm/i915/dg1: " Matt Roper
2023-01-30 17:19 ` Rodrigo Vivi
2023-01-30 17:34 ` Matt Roper
2023-01-30 18:03 ` Rodrigo Vivi
2023-01-27 22:43 ` [Intel-gfx] [PATCH 3/3] drm/i915/dg1: Drop final use of IS_DG1_GRAPHICS_STEP Matt Roper
2023-01-30 17:20 ` Rodrigo Vivi
2023-01-27 23:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Drop TGL/DG1 workarounds for pre-prod steppings Patchwork
2023-01-28 6:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-01-30 18:18 ` Matt Roper
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