[PATCH] riscv: mm: fix regression due to update_mmu_cache change

[PATCH] riscv: mm: fix regression due to update_mmu_cache change

[Sergey Matyukevich]

From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>

This is a partial revert of the commit 4bd1d80efb5a ("riscv: mm: notify
remote harts about mmu cache updates"). Original commit included two
loosely related changes serving the same purpose of fixing stale TLB
entries causing user-space application crash:
- introduce deferred per-ASID TLB flush for CPUs not running the task
- switch to per-ASID TLB flush on all CPUs running the task in update_mmu_cache

According to report and discussion in [1], the second part caused a
regression on Renesas RZ/Five SoC. For now restore the old behavior
of the update_mmu_cache.

[1] https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/

Fixes: 4bd1d80efb5a ("riscv: mm: notify remote harts about mmu cache updates")
Reported-by: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
---
 arch/riscv/include/asm/pgtable.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 4eba9a98d0e3..4c3c130ee328 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -415,7 +415,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 	 * Relying on flush_tlb_fix_spurious_fault would suffice, but
 	 * the extra traps reduce performance.  So, eagerly SFENCE.VMA.
 	 */
-	flush_tlb_page(vma, address);
+	local_flush_tlb_page(address);
 }
 
 #define __HAVE_ARCH_UPDATE_MMU_TLB
-- 
2.39.0

[PATCH] riscv: mm: fix regression due to update_mmu_cache change

[Sergey Matyukevich]

From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>

This is a partial revert of the commit 4bd1d80efb5a ("riscv: mm: notify
remote harts about mmu cache updates"). Original commit included two
loosely related changes serving the same purpose of fixing stale TLB
entries causing user-space application crash:
- introduce deferred per-ASID TLB flush for CPUs not running the task
- switch to per-ASID TLB flush on all CPUs running the task in update_mmu_cache

According to report and discussion in [1], the second part caused a
regression on Renesas RZ/Five SoC. For now restore the old behavior
of the update_mmu_cache.

[1] https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/

Fixes: 4bd1d80efb5a ("riscv: mm: notify remote harts about mmu cache updates")
Reported-by: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
---
 arch/riscv/include/asm/pgtable.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 4eba9a98d0e3..4c3c130ee328 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -415,7 +415,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 	 * Relying on flush_tlb_fix_spurious_fault would suffice, but
 	 * the extra traps reduce performance.  So, eagerly SFENCE.VMA.
 	 */
-	flush_tlb_page(vma, address);
+	local_flush_tlb_page(address);
 }
 
 #define __HAVE_ARCH_UPDATE_MMU_TLB
-- 
2.39.0


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Re: [PATCH] riscv: mm: fix regression due to update_mmu_cache change

[Conor Dooley]

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On Mon, Jan 30, 2023 at 12:18:18AM +0300, Sergey Matyukevich wrote:
> From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> 
> This is a partial revert of the commit 4bd1d80efb5a ("riscv: mm: notify
> remote harts about mmu cache updates"). Original commit included two
> loosely related changes serving the same purpose of fixing stale TLB
> entries causing user-space application crash:
> - introduce deferred per-ASID TLB flush for CPUs not running the task
> - switch to per-ASID TLB flush on all CPUs running the task in update_mmu_cache
> 
> According to report and discussion in [1], the second part caused a
> regression on Renesas RZ/Five SoC. For now restore the old behavior
> of the update_mmu_cache.
> 
> [1] https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/

If you respin for another reason, can you convert this into a "regular"
Link: trailer, so that it can be parsed with git's trailer functionality?
IOW, like so:
Link: https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/ [1]

Otherwise, glad to see you two get this sorted out, even if it is just a
revert.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> Fixes: 4bd1d80efb5a ("riscv: mm: notify remote harts about mmu cache updates")
> Reported-by: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
> Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> ---
>  arch/riscv/include/asm/pgtable.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 4eba9a98d0e3..4c3c130ee328 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -415,7 +415,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
>  	 * Relying on flush_tlb_fix_spurious_fault would suffice, but
>  	 * the extra traps reduce performance.  So, eagerly SFENCE.VMA.
>  	 */
> -	flush_tlb_page(vma, address);
> +	local_flush_tlb_page(address);
>  }
>  
>  #define __HAVE_ARCH_UPDATE_MMU_TLB
> -- 
> 2.39.0
> 

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Re: [PATCH] riscv: mm: fix regression due to update_mmu_cache change

[Conor Dooley]

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On Mon, Jan 30, 2023 at 12:18:18AM +0300, Sergey Matyukevich wrote:
> From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> 
> This is a partial revert of the commit 4bd1d80efb5a ("riscv: mm: notify
> remote harts about mmu cache updates"). Original commit included two
> loosely related changes serving the same purpose of fixing stale TLB
> entries causing user-space application crash:
> - introduce deferred per-ASID TLB flush for CPUs not running the task
> - switch to per-ASID TLB flush on all CPUs running the task in update_mmu_cache
> 
> According to report and discussion in [1], the second part caused a
> regression on Renesas RZ/Five SoC. For now restore the old behavior
> of the update_mmu_cache.
> 
> [1] https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/

If you respin for another reason, can you convert this into a "regular"
Link: trailer, so that it can be parsed with git's trailer functionality?
IOW, like so:
Link: https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/ [1]

Otherwise, glad to see you two get this sorted out, even if it is just a
revert.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> Fixes: 4bd1d80efb5a ("riscv: mm: notify remote harts about mmu cache updates")
> Reported-by: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
> Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> ---
>  arch/riscv/include/asm/pgtable.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> index 4eba9a98d0e3..4c3c130ee328 100644
> --- a/arch/riscv/include/asm/pgtable.h
> +++ b/arch/riscv/include/asm/pgtable.h
> @@ -415,7 +415,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
>  	 * Relying on flush_tlb_fix_spurious_fault would suffice, but
>  	 * the extra traps reduce performance.  So, eagerly SFENCE.VMA.
>  	 */
> -	flush_tlb_page(vma, address);
> +	local_flush_tlb_page(address);
>  }
>  
>  #define __HAVE_ARCH_UPDATE_MMU_TLB
> -- 
> 2.39.0
> 

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Re: [PATCH] riscv: mm: fix regression due to update_mmu_cache change

[patchwork-bot+linux-riscv]

Hello:

This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Mon, 30 Jan 2023 00:18:18 +0300 you wrote:
> From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> 
> This is a partial revert of the commit 4bd1d80efb5a ("riscv: mm: notify
> remote harts about mmu cache updates"). Original commit included two
> loosely related changes serving the same purpose of fixing stale TLB
> entries causing user-space application crash:
> - introduce deferred per-ASID TLB flush for CPUs not running the task
> - switch to per-ASID TLB flush on all CPUs running the task in update_mmu_cache
> 
> [...]

Here is the summary with links:
  - riscv: mm: fix regression due to update_mmu_cache change
    https://git.kernel.org/riscv/c/b49f700668ff

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html

Re: [PATCH] riscv: mm: fix regression due to update_mmu_cache change

[patchwork-bot+linux-riscv]

Hello:

This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Mon, 30 Jan 2023 00:18:18 +0300 you wrote:
> From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
> 
> This is a partial revert of the commit 4bd1d80efb5a ("riscv: mm: notify
> remote harts about mmu cache updates"). Original commit included two
> loosely related changes serving the same purpose of fixing stale TLB
> entries causing user-space application crash:
> - introduce deferred per-ASID TLB flush for CPUs not running the task
> - switch to per-ASID TLB flush on all CPUs running the task in update_mmu_cache
> 
> [...]

Here is the summary with links:
  - riscv: mm: fix regression due to update_mmu_cache change
    https://git.kernel.org/riscv/c/b49f700668ff

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



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