* [PATCH] xio3130_downstream: Add ACS (Access Control Services) capability
@ 2023-01-31 6:30 wlfightup
2023-02-18 7:36 ` Paul Schlacter
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: wlfightup @ 2023-01-31 6:30 UTC (permalink / raw)
To: mst, marcel.apfelbaum; +Cc: qemu-devel, wlfightup
When vfio-pci devices are attached to the downstream, pcie acs
capability may be needed, Consistent with physical machine.
It has been tested in our environment, and pcie acs capability
is required in some scenarios.
Claim ACS support in the downstream port to allow
passthrough of individual functions of a device to different
guests (in a nested virt.setting) with VFIO.
Without this patch, all functions of a device, such as all VFs of
an SR/IOV device, will end up in the same IOMMU group.
A similar situation occurs on Windows with Hyper-V.
Signed-off-by: wlfightup <wlfightup@gmail.com>
---
hw/pci-bridge/xio3130_downstream.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
index 38a2361fa2..2017cf42a3 100644
--- a/hw/pci-bridge/xio3130_downstream.c
+++ b/hw/pci-bridge/xio3130_downstream.c
@@ -40,6 +40,8 @@
#define XIO3130_SSVID_SSID 0
#define XIO3130_EXP_OFFSET 0x90
#define XIO3130_AER_OFFSET 0x100
+#define XIO3130_ACS_OFFSET \
+ (XIO3130_AER_OFFSET + PCI_ERR_SIZEOF)
static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
uint32_t val, int len)
@@ -111,6 +113,10 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
goto err;
}
+ if (!s->disable_acs) {
+ pcie_acs_init(d, XIO3130_ACS_OFFSET);
+ }
+
return;
err:
@@ -137,6 +143,7 @@ static void xio3130_downstream_exitfn(PCIDevice *d)
static Property xio3130_downstream_props[] = {
DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
QEMU_PCIE_SLTCAP_PCP_BITNR, true),
+ DEFINE_PROP_BOOL("x-disable-acs", PCIESlot, disable_acs, true),
DEFINE_PROP_END_OF_LIST()
};
--
2.24.3 (Apple Git-128)
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] xio3130_downstream: Add ACS (Access Control Services) capability
2023-01-31 6:30 [PATCH] xio3130_downstream: Add ACS (Access Control Services) capability wlfightup
@ 2023-02-18 7:36 ` Paul Schlacter
2023-02-20 7:13 ` Philippe Mathieu-Daudé
2023-03-01 20:38 ` Michael S. Tsirkin
2 siblings, 0 replies; 6+ messages in thread
From: Paul Schlacter @ 2023-02-18 7:36 UTC (permalink / raw)
To: mst, marcel.apfelbaum; +Cc: qemu-devel
ping
On Tue, Jan 31, 2023 at 2:30 PM wlfightup <wlfightup@gmail.com> wrote:
>
> When vfio-pci devices are attached to the downstream, pcie acs
> capability may be needed, Consistent with physical machine.
>
> It has been tested in our environment, and pcie acs capability
> is required in some scenarios.
>
> Claim ACS support in the downstream port to allow
> passthrough of individual functions of a device to different
> guests (in a nested virt.setting) with VFIO.
> Without this patch, all functions of a device, such as all VFs of
> an SR/IOV device, will end up in the same IOMMU group.
> A similar situation occurs on Windows with Hyper-V.
>
> Signed-off-by: wlfightup <wlfightup@gmail.com>
> ---
> hw/pci-bridge/xio3130_downstream.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
> index 38a2361fa2..2017cf42a3 100644
> --- a/hw/pci-bridge/xio3130_downstream.c
> +++ b/hw/pci-bridge/xio3130_downstream.c
> @@ -40,6 +40,8 @@
> #define XIO3130_SSVID_SSID 0
> #define XIO3130_EXP_OFFSET 0x90
> #define XIO3130_AER_OFFSET 0x100
> +#define XIO3130_ACS_OFFSET \
> + (XIO3130_AER_OFFSET + PCI_ERR_SIZEOF)
>
> static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
> uint32_t val, int len)
> @@ -111,6 +113,10 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
> goto err;
> }
>
> + if (!s->disable_acs) {
> + pcie_acs_init(d, XIO3130_ACS_OFFSET);
> + }
> +
> return;
>
> err:
> @@ -137,6 +143,7 @@ static void xio3130_downstream_exitfn(PCIDevice *d)
> static Property xio3130_downstream_props[] = {
> DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
> QEMU_PCIE_SLTCAP_PCP_BITNR, true),
> + DEFINE_PROP_BOOL("x-disable-acs", PCIESlot, disable_acs, true),
> DEFINE_PROP_END_OF_LIST()
> };
>
> --
> 2.24.3 (Apple Git-128)
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] xio3130_downstream: Add ACS (Access Control Services) capability
2023-01-31 6:30 [PATCH] xio3130_downstream: Add ACS (Access Control Services) capability wlfightup
2023-02-18 7:36 ` Paul Schlacter
@ 2023-02-20 7:13 ` Philippe Mathieu-Daudé
2023-03-01 20:38 ` Michael S. Tsirkin
2 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-02-20 7:13 UTC (permalink / raw)
To: wlfightup, mst, marcel.apfelbaum
Cc: qemu-devel, Alex Williamson, Cédric Le Goater
Hi Paul,
On 31/1/23 07:30, wlfightup wrote:
> When vfio-pci devices are attached to the downstream, pcie acs
> capability may be needed, Consistent with physical machine.
>
> It has been tested in our environment, and pcie acs capability
> is required in some scenarios.
>
> Claim ACS support in the downstream port to allow
> passthrough of individual functions of a device to different
> guests (in a nested virt.setting) with VFIO.
> Without this patch, all functions of a device, such as all VFs of
> an SR/IOV device, will end up in the same IOMMU group.
> A similar situation occurs on Windows with Hyper-V.
>
> Signed-off-by: wlfightup <wlfightup@gmail.com>
Please use your real name, "Paul Schlacter <wlfightup@gmail.com>"
See https://www.qemu.org/docs/master/devel/submitting-a-patch.html
Cc'ing VFIO maintainers.
Regards,
Phil.
> ---
> hw/pci-bridge/xio3130_downstream.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
> index 38a2361fa2..2017cf42a3 100644
> --- a/hw/pci-bridge/xio3130_downstream.c
> +++ b/hw/pci-bridge/xio3130_downstream.c
> @@ -40,6 +40,8 @@
> #define XIO3130_SSVID_SSID 0
> #define XIO3130_EXP_OFFSET 0x90
> #define XIO3130_AER_OFFSET 0x100
> +#define XIO3130_ACS_OFFSET \
> + (XIO3130_AER_OFFSET + PCI_ERR_SIZEOF)
>
> static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
> uint32_t val, int len)
> @@ -111,6 +113,10 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
> goto err;
> }
>
> + if (!s->disable_acs) {
> + pcie_acs_init(d, XIO3130_ACS_OFFSET);
> + }
> +
> return;
>
> err:
> @@ -137,6 +143,7 @@ static void xio3130_downstream_exitfn(PCIDevice *d)
> static Property xio3130_downstream_props[] = {
> DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
> QEMU_PCIE_SLTCAP_PCP_BITNR, true),
> + DEFINE_PROP_BOOL("x-disable-acs", PCIESlot, disable_acs, true),
> DEFINE_PROP_END_OF_LIST()
> };
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] xio3130_downstream: Add ACS (Access Control Services) capability
2023-01-31 6:30 [PATCH] xio3130_downstream: Add ACS (Access Control Services) capability wlfightup
2023-02-18 7:36 ` Paul Schlacter
2023-02-20 7:13 ` Philippe Mathieu-Daudé
@ 2023-03-01 20:38 ` Michael S. Tsirkin
2 siblings, 0 replies; 6+ messages in thread
From: Michael S. Tsirkin @ 2023-03-01 20:38 UTC (permalink / raw)
To: wlfightup; +Cc: marcel.apfelbaum, qemu-devel
On Tue, Jan 31, 2023 at 02:30:13PM +0800, wlfightup wrote:
> When vfio-pci devices are attached to the downstream, pcie acs
> capability may be needed, Consistent with physical machine.
>
> It has been tested in our environment, and pcie acs capability
> is required in some scenarios.
>
> Claim ACS support in the downstream port to allow
> passthrough of individual functions of a device to different
> guests (in a nested virt.setting) with VFIO.
> Without this patch, all functions of a device, such as all VFs of
> an SR/IOV device, will end up in the same IOMMU group.
> A similar situation occurs on Windows with Hyper-V.
>
> Signed-off-by: wlfightup <wlfightup@gmail.com>
Hmm ok but this is an unstable property and nothing sets it.
If your product starts using it, it will break when qemu
changes the property in some way.
Do we want to maybe set this by default?
If not I am guessing at least a stable property is needed.
> ---
> hw/pci-bridge/xio3130_downstream.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
> index 38a2361fa2..2017cf42a3 100644
> --- a/hw/pci-bridge/xio3130_downstream.c
> +++ b/hw/pci-bridge/xio3130_downstream.c
> @@ -40,6 +40,8 @@
> #define XIO3130_SSVID_SSID 0
> #define XIO3130_EXP_OFFSET 0x90
> #define XIO3130_AER_OFFSET 0x100
> +#define XIO3130_ACS_OFFSET \
> + (XIO3130_AER_OFFSET + PCI_ERR_SIZEOF)
>
> static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
> uint32_t val, int len)
> @@ -111,6 +113,10 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
> goto err;
> }
>
> + if (!s->disable_acs) {
> + pcie_acs_init(d, XIO3130_ACS_OFFSET);
> + }
> +
> return;
>
> err:
> @@ -137,6 +143,7 @@ static void xio3130_downstream_exitfn(PCIDevice *d)
> static Property xio3130_downstream_props[] = {
> DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
> QEMU_PCIE_SLTCAP_PCP_BITNR, true),
> + DEFINE_PROP_BOOL("x-disable-acs", PCIESlot, disable_acs, true),
> DEFINE_PROP_END_OF_LIST()
> };
>
> --
> 2.24.3 (Apple Git-128)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] xio3130_downstream: Add ACS (Access Control Services) capability
2022-05-16 13:15 Wang,Liang(ACG CCN01)
@ 2022-05-18 5:10 ` Paul Schlacter
0 siblings, 0 replies; 6+ messages in thread
From: Paul Schlacter @ 2022-05-18 5:10 UTC (permalink / raw)
To: Wang,Liang(ACG CCN01); +Cc: mst, marcel.apfelbaum, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1354 bytes --]
pin
On Mon, May 16, 2022 at 9:54 PM Wang,Liang(ACG CCN01) <wangliang40@baidu.com>
wrote:
> When vfio-pci devices are attached to the downstream, pcie acs
>
> capability may be needed, Consistent with physical machine.
>
>
> It has been tested in our environment, and pcie acs capability
>
> is required in some scenarios.
>
>
> Signed-off-by: wangliang <wangliang40@baidu.com>
>
> ---
>
> hw/pci-bridge/xio3130_downstream.c | 4 ++++
>
> 1 file changed, 4 insertions(+)
>
>
> diff --git a/hw/pci-bridge/xio3130_downstream.c
> b/hw/pci-bridge/xio3130_downstream.c
>
> index 05e2b06c0c..6ab13b47e2 100644
>
> --- a/hw/pci-bridge/xio3130_downstream.c
>
> +++ b/hw/pci-bridge/xio3130_downstream.c
>
> @@ -40,6 +40,8 @@
>
> #define XIO3130_SSVID_SSID 0
>
> #define XIO3130_EXP_OFFSET 0x90
>
> #define XIO3130_AER_OFFSET 0x100
>
> +#define XIO3130_ACS_OFFSET \
>
> + (XIO3130_AER_OFFSET + PCI_ERR_SIZEOF)
>
>
> static void xio3130_downstream_write_config(PCIDevice *d, uint32_t
> address,
>
> uint32_t val, int len)
>
> @@ -111,6 +113,8 @@ static void xio3130_downstream_realize(PCIDevice *d,
> Error **errp)
>
> goto err;
>
> }
>
>
> +
>
> + pcie_acs_init(d, XIO3130_ACS_OFFSET);
>
> return;
>
>
> err:
>
> --
>
> 2.24.3 (Apple Git-128)
>
>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] xio3130_downstream: Add ACS (Access Control Services) capability
@ 2022-05-16 13:15 Wang,Liang(ACG CCN01)
2022-05-18 5:10 ` Paul Schlacter
0 siblings, 1 reply; 6+ messages in thread
From: Wang,Liang(ACG CCN01) @ 2022-05-16 13:15 UTC (permalink / raw)
To: mst, marcel.apfelbaum; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1226 bytes --]
When vfio-pci devices are attached to the downstream, pcie acs
capability may be needed, Consistent with physical machine.
It has been tested in our environment, and pcie acs capability
is required in some scenarios.
Signed-off-by: wangliang <wangliang40@baidu.com>
---
hw/pci-bridge/xio3130_downstream.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
index 05e2b06c0c..6ab13b47e2 100644
--- a/hw/pci-bridge/xio3130_downstream.c
+++ b/hw/pci-bridge/xio3130_downstream.c
@@ -40,6 +40,8 @@
#define XIO3130_SSVID_SSID 0
#define XIO3130_EXP_OFFSET 0x90
#define XIO3130_AER_OFFSET 0x100
+#define XIO3130_ACS_OFFSET \
+ (XIO3130_AER_OFFSET + PCI_ERR_SIZEOF)
static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
uint32_t val, int len)
@@ -111,6 +113,8 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
goto err;
}
+
+ pcie_acs_init(d, XIO3130_ACS_OFFSET);
return;
err:
--
2.24.3 (Apple Git-128)
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-03-01 20:39 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2023-01-31 6:30 [PATCH] xio3130_downstream: Add ACS (Access Control Services) capability wlfightup
2023-02-18 7:36 ` Paul Schlacter
2023-02-20 7:13 ` Philippe Mathieu-Daudé
2023-03-01 20:38 ` Michael S. Tsirkin
-- strict thread matches above, loose matches on Subject: below --
2022-05-16 13:15 Wang,Liang(ACG CCN01)
2022-05-18 5:10 ` Paul Schlacter
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