[PATCH 01/10] arm: psci: Add PSCI v1.1 macro

[PATCH 01/10] arm: psci: Add PSCI v1.1 macro

[Marek Vasut]

Add macro representing the PSCI v1.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Adam Ford <aford173@gmail.com>
Cc: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ricardo Salveti <ricardo@foundries.io>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Ye Li <ye.li@nxp.com>
---
 arch/arm/include/asm/psci.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 67e9234066b..8b3fb872255 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -22,6 +22,7 @@
 #include <linux/bitops.h>
 #endif
 
+#define ARM_PSCI_VER_1_1		(0x00010001)
 #define ARM_PSCI_VER_1_0		(0x00010000)
 #define ARM_PSCI_VER_0_2		(0x00000002)
 
-- 
2.35.1

[PATCH 02/10] arm: psci: Fix RESET2 hook

[Marek Vasut]

The RESET2 hook is a PSCI v1.1 functionality, rename the macro accordinly.
Add missing handler for the RESET2 hook, so it can be implemented by U-Boot.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Adam Ford <aford173@gmail.com>
Cc: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ricardo Salveti <ricardo@foundries.io>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Ye Li <ye.li@nxp.com>
---
 arch/arm/cpu/armv8/fwcall.c | 2 +-
 arch/arm/cpu/armv8/psci.S   | 2 ++
 arch/arm/include/asm/psci.h | 4 +++-
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
index 16914dc1eed..87de09979b1 100644
--- a/arch/arm/cpu/armv8/fwcall.c
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -103,7 +103,7 @@ void __noreturn psci_system_reset2(u32 reset_level, u32 cookie)
 {
 	struct pt_regs regs;
 
-	regs.regs[0] = ARM_PSCI_0_2_FN64_SYSTEM_RESET2;
+	regs.regs[0] = ARM_PSCI_1_1_FN64_SYSTEM_RESET2;
 	regs.regs[1] = PSCI_RESET2_TYPE_VENDOR | reset_level;
 	regs.regs[2] = cookie;
 	if (use_smc_for_psci)
diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S
index 7ffc8dbadbe..1133518f16e 100644
--- a/arch/arm/cpu/armv8/psci.S
+++ b/arch/arm/cpu/armv8/psci.S
@@ -82,6 +82,7 @@ PSCI_DEFAULT(psci_node_hw_state_64)
 PSCI_DEFAULT(psci_system_suspend_64)
 PSCI_DEFAULT(psci_stat_residency_64)
 PSCI_DEFAULT(psci_stat_count_64)
+PSCI_DEFAULT(psci_system_reset2_64)
 
 .align 3
 _psci_64_table:
@@ -95,6 +96,7 @@ PSCI_TABLE(ARM_PSCI_1_0_FN64_NODE_HW_STATE, psci_node_hw_state_64)
 PSCI_TABLE(ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND, psci_system_suspend_64)
 PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_RESIDENCY, psci_stat_residency_64)
 PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_COUNT, psci_stat_count_64)
+PSCI_TABLE(ARM_PSCI_1_1_FN64_SYSTEM_RESET2, psci_system_reset2_64)
 PSCI_TABLE(0, 0)
 
 .macro	psci_enter
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 8b3fb872255..7343b941ef0 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -69,7 +69,6 @@
 #define ARM_PSCI_0_2_FN64_AFFINITY_INFO		ARM_PSCI_0_2_FN64(4)
 #define ARM_PSCI_0_2_FN64_MIGRATE		ARM_PSCI_0_2_FN64(5)
 #define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU	ARM_PSCI_0_2_FN64(7)
-#define ARM_PSCI_0_2_FN64_SYSTEM_RESET2		ARM_PSCI_0_2_FN64(18)
 
 /* PSCI 1.0 interface */
 #define ARM_PSCI_1_0_FN_PSCI_FEATURES		ARM_PSCI_0_2_FN(10)
@@ -87,6 +86,9 @@
 #define ARM_PSCI_1_0_FN64_STAT_RESIDENCY	ARM_PSCI_0_2_FN64(16)
 #define ARM_PSCI_1_0_FN64_STAT_COUNT		ARM_PSCI_0_2_FN64(17)
 
+/* PSCI 1.1 interface */
+#define ARM_PSCI_1_1_FN64_SYSTEM_RESET2		ARM_PSCI_0_2_FN64(18)
+
 /* 1KB stack per core */
 #define ARM_PSCI_STACK_SHIFT	10
 #define ARM_PSCI_STACK_SIZE	(1 << ARM_PSCI_STACK_SHIFT)
-- 
2.35.1

[PATCH 03/10] arm: imx: Drop custom lowlevel_init

[Marek Vasut]

The custom lowlevel_init implementation is no longer necessary, since
it is responsible for routing and trapping SErrors in U-Boot in EL2,
which is implemented in common code since commit:
6c7691edd55 ("armv8: Always unmask SErrors")

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Adam Ford <aford173@gmail.com>
Cc: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ricardo Salveti <ricardo@foundries.io>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Ye Li <ye.li@nxp.com>
---
 arch/arm/mach-imx/Makefile   |  2 --
 arch/arm/mach-imx/lowlevel.S | 22 ----------------------
 2 files changed, 24 deletions(-)
 delete mode 100644 arch/arm/mach-imx/lowlevel.S

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 61b4f4f8cd3..4dfc60eedc4 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -235,8 +235,6 @@ endif
 
 targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
 
-obj-$(CONFIG_ARM64) += lowlevel.o
-
 obj-$(CONFIG_MX5) += mx5/
 obj-$(CONFIG_MX6) += mx6/
 obj-$(CONFIG_MX7) += mx7/
diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-imx/lowlevel.S
deleted file mode 100644
index 158fdb7d87b..00000000000
--- a/arch/arm/mach-imx/lowlevel.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2019 NXP
- */
-
-#include <linux/linkage.h>
-
-ENTRY(lowlevel_init)
-	mrs	x0, CurrentEL
-	cmp	x0, #8
-	b.eq	1f
-	ret
-1:
-	msr daifclr, #4
-
-	/* set HCR_EL2.AMO to catch SERROR */
-	mrs	x0, hcr_el2
-	orr	x0, x0, #0x20
-	msr	hcr_el2, x0
-	isb
-	ret
-ENDPROC(lowlevel_init)
-- 
2.35.1

[PATCH 04/10] arm: dts: imx8m: Require ATF BL31 blob only if not PSCI provider

[Marek Vasut]

In case U-Boot itself if the PSCI provider on i.MX8M, do not
require the ATF BL31 blob, as at that point the blob is useless
and would interfere with U-Boot operation.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Adam Ford <aford173@gmail.com>
Cc: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ricardo Salveti <ricardo@foundries.io>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Ye Li <ye.li@nxp.com>
---
 arch/arm/dts/imx8mm-u-boot.dtsi | 4 ++++
 arch/arm/dts/imx8mn-u-boot.dtsi | 4 ++++
 arch/arm/dts/imx8mp-u-boot.dtsi | 4 ++++
 arch/arm/dts/imx8mq-u-boot.dtsi | 4 ++++
 4 files changed, 16 insertions(+)

diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 60d49bc3d7b..25dc8e12dde 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -99,6 +99,7 @@
 					};
 				};
 
+#ifndef CONFIG_ARMV8_PSCI
 				atf {
 					arch = "arm64";
 					compression = "none";
@@ -112,6 +113,7 @@
 						type = "atf-bl31";
 					};
 				};
+#endif
 
 				binman_fip: fip {
 					arch = "arm64";
@@ -140,7 +142,9 @@
 					description = "NAME";
 					fdt = "fdt-SEQ";
 					firmware = "uboot";
+#ifndef CONFIG_ARMV8_PSCI
 					loadables = "atf";
+#endif
 				};
 			};
 		};
diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi
index 95f45ad2522..b019b2341d6 100644
--- a/arch/arm/dts/imx8mn-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-u-boot.dtsi
@@ -161,6 +161,7 @@
 					};
 				};
 
+#ifndef CONFIG_ARMV8_PSCI
 				atf {
 					arch = "arm64";
 					compression = "none";
@@ -174,6 +175,7 @@
 						type = "atf-bl31";
 					};
 				};
+#endif
 
 				binman_fip: fip {
 					arch = "arm64";
@@ -202,7 +204,9 @@
 					description = "NAME";
 					fdt = "fdt-SEQ";
 					firmware = "uboot";
+#ifndef CONFIG_ARMV8_PSCI
 					loadables = "atf";
+#endif
 				};
 			};
 		};
diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
index f9883aa1336..9a3de8f6a07 100644
--- a/arch/arm/dts/imx8mp-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-u-boot.dtsi
@@ -120,6 +120,7 @@
 					};
 				};
 
+#ifndef CONFIG_ARMV8_PSCI
 				atf {
 					description = "ARM Trusted Firmware";
 					type = "firmware";
@@ -133,6 +134,7 @@
 						type = "atf-bl31";
 					};
 				};
+#endif
 
 				@fdt-SEQ {
 					description = "NAME";
@@ -152,7 +154,9 @@
 					description = "NAME";
 					fdt = "fdt-SEQ";
 					firmware = "uboot";
+#ifndef CONFIG_ARMV8_PSCI
 					loadables = "atf";
+#endif
 				};
 			};
 		};
diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi
index 8d385e8da4f..2bc9f413da0 100644
--- a/arch/arm/dts/imx8mq-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-u-boot.dtsi
@@ -114,6 +114,7 @@
 					};
 				};
 
+#ifndef CONFIG_ARMV8_PSCI
 				atf {
 					arch = "arm64";
 					compression = "none";
@@ -127,6 +128,7 @@
 						type = "blob-ext";
 					};
 				};
+#endif
 
 				fdt {
 					compression = "none";
@@ -147,7 +149,9 @@
 					description = "NAME";
 					fdt = "fdt";
 					firmware = "uboot";
+#ifndef CONFIG_ARMV8_PSCI
 					loadables = "atf";
+#endif
 				};
 			};
 		};
-- 
2.35.1

[PATCH 05/10] arm: imx: imx8m: Only use ROM pointers if not PSCI provider

[Marek Vasut]

The ROM pointers are in fact populated by the ATF BL31 blob, in case
U-Boot itself if the PSCI provider, there is no ATF BL31 blob, hence
ignore the ROM pointers.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Adam Ford <aford173@gmail.com>
Cc: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ricardo Salveti <ricardo@foundries.io>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Ye Li <ye.li@nxp.com>
---
 arch/arm/mach-imx/imx8m/soc.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 5e92f8143cf..96c6e69aae4 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -238,7 +238,7 @@ int dram_init(void)
 		return ret;
 
 	/* rom_pointer[1] contains the size of TEE occupies */
-	if (rom_pointer[1])
+	if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1])
 		gd->ram_size = sdram_size - rom_pointer[1];
 	else
 		gd->ram_size = sdram_size;
@@ -267,7 +267,7 @@ int dram_init_banksize(void)
 	}
 
 	gd->bd->bi_dram[bank].start = PHYS_SDRAM;
-	if (rom_pointer[1]) {
+	if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) {
 		phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
 		phys_size_t optee_size = (size_t)rom_pointer[1];
 
@@ -312,7 +312,7 @@ phys_size_t get_effective_memsize(void)
 			sdram_b1_size = sdram_size;
 		}
 
-		if (rom_pointer[1]) {
+		if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[1]) {
 			/* We will relocate u-boot to Top of dram1. Tee position has two cases:
 			 * 1. At the top of dram1,  Then return the size removed optee size.
 			 * 2. In the middle of dram1, return the size of dram1.
@@ -344,7 +344,8 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size)
 	 * rom_pointer[1] stores the size TEE uses.
 	 * We need to reserve the memory region for TEE.
 	 */
-	if (rom_pointer[0] && rom_pointer[1] && top_addr > rom_pointer[0])
+	if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[0] &&
+	    rom_pointer[1] && top_addr > rom_pointer[0])
 		top_addr = rom_pointer[0];
 
 	return top_addr;
-- 
2.35.1

[PATCH 06/10] arm: imx: imx8m: Enable GICv3 support if PSCI provider

[Marek Vasut]

In case U-Boot is a PSCI provider, enable GICv3 support as this
is necessary to bring up secondary cores.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Adam Ford <aford173@gmail.com>
Cc: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ricardo Salveti <ricardo@foundries.io>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Ye Li <ye.li@nxp.com>
---
 arch/arm/include/asm/arch-imx8m/imx-regs.h | 3 +++
 arch/arm/mach-imx/imx8m/Kconfig            | 1 +
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 20f4699a12b..cfd5479cd73 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -81,6 +81,9 @@
 #define MXS_GPMI_BASE		(APBH_DMA_ARB_BASE_ADDR + 0x02000)
 #define MXS_BCH_BASE		(APBH_DMA_ARB_BASE_ADDR + 0x04000)
 
+#define GICD_BASE		0x38800000
+#define GICR_BASE		0x38880000
+
 #define DDRC_DDR_SS_GPR0	0x3d000000
 #define DDRC_IPS_BASE_ADDR(X)	(0x3d400000 + ((X) * 0x2000000))
 #define DDR_CSD1_BASE_ADDR	0x40000000
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 3313ea38832..9e957e2de57 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -2,6 +2,7 @@ if ARCH_IMX8M
 
 config IMX8M
 	bool
+	select GICV3 if ARMV8_PSCI
 	select HAS_CAAM
 	select ROM_UNIFIED_SECTIONS
 	select ARMV8_CRYPTO
-- 
2.35.1

[PATCH 07/10] arm: imx: imx8m: Map RAM as NS if PSCI provider

[Marek Vasut]

In case U-Boot is a PSCI provider, map RAM explicitly as NS,
otherwise secondary cores crash with SError when attempting
to access RAM mapped as secure in EL2.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Adam Ford <aford173@gmail.com>
Cc: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ricardo Salveti <ricardo@foundries.io>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Ye Li <ye.li@nxp.com>
---
 arch/arm/mach-imx/imx8m/soc.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 96c6e69aae4..706ba8509da 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -100,6 +100,12 @@ void set_wdog_reset(struct wdog_regs *wdog)
 	setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
 }
 
+#ifdef CONFIG_ARMV8_PSCI
+#define PTE_MAP_NS	PTE_BLOCK_NS
+#else
+#define PTE_MAP_NS	0
+#endif
+
 static struct mm_region imx8m_mem_map[] = {
 	{
 		/* ROM */
@@ -122,7 +128,7 @@ static struct mm_region imx8m_mem_map[] = {
 		.phys = 0x180000UL,
 		.size = 0x8000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_OUTER_SHARE
+			 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
 	}, {
 		/* TCM */
 		.virt = 0x7C0000UL,
@@ -130,14 +136,14 @@ static struct mm_region imx8m_mem_map[] = {
 		.size = 0x80000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 			 PTE_BLOCK_NON_SHARE |
-			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_MAP_NS
 	}, {
 		/* OCRAM */
 		.virt = 0x900000UL,
 		.phys = 0x900000UL,
 		.size = 0x200000UL,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_OUTER_SHARE
+			 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
 	}, {
 		/* AIPS */
 		.virt = 0xB00000UL,
@@ -152,7 +158,7 @@ static struct mm_region imx8m_mem_map[] = {
 		.phys = 0x40000000UL,
 		.size = PHYS_SDRAM_SIZE,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_OUTER_SHARE
+			 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
 #ifdef PHYS_SDRAM_2_SIZE
 	}, {
 		/* DRAM2 */
@@ -160,7 +166,7 @@ static struct mm_region imx8m_mem_map[] = {
 		.phys = 0x100000000UL,
 		.size = PHYS_SDRAM_2_SIZE,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-			 PTE_BLOCK_OUTER_SHARE
+			 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
 #endif
 	}, {
 		/* empty entrie to split table entry 5 if needed when TEEs are used */
-- 
2.35.1

[PATCH 08/10] arm: imx: imx8m: Define trampoline location if PSCI provider

[Marek Vasut]

The common code used to bring up secondary cores requires a final
jump location to be stored in some sort of memory location, define
this memory location to be the start of OCRAM, since it is available.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Adam Ford <aford173@gmail.com>
Cc: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ricardo Salveti <ricardo@foundries.io>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Ye Li <ye.li@nxp.com>
---
 arch/arm/include/asm/arch-imx8m/imx-regs.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index cfd5479cd73..3034d280cc3 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -91,6 +91,10 @@
 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
 #define FEC_QUIRK_ENET_MAC
 
+#ifdef CONFIG_ARMV8_PSCI	/* Final jump location */
+#define CPU_RELEASE_ADDR               0x900000
+#endif
+
 #define CAAM_ARB_BASE_ADDR              (0x00100000)
 #define CAAM_ARB_END_ADDR               (0x00107FFF)
 #define CAAM_IPS_BASE_ADDR              (0x30900000)
-- 
2.35.1

[PATCH 09/10] arm: imx: imx8m: Program CSU and TZASC if PSCI provider

[Marek Vasut]

In case U-Boot is the PSCI provider, it is necessary to correctly
program CSU and TZASC registers. Those are poorly documented, so
push in the correct values.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Adam Ford <aford173@gmail.com>
Cc: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ricardo Salveti <ricardo@foundries.io>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Ye Li <ye.li@nxp.com>
---
 arch/arm/include/asm/arch-imx8m/imx-regs.h |  1 +
 arch/arm/mach-imx/imx8m/soc.c              | 25 ++++++++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 3034d280cc3..1559bf6d218 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -31,6 +31,7 @@
 #define CCM_BASE_ADDR		0x30380000
 #define SRC_BASE_ADDR		0x30390000
 #define GPC_BASE_ADDR		0x303A0000
+#define CSU_BASE_ADDR		0x303E0000
 
 #define SYSCNT_RD_BASE_ADDR	0x306A0000
 #define SYSCNT_CMP_BASE_ADDR	0x306B0000
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 706ba8509da..99c41c654a1 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -561,6 +561,29 @@ static void imx8m_setup_snvs(void)
 	writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
 }
 
+static void imx8m_setup_csu_tzasc(void)
+{
+	const uintptr_t tzasc_base[4] = {
+		0x301f0000, 0x301f0000, 0x301f0000, 0x301f0000
+	};
+	int i, j;
+
+	if (!IS_ENABLED(CONFIG_ARMV8_PSCI))
+		return;
+
+	/* CSU */
+	for (i = 0; i < 64; i++)
+		writel(0x00ff00ff, (void *)CSU_BASE_ADDR + (4 * i));
+
+	/* TZASC */
+	for (j = 0; j < 4; j++) {
+		writel(0x77777777, (void *)(tzasc_base[j]));
+		writel(0x77777777, (void *)(tzasc_base[j]) + 0x4);
+		for (i = 0; i <= 0x10; i += 4)
+			writel(0, (void *)(tzasc_base[j]) + 0x40 + i);
+	}
+}
+
 int arch_cpu_init(void)
 {
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@@ -613,6 +636,8 @@ int arch_cpu_init(void)
 
 	imx8m_setup_snvs();
 
+	imx8m_setup_csu_tzasc();
+
 	return 0;
 }
 
-- 
2.35.1

[PATCH 10/10] arm: imx: imx8m: Add basic PSCI provider implementation

[Marek Vasut]

Implement basic PSCI provider to let OS turn CPU cores off and on,
power off and restart the system and determine PSCI version. This
is sufficient to remove the need for the ATF BL31 blob altogether.

To make use of this functionality, active the following Kconfig options:
  # CONFIG_PSCI_RESET is not set
  CONFIG_ARMV8_MULTIENTRY=y
  CONFIG_ARMV8_SET_SMPEN=y
  CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
  CONFIG_ARMV8_EA_EL3_FIRST=y
  CONFIG_ARMV8_PSCI=y
  CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
  CONFIG_ARMV8_SECURE_BASE=0x970000
  CONFIG_ARM_SMCCC=y
  CONFIG_SYS_HAS_ARMV8_SECURE_BASE=y

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Adam Ford <aford173@gmail.com>
Cc: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Ricardo Salveti <ricardo@foundries.io>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Ye Li <ye.li@nxp.com>
---
 arch/arm/mach-imx/imx8m/Kconfig  |   8 +
 arch/arm/mach-imx/imx8m/Makefile |   1 +
 arch/arm/mach-imx/imx8m/psci.c   | 288 +++++++++++++++++++++++++++++++
 3 files changed, 297 insertions(+)
 create mode 100644 arch/arm/mach-imx/imx8m/psci.c

diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 9e957e2de57..080c84f8163 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -27,6 +27,14 @@ config IMX8MP
 config SYS_SOC
 	default "imx8m"
 
+config SYS_HAS_ARMV8_SECURE_BASE
+	bool "Enable secure address for PSCI image"
+	depends on ARMV8_PSCI
+	help
+	  PSCI image can be re-located to secure RAM.
+	  If enabled, please also define the value for ARMV8_SECURE_BASE,
+	  for i.MX8M, it could be some address in OCRAM.
+
 choice
 	prompt "NXP i.MX8M board select"
 	optional
diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile
index d9dee894aae..abd5ddc1774 100644
--- a/arch/arm/mach-imx/imx8m/Makefile
+++ b/arch/arm/mach-imx/imx8m/Makefile
@@ -4,5 +4,6 @@
 
 obj-y += lowlevel_init.o
 obj-y += clock_slice.o soc.o
+obj-$(CONFIG_ARMV8_PSCI) += psci.o
 obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
 obj-$(CONFIG_IMX8MM)$(CONFIG_IMX8MN)$(CONFIG_IMX8MP) += clock_imx8mm.o
diff --git a/arch/arm/mach-imx/imx8m/psci.c b/arch/arm/mach-imx/imx8m/psci.c
new file mode 100644
index 00000000000..62f0b768cfa
--- /dev/null
+++ b/arch/arm/mach-imx/imx8m/psci.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * This file implements basic PSCI support for i.MX8M
+ *
+ * Copyright (C) 2022 Marek Vasut <marex@denx.de>
+ */
+#include <asm/arch/imx-regs.h>
+#include <asm/cache.h>
+#include <asm/gic.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/secure.h>
+#include <common.h>
+#include <cpu_func.h>
+#include <debug_uart.h>
+#include <fsl_wdog.h>
+#include <linux/bitops.h>
+
+#define SNVS_LPCR			0x38
+#define SNVS_LPCR_TOP			BIT(6)
+#define SNVS_LPCR_DP_EN			BIT(5)
+#define SNVS_LPCR_SRTC_ENV		BIT(0)
+
+#define MPIDR_AFF0			GENMASK(7, 0)
+
+#define GPC_LPCR_A53_AD			0x4
+#define EN_Cn_WFI_PDN(cpu)		BIT(((((cpu) & 1) * 2) + (((cpu) & 2) * 8)))
+#define GPC_PGC_nCTRL(cpu)		(0x800 + ((cpu) * 0x40))
+#define PGC_PCR				BIT(0)
+#define GPC_CPU_PGC_SW_PUP_REQ		(IS_ENABLED(CONFIG_IMX8MP) ? 0xd0 : 0xf0)
+#define COREn_A53_SW_PUP_REQ(cpu)	BIT(cpu)
+
+#define SRC_A53RCR1			0x8
+#define A53_COREn_ENABLE(n)		BIT(n)
+#define SRC_GPR(n)			(0x74 + ((n) * 4))
+
+/*
+ * Helper code
+ */
+static u8 psci_state[CONFIG_ARMV8_PSCI_NR_CPUS] __secure_data = {
+	PSCI_AFFINITY_LEVEL_ON,
+	PSCI_AFFINITY_LEVEL_OFF,
+	PSCI_AFFINITY_LEVEL_OFF,
+	PSCI_AFFINITY_LEVEL_OFF
+};
+
+int psci_update_dt(void *fdt)
+{
+	return 0;
+}
+
+__secure static void psci_set_state(int cpu, u8 state)
+{
+	psci_state[cpu] = state;
+	dsb();
+	isb();
+}
+
+__secure static s32 psci_cpu_on_validate_mpidr(u64 mpidr, u32 *cpu)
+{
+	*cpu = mpidr & MPIDR_AFF0;
+
+	if (mpidr & ~MPIDR_AFF0)
+		return ARM_PSCI_RET_INVAL;
+
+	if (*cpu >= CONFIG_ARMV8_PSCI_NR_CPUS)
+		return ARM_PSCI_RET_INVAL;
+
+	if (psci_state[*cpu] == PSCI_AFFINITY_LEVEL_ON)
+		return ARM_PSCI_RET_ALREADY_ON;
+
+	if (psci_state[*cpu] == PSCI_AFFINITY_LEVEL_ON_PENDING)
+		return ARM_PSCI_RET_ON_PENDING;
+
+	return ARM_PSCI_RET_SUCCESS;
+}
+
+__secure static void psci_cpu_on_write_entry_point(const u32 cpu, u64 entry_point)
+{
+	const u64 ep = CONFIG_SPL_TEXT_BASE;
+
+	/* Trampoline target */
+	writeq(entry_point, CPU_RELEASE_ADDR);
+	/* RVBAR address HI */
+	writel((u32)(ep >> 24) & 0xffff,
+	       (void *)SRC_BASE_ADDR + SRC_GPR(cpu * 2));
+	/* RVBAR address LO */
+	writel((u32)(ep >> 2) & 0x3fffff,
+	       (void *)SRC_BASE_ADDR + SRC_GPR(cpu * 2 + 1));
+}
+
+__secure static void psci_cpu_on_power_on(const u32 cpu)
+{
+	int i;
+
+	clrbits_le32((void *)GPC_BASE_ADDR + GPC_LPCR_A53_AD, EN_Cn_WFI_PDN(cpu));
+	clrbits_le32((void *)SRC_BASE_ADDR + SRC_A53RCR1, A53_COREn_ENABLE(cpu));
+	setbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR);
+	setbits_le32((void *)GPC_BASE_ADDR + GPC_CPU_PGC_SW_PUP_REQ, COREn_A53_SW_PUP_REQ(cpu));
+
+	/* If we fail here, the core gets power cycled, hang is OK */
+	while (readl(GPC_BASE_ADDR + GPC_CPU_PGC_SW_PUP_REQ) & COREn_A53_SW_PUP_REQ(cpu))
+			;
+
+	clrbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR);
+	setbits_le32((void *)SRC_BASE_ADDR + SRC_A53RCR1, A53_COREn_ENABLE(cpu));
+
+	/* Give the core a bit of time to boot and start executing code */
+	for (i = 0; i < 100000; i++)
+		asm volatile("nop");
+}
+
+__secure static void psci_cpu_on_power_off(const u32 cpu)
+{
+	setbits_le32((void *)GPC_BASE_ADDR + GPC_LPCR_A53_AD, EN_Cn_WFI_PDN(cpu));
+	setbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR);
+}
+
+/*
+ * Common PSCI code
+ */
+/* Return supported PSCI version */
+__secure u32 psci_version(void)
+{
+	return ARM_PSCI_VER_1_0;
+}
+
+/*
+ * 64bit PSCI code
+ */
+__secure s32 psci_cpu_on_64(u32 __always_unused function_id, u64 mpidr,
+			    u64 entry_point_address, u64 context_id)
+{
+	u32 cpu = 0;
+	int ret;
+
+	ret = psci_cpu_on_validate_mpidr(mpidr, &cpu);
+	if (ret != ARM_PSCI_RET_SUCCESS)
+		return ret;
+
+	psci_cpu_on_write_entry_point(cpu, entry_point_address);
+
+	psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
+
+	psci_cpu_on_power_on(cpu);
+
+	smp_kick_all_cpus();
+
+	return ARM_PSCI_RET_SUCCESS;
+}
+
+__secure s32 psci_affinity_info_64(u32 __always_unused function_id,
+				   u64 target_affinity, u32 lowest_affinity_level)
+{
+	u32 cpu = target_affinity & MPIDR_AFF0;
+
+	if (lowest_affinity_level > 0)
+		return ARM_PSCI_RET_INVAL;
+
+	if (target_affinity & ~MPIDR_AFF0)
+		return ARM_PSCI_RET_INVAL;
+
+	if (cpu >= CONFIG_ARMV8_PSCI_NR_CPUS)
+		return ARM_PSCI_RET_INVAL;
+
+	return psci_state[cpu];
+}
+
+__secure s32 psci_system_reset2_64(u32 __always_unused function_id,
+				   u32 reset_type, u64 cookie)
+{
+	psci_system_reset();
+	return 0;	/* Not reached */
+}
+
+/*
+ * 32bit PSCI code
+ */
+__secure s32 psci_affinity_info(u32 __always_unused function_id,
+				u32 target_affinity, u32 lowest_affinity_level)
+{
+	return psci_affinity_info_64(function_id, target_affinity, lowest_affinity_level);
+}
+
+__secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr,
+			 u32 entry_point_address, u32 context_id)
+{
+	return psci_cpu_on_64(function_id, mpidr, entry_point_address, context_id);
+}
+
+__secure s32 psci_cpu_off(void)
+{
+	u32 cpu = psci_get_cpu_id();
+
+	psci_cpu_on_power_off(cpu);
+	psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
+
+	while (1)
+		wfi();
+}
+
+__secure u32 psci_migrate_info_type(void)
+{
+	/* Trusted OS is either not present or does not require migration */
+	return 2;
+}
+
+__secure void psci_system_reset(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+	bool ext_reset = true;
+
+	u16 wcr = WCR_WDE;
+
+	if (ext_reset)
+		wcr |= WCR_SRS; /* do not assert internal reset */
+	else
+		wcr |= WCR_WDA; /* do not assert external reset */
+
+	/* Write 3 times to ensure it works, due to IMX6Q errata ERR004346 */
+	writew(wcr, &wdog->wcr);
+	writew(wcr, &wdog->wcr);
+	writew(wcr, &wdog->wcr);
+
+	while (1)
+		wfi();
+}
+
+__secure void psci_system_off(void)
+{
+	writel(SNVS_LPCR_TOP | SNVS_LPCR_DP_EN | SNVS_LPCR_SRTC_ENV,
+	       SNVS_BASE_ADDR + SNVS_LPCR);
+
+	while (1)
+		wfi();
+}
+
+/*
+ * PSCI jump table
+ */
+__secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid)
+{
+	switch (psci_fid) {
+	case ARM_PSCI_0_2_FN_PSCI_VERSION:
+	case ARM_PSCI_0_2_FN_CPU_OFF:
+	case ARM_PSCI_0_2_FN_CPU_ON:
+	case ARM_PSCI_0_2_FN_AFFINITY_INFO:
+	case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
+	case ARM_PSCI_0_2_FN_SYSTEM_OFF:
+	case ARM_PSCI_0_2_FN_SYSTEM_RESET:
+	case ARM_PSCI_0_2_FN64_CPU_ON:
+	case ARM_PSCI_0_2_FN64_AFFINITY_INFO:
+
+	/* PSCI 1.0 interface */
+	case ARM_PSCI_1_0_FN_PSCI_FEATURES:
+
+	/* PSCI 1.1 interface */
+	case ARM_PSCI_1_1_FN64_SYSTEM_RESET2:
+		return 0x0;
+
+	/*
+	 * Not implemented:
+	 * ARM_PSCI_0_2_FN_CPU_SUSPEND
+	 * ARM_PSCI_1_0_FN_CPU_FREEZE
+	 * ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND
+	 * ARM_PSCI_1_0_FN_NODE_HW_STATE
+	 * ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
+	 * ARM_PSCI_1_0_FN_SET_SUSPEND_MODE
+	 * ARM_PSCI_1_0_FN_STAT_RESIDENCY
+	 * ARM_PSCI_1_0_FN_STAT_COUNT
+	 * ARM_PSCI_0_2_FN64_CPU_SUSPEND
+	 * ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND
+	 * ARM_PSCI_1_0_FN64_NODE_HW_STATE
+	 * ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND
+	 * ARM_PSCI_1_0_FN64_STAT_RESIDENCY
+	 * ARM_PSCI_1_0_FN64_STAT_COUNT
+	 */
+
+	/* Not required, ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE returns 2 */
+	case ARM_PSCI_0_2_FN_MIGRATE:
+	case ARM_PSCI_0_2_FN64_MIGRATE:
+	/* Not required */
+	case ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU:
+	case ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU:
+	default:
+		return ARM_PSCI_RET_NI;
+	}
+}
-- 
2.35.1

Re: [PATCH 10/10] arm: imx: imx8m: Add basic PSCI provider implementation

[Adam Ford]

On Wed, Dec 21, 2022 at 6:47 PM Marek Vasut <marex@denx.de> wrote:
>
> Implement basic PSCI provider to let OS turn CPU cores off and on,
> power off and restart the system and determine PSCI version. This
> is sufficient to remove the need for the ATF BL31 blob altogether.
>
> To make use of this functionality, active the following Kconfig options:
>   # CONFIG_PSCI_RESET is not set
>   CONFIG_ARMV8_MULTIENTRY=y
>   CONFIG_ARMV8_SET_SMPEN=y
>   CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
>   CONFIG_ARMV8_EA_EL3_FIRST=y
>   CONFIG_ARMV8_PSCI=y
>   CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
>   CONFIG_ARMV8_SECURE_BASE=0x970000

 I am guessing 0x970000 was for the 8MP based on the previous location
of ATF.  Is that true?   If that's the case, can I assume that this
address would be  0x910000, 0x920000 and 0x960000 for the imx8mq,
imx8mm and imx8mn respectively?

>   CONFIG_ARM_SMCCC=y
>   CONFIG_SYS_HAS_ARMV8_SECURE_BASE=y
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> Cc: "Ariel D'Alessandro" <ariel.dalessandro@collabora.com>
> Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
> Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
> Cc: Adam Ford <aford173@gmail.com>
> Cc: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Cc: Michael Trimarchi <michael@amarulasolutions.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Ricardo Salveti <ricardo@foundries.io>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Tim Harvey <tharvey@gateworks.com>
> Cc: Ye Li <ye.li@nxp.com>
> ---
>  arch/arm/mach-imx/imx8m/Kconfig  |   8 +
>  arch/arm/mach-imx/imx8m/Makefile |   1 +
>  arch/arm/mach-imx/imx8m/psci.c   | 288 +++++++++++++++++++++++++++++++
>  3 files changed, 297 insertions(+)
>  create mode 100644 arch/arm/mach-imx/imx8m/psci.c
>
> diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
> index 9e957e2de57..080c84f8163 100644
> --- a/arch/arm/mach-imx/imx8m/Kconfig
> +++ b/arch/arm/mach-imx/imx8m/Kconfig
> @@ -27,6 +27,14 @@ config IMX8MP
>  config SYS_SOC
>         default "imx8m"
>
> +config SYS_HAS_ARMV8_SECURE_BASE
> +       bool "Enable secure address for PSCI image"
> +       depends on ARMV8_PSCI
> +       help
> +         PSCI image can be re-located to secure RAM.
> +         If enabled, please also define the value for ARMV8_SECURE_BASE,
> +         for i.MX8M, it could be some address in OCRAM.
> +
>  choice
>         prompt "NXP i.MX8M board select"
>         optional
> diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile
> index d9dee894aae..abd5ddc1774 100644
> --- a/arch/arm/mach-imx/imx8m/Makefile
> +++ b/arch/arm/mach-imx/imx8m/Makefile
> @@ -4,5 +4,6 @@
>
>  obj-y += lowlevel_init.o
>  obj-y += clock_slice.o soc.o
> +obj-$(CONFIG_ARMV8_PSCI) += psci.o
>  obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
>  obj-$(CONFIG_IMX8MM)$(CONFIG_IMX8MN)$(CONFIG_IMX8MP) += clock_imx8mm.o
> diff --git a/arch/arm/mach-imx/imx8m/psci.c b/arch/arm/mach-imx/imx8m/psci.c
> new file mode 100644
> index 00000000000..62f0b768cfa
> --- /dev/null
> +++ b/arch/arm/mach-imx/imx8m/psci.c
> @@ -0,0 +1,288 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * This file implements basic PSCI support for i.MX8M
> + *
> + * Copyright (C) 2022 Marek Vasut <marex@denx.de>
> + */
> +#include <asm/arch/imx-regs.h>
> +#include <asm/cache.h>
> +#include <asm/gic.h>
> +#include <asm/io.h>
> +#include <asm/psci.h>
> +#include <asm/secure.h>
> +#include <common.h>
> +#include <cpu_func.h>
> +#include <debug_uart.h>
> +#include <fsl_wdog.h>
> +#include <linux/bitops.h>
> +
> +#define SNVS_LPCR                      0x38
> +#define SNVS_LPCR_TOP                  BIT(6)
> +#define SNVS_LPCR_DP_EN                        BIT(5)
> +#define SNVS_LPCR_SRTC_ENV             BIT(0)
> +
> +#define MPIDR_AFF0                     GENMASK(7, 0)
> +
> +#define GPC_LPCR_A53_AD                        0x4
> +#define EN_Cn_WFI_PDN(cpu)             BIT(((((cpu) & 1) * 2) + (((cpu) & 2) * 8)))
> +#define GPC_PGC_nCTRL(cpu)             (0x800 + ((cpu) * 0x40))
> +#define PGC_PCR                                BIT(0)
> +#define GPC_CPU_PGC_SW_PUP_REQ         (IS_ENABLED(CONFIG_IMX8MP) ? 0xd0 : 0xf0)
> +#define COREn_A53_SW_PUP_REQ(cpu)      BIT(cpu)
> +
> +#define SRC_A53RCR1                    0x8
> +#define A53_COREn_ENABLE(n)            BIT(n)
> +#define SRC_GPR(n)                     (0x74 + ((n) * 4))
> +
> +/*
> + * Helper code
> + */
> +static u8 psci_state[CONFIG_ARMV8_PSCI_NR_CPUS] __secure_data = {
> +       PSCI_AFFINITY_LEVEL_ON,
> +       PSCI_AFFINITY_LEVEL_OFF,
> +       PSCI_AFFINITY_LEVEL_OFF,
> +       PSCI_AFFINITY_LEVEL_OFF
> +};
> +
> +int psci_update_dt(void *fdt)
> +{
> +       return 0;
> +}
> +
> +__secure static void psci_set_state(int cpu, u8 state)
> +{
> +       psci_state[cpu] = state;
> +       dsb();
> +       isb();
> +}
> +
> +__secure static s32 psci_cpu_on_validate_mpidr(u64 mpidr, u32 *cpu)
> +{
> +       *cpu = mpidr & MPIDR_AFF0;
> +
> +       if (mpidr & ~MPIDR_AFF0)
> +               return ARM_PSCI_RET_INVAL;
> +
> +       if (*cpu >= CONFIG_ARMV8_PSCI_NR_CPUS)
> +               return ARM_PSCI_RET_INVAL;
> +
> +       if (psci_state[*cpu] == PSCI_AFFINITY_LEVEL_ON)
> +               return ARM_PSCI_RET_ALREADY_ON;
> +
> +       if (psci_state[*cpu] == PSCI_AFFINITY_LEVEL_ON_PENDING)
> +               return ARM_PSCI_RET_ON_PENDING;
> +
> +       return ARM_PSCI_RET_SUCCESS;
> +}
> +
> +__secure static void psci_cpu_on_write_entry_point(const u32 cpu, u64 entry_point)
> +{
> +       const u64 ep = CONFIG_SPL_TEXT_BASE;
> +
> +       /* Trampoline target */
> +       writeq(entry_point, CPU_RELEASE_ADDR);
> +       /* RVBAR address HI */
> +       writel((u32)(ep >> 24) & 0xffff,
> +              (void *)SRC_BASE_ADDR + SRC_GPR(cpu * 2));
> +       /* RVBAR address LO */
> +       writel((u32)(ep >> 2) & 0x3fffff,
> +              (void *)SRC_BASE_ADDR + SRC_GPR(cpu * 2 + 1));
> +}
> +
> +__secure static void psci_cpu_on_power_on(const u32 cpu)
> +{
> +       int i;
> +
> +       clrbits_le32((void *)GPC_BASE_ADDR + GPC_LPCR_A53_AD, EN_Cn_WFI_PDN(cpu));
> +       clrbits_le32((void *)SRC_BASE_ADDR + SRC_A53RCR1, A53_COREn_ENABLE(cpu));
> +       setbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR);
> +       setbits_le32((void *)GPC_BASE_ADDR + GPC_CPU_PGC_SW_PUP_REQ, COREn_A53_SW_PUP_REQ(cpu));
> +
> +       /* If we fail here, the core gets power cycled, hang is OK */
> +       while (readl(GPC_BASE_ADDR + GPC_CPU_PGC_SW_PUP_REQ) & COREn_A53_SW_PUP_REQ(cpu))
> +                       ;
> +
> +       clrbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR);
> +       setbits_le32((void *)SRC_BASE_ADDR + SRC_A53RCR1, A53_COREn_ENABLE(cpu));
> +
> +       /* Give the core a bit of time to boot and start executing code */
> +       for (i = 0; i < 100000; i++)
> +               asm volatile("nop");
> +}
> +
> +__secure static void psci_cpu_on_power_off(const u32 cpu)
> +{
> +       setbits_le32((void *)GPC_BASE_ADDR + GPC_LPCR_A53_AD, EN_Cn_WFI_PDN(cpu));
> +       setbits_le32((void *)GPC_BASE_ADDR + GPC_PGC_nCTRL(cpu), PGC_PCR);
> +}
> +
> +/*
> + * Common PSCI code
> + */
> +/* Return supported PSCI version */
> +__secure u32 psci_version(void)
> +{
> +       return ARM_PSCI_VER_1_0;
> +}
> +
> +/*
> + * 64bit PSCI code
> + */
> +__secure s32 psci_cpu_on_64(u32 __always_unused function_id, u64 mpidr,
> +                           u64 entry_point_address, u64 context_id)
> +{
> +       u32 cpu = 0;
> +       int ret;
> +
> +       ret = psci_cpu_on_validate_mpidr(mpidr, &cpu);
> +       if (ret != ARM_PSCI_RET_SUCCESS)
> +               return ret;
> +
> +       psci_cpu_on_write_entry_point(cpu, entry_point_address);
> +
> +       psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
> +
> +       psci_cpu_on_power_on(cpu);
> +
> +       smp_kick_all_cpus();
> +
> +       return ARM_PSCI_RET_SUCCESS;
> +}
> +
> +__secure s32 psci_affinity_info_64(u32 __always_unused function_id,
> +                                  u64 target_affinity, u32 lowest_affinity_level)
> +{
> +       u32 cpu = target_affinity & MPIDR_AFF0;
> +
> +       if (lowest_affinity_level > 0)
> +               return ARM_PSCI_RET_INVAL;
> +
> +       if (target_affinity & ~MPIDR_AFF0)
> +               return ARM_PSCI_RET_INVAL;
> +
> +       if (cpu >= CONFIG_ARMV8_PSCI_NR_CPUS)
> +               return ARM_PSCI_RET_INVAL;
> +
> +       return psci_state[cpu];
> +}
> +
> +__secure s32 psci_system_reset2_64(u32 __always_unused function_id,
> +                                  u32 reset_type, u64 cookie)
> +{
> +       psci_system_reset();
> +       return 0;       /* Not reached */
> +}
> +
> +/*
> + * 32bit PSCI code
> + */
> +__secure s32 psci_affinity_info(u32 __always_unused function_id,
> +                               u32 target_affinity, u32 lowest_affinity_level)
> +{
> +       return psci_affinity_info_64(function_id, target_affinity, lowest_affinity_level);
> +}
> +
> +__secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr,
> +                        u32 entry_point_address, u32 context_id)
> +{
> +       return psci_cpu_on_64(function_id, mpidr, entry_point_address, context_id);
> +}
> +
> +__secure s32 psci_cpu_off(void)
> +{
> +       u32 cpu = psci_get_cpu_id();
> +
> +       psci_cpu_on_power_off(cpu);
> +       psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
> +
> +       while (1)
> +               wfi();
> +}
> +
> +__secure u32 psci_migrate_info_type(void)
> +{
> +       /* Trusted OS is either not present or does not require migration */
> +       return 2;
> +}
> +
> +__secure void psci_system_reset(void)
> +{
> +       struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
> +       bool ext_reset = true;
> +
> +       u16 wcr = WCR_WDE;
> +
> +       if (ext_reset)
> +               wcr |= WCR_SRS; /* do not assert internal reset */
> +       else
> +               wcr |= WCR_WDA; /* do not assert external reset */
> +
> +       /* Write 3 times to ensure it works, due to IMX6Q errata ERR004346 */
> +       writew(wcr, &wdog->wcr);
> +       writew(wcr, &wdog->wcr);
> +       writew(wcr, &wdog->wcr);
> +
> +       while (1)
> +               wfi();
> +}
> +
> +__secure void psci_system_off(void)
> +{
> +       writel(SNVS_LPCR_TOP | SNVS_LPCR_DP_EN | SNVS_LPCR_SRTC_ENV,
> +              SNVS_BASE_ADDR + SNVS_LPCR);
> +
> +       while (1)
> +               wfi();
> +}
> +
> +/*
> + * PSCI jump table
> + */
> +__secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid)
> +{
> +       switch (psci_fid) {
> +       case ARM_PSCI_0_2_FN_PSCI_VERSION:
> +       case ARM_PSCI_0_2_FN_CPU_OFF:
> +       case ARM_PSCI_0_2_FN_CPU_ON:
> +       case ARM_PSCI_0_2_FN_AFFINITY_INFO:
> +       case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
> +       case ARM_PSCI_0_2_FN_SYSTEM_OFF:
> +       case ARM_PSCI_0_2_FN_SYSTEM_RESET:
> +       case ARM_PSCI_0_2_FN64_CPU_ON:
> +       case ARM_PSCI_0_2_FN64_AFFINITY_INFO:
> +
> +       /* PSCI 1.0 interface */
> +       case ARM_PSCI_1_0_FN_PSCI_FEATURES:
> +
> +       /* PSCI 1.1 interface */
> +       case ARM_PSCI_1_1_FN64_SYSTEM_RESET2:
> +               return 0x0;
> +
> +       /*
> +        * Not implemented:
> +        * ARM_PSCI_0_2_FN_CPU_SUSPEND
> +        * ARM_PSCI_1_0_FN_CPU_FREEZE
> +        * ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND
> +        * ARM_PSCI_1_0_FN_NODE_HW_STATE
> +        * ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
> +        * ARM_PSCI_1_0_FN_SET_SUSPEND_MODE
> +        * ARM_PSCI_1_0_FN_STAT_RESIDENCY
> +        * ARM_PSCI_1_0_FN_STAT_COUNT
> +        * ARM_PSCI_0_2_FN64_CPU_SUSPEND
> +        * ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND
> +        * ARM_PSCI_1_0_FN64_NODE_HW_STATE
> +        * ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND
> +        * ARM_PSCI_1_0_FN64_STAT_RESIDENCY
> +        * ARM_PSCI_1_0_FN64_STAT_COUNT
> +        */
> +
> +       /* Not required, ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE returns 2 */
> +       case ARM_PSCI_0_2_FN_MIGRATE:
> +       case ARM_PSCI_0_2_FN64_MIGRATE:
> +       /* Not required */
> +       case ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU:
> +       case ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU:
> +       default:
> +               return ARM_PSCI_RET_NI;
> +       }
> +}
> --
> 2.35.1
>

Re: [PATCH 10/10] arm: imx: imx8m: Add basic PSCI provider implementation

[Marek Vasut]

On 12/22/22 04:05, Adam Ford wrote:
> On Wed, Dec 21, 2022 at 6:47 PM Marek Vasut <marex@denx.de> wrote:
>>
>> Implement basic PSCI provider to let OS turn CPU cores off and on,
>> power off and restart the system and determine PSCI version. This
>> is sufficient to remove the need for the ATF BL31 blob altogether.
>>
>> To make use of this functionality, active the following Kconfig options:
>>    # CONFIG_PSCI_RESET is not set
>>    CONFIG_ARMV8_MULTIENTRY=y
>>    CONFIG_ARMV8_SET_SMPEN=y
>>    CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
>>    CONFIG_ARMV8_EA_EL3_FIRST=y
>>    CONFIG_ARMV8_PSCI=y
>>    CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
>>    CONFIG_ARMV8_SECURE_BASE=0x970000
> 
>   I am guessing 0x970000 was for the 8MP based on the previous location
> of ATF.  Is that true?   If that's the case, can I assume that this
> address would be  0x910000, 0x920000 and 0x960000 for the imx8mq,
> imx8mm and imx8mn respectively?

It was for MX8MP, but you can pick whichever address you want, since it 
is U-Boot that installs the SMC handlers, you are no longer forced to 
somehow try and accommodate custom not well fitting load address picked 
by some 3rd party binary blob.

Re: [PATCH 10/10] arm: imx: imx8m: Add basic PSCI provider implementation

[Adam Ford]

On Wed, Dec 21, 2022 at 9:58 PM Marek Vasut <marex@denx.de> wrote:
>
> On 12/22/22 04:05, Adam Ford wrote:
> > On Wed, Dec 21, 2022 at 6:47 PM Marek Vasut <marex@denx.de> wrote:
> >>
> >> Implement basic PSCI provider to let OS turn CPU cores off and on,
> >> power off and restart the system and determine PSCI version. This
> >> is sufficient to remove the need for the ATF BL31 blob altogether.
> >>
> >> To make use of this functionality, active the following Kconfig options:
> >>    # CONFIG_PSCI_RESET is not set
> >>    CONFIG_ARMV8_MULTIENTRY=y
> >>    CONFIG_ARMV8_SET_SMPEN=y
> >>    CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
> >>    CONFIG_ARMV8_EA_EL3_FIRST=y
> >>    CONFIG_ARMV8_PSCI=y
> >>    CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
> >>    CONFIG_ARMV8_SECURE_BASE=0x970000
> >
> >   I am guessing 0x970000 was for the 8MP based on the previous location
> > of ATF.  Is that true?   If that's the case, can I assume that this
> > address would be  0x910000, 0x920000 and 0x960000 for the imx8mq,
> > imx8mm and imx8mn respectively?
>
> It was for MX8MP, but you can pick whichever address you want, since it
> is U-Boot that installs the SMC handlers, you are no longer forced to
> somehow try and accommodate custom not well fitting load address picked
> by some 3rd party binary blob.

I patched U-Boot's master with this series and I tried it on
imx8mn_beacon and imx8mm_beacon without success. I never even saw the
SPL message.  I tried to focus on the Nano since the boot ROM in that
one is more similar to that of the 8mp, but the behaviour was similar
to that of the Nano.  Are there any dependencies or should I have used
a specific starting branch?

adam

Re: [PATCH 10/10] arm: imx: imx8m: Add basic PSCI provider implementation

[Marek Vasut]

On 1/2/23 17:44, Adam Ford wrote:
> On Wed, Dec 21, 2022 at 9:58 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 12/22/22 04:05, Adam Ford wrote:
>>> On Wed, Dec 21, 2022 at 6:47 PM Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> Implement basic PSCI provider to let OS turn CPU cores off and on,
>>>> power off and restart the system and determine PSCI version. This
>>>> is sufficient to remove the need for the ATF BL31 blob altogether.
>>>>
>>>> To make use of this functionality, active the following Kconfig options:
>>>>     # CONFIG_PSCI_RESET is not set
>>>>     CONFIG_ARMV8_MULTIENTRY=y
>>>>     CONFIG_ARMV8_SET_SMPEN=y
>>>>     CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
>>>>     CONFIG_ARMV8_EA_EL3_FIRST=y
>>>>     CONFIG_ARMV8_PSCI=y
>>>>     CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
>>>>     CONFIG_ARMV8_SECURE_BASE=0x970000
>>>
>>>    I am guessing 0x970000 was for the 8MP based on the previous location
>>> of ATF.  Is that true?   If that's the case, can I assume that this
>>> address would be  0x910000, 0x920000 and 0x960000 for the imx8mq,
>>> imx8mm and imx8mn respectively?
>>
>> It was for MX8MP, but you can pick whichever address you want, since it
>> is U-Boot that installs the SMC handlers, you are no longer forced to
>> somehow try and accommodate custom not well fitting load address picked
>> by some 3rd party binary blob.
> 
> I patched U-Boot's master with this series and I tried it on
> imx8mn_beacon and imx8mm_beacon without success. I never even saw the
> SPL message.  I tried to focus on the Nano since the boot ROM in that
> one is more similar to that of the 8mp, but the behaviour was similar
> to that of the Nano.  Are there any dependencies or should I have used
> a specific starting branch?

Nope . But if you don't even see output from SPL, that's where I would 
start looking. Do you see output from SPL without this series ? Note 
that bulk of this series content applies to U-Boot proper, not SPL so far.

Re: [PATCH 10/10] arm: imx: imx8m: Add basic PSCI provider implementation

[Adam Ford]

On Mon, Jan 2, 2023 at 5:41 PM Marek Vasut <marex@denx.de> wrote:
>
> On 1/2/23 17:44, Adam Ford wrote:
> > On Wed, Dec 21, 2022 at 9:58 PM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 12/22/22 04:05, Adam Ford wrote:
> >>> On Wed, Dec 21, 2022 at 6:47 PM Marek Vasut <marex@denx.de> wrote:
> >>>>
> >>>> Implement basic PSCI provider to let OS turn CPU cores off and on,
> >>>> power off and restart the system and determine PSCI version. This
> >>>> is sufficient to remove the need for the ATF BL31 blob altogether.
> >>>>
> >>>> To make use of this functionality, active the following Kconfig options:
> >>>>     # CONFIG_PSCI_RESET is not set
> >>>>     CONFIG_ARMV8_MULTIENTRY=y
> >>>>     CONFIG_ARMV8_SET_SMPEN=y
> >>>>     CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
> >>>>     CONFIG_ARMV8_EA_EL3_FIRST=y
> >>>>     CONFIG_ARMV8_PSCI=y
> >>>>     CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
> >>>>     CONFIG_ARMV8_SECURE_BASE=0x970000
> >>>
> >>>    I am guessing 0x970000 was for the 8MP based on the previous location
> >>> of ATF.  Is that true?   If that's the case, can I assume that this
> >>> address would be  0x910000, 0x920000 and 0x960000 for the imx8mq,
> >>> imx8mm and imx8mn respectively?
> >>
> >> It was for MX8MP, but you can pick whichever address you want, since it
> >> is U-Boot that installs the SMC handlers, you are no longer forced to
> >> somehow try and accommodate custom not well fitting load address picked
> >> by some 3rd party binary blob.
> >
> > I patched U-Boot's master with this series and I tried it on
> > imx8mn_beacon and imx8mm_beacon without success. I never even saw the
> > SPL message.  I tried to focus on the Nano since the boot ROM in that
> > one is more similar to that of the 8mp, but the behaviour was similar
> > to that of the Nano.  Are there any dependencies or should I have used
> > a specific starting branch?
>
> Nope . But if you don't even see output from SPL, that's where I would
> start looking. Do you see output from SPL without this series ? Note
> that bulk of this series content applies to U-Boot proper, not SPL so far.

Without the patch series the generated flash.bin file booted both the
Mini and the Nano just fine.  I have a pending 8m plus that I can also
try, since that is what you used.  I just wanted to make sure I was
starting from the right place before I went too far with it.


adam

Re: [PATCH 10/10] arm: imx: imx8m: Add basic PSCI provider implementation

[Marek Vasut]

On 1/3/23 00:47, Adam Ford wrote:
> On Mon, Jan 2, 2023 at 5:41 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 1/2/23 17:44, Adam Ford wrote:
>>> On Wed, Dec 21, 2022 at 9:58 PM Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> On 12/22/22 04:05, Adam Ford wrote:
>>>>> On Wed, Dec 21, 2022 at 6:47 PM Marek Vasut <marex@denx.de> wrote:
>>>>>>
>>>>>> Implement basic PSCI provider to let OS turn CPU cores off and on,
>>>>>> power off and restart the system and determine PSCI version. This
>>>>>> is sufficient to remove the need for the ATF BL31 blob altogether.
>>>>>>
>>>>>> To make use of this functionality, active the following Kconfig options:
>>>>>>      # CONFIG_PSCI_RESET is not set
>>>>>>      CONFIG_ARMV8_MULTIENTRY=y
>>>>>>      CONFIG_ARMV8_SET_SMPEN=y
>>>>>>      CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
>>>>>>      CONFIG_ARMV8_EA_EL3_FIRST=y
>>>>>>      CONFIG_ARMV8_PSCI=y
>>>>>>      CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
>>>>>>      CONFIG_ARMV8_SECURE_BASE=0x970000
>>>>>
>>>>>     I am guessing 0x970000 was for the 8MP based on the previous location
>>>>> of ATF.  Is that true?   If that's the case, can I assume that this
>>>>> address would be  0x910000, 0x920000 and 0x960000 for the imx8mq,
>>>>> imx8mm and imx8mn respectively?
>>>>
>>>> It was for MX8MP, but you can pick whichever address you want, since it
>>>> is U-Boot that installs the SMC handlers, you are no longer forced to
>>>> somehow try and accommodate custom not well fitting load address picked
>>>> by some 3rd party binary blob.
>>>
>>> I patched U-Boot's master with this series and I tried it on
>>> imx8mn_beacon and imx8mm_beacon without success. I never even saw the
>>> SPL message.  I tried to focus on the Nano since the boot ROM in that
>>> one is more similar to that of the 8mp, but the behaviour was similar
>>> to that of the Nano.  Are there any dependencies or should I have used
>>> a specific starting branch?
>>
>> Nope . But if you don't even see output from SPL, that's where I would
>> start looking. Do you see output from SPL without this series ? Note
>> that bulk of this series content applies to U-Boot proper, not SPL so far.
> 
> Without the patch series the generated flash.bin file booted both the
> Mini and the Nano just fine.  I have a pending 8m plus that I can also
> try, since that is what you used.  I just wanted to make sure I was
> starting from the right place before I went too far with it.

Try and drop

[PATCH 09/10] arm: imx: imx8m: Program CSU and TZASC if PSCI provider

does SPL start then ?

I plan to try this on Nano at some point this month too.

Re: [PATCH 10/10] arm: imx: imx8m: Add basic PSCI provider implementation

[Adam Ford]

On Mon, Jan 2, 2023 at 5:58 PM Marek Vasut <marex@denx.de> wrote:
>
> On 1/3/23 00:47, Adam Ford wrote:
> > On Mon, Jan 2, 2023 at 5:41 PM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 1/2/23 17:44, Adam Ford wrote:
> >>> On Wed, Dec 21, 2022 at 9:58 PM Marek Vasut <marex@denx.de> wrote:
> >>>>
> >>>> On 12/22/22 04:05, Adam Ford wrote:
> >>>>> On Wed, Dec 21, 2022 at 6:47 PM Marek Vasut <marex@denx.de> wrote:
> >>>>>>
> >>>>>> Implement basic PSCI provider to let OS turn CPU cores off and on,
> >>>>>> power off and restart the system and determine PSCI version. This
> >>>>>> is sufficient to remove the need for the ATF BL31 blob altogether.
> >>>>>>
> >>>>>> To make use of this functionality, active the following Kconfig options:
> >>>>>>      # CONFIG_PSCI_RESET is not set
> >>>>>>      CONFIG_ARMV8_MULTIENTRY=y
> >>>>>>      CONFIG_ARMV8_SET_SMPEN=y
> >>>>>>      CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
> >>>>>>      CONFIG_ARMV8_EA_EL3_FIRST=y
> >>>>>>      CONFIG_ARMV8_PSCI=y
> >>>>>>      CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
> >>>>>>      CONFIG_ARMV8_SECURE_BASE=0x970000
> >>>>>
> >>>>>     I am guessing 0x970000 was for the 8MP based on the previous location
> >>>>> of ATF.  Is that true?   If that's the case, can I assume that this
> >>>>> address would be  0x910000, 0x920000 and 0x960000 for the imx8mq,
> >>>>> imx8mm and imx8mn respectively?
> >>>>
> >>>> It was for MX8MP, but you can pick whichever address you want, since it
> >>>> is U-Boot that installs the SMC handlers, you are no longer forced to
> >>>> somehow try and accommodate custom not well fitting load address picked
> >>>> by some 3rd party binary blob.
> >>>
> >>> I patched U-Boot's master with this series and I tried it on
> >>> imx8mn_beacon and imx8mm_beacon without success. I never even saw the
> >>> SPL message.  I tried to focus on the Nano since the boot ROM in that
> >>> one is more similar to that of the 8mp, but the behaviour was similar
> >>> to that of the Nano.  Are there any dependencies or should I have used
> >>> a specific starting branch?
> >>
> >> Nope . But if you don't even see output from SPL, that's where I would
> >> start looking. Do you see output from SPL without this series ? Note
> >> that bulk of this series content applies to U-Boot proper, not SPL so far.
> >
> > Without the patch series the generated flash.bin file booted both the
> > Mini and the Nano just fine.  I have a pending 8m plus that I can also
> > try, since that is what you used.  I just wanted to make sure I was
> > starting from the right place before I went too far with it.
>
> Try and drop
>
> [PATCH 09/10] arm: imx: imx8m: Program CSU and TZASC if PSCI provider
>
> does SPL start then ?

I reverted 9/19 without success either.  I'll try to do a git bisect
to see if I can narrow it down.  I might see if my employer will let
me borrow  a debugger.  Debugging SPL is a bit challenging due to the
relocation step, but I am not convinced I am geting that far since I
get no text output at all.
>
> I plan to try this on Nano at some point this month too.

I'll let you know my findings when I get some more time to test this.

adam

Re: [PATCH 10/10] arm: imx: imx8m: Add basic PSCI provider implementation

[Marek Vasut]

On 1/3/23 02:05, Adam Ford wrote:
> On Mon, Jan 2, 2023 at 5:58 PM Marek Vasut <marex@denx.de> wrote:
>>
>> On 1/3/23 00:47, Adam Ford wrote:
>>> On Mon, Jan 2, 2023 at 5:41 PM Marek Vasut <marex@denx.de> wrote:
>>>>
>>>> On 1/2/23 17:44, Adam Ford wrote:
>>>>> On Wed, Dec 21, 2022 at 9:58 PM Marek Vasut <marex@denx.de> wrote:
>>>>>>
>>>>>> On 12/22/22 04:05, Adam Ford wrote:
>>>>>>> On Wed, Dec 21, 2022 at 6:47 PM Marek Vasut <marex@denx.de> wrote:
>>>>>>>>
>>>>>>>> Implement basic PSCI provider to let OS turn CPU cores off and on,
>>>>>>>> power off and restart the system and determine PSCI version. This
>>>>>>>> is sufficient to remove the need for the ATF BL31 blob altogether.
>>>>>>>>
>>>>>>>> To make use of this functionality, active the following Kconfig options:
>>>>>>>>       # CONFIG_PSCI_RESET is not set
>>>>>>>>       CONFIG_ARMV8_MULTIENTRY=y
>>>>>>>>       CONFIG_ARMV8_SET_SMPEN=y
>>>>>>>>       CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
>>>>>>>>       CONFIG_ARMV8_EA_EL3_FIRST=y
>>>>>>>>       CONFIG_ARMV8_PSCI=y
>>>>>>>>       CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
>>>>>>>>       CONFIG_ARMV8_SECURE_BASE=0x970000
>>>>>>>
>>>>>>>      I am guessing 0x970000 was for the 8MP based on the previous location
>>>>>>> of ATF.  Is that true?   If that's the case, can I assume that this
>>>>>>> address would be  0x910000, 0x920000 and 0x960000 for the imx8mq,
>>>>>>> imx8mm and imx8mn respectively?
>>>>>>
>>>>>> It was for MX8MP, but you can pick whichever address you want, since it
>>>>>> is U-Boot that installs the SMC handlers, you are no longer forced to
>>>>>> somehow try and accommodate custom not well fitting load address picked
>>>>>> by some 3rd party binary blob.
>>>>>
>>>>> I patched U-Boot's master with this series and I tried it on
>>>>> imx8mn_beacon and imx8mm_beacon without success. I never even saw the
>>>>> SPL message.  I tried to focus on the Nano since the boot ROM in that
>>>>> one is more similar to that of the 8mp, but the behaviour was similar
>>>>> to that of the Nano.  Are there any dependencies or should I have used
>>>>> a specific starting branch?
>>>>
>>>> Nope . But if you don't even see output from SPL, that's where I would
>>>> start looking. Do you see output from SPL without this series ? Note
>>>> that bulk of this series content applies to U-Boot proper, not SPL so far.
>>>
>>> Without the patch series the generated flash.bin file booted both the
>>> Mini and the Nano just fine.  I have a pending 8m plus that I can also
>>> try, since that is what you used.  I just wanted to make sure I was
>>> starting from the right place before I went too far with it.
>>
>> Try and drop
>>
>> [PATCH 09/10] arm: imx: imx8m: Program CSU and TZASC if PSCI provider
>>
>> does SPL start then ?
> 
> I reverted 9/19 without success either.  I'll try to do a git bisect
> to see if I can narrow it down.  I might see if my employer will let
> me borrow  a debugger.  Debugging SPL is a bit challenging due to the
> relocation step, but I am not convinced I am geting that far since I
> get no text output at all.

Hmmmmm, did you tweak the CONFIG_ARMV8_SECURE_BASE ? Are you sure your 
setting is within valid OCRAM address range ? I think the MX8MN OCRAM is 
smaller than the MX8MP one, but I might be wrong.

Bisect looks like the best option now. You can start by scrubbing the 
custom config options and see if the result still boots with the blob 
bl31.bin . If it does, it is somehow related to the newly enabled code. 
It has to be related to something very early though, something which is 
triggered before the UART init. Do you use DM_SERIAL in SPL ?

>> I plan to try this on Nano at some point this month too.
> 
> I'll let you know my findings when I get some more time to test this.

Thanks

[PATCH 01/10] arm: psci: Add PSCI v1.1 macro

[sbabic]

> Add macro representing the PSCI v1.1 .
> Signed-off-by: Marek Vasut <marex@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 07/10] arm: imx: imx8m: Map RAM as NS if PSCI provider

[sbabic]

> In case U-Boot is a PSCI provider, map RAM explicitly as NS,
> otherwise secondary cores crash with SError when attempting
> to access RAM mapped as secure in EL2.
> Signed-off-by: Marek Vasut <marex@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 04/10] arm: dts: imx8m: Require ATF BL31 blob only if not PSCI provider

[sbabic]

> In case U-Boot itself if the PSCI provider on i.MX8M, do not
> require the ATF BL31 blob, as at that point the blob is useless
> and would interfere with U-Boot operation.
> Signed-off-by: Marek Vasut <marex@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 10/10] arm: imx: imx8m: Add basic PSCI provider implementation

[sbabic]

> Implement basic PSCI provider to let OS turn CPU cores off and on,
> power off and restart the system and determine PSCI version. This
> is sufficient to remove the need for the ATF BL31 blob altogether.
> To make use of this functionality, active the following Kconfig options:
>   # CONFIG_PSCI_RESET is not set
>   CONFIG_ARMV8_MULTIENTRY=y
>   CONFIG_ARMV8_SET_SMPEN=y
>   CONFIG_ARMV8_SPL_EXCEPTION_VECTORS=y
>   CONFIG_ARMV8_EA_EL3_FIRST=y
>   CONFIG_ARMV8_PSCI=y
>   CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER=4
>   CONFIG_ARMV8_SECURE_BASE=0x970000
>   CONFIG_ARM_SMCCC=y
>   CONFIG_SYS_HAS_ARMV8_SECURE_BASE=y
> Signed-off-by: Marek Vasut <marex@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 02/10] arm: psci: Fix RESET2 hook

[sbabic]

> The RESET2 hook is a PSCI v1.1 functionality, rename the macro accordinly.
> Add missing handler for the RESET2 hook, so it can be implemented by U-Boot.
> Signed-off-by: Marek Vasut <marex@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 05/10] arm: imx: imx8m: Only use ROM pointers if not PSCI provider

[sbabic]

> The ROM pointers are in fact populated by the ATF BL31 blob, in case
> U-Boot itself if the PSCI provider, there is no ATF BL31 blob, hence
> ignore the ROM pointers.
> Signed-off-by: Marek Vasut <marex@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 03/10] arm: imx: Drop custom lowlevel_init

[sbabic]

> The custom lowlevel_init implementation is no longer necessary, since
> it is responsible for routing and trapping SErrors in U-Boot in EL2,
> which is implemented in common code since commit:
> 6c7691edd55 ("armv8: Always unmask SErrors")
> Signed-off-by: Marek Vasut <marex@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 06/10] arm: imx: imx8m: Enable GICv3 support if PSCI provider

[sbabic]

> In case U-Boot is a PSCI provider, enable GICv3 support as this
> is necessary to bring up secondary cores.
> Signed-off-by: Marek Vasut <marex@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 08/10] arm: imx: imx8m: Define trampoline location if PSCI provider

[sbabic]

> The common code used to bring up secondary cores requires a final
> jump location to be stored in some sort of memory location, define
> this memory location to be the start of OCRAM, since it is available.
> Signed-off-by: Marek Vasut <marex@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 09/10] arm: imx: imx8m: Program CSU and TZASC if PSCI provider

[sbabic]

> In case U-Boot is the PSCI provider, it is necessary to correctly
> program CSU and TZASC registers. Those are poorly documented, so
> push in the correct values.
> Signed-off-by: Marek Vasut <marex@denx.de>
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,        Managing Director: Erika Unter  
HRB 165235 Munich,   Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================