* [PATCH] drm/amdgpu: Revert programming GRBM_GFX_* in RLCG interface to support GFX9
@ 2023-02-08 9:54 Yifan Zha
2023-02-13 6:05 ` Zhang, Hawking
0 siblings, 1 reply; 2+ messages in thread
From: Yifan Zha @ 2023-02-08 9:54 UTC (permalink / raw)
To: amd-gfx, Alexander.Deucher, Hawking.Zhang
Cc: Horace.Chen, Yifan Zha, haijun.chang
[Why]
Regression of commit a291321cce8e("drm/amdgpu: Remove writing GRBM_GFX_CNTL in RLCG interface under SRIOV") on GFX9.
According to GFX9 VF using different method to access GC registers including MMIO(direct) and RLCG(indirect),
removing GRBM_GFX_* writing would make PIPE/ME/VM/QUEUE selection chaos leading to some OCL benchmark failure.
For example,
using RLCG interface to program GRBM_GFX_CNTL/INDEX for selecting MEC(actually the value is only in scratch2/3),
then using MMIO directly program a MEC register in VF driver.
The register programming are invalid due to GC switched to incorrect ME.
[How]
With checking RLCG accessing flag, keep writing GRBM_GFX_* as a legacy way.
But it is still skipped on GFX10+ to avoid violation occurrence.
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index ca5a1d026f5a..f2e2cbaa7fde 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -983,9 +983,13 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
if (offset == reg_access_ctrl->grbm_cntl) {
/* if the target reg offset is grbm_cntl, write to scratch_reg2 */
writel(v, scratch_reg2);
+ if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY)
+ writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
} else if (offset == reg_access_ctrl->grbm_idx) {
/* if the target reg offset is grbm_idx, write to scratch_reg3 */
writel(v, scratch_reg3);
+ if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY)
+ writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
} else {
/*
* SCRATCH_REG0 = read/write value
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* RE: [PATCH] drm/amdgpu: Revert programming GRBM_GFX_* in RLCG interface to support GFX9
2023-02-08 9:54 [PATCH] drm/amdgpu: Revert programming GRBM_GFX_* in RLCG interface to support GFX9 Yifan Zha
@ 2023-02-13 6:05 ` Zhang, Hawking
0 siblings, 0 replies; 2+ messages in thread
From: Zhang, Hawking @ 2023-02-13 6:05 UTC (permalink / raw)
To: Zha, YiFan(Even), amd-gfx, Deucher, Alexander
Cc: Chen, Horace, Zha, YiFan(Even), Chang, HaiJun
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Regards,
Hawking
-----Original Message-----
From: Yifan Zha <Yifan.Zha@amd.com>
Sent: Wednesday, February 8, 2023 17:55
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>
Cc: Chen, Horace <Horace.Chen@amd.com>; Chang, HaiJun <HaiJun.Chang@amd.com>; Zha, YiFan(Even) <Yifan.Zha@amd.com>
Subject: [PATCH] drm/amdgpu: Revert programming GRBM_GFX_* in RLCG interface to support GFX9
[Why]
Regression of commit a291321cce8e("drm/amdgpu: Remove writing GRBM_GFX_CNTL in RLCG interface under SRIOV") on GFX9.
According to GFX9 VF using different method to access GC registers including MMIO(direct) and RLCG(indirect), removing GRBM_GFX_* writing would make PIPE/ME/VM/QUEUE selection chaos leading to some OCL benchmark failure.
For example,
using RLCG interface to program GRBM_GFX_CNTL/INDEX for selecting MEC(actually the value is only in scratch2/3), then using MMIO directly program a MEC register in VF driver.
The register programming are invalid due to GC switched to incorrect ME.
[How]
With checking RLCG accessing flag, keep writing GRBM_GFX_* as a legacy way.
But it is still skipped on GFX10+ to avoid violation occurrence.
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index ca5a1d026f5a..f2e2cbaa7fde 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -983,9 +983,13 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
if (offset == reg_access_ctrl->grbm_cntl) {
/* if the target reg offset is grbm_cntl, write to scratch_reg2 */
writel(v, scratch_reg2);
+ if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY)
+ writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
} else if (offset == reg_access_ctrl->grbm_idx) {
/* if the target reg offset is grbm_idx, write to scratch_reg3 */
writel(v, scratch_reg3);
+ if (flag == AMDGPU_RLCG_GC_WRITE_LEGACY)
+ writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
} else {
/*
* SCRATCH_REG0 = read/write value
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
end of thread, other threads:[~2023-02-13 6:05 UTC | newest]
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2023-02-13 6:05 ` Zhang, Hawking
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