* [PATCH 1/3] perf/amlogic: Fix config1/config2 parsing issue
@ 2023-02-09 11:54 ` Jiucheng Xu
0 siblings, 0 replies; 24+ messages in thread
From: Jiucheng Xu @ 2023-02-09 11:54 UTC (permalink / raw)
To: Jiucheng Xu, Will Deacon, Mark Rutland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: Jianxin Pan, Kelvin Zhang, Chris Healy, Chris Healy,
linux-amlogic, linux-arm-kernel, linux-kernel
The 3th argument of for_each_set_bit is incorrect, fix them.
Fixes: 2016e2113d35 ("perf/amlogic: Add support for Amlogic meson G12 SoC DDR PMU driver")
Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
---
drivers/perf/amlogic/meson_ddr_pmu_core.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
index b84346dbac2c..0b24dee1ed3c 100644
--- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
+++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
@@ -156,10 +156,14 @@ static int meson_ddr_perf_event_add(struct perf_event *event, int flags)
u64 config2 = event->attr.config2;
int i;
- for_each_set_bit(i, (const unsigned long *)&config1, sizeof(config1))
+ for_each_set_bit(i,
+ (const unsigned long *)&config1,
+ BITS_PER_TYPE(config1))
meson_ddr_set_axi_filter(event, i);
- for_each_set_bit(i, (const unsigned long *)&config2, sizeof(config2))
+ for_each_set_bit(i,
+ (const unsigned long *)&config2,
+ BITS_PER_TYPE(config2))
meson_ddr_set_axi_filter(event, i + 64);
if (flags & PERF_EF_START)
base-commit: e8a709dc2a9156f223ec953ae70a919e87ad7e9a
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 1/3] perf/amlogic: Fix config1/config2 parsing issue
@ 2023-02-09 11:54 ` Jiucheng Xu
0 siblings, 0 replies; 24+ messages in thread
From: Jiucheng Xu @ 2023-02-09 11:54 UTC (permalink / raw)
To: Jiucheng Xu, Will Deacon, Mark Rutland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: Jianxin Pan, Kelvin Zhang, Chris Healy, Chris Healy,
linux-amlogic, linux-arm-kernel, linux-kernel
The 3th argument of for_each_set_bit is incorrect, fix them.
Fixes: 2016e2113d35 ("perf/amlogic: Add support for Amlogic meson G12 SoC DDR PMU driver")
Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
---
drivers/perf/amlogic/meson_ddr_pmu_core.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
index b84346dbac2c..0b24dee1ed3c 100644
--- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
+++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
@@ -156,10 +156,14 @@ static int meson_ddr_perf_event_add(struct perf_event *event, int flags)
u64 config2 = event->attr.config2;
int i;
- for_each_set_bit(i, (const unsigned long *)&config1, sizeof(config1))
+ for_each_set_bit(i,
+ (const unsigned long *)&config1,
+ BITS_PER_TYPE(config1))
meson_ddr_set_axi_filter(event, i);
- for_each_set_bit(i, (const unsigned long *)&config2, sizeof(config2))
+ for_each_set_bit(i,
+ (const unsigned long *)&config2,
+ BITS_PER_TYPE(config2))
meson_ddr_set_axi_filter(event, i + 64);
if (flags & PERF_EF_START)
base-commit: e8a709dc2a9156f223ec953ae70a919e87ad7e9a
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 2/3] perf/amlogic: Fix large number of counter issue
2023-02-09 11:54 ` Jiucheng Xu
(?)
@ 2023-02-09 11:54 ` Jiucheng Xu
-1 siblings, 0 replies; 24+ messages in thread
From: Jiucheng Xu @ 2023-02-09 11:54 UTC (permalink / raw)
To: Jiucheng Xu, Will Deacon, Mark Rutland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: Jianxin Pan, Kelvin Zhang, Chris Healy, Chris Healy,
linux-amlogic, linux-arm-kernel, linux-kernel
When use 1ms interval, very large number of counter happens
once in a while as below:
25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
Root cause is the race between irq handler
and pmu.read callback. Use spin lock to protect the sw&hw
counters.
Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
---
drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
index 0b24dee1ed3c..9b2e5d5c0626 100644
--- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
+++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
@@ -14,6 +14,7 @@
#include <linux/perf_event.h>
#include <linux/platform_device.h>
#include <linux/printk.h>
+#include <linux/spinlock.h>
#include <linux/sysfs.h>
#include <linux/types.h>
@@ -23,6 +24,7 @@ struct ddr_pmu {
struct pmu pmu;
struct dmc_info info;
struct dmc_counter counters; /* save counters from hw */
+ spinlock_t lock; /* protect hw/sw counter */
bool pmu_enabled;
struct device *dev;
char *name;
@@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event)
int idx;
int chann_nr = pmu->info.hw_info->chann_nr;
+ spin_lock(&pmu->lock);
/* get the remain counters in register. */
pmu->info.hw_info->get_counters(&pmu->info, &dc);
ddr_cnt_addition(&sum_dc, &pmu->counters, &dc, chann_nr);
+ spin_unlock(&pmu->lock);
switch (event->attr.config) {
case ALL_CHAN_COUNTER_ID:
@@ -355,6 +359,7 @@ static irqreturn_t dmc_irq_handler(int irq, void *dev_id)
pmu = dmc_info_to_pmu(info);
+ spin_lock(&pmu->lock);
if (info->hw_info->irq_handler(info, &counters) != 0)
goto out;
@@ -372,6 +377,8 @@ static irqreturn_t dmc_irq_handler(int irq, void *dev_id)
* it in ISR to support continue mode.
*/
info->hw_info->enable(info);
+out:
+ spin_unlock(&pmu->lock);
dev_dbg(pmu->dev, "counts: %llu %llu %llu, %llu, %llu, %llu\t\t"
"sum: %llu %llu %llu, %llu, %llu, %llu\n",
@@ -388,7 +395,7 @@ static irqreturn_t dmc_irq_handler(int irq, void *dev_id)
pmu->counters.channel_cnt[1],
pmu->counters.channel_cnt[2],
pmu->counters.channel_cnt[3]);
-out:
+
return IRQ_HANDLED;
}
@@ -539,6 +546,7 @@ int meson_ddr_pmu_create(struct platform_device *pdev)
pmu->name = name;
pmu->dev = &pdev->dev;
pmu->pmu_enabled = false;
+ spin_lock_init(&pmu->lock);
platform_set_drvdata(pdev, pmu);
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 2/3] perf/amlogic: Fix large number of counter issue
@ 2023-02-09 11:54 ` Jiucheng Xu
0 siblings, 0 replies; 24+ messages in thread
From: Jiucheng Xu @ 2023-02-09 11:54 UTC (permalink / raw)
To: Jiucheng Xu, Will Deacon, Mark Rutland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: Jianxin Pan, Kelvin Zhang, Chris Healy, Chris Healy,
linux-amlogic, linux-arm-kernel, linux-kernel
When use 1ms interval, very large number of counter happens
once in a while as below:
25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
Root cause is the race between irq handler
and pmu.read callback. Use spin lock to protect the sw&hw
counters.
Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
---
drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
index 0b24dee1ed3c..9b2e5d5c0626 100644
--- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
+++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
@@ -14,6 +14,7 @@
#include <linux/perf_event.h>
#include <linux/platform_device.h>
#include <linux/printk.h>
+#include <linux/spinlock.h>
#include <linux/sysfs.h>
#include <linux/types.h>
@@ -23,6 +24,7 @@ struct ddr_pmu {
struct pmu pmu;
struct dmc_info info;
struct dmc_counter counters; /* save counters from hw */
+ spinlock_t lock; /* protect hw/sw counter */
bool pmu_enabled;
struct device *dev;
char *name;
@@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event)
int idx;
int chann_nr = pmu->info.hw_info->chann_nr;
+ spin_lock(&pmu->lock);
/* get the remain counters in register. */
pmu->info.hw_info->get_counters(&pmu->info, &dc);
ddr_cnt_addition(&sum_dc, &pmu->counters, &dc, chann_nr);
+ spin_unlock(&pmu->lock);
switch (event->attr.config) {
case ALL_CHAN_COUNTER_ID:
@@ -355,6 +359,7 @@ static irqreturn_t dmc_irq_handler(int irq, void *dev_id)
pmu = dmc_info_to_pmu(info);
+ spin_lock(&pmu->lock);
if (info->hw_info->irq_handler(info, &counters) != 0)
goto out;
@@ -372,6 +377,8 @@ static irqreturn_t dmc_irq_handler(int irq, void *dev_id)
* it in ISR to support continue mode.
*/
info->hw_info->enable(info);
+out:
+ spin_unlock(&pmu->lock);
dev_dbg(pmu->dev, "counts: %llu %llu %llu, %llu, %llu, %llu\t\t"
"sum: %llu %llu %llu, %llu, %llu, %llu\n",
@@ -388,7 +395,7 @@ static irqreturn_t dmc_irq_handler(int irq, void *dev_id)
pmu->counters.channel_cnt[1],
pmu->counters.channel_cnt[2],
pmu->counters.channel_cnt[3]);
-out:
+
return IRQ_HANDLED;
}
@@ -539,6 +546,7 @@ int meson_ddr_pmu_create(struct platform_device *pdev)
pmu->name = name;
pmu->dev = &pdev->dev;
pmu->pmu_enabled = false;
+ spin_lock_init(&pmu->lock);
platform_set_drvdata(pdev, pmu);
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH 2/3] perf/amlogic: Fix large number of counter issue
@ 2023-02-09 11:54 ` Jiucheng Xu
0 siblings, 0 replies; 24+ messages in thread
From: Jiucheng Xu @ 2023-02-09 11:54 UTC (permalink / raw)
To: Jiucheng Xu, Will Deacon, Mark Rutland, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl
Cc: Jianxin Pan, Kelvin Zhang, Chris Healy, Chris Healy,
linux-amlogic, linux-arm-kernel, linux-kernel
When use 1ms interval, very large number of counter happens
once in a while as below:
25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
Root cause is the race between irq handler
and pmu.read callback. Use spin lock to protect the sw&hw
counters.
Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
---
drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
index 0b24dee1ed3c..9b2e5d5c0626 100644
--- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
+++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
@@ -14,6 +14,7 @@
#include <linux/perf_event.h>
#include <linux/platform_device.h>
#include <linux/printk.h>
+#include <linux/spinlock.h>
#include <linux/sysfs.h>
#include <linux/types.h>
@@ -23,6 +24,7 @@ struct ddr_pmu {
struct pmu pmu;
struct dmc_info info;
struct dmc_counter counters; /* save counters from hw */
+ spinlock_t lock; /* protect hw/sw counter */
bool pmu_enabled;
struct device *dev;
char *name;
@@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event)
int idx;
int chann_nr = pmu->info.hw_info->chann_nr;
+ spin_lock(&pmu->lock);
/* get the remain counters in register. */
pmu->info.hw_info->get_counters(&pmu->info, &dc);
ddr_cnt_addition(&sum_dc, &pmu->counters, &dc, chann_nr);
+ spin_unlock(&pmu->lock);
switch (event->attr.config) {
case ALL_CHAN_COUNTER_ID:
@@ -355,6 +359,7 @@ static irqreturn_t dmc_irq_handler(int irq, void *dev_id)
pmu = dmc_info_to_pmu(info);
+ spin_lock(&pmu->lock);
if (info->hw_info->irq_handler(info, &counters) != 0)
goto out;
@@ -372,6 +377,8 @@ static irqreturn_t dmc_irq_handler(int irq, void *dev_id)
* it in ISR to support continue mode.
*/
info->hw_info->enable(info);
+out:
+ spin_unlock(&pmu->lock);
dev_dbg(pmu->dev, "counts: %llu %llu %llu, %llu, %llu, %llu\t\t"
"sum: %llu %llu %llu, %llu, %llu, %llu\n",
@@ -388,7 +395,7 @@ static irqreturn_t dmc_irq_handler(int irq, void *dev_id)
pmu->counters.channel_cnt[1],
pmu->counters.channel_cnt[2],
pmu->counters.channel_cnt[3]);
-out:
+
return IRQ_HANDLED;
}
@@ -539,6 +546,7 @@ int meson_ddr_pmu_create(struct platform_device *pdev)
pmu->name = name;
pmu->dev = &pdev->dev;
pmu->pmu_enabled = false;
+ spin_lock_init(&pmu->lock);
platform_set_drvdata(pdev, pmu);
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH 2/3] perf/amlogic: Fix large number of counter issue
2023-02-09 11:54 ` Jiucheng Xu
(?)
@ 2023-03-27 14:10 ` Will Deacon
-1 siblings, 0 replies; 24+ messages in thread
From: Will Deacon @ 2023-03-27 14:10 UTC (permalink / raw)
To: Jiucheng Xu
Cc: Mark Rutland, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Jianxin Pan, Kelvin Zhang, Chris Healy,
Chris Healy, linux-amlogic, linux-arm-kernel, linux-kernel
On Thu, Feb 09, 2023 at 07:54:02PM +0800, Jiucheng Xu wrote:
> When use 1ms interval, very large number of counter happens
> once in a while as below:
>
> 25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> 26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> 26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
>
> Root cause is the race between irq handler
> and pmu.read callback. Use spin lock to protect the sw&hw
> counters.
>
> Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
> ---
> drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
> index 0b24dee1ed3c..9b2e5d5c0626 100644
> --- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
> +++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
> @@ -14,6 +14,7 @@
> #include <linux/perf_event.h>
> #include <linux/platform_device.h>
> #include <linux/printk.h>
> +#include <linux/spinlock.h>
> #include <linux/sysfs.h>
> #include <linux/types.h>
>
> @@ -23,6 +24,7 @@ struct ddr_pmu {
> struct pmu pmu;
> struct dmc_info info;
> struct dmc_counter counters; /* save counters from hw */
> + spinlock_t lock; /* protect hw/sw counter */
> bool pmu_enabled;
> struct device *dev;
> char *name;
> @@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event)
> int idx;
> int chann_nr = pmu->info.hw_info->chann_nr;
>
> + spin_lock(&pmu->lock);
Why doesn't this need the _irqsave() variant if we're racing with the irq
handler?
Will
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 2/3] perf/amlogic: Fix large number of counter issue
@ 2023-03-27 14:10 ` Will Deacon
0 siblings, 0 replies; 24+ messages in thread
From: Will Deacon @ 2023-03-27 14:10 UTC (permalink / raw)
To: Jiucheng Xu
Cc: Mark Rutland, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Jianxin Pan, Kelvin Zhang, Chris Healy,
Chris Healy, linux-amlogic, linux-arm-kernel, linux-kernel
On Thu, Feb 09, 2023 at 07:54:02PM +0800, Jiucheng Xu wrote:
> When use 1ms interval, very large number of counter happens
> once in a while as below:
>
> 25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> 26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> 26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
>
> Root cause is the race between irq handler
> and pmu.read callback. Use spin lock to protect the sw&hw
> counters.
>
> Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
> ---
> drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
> index 0b24dee1ed3c..9b2e5d5c0626 100644
> --- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
> +++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
> @@ -14,6 +14,7 @@
> #include <linux/perf_event.h>
> #include <linux/platform_device.h>
> #include <linux/printk.h>
> +#include <linux/spinlock.h>
> #include <linux/sysfs.h>
> #include <linux/types.h>
>
> @@ -23,6 +24,7 @@ struct ddr_pmu {
> struct pmu pmu;
> struct dmc_info info;
> struct dmc_counter counters; /* save counters from hw */
> + spinlock_t lock; /* protect hw/sw counter */
> bool pmu_enabled;
> struct device *dev;
> char *name;
> @@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event)
> int idx;
> int chann_nr = pmu->info.hw_info->chann_nr;
>
> + spin_lock(&pmu->lock);
Why doesn't this need the _irqsave() variant if we're racing with the irq
handler?
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 2/3] perf/amlogic: Fix large number of counter issue
@ 2023-03-27 14:10 ` Will Deacon
0 siblings, 0 replies; 24+ messages in thread
From: Will Deacon @ 2023-03-27 14:10 UTC (permalink / raw)
To: Jiucheng Xu
Cc: Mark Rutland, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Jianxin Pan, Kelvin Zhang, Chris Healy,
Chris Healy, linux-amlogic, linux-arm-kernel, linux-kernel
On Thu, Feb 09, 2023 at 07:54:02PM +0800, Jiucheng Xu wrote:
> When use 1ms interval, very large number of counter happens
> once in a while as below:
>
> 25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> 26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> 26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
>
> Root cause is the race between irq handler
> and pmu.read callback. Use spin lock to protect the sw&hw
> counters.
>
> Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
> ---
> drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
> index 0b24dee1ed3c..9b2e5d5c0626 100644
> --- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
> +++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
> @@ -14,6 +14,7 @@
> #include <linux/perf_event.h>
> #include <linux/platform_device.h>
> #include <linux/printk.h>
> +#include <linux/spinlock.h>
> #include <linux/sysfs.h>
> #include <linux/types.h>
>
> @@ -23,6 +24,7 @@ struct ddr_pmu {
> struct pmu pmu;
> struct dmc_info info;
> struct dmc_counter counters; /* save counters from hw */
> + spinlock_t lock; /* protect hw/sw counter */
> bool pmu_enabled;
> struct device *dev;
> char *name;
> @@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event)
> int idx;
> int chann_nr = pmu->info.hw_info->chann_nr;
>
> + spin_lock(&pmu->lock);
Why doesn't this need the _irqsave() variant if we're racing with the irq
handler?
Will
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 2/3] perf/amlogic: Fix large number of counter issue
2023-03-27 14:10 ` Will Deacon
(?)
@ 2023-03-28 2:29 ` Jiucheng Xu
-1 siblings, 0 replies; 24+ messages in thread
From: Jiucheng Xu @ 2023-03-28 2:29 UTC (permalink / raw)
To: Will Deacon
Cc: Mark Rutland, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Jianxin Pan, Kelvin Zhang, Chris Healy,
Chris Healy, linux-amlogic, linux-arm-kernel, linux-kernel
My Amlogic email box has some issues. Use my personal email
<jiucheng.xu@163.com> to reply.
On 2023/3/27 22:10, Will Deacon wrote:
> [ EXTERNAL EMAIL ]
>
> On Thu, Feb 09, 2023 at 07:54:02PM +0800, Jiucheng Xu wrote:
>> When use 1ms interval, very large number of counter happens
>> once in a while as below:
>>
>> 25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
>> 26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
>> 26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
>>
>> Root cause is the race between irq handler
>> and pmu.read callback. Use spin lock to protect the sw&hw
>> counters.
>>
>> Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
>> ---
>> drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++-
>> 1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
>> index 0b24dee1ed3c..9b2e5d5c0626 100644
>> --- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
>> +++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
>> @@ -14,6 +14,7 @@
>> #include <linux/perf_event.h>
>> #include <linux/platform_device.h>
>> #include <linux/printk.h>
>> +#include <linux/spinlock.h>
>> #include <linux/sysfs.h>
>> #include <linux/types.h>
>>
>> @@ -23,6 +24,7 @@ struct ddr_pmu {
>> struct pmu pmu;
>> struct dmc_info info;
>> struct dmc_counter counters; /* save counters from hw */
>> + spinlock_t lock; /* protect hw/sw counter */
>> bool pmu_enabled;
>> struct device *dev;
>> char *name;
>> @@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event)
>> int idx;
>> int chann_nr = pmu->info.hw_info->chann_nr;
>>
>> + spin_lock(&pmu->lock);
> Why doesn't this need the _irqsave() variant if we're racing with the irq
> handler?
>
> Will
I think meson_ddr_perf_event_update function is called with hard irq off.
So update function couldn't be interrupted by irq handler. Right?
Thanks,
Jiucheng
>
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 2/3] perf/amlogic: Fix large number of counter issue
@ 2023-03-28 2:29 ` Jiucheng Xu
0 siblings, 0 replies; 24+ messages in thread
From: Jiucheng Xu @ 2023-03-28 2:29 UTC (permalink / raw)
To: Will Deacon
Cc: Mark Rutland, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Jianxin Pan, Kelvin Zhang, Chris Healy,
Chris Healy, linux-amlogic, linux-arm-kernel, linux-kernel
My Amlogic email box has some issues. Use my personal email
<jiucheng.xu@163.com> to reply.
On 2023/3/27 22:10, Will Deacon wrote:
> [ EXTERNAL EMAIL ]
>
> On Thu, Feb 09, 2023 at 07:54:02PM +0800, Jiucheng Xu wrote:
>> When use 1ms interval, very large number of counter happens
>> once in a while as below:
>>
>> 25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
>> 26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
>> 26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
>>
>> Root cause is the race between irq handler
>> and pmu.read callback. Use spin lock to protect the sw&hw
>> counters.
>>
>> Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
>> ---
>> drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++-
>> 1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
>> index 0b24dee1ed3c..9b2e5d5c0626 100644
>> --- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
>> +++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
>> @@ -14,6 +14,7 @@
>> #include <linux/perf_event.h>
>> #include <linux/platform_device.h>
>> #include <linux/printk.h>
>> +#include <linux/spinlock.h>
>> #include <linux/sysfs.h>
>> #include <linux/types.h>
>>
>> @@ -23,6 +24,7 @@ struct ddr_pmu {
>> struct pmu pmu;
>> struct dmc_info info;
>> struct dmc_counter counters; /* save counters from hw */
>> + spinlock_t lock; /* protect hw/sw counter */
>> bool pmu_enabled;
>> struct device *dev;
>> char *name;
>> @@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event)
>> int idx;
>> int chann_nr = pmu->info.hw_info->chann_nr;
>>
>> + spin_lock(&pmu->lock);
> Why doesn't this need the _irqsave() variant if we're racing with the irq
> handler?
>
> Will
I think meson_ddr_perf_event_update function is called with hard irq off.
So update function couldn't be interrupted by irq handler. Right?
Thanks,
Jiucheng
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 2/3] perf/amlogic: Fix large number of counter issue
@ 2023-03-28 2:29 ` Jiucheng Xu
0 siblings, 0 replies; 24+ messages in thread
From: Jiucheng Xu @ 2023-03-28 2:29 UTC (permalink / raw)
To: Will Deacon
Cc: Mark Rutland, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Jianxin Pan, Kelvin Zhang, Chris Healy,
Chris Healy, linux-amlogic, linux-arm-kernel, linux-kernel
My Amlogic email box has some issues. Use my personal email
<jiucheng.xu@163.com> to reply.
On 2023/3/27 22:10, Will Deacon wrote:
> [ EXTERNAL EMAIL ]
>
> On Thu, Feb 09, 2023 at 07:54:02PM +0800, Jiucheng Xu wrote:
>> When use 1ms interval, very large number of counter happens
>> once in a while as below:
>>
>> 25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
>> 26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
>> 26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
>>
>> Root cause is the race between irq handler
>> and pmu.read callback. Use spin lock to protect the sw&hw
>> counters.
>>
>> Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
>> ---
>> drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++-
>> 1 file changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
>> index 0b24dee1ed3c..9b2e5d5c0626 100644
>> --- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
>> +++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
>> @@ -14,6 +14,7 @@
>> #include <linux/perf_event.h>
>> #include <linux/platform_device.h>
>> #include <linux/printk.h>
>> +#include <linux/spinlock.h>
>> #include <linux/sysfs.h>
>> #include <linux/types.h>
>>
>> @@ -23,6 +24,7 @@ struct ddr_pmu {
>> struct pmu pmu;
>> struct dmc_info info;
>> struct dmc_counter counters; /* save counters from hw */
>> + spinlock_t lock; /* protect hw/sw counter */
>> bool pmu_enabled;
>> struct device *dev;
>> char *name;
>> @@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event)
>> int idx;
>> int chann_nr = pmu->info.hw_info->chann_nr;
>>
>> + spin_lock(&pmu->lock);
> Why doesn't this need the _irqsave() variant if we're racing with the irq
> handler?
>
> Will
I think meson_ddr_perf_event_update function is called with hard irq off.
So update function couldn't be interrupted by irq handler. Right?
Thanks,
Jiucheng
>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 2/3] perf/amlogic: Fix large number of counter issue
2023-03-28 2:29 ` Jiucheng Xu
(?)
@ 2023-03-28 11:55 ` Will Deacon
-1 siblings, 0 replies; 24+ messages in thread
From: Will Deacon @ 2023-03-28 11:55 UTC (permalink / raw)
To: Jiucheng Xu
Cc: Mark Rutland, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Jianxin Pan, Kelvin Zhang, Chris Healy,
Chris Healy, linux-amlogic, linux-arm-kernel, linux-kernel
On Tue, Mar 28, 2023 at 10:29:04AM +0800, Jiucheng Xu wrote:
>
> My Amlogic email box has some issues. Use my personal email
> <jiucheng.xu@163.com> to reply.
>
> On 2023/3/27 22:10, Will Deacon wrote:
> > [ EXTERNAL EMAIL ]
> >
> > On Thu, Feb 09, 2023 at 07:54:02PM +0800, Jiucheng Xu wrote:
> > > When use 1ms interval, very large number of counter happens
> > > once in a while as below:
> > >
> > > 25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> > > 26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> > > 26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> > >
> > > Root cause is the race between irq handler
> > > and pmu.read callback. Use spin lock to protect the sw&hw
> > > counters.
> > >
> > > Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
> > > ---
> > > drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++-
> > > 1 file changed, 9 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
> > > index 0b24dee1ed3c..9b2e5d5c0626 100644
> > > --- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
> > > +++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
> > > @@ -14,6 +14,7 @@
> > > #include <linux/perf_event.h>
> > > #include <linux/platform_device.h>
> > > #include <linux/printk.h>
> > > +#include <linux/spinlock.h>
> > > #include <linux/sysfs.h>
> > > #include <linux/types.h>
> > > @@ -23,6 +24,7 @@ struct ddr_pmu {
> > > struct pmu pmu;
> > > struct dmc_info info;
> > > struct dmc_counter counters; /* save counters from hw */
> > > + spinlock_t lock; /* protect hw/sw counter */
> > > bool pmu_enabled;
> > > struct device *dev;
> > > char *name;
> > > @@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event)
> > > int idx;
> > > int chann_nr = pmu->info.hw_info->chann_nr;
> > > + spin_lock(&pmu->lock);
> > Why doesn't this need the _irqsave() variant if we're racing with the irq
> > handler?
> >
> > Will
> I think meson_ddr_perf_event_update function is called with hard irq off.
> So update function couldn't be interrupted by irq handler. Right?
I'm just confused about the race, then. The commit message says you have a
race between an irq handler and a callback, which you fix with a spinlock
that isn't irq safe. So either the race is real and the lock needs to be
irqsafe, or the race is something else entirely, no?
Will
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 2/3] perf/amlogic: Fix large number of counter issue
@ 2023-03-28 11:55 ` Will Deacon
0 siblings, 0 replies; 24+ messages in thread
From: Will Deacon @ 2023-03-28 11:55 UTC (permalink / raw)
To: Jiucheng Xu
Cc: Mark Rutland, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Jianxin Pan, Kelvin Zhang, Chris Healy,
Chris Healy, linux-amlogic, linux-arm-kernel, linux-kernel
On Tue, Mar 28, 2023 at 10:29:04AM +0800, Jiucheng Xu wrote:
>
> My Amlogic email box has some issues. Use my personal email
> <jiucheng.xu@163.com> to reply.
>
> On 2023/3/27 22:10, Will Deacon wrote:
> > [ EXTERNAL EMAIL ]
> >
> > On Thu, Feb 09, 2023 at 07:54:02PM +0800, Jiucheng Xu wrote:
> > > When use 1ms interval, very large number of counter happens
> > > once in a while as below:
> > >
> > > 25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> > > 26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> > > 26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> > >
> > > Root cause is the race between irq handler
> > > and pmu.read callback. Use spin lock to protect the sw&hw
> > > counters.
> > >
> > > Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
> > > ---
> > > drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++-
> > > 1 file changed, 9 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
> > > index 0b24dee1ed3c..9b2e5d5c0626 100644
> > > --- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
> > > +++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
> > > @@ -14,6 +14,7 @@
> > > #include <linux/perf_event.h>
> > > #include <linux/platform_device.h>
> > > #include <linux/printk.h>
> > > +#include <linux/spinlock.h>
> > > #include <linux/sysfs.h>
> > > #include <linux/types.h>
> > > @@ -23,6 +24,7 @@ struct ddr_pmu {
> > > struct pmu pmu;
> > > struct dmc_info info;
> > > struct dmc_counter counters; /* save counters from hw */
> > > + spinlock_t lock; /* protect hw/sw counter */
> > > bool pmu_enabled;
> > > struct device *dev;
> > > char *name;
> > > @@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event)
> > > int idx;
> > > int chann_nr = pmu->info.hw_info->chann_nr;
> > > + spin_lock(&pmu->lock);
> > Why doesn't this need the _irqsave() variant if we're racing with the irq
> > handler?
> >
> > Will
> I think meson_ddr_perf_event_update function is called with hard irq off.
> So update function couldn't be interrupted by irq handler. Right?
I'm just confused about the race, then. The commit message says you have a
race between an irq handler and a callback, which you fix with a spinlock
that isn't irq safe. So either the race is real and the lock needs to be
irqsafe, or the race is something else entirely, no?
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 2/3] perf/amlogic: Fix large number of counter issue
@ 2023-03-28 11:55 ` Will Deacon
0 siblings, 0 replies; 24+ messages in thread
From: Will Deacon @ 2023-03-28 11:55 UTC (permalink / raw)
To: Jiucheng Xu
Cc: Mark Rutland, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Jianxin Pan, Kelvin Zhang, Chris Healy,
Chris Healy, linux-amlogic, linux-arm-kernel, linux-kernel
On Tue, Mar 28, 2023 at 10:29:04AM +0800, Jiucheng Xu wrote:
>
> My Amlogic email box has some issues. Use my personal email
> <jiucheng.xu@163.com> to reply.
>
> On 2023/3/27 22:10, Will Deacon wrote:
> > [ EXTERNAL EMAIL ]
> >
> > On Thu, Feb 09, 2023 at 07:54:02PM +0800, Jiucheng Xu wrote:
> > > When use 1ms interval, very large number of counter happens
> > > once in a while as below:
> > >
> > > 25.968654513 281474976710655.84 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> > > 26.118657346 281474976710655.88 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> > > 26.180137180 281474976710655.66 MB meson_ddr_bw/chan_1_rw_bytes,arm=1/
> > >
> > > Root cause is the race between irq handler
> > > and pmu.read callback. Use spin lock to protect the sw&hw
> > > counters.
> > >
> > > Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
> > > ---
> > > drivers/perf/amlogic/meson_ddr_pmu_core.c | 10 +++++++++-
> > > 1 file changed, 9 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/perf/amlogic/meson_ddr_pmu_core.c b/drivers/perf/amlogic/meson_ddr_pmu_core.c
> > > index 0b24dee1ed3c..9b2e5d5c0626 100644
> > > --- a/drivers/perf/amlogic/meson_ddr_pmu_core.c
> > > +++ b/drivers/perf/amlogic/meson_ddr_pmu_core.c
> > > @@ -14,6 +14,7 @@
> > > #include <linux/perf_event.h>
> > > #include <linux/platform_device.h>
> > > #include <linux/printk.h>
> > > +#include <linux/spinlock.h>
> > > #include <linux/sysfs.h>
> > > #include <linux/types.h>
> > > @@ -23,6 +24,7 @@ struct ddr_pmu {
> > > struct pmu pmu;
> > > struct dmc_info info;
> > > struct dmc_counter counters; /* save counters from hw */
> > > + spinlock_t lock; /* protect hw/sw counter */
> > > bool pmu_enabled;
> > > struct device *dev;
> > > char *name;
> > > @@ -92,10 +94,12 @@ static void meson_ddr_perf_event_update(struct perf_event *event)
> > > int idx;
> > > int chann_nr = pmu->info.hw_info->chann_nr;
> > > + spin_lock(&pmu->lock);
> > Why doesn't this need the _irqsave() variant if we're racing with the irq
> > handler?
> >
> > Will
> I think meson_ddr_perf_event_update function is called with hard irq off.
> So update function couldn't be interrupted by irq handler. Right?
I'm just confused about the race, then. The commit message says you have a
race between an irq handler and a callback, which you fix with a spinlock
that isn't irq safe. So either the race is real and the lock needs to be
irqsafe, or the race is something else entirely, no?
Will
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 3/3] arm64: defconfig: Add Meson DDR PMU as build-in
2023-02-09 11:54 ` Jiucheng Xu
(?)
@ 2023-02-09 11:54 ` Jiucheng Xu
-1 siblings, 0 replies; 24+ messages in thread
From: Jiucheng Xu @ 2023-02-09 11:54 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Jianxin Pan, Kelvin Zhang, Chris Healy, Chris Healy,
Neil Armstrong, linux-amlogic, Jiucheng Xu, linux-arm-kernel,
linux-kernel
Add Meson DDR PMU to defconfig so that build errors are caught.
Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 851e8f9be06d..9fefe659ade7 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1296,6 +1296,7 @@ CONFIG_ARM_DMC620_PMU=m
CONFIG_QCOM_L2_PMU=y
CONFIG_QCOM_L3_PMU=y
CONFIG_HISI_PMU=y
+CONFIG_MESON_DDR_PMU=y
CONFIG_NVMEM_IMX_OCOTP=y
CONFIG_NVMEM_IMX_OCOTP_SCU=y
CONFIG_NVMEM_MTK_EFUSE=y
--
2.25.1
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 3/3] arm64: defconfig: Add Meson DDR PMU as build-in
@ 2023-02-09 11:54 ` Jiucheng Xu
0 siblings, 0 replies; 24+ messages in thread
From: Jiucheng Xu @ 2023-02-09 11:54 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Jianxin Pan, Kelvin Zhang, Chris Healy, Chris Healy,
Neil Armstrong, linux-amlogic, Jiucheng Xu, linux-arm-kernel,
linux-kernel
Add Meson DDR PMU to defconfig so that build errors are caught.
Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 851e8f9be06d..9fefe659ade7 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1296,6 +1296,7 @@ CONFIG_ARM_DMC620_PMU=m
CONFIG_QCOM_L2_PMU=y
CONFIG_QCOM_L3_PMU=y
CONFIG_HISI_PMU=y
+CONFIG_MESON_DDR_PMU=y
CONFIG_NVMEM_IMX_OCOTP=y
CONFIG_NVMEM_IMX_OCOTP_SCU=y
CONFIG_NVMEM_MTK_EFUSE=y
--
2.25.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 3/3] arm64: defconfig: Add Meson DDR PMU as build-in
@ 2023-02-09 11:54 ` Jiucheng Xu
0 siblings, 0 replies; 24+ messages in thread
From: Jiucheng Xu @ 2023-02-09 11:54 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Jianxin Pan, Kelvin Zhang, Chris Healy, Chris Healy,
Neil Armstrong, linux-amlogic, Jiucheng Xu, linux-arm-kernel,
linux-kernel
Add Meson DDR PMU to defconfig so that build errors are caught.
Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 851e8f9be06d..9fefe659ade7 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1296,6 +1296,7 @@ CONFIG_ARM_DMC620_PMU=m
CONFIG_QCOM_L2_PMU=y
CONFIG_QCOM_L3_PMU=y
CONFIG_HISI_PMU=y
+CONFIG_MESON_DDR_PMU=y
CONFIG_NVMEM_IMX_OCOTP=y
CONFIG_NVMEM_IMX_OCOTP_SCU=y
CONFIG_NVMEM_MTK_EFUSE=y
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 3/3] arm64: defconfig: Add Meson DDR PMU as build-in
2023-02-09 11:54 ` Jiucheng Xu
(?)
@ 2023-02-10 15:58 ` Chris Healy
-1 siblings, 0 replies; 24+ messages in thread
From: Chris Healy @ 2023-02-10 15:58 UTC (permalink / raw)
To: Jiucheng Xu
Cc: Catalin Marinas, Will Deacon, Jianxin Pan, Kelvin Zhang,
Chris Healy, Neil Armstrong, linux-amlogic, linux-arm-kernel,
linux-kernel
Reviewed-by: Chris Healy <healych@amazon.com>
On Thu, Feb 9, 2023 at 3:54 AM Jiucheng Xu <jiucheng.xu@amlogic.com> wrote:
>
> Add Meson DDR PMU to defconfig so that build errors are caught.
>
> Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 851e8f9be06d..9fefe659ade7 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -1296,6 +1296,7 @@ CONFIG_ARM_DMC620_PMU=m
> CONFIG_QCOM_L2_PMU=y
> CONFIG_QCOM_L3_PMU=y
> CONFIG_HISI_PMU=y
> +CONFIG_MESON_DDR_PMU=y
> CONFIG_NVMEM_IMX_OCOTP=y
> CONFIG_NVMEM_IMX_OCOTP_SCU=y
> CONFIG_NVMEM_MTK_EFUSE=y
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/3] arm64: defconfig: Add Meson DDR PMU as build-in
@ 2023-02-10 15:58 ` Chris Healy
0 siblings, 0 replies; 24+ messages in thread
From: Chris Healy @ 2023-02-10 15:58 UTC (permalink / raw)
To: Jiucheng Xu
Cc: Catalin Marinas, Will Deacon, Jianxin Pan, Kelvin Zhang,
Chris Healy, Neil Armstrong, linux-amlogic, linux-arm-kernel,
linux-kernel
Reviewed-by: Chris Healy <healych@amazon.com>
On Thu, Feb 9, 2023 at 3:54 AM Jiucheng Xu <jiucheng.xu@amlogic.com> wrote:
>
> Add Meson DDR PMU to defconfig so that build errors are caught.
>
> Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 851e8f9be06d..9fefe659ade7 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -1296,6 +1296,7 @@ CONFIG_ARM_DMC620_PMU=m
> CONFIG_QCOM_L2_PMU=y
> CONFIG_QCOM_L3_PMU=y
> CONFIG_HISI_PMU=y
> +CONFIG_MESON_DDR_PMU=y
> CONFIG_NVMEM_IMX_OCOTP=y
> CONFIG_NVMEM_IMX_OCOTP_SCU=y
> CONFIG_NVMEM_MTK_EFUSE=y
> --
> 2.25.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 3/3] arm64: defconfig: Add Meson DDR PMU as build-in
@ 2023-02-10 15:58 ` Chris Healy
0 siblings, 0 replies; 24+ messages in thread
From: Chris Healy @ 2023-02-10 15:58 UTC (permalink / raw)
To: Jiucheng Xu
Cc: Catalin Marinas, Will Deacon, Jianxin Pan, Kelvin Zhang,
Chris Healy, Neil Armstrong, linux-amlogic, linux-arm-kernel,
linux-kernel
Reviewed-by: Chris Healy <healych@amazon.com>
On Thu, Feb 9, 2023 at 3:54 AM Jiucheng Xu <jiucheng.xu@amlogic.com> wrote:
>
> Add Meson DDR PMU to defconfig so that build errors are caught.
>
> Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 851e8f9be06d..9fefe659ade7 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -1296,6 +1296,7 @@ CONFIG_ARM_DMC620_PMU=m
> CONFIG_QCOM_L2_PMU=y
> CONFIG_QCOM_L3_PMU=y
> CONFIG_HISI_PMU=y
> +CONFIG_MESON_DDR_PMU=y
> CONFIG_NVMEM_IMX_OCOTP=y
> CONFIG_NVMEM_IMX_OCOTP_SCU=y
> CONFIG_NVMEM_MTK_EFUSE=y
> --
> 2.25.1
>
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/3] perf/amlogic: Fix config1/config2 parsing issue
2023-02-09 11:54 ` Jiucheng Xu
(?)
@ 2023-03-27 15:01 ` Will Deacon
-1 siblings, 0 replies; 24+ messages in thread
From: Will Deacon @ 2023-03-27 15:01 UTC (permalink / raw)
To: Mark Rutland, Martin Blumenstingl, Kevin Hilman, Jiucheng Xu,
Neil Armstrong, Jerome Brunet
Cc: catalin.marinas, kernel-team, Will Deacon, linux-amlogic,
Kelvin Zhang, Chris Healy, linux-arm-kernel, Jianxin Pan,
Chris Healy, linux-kernel
On Thu, 9 Feb 2023 19:54:01 +0800, Jiucheng Xu wrote:
> The 3th argument of for_each_set_bit is incorrect, fix them.
>
>
Applied first patch only to will (for-next/perf), thanks!
[1/3] perf/amlogic: Fix config1/config2 parsing issue
https://git.kernel.org/will/c/c61e5720f232
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 1/3] perf/amlogic: Fix config1/config2 parsing issue
@ 2023-03-27 15:01 ` Will Deacon
0 siblings, 0 replies; 24+ messages in thread
From: Will Deacon @ 2023-03-27 15:01 UTC (permalink / raw)
To: Mark Rutland, Martin Blumenstingl, Kevin Hilman, Jiucheng Xu,
Neil Armstrong, Jerome Brunet
Cc: catalin.marinas, kernel-team, Will Deacon, linux-amlogic,
Kelvin Zhang, Chris Healy, linux-arm-kernel, Jianxin Pan,
Chris Healy, linux-kernel
On Thu, 9 Feb 2023 19:54:01 +0800, Jiucheng Xu wrote:
> The 3th argument of for_each_set_bit is incorrect, fix them.
>
>
Applied first patch only to will (for-next/perf), thanks!
[1/3] perf/amlogic: Fix config1/config2 parsing issue
https://git.kernel.org/will/c/c61e5720f232
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH 1/3] perf/amlogic: Fix config1/config2 parsing issue
@ 2023-03-27 15:01 ` Will Deacon
0 siblings, 0 replies; 24+ messages in thread
From: Will Deacon @ 2023-03-27 15:01 UTC (permalink / raw)
To: Mark Rutland, Martin Blumenstingl, Kevin Hilman, Jiucheng Xu,
Neil Armstrong, Jerome Brunet
Cc: catalin.marinas, kernel-team, Will Deacon, linux-amlogic,
Kelvin Zhang, Chris Healy, linux-arm-kernel, Jianxin Pan,
Chris Healy, linux-kernel
On Thu, 9 Feb 2023 19:54:01 +0800, Jiucheng Xu wrote:
> The 3th argument of for_each_set_bit is incorrect, fix them.
>
>
Applied first patch only to will (for-next/perf), thanks!
[1/3] perf/amlogic: Fix config1/config2 parsing issue
https://git.kernel.org/will/c/c61e5720f232
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 24+ messages in thread