[PATCH 1/4] phy: phy-mtk-tphy: add support mt8195

[PATCH 1/4] phy: phy-mtk-tphy: add support mt8195

[Chunfeng Yun]

The T-PHY controller is designed to use use PLL integer mode, but
in fact use fractional mode for some ones on mt8195 by mistake,
this causes signal degradation (e.g. eye diagram test fail), fix
it by switching PLL to 26Mhz from default 48Mhz to improve signal
quality.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 drivers/phy/phy-mtk-tphy.c | 93 ++++++++++++++++++++++++++++++++++----
 1 file changed, 83 insertions(+), 10 deletions(-)

diff --git a/drivers/phy/phy-mtk-tphy.c b/drivers/phy/phy-mtk-tphy.c
index 2dd964f7b2..bdad0053d4 100644
--- a/drivers/phy/phy-mtk-tphy.c
+++ b/drivers/phy/phy-mtk-tphy.c
@@ -43,8 +43,14 @@
 
 #define U3P_USBPHYACR0			0x000
 #define PA0_RG_U2PLL_FORCE_ON		BIT(15)
+#define PA0_USB20_PLL_PREDIV		GENMASK(7, 6)
+#define PA0_USB20_PLL_PREDIV_VAL(x)	((0x3 & (x)) << 6)
 #define PA0_RG_USB20_INTR_EN		BIT(5)
 
+#define U3P_USBPHYACR2			0x008
+#define PA2_RG_U2PLL_BW			GENMASK(21, 19)
+#define PA2_RG_U2PLL_BW_VAL(x)		((0x7 & (x)) << 19)
+
 #define U3P_USBPHYACR5			0x014
 #define PA5_RG_U2_HSTX_SRCAL_EN		BIT(15)
 #define PA5_RG_U2_HSTX_SRCTRL		GENMASK(14, 12)
@@ -63,6 +69,14 @@
 #define P2C_U2_GPIO_CTR_MSK	\
 		(P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
 
+#define U3P_U2PHYA_RESV			0x030
+#define P2R_RG_U2PLL_FBDIV_26M		0x1bb13b
+#define P2R_RG_U2PLL_FBDIV_48M		0x3c0000
+
+#define U3P_U2PHYA_RESV1		0x044
+#define P2R_RG_U2PLL_REFCLK_SEL		BIT(5)
+#define P2R_RG_U2PLL_FRA_EN		BIT(3)
+
 #define U3P_U2PHYDTM0			0x068
 #define P2C_FORCE_UART_EN		BIT(26)
 #define P2C_FORCE_DATAIN		BIT(23)
@@ -239,6 +253,17 @@ enum mtk_phy_version {
 	MTK_TPHY_V2,
 };
 
+struct tphy_pdata {
+	enum mtk_phy_version version;
+
+	/*
+	 * workaround only for mt8195:
+	 * u2phy should use integer mode instead of fractional mode of
+	 * 48M PLL, fix it by switching PLL to 26M from default 48M
+	 */
+	bool sw_pll_48m_to_26m;
+};
+
 struct u2phy_banks {
 	void __iomem *misc;
 	void __iomem *fmreg;
@@ -269,11 +294,32 @@ struct mtk_phy_instance {
 struct mtk_tphy {
 	struct udevice *dev;
 	void __iomem *sif_base;
-	enum mtk_phy_version version;
+	const struct tphy_pdata *pdata;
 	struct mtk_phy_instance **phys;
 	int nphys;
 };
 
+/* workaround only for mt8195 */
+static void u2_phy_pll_26m_set(struct mtk_tphy *tphy,
+			       struct mtk_phy_instance *instance)
+{
+	struct u2phy_banks *u2_banks = &instance->u2_banks;
+
+	if (!tphy->pdata->sw_pll_48m_to_26m)
+		return;
+
+	clrsetbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV,
+			PA0_USB20_PLL_PREDIV_VAL(0));
+
+	clrsetbits_le32(u2_banks->com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW,
+			PA2_RG_U2PLL_BW_VAL(3));
+
+	writel(P2R_RG_U2PLL_FBDIV_26M, u2_banks->com + U3P_U2PHYA_RESV);
+
+	setbits_le32(u2_banks->com + U3P_U2PHYA_RESV1,
+		     P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL);
+}
+
 static void u2_phy_instance_init(struct mtk_tphy *tphy,
 				 struct mtk_phy_instance *instance)
 {
@@ -301,6 +347,8 @@ static void u2_phy_instance_init(struct mtk_tphy *tphy,
 	clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5,
 			PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
 
+	u2_phy_pll_26m_set(tphy, instance);
+
 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 }
 
@@ -382,7 +430,7 @@ static void pcie_phy_instance_init(struct mtk_tphy *tphy,
 {
 	struct u3phy_banks *u3_banks = &instance->u3_banks;
 
-	if (tphy->version != MTK_TPHY_V1)
+	if (tphy->pdata->version != MTK_TPHY_V1)
 		return;
 
 	clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
@@ -662,11 +710,14 @@ static int mtk_phy_xlate(struct phy *phy,
 		return -EINVAL;
 	}
 
-	if (tphy->version == MTK_TPHY_V1) {
+	switch (tphy->pdata->version) {
+	case MTK_TPHY_V1:
 		phy_v1_banks_init(tphy, instance);
-	} else if (tphy->version == MTK_TPHY_V2) {
+		break;
+	case MTK_TPHY_V2:
 		phy_v2_banks_init(tphy, instance);
-	} else {
+		break;
+	default:
 		dev_err(phy->dev, "phy version is not supported\n");
 		return -EINVAL;
 	}
@@ -696,13 +747,12 @@ static int mtk_tphy_probe(struct udevice *dev)
 		return -ENOMEM;
 
 	tphy->dev = dev;
-	tphy->version = dev_get_driver_data(dev);
+	tphy->pdata = (void *)dev_get_driver_data(dev);
 
 	/* v1 has shared banks for usb/pcie mode, */
 	/* but not for sata mode */
-	if (tphy->version == MTK_TPHY_V1) {
+	if (tphy->pdata->version == MTK_TPHY_V1)
 		tphy->sif_base = dev_read_addr_ptr(dev);
-	}
 
 	dev_for_each_subnode(subnode, dev) {
 		struct mtk_phy_instance *instance;
@@ -737,9 +787,32 @@ static int mtk_tphy_probe(struct udevice *dev)
 	return 0;
 }
 
+static struct tphy_pdata tphy_v1_pdata = {
+	.version = MTK_TPHY_V1,
+};
+
+static struct tphy_pdata tphy_v2_pdata = {
+	.version = MTK_TPHY_V2,
+};
+
+static struct tphy_pdata mt8195_pdata = {
+	.version = MTK_TPHY_V2,
+	.sw_pll_48m_to_26m = true,
+};
+
 static const struct udevice_id mtk_tphy_id_table[] = {
-	{ .compatible = "mediatek,generic-tphy-v1", .data = MTK_TPHY_V1, },
-	{ .compatible = "mediatek,generic-tphy-v2", .data = MTK_TPHY_V2, },
+	{
+		.compatible = "mediatek,generic-tphy-v1",
+		.data = (ulong)&tphy_v1_pdata,
+	},
+	{
+		.compatible = "mediatek,generic-tphy-v2",
+		.data = (ulong)&tphy_v2_pdata,
+	},
+	{
+		.compatible = "mediatek,mt8195-tphy",
+		.data = (ulong)&mt8195_pdata,
+	},
 	{ }
 };
 
-- 
2.18.0

[PATCH 2/4] usb: xhci-mtk: modify the SOF/ITP interval for mt8195

[Chunfeng Yun]

There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
exclude IP0) have a wrong default SOF/ITP interval which is
calculated from the frame counter clock 24Mhz by default, but
in fact, the frame counter clock is 48Mhz, so we shall set the
accurate interval according to 48Mhz for those controllers.

Note:
The first controller no need set it, but if set it, shall change
tphy's pll at the same time.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 drivers/usb/host/xhci-mtk.c | 47 +++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 3838a990ec..46f8039960 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -50,6 +50,27 @@
 #define IPPC_U3_CTRL(p)	(IPPC_U3_CTRL_0P + ((p) * 0x08))
 #define IPPC_U2_CTRL(p)	(IPPC_U2_CTRL_0P + ((p) * 0x08))
 
+/* xHCI CSR */
+#define LS_EOF_CFG		0x930
+#define LSEOF_OFFSET		0x89
+
+#define FS_EOF_CFG		0x934
+#define FSEOF_OFFSET		0x2e
+
+#define SS_GEN1_EOF_CFG		0x93c
+#define SSG1EOF_OFFSET		0x78
+
+#define HFCNTR_CFG		0x944
+#define ITP_DELTA_CLK		(0xa << 1)
+#define ITP_DELTA_CLK_MASK	GENMASK(5, 1)
+#define FRMCNT_LEV1_RANG	(0x12b << 8)
+#define FRMCNT_LEV1_RANG_MASK	GENMASK(19, 8)
+
+#define SS_GEN2_EOF_CFG		0x990
+#define SSG2EOF_OFFSET		0x3c
+
+#define XSEOF_OFFSET_MASK	GENMASK(11, 0)
+
 struct mtk_xhci {
 	struct xhci_ctrl ctrl;	/* Needs to come first in this struct! */
 	struct xhci_hccr *hcd;
@@ -65,6 +86,29 @@ struct mtk_xhci {
 	u32 u2p_dis_msk;
 };
 
+/*
+ * workaround for mt8195:
+ * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
+ * is calculated from the frame counter clock 24M, but in fact, the clock
+ * is 48M.
+ */
+static void xhci_mtk_set_frame_interval(struct mtk_xhci *mtk)
+{
+	void __iomem *mac = (void __iomem *)mtk->hcd;
+
+	if (!ofnode_device_is_compatible(dev_ofnode(mtk->dev), "mediatek,mt8195-xhci"))
+		return;
+
+	clrsetbits_le32(mac + HFCNTR_CFG,
+			ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK,
+			ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
+
+	clrsetbits_le32(mac + LS_EOF_CFG, XSEOF_OFFSET_MASK, LSEOF_OFFSET);
+	clrsetbits_le32(mac + FS_EOF_CFG, XSEOF_OFFSET_MASK, FSEOF_OFFSET);
+	clrsetbits_le32(mac + SS_GEN1_EOF_CFG, XSEOF_OFFSET_MASK, SSG1EOF_OFFSET);
+	clrsetbits_le32(mac + SS_GEN2_EOF_CFG, XSEOF_OFFSET_MASK, SSG2EOF_OFFSET);
+}
+
 static int xhci_mtk_host_enable(struct mtk_xhci *mtk)
 {
 	int u3_ports_disabed = 0;
@@ -278,6 +322,8 @@ static int xhci_mtk_probe(struct udevice *dev)
 	if (ret)
 		goto ssusb_init_err;
 
+	xhci_mtk_set_frame_interval(mtk);
+
 	mtk->ctrl.quirks = XHCI_MTK_HOST;
 	hcor = (struct xhci_hcor *)((uintptr_t)mtk->hcd +
 			HC_LENGTH(xhci_readl(&mtk->hcd->cr_capbase)));
@@ -308,6 +354,7 @@ static int xhci_mtk_remove(struct udevice *dev)
 
 static const struct udevice_id xhci_mtk_ids[] = {
 	{ .compatible = "mediatek,mtk-xhci" },
+	{ .compatible = "mediatek,mt8195-xhci" },
 	{ }
 };
 
-- 
2.18.0

[PATCH 3/4] dt-bindings: phy-mtk-tphy: add support mt8195

[Chunfeng Yun]

Add a new compatible for mt8195 to add a workaround for hardware
issue.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 doc/device-tree-bindings/phy/phy-mtk-tphy.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/doc/device-tree-bindings/phy/phy-mtk-tphy.txt b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt
index 8cd23d8c0b..3042c39d09 100644
--- a/doc/device-tree-bindings/phy/phy-mtk-tphy.txt
+++ b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt
@@ -8,6 +8,7 @@ Required properties (controller (parent) node):
  - compatible	: should be one of
 		  "mediatek,generic-tphy-v1"
 		  "mediatek,generic-tphy-v2"
+		  "mediatek,mt8195-tphy"
 
 - #address-cells:	the number of cells used to represent physical
 		base addresses.
-- 
2.18.0

[PATCH 4/4] dt-bindings: usb: mtk-xhci: add support mt8195

[Chunfeng Yun]

Add a new compatible for mt8195 to add a workaround for hardware
issue.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 doc/device-tree-bindings/usb/mediatek,mtk-xhci.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/doc/device-tree-bindings/usb/mediatek,mtk-xhci.txt b/doc/device-tree-bindings/usb/mediatek,mtk-xhci.txt
index 2a298f7b16..e26e9618eb 100644
--- a/doc/device-tree-bindings/usb/mediatek,mtk-xhci.txt
+++ b/doc/device-tree-bindings/usb/mediatek,mtk-xhci.txt
@@ -3,7 +3,9 @@ MediaTek xHCI
 The device node for USB3 host controller on MediaTek SoCs.
 
 Required properties:
- - compatible : should be "mediatek,mtk-xhci"
+ - compatible : should be one of
+	"mediatek,mtk-xhci"
+	"mediatek,mt8195-xhci"
  - reg : specifies physical base address and size of the registers
  - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
  - power-domains : a phandle to USB power domain node to control USB's
-- 
2.18.0

Re: [PATCH 2/4] usb: xhci-mtk: modify the SOF/ITP interval for mt8195

[Marek Vasut]

On 2/10/23 09:33, Chunfeng Yun wrote:
[...]
> @@ -50,6 +50,27 @@
>   #define IPPC_U3_CTRL(p)	(IPPC_U3_CTRL_0P + ((p) * 0x08))
>   #define IPPC_U2_CTRL(p)	(IPPC_U2_CTRL_0P + ((p) * 0x08))
>   
> +/* xHCI CSR */
> +#define LS_EOF_CFG		0x930
> +#define LSEOF_OFFSET		0x89
> +
> +#define FS_EOF_CFG		0x934
> +#define FSEOF_OFFSET		0x2e
> +
> +#define SS_GEN1_EOF_CFG		0x93c
> +#define SSG1EOF_OFFSET		0x78
> +
> +#define HFCNTR_CFG		0x944
> +#define ITP_DELTA_CLK		(0xa << 1)
> +#define ITP_DELTA_CLK_MASK	GENMASK(5, 1)
> +#define FRMCNT_LEV1_RANG	(0x12b << 8)

Look at FIELD_PREP() macro, that should let you avoid the (0x12b << 8) .

> +#define FRMCNT_LEV1_RANG_MASK	GENMASK(19, 8)
> +
> +#define SS_GEN2_EOF_CFG		0x990
> +#define SSG2EOF_OFFSET		0x3c
> +
> +#define XSEOF_OFFSET_MASK	GENMASK(11, 0)

[...]

> @@ -308,6 +354,7 @@ static int xhci_mtk_remove(struct udevice *dev)
>   
>   static const struct udevice_id xhci_mtk_ids[] = {
>   	{ .compatible = "mediatek,mtk-xhci" },
> +	{ .compatible = "mediatek,mt8195-xhci" },

Is the extra compatible string really needed, can't the driver match on 
the generic one ?

Re: [PATCH 2/4] usb: xhci-mtk: modify the SOF/ITP interval for mt8195

[Chunfeng Yun (云春峰)]

On Fri, 2023-02-10 at 11:32 +0100, Marek Vasut wrote:
> On 2/10/23 09:33, Chunfeng Yun wrote:
> [...]
> > @@ -50,6 +50,27 @@
> >   #define IPPC_U3_CTRL(p)	(IPPC_U3_CTRL_0P + ((p) * 0x08))
> >   #define IPPC_U2_CTRL(p)	(IPPC_U2_CTRL_0P + ((p) * 0x08))
> >   
> > +/* xHCI CSR */
> > +#define LS_EOF_CFG		0x930
> > +#define LSEOF_OFFSET		0x89
> > +
> > +#define FS_EOF_CFG		0x934
> > +#define FSEOF_OFFSET		0x2e
> > +
> > +#define SS_GEN1_EOF_CFG		0x93c
> > +#define SSG1EOF_OFFSET		0x78
> > +
> > +#define HFCNTR_CFG		0x944
> > +#define ITP_DELTA_CLK		(0xa << 1)
> > +#define ITP_DELTA_CLK_MASK	GENMASK(5, 1)
> > +#define FRMCNT_LEV1_RANG	(0x12b << 8)
> 
> Look at FIELD_PREP() macro, that should let you avoid the (0x12b <<
> 8) .
Seems not use FIELD_PREP() macro here.
It's not a mask, it's the value set in below mask
FRMCNT_LEV1_RANG_MASK.

> 
> > +#define FRMCNT_LEV1_RANG_MASK	GENMASK(19, 8)
> > +
> > +#define SS_GEN2_EOF_CFG		0x990
> > +#define SSG2EOF_OFFSET		0x3c
> > +
> > +#define XSEOF_OFFSET_MASK	GENMASK(11, 0)
> 
> [...]
> 
> > @@ -308,6 +354,7 @@ static int xhci_mtk_remove(struct udevice *dev)
> >   
> >   static const struct udevice_id xhci_mtk_ids[] = {
> >   	{ .compatible = "mediatek,mtk-xhci" },
> > +	{ .compatible = "mediatek,mt8195-xhci" },
> 
> Is the extra compatible string really needed, can't the driver match
> on 
> the generic one ?
These settings are a workaround only for mt8195 to fix HW issue, can't
use generic compatible.

Thanks a lot

Re: [PATCH 2/4] usb: xhci-mtk: modify the SOF/ITP interval for mt8195

[Marek Vasut]

On 2/13/23 02:46, Chunfeng Yun (云春峰) wrote:
> On Fri, 2023-02-10 at 11:32 +0100, Marek Vasut wrote:
>> On 2/10/23 09:33, Chunfeng Yun wrote:
>> [...]
>>> @@ -50,6 +50,27 @@
>>>    #define IPPC_U3_CTRL(p)	(IPPC_U3_CTRL_0P + ((p) * 0x08))
>>>    #define IPPC_U2_CTRL(p)	(IPPC_U2_CTRL_0P + ((p) * 0x08))
>>>    
>>> +/* xHCI CSR */
>>> +#define LS_EOF_CFG		0x930
>>> +#define LSEOF_OFFSET		0x89
>>> +
>>> +#define FS_EOF_CFG		0x934
>>> +#define FSEOF_OFFSET		0x2e
>>> +
>>> +#define SS_GEN1_EOF_CFG		0x93c
>>> +#define SSG1EOF_OFFSET		0x78
>>> +
>>> +#define HFCNTR_CFG		0x944
>>> +#define ITP_DELTA_CLK		(0xa << 1)
>>> +#define ITP_DELTA_CLK_MASK	GENMASK(5, 1)
>>> +#define FRMCNT_LEV1_RANG	(0x12b << 8)
>>
>> Look at FIELD_PREP() macro, that should let you avoid the (0x12b <<
>> 8) .
> Seems not use FIELD_PREP() macro here.
> It's not a mask, it's the value set in below mask
> FRMCNT_LEV1_RANG_MASK.

So that would be

FIELD_PREP(FRMCNT_LEV1_RANG_MASK, 0x12b)

I think ?

>>> +#define FRMCNT_LEV1_RANG_MASK	GENMASK(19, 8)
>>> +
>>> +#define SS_GEN2_EOF_CFG		0x990
>>> +#define SSG2EOF_OFFSET		0x3c
>>> +
>>> +#define XSEOF_OFFSET_MASK	GENMASK(11, 0)
>>
>> [...]
>>
>>> @@ -308,6 +354,7 @@ static int xhci_mtk_remove(struct udevice *dev)
>>>    
>>>    static const struct udevice_id xhci_mtk_ids[] = {
>>>    	{ .compatible = "mediatek,mtk-xhci" },
>>> +	{ .compatible = "mediatek,mt8195-xhci" },
>>
>> Is the extra compatible string really needed, can't the driver match
>> on
>> the generic one ?
> These settings are a workaround only for mt8195 to fix HW issue, can't
> use generic compatible.

Ah, I see, OK

Re: [PATCH 2/4] usb: xhci-mtk: modify the SOF/ITP interval for mt8195

[Chunfeng Yun (云春峰)]

On Mon, 2023-02-13 at 22:00 +0100, Marek Vasut wrote:
> On 2/13/23 02:46, Chunfeng Yun (云春峰) wrote:
> > On Fri, 2023-02-10 at 11:32 +0100, Marek Vasut wrote:
> > > On 2/10/23 09:33, Chunfeng Yun wrote:
> > > [...]
> > > > @@ -50,6 +50,27 @@
> > > >    #define IPPC_U3_CTRL(p)	(IPPC_U3_CTRL_0P + ((p) *
> > > > 0x08))
> > > >    #define IPPC_U2_CTRL(p)	(IPPC_U2_CTRL_0P + ((p) *
> > > > 0x08))
> > > >    
> > > > +/* xHCI CSR */
> > > > +#define LS_EOF_CFG		0x930
> > > > +#define LSEOF_OFFSET		0x89
> > > > +
> > > > +#define FS_EOF_CFG		0x934
> > > > +#define FSEOF_OFFSET		0x2e
> > > > +
> > > > +#define SS_GEN1_EOF_CFG		0x93c
> > > > +#define SSG1EOF_OFFSET		0x78
> > > > +
> > > > +#define HFCNTR_CFG		0x944
> > > > +#define ITP_DELTA_CLK		(0xa << 1)
> > > > +#define ITP_DELTA_CLK_MASK	GENMASK(5, 1)
> > > > +#define FRMCNT_LEV1_RANG	(0x12b << 8)
> > > 
> > > Look at FIELD_PREP() macro, that should let you avoid the (0x12b
> > > <<
> > > 8) .
Sorry, misunderstood you

> > 
> > Seems not use FIELD_PREP() macro here.
> > It's not a mask, it's the value set in below mask
> > FRMCNT_LEV1_RANG_MASK.
> 
> So that would be
> 
> FIELD_PREP(FRMCNT_LEV1_RANG_MASK, 0x12b)
> 
> I think ?
Sure, I'll use it instead

Thanks a lot

> 
> > > > +#define FRMCNT_LEV1_RANG_MASK	GENMASK(19, 8)
> > > > +
> > > > +#define SS_GEN2_EOF_CFG		0x990
> > > > +#define SSG2EOF_OFFSET		0x3c
> > > > +
> > > > +#define XSEOF_OFFSET_MASK	GENMASK(11, 0)
> > > 
> > > [...]
> > > 
> > > > @@ -308,6 +354,7 @@ static int xhci_mtk_remove(struct udevice
> > > > *dev)
> > > >    
> > > >    static const struct udevice_id xhci_mtk_ids[] = {
> > > >    	{ .compatible = "mediatek,mtk-xhci" },
> > > > +	{ .compatible = "mediatek,mt8195-xhci" },
> > > 
> > > Is the extra compatible string really needed, can't the driver
> > > match
> > > on
> > > the generic one ?
> > 
> > These settings are a workaround only for mt8195 to fix HW issue,
> > can't
> > use generic compatible.
> 
> Ah, I see, OK