All of lore.kernel.org
 help / color / mirror / Atom feed
From: Raghavendra Rao Ananta <rananta@google.com>
To: Oliver Upton <oupton@google.com>,
	Reiji Watanabe <reijiw@google.com>, Marc Zyngier <maz@kernel.org>,
	Ricardo Koller <ricarkol@google.com>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Jing Zhang <jingzhangos@google.com>,
	Colton Lewis <coltonlewis@google.com>,
	Raghavendra Rao Anata <rananta@google.com>,
	linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
	linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: [REPOST PATCH 06/16] tools: arm64: perf_event: Define Cycle counter enable/overflow bits
Date: Wed, 15 Feb 2023 01:07:07 +0000	[thread overview]
Message-ID: <20230215010717.3612794-7-rananta@google.com> (raw)
In-Reply-To: <20230215010717.3612794-1-rananta@google.com>

Add the definitions of ARMV8_PMU_CNTOVS_C (Cycle counter overflow
bit) for overflow status registers and ARMV8_PMU_CNTENSET_C (Cycle
counter enable bit) for PMCNTENSET_EL0 register.

Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
---
 tools/arch/arm64/include/asm/perf_event.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/tools/arch/arm64/include/asm/perf_event.h b/tools/arch/arm64/include/asm/perf_event.h
index 97e49a4d4969f..8ce23aabf6fe6 100644
--- a/tools/arch/arm64/include/asm/perf_event.h
+++ b/tools/arch/arm64/include/asm/perf_event.h
@@ -222,9 +222,11 @@
 /*
  * PMOVSR: counters overflow flag status reg
  */
+#define ARMV8_PMU_CNTOVS_C      (1 << 31) /* Cycle counter overflow bit */
 #define	ARMV8_PMU_OVSR_MASK		0xffffffff	/* Mask for writable bits */
 #define	ARMV8_PMU_OVERFLOWED_MASK	ARMV8_PMU_OVSR_MASK
 
+
 /*
  * PMXEVTYPER: Event selection reg
  */
@@ -247,6 +249,11 @@
 #define ARMV8_PMU_USERENR_CR	(1 << 2) /* Cycle counter can be read at EL0 */
 #define ARMV8_PMU_USERENR_ER	(1 << 3) /* Event counter can be read at EL0 */
 
+/*
+ * PMCNTENSET: Count Enable set reg
+ */
+#define ARMV8_PMU_CNTENSET_C    (1 << 31) /* Cycle counter enable bit */
+
 /* PMMIR_EL1.SLOTS mask */
 #define ARMV8_PMU_SLOTS_MASK	0xff
 
-- 
2.39.1.581.gbfd45094c4-goog


WARNING: multiple messages have this Message-ID (diff)
From: Raghavendra Rao Ananta <rananta@google.com>
To: Oliver Upton <oupton@google.com>,
	Reiji Watanabe <reijiw@google.com>, Marc Zyngier <maz@kernel.org>,
	 Ricardo Koller <ricarkol@google.com>,
	James Morse <james.morse@arm.com>,
	 Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Jing Zhang <jingzhangos@google.com>,
	 Colton Lewis <coltonlewis@google.com>,
	Raghavendra Rao Anata <rananta@google.com>,
	 linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
	 linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: [REPOST PATCH 06/16] tools: arm64: perf_event: Define Cycle counter enable/overflow bits
Date: Wed, 15 Feb 2023 01:07:07 +0000	[thread overview]
Message-ID: <20230215010717.3612794-7-rananta@google.com> (raw)
In-Reply-To: <20230215010717.3612794-1-rananta@google.com>

Add the definitions of ARMV8_PMU_CNTOVS_C (Cycle counter overflow
bit) for overflow status registers and ARMV8_PMU_CNTENSET_C (Cycle
counter enable bit) for PMCNTENSET_EL0 register.

Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
---
 tools/arch/arm64/include/asm/perf_event.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/tools/arch/arm64/include/asm/perf_event.h b/tools/arch/arm64/include/asm/perf_event.h
index 97e49a4d4969f..8ce23aabf6fe6 100644
--- a/tools/arch/arm64/include/asm/perf_event.h
+++ b/tools/arch/arm64/include/asm/perf_event.h
@@ -222,9 +222,11 @@
 /*
  * PMOVSR: counters overflow flag status reg
  */
+#define ARMV8_PMU_CNTOVS_C      (1 << 31) /* Cycle counter overflow bit */
 #define	ARMV8_PMU_OVSR_MASK		0xffffffff	/* Mask for writable bits */
 #define	ARMV8_PMU_OVERFLOWED_MASK	ARMV8_PMU_OVSR_MASK
 
+
 /*
  * PMXEVTYPER: Event selection reg
  */
@@ -247,6 +249,11 @@
 #define ARMV8_PMU_USERENR_CR	(1 << 2) /* Cycle counter can be read at EL0 */
 #define ARMV8_PMU_USERENR_ER	(1 << 3) /* Event counter can be read at EL0 */
 
+/*
+ * PMCNTENSET: Count Enable set reg
+ */
+#define ARMV8_PMU_CNTENSET_C    (1 << 31) /* Cycle counter enable bit */
+
 /* PMMIR_EL1.SLOTS mask */
 #define ARMV8_PMU_SLOTS_MASK	0xff
 
-- 
2.39.1.581.gbfd45094c4-goog


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2023-02-15  1:07 UTC|newest]

Thread overview: 72+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-15  1:07 [REPOST PATCH 00/16] Add support for vPMU selftests Raghavendra Rao Ananta
2023-02-15  1:07 ` Raghavendra Rao Ananta
2023-02-15  1:07 ` [REPOST PATCH 01/16] tools: arm64: Import perf_event.h Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-02-15  1:07 ` [REPOST PATCH 02/16] KVM: selftests: aarch64: Introduce vpmu_counter_access test Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-02-15  1:07 ` [REPOST PATCH 03/16] KVM: selftests: aarch64: vPMU register test for implemented counters Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-02-15  1:07 ` [REPOST PATCH 04/16] KVM: selftests: aarch64: vPMU register test for unimplemented counters Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-02-15  1:07 ` [REPOST PATCH 05/16] selftests: KVM: aarch64: Refactor the vPMU counter access tests Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-02-15  1:07 ` Raghavendra Rao Ananta [this message]
2023-02-15  1:07   ` [REPOST PATCH 06/16] tools: arm64: perf_event: Define Cycle counter enable/overflow bits Raghavendra Rao Ananta
2023-03-03  0:46   ` Reiji Watanabe
2023-03-03  0:46     ` Reiji Watanabe
2023-03-09 22:14     ` Raghavendra Rao Ananta
2023-03-09 22:14       ` Raghavendra Rao Ananta
2023-02-15  1:07 ` [REPOST PATCH 07/16] selftests: KVM: aarch64: Add PMU cycle counter helpers Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-03-03  3:06   ` Reiji Watanabe
2023-03-03  3:06     ` Reiji Watanabe
2023-03-09 22:19     ` Raghavendra Rao Ananta
2023-03-09 22:19       ` Raghavendra Rao Ananta
2023-02-15  1:07 ` [REPOST PATCH 08/16] selftests: KVM: aarch64: Consider PMU event filters for VM creation Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-03-03  4:30   ` Reiji Watanabe
2023-03-03  4:30     ` Reiji Watanabe
2023-03-09 22:45     ` Raghavendra Rao Ananta
2023-03-09 22:45       ` Raghavendra Rao Ananta
2023-02-15  1:07 ` [REPOST PATCH 09/16] selftests: KVM: aarch64: Add KVM PMU event filter test Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-03-04 20:28   ` Reiji Watanabe
2023-03-04 20:28     ` Reiji Watanabe
2023-03-09 23:17     ` Raghavendra Rao Ananta
2023-03-09 23:17       ` Raghavendra Rao Ananta
2023-02-15  1:07 ` [REPOST PATCH 10/16] selftests: KVM: aarch64: Add KVM EVTYPE filter PMU test Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-03-07  1:19   ` Reiji Watanabe
2023-03-07  1:19     ` Reiji Watanabe
2023-03-07 16:09     ` Sean Christopherson
2023-03-07 16:09       ` Sean Christopherson
2023-03-10 21:57     ` Raghavendra Rao Ananta
2023-03-10 21:57       ` Raghavendra Rao Ananta
2023-02-15  1:07 ` [REPOST PATCH 11/16] selftests: KVM: aarch64: Add vCPU migration test for PMU Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-03-07  3:43   ` Reiji Watanabe
2023-03-07  3:43     ` Reiji Watanabe
2023-03-10  2:28     ` Raghavendra Rao Ananta
2023-03-10  2:28       ` Raghavendra Rao Ananta
2023-02-15  1:07 ` [REPOST PATCH 12/16] selftests: KVM: aarch64: Test PMU overflow/IRQ functionality Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-03-07  6:09   ` Reiji Watanabe
2023-03-07  6:09     ` Reiji Watanabe
2023-03-08  1:19     ` Reiji Watanabe
2023-03-08  1:19       ` Reiji Watanabe
2023-03-10 23:58     ` Raghavendra Rao Ananta
2023-03-10 23:58       ` Raghavendra Rao Ananta
2023-02-15  1:07 ` [REPOST PATCH 13/16] selftests: KVM: aarch64: Test chained events for PMU Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-03-08  3:15   ` Reiji Watanabe
2023-03-08  3:15     ` Reiji Watanabe
2023-02-15  1:07 ` [REPOST PATCH 14/16] selftests: KVM: aarch64: Add PMU test to chain all the counters Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-03-08  3:40   ` Reiji Watanabe
2023-03-08  3:40     ` Reiji Watanabe
2023-02-15  1:07 ` [REPOST PATCH 15/16] selftests: KVM: aarch64: Add multi-vCPU support for vPMU VM creation Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-02-15  1:07 ` [REPOST PATCH 16/16] selftests: KVM: aarch64: Extend the vCPU migration test to multi-vCPUs Raghavendra Rao Ananta
2023-02-15  1:07   ` Raghavendra Rao Ananta
2023-03-08  4:44   ` Reiji Watanabe
2023-03-08  4:44     ` Reiji Watanabe

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230215010717.3612794-7-rananta@google.com \
    --to=rananta@google.com \
    --cc=coltonlewis@google.com \
    --cc=james.morse@arm.com \
    --cc=jingzhangos@google.com \
    --cc=kvm@vger.kernel.org \
    --cc=kvmarm@lists.linux.dev \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=maz@kernel.org \
    --cc=oupton@google.com \
    --cc=pbonzini@redhat.com \
    --cc=reijiw@google.com \
    --cc=ricarkol@google.com \
    --cc=suzuki.poulose@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.