* [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch]
@ 2023-02-15 14:19 Jani Nikula
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 2/5] drm/i915/wm: warn about ilk_wm_sanitize() on display ver 9+ Jani Nikula
` (7 more replies)
0 siblings, 8 replies; 12+ messages in thread
From: Jani Nikula @ 2023-02-15 14:19 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Move sanitize_watermarks() to i9xx_wm.[ch] and rename as
ilk_wm_sanitize(). The slightly unfortunate downside is having to expose
intel_atomic_check() from intel_display.c, but this declutters
intel_display.c nicely.
v2:
- Move to i9xx_wm.[ch] instead of intel_wm.[ch] (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 119 ++++++++++++++++++
drivers/gpu/drm/i915/display/i9xx_wm.h | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 124 +------------------
drivers/gpu/drm/i915/display/intel_display.h | 2 +
4 files changed, 125 insertions(+), 121 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index dfdd40991871..f76ac64ebd71 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -5,6 +5,7 @@
#include "i915_drv.h"
#include "i9xx_wm.h"
+#include "intel_atomic.h"
#include "intel_display.h"
#include "intel_display_trace.h"
#include "intel_mchbar_regs.h"
@@ -3380,6 +3381,124 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
crtc->wm.active.ilk = *active;
}
+static int ilk_sanitize_watermarks_add_affected(struct drm_atomic_state *state)
+{
+ struct drm_plane *plane;
+ struct intel_crtc *crtc;
+
+ for_each_intel_crtc(state->dev, crtc) {
+ struct intel_crtc_state *crtc_state;
+
+ crtc_state = intel_atomic_get_crtc_state(state, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
+ if (crtc_state->hw.active) {
+ /*
+ * Preserve the inherited flag to avoid
+ * taking the full modeset path.
+ */
+ crtc_state->inherited = true;
+ }
+ }
+
+ drm_for_each_plane(plane, state->dev) {
+ struct drm_plane_state *plane_state;
+
+ plane_state = drm_atomic_get_plane_state(state, plane);
+ if (IS_ERR(plane_state))
+ return PTR_ERR(plane_state);
+ }
+
+ return 0;
+}
+
+/*
+ * Calculate what we think the watermarks should be for the state we've read
+ * out of the hardware and then immediately program those watermarks so that
+ * we ensure the hardware settings match our internal state.
+ *
+ * We can calculate what we think WM's should be by creating a duplicate of the
+ * current state (which was constructed during hardware readout) and running it
+ * through the atomic check code to calculate new watermark values in the
+ * state object.
+ */
+void ilk_wm_sanitize(struct drm_i915_private *dev_priv)
+{
+ struct drm_atomic_state *state;
+ struct intel_atomic_state *intel_state;
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret;
+ int i;
+
+ /* Only supported on platforms that use atomic watermark design */
+ if (!dev_priv->display.funcs.wm->optimize_watermarks)
+ return;
+
+ state = drm_atomic_state_alloc(&dev_priv->drm);
+ if (drm_WARN_ON(&dev_priv->drm, !state))
+ return;
+
+ intel_state = to_intel_atomic_state(state);
+
+ drm_modeset_acquire_init(&ctx, 0);
+
+retry:
+ state->acquire_ctx = &ctx;
+
+ /*
+ * Hardware readout is the only time we don't want to calculate
+ * intermediate watermarks (since we don't trust the current
+ * watermarks).
+ */
+ if (!HAS_GMCH(dev_priv))
+ intel_state->skip_intermediate_wm = true;
+
+ ret = ilk_sanitize_watermarks_add_affected(state);
+ if (ret)
+ goto fail;
+
+ ret = intel_atomic_check(&dev_priv->drm, state);
+ if (ret)
+ goto fail;
+
+ /* Write calculated watermark values back */
+ for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
+ crtc_state->wm.need_postvbl_update = true;
+ intel_optimize_watermarks(intel_state, crtc);
+
+ to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
+ }
+
+fail:
+ if (ret == -EDEADLK) {
+ drm_atomic_state_clear(state);
+ drm_modeset_backoff(&ctx);
+ goto retry;
+ }
+
+ /*
+ * If we fail here, it means that the hardware appears to be
+ * programmed in a way that shouldn't be possible, given our
+ * understanding of watermark requirements. This might mean a
+ * mistake in the hardware readout code or a mistake in the
+ * watermark calculations for a given platform. Raise a WARN
+ * so that this is noticeable.
+ *
+ * If this actually happens, we'll have to just leave the
+ * BIOS-programmed watermarks untouched and hope for the best.
+ */
+ drm_WARN(&dev_priv->drm, ret,
+ "Could not determine valid watermarks for inherited state\n");
+
+ drm_atomic_state_put(state);
+
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+}
+
#define _FW_WM(value, plane) \
(((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
#define _FW_WM_VLV(value, plane) \
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.h b/drivers/gpu/drm/i915/display/i9xx_wm.h
index 133a3234dea5..a7875cbcd05a 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.h
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.h
@@ -14,6 +14,7 @@ struct intel_plane_state;
int ilk_wm_max_level(const struct drm_i915_private *i915);
bool ilk_disable_lp_wm(struct drm_i915_private *i915);
+void ilk_wm_sanitize(struct drm_i915_private *i915);
bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable);
void i9xx_wm_init(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3479125fbda6..d5769e8d5a5c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6606,8 +6606,8 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
* @dev: drm device
* @_state: state to validate
*/
-static int intel_atomic_check(struct drm_device *dev,
- struct drm_atomic_state *_state)
+int intel_atomic_check(struct drm_device *dev,
+ struct drm_atomic_state *_state)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_atomic_state *state = to_intel_atomic_state(_state);
@@ -8267,124 +8267,6 @@ void intel_modeset_init_hw(struct drm_i915_private *i915)
cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
}
-static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
-{
- struct drm_plane *plane;
- struct intel_crtc *crtc;
-
- for_each_intel_crtc(state->dev, crtc) {
- struct intel_crtc_state *crtc_state;
-
- crtc_state = intel_atomic_get_crtc_state(state, crtc);
- if (IS_ERR(crtc_state))
- return PTR_ERR(crtc_state);
-
- if (crtc_state->hw.active) {
- /*
- * Preserve the inherited flag to avoid
- * taking the full modeset path.
- */
- crtc_state->inherited = true;
- }
- }
-
- drm_for_each_plane(plane, state->dev) {
- struct drm_plane_state *plane_state;
-
- plane_state = drm_atomic_get_plane_state(state, plane);
- if (IS_ERR(plane_state))
- return PTR_ERR(plane_state);
- }
-
- return 0;
-}
-
-/*
- * Calculate what we think the watermarks should be for the state we've read
- * out of the hardware and then immediately program those watermarks so that
- * we ensure the hardware settings match our internal state.
- *
- * We can calculate what we think WM's should be by creating a duplicate of the
- * current state (which was constructed during hardware readout) and running it
- * through the atomic check code to calculate new watermark values in the
- * state object.
- */
-static void sanitize_watermarks(struct drm_i915_private *dev_priv)
-{
- struct drm_atomic_state *state;
- struct intel_atomic_state *intel_state;
- struct intel_crtc *crtc;
- struct intel_crtc_state *crtc_state;
- struct drm_modeset_acquire_ctx ctx;
- int ret;
- int i;
-
- /* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->display.funcs.wm->optimize_watermarks)
- return;
-
- state = drm_atomic_state_alloc(&dev_priv->drm);
- if (drm_WARN_ON(&dev_priv->drm, !state))
- return;
-
- intel_state = to_intel_atomic_state(state);
-
- drm_modeset_acquire_init(&ctx, 0);
-
-retry:
- state->acquire_ctx = &ctx;
-
- /*
- * Hardware readout is the only time we don't want to calculate
- * intermediate watermarks (since we don't trust the current
- * watermarks).
- */
- if (!HAS_GMCH(dev_priv))
- intel_state->skip_intermediate_wm = true;
-
- ret = sanitize_watermarks_add_affected(state);
- if (ret)
- goto fail;
-
- ret = intel_atomic_check(&dev_priv->drm, state);
- if (ret)
- goto fail;
-
- /* Write calculated watermark values back */
- for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
- crtc_state->wm.need_postvbl_update = true;
- intel_optimize_watermarks(intel_state, crtc);
-
- to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
- }
-
-fail:
- if (ret == -EDEADLK) {
- drm_atomic_state_clear(state);
- drm_modeset_backoff(&ctx);
- goto retry;
- }
-
- /*
- * If we fail here, it means that the hardware appears to be
- * programmed in a way that shouldn't be possible, given our
- * understanding of watermark requirements. This might mean a
- * mistake in the hardware readout code or a mistake in the
- * watermark calculations for a given platform. Raise a WARN
- * so that this is noticeable.
- *
- * If this actually happens, we'll have to just leave the
- * BIOS-programmed watermarks untouched and hope for the best.
- */
- drm_WARN(&dev_priv->drm, ret,
- "Could not determine valid watermarks for inherited state\n");
-
- drm_atomic_state_put(state);
-
- drm_modeset_drop_locks(&ctx);
- drm_modeset_acquire_fini(&ctx);
-}
-
static int intel_initial_commit(struct drm_device *dev)
{
struct drm_atomic_state *state = NULL;
@@ -8666,7 +8548,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
* since the watermark calculation done here will use pstate->fb.
*/
if (!HAS_GMCH(i915))
- sanitize_watermarks(i915);
+ ilk_wm_sanitize(i915);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index cb6f520cc575..ed852f62721d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -32,6 +32,7 @@
enum drm_scaling_filter;
struct dpll;
+struct drm_atomic_state;
struct drm_connector;
struct drm_device;
struct drm_display_mode;
@@ -394,6 +395,7 @@ enum phy_fia {
((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
(new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
+int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
struct intel_crtc *crtc);
u8 intel_calc_active_pipes(struct intel_atomic_state *state,
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v3 2/5] drm/i915/wm: warn about ilk_wm_sanitize() on display ver 9+
2023-02-15 14:19 [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch] Jani Nikula
@ 2023-02-15 14:19 ` Jani Nikula
2023-02-15 14:28 ` Ville Syrjälä
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 3/5] drm/i915/wm: move watermark debugfs to intel_wm.c Jani Nikula
` (6 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2023-02-15 14:19 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The sanitization should be limited to PCH split platforms up to display
version 8. Warn and bail out otherwise.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index f76ac64ebd71..50cdfe11192e 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -3437,6 +3437,9 @@ void ilk_wm_sanitize(struct drm_i915_private *dev_priv)
if (!dev_priv->display.funcs.wm->optimize_watermarks)
return;
+ if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) >= 9))
+ return;
+
state = drm_atomic_state_alloc(&dev_priv->drm);
if (drm_WARN_ON(&dev_priv->drm, !state))
return;
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v3 3/5] drm/i915/wm: move watermark debugfs to intel_wm.c
2023-02-15 14:19 [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch] Jani Nikula
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 2/5] drm/i915/wm: warn about ilk_wm_sanitize() on display ver 9+ Jani Nikula
@ 2023-02-15 14:19 ` Jani Nikula
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 4/5] drm/i915: rename intel_pm_types.h -> display/intel_wm_types.h Jani Nikula
` (5 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Jani Nikula @ 2023-02-15 14:19 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Follow the new convention of placing debugfs with the code.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 219 +----------------
drivers/gpu/drm/i915/display/intel_wm.c | 226 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_wm.h | 1 +
3 files changed, 229 insertions(+), 217 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 953cdffb3a66..25013f303c82 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -11,7 +11,6 @@
#include "i915_debugfs.h"
#include "i915_irq.h"
#include "i915_reg.h"
-#include "i9xx_wm.h"
#include "intel_de.h"
#include "intel_display_debugfs.h"
#include "intel_display_power.h"
@@ -30,7 +29,7 @@
#include "intel_pm.h"
#include "intel_psr.h"
#include "intel_sprite.h"
-#include "skl_watermark.h"
+#include "intel_wm.h"
static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
{
@@ -1283,217 +1282,6 @@ static int i915_displayport_test_type_show(struct seq_file *m, void *data)
}
DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type);
-static void wm_latency_show(struct seq_file *m, const u16 wm[8])
-{
- struct drm_i915_private *dev_priv = m->private;
- int level;
-
- drm_modeset_lock_all(&dev_priv->drm);
-
- for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
- unsigned int latency = wm[level];
-
- /*
- * - WM1+ latency values in 0.5us units
- * - latencies are in us on gen9/vlv/chv
- */
- if (DISPLAY_VER(dev_priv) >= 9 ||
- IS_VALLEYVIEW(dev_priv) ||
- IS_CHERRYVIEW(dev_priv) ||
- IS_G4X(dev_priv))
- latency *= 10;
- else if (level > 0)
- latency *= 5;
-
- seq_printf(m, "WM%d %u (%u.%u usec)\n",
- level, wm[level], latency / 10, latency % 10);
- }
-
- drm_modeset_unlock_all(&dev_priv->drm);
-}
-
-static int pri_wm_latency_show(struct seq_file *m, void *data)
-{
- struct drm_i915_private *dev_priv = m->private;
- const u16 *latencies;
-
- if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->display.wm.skl_latency;
- else
- latencies = dev_priv->display.wm.pri_latency;
-
- wm_latency_show(m, latencies);
-
- return 0;
-}
-
-static int spr_wm_latency_show(struct seq_file *m, void *data)
-{
- struct drm_i915_private *dev_priv = m->private;
- const u16 *latencies;
-
- if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->display.wm.skl_latency;
- else
- latencies = dev_priv->display.wm.spr_latency;
-
- wm_latency_show(m, latencies);
-
- return 0;
-}
-
-static int cur_wm_latency_show(struct seq_file *m, void *data)
-{
- struct drm_i915_private *dev_priv = m->private;
- const u16 *latencies;
-
- if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->display.wm.skl_latency;
- else
- latencies = dev_priv->display.wm.cur_latency;
-
- wm_latency_show(m, latencies);
-
- return 0;
-}
-
-static int pri_wm_latency_open(struct inode *inode, struct file *file)
-{
- struct drm_i915_private *dev_priv = inode->i_private;
-
- if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
- return -ENODEV;
-
- return single_open(file, pri_wm_latency_show, dev_priv);
-}
-
-static int spr_wm_latency_open(struct inode *inode, struct file *file)
-{
- struct drm_i915_private *dev_priv = inode->i_private;
-
- if (HAS_GMCH(dev_priv))
- return -ENODEV;
-
- return single_open(file, spr_wm_latency_show, dev_priv);
-}
-
-static int cur_wm_latency_open(struct inode *inode, struct file *file)
-{
- struct drm_i915_private *dev_priv = inode->i_private;
-
- if (HAS_GMCH(dev_priv))
- return -ENODEV;
-
- return single_open(file, cur_wm_latency_show, dev_priv);
-}
-
-static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
- size_t len, loff_t *offp, u16 wm[8])
-{
- struct seq_file *m = file->private_data;
- struct drm_i915_private *dev_priv = m->private;
- u16 new[8] = { 0 };
- int level;
- int ret;
- char tmp[32];
-
- if (len >= sizeof(tmp))
- return -EINVAL;
-
- if (copy_from_user(tmp, ubuf, len))
- return -EFAULT;
-
- tmp[len] = '\0';
-
- ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
- &new[0], &new[1], &new[2], &new[3],
- &new[4], &new[5], &new[6], &new[7]);
- if (ret != dev_priv->display.wm.num_levels)
- return -EINVAL;
-
- drm_modeset_lock_all(&dev_priv->drm);
-
- for (level = 0; level < dev_priv->display.wm.num_levels; level++)
- wm[level] = new[level];
-
- drm_modeset_unlock_all(&dev_priv->drm);
-
- return len;
-}
-
-
-static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
- size_t len, loff_t *offp)
-{
- struct seq_file *m = file->private_data;
- struct drm_i915_private *dev_priv = m->private;
- u16 *latencies;
-
- if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->display.wm.skl_latency;
- else
- latencies = dev_priv->display.wm.pri_latency;
-
- return wm_latency_write(file, ubuf, len, offp, latencies);
-}
-
-static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
- size_t len, loff_t *offp)
-{
- struct seq_file *m = file->private_data;
- struct drm_i915_private *dev_priv = m->private;
- u16 *latencies;
-
- if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->display.wm.skl_latency;
- else
- latencies = dev_priv->display.wm.spr_latency;
-
- return wm_latency_write(file, ubuf, len, offp, latencies);
-}
-
-static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
- size_t len, loff_t *offp)
-{
- struct seq_file *m = file->private_data;
- struct drm_i915_private *dev_priv = m->private;
- u16 *latencies;
-
- if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->display.wm.skl_latency;
- else
- latencies = dev_priv->display.wm.cur_latency;
-
- return wm_latency_write(file, ubuf, len, offp, latencies);
-}
-
-static const struct file_operations i915_pri_wm_latency_fops = {
- .owner = THIS_MODULE,
- .open = pri_wm_latency_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
- .write = pri_wm_latency_write
-};
-
-static const struct file_operations i915_spr_wm_latency_fops = {
- .owner = THIS_MODULE,
- .open = spr_wm_latency_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
- .write = spr_wm_latency_write
-};
-
-static const struct file_operations i915_cur_wm_latency_fops = {
- .owner = THIS_MODULE,
- .open = cur_wm_latency_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
- .write = cur_wm_latency_write
-};
-
static ssize_t
i915_fifo_underrun_reset_write(struct file *filp,
const char __user *ubuf,
@@ -1574,9 +1362,6 @@ static const struct {
const struct file_operations *fops;
} intel_display_debugfs_files[] = {
{"i915_fifo_underrun_reset", &i915_fifo_underrun_reset_ops},
- {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
- {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
- {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
{"i915_dp_test_data", &i915_displayport_test_data_fops},
{"i915_dp_test_type", &i915_displayport_test_type_fops},
{"i915_dp_test_active", &i915_displayport_test_active_fops},
@@ -1603,7 +1388,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
intel_dmc_debugfs_register(i915);
intel_fbc_debugfs_register(i915);
intel_hpd_debugfs_register(i915);
- skl_watermark_debugfs_register(i915);
+ intel_wm_debugfs_register(i915);
}
static int i915_panel_show(struct seq_file *m, void *data)
diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c
index c4d14a51869b..bb99179cd5fd 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.c
+++ b/drivers/gpu/drm/i915/display/intel_wm.c
@@ -180,3 +180,229 @@ void intel_wm_init(struct drm_i915_private *i915)
else
i9xx_wm_init(i915);
}
+
+static void wm_latency_show(struct seq_file *m, const u16 wm[8])
+{
+ struct drm_i915_private *dev_priv = m->private;
+ int level;
+
+ drm_modeset_lock_all(&dev_priv->drm);
+
+ for (level = 0; level < dev_priv->display.wm.num_levels; level++) {
+ unsigned int latency = wm[level];
+
+ /*
+ * - WM1+ latency values in 0.5us units
+ * - latencies are in us on gen9/vlv/chv
+ */
+ if (DISPLAY_VER(dev_priv) >= 9 ||
+ IS_VALLEYVIEW(dev_priv) ||
+ IS_CHERRYVIEW(dev_priv) ||
+ IS_G4X(dev_priv))
+ latency *= 10;
+ else if (level > 0)
+ latency *= 5;
+
+ seq_printf(m, "WM%d %u (%u.%u usec)\n",
+ level, wm[level], latency / 10, latency % 10);
+ }
+
+ drm_modeset_unlock_all(&dev_priv->drm);
+}
+
+static int pri_wm_latency_show(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *dev_priv = m->private;
+ const u16 *latencies;
+
+ if (DISPLAY_VER(dev_priv) >= 9)
+ latencies = dev_priv->display.wm.skl_latency;
+ else
+ latencies = dev_priv->display.wm.pri_latency;
+
+ wm_latency_show(m, latencies);
+
+ return 0;
+}
+
+static int spr_wm_latency_show(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *dev_priv = m->private;
+ const u16 *latencies;
+
+ if (DISPLAY_VER(dev_priv) >= 9)
+ latencies = dev_priv->display.wm.skl_latency;
+ else
+ latencies = dev_priv->display.wm.spr_latency;
+
+ wm_latency_show(m, latencies);
+
+ return 0;
+}
+
+static int cur_wm_latency_show(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *dev_priv = m->private;
+ const u16 *latencies;
+
+ if (DISPLAY_VER(dev_priv) >= 9)
+ latencies = dev_priv->display.wm.skl_latency;
+ else
+ latencies = dev_priv->display.wm.cur_latency;
+
+ wm_latency_show(m, latencies);
+
+ return 0;
+}
+
+static int pri_wm_latency_open(struct inode *inode, struct file *file)
+{
+ struct drm_i915_private *dev_priv = inode->i_private;
+
+ if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
+ return -ENODEV;
+
+ return single_open(file, pri_wm_latency_show, dev_priv);
+}
+
+static int spr_wm_latency_open(struct inode *inode, struct file *file)
+{
+ struct drm_i915_private *dev_priv = inode->i_private;
+
+ if (HAS_GMCH(dev_priv))
+ return -ENODEV;
+
+ return single_open(file, spr_wm_latency_show, dev_priv);
+}
+
+static int cur_wm_latency_open(struct inode *inode, struct file *file)
+{
+ struct drm_i915_private *dev_priv = inode->i_private;
+
+ if (HAS_GMCH(dev_priv))
+ return -ENODEV;
+
+ return single_open(file, cur_wm_latency_show, dev_priv);
+}
+
+static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
+ size_t len, loff_t *offp, u16 wm[8])
+{
+ struct seq_file *m = file->private_data;
+ struct drm_i915_private *dev_priv = m->private;
+ u16 new[8] = { 0 };
+ int level;
+ int ret;
+ char tmp[32];
+
+ if (len >= sizeof(tmp))
+ return -EINVAL;
+
+ if (copy_from_user(tmp, ubuf, len))
+ return -EFAULT;
+
+ tmp[len] = '\0';
+
+ ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
+ &new[0], &new[1], &new[2], &new[3],
+ &new[4], &new[5], &new[6], &new[7]);
+ if (ret != dev_priv->display.wm.num_levels)
+ return -EINVAL;
+
+ drm_modeset_lock_all(&dev_priv->drm);
+
+ for (level = 0; level < dev_priv->display.wm.num_levels; level++)
+ wm[level] = new[level];
+
+ drm_modeset_unlock_all(&dev_priv->drm);
+
+ return len;
+}
+
+static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ struct drm_i915_private *dev_priv = m->private;
+ u16 *latencies;
+
+ if (DISPLAY_VER(dev_priv) >= 9)
+ latencies = dev_priv->display.wm.skl_latency;
+ else
+ latencies = dev_priv->display.wm.pri_latency;
+
+ return wm_latency_write(file, ubuf, len, offp, latencies);
+}
+
+static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ struct drm_i915_private *dev_priv = m->private;
+ u16 *latencies;
+
+ if (DISPLAY_VER(dev_priv) >= 9)
+ latencies = dev_priv->display.wm.skl_latency;
+ else
+ latencies = dev_priv->display.wm.spr_latency;
+
+ return wm_latency_write(file, ubuf, len, offp, latencies);
+}
+
+static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
+ size_t len, loff_t *offp)
+{
+ struct seq_file *m = file->private_data;
+ struct drm_i915_private *dev_priv = m->private;
+ u16 *latencies;
+
+ if (DISPLAY_VER(dev_priv) >= 9)
+ latencies = dev_priv->display.wm.skl_latency;
+ else
+ latencies = dev_priv->display.wm.cur_latency;
+
+ return wm_latency_write(file, ubuf, len, offp, latencies);
+}
+
+static const struct file_operations i915_pri_wm_latency_fops = {
+ .owner = THIS_MODULE,
+ .open = pri_wm_latency_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = pri_wm_latency_write
+};
+
+static const struct file_operations i915_spr_wm_latency_fops = {
+ .owner = THIS_MODULE,
+ .open = spr_wm_latency_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = spr_wm_latency_write
+};
+
+static const struct file_operations i915_cur_wm_latency_fops = {
+ .owner = THIS_MODULE,
+ .open = cur_wm_latency_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = cur_wm_latency_write
+};
+
+void intel_wm_debugfs_register(struct drm_i915_private *i915)
+{
+ struct drm_minor *minor = i915->drm.primary;
+
+ debugfs_create_file("i915_pri_wm_latency", 0644, minor->debugfs_root,
+ i915, &i915_pri_wm_latency_fops);
+
+ debugfs_create_file("i915_spr_wm_latency", 0644, minor->debugfs_root,
+ i915, &i915_spr_wm_latency_fops);
+
+ debugfs_create_file("i915_cur_wm_latency", 0644, minor->debugfs_root,
+ i915, &i915_cur_wm_latency_fops);
+
+ skl_watermark_debugfs_register(i915);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_wm.h b/drivers/gpu/drm/i915/display/intel_wm.h
index dc582967a25e..48429ac140d2 100644
--- a/drivers/gpu/drm/i915/display/intel_wm.h
+++ b/drivers/gpu/drm/i915/display/intel_wm.h
@@ -32,5 +32,6 @@ bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
void intel_print_wm_latency(struct drm_i915_private *i915,
const char *name, const u16 wm[]);
void intel_wm_init(struct drm_i915_private *i915);
+void intel_wm_debugfs_register(struct drm_i915_private *i915);
#endif /* __INTEL_WM_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v3 4/5] drm/i915: rename intel_pm_types.h -> display/intel_wm_types.h
2023-02-15 14:19 [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch] Jani Nikula
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 2/5] drm/i915/wm: warn about ilk_wm_sanitize() on display ver 9+ Jani Nikula
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 3/5] drm/i915/wm: move watermark debugfs to intel_wm.c Jani Nikula
@ 2023-02-15 14:19 ` Jani Nikula
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 5/5] drm/i915/wm: remove ILK+ nop funcs fallback Jani Nikula
` (4 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Jani Nikula @ 2023-02-15 14:19 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
The file was never really about pm types, and now it's even more
obvious. Move under display as intel_wm_types.h.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_core.h | 2 +-
drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
.../drm/i915/{intel_pm_types.h => display/intel_wm_types.h} | 6 +++---
drivers/gpu/drm/i915/display/skl_watermark.h | 2 +-
4 files changed, 6 insertions(+), 6 deletions(-)
rename drivers/gpu/drm/i915/{intel_pm_types.h => display/intel_wm_types.h} (93%)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 52614fff0d76..b870f7f47f2b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -25,7 +25,7 @@
#include "intel_global_state.h"
#include "intel_gmbus.h"
#include "intel_opregion.h"
-#include "intel_pm_types.h"
+#include "intel_wm_types.h"
struct drm_i915_private;
struct drm_property;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6e94be7c3e7f..748b0cd411fa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -53,7 +53,7 @@
#include "intel_display_limits.h"
#include "intel_display_power.h"
#include "intel_dpll_mgr.h"
-#include "intel_pm_types.h"
+#include "intel_wm_types.h"
struct drm_printer;
struct __intel_global_objs_state;
diff --git a/drivers/gpu/drm/i915/intel_pm_types.h b/drivers/gpu/drm/i915/display/intel_wm_types.h
similarity index 93%
rename from drivers/gpu/drm/i915/intel_pm_types.h
rename to drivers/gpu/drm/i915/display/intel_wm_types.h
index 93152537b420..bac2b6fdc5d0 100644
--- a/drivers/gpu/drm/i915/intel_pm_types.h
+++ b/drivers/gpu/drm/i915/display/intel_wm_types.h
@@ -3,8 +3,8 @@
* Copyright © 2021 Intel Corporation
*/
-#ifndef __INTEL_PM_TYPES_H__
-#define __INTEL_PM_TYPES_H__
+#ifndef __INTEL_WM_TYPES_H__
+#define __INTEL_WM_TYPES_H__
#include <linux/types.h>
@@ -73,4 +73,4 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
return false;
}
-#endif /* __INTEL_PM_TYPES_H__ */
+#endif /* __INTEL_WM_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index f03fd991b189..f91a3d4ddc07 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -10,7 +10,7 @@
#include "intel_display_limits.h"
#include "intel_global_state.h"
-#include "intel_pm_types.h"
+#include "intel_wm_types.h"
struct drm_i915_private;
struct intel_atomic_state;
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH v3 5/5] drm/i915/wm: remove ILK+ nop funcs fallback
2023-02-15 14:19 [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch] Jani Nikula
` (2 preceding siblings ...)
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 4/5] drm/i915: rename intel_pm_types.h -> display/intel_wm_types.h Jani Nikula
@ 2023-02-15 14:19 ` Jani Nikula
2023-02-15 14:29 ` Ville Syrjälä
2023-02-15 14:27 ` [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch] Ville Syrjälä
` (3 subsequent siblings)
7 siblings, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2023-02-15 14:19 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Disabling ILK+ watermarks on failure to read the watermark levels dates
back to 2010 and commit 7f8a85698f5c ("drm/i915: Add the support of
memory self-refresh on Ironlake"), with no explanations, and it's been
copied and modified from that ever since. Finally drop it.
If the value are actually zero, the ilk_compute_*_wm() functions should
handle it gracefully.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 14 +-------------
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 50cdfe11192e..3d4687efe4dd 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -4007,19 +4007,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
/* For FIFO watermark updates */
if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
-
- if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->display.wm.pri_latency[1] &&
- dev_priv->display.wm.spr_latency[1] && dev_priv->display.wm.cur_latency[1]) ||
- (DISPLAY_VER(dev_priv) != 5 && dev_priv->display.wm.pri_latency[0] &&
- dev_priv->display.wm.spr_latency[0] && dev_priv->display.wm.cur_latency[0])) {
- dev_priv->display.funcs.wm = &ilk_wm_funcs;
- } else {
- ilk_init_lp_watermarks(dev_priv);
- drm_dbg_kms(&dev_priv->drm,
- "Failed to read display plane latency. "
- "Disable CxSR\n");
- dev_priv->display.funcs.wm = &nop_funcs;
- }
+ dev_priv->display.funcs.wm = &ilk_wm_funcs;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
vlv_setup_wm_latency(dev_priv);
dev_priv->display.funcs.wm = &vlv_wm_funcs;
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch]
2023-02-15 14:19 [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch] Jani Nikula
` (3 preceding siblings ...)
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 5/5] drm/i915/wm: remove ILK+ nop funcs fallback Jani Nikula
@ 2023-02-15 14:27 ` Ville Syrjälä
2023-02-15 18:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/5] " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2023-02-15 14:27 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Feb 15, 2023 at 04:19:06PM +0200, Jani Nikula wrote:
> Move sanitize_watermarks() to i9xx_wm.[ch] and rename as
> ilk_wm_sanitize(). The slightly unfortunate downside is having to expose
> intel_atomic_check() from intel_display.c, but this declutters
> intel_display.c nicely.
>
> v2:
> - Move to i9xx_wm.[ch] instead of intel_wm.[ch] (Ville)
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c | 119 ++++++++++++++++++
> drivers/gpu/drm/i915/display/i9xx_wm.h | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 124 +------------------
> drivers/gpu/drm/i915/display/intel_display.h | 2 +
> 4 files changed, 125 insertions(+), 121 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index dfdd40991871..f76ac64ebd71 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -5,6 +5,7 @@
>
> #include "i915_drv.h"
> #include "i9xx_wm.h"
> +#include "intel_atomic.h"
> #include "intel_display.h"
> #include "intel_display_trace.h"
> #include "intel_mchbar_regs.h"
> @@ -3380,6 +3381,124 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
> crtc->wm.active.ilk = *active;
> }
>
> +static int ilk_sanitize_watermarks_add_affected(struct drm_atomic_state *state)
> +{
> + struct drm_plane *plane;
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(state->dev, crtc) {
> + struct intel_crtc_state *crtc_state;
> +
> + crtc_state = intel_atomic_get_crtc_state(state, crtc);
> + if (IS_ERR(crtc_state))
> + return PTR_ERR(crtc_state);
> +
> + if (crtc_state->hw.active) {
> + /*
> + * Preserve the inherited flag to avoid
> + * taking the full modeset path.
> + */
> + crtc_state->inherited = true;
> + }
> + }
> +
> + drm_for_each_plane(plane, state->dev) {
> + struct drm_plane_state *plane_state;
> +
> + plane_state = drm_atomic_get_plane_state(state, plane);
> + if (IS_ERR(plane_state))
> + return PTR_ERR(plane_state);
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * Calculate what we think the watermarks should be for the state we've read
> + * out of the hardware and then immediately program those watermarks so that
> + * we ensure the hardware settings match our internal state.
> + *
> + * We can calculate what we think WM's should be by creating a duplicate of the
> + * current state (which was constructed during hardware readout) and running it
> + * through the atomic check code to calculate new watermark values in the
> + * state object.
> + */
> +void ilk_wm_sanitize(struct drm_i915_private *dev_priv)
> +{
> + struct drm_atomic_state *state;
> + struct intel_atomic_state *intel_state;
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *crtc_state;
> + struct drm_modeset_acquire_ctx ctx;
> + int ret;
> + int i;
> +
> + /* Only supported on platforms that use atomic watermark design */
> + if (!dev_priv->display.funcs.wm->optimize_watermarks)
> + return;
> +
> + state = drm_atomic_state_alloc(&dev_priv->drm);
> + if (drm_WARN_ON(&dev_priv->drm, !state))
> + return;
> +
> + intel_state = to_intel_atomic_state(state);
> +
> + drm_modeset_acquire_init(&ctx, 0);
> +
> +retry:
> + state->acquire_ctx = &ctx;
> +
> + /*
> + * Hardware readout is the only time we don't want to calculate
> + * intermediate watermarks (since we don't trust the current
> + * watermarks).
> + */
> + if (!HAS_GMCH(dev_priv))
> + intel_state->skip_intermediate_wm = true;
> +
> + ret = ilk_sanitize_watermarks_add_affected(state);
> + if (ret)
> + goto fail;
> +
> + ret = intel_atomic_check(&dev_priv->drm, state);
> + if (ret)
> + goto fail;
> +
> + /* Write calculated watermark values back */
> + for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> + crtc_state->wm.need_postvbl_update = true;
> + intel_optimize_watermarks(intel_state, crtc);
> +
> + to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
> + }
> +
> +fail:
> + if (ret == -EDEADLK) {
> + drm_atomic_state_clear(state);
> + drm_modeset_backoff(&ctx);
> + goto retry;
> + }
> +
> + /*
> + * If we fail here, it means that the hardware appears to be
> + * programmed in a way that shouldn't be possible, given our
> + * understanding of watermark requirements. This might mean a
> + * mistake in the hardware readout code or a mistake in the
> + * watermark calculations for a given platform. Raise a WARN
> + * so that this is noticeable.
> + *
> + * If this actually happens, we'll have to just leave the
> + * BIOS-programmed watermarks untouched and hope for the best.
> + */
> + drm_WARN(&dev_priv->drm, ret,
> + "Could not determine valid watermarks for inherited state\n");
> +
> + drm_atomic_state_put(state);
> +
> + drm_modeset_drop_locks(&ctx);
> + drm_modeset_acquire_fini(&ctx);
> +}
> +
> #define _FW_WM(value, plane) \
> (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
> #define _FW_WM_VLV(value, plane) \
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.h b/drivers/gpu/drm/i915/display/i9xx_wm.h
> index 133a3234dea5..a7875cbcd05a 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.h
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.h
> @@ -14,6 +14,7 @@ struct intel_plane_state;
>
> int ilk_wm_max_level(const struct drm_i915_private *i915);
> bool ilk_disable_lp_wm(struct drm_i915_private *i915);
> +void ilk_wm_sanitize(struct drm_i915_private *i915);
> bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable);
> void i9xx_wm_init(struct drm_i915_private *i915);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 3479125fbda6..d5769e8d5a5c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6606,8 +6606,8 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
> * @dev: drm device
> * @_state: state to validate
> */
> -static int intel_atomic_check(struct drm_device *dev,
> - struct drm_atomic_state *_state)
> +int intel_atomic_check(struct drm_device *dev,
> + struct drm_atomic_state *_state)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_atomic_state *state = to_intel_atomic_state(_state);
> @@ -8267,124 +8267,6 @@ void intel_modeset_init_hw(struct drm_i915_private *i915)
> cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
> }
>
> -static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
> -{
> - struct drm_plane *plane;
> - struct intel_crtc *crtc;
> -
> - for_each_intel_crtc(state->dev, crtc) {
> - struct intel_crtc_state *crtc_state;
> -
> - crtc_state = intel_atomic_get_crtc_state(state, crtc);
> - if (IS_ERR(crtc_state))
> - return PTR_ERR(crtc_state);
> -
> - if (crtc_state->hw.active) {
> - /*
> - * Preserve the inherited flag to avoid
> - * taking the full modeset path.
> - */
> - crtc_state->inherited = true;
> - }
> - }
> -
> - drm_for_each_plane(plane, state->dev) {
> - struct drm_plane_state *plane_state;
> -
> - plane_state = drm_atomic_get_plane_state(state, plane);
> - if (IS_ERR(plane_state))
> - return PTR_ERR(plane_state);
> - }
> -
> - return 0;
> -}
> -
> -/*
> - * Calculate what we think the watermarks should be for the state we've read
> - * out of the hardware and then immediately program those watermarks so that
> - * we ensure the hardware settings match our internal state.
> - *
> - * We can calculate what we think WM's should be by creating a duplicate of the
> - * current state (which was constructed during hardware readout) and running it
> - * through the atomic check code to calculate new watermark values in the
> - * state object.
> - */
> -static void sanitize_watermarks(struct drm_i915_private *dev_priv)
> -{
> - struct drm_atomic_state *state;
> - struct intel_atomic_state *intel_state;
> - struct intel_crtc *crtc;
> - struct intel_crtc_state *crtc_state;
> - struct drm_modeset_acquire_ctx ctx;
> - int ret;
> - int i;
> -
> - /* Only supported on platforms that use atomic watermark design */
> - if (!dev_priv->display.funcs.wm->optimize_watermarks)
> - return;
> -
> - state = drm_atomic_state_alloc(&dev_priv->drm);
> - if (drm_WARN_ON(&dev_priv->drm, !state))
> - return;
> -
> - intel_state = to_intel_atomic_state(state);
> -
> - drm_modeset_acquire_init(&ctx, 0);
> -
> -retry:
> - state->acquire_ctx = &ctx;
> -
> - /*
> - * Hardware readout is the only time we don't want to calculate
> - * intermediate watermarks (since we don't trust the current
> - * watermarks).
> - */
> - if (!HAS_GMCH(dev_priv))
> - intel_state->skip_intermediate_wm = true;
> -
> - ret = sanitize_watermarks_add_affected(state);
> - if (ret)
> - goto fail;
> -
> - ret = intel_atomic_check(&dev_priv->drm, state);
> - if (ret)
> - goto fail;
> -
> - /* Write calculated watermark values back */
> - for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
> - crtc_state->wm.need_postvbl_update = true;
> - intel_optimize_watermarks(intel_state, crtc);
> -
> - to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
> - }
> -
> -fail:
> - if (ret == -EDEADLK) {
> - drm_atomic_state_clear(state);
> - drm_modeset_backoff(&ctx);
> - goto retry;
> - }
> -
> - /*
> - * If we fail here, it means that the hardware appears to be
> - * programmed in a way that shouldn't be possible, given our
> - * understanding of watermark requirements. This might mean a
> - * mistake in the hardware readout code or a mistake in the
> - * watermark calculations for a given platform. Raise a WARN
> - * so that this is noticeable.
> - *
> - * If this actually happens, we'll have to just leave the
> - * BIOS-programmed watermarks untouched and hope for the best.
> - */
> - drm_WARN(&dev_priv->drm, ret,
> - "Could not determine valid watermarks for inherited state\n");
> -
> - drm_atomic_state_put(state);
> -
> - drm_modeset_drop_locks(&ctx);
> - drm_modeset_acquire_fini(&ctx);
> -}
> -
> static int intel_initial_commit(struct drm_device *dev)
> {
> struct drm_atomic_state *state = NULL;
> @@ -8666,7 +8548,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
> * since the watermark calculation done here will use pstate->fb.
> */
> if (!HAS_GMCH(i915))
Maybe also pimp this a bit so we don't even call it on skl+?
Either way
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> - sanitize_watermarks(i915);
> + ilk_wm_sanitize(i915);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index cb6f520cc575..ed852f62721d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -32,6 +32,7 @@
>
> enum drm_scaling_filter;
> struct dpll;
> +struct drm_atomic_state;
> struct drm_connector;
> struct drm_device;
> struct drm_display_mode;
> @@ -394,6 +395,7 @@ enum phy_fia {
> ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
> (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
>
> +int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
> int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> u8 intel_calc_active_pipes(struct intel_atomic_state *state,
> --
> 2.34.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/5] drm/i915/wm: warn about ilk_wm_sanitize() on display ver 9+
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 2/5] drm/i915/wm: warn about ilk_wm_sanitize() on display ver 9+ Jani Nikula
@ 2023-02-15 14:28 ` Ville Syrjälä
2023-02-16 15:19 ` Jani Nikula
0 siblings, 1 reply; 12+ messages in thread
From: Ville Syrjälä @ 2023-02-15 14:28 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Feb 15, 2023 at 04:19:07PM +0200, Jani Nikula wrote:
> The sanitization should be limited to PCH split platforms up to display
> version 8. Warn and bail out otherwise.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index f76ac64ebd71..50cdfe11192e 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -3437,6 +3437,9 @@ void ilk_wm_sanitize(struct drm_i915_private *dev_priv)
> if (!dev_priv->display.funcs.wm->optimize_watermarks)
> return;
>
> + if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) >= 9))
> + return;
> +
Oh you put it here. I guess that works too, though still
a bit confusing that we call an ilk_ thing on skl+.
Whatever you decide
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> state = drm_atomic_state_alloc(&dev_priv->drm);
> if (drm_WARN_ON(&dev_priv->drm, !state))
> return;
> --
> 2.34.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v3 5/5] drm/i915/wm: remove ILK+ nop funcs fallback
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 5/5] drm/i915/wm: remove ILK+ nop funcs fallback Jani Nikula
@ 2023-02-15 14:29 ` Ville Syrjälä
0 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjälä @ 2023-02-15 14:29 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Feb 15, 2023 at 04:19:10PM +0200, Jani Nikula wrote:
> Disabling ILK+ watermarks on failure to read the watermark levels dates
> back to 2010 and commit 7f8a85698f5c ("drm/i915: Add the support of
> memory self-refresh on Ironlake"), with no explanations, and it's been
> copied and modified from that ever since. Finally drop it.
>
> If the value are actually zero, the ilk_compute_*_wm() functions should
> handle it gracefully.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c | 14 +-------------
> 1 file changed, 1 insertion(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 50cdfe11192e..3d4687efe4dd 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -4007,19 +4007,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
> /* For FIFO watermark updates */
> if (HAS_PCH_SPLIT(dev_priv)) {
> ilk_setup_wm_latency(dev_priv);
> -
> - if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->display.wm.pri_latency[1] &&
> - dev_priv->display.wm.spr_latency[1] && dev_priv->display.wm.cur_latency[1]) ||
> - (DISPLAY_VER(dev_priv) != 5 && dev_priv->display.wm.pri_latency[0] &&
> - dev_priv->display.wm.spr_latency[0] && dev_priv->display.wm.cur_latency[0])) {
> - dev_priv->display.funcs.wm = &ilk_wm_funcs;
> - } else {
> - ilk_init_lp_watermarks(dev_priv);
> - drm_dbg_kms(&dev_priv->drm,
> - "Failed to read display plane latency. "
> - "Disable CxSR\n");
> - dev_priv->display.funcs.wm = &nop_funcs;
> - }
> + dev_priv->display.funcs.wm = &ilk_wm_funcs;
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> vlv_setup_wm_latency(dev_priv);
> dev_priv->display.funcs.wm = &vlv_wm_funcs;
> --
> 2.34.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch]
2023-02-15 14:19 [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch] Jani Nikula
` (4 preceding siblings ...)
2023-02-15 14:27 ` [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch] Ville Syrjälä
@ 2023-02-15 18:32 ` Patchwork
2023-02-15 18:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-02-16 14:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
7 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-02-15 18:32 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch]
URL : https://patchwork.freedesktop.org/series/114055/
State : warning
== Summary ==
Error: dim checkpatch failed
0a089d0ac10a drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch]
cf777d7c7bb0 drm/i915/wm: warn about ilk_wm_sanitize() on display ver 9+
2c91a9e0013f drm/i915/wm: move watermark debugfs to intel_wm.c
f6734d77c3e5 drm/i915: rename intel_pm_types.h -> display/intel_wm_types.h
-:44: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#44:
rename from drivers/gpu/drm/i915/intel_pm_types.h
total: 0 errors, 1 warnings, 0 checks, 39 lines checked
c1a6ab934cfd drm/i915/wm: remove ILK+ nop funcs fallback
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch]
2023-02-15 14:19 [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch] Jani Nikula
` (5 preceding siblings ...)
2023-02-15 18:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/5] " Patchwork
@ 2023-02-15 18:56 ` Patchwork
2023-02-16 14:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
7 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-02-15 18:56 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3324 bytes --]
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch]
URL : https://patchwork.freedesktop.org/series/114055/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12744 -> Patchwork_114055v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/index.html
Participating hosts (40 -> 39)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_114055v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_suspend@basic-s2idle-without-i915:
- {bat-rpls-1}: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html
Known issues
------------
Here are the changes found in Patchwork_114055v1 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- fi-skl-guc: [DMESG-WARN][3] ([i915#8073]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/fi-skl-guc/igt@i915_selftest@live@hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/fi-skl-guc/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@mman:
- {bat-rpls-1}: [TIMEOUT][5] ([i915#6794]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/bat-rpls-1/igt@i915_selftest@live@mman.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/bat-rpls-1/igt@i915_selftest@live@mman.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#8073]: https://gitlab.freedesktop.org/drm/intel/issues/8073
Build changes
-------------
* Linux: CI_DRM_12744 -> Patchwork_114055v1
CI-20190529: 20190529
CI_DRM_12744: 2e4cac06e4de01a35626de676b9eeb474ae7ab5d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7160: 45da871dd2684227e93a2fc002b87dfc58bd5fd9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_114055v1: 2e4cac06e4de01a35626de676b9eeb474ae7ab5d @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
b1404f970ed2 drm/i915/wm: remove ILK+ nop funcs fallback
69a27ab18b64 drm/i915: rename intel_pm_types.h -> display/intel_wm_types.h
bcd01833e2cf drm/i915/wm: move watermark debugfs to intel_wm.c
3e253f36a438 drm/i915/wm: warn about ilk_wm_sanitize() on display ver 9+
b530d5df24ab drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch]
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/index.html
[-- Attachment #2: Type: text/html, Size: 3889 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v3,1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch]
2023-02-15 14:19 [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch] Jani Nikula
` (6 preceding siblings ...)
2023-02-15 18:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-02-16 14:01 ` Patchwork
7 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-02-16 14:01 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 23109 bytes --]
== Series Details ==
Series: series starting with [v3,1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch]
URL : https://patchwork.freedesktop.org/series/114055/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12744_full -> Patchwork_114055v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_114055v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_114055v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/index.html
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_114055v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_eio@in-flight-contexts-10ms:
- {shard-rkl}: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-2/igt@gem_eio@in-flight-contexts-10ms.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-6/igt@gem_eio@in-flight-contexts-10ms.html
Known issues
------------
Here are the changes found in Patchwork_114055v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-glk9/igt@gem_exec_fair@basic-pace@vcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-glk8/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][9] ([i915#3318])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-apl1/igt@gem_userptr_blits@vma-merge.html
* igt@kms_color@ctm-0-75@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][10] ([fdo#109271]) +12 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-snb4/igt@kms_color@ctm-0-75@pipe-b-vga-1.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-apl: [PASS][11] -> [FAIL][12] ([i915#2346])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][13] -> [FAIL][14] ([i915#4767])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#79])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-c-dp-1:
- shard-apl: NOTRUN -> [FAIL][17] ([i915#4573]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-apl1/igt@kms_plane_alpha_blend@alpha-transparent-fb@pipe-c-dp-1.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-b-dp-1:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271]) +32 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-apl1/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-75@pipe-b-dp-1.html
* igt@perf@gen12-mi-rpc:
- shard-glk: NOTRUN -> [SKIP][19] ([fdo#109271]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-glk2/igt@perf@gen12-mi-rpc.html
#### Possible fixes ####
* igt@drm_fdinfo@virtual-idle:
- {shard-rkl}: [FAIL][20] ([i915#7742]) -> [PASS][21] +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-1/igt@drm_fdinfo@virtual-idle.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-4/igt@drm_fdinfo@virtual-idle.html
* igt@fbdev@eof:
- {shard-tglu}: [SKIP][22] ([i915#2582]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-tglu-6/igt@fbdev@eof.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-tglu-2/igt@fbdev@eof.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-apl: [ABORT][24] -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-apl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-apl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_ctx_persistence@hang:
- {shard-rkl}: [SKIP][26] ([i915#6252]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-5/igt@gem_ctx_persistence@hang.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-3/igt@gem_ctx_persistence@hang.html
* igt@gem_eio@in-flight-external:
- {shard-rkl}: [ABORT][28] ([i915#7811]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-1/igt@gem_eio@in-flight-external.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-6/igt@gem_eio@in-flight-external.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][30] ([i915#2842]) -> [PASS][31] +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_suspend@basic-s3@smem:
- {shard-rkl}: [ABORT][32] ([i915#5122]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-4/igt@gem_exec_suspend@basic-s3@smem.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_partial_pwrite_pread@reads:
- {shard-rkl}: [SKIP][34] ([i915#3282]) -> [PASS][35] +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-1/igt@gem_partial_pwrite_pread@reads.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-5/igt@gem_partial_pwrite_pread@reads.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- {shard-rkl}: [SKIP][36] ([i915#3281]) -> [PASS][37] +5 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-6/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-5/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [ABORT][38] ([i915#5566]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-glk6/igt@gen9_exec_parse@allowed-single.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-glk2/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-start-out:
- {shard-rkl}: [SKIP][40] ([i915#2527]) -> [PASS][41] +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-6/igt@gen9_exec_parse@bb-start-out.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-5/igt@gen9_exec_parse@bb-start-out.html
* igt@i915_pm_sseu@full-enable:
- {shard-rkl}: [SKIP][42] ([i915#4387]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-2/igt@i915_pm_sseu@full-enable.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-5/igt@i915_pm_sseu@full-enable.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs:
- {shard-tglu}: [SKIP][44] ([i915#1845] / [i915#7651]) -> [PASS][45] +12 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-tglu-6/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-tglu-2/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [FAIL][46] ([i915#2346]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- {shard-tglu}: [SKIP][48] ([i915#1849]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-tglu-2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- {shard-rkl}: [SKIP][50] ([i915#1849] / [i915#4098]) -> [PASS][51] +8 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_plane@plane-position-hole@pipe-b-planes:
- {shard-rkl}: [SKIP][52] ([i915#1849]) -> [PASS][53] +3 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-1/igt@kms_plane@plane-position-hole@pipe-b-planes.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-6/igt@kms_plane@plane-position-hole@pipe-b-planes.html
* igt@kms_psr@sprite_render:
- {shard-rkl}: [SKIP][54] ([i915#1072]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-4/igt@kms_psr@sprite_render.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-6/igt@kms_psr@sprite_render.html
* igt@kms_vblank@pipe-b-ts-continuation-idle:
- {shard-rkl}: [SKIP][56] ([i915#1845] / [i915#4098]) -> [PASS][57] +10 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-4/igt@kms_vblank@pipe-b-ts-continuation-idle.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-6/igt@kms_vblank@pipe-b-ts-continuation-idle.html
* igt@perf_pmu@idle@rcs0:
- {shard-rkl}: [FAIL][58] ([i915#4349]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-rkl-6/igt@perf_pmu@idle@rcs0.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-rkl-5/igt@perf_pmu@idle@rcs0.html
* igt@syncobj_wait@wait-all-delayed-signal:
- {shard-dg1}: [DMESG-WARN][60] ([i915#1982]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12744/shard-dg1-18/igt@syncobj_wait@wait-all-delayed-signal.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/shard-dg1-17/igt@syncobj_wait@wait-all-delayed-signal.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#5115]: https://gitlab.freedesktop.org/drm/intel/issues/5115
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7178]: https://gitlab.freedesktop.org/drm/intel/issues/7178
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7811]: https://gitlab.freedesktop.org/drm/intel/issues/7811
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
[i915#7984]: https://gitlab.freedesktop.org/drm/intel/issues/7984
[i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
[i915#8155]: https://gitlab.freedesktop.org/drm/intel/issues/8155
Build changes
-------------
* Linux: CI_DRM_12744 -> Patchwork_114055v1
CI-20190529: 20190529
CI_DRM_12744: 2e4cac06e4de01a35626de676b9eeb474ae7ab5d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7160: 45da871dd2684227e93a2fc002b87dfc58bd5fd9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_114055v1: 2e4cac06e4de01a35626de676b9eeb474ae7ab5d @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114055v1/index.html
[-- Attachment #2: Type: text/html, Size: 17218 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/5] drm/i915/wm: warn about ilk_wm_sanitize() on display ver 9+
2023-02-15 14:28 ` Ville Syrjälä
@ 2023-02-16 15:19 ` Jani Nikula
0 siblings, 0 replies; 12+ messages in thread
From: Jani Nikula @ 2023-02-16 15:19 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, 15 Feb 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Feb 15, 2023 at 04:19:07PM +0200, Jani Nikula wrote:
>> The sanitization should be limited to PCH split platforms up to display
>> version 8. Warn and bail out otherwise.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/i9xx_wm.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> index f76ac64ebd71..50cdfe11192e 100644
>> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
>> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> @@ -3437,6 +3437,9 @@ void ilk_wm_sanitize(struct drm_i915_private *dev_priv)
>> if (!dev_priv->display.funcs.wm->optimize_watermarks)
>> return;
>>
>> + if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) >= 9))
>> + return;
>> +
>
> Oh you put it here. I guess that works too, though still
> a bit confusing that we call an ilk_ thing on skl+.
>
> Whatever you decide
Decided to push the lot as-is.
Thanks,
Jani.
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>> state = drm_atomic_state_alloc(&dev_priv->drm);
>> if (drm_WARN_ON(&dev_priv->drm, !state))
>> return;
>> --
>> 2.34.1
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-02-16 15:20 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-15 14:19 [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch] Jani Nikula
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 2/5] drm/i915/wm: warn about ilk_wm_sanitize() on display ver 9+ Jani Nikula
2023-02-15 14:28 ` Ville Syrjälä
2023-02-16 15:19 ` Jani Nikula
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 3/5] drm/i915/wm: move watermark debugfs to intel_wm.c Jani Nikula
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 4/5] drm/i915: rename intel_pm_types.h -> display/intel_wm_types.h Jani Nikula
2023-02-15 14:19 ` [Intel-gfx] [PATCH v3 5/5] drm/i915/wm: remove ILK+ nop funcs fallback Jani Nikula
2023-02-15 14:29 ` Ville Syrjälä
2023-02-15 14:27 ` [Intel-gfx] [PATCH v3 1/5] drm/i915/wm: move ILK watermark sanitization to i9xx_wm.[ch] Ville Syrjälä
2023-02-15 18:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/5] " Patchwork
2023-02-15 18:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-02-16 14:01 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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