[PATCH 0/7] Enable YCbCr420 format for VDSC

[PATCH 0/7] Enable YCbCr420 format for VDSC

[Suraj Kandpal]

This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.
There have been discussions prior to this series in which some patches
have gotten rb and can be found in the below link
https://patchwork.freedesktop.org/series/113729

Ankit Nautiyal (2):
  drm/dp_helper: Add helper to check DSC support with given o/p format
  drm/i915/dp: Check if DSC supports the given output_format

Suraj Kandpal (4):
  drm/i915: Adding the new registers for DSC
  drm/i915: Enable YCbCr420 for VDSC
  drm/i915/display: Fill in native_420 field
  drm/i915/vdsc: Check slice design requirement

Swati Sharma (1):
  drm/i915/dsc: Add debugfs entry to validate DSC output formats

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
 .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
 .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
 .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
 .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
 drivers/gpu/drm/i915/i915_reg.h               |  28 +++
 include/drm/display/drm_dp_helper.h           |  13 ++
 11 files changed, 442 insertions(+), 24 deletions(-)

-- 
2.25.1

[Intel-gfx] [PATCH 0/7] Enable YCbCr420 format for VDSC

[Suraj Kandpal]

This patch series aims to enable the YCbCr420 format
for DSC. Changes are mostly compute params related for
hdmi,dp and dsi along with the addition of new rc_tables
for native_420 and corresponding changes to macros used to
fetch them.
There have been discussions prior to this series in which some patches
have gotten rb and can be found in the below link
https://patchwork.freedesktop.org/series/113729

Ankit Nautiyal (2):
  drm/dp_helper: Add helper to check DSC support with given o/p format
  drm/i915/dp: Check if DSC supports the given output_format

Suraj Kandpal (4):
  drm/i915: Adding the new registers for DSC
  drm/i915: Enable YCbCr420 for VDSC
  drm/i915/display: Fill in native_420 field
  drm/i915/vdsc: Check slice design requirement

Swati Sharma (1):
  drm/i915/dsc: Add debugfs entry to validate DSC output formats

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
 .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
 .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
 .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
 .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
 drivers/gpu/drm/i915/i915_reg.h               |  28 +++
 include/drm/display/drm_dp_helper.h           |  13 ++
 11 files changed, 442 insertions(+), 24 deletions(-)

-- 
2.25.1

[PATCH 1/7] drm/dp_helper: Add helper to check DSC support with given o/p format

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Add helper to check if the DP sink supports DSC with the given
o/p format.

v2: Add documentation for the helper. (Uma Shankar)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 include/drm/display/drm_dp_helper.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index ab55453f2d2c..41da8eb4801e 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -194,6 +194,19 @@ drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
 		DP_DSC_SLICE_WIDTH_MULTIPLIER;
 }
 
+/*
+ * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format
+ * @dsc_dpcd : DSC-capability DPCDs of the sink
+ * @output_format: output_format which is to be checked
+ *
+ * Returns true if the sink supports DSC with the given output_format, false otherwise.
+ */
+static inline bool
+drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format)
+{
+	return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format;
+}
+
 /* Forward Error Correction Support on DP 1.4 */
 static inline bool
 drm_dp_sink_supports_fec(const u8 fec_capable)
-- 
2.25.1

[Intel-gfx] [PATCH 1/7] drm/dp_helper: Add helper to check DSC support with given o/p format

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Add helper to check if the DP sink supports DSC with the given
o/p format.

v2: Add documentation for the helper. (Uma Shankar)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 include/drm/display/drm_dp_helper.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index ab55453f2d2c..41da8eb4801e 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -194,6 +194,19 @@ drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
 		DP_DSC_SLICE_WIDTH_MULTIPLIER;
 }
 
+/*
+ * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format
+ * @dsc_dpcd : DSC-capability DPCDs of the sink
+ * @output_format: output_format which is to be checked
+ *
+ * Returns true if the sink supports DSC with the given output_format, false otherwise.
+ */
+static inline bool
+drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format)
+{
+	return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format;
+}
+
 /* Forward Error Correction Support on DP 1.4 */
 static inline bool
 drm_dp_sink_supports_fec(const u8 fec_capable)
-- 
2.25.1

[PATCH 2/7] drm/i915/dp: Check if DSC supports the given output_format

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Go with DSC only if the given output_format is supported.

v2: Use drm helper to get DSC format support for sink.

v3: remove drm_dp_dsc_compute_bpp.

Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fe98c7dec193..f2fb3ec2dd99 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1491,6 +1491,31 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 	return drm_dsc_compute_rc_parameters(vdsc_cfg);
 }
 
+static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
+					 enum intel_output_format output_format)
+{
+	u8 sink_dsc_format;
+
+	switch (output_format) {
+	case INTEL_OUTPUT_FORMAT_RGB:
+		sink_dsc_format = DP_DSC_RGB;
+		break;
+	case INTEL_OUTPUT_FORMAT_YCBCR444:
+		sink_dsc_format = DP_DSC_YCbCr444;
+		break;
+	case INTEL_OUTPUT_FORMAT_YCBCR420:
+		if (min(intel_dp_source_dsc_version_minor(intel_dp),
+			intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
+			return false;
+		sink_dsc_format = DP_DSC_YCbCr420_Native;
+		break;
+	default:
+		return false;
+	}
+
+	return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
+}
+
 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config,
 				struct drm_connector_state *conn_state,
@@ -1511,6 +1536,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
 		return -EINVAL;
 
+	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
+		return -EINVAL;
+
 	if (compute_pipe_bpp)
 		pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
 	else
-- 
2.25.1

[Intel-gfx] [PATCH 2/7] drm/i915/dp: Check if DSC supports the given output_format

[Suraj Kandpal]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Go with DSC only if the given output_format is supported.

v2: Use drm helper to get DSC format support for sink.

v3: remove drm_dp_dsc_compute_bpp.

Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fe98c7dec193..f2fb3ec2dd99 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1491,6 +1491,31 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 	return drm_dsc_compute_rc_parameters(vdsc_cfg);
 }
 
+static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
+					 enum intel_output_format output_format)
+{
+	u8 sink_dsc_format;
+
+	switch (output_format) {
+	case INTEL_OUTPUT_FORMAT_RGB:
+		sink_dsc_format = DP_DSC_RGB;
+		break;
+	case INTEL_OUTPUT_FORMAT_YCBCR444:
+		sink_dsc_format = DP_DSC_YCbCr444;
+		break;
+	case INTEL_OUTPUT_FORMAT_YCBCR420:
+		if (min(intel_dp_source_dsc_version_minor(intel_dp),
+			intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
+			return false;
+		sink_dsc_format = DP_DSC_YCbCr420_Native;
+		break;
+	default:
+		return false;
+	}
+
+	return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format);
+}
+
 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 				struct intel_crtc_state *pipe_config,
 				struct drm_connector_state *conn_state,
@@ -1511,6 +1536,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
 		return -EINVAL;
 
+	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
+		return -EINVAL;
+
 	if (compute_pipe_bpp)
 		pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
 	else
-- 
2.25.1

[PATCH 3/7] drm/i915: Adding the new registers for DSC

[Suraj Kandpal]

Adding new DSC register which are introducted MTL onwards

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 596efc940ee7..9e25e21d37e4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7715,6 +7715,8 @@ enum skl_power_gate {
 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
+#define  DSC_NATIVE_422_ENABLE		BIT(23)
+#define  DSC_NATIVE_420_ENABLE		BIT(22)
 #define  DSC_ALT_ICH_SEL		(1 << 20)
 #define  DSC_VBR_ENABLE			(1 << 19)
 #define  DSC_422_ENABLE			(1 << 18)
@@ -7959,6 +7961,32 @@ enum skl_power_gate {
 #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
 
+/* MTL Display Stream Compression registers */
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB	0x782B4
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB	0x783B4
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC	0x784B4
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC	0x785B4
+#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							   _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
+							   _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
+#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							   _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
+							   _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
+#define DSC_SL_BPG_OFFSET(offset)		((offset) << 27)
+
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB	0x782B8
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB	0x783B8
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC	0x784B8
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC	0x785B8
+#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							   _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
+							   _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
+#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							   _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
+							   _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
+#define DSC_NSL_BPG_OFFSET(offset)		((offset) << 16)
+#define DSC_SL_OFFSET_ADJ(offset)		((offset) << 0)
+
 /* Icelake Rate Control Buffer Threshold Registers */
 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
 #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
-- 
2.25.1

[Intel-gfx] [PATCH 3/7] drm/i915: Adding the new registers for DSC

[Suraj Kandpal]

Adding new DSC register which are introducted MTL onwards

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 596efc940ee7..9e25e21d37e4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7715,6 +7715,8 @@ enum skl_power_gate {
 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
+#define  DSC_NATIVE_422_ENABLE		BIT(23)
+#define  DSC_NATIVE_420_ENABLE		BIT(22)
 #define  DSC_ALT_ICH_SEL		(1 << 20)
 #define  DSC_VBR_ENABLE			(1 << 19)
 #define  DSC_422_ENABLE			(1 << 18)
@@ -7959,6 +7961,32 @@ enum skl_power_gate {
 #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
 #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
 
+/* MTL Display Stream Compression registers */
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB	0x782B4
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB	0x783B4
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC	0x784B4
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC	0x785B4
+#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							   _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
+							   _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
+#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							   _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
+							   _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
+#define DSC_SL_BPG_OFFSET(offset)		((offset) << 27)
+
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB	0x782B8
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB	0x783B8
+#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC	0x784B8
+#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC	0x785B8
+#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							   _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
+							   _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
+#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
+							   _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
+							   _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
+#define DSC_NSL_BPG_OFFSET(offset)		((offset) << 16)
+#define DSC_SL_OFFSET_ADJ(offset)		((offset) << 0)
+
 /* Icelake Rate Control Buffer Threshold Registers */
 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
 #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
-- 
2.25.1

[PATCH 4/7] drm/i915: Enable YCbCr420 for VDSC

[Suraj Kandpal]

Implementation of VDSC for YCbCr420.
Add QP tables for 8,10,12 BPC from rc_tables.h in intel_qp_tables.c
(Derived from C-Model, which is given along with DSC1.2a Spec from Vesa)
intel_lookup_range_min/max_qp functons need to take into account the
output format. Based on that appropriate qp table need to be chosen.
Other rc_parameters need to be set where currently values for 444 format
is hardcoded in calculate_rc_parameters( ).
vdsc_cfg struct needs to be filled with output format information, where
these are hardcoded for 444 format.
Bspec: 49259

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
---
 .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
 3 files changed, 180 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 6f8e4ec5c0fb..6e86c0971d24 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -17,6 +17,15 @@
 /* from BPP 6 to 36 in steps of 0.5 */
 #define RC_RANGE_QP444_12BPC_MAX_NUM_BPP	61
 
+/* from BPP 6 to 24 in steps of 0.5 */
+#define RC_RANGE_QP420_8BPC_MAX_NUM_BPP		17
+
+/* from BPP 6 to 30 in steps of 0.5 */
+#define RC_RANGE_QP420_10BPC_MAX_NUM_BPP	23
+
+/* from BPP 6 to 36 in steps of 0.5 */
+#define RC_RANGE_QP420_12BPC_MAX_NUM_BPP	29
+
 /*
  * These qp tables are as per the C model
  * and it has the rows pointing to bpps which increment
@@ -283,26 +292,182 @@ static const u8 rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC
 	  11, 11, 10, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4 }
 };
 
-#define PARAM_TABLE(_minmax, _bpc, _row, _col)  do { \
-	if (bpc == (_bpc)) \
-		return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+static const u8 rc_range_minqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 },
+	{ 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+	{ 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
+	{ 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
+	{ 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 0 },
+	{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1 },
+	{ 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 1, 1 },
+	{ 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 2, 2, 1 },
+	{ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 3, 3, 2, 1 },
+	{ 9, 8, 8, 7, 7, 7, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 2 },
+	{ 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3 }
+};
+
+static const u8 rc_range_maxqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {
+	{ 4, 4, 3, 3, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 4, 4, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+	{ 5, 5, 5, 5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+	{ 6, 6, 6, 6, 6, 5, 4, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0 },
+	{ 7, 7, 7, 7, 7, 5, 4, 3, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
+	{ 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 2, 2, 2, 1, 1, 0 },
+	{ 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1 },
+	{ 8, 8, 8, 8, 8, 7, 6, 5, 4, 4, 4, 3, 3, 2, 2, 2, 1 },
+	{ 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
+	{ 10, 10, 9, 9, 9, 8, 7, 6, 5, 5, 5, 4, 4, 3, 3, 2, 2 },
+	{ 10, 10, 10, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 2, 2 },
+	{ 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2 },
+	{ 11, 11, 11, 10, 9, 9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3, 2 },
+	{ 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4, 4, 4, 3 },
+	{ 14, 13, 13, 12, 11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4 }
+};
+
+static const u8 rc_range_minqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = {
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0 },
+	{ 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0 },
+	{ 7, 7, 7, 7, 7, 6, 5, 5, 5, 5, 5, 4, 3, 3, 2, 2, 1, 1, 1, 1, 1, 0, 0 },
+	{ 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 2, 2, 1, 1, 1, 0 },
+	{ 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 4, 4, 4, 3, 2, 2, 2, 1, 1, 1, 0 },
+	{ 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 2, 1, 1 },
+	{ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1 },
+	{ 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
+	{ 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 7, 6, 6, 5, 4, 4, 3, 3, 2, 1 },
+	{ 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 2, 1 },
+	{ 13, 12, 12, 11, 11, 11, 11, 11, 11, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4, 3, 3,
+	  2, 2 },
+	{ 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 10, 9, 8, 8, 7, 6, 6, 5,
+	  5, 4, 4 }
+};
+
+static const u8 rc_range_maxqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = {
+	{ 8, 8, 7, 6, 4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 8, 8, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
+	{ 9, 9, 9, 8, 8, 7, 6, 5, 4, 3, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0 },
+	{ 10, 10, 10, 9, 9, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 0,
+	  0 },
+	{ 11, 11, 11, 10, 10, 8, 7, 6, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 1, 1, 1,
+	  0 },
+	{ 11, 11, 11, 10, 10, 9, 8, 7, 6, 6, 6, 5, 4, 4, 3, 3, 2, 2, 2, 2, 2, 1,
+	  1 },
+	{ 11, 11, 11, 11, 11, 10, 9, 8, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 3, 2, 2, 2,
+	  1 },
+	{ 12, 12, 12, 12, 12, 11, 10, 9, 8, 8, 8, 7, 6, 5, 5, 4, 3, 3, 3, 2, 2,
+	  2, 1 },
+	{ 13, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 3,
+	  2, 2 },
+	{ 14, 14, 13, 13, 13, 12, 11, 10, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3,
+	  2, 2 },
+	{ 14, 14, 14, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4, 4,
+	  3, 3, 2 },
+	{ 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4,
+	  4, 3, 2 },
+	{ 15, 15, 15, 14, 13, 13, 13, 12, 11, 11, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4,
+	  4, 3, 2 },
+	{ 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4,
+	  4, 3, 3 },
+	{ 18, 17, 17, 16, 15, 15, 14, 13, 13, 12, 11, 11, 11, 10, 9, 9, 8, 7, 7,
+	  6, 6, 5, 5 }
+};
+
+static const u8 rc_range_minqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = {
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0 },
+	{ 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0 },
+	{ 9, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 1, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0 },
+	{ 10, 9, 9, 8, 8, 8, 7, 7, 6, 6, 6, 5, 5, 4, 4, 3, 2, 2, 1, 1, 1, 0, 0, 0,
+	  0, 0, 0, 0, 0 },
+	{ 11, 10, 10, 10, 10, 9, 9, 8, 7, 6, 6, 6, 6, 5, 5, 4, 3, 3, 3, 2, 2, 1,
+	  0, 0, 0, 0, 0, 0, 0 },
+	{ 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 7, 6, 5, 5, 4, 4, 3, 3, 3, 2,
+	  1, 1, 0, 0, 0, 0, 0 },
+	{ 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 7, 6, 5, 5, 5, 5, 4, 3, 3,
+	  2, 1, 1, 1, 1, 1, 0 },
+	{ 11, 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 8, 8, 7, 6, 6, 5, 4, 4,
+	  3, 2, 2, 1, 1, 1, 1, 1 },
+	{ 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5,
+	  5, 4, 4, 2, 2, 1, 1, 1, 1 },
+	{ 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6,
+	  5, 4, 4, 3, 2, 2, 1, 1, 1 },
+	{ 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7,
+	  6, 5, 4, 3, 3, 2, 2, 1, 1 },
+	{ 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12, 11, 10, 10, 9, 8, 8,
+	  7, 7, 6, 5, 4, 3, 3, 2, 2, 1 },
+	{ 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
+	  7, 7, 6, 5, 4, 4, 3, 2, 2, 1 },
+	{ 15, 15, 15, 15, 15, 15, 15, 15, 15, 14, 13, 13, 12, 11, 11, 10, 9, 9, 8,
+	  8, 7, 6, 6, 5, 4, 4, 3, 3, 2 },
+	{ 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 14, 13, 12, 12, 11, 10,
+	  10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4 }
+};
+
+static const u8 rc_range_maxqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = {
+	{ 11, 10, 9, 8, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0,
+	  0, 0, 0, 0, 0, 0 },
+	{ 12, 11, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1,
+	  1, 0, 0, 0, 0, 0, 0 },
+	{ 13, 12, 12, 11, 11, 10, 9, 8, 7, 6, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1,
+	  1, 0, 0, 0, 0, 0, 0 },
+	{ 14, 13, 13, 12, 12, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1,
+	  1, 1, 0, 0, 0, 0, 0 },
+	{ 15, 14, 14, 13, 13, 11, 10, 9, 8, 7, 7, 7, 7, 6, 6, 5, 4, 4, 4, 3, 3, 2,
+	  1, 1, 1, 0, 0, 0, 0 },
+	{ 15, 15, 15, 14, 14, 13, 12, 11, 10, 10, 10, 9, 8, 7, 6, 6, 5, 5, 4, 4,
+	  4, 3, 2, 2, 1, 1, 0, 0, 0 },
+	{ 15, 15, 15, 15, 15, 14, 13, 12, 11, 11, 11, 10, 9, 8, 7, 6, 6, 6, 6, 5,
+	  4, 4, 3, 2, 2, 2, 1, 1, 0 },
+	{ 16, 16, 16, 16, 16, 15, 14, 13, 12, 12, 12, 11, 10, 9, 9, 8, 7, 7, 6, 5,
+	  5, 4, 3, 3, 2, 2, 2, 1, 1 },
+	{ 17, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8, 7,
+	  6, 6, 5, 5, 3, 3, 2, 2, 1, 1 },
+	{ 18, 18, 17, 17, 17, 16, 15, 14, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
+	  7, 6, 5, 5, 4, 3, 3, 2, 2, 1 },
+	{ 18, 18, 18, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 10, 9, 9, 8,
+	  8, 7, 6, 5, 4, 4, 3, 3, 2, 2 },
+	{ 19, 19, 18, 18, 17, 17, 16, 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 9,
+	  9, 8, 8, 7, 6, 5, 4, 4, 3, 3, 2 },
+	{ 19, 19, 19, 18, 17, 17, 17, 16, 15, 15, 14, 13, 13, 12, 12, 11, 10, 9,
+	  9, 8, 8, 7, 6, 5, 5, 4, 3, 3, 2 },
+	{ 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10,
+	  9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3 },
+	{ 22, 21, 21, 20, 19, 19, 18, 17, 17, 16, 15, 15, 15, 14, 13, 13, 12, 11,
+	  11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5 }
+};
+
+#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420)  do { \
+	if (bpc == (_bpc)) {	\
+		if (_is_420)	\
+			return rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
+		else	\
+			return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+	}	\
 } while (0)
 
-u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i)
+u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420)
 {
-	PARAM_TABLE(min, 8, buf_i, bpp_i);
-	PARAM_TABLE(min, 10, buf_i, bpp_i);
-	PARAM_TABLE(min, 12, buf_i, bpp_i);
+	PARAM_TABLE(min, 8, buf_i, bpp_i, is_420);
+	PARAM_TABLE(min, 10, buf_i, bpp_i, is_420);
+	PARAM_TABLE(min, 12, buf_i, bpp_i, is_420);
 
 	MISSING_CASE(bpc);
 	return 0;
 }
 
-u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i)
+u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420)
 {
-	PARAM_TABLE(max, 8, buf_i, bpp_i);
-	PARAM_TABLE(max, 10, buf_i, bpp_i);
-	PARAM_TABLE(max, 12, buf_i, bpp_i);
+	PARAM_TABLE(max, 8, buf_i, bpp_i, is_420);
+	PARAM_TABLE(max, 10, buf_i, bpp_i, is_420);
+	PARAM_TABLE(max, 12, buf_i, bpp_i, is_420);
 
 	MISSING_CASE(bpc);
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h b/drivers/gpu/drm/i915/display/intel_qp_tables.h
index 9fb3c36bd7c6..a9ff9ca29938 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.h
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h
@@ -8,7 +8,7 @@
 
 #include <linux/types.h>
 
-u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i);
-u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i);
+u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420);
+u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..ed16f63d6355 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -422,9 +422,9 @@ calculate_rc_params(struct rc_parameters *rc,
 	for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
 		/* Read range_minqp and range_max_qp from qp tables */
 		rc->rc_range_params[buf_i].range_min_qp =
-			intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
+			intel_lookup_range_min_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);
 		rc->rc_range_params[buf_i].range_max_qp =
-			intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
+			intel_lookup_range_max_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);
 
 		/* Calculate range_bgp_offset */
 		if (bpp <= 6) {
-- 
2.25.1

[Intel-gfx] [PATCH 4/7] drm/i915: Enable YCbCr420 for VDSC

[Suraj Kandpal]

Implementation of VDSC for YCbCr420.
Add QP tables for 8,10,12 BPC from rc_tables.h in intel_qp_tables.c
(Derived from C-Model, which is given along with DSC1.2a Spec from Vesa)
intel_lookup_range_min/max_qp functons need to take into account the
output format. Based on that appropriate qp table need to be chosen.
Other rc_parameters need to be set where currently values for 444 format
is hardcoded in calculate_rc_parameters( ).
vdsc_cfg struct needs to be filled with output format information, where
these are hardcoded for 444 format.
Bspec: 49259

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
---
 .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
 3 files changed, 180 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c
index 6f8e4ec5c0fb..6e86c0971d24 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -17,6 +17,15 @@
 /* from BPP 6 to 36 in steps of 0.5 */
 #define RC_RANGE_QP444_12BPC_MAX_NUM_BPP	61
 
+/* from BPP 6 to 24 in steps of 0.5 */
+#define RC_RANGE_QP420_8BPC_MAX_NUM_BPP		17
+
+/* from BPP 6 to 30 in steps of 0.5 */
+#define RC_RANGE_QP420_10BPC_MAX_NUM_BPP	23
+
+/* from BPP 6 to 36 in steps of 0.5 */
+#define RC_RANGE_QP420_12BPC_MAX_NUM_BPP	29
+
 /*
  * These qp tables are as per the C model
  * and it has the rows pointing to bpps which increment
@@ -283,26 +292,182 @@ static const u8 rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC
 	  11, 11, 10, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4 }
 };
 
-#define PARAM_TABLE(_minmax, _bpc, _row, _col)  do { \
-	if (bpc == (_bpc)) \
-		return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+static const u8 rc_range_minqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 },
+	{ 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+	{ 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
+	{ 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
+	{ 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 0 },
+	{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1 },
+	{ 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 1, 1 },
+	{ 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 2, 2, 1 },
+	{ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 3, 3, 2, 1 },
+	{ 9, 8, 8, 7, 7, 7, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 2 },
+	{ 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3 }
+};
+
+static const u8 rc_range_maxqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {
+	{ 4, 4, 3, 3, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 4, 4, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+	{ 5, 5, 5, 5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+	{ 6, 6, 6, 6, 6, 5, 4, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0 },
+	{ 7, 7, 7, 7, 7, 5, 4, 3, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
+	{ 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 2, 2, 2, 1, 1, 0 },
+	{ 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1 },
+	{ 8, 8, 8, 8, 8, 7, 6, 5, 4, 4, 4, 3, 3, 2, 2, 2, 1 },
+	{ 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
+	{ 10, 10, 9, 9, 9, 8, 7, 6, 5, 5, 5, 4, 4, 3, 3, 2, 2 },
+	{ 10, 10, 10, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 2, 2 },
+	{ 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2 },
+	{ 11, 11, 11, 10, 9, 9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3, 2 },
+	{ 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4, 4, 4, 3 },
+	{ 14, 13, 13, 12, 11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4 }
+};
+
+static const u8 rc_range_minqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = {
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0 },
+	{ 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0 },
+	{ 7, 7, 7, 7, 7, 6, 5, 5, 5, 5, 5, 4, 3, 3, 2, 2, 1, 1, 1, 1, 1, 0, 0 },
+	{ 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 2, 2, 1, 1, 1, 0 },
+	{ 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 4, 4, 4, 3, 2, 2, 2, 1, 1, 1, 0 },
+	{ 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 2, 1, 1 },
+	{ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1 },
+	{ 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
+	{ 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 7, 6, 6, 5, 4, 4, 3, 3, 2, 1 },
+	{ 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 2, 1 },
+	{ 13, 12, 12, 11, 11, 11, 11, 11, 11, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4, 3, 3,
+	  2, 2 },
+	{ 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 10, 9, 8, 8, 7, 6, 6, 5,
+	  5, 4, 4 }
+};
+
+static const u8 rc_range_maxqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = {
+	{ 8, 8, 7, 6, 4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 8, 8, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
+	{ 9, 9, 9, 8, 8, 7, 6, 5, 4, 3, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0 },
+	{ 10, 10, 10, 9, 9, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 0,
+	  0 },
+	{ 11, 11, 11, 10, 10, 8, 7, 6, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 1, 1, 1,
+	  0 },
+	{ 11, 11, 11, 10, 10, 9, 8, 7, 6, 6, 6, 5, 4, 4, 3, 3, 2, 2, 2, 2, 2, 1,
+	  1 },
+	{ 11, 11, 11, 11, 11, 10, 9, 8, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 3, 2, 2, 2,
+	  1 },
+	{ 12, 12, 12, 12, 12, 11, 10, 9, 8, 8, 8, 7, 6, 5, 5, 4, 3, 3, 3, 2, 2,
+	  2, 1 },
+	{ 13, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 3,
+	  2, 2 },
+	{ 14, 14, 13, 13, 13, 12, 11, 10, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3,
+	  2, 2 },
+	{ 14, 14, 14, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4, 4,
+	  3, 3, 2 },
+	{ 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4,
+	  4, 3, 2 },
+	{ 15, 15, 15, 14, 13, 13, 13, 12, 11, 11, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4,
+	  4, 3, 2 },
+	{ 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4,
+	  4, 3, 3 },
+	{ 18, 17, 17, 16, 15, 15, 14, 13, 13, 12, 11, 11, 11, 10, 9, 9, 8, 7, 7,
+	  6, 6, 5, 5 }
+};
+
+static const u8 rc_range_minqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = {
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0 },
+	{ 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0 },
+	{ 9, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 1, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0 },
+	{ 10, 9, 9, 8, 8, 8, 7, 7, 6, 6, 6, 5, 5, 4, 4, 3, 2, 2, 1, 1, 1, 0, 0, 0,
+	  0, 0, 0, 0, 0 },
+	{ 11, 10, 10, 10, 10, 9, 9, 8, 7, 6, 6, 6, 6, 5, 5, 4, 3, 3, 3, 2, 2, 1,
+	  0, 0, 0, 0, 0, 0, 0 },
+	{ 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 7, 6, 5, 5, 4, 4, 3, 3, 3, 2,
+	  1, 1, 0, 0, 0, 0, 0 },
+	{ 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 7, 6, 5, 5, 5, 5, 4, 3, 3,
+	  2, 1, 1, 1, 1, 1, 0 },
+	{ 11, 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 8, 8, 7, 6, 6, 5, 4, 4,
+	  3, 2, 2, 1, 1, 1, 1, 1 },
+	{ 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5,
+	  5, 4, 4, 2, 2, 1, 1, 1, 1 },
+	{ 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6,
+	  5, 4, 4, 3, 2, 2, 1, 1, 1 },
+	{ 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7,
+	  6, 5, 4, 3, 3, 2, 2, 1, 1 },
+	{ 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12, 11, 10, 10, 9, 8, 8,
+	  7, 7, 6, 5, 4, 3, 3, 2, 2, 1 },
+	{ 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
+	  7, 7, 6, 5, 4, 4, 3, 2, 2, 1 },
+	{ 15, 15, 15, 15, 15, 15, 15, 15, 15, 14, 13, 13, 12, 11, 11, 10, 9, 9, 8,
+	  8, 7, 6, 6, 5, 4, 4, 3, 3, 2 },
+	{ 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 14, 13, 12, 12, 11, 10,
+	  10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4 }
+};
+
+static const u8 rc_range_maxqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = {
+	{ 11, 10, 9, 8, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0,
+	  0, 0, 0, 0, 0, 0 },
+	{ 12, 11, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1,
+	  1, 0, 0, 0, 0, 0, 0 },
+	{ 13, 12, 12, 11, 11, 10, 9, 8, 7, 6, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1,
+	  1, 0, 0, 0, 0, 0, 0 },
+	{ 14, 13, 13, 12, 12, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1,
+	  1, 1, 0, 0, 0, 0, 0 },
+	{ 15, 14, 14, 13, 13, 11, 10, 9, 8, 7, 7, 7, 7, 6, 6, 5, 4, 4, 4, 3, 3, 2,
+	  1, 1, 1, 0, 0, 0, 0 },
+	{ 15, 15, 15, 14, 14, 13, 12, 11, 10, 10, 10, 9, 8, 7, 6, 6, 5, 5, 4, 4,
+	  4, 3, 2, 2, 1, 1, 0, 0, 0 },
+	{ 15, 15, 15, 15, 15, 14, 13, 12, 11, 11, 11, 10, 9, 8, 7, 6, 6, 6, 6, 5,
+	  4, 4, 3, 2, 2, 2, 1, 1, 0 },
+	{ 16, 16, 16, 16, 16, 15, 14, 13, 12, 12, 12, 11, 10, 9, 9, 8, 7, 7, 6, 5,
+	  5, 4, 3, 3, 2, 2, 2, 1, 1 },
+	{ 17, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8, 7,
+	  6, 6, 5, 5, 3, 3, 2, 2, 1, 1 },
+	{ 18, 18, 17, 17, 17, 16, 15, 14, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
+	  7, 6, 5, 5, 4, 3, 3, 2, 2, 1 },
+	{ 18, 18, 18, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 10, 9, 9, 8,
+	  8, 7, 6, 5, 4, 4, 3, 3, 2, 2 },
+	{ 19, 19, 18, 18, 17, 17, 16, 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 9,
+	  9, 8, 8, 7, 6, 5, 4, 4, 3, 3, 2 },
+	{ 19, 19, 19, 18, 17, 17, 17, 16, 15, 15, 14, 13, 13, 12, 12, 11, 10, 9,
+	  9, 8, 8, 7, 6, 5, 5, 4, 3, 3, 2 },
+	{ 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10,
+	  9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3 },
+	{ 22, 21, 21, 20, 19, 19, 18, 17, 17, 16, 15, 15, 15, 14, 13, 13, 12, 11,
+	  11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5 }
+};
+
+#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420)  do { \
+	if (bpc == (_bpc)) {	\
+		if (_is_420)	\
+			return rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
+		else	\
+			return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+	}	\
 } while (0)
 
-u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i)
+u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420)
 {
-	PARAM_TABLE(min, 8, buf_i, bpp_i);
-	PARAM_TABLE(min, 10, buf_i, bpp_i);
-	PARAM_TABLE(min, 12, buf_i, bpp_i);
+	PARAM_TABLE(min, 8, buf_i, bpp_i, is_420);
+	PARAM_TABLE(min, 10, buf_i, bpp_i, is_420);
+	PARAM_TABLE(min, 12, buf_i, bpp_i, is_420);
 
 	MISSING_CASE(bpc);
 	return 0;
 }
 
-u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i)
+u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420)
 {
-	PARAM_TABLE(max, 8, buf_i, bpp_i);
-	PARAM_TABLE(max, 10, buf_i, bpp_i);
-	PARAM_TABLE(max, 12, buf_i, bpp_i);
+	PARAM_TABLE(max, 8, buf_i, bpp_i, is_420);
+	PARAM_TABLE(max, 10, buf_i, bpp_i, is_420);
+	PARAM_TABLE(max, 12, buf_i, bpp_i, is_420);
 
 	MISSING_CASE(bpc);
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h b/drivers/gpu/drm/i915/display/intel_qp_tables.h
index 9fb3c36bd7c6..a9ff9ca29938 100644
--- a/drivers/gpu/drm/i915/display/intel_qp_tables.h
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h
@@ -8,7 +8,7 @@
 
 #include <linux/types.h>
 
-u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i);
-u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i);
+u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool is_420);
+u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool is_420);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..ed16f63d6355 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -422,9 +422,9 @@ calculate_rc_params(struct rc_parameters *rc,
 	for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
 		/* Read range_minqp and range_max_qp from qp tables */
 		rc->rc_range_params[buf_i].range_min_qp =
-			intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
+			intel_lookup_range_min_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);
 		rc->rc_range_params[buf_i].range_max_qp =
-			intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
+			intel_lookup_range_max_qp(bpc, buf_i, bpp_i, vdsc_cfg->native_420);
 
 		/* Calculate range_bgp_offset */
 		if (bpp <= 6) {
-- 
2.25.1

[PATCH 5/7] drm/i915/display: Fill in native_420 field

[Suraj Kandpal]

Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.

---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vds_cfg when native_420 is true

---v3
-adding display version check to solve igt issue

--v7
-remove is_pipe_dsc check as its always true for D14 [Jani]

--v10
-keep sink capability check [Jani]
-move from !(x == y  || w == z) to x !=y && w != z [Jani]

--v11
-avoid native_420 computation if not gen14 [Uma]

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c    |  2 -
 drivers/gpu/drm/i915/display/intel_dp.c   |  7 ++-
 drivers/gpu/drm/i915/display/intel_vdsc.c | 74 ++++++++++++++++++++++-
 3 files changed, 75 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 05e749861658..7065203460d3 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1534,8 +1534,6 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 	if (crtc_state->dsc.slice_count > 1)
 		crtc_state->dsc.dsc_split = true;
 
-	vdsc_cfg->convert_rgb = true;
-
 	/* FIXME: initialize from VBT */
 	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f2fb3ec2dd99..95e9d0365e23 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1466,9 +1466,10 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 	vdsc_cfg->dsc_version_minor =
 		min(intel_dp_source_dsc_version_minor(intel_dp),
 		    intel_dp_sink_dsc_version_minor(intel_dp));
-
-	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
-		DP_DSC_RGB;
+	if (vdsc_cfg->convert_rgb)
+		vdsc_cfg->convert_rgb =
+			intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
+			DP_DSC_RGB;
 
 	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
 	if (!line_buf_depth) {
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ed16f63d6355..32997c9773aa 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -460,14 +460,50 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 					     pipe_config->dsc.slice_count);
-
-	/* Gen 11 does not support YCbCr */
+	/*
+	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
+	 * else 1
+	 */
+	vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
+				pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444;
+
+	if (DISPLAY_VER(dev_priv) >= 14 &&
+	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		vdsc_cfg->native_420 = true;
+	/* We do not support YcBCr422 as of now */
+	vdsc_cfg->native_422 = false;
 	vdsc_cfg->simple_422 = false;
 	/* Gen 11 does not support VBR */
 	vdsc_cfg->vbr_enable = false;
 
 	/* Gen 11 only supports integral values of bpp */
 	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+
+	/*
+	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set:
+	 * -We need to double the current bpp.
+	 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
+	 * height < 8.
+	 * -second_line_offset_adj is 512 as shown by emperical values to yeild best chroma
+	 * preservation in second line.
+	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
+	 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
+	 * fractional bits.
+	 */
+	if (vdsc_cfg->native_420) {
+		vdsc_cfg->bits_per_pixel <<= 1;
+
+		if (vdsc_cfg->slice_height >= 8)
+			vdsc_cfg->second_line_bpg_offset = 12;
+		else
+			vdsc_cfg->second_line_bpg_offset =
+				2 * (vdsc_cfg->slice_height - 1);
+
+		vdsc_cfg->second_line_offset_adj = 512;
+		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
+							vdsc_cfg->slice_height - 1);
+	}
+
 	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 
 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
@@ -594,8 +630,13 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_VER_MIN_SHIFT |
 		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
 		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
-	if (vdsc_cfg->dsc_version_minor == 2)
+	if (vdsc_cfg->dsc_version_minor == 2) {
 		pps_val |= DSC_ALT_ICH_SEL;
+		if (vdsc_cfg->native_420)
+			pps_val |= DSC_NATIVE_420_ENABLE;
+		if (vdsc_cfg->native_422)
+			pps_val |= DSC_NATIVE_422_ENABLE;
+	}
 	if (vdsc_cfg->block_pred_enable)
 		pps_val |= DSC_BLOCK_PREDICTION;
 	if (vdsc_cfg->convert_rgb)
@@ -906,6 +947,33 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 				       pps_val);
 	}
 
+	if (DISPLAY_VER(dev_priv) >= 14) {
+		/* Populate PICTURE_PARAMETER_SET_17 registers */
+		pps_val = 0;
+		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
+		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
+		intel_de_write(dev_priv,
+			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
+			       pps_val);
+		if (crtc_state->dsc.dsc_split)
+			intel_de_write(dev_priv,
+				       MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
+				       pps_val);
+
+		/* Populate PICTURE_PARAMETER_SET_18 registers */
+		pps_val = 0;
+		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
+			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
+		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
+		intel_de_write(dev_priv,
+			       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
+			       pps_val);
+		if (crtc_state->dsc.dsc_split)
+			intel_de_write(dev_priv,
+				       MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
+				       pps_val);
+	}
+
 	/* Populate the RC_BUF_THRESH registers */
 	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
-- 
2.25.1

[Intel-gfx] [PATCH 5/7] drm/i915/display: Fill in native_420 field

[Suraj Kandpal]

Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.

---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vds_cfg when native_420 is true

---v3
-adding display version check to solve igt issue

--v7
-remove is_pipe_dsc check as its always true for D14 [Jani]

--v10
-keep sink capability check [Jani]
-move from !(x == y  || w == z) to x !=y && w != z [Jani]

--v11
-avoid native_420 computation if not gen14 [Uma]

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c    |  2 -
 drivers/gpu/drm/i915/display/intel_dp.c   |  7 ++-
 drivers/gpu/drm/i915/display/intel_vdsc.c | 74 ++++++++++++++++++++++-
 3 files changed, 75 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 05e749861658..7065203460d3 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1534,8 +1534,6 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 	if (crtc_state->dsc.slice_count > 1)
 		crtc_state->dsc.dsc_split = true;
 
-	vdsc_cfg->convert_rgb = true;
-
 	/* FIXME: initialize from VBT */
 	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f2fb3ec2dd99..95e9d0365e23 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1466,9 +1466,10 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 	vdsc_cfg->dsc_version_minor =
 		min(intel_dp_source_dsc_version_minor(intel_dp),
 		    intel_dp_sink_dsc_version_minor(intel_dp));
-
-	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
-		DP_DSC_RGB;
+	if (vdsc_cfg->convert_rgb)
+		vdsc_cfg->convert_rgb =
+			intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
+			DP_DSC_RGB;
 
 	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
 	if (!line_buf_depth) {
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ed16f63d6355..32997c9773aa 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -460,14 +460,50 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 					     pipe_config->dsc.slice_count);
-
-	/* Gen 11 does not support YCbCr */
+	/*
+	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
+	 * else 1
+	 */
+	vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
+				pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444;
+
+	if (DISPLAY_VER(dev_priv) >= 14 &&
+	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		vdsc_cfg->native_420 = true;
+	/* We do not support YcBCr422 as of now */
+	vdsc_cfg->native_422 = false;
 	vdsc_cfg->simple_422 = false;
 	/* Gen 11 does not support VBR */
 	vdsc_cfg->vbr_enable = false;
 
 	/* Gen 11 only supports integral values of bpp */
 	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+
+	/*
+	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set:
+	 * -We need to double the current bpp.
+	 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
+	 * height < 8.
+	 * -second_line_offset_adj is 512 as shown by emperical values to yeild best chroma
+	 * preservation in second line.
+	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
+	 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
+	 * fractional bits.
+	 */
+	if (vdsc_cfg->native_420) {
+		vdsc_cfg->bits_per_pixel <<= 1;
+
+		if (vdsc_cfg->slice_height >= 8)
+			vdsc_cfg->second_line_bpg_offset = 12;
+		else
+			vdsc_cfg->second_line_bpg_offset =
+				2 * (vdsc_cfg->slice_height - 1);
+
+		vdsc_cfg->second_line_offset_adj = 512;
+		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
+							vdsc_cfg->slice_height - 1);
+	}
+
 	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 
 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
@@ -594,8 +630,13 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_VER_MIN_SHIFT |
 		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
 		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
-	if (vdsc_cfg->dsc_version_minor == 2)
+	if (vdsc_cfg->dsc_version_minor == 2) {
 		pps_val |= DSC_ALT_ICH_SEL;
+		if (vdsc_cfg->native_420)
+			pps_val |= DSC_NATIVE_420_ENABLE;
+		if (vdsc_cfg->native_422)
+			pps_val |= DSC_NATIVE_422_ENABLE;
+	}
 	if (vdsc_cfg->block_pred_enable)
 		pps_val |= DSC_BLOCK_PREDICTION;
 	if (vdsc_cfg->convert_rgb)
@@ -906,6 +947,33 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 				       pps_val);
 	}
 
+	if (DISPLAY_VER(dev_priv) >= 14) {
+		/* Populate PICTURE_PARAMETER_SET_17 registers */
+		pps_val = 0;
+		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
+		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
+		intel_de_write(dev_priv,
+			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
+			       pps_val);
+		if (crtc_state->dsc.dsc_split)
+			intel_de_write(dev_priv,
+				       MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
+				       pps_val);
+
+		/* Populate PICTURE_PARAMETER_SET_18 registers */
+		pps_val = 0;
+		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
+			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
+		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
+		intel_de_write(dev_priv,
+			       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
+			       pps_val);
+		if (crtc_state->dsc.dsc_split)
+			intel_de_write(dev_priv,
+				       MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
+				       pps_val);
+	}
+
 	/* Populate the RC_BUF_THRESH registers */
 	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
-- 
2.25.1

[PATCH 6/7] drm/i915/vdsc: Check slice design requirement

[Suraj Kandpal]

Add function to check if slice design requirements are being
met as defined in Bspec: 49259 in the section
Slice Design Requirement

--v7
-remove full bspec link [Jani]
-rename intel_dsc_check_slice_design_req to
intel_dsc_slice_dimensions_valid [Jani]

--v8
-fix condition to check if slice width and height are
of two
-fix minimum pixel in slice condition

--v10
-condition should be < rather then >= [Uma]

Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 32997c9773aa..a9585f493318 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -447,6 +447,29 @@ calculate_rc_params(struct rc_parameters *rc,
 	}
 }
 
+static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config,
+					    struct drm_dsc_config *vdsc_cfg)
+{
+	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
+	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
+		if (vdsc_cfg->slice_height > 4095)
+			return -EINVAL;
+		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000)
+			return -EINVAL;
+	} else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+		if (vdsc_cfg->slice_width % 2)
+			return -EINVAL;
+		if (vdsc_cfg->slice_height % 2)
+			return -EINVAL;
+		if (vdsc_cfg->slice_height > 4094)
+			return -EINVAL;
+		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000)
+			return -EINVAL;
+	}
+
+	return 0;
+}
+
 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 {
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -455,11 +478,20 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
 	const struct rc_parameters *rc_params;
 	struct rc_parameters *rc = NULL;
+	int err;
 	u8 i = 0;
 
 	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 					     pipe_config->dsc.slice_count);
+
+	err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
+
+	if (err) {
+		drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n");
+		return err;
+	}
+
 	/*
 	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
 	 * else 1
-- 
2.25.1

[Intel-gfx] [PATCH 6/7] drm/i915/vdsc: Check slice design requirement

[Suraj Kandpal]

Add function to check if slice design requirements are being
met as defined in Bspec: 49259 in the section
Slice Design Requirement

--v7
-remove full bspec link [Jani]
-rename intel_dsc_check_slice_design_req to
intel_dsc_slice_dimensions_valid [Jani]

--v8
-fix condition to check if slice width and height are
of two
-fix minimum pixel in slice condition

--v10
-condition should be < rather then >= [Uma]

Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 32997c9773aa..a9585f493318 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -447,6 +447,29 @@ calculate_rc_params(struct rc_parameters *rc,
 	}
 }
 
+static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config,
+					    struct drm_dsc_config *vdsc_cfg)
+{
+	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
+	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
+		if (vdsc_cfg->slice_height > 4095)
+			return -EINVAL;
+		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000)
+			return -EINVAL;
+	} else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
+		if (vdsc_cfg->slice_width % 2)
+			return -EINVAL;
+		if (vdsc_cfg->slice_height % 2)
+			return -EINVAL;
+		if (vdsc_cfg->slice_height > 4094)
+			return -EINVAL;
+		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000)
+			return -EINVAL;
+	}
+
+	return 0;
+}
+
 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 {
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
@@ -455,11 +478,20 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
 	const struct rc_parameters *rc_params;
 	struct rc_parameters *rc = NULL;
+	int err;
 	u8 i = 0;
 
 	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 					     pipe_config->dsc.slice_count);
+
+	err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
+
+	if (err) {
+		drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not met\n");
+		return err;
+	}
+
 	/*
 	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
 	 * else 1
-- 
2.25.1

[PATCH 7/7] drm/i915/dsc: Add debugfs entry to validate DSC output formats

[Suraj Kandpal]

From: Swati Sharma <swati2.sharma@intel.com>

DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show
to depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444).
Also, new debugfs entry is created to enforce output format. This is
required because of our driver policy. For ex. if a mode is supported
in both RGB and YCbCr420 output formats by the sink, our policy is to
try RGB first and fall back to YCbCr420, if mode cannot be shown
using RGB. So, to test other output formats like YCbCr420 or YCbCr444,
we need a debugfs entry (force_dsc_output_format) to force this
output format.

v2: -Func name changed to intel_output_format_name() (Jani N)
    -Return forced o/p format from intel_dp_output_format() (Jani N)
v3: -output_format_str[] to remain static (Jani N)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 .../drm/i915/display/intel_crtc_state_dump.c  |  4 +-
 .../drm/i915/display/intel_crtc_state_dump.h  |  2 +
 .../drm/i915/display/intel_display_debugfs.c  | 78 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  4 +
 5 files changed, 87 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 2422d6ef5777..45655efc9468 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -121,7 +121,7 @@ static const char * const output_format_str[] = {
 	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
 };
 
-static const char *output_formats(enum intel_output_format format)
+const char *intel_output_format_name(enum intel_output_format format)
 {
 	if (format >= ARRAY_SIZE(output_format_str))
 		return "invalid";
@@ -179,7 +179,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		    "active: %s, output_types: %s (0x%x), output format: %s\n",
 		    str_yes_no(pipe_config->hw.active),
 		    buf, pipe_config->output_types,
-		    output_formats(pipe_config->output_format));
+		    intel_output_format_name(pipe_config->output_format));
 
 	drm_dbg_kms(&i915->drm,
 		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
index 9399c35b7e5e..780f3f1190d7 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
@@ -8,9 +8,11 @@
 
 struct intel_crtc_state;
 struct intel_atomic_state;
+enum intel_output_format;
 
 void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
 			   struct intel_atomic_state *state,
 			   const char *context);
+const char *intel_output_format_name(enum intel_output_format format);
 
 #endif /* __INTEL_CRTC_STATE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 49a7c00c0664..7ebac255865f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -12,6 +12,7 @@
 #include "i915_irq.h"
 #include "i915_reg.h"
 #include "intel_de.h"
+#include "intel_crtc_state_dump.h"
 #include "intel_display_debugfs.h"
 #include "intel_display_power.h"
 #include "intel_display_power_well.h"
@@ -1750,6 +1751,13 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 			   str_yes_no(crtc_state->dsc.compression_enable));
 		seq_printf(m, "DSC_Sink_Support: %s\n",
 			   str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
+		seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n",
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_RGB)),
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_YCbCr420_Native)),
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_YCbCr444)));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
 		if (!intel_dp_is_edp(intel_dp))
@@ -1875,6 +1883,73 @@ static const struct file_operations i915_dsc_bpc_fops = {
 	.write = i915_dsc_bpc_write
 };
 
+static int i915_dsc_output_format_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_crtc_state *crtc_state;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	crtc_state = to_intel_crtc_state(crtc->state);
+	seq_printf(m, "DSC_Output_Format: %s\n",
+		   intel_output_format_name(crtc_state->output_format));
+
+out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_output_format_write(struct file *file,
+					    const char __user *ubuf,
+					    size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	int dsc_output_format = 0;
+	int ret;
+
+	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_output_format);
+	if (ret < 0)
+		return ret;
+
+	intel_dp->force_dsc_output_format = dsc_output_format;
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_output_format_open(struct inode *inode,
+				       struct file *file)
+{
+	return single_open(file, i915_dsc_output_format_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_output_format_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_output_format_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_output_format_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1946,6 +2021,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_bpc", 0644, root,
 				    connector, &i915_dsc_bpc_fops);
+
+		debugfs_create_file("i915_dsc_output_format", 0644, root,
+				    connector, &i915_dsc_output_format_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9ccae7a46020..9f7951b49c42 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1743,6 +1743,7 @@ struct intel_dp {
 
 	/* Display stream compression testing */
 	bool force_dsc_en;
+	int force_dsc_output_format;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 95e9d0365e23..13bb4497b1fe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -76,6 +76,7 @@
 #include "intel_tc.h"
 #include "intel_vdsc.h"
 #include "intel_vrr.h"
+#include "intel_crtc_state_dump.h"
 
 /* DP DSC throughput values used for slice count calculations KPixels/s */
 #define DP_DSC_PEAK_PIXEL_RATE			2720000
@@ -810,6 +811,9 @@ intel_dp_output_format(struct intel_connector *connector,
 {
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 
+	if (intel_dp->force_dsc_output_format)
+		return intel_dp->force_dsc_output_format;
+
 	if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
 		return INTEL_OUTPUT_FORMAT_RGB;
 
-- 
2.25.1

[Intel-gfx] [PATCH 7/7] drm/i915/dsc: Add debugfs entry to validate DSC output formats

[Suraj Kandpal]

From: Swati Sharma <swati2.sharma@intel.com>

DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show
to depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444).
Also, new debugfs entry is created to enforce output format. This is
required because of our driver policy. For ex. if a mode is supported
in both RGB and YCbCr420 output formats by the sink, our policy is to
try RGB first and fall back to YCbCr420, if mode cannot be shown
using RGB. So, to test other output formats like YCbCr420 or YCbCr444,
we need a debugfs entry (force_dsc_output_format) to force this
output format.

v2: -Func name changed to intel_output_format_name() (Jani N)
    -Return forced o/p format from intel_dp_output_format() (Jani N)
v3: -output_format_str[] to remain static (Jani N)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 .../drm/i915/display/intel_crtc_state_dump.c  |  4 +-
 .../drm/i915/display/intel_crtc_state_dump.h  |  2 +
 .../drm/i915/display/intel_display_debugfs.c  | 78 +++++++++++++++++++
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  4 +
 5 files changed, 87 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 2422d6ef5777..45655efc9468 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -121,7 +121,7 @@ static const char * const output_format_str[] = {
 	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
 };
 
-static const char *output_formats(enum intel_output_format format)
+const char *intel_output_format_name(enum intel_output_format format)
 {
 	if (format >= ARRAY_SIZE(output_format_str))
 		return "invalid";
@@ -179,7 +179,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		    "active: %s, output_types: %s (0x%x), output format: %s\n",
 		    str_yes_no(pipe_config->hw.active),
 		    buf, pipe_config->output_types,
-		    output_formats(pipe_config->output_format));
+		    intel_output_format_name(pipe_config->output_format));
 
 	drm_dbg_kms(&i915->drm,
 		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
index 9399c35b7e5e..780f3f1190d7 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
@@ -8,9 +8,11 @@
 
 struct intel_crtc_state;
 struct intel_atomic_state;
+enum intel_output_format;
 
 void intel_crtc_state_dump(const struct intel_crtc_state *crtc_state,
 			   struct intel_atomic_state *state,
 			   const char *context);
+const char *intel_output_format_name(enum intel_output_format format);
 
 #endif /* __INTEL_CRTC_STATE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 49a7c00c0664..7ebac255865f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -12,6 +12,7 @@
 #include "i915_irq.h"
 #include "i915_reg.h"
 #include "intel_de.h"
+#include "intel_crtc_state_dump.h"
 #include "intel_display_debugfs.h"
 #include "intel_display_power.h"
 #include "intel_display_power_well.h"
@@ -1750,6 +1751,13 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 			   str_yes_no(crtc_state->dsc.compression_enable));
 		seq_printf(m, "DSC_Sink_Support: %s\n",
 			   str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)));
+		seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n",
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_RGB)),
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_YCbCr420_Native)),
+			   str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
+								      DP_DSC_YCbCr444)));
 		seq_printf(m, "Force_DSC_Enable: %s\n",
 			   str_yes_no(intel_dp->force_dsc_en));
 		if (!intel_dp_is_edp(intel_dp))
@@ -1875,6 +1883,73 @@ static const struct file_operations i915_dsc_bpc_fops = {
 	.write = i915_dsc_bpc_write
 };
 
+static int i915_dsc_output_format_show(struct seq_file *m, void *data)
+{
+	struct drm_connector *connector = m->private;
+	struct drm_device *dev = connector->dev;
+	struct drm_crtc *crtc;
+	struct intel_crtc_state *crtc_state;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	int ret;
+
+	if (!encoder)
+		return -ENODEV;
+
+	ret = drm_modeset_lock_single_interruptible(&dev->mode_config.connection_mutex);
+	if (ret)
+		return ret;
+
+	crtc = connector->state->crtc;
+	if (connector->status != connector_status_connected || !crtc) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	crtc_state = to_intel_crtc_state(crtc->state);
+	seq_printf(m, "DSC_Output_Format: %s\n",
+		   intel_output_format_name(crtc_state->output_format));
+
+out:	drm_modeset_unlock(&dev->mode_config.connection_mutex);
+
+	return ret;
+}
+
+static ssize_t i915_dsc_output_format_write(struct file *file,
+					    const char __user *ubuf,
+					    size_t len, loff_t *offp)
+{
+	struct drm_connector *connector =
+		((struct seq_file *)file->private_data)->private;
+	struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	int dsc_output_format = 0;
+	int ret;
+
+	ret = kstrtoint_from_user(ubuf, len, 0, &dsc_output_format);
+	if (ret < 0)
+		return ret;
+
+	intel_dp->force_dsc_output_format = dsc_output_format;
+	*offp += len;
+
+	return len;
+}
+
+static int i915_dsc_output_format_open(struct inode *inode,
+				       struct file *file)
+{
+	return single_open(file, i915_dsc_output_format_show, inode->i_private);
+}
+
+static const struct file_operations i915_dsc_output_format_fops = {
+	.owner = THIS_MODULE,
+	.open = i915_dsc_output_format_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = i915_dsc_output_format_write
+};
+
 /*
  * Returns the Current CRTC's bpc.
  * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/i915_current_bpc
@@ -1946,6 +2021,9 @@ void intel_connector_debugfs_add(struct intel_connector *intel_connector)
 
 		debugfs_create_file("i915_dsc_bpc", 0644, root,
 				    connector, &i915_dsc_bpc_fops);
+
+		debugfs_create_file("i915_dsc_output_format", 0644, root,
+				    connector, &i915_dsc_output_format_fops);
 	}
 
 	if (connector->connector_type == DRM_MODE_CONNECTOR_DSI ||
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9ccae7a46020..9f7951b49c42 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1743,6 +1743,7 @@ struct intel_dp {
 
 	/* Display stream compression testing */
 	bool force_dsc_en;
+	int force_dsc_output_format;
 	int force_dsc_bpc;
 
 	bool hobl_failed;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 95e9d0365e23..13bb4497b1fe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -76,6 +76,7 @@
 #include "intel_tc.h"
 #include "intel_vdsc.h"
 #include "intel_vrr.h"
+#include "intel_crtc_state_dump.h"
 
 /* DP DSC throughput values used for slice count calculations KPixels/s */
 #define DP_DSC_PEAK_PIXEL_RATE			2720000
@@ -810,6 +811,9 @@ intel_dp_output_format(struct intel_connector *connector,
 {
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 
+	if (intel_dp->force_dsc_output_format)
+		return intel_dp->force_dsc_output_format;
+
 	if (!connector->base.ycbcr_420_allowed || !ycbcr_420_output)
 		return INTEL_OUTPUT_FORMAT_RGB;
 
-- 
2.25.1

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable YCbCr420 format for VDSC

[Patchwork]

== Series Details ==

Series: Enable YCbCr420 format for VDSC
URL   : https://patchwork.freedesktop.org/series/114246/
State : warning

== Summary ==

Error: dim checkpatch failed
50d82404259d drm/dp_helper: Add helper to check DSC support with given o/p format
8a054916220a drm/i915/dp: Check if DSC supports the given output_format
cc078397ede3 drm/i915: Adding the new registers for DSC
010a8a43fda3 drm/i915: Enable YCbCr420 for VDSC
-:199: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_row' - possible side-effects?
#199: FILE: drivers/gpu/drm/i915/display/intel_qp_tables.c:447:
+#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420)  do { \
+	if (bpc == (_bpc)) {	\
+		if (_is_420)	\
+			return rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
+		else	\
+			return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+	}	\
 } while (0)

-:199: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_col' - possible side-effects?
#199: FILE: drivers/gpu/drm/i915/display/intel_qp_tables.c:447:
+#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420)  do { \
+	if (bpc == (_bpc)) {	\
+		if (_is_420)	\
+			return rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
+		else	\
+			return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+	}	\
 } while (0)

total: 0 errors, 0 warnings, 2 checks, 228 lines checked
ae5e251167ba drm/i915/display: Fill in native_420 field
c2dc1975afc9 drm/i915/vdsc: Check slice design requirement
727724e06154 drm/i915/dsc: Add debugfs entry to validate DSC output formats

[Intel-gfx] ✗ Fi.CI.BAT: failure for Enable YCbCr420 format for VDSC

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 10553 bytes --]

== Series Details ==

Series: Enable YCbCr420 format for VDSC
URL   : https://patchwork.freedesktop.org/series/114246/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12768 -> Patchwork_114246v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_114246v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_114246v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/index.html

Participating hosts (38 -> 38)
------------------------------

  Additional (1): bat-atsm-1 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_114246v1:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@memory_region:
    - fi-kbl-soraka:      [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/fi-kbl-soraka/igt@i915_selftest@live@memory_region.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/fi-kbl-soraka/igt@i915_selftest@live@memory_region.html

  
Known issues
------------

  Here are the changes found in Patchwork_114246v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@eof:
    - bat-atsm-1:         NOTRUN -> [SKIP][3] ([i915#2582]) +4 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@fbdev@eof.html

  * igt@gem_lmem_swapping@basic:
    - fi-apl-guc:         NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/fi-apl-guc/igt@gem_lmem_swapping@basic.html

  * igt@gem_mmap@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@gem_mmap@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][7] ([i915#4079]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-atsm-1:         NOTRUN -> [SKIP][8] ([i915#6621])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-kbl-soraka:      [PASS][9] -> [DMESG-FAIL][10] ([i915#5334] / [i915#7872])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@slpc:
    - bat-rpls-2:         NOTRUN -> [DMESG-FAIL][11] ([i915#6997])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-rpls-2/igt@i915_selftest@live@slpc.html
    - bat-rpls-1:         [PASS][12] -> [DMESG-FAIL][13] ([i915#6367] / [i915#7996])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-rpls-1/igt@i915_selftest@live@slpc.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-rpls-1/igt@i915_selftest@live@slpc.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-atsm-1:         NOTRUN -> [SKIP][14] ([i915#6645])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@size-max:
    - bat-atsm-1:         NOTRUN -> [SKIP][15] ([i915#6077]) +36 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@kms_addfb_basic@size-max.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - bat-rpls-2:         NOTRUN -> [SKIP][16] ([i915#7828])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-rpls-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
    - fi-apl-guc:         NOTRUN -> [SKIP][17] ([fdo#109271])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/fi-apl-guc/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor:
    - bat-atsm-1:         NOTRUN -> [SKIP][18] ([i915#6078]) +14 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@kms_cursor_legacy@basic-flip-after-cursor.html

  * igt@kms_flip@basic-plain-flip:
    - bat-atsm-1:         NOTRUN -> [SKIP][19] ([i915#6166]) +3 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@kms_flip@basic-plain-flip.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-atsm-1:         NOTRUN -> [SKIP][20] ([i915#6093]) +3 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_pipe_crc_basic@hang-read-crc:
    - bat-atsm-1:         NOTRUN -> [SKIP][21] ([i915#1836]) +6 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@kms_pipe_crc_basic@hang-read-crc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - bat-rpls-2:         NOTRUN -> [SKIP][22] ([i915#1845])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@kms_prop_blob@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][23] ([i915#7357])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@kms_prop_blob@basic.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-atsm-1:         NOTRUN -> [SKIP][24] ([i915#1072]) +3 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-atsm-1:         NOTRUN -> [SKIP][25] ([i915#6094])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-atsm-1:         NOTRUN -> [SKIP][26] ([fdo#109295] / [i915#6078])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-atsm-1:         NOTRUN -> [SKIP][27] ([fdo#109295] / [i915#4077]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-write:
    - bat-atsm-1:         NOTRUN -> [SKIP][28] ([fdo#109295]) +3 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-atsm-1/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-apl-guc:         [ABORT][29] -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_selftest@live@reset:
    - bat-rpls-2:         [ABORT][31] ([i915#4983]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12768/bat-rpls-2/igt@i915_selftest@live@reset.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/bat-rpls-2/igt@i915_selftest@live@reset.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6077]: https://gitlab.freedesktop.org/drm/intel/issues/6077
  [i915#6078]: https://gitlab.freedesktop.org/drm/intel/issues/6078
  [i915#6093]: https://gitlab.freedesktop.org/drm/intel/issues/6093
  [i915#6094]: https://gitlab.freedesktop.org/drm/intel/issues/6094
  [i915#6166]: https://gitlab.freedesktop.org/drm/intel/issues/6166
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7357]: https://gitlab.freedesktop.org/drm/intel/issues/7357
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
  [i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996


Build changes
-------------

  * Linux: CI_DRM_12768 -> Patchwork_114246v1

  CI-20190529: 20190529
  CI_DRM_12768: d9a0aa492e367314a1681974bf178363a4b5587a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7168: 165df656261863684067cd53f95c3a301e67fa24 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_114246v1: d9a0aa492e367314a1681974bf178363a4b5587a @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

4243f1fac967 drm/i915/dsc: Add debugfs entry to validate DSC output formats
16c55cffb9df drm/i915/vdsc: Check slice design requirement
3a7b62cf837a drm/i915/display: Fill in native_420 field
dbd4161d46d0 drm/i915: Enable YCbCr420 for VDSC
56ad6b5f097c drm/i915: Adding the new registers for DSC
e16280f40fcb drm/i915/dp: Check if DSC supports the given output_format
9bed9f8c58ec drm/dp_helper: Add helper to check DSC support with given o/p format

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v1/index.html

[-- Attachment #2: Type: text/html, Size: 12214 bytes --]

[PATCH v2 5/7] drm/i915/display: Fill in native_420 field

[Suraj Kandpal]

Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.

---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vds_cfg when native_420 is true

---v3
-adding display version check to solve igt issue

--v7
-remove is_pipe_dsc check as its always true for D14 [Jani]

--v10
-keep sink capability check [Jani]
-move from !(x == y  || w == z) to x !=y && w != z [Jani]

--v11
-avoid native_420 computation if not gen14 [Uma]

--v12
-fix state mismatch issue of compressed_bpp

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c    |  2 -
 drivers/gpu/drm/i915/display/intel_dp.c   | 16 +++-
 drivers/gpu/drm/i915/display/intel_vdsc.c | 98 ++++++++++++++++++++---
 3 files changed, 100 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index b5316715bb3b..fb7efab8e9e6 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1539,8 +1539,6 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 	if (crtc_state->dsc.slice_count > 1)
 		crtc_state->dsc.dsc_split = true;
 
-	vdsc_cfg->convert_rgb = true;
-
 	/* FIXME: initialize from VBT */
 	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2649e8b8ef57..86b9348b74bb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1467,9 +1467,10 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 	vdsc_cfg->dsc_version_minor =
 		min(intel_dp_source_dsc_version_minor(intel_dp),
 		    intel_dp_sink_dsc_version_minor(intel_dp));
-
-	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
-		DP_DSC_RGB;
+	if (vdsc_cfg->convert_rgb)
+		vdsc_cfg->convert_rgb =
+			intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
+			DP_DSC_RGB;
 
 	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
 	if (!line_buf_depth) {
@@ -1587,6 +1588,15 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 							    pipe_config->bigjoiner_pipes,
 							    pipe_bpp,
 							    timeslots);
+			/*
+			 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
+			 * supported PPS value can be 63.9375 and with the further
+			 * mention that bpp should be programmed double the target bpp
+			 * restricting our target bpp to be 31.9375 at max
+			 */
+			if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+				dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4);
+
 			if (!dsc_max_output_bpp) {
 				drm_dbg_kms(&dev_priv->drm,
 					    "Compressed BPP not supported\n");
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ed16f63d6355..44243fc81b46 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -460,14 +460,50 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 					     pipe_config->dsc.slice_count);
-
-	/* Gen 11 does not support YCbCr */
+	/*
+	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
+	 * else 1
+	 */
+	vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
+				pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444;
+
+	if (DISPLAY_VER(dev_priv) >= 14 &&
+	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		vdsc_cfg->native_420 = true;
+	/* We do not support YcBCr422 as of now */
+	vdsc_cfg->native_422 = false;
 	vdsc_cfg->simple_422 = false;
 	/* Gen 11 does not support VBR */
 	vdsc_cfg->vbr_enable = false;
 
 	/* Gen 11 only supports integral values of bpp */
 	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+
+	/*
+	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set:
+	 * -We need to double the current bpp.
+	 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
+	 * height < 8.
+	 * -second_line_offset_adj is 512 as shown by emperical values to yeild best chroma
+	 * preservation in second line.
+	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
+	 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
+	 * fractional bits.
+	 */
+	if (vdsc_cfg->native_420) {
+		vdsc_cfg->bits_per_pixel <<= 1;
+
+		if (vdsc_cfg->slice_height >= 8)
+			vdsc_cfg->second_line_bpg_offset = 12;
+		else
+			vdsc_cfg->second_line_bpg_offset =
+				2 * (vdsc_cfg->slice_height - 1);
+
+		vdsc_cfg->second_line_offset_adj = 512;
+		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
+							vdsc_cfg->slice_height - 1);
+	}
+
 	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 
 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
@@ -594,8 +630,13 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_VER_MIN_SHIFT |
 		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
 		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
-	if (vdsc_cfg->dsc_version_minor == 2)
+	if (vdsc_cfg->dsc_version_minor == 2) {
 		pps_val |= DSC_ALT_ICH_SEL;
+		if (vdsc_cfg->native_420)
+			pps_val |= DSC_NATIVE_420_ENABLE;
+		if (vdsc_cfg->native_422)
+			pps_val |= DSC_NATIVE_422_ENABLE;
+	}
 	if (vdsc_cfg->block_pred_enable)
 		pps_val |= DSC_BLOCK_PREDICTION;
 	if (vdsc_cfg->convert_rgb)
@@ -906,6 +947,33 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 				       pps_val);
 	}
 
+	if (DISPLAY_VER(dev_priv) >= 14) {
+		/* Populate PICTURE_PARAMETER_SET_17 registers */
+		pps_val = 0;
+		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
+		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
+		intel_de_write(dev_priv,
+			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
+			       pps_val);
+		if (crtc_state->dsc.dsc_split)
+			intel_de_write(dev_priv,
+				       MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
+				       pps_val);
+
+		/* Populate PICTURE_PARAMETER_SET_18 registers */
+		pps_val = 0;
+		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
+			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
+		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
+		intel_de_write(dev_priv,
+			       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
+			       pps_val);
+		if (crtc_state->dsc.dsc_split)
+			intel_de_write(dev_priv,
+				       MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
+				       pps_val);
+	}
+
 	/* Populate the RC_BUF_THRESH registers */
 	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
@@ -1180,7 +1248,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	enum intel_display_power_domain power_domain;
 	intel_wakeref_t wakeref;
-	u32 dss_ctl1, dss_ctl2, val;
+	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0;
 
 	if (!intel_dsc_source_support(crtc_state))
 		return;
@@ -1203,13 +1271,21 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 
 	/* FIXME: add more state readout as needed */
 
-	/* PPS1 */
-	if (!is_pipe_dsc(crtc, cpu_transcoder))
-		val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
-	else
-		val = intel_de_read(dev_priv,
-				    ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
-	vdsc_cfg->bits_per_pixel = val;
+	/* PPS0 & PPS1 */
+	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+		pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
+	} else {
+		pps0 = intel_de_read(dev_priv,
+				     ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
+		pps1 = intel_de_read(dev_priv,
+				     ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
+	}
+
+	vdsc_cfg->bits_per_pixel = pps1;
+
+	if (pps0 & DSC_NATIVE_420_ENABLE)
+		vdsc_cfg->bits_per_pixel >>= 1;
+
 	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
 out:
 	intel_display_power_put(dev_priv, power_domain, wakeref);
-- 
2.25.1

[Intel-gfx] [PATCH v2 5/7] drm/i915/display: Fill in native_420 field

[Suraj Kandpal]

Now that we have laid the groundwork for YUV420 Enablement
we fill up native_420 field in vdsc_cfg and add appropriate
checks wherever required.

---v2
-adding native_422 field as 0 [Vandita]
-filling in second_line_bpg_offset, second_line_offset_adj
and nsl_bpg_offset in vds_cfg when native_420 is true

---v3
-adding display version check to solve igt issue

--v7
-remove is_pipe_dsc check as its always true for D14 [Jani]

--v10
-keep sink capability check [Jani]
-move from !(x == y  || w == z) to x !=y && w != z [Jani]

--v11
-avoid native_420 computation if not gen14 [Uma]

--v12
-fix state mismatch issue of compressed_bpp

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c    |  2 -
 drivers/gpu/drm/i915/display/intel_dp.c   | 16 +++-
 drivers/gpu/drm/i915/display/intel_vdsc.c | 98 ++++++++++++++++++++---
 3 files changed, 100 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index b5316715bb3b..fb7efab8e9e6 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1539,8 +1539,6 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
 	if (crtc_state->dsc.slice_count > 1)
 		crtc_state->dsc.dsc_split = true;
 
-	vdsc_cfg->convert_rgb = true;
-
 	/* FIXME: initialize from VBT */
 	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2649e8b8ef57..86b9348b74bb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1467,9 +1467,10 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 	vdsc_cfg->dsc_version_minor =
 		min(intel_dp_source_dsc_version_minor(intel_dp),
 		    intel_dp_sink_dsc_version_minor(intel_dp));
-
-	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
-		DP_DSC_RGB;
+	if (vdsc_cfg->convert_rgb)
+		vdsc_cfg->convert_rgb =
+			intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
+			DP_DSC_RGB;
 
 	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
 	if (!line_buf_depth) {
@@ -1587,6 +1588,15 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 							    pipe_config->bigjoiner_pipes,
 							    pipe_bpp,
 							    timeslots);
+			/*
+			 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
+			 * supported PPS value can be 63.9375 and with the further
+			 * mention that bpp should be programmed double the target bpp
+			 * restricting our target bpp to be 31.9375 at max
+			 */
+			if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+				dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4);
+
 			if (!dsc_max_output_bpp) {
 				drm_dbg_kms(&dev_priv->drm,
 					    "Compressed BPP not supported\n");
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ed16f63d6355..44243fc81b46 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -460,14 +460,50 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
 	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 					     pipe_config->dsc.slice_count);
-
-	/* Gen 11 does not support YCbCr */
+	/*
+	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
+	 * else 1
+	 */
+	vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
+				pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444;
+
+	if (DISPLAY_VER(dev_priv) >= 14 &&
+	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		vdsc_cfg->native_420 = true;
+	/* We do not support YcBCr422 as of now */
+	vdsc_cfg->native_422 = false;
 	vdsc_cfg->simple_422 = false;
 	/* Gen 11 does not support VBR */
 	vdsc_cfg->vbr_enable = false;
 
 	/* Gen 11 only supports integral values of bpp */
 	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
+
+	/*
+	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set:
+	 * -We need to double the current bpp.
+	 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
+	 * height < 8.
+	 * -second_line_offset_adj is 512 as shown by emperical values to yeild best chroma
+	 * preservation in second line.
+	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
+	 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
+	 * fractional bits.
+	 */
+	if (vdsc_cfg->native_420) {
+		vdsc_cfg->bits_per_pixel <<= 1;
+
+		if (vdsc_cfg->slice_height >= 8)
+			vdsc_cfg->second_line_bpg_offset = 12;
+		else
+			vdsc_cfg->second_line_bpg_offset =
+				2 * (vdsc_cfg->slice_height - 1);
+
+		vdsc_cfg->second_line_offset_adj = 512;
+		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
+							vdsc_cfg->slice_height - 1);
+	}
+
 	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
 
 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
@@ -594,8 +630,13 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_VER_MIN_SHIFT |
 		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
 		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
-	if (vdsc_cfg->dsc_version_minor == 2)
+	if (vdsc_cfg->dsc_version_minor == 2) {
 		pps_val |= DSC_ALT_ICH_SEL;
+		if (vdsc_cfg->native_420)
+			pps_val |= DSC_NATIVE_420_ENABLE;
+		if (vdsc_cfg->native_422)
+			pps_val |= DSC_NATIVE_422_ENABLE;
+	}
 	if (vdsc_cfg->block_pred_enable)
 		pps_val |= DSC_BLOCK_PREDICTION;
 	if (vdsc_cfg->convert_rgb)
@@ -906,6 +947,33 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 				       pps_val);
 	}
 
+	if (DISPLAY_VER(dev_priv) >= 14) {
+		/* Populate PICTURE_PARAMETER_SET_17 registers */
+		pps_val = 0;
+		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
+		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
+		intel_de_write(dev_priv,
+			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
+			       pps_val);
+		if (crtc_state->dsc.dsc_split)
+			intel_de_write(dev_priv,
+				       MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
+				       pps_val);
+
+		/* Populate PICTURE_PARAMETER_SET_18 registers */
+		pps_val = 0;
+		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
+			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
+		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
+		intel_de_write(dev_priv,
+			       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
+			       pps_val);
+		if (crtc_state->dsc.dsc_split)
+			intel_de_write(dev_priv,
+				       MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
+				       pps_val);
+	}
+
 	/* Populate the RC_BUF_THRESH registers */
 	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
 	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
@@ -1180,7 +1248,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	enum intel_display_power_domain power_domain;
 	intel_wakeref_t wakeref;
-	u32 dss_ctl1, dss_ctl2, val;
+	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0;
 
 	if (!intel_dsc_source_support(crtc_state))
 		return;
@@ -1203,13 +1271,21 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 
 	/* FIXME: add more state readout as needed */
 
-	/* PPS1 */
-	if (!is_pipe_dsc(crtc, cpu_transcoder))
-		val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
-	else
-		val = intel_de_read(dev_priv,
-				    ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
-	vdsc_cfg->bits_per_pixel = val;
+	/* PPS0 & PPS1 */
+	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
+		pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
+	} else {
+		pps0 = intel_de_read(dev_priv,
+				     ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
+		pps1 = intel_de_read(dev_priv,
+				     ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
+	}
+
+	vdsc_cfg->bits_per_pixel = pps1;
+
+	if (pps0 & DSC_NATIVE_420_ENABLE)
+		vdsc_cfg->bits_per_pixel >>= 1;
+
 	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
 out:
 	intel_display_power_put(dev_priv, power_domain, wakeref);
-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.BAT: success for Enable YCbCr420 format for VDSC (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1545 bytes --]

== Series Details ==

Series: Enable YCbCr420 format for VDSC (rev2)
URL   : https://patchwork.freedesktop.org/series/114246/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12805 -> Patchwork_114246v2
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/index.html

Participating hosts (3 -> 2)
------------------------------

  Missing    (1): fi-snb-2520m 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: CI_DRM_12805 -> Patchwork_114246v2

  CI-20190529: 20190529
  CI_DRM_12805: c1dbd5b5c8fdb5efd37a5a5234469b293c89a358 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7179: fcbbb6ab645cdbd7545c3f96d7b7df7674e620be @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_114246v2: c1dbd5b5c8fdb5efd37a5a5234469b293c89a358 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

854d3e83acbf drm/i915/dsc: Add debugfs entry to validate DSC output formats
75d7b64e8731 drm/i915/vdsc: Check slice design requirement
df0c32d69a62 drm/i915/display: Fill in native_420 field
95200017860b drm/i915: Enable YCbCr420 for VDSC
a5f19b5be267 drm/i915: Adding the new registers for DSC
81922029e90d drm/i915/dp: Check if DSC supports the given output_format
57d743e4928a drm/dp_helper: Add helper to check DSC support with given o/p format

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/index.html

[-- Attachment #2: Type: text/html, Size: 2155 bytes --]

[Intel-gfx] ✗ Fi.CI.IGT: failure for Enable YCbCr420 format for VDSC (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 15580 bytes --]

== Series Details ==

Series: Enable YCbCr420 format for VDSC (rev2)
URL   : https://patchwork.freedesktop.org/series/114246/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12805_full -> Patchwork_114246v2_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_114246v2_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_114246v2_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/index.html

Participating hosts (10 -> 9)
------------------------------

  Missing    (1): shard-tglu-10 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_114246v2_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_plane@pixel-format-source-clamping@pipe-a-planes:
    - shard-apl:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-apl6/igt@kms_plane@pixel-format-source-clamping@pipe-a-planes.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a1:
    - {shard-tglu}:       NOTRUN -> [DMESG-WARN][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-tglu-3/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html

  
Known issues
------------

  Here are the changes found in Patchwork_114246v2_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@file:
    - shard-snb:          NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-snb1/igt@gem_ctx_persistence@file.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][4] -> [FAIL][5] ([i915#2842])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12805/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][6] ([fdo#109271]) +7 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-apl1/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-glk:          NOTRUN -> [SKIP][7] ([fdo#109271]) +23 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-glk1/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-snb:          NOTRUN -> [SKIP][8] ([fdo#109271]) +322 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-snb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_setmode@basic@pipe-a-hdmi-a-1:
    - shard-snb:          NOTRUN -> [FAIL][9] ([i915#5465]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-snb1/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html

  * igt@perf_pmu@module-unload:
    - shard-apl:          [PASS][10] -> [DMESG-WARN][11] ([i915#1982])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12805/shard-apl3/igt@perf_pmu@module-unload.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-apl1/igt@perf_pmu@module-unload.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
    - {shard-rkl}:        [FAIL][12] ([i915#7742]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12805/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
    - shard-apl:          [ABORT][14] ([i915#180]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12805/shard-apl3/igt@gem_ctx_isolation@preservation-s3@vecs0.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-apl1/igt@gem_ctx_isolation@preservation-s3@vecs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
    - shard-glk:          [FAIL][16] ([i915#2842]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12805/shard-glk1/igt@gem_exec_fair@basic-none@rcs0.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-glk5/igt@gem_exec_fair@basic-none@rcs0.html

  * igt@i915_pm_dc@dc9-dpms:
    - {shard-tglu}:       [SKIP][18] ([i915#4281]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12805/shard-tglu-5/igt@i915_pm_dc@dc9-dpms.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-tglu-4/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rpm@modeset-lpsp-stress:
    - {shard-dg1}:        [SKIP][20] ([i915#1397]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12805/shard-dg1-17/igt@i915_pm_rpm@modeset-lpsp-stress.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-dg1-14/igt@i915_pm_rpm@modeset-lpsp-stress.html

  * igt@i915_suspend@fence-restore-untiled:
    - {shard-rkl}:        [FAIL][22] ([fdo#103375]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12805/shard-rkl-4/igt@i915_suspend@fence-restore-untiled.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-rkl-2/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-apl:          [FAIL][24] ([i915#2346]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12805/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
  [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
  [i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5431]: https://gitlab.freedesktop.org/drm/intel/issues/5431
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7330]: https://gitlab.freedesktop.org/drm/intel/issues/7330
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
  [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
  [i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
  [i915#8155]: https://gitlab.freedesktop.org/drm/intel/issues/8155
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228


Build changes
-------------

  * Linux: CI_DRM_12805 -> Patchwork_114246v2

  CI-20190529: 20190529
  CI_DRM_12805: c1dbd5b5c8fdb5efd37a5a5234469b293c89a358 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7179: fcbbb6ab645cdbd7545c3f96d7b7df7674e620be @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_114246v2: c1dbd5b5c8fdb5efd37a5a5234469b293c89a358 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114246v2/index.html

[-- Attachment #2: Type: text/html, Size: 9060 bytes --]

RE: [PATCH 1/7] drm/dp_helper: Add helper to check DSC support with given o/p format

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, February 22, 2023 11:02 AM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>
> Subject: [PATCH 1/7] drm/dp_helper: Add helper to check DSC support with given
> o/p format
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Add helper to check if the DP sink supports DSC with the given o/p format.
> 
> v2: Add documentation for the helper. (Uma Shankar)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  include/drm/display/drm_dp_helper.h | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/include/drm/display/drm_dp_helper.h
> b/include/drm/display/drm_dp_helper.h
> index ab55453f2d2c..41da8eb4801e 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -194,6 +194,19 @@ drm_dp_dsc_sink_max_slice_width(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>  		DP_DSC_SLICE_WIDTH_MULTIPLIER;
>  }
> 
> +/*

Use /** instead of /*

With that fixed, this is
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> + * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with
> +given output format
> + * @dsc_dpcd : DSC-capability DPCDs of the sink
> + * @output_format: output_format which is to be checked
> + *
> + * Returns true if the sink supports DSC with the given output_format, false
> otherwise.
> + */
> +static inline bool
> +drm_dp_dsc_sink_supports_format(const u8
> +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) {
> +	return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT]
> &
> +output_format; }
> +
>  /* Forward Error Correction Support on DP 1.4 */  static inline bool
> drm_dp_sink_supports_fec(const u8 fec_capable)
> --
> 2.25.1

Re: [Intel-gfx] [PATCH 1/7] drm/dp_helper: Add helper to check DSC support with given o/p format

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, February 22, 2023 11:02 AM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>
> Subject: [PATCH 1/7] drm/dp_helper: Add helper to check DSC support with given
> o/p format
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Add helper to check if the DP sink supports DSC with the given o/p format.
> 
> v2: Add documentation for the helper. (Uma Shankar)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  include/drm/display/drm_dp_helper.h | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/include/drm/display/drm_dp_helper.h
> b/include/drm/display/drm_dp_helper.h
> index ab55453f2d2c..41da8eb4801e 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -194,6 +194,19 @@ drm_dp_dsc_sink_max_slice_width(const u8
> dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
>  		DP_DSC_SLICE_WIDTH_MULTIPLIER;
>  }
> 
> +/*

Use /** instead of /*

With that fixed, this is
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> + * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with
> +given output format
> + * @dsc_dpcd : DSC-capability DPCDs of the sink
> + * @output_format: output_format which is to be checked
> + *
> + * Returns true if the sink supports DSC with the given output_format, false
> otherwise.
> + */
> +static inline bool
> +drm_dp_dsc_sink_supports_format(const u8
> +dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) {
> +	return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT]
> &
> +output_format; }
> +
>  /* Forward Error Correction Support on DP 1.4 */  static inline bool
> drm_dp_sink_supports_fec(const u8 fec_capable)
> --
> 2.25.1

RE: [PATCH 2/7] drm/i915/dp: Check if DSC supports the given output_format

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, February 22, 2023 11:02 AM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>
> Subject: [PATCH 2/7] drm/i915/dp: Check if DSC supports the given output_format
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Go with DSC only if the given output_format is supported.
> 
> v2: Use drm helper to get DSC format support for sink.
> 
> v3: remove drm_dp_dsc_compute_bpp.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index fe98c7dec193..f2fb3ec2dd99 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1491,6 +1491,31 @@ static int intel_dp_dsc_compute_params(struct
> intel_encoder *encoder,
>  	return drm_dsc_compute_rc_parameters(vdsc_cfg);
>  }
> 
> +static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
> +					 enum intel_output_format output_format)
> {
> +	u8 sink_dsc_format;
> +
> +	switch (output_format) {
> +	case INTEL_OUTPUT_FORMAT_RGB:
> +		sink_dsc_format = DP_DSC_RGB;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_YCBCR444:
> +		sink_dsc_format = DP_DSC_YCbCr444;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_YCBCR420:
> +		if (min(intel_dp_source_dsc_version_minor(intel_dp),
> +			intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
> +			return false;
> +		sink_dsc_format = DP_DSC_YCbCr420_Native;
> +		break;
> +	default:
> +		return false;
> +	}
> +
> +	return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> +sink_dsc_format); }
> +
>  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  				struct intel_crtc_state *pipe_config,
>  				struct drm_connector_state *conn_state, @@ -
> 1511,6 +1536,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>  		return -EINVAL;
> 
> +	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> +		return -EINVAL;
> +
>  	if (compute_pipe_bpp)
>  		pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state-
> >max_requested_bpc);
>  	else
> --
> 2.25.1

Re: [Intel-gfx] [PATCH 2/7] drm/i915/dp: Check if DSC supports the given output_format

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, February 22, 2023 11:02 AM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>
> Subject: [PATCH 2/7] drm/i915/dp: Check if DSC supports the given output_format
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Go with DSC only if the given output_format is supported.
> 
> v2: Use drm helper to get DSC format support for sink.
> 
> v3: remove drm_dp_dsc_compute_bpp.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index fe98c7dec193..f2fb3ec2dd99 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1491,6 +1491,31 @@ static int intel_dp_dsc_compute_params(struct
> intel_encoder *encoder,
>  	return drm_dsc_compute_rc_parameters(vdsc_cfg);
>  }
> 
> +static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp,
> +					 enum intel_output_format output_format)
> {
> +	u8 sink_dsc_format;
> +
> +	switch (output_format) {
> +	case INTEL_OUTPUT_FORMAT_RGB:
> +		sink_dsc_format = DP_DSC_RGB;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_YCBCR444:
> +		sink_dsc_format = DP_DSC_YCbCr444;
> +		break;
> +	case INTEL_OUTPUT_FORMAT_YCBCR420:
> +		if (min(intel_dp_source_dsc_version_minor(intel_dp),
> +			intel_dp_sink_dsc_version_minor(intel_dp)) < 2)
> +			return false;
> +		sink_dsc_format = DP_DSC_YCbCr420_Native;
> +		break;
> +	default:
> +		return false;
> +	}
> +
> +	return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd,
> +sink_dsc_format); }
> +
>  int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  				struct intel_crtc_state *pipe_config,
>  				struct drm_connector_state *conn_state, @@ -
> 1511,6 +1536,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
>  	if (!intel_dp_supports_dsc(intel_dp, pipe_config))
>  		return -EINVAL;
> 
> +	if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format))
> +		return -EINVAL;
> +
>  	if (compute_pipe_bpp)
>  		pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state-
> >max_requested_bpc);
>  	else
> --
> 2.25.1

RE: [PATCH 3/7] drm/i915: Adding the new registers for DSC

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, February 22, 2023 11:02 AM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>; Kulkarni,
> Vandita <vandita.kulkarni@intel.com>
> Subject: [PATCH 3/7] drm/i915: Adding the new registers for DSC

Nit: drm/i915/dsc would be better.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Adding new DSC register which are introducted MTL onwards
> 
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 596efc940ee7..9e25e21d37e4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7715,6 +7715,8 @@ enum skl_power_gate {
>  #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) -
> PIPE_B, \
> 
> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> 
> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> +#define  DSC_NATIVE_422_ENABLE		BIT(23)
> +#define  DSC_NATIVE_420_ENABLE		BIT(22)
>  #define  DSC_ALT_ICH_SEL		(1 << 20)
>  #define  DSC_VBR_ENABLE			(1 << 19)
>  #define  DSC_422_ENABLE			(1 << 18)
> @@ -7959,6 +7961,32 @@ enum skl_power_gate {
>  #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
>  #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size)
> << 0)
> 
> +/* MTL Display Stream Compression registers */
> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB	0x782B4
> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB	0x783B4
> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC	0x784B4
> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC	0x785B4
> +#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe)
> 	_MMIO_PIPE((pipe) - PIPE_B, \
> +
> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
> +
> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
> +#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)
> 	_MMIO_PIPE((pipe) - PIPE_B, \
> +
> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
> +
> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
> +#define DSC_SL_BPG_OFFSET(offset)		((offset) << 27)
> +
> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB	0x782B8
> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB	0x783B8
> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC	0x784B8
> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC	0x785B8
> +#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe)
> 	_MMIO_PIPE((pipe) - PIPE_B, \
> +
> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
> +
> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
> +#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)
> 	_MMIO_PIPE((pipe) - PIPE_B, \
> +
> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
> +
> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
> +#define DSC_NSL_BPG_OFFSET(offset)		((offset) << 16)
> +#define DSC_SL_OFFSET_ADJ(offset)		((offset) << 0)
> +
>  /* Icelake Rate Control Buffer Threshold Registers */
>  #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
>  #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
> --
> 2.25.1

Re: [Intel-gfx] [PATCH 3/7] drm/i915: Adding the new registers for DSC

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, February 22, 2023 11:02 AM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>; Kulkarni,
> Vandita <vandita.kulkarni@intel.com>
> Subject: [PATCH 3/7] drm/i915: Adding the new registers for DSC

Nit: drm/i915/dsc would be better.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Adding new DSC register which are introducted MTL onwards
> 
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 596efc940ee7..9e25e21d37e4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7715,6 +7715,8 @@ enum skl_power_gate {
>  #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) -
> PIPE_B, \
> 
> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> 
> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> +#define  DSC_NATIVE_422_ENABLE		BIT(23)
> +#define  DSC_NATIVE_420_ENABLE		BIT(22)
>  #define  DSC_ALT_ICH_SEL		(1 << 20)
>  #define  DSC_VBR_ENABLE			(1 << 19)
>  #define  DSC_422_ENABLE			(1 << 18)
> @@ -7959,6 +7961,32 @@ enum skl_power_gate {
>  #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
>  #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size)
> << 0)
> 
> +/* MTL Display Stream Compression registers */
> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB	0x782B4
> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB	0x783B4
> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC	0x784B4
> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC	0x785B4
> +#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe)
> 	_MMIO_PIPE((pipe) - PIPE_B, \
> +
> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
> +
> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
> +#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)
> 	_MMIO_PIPE((pipe) - PIPE_B, \
> +
> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
> +
> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
> +#define DSC_SL_BPG_OFFSET(offset)		((offset) << 27)
> +
> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB	0x782B8
> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB	0x783B8
> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC	0x784B8
> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC	0x785B8
> +#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe)
> 	_MMIO_PIPE((pipe) - PIPE_B, \
> +
> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
> +
> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
> +#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)
> 	_MMIO_PIPE((pipe) - PIPE_B, \
> +
> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
> +
> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
> +#define DSC_NSL_BPG_OFFSET(offset)		((offset) << 16)
> +#define DSC_SL_OFFSET_ADJ(offset)		((offset) << 0)
> +
>  /* Icelake Rate Control Buffer Threshold Registers */
>  #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
>  #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
> --
> 2.25.1

RE: [PATCH 4/7] drm/i915: Enable YCbCr420 for VDSC

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, February 22, 2023 11:02 AM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>; Kulkarni,
> Vandita <vandita.kulkarni@intel.com>
> Subject: [PATCH 4/7] drm/i915: Enable YCbCr420 for VDSC

drm/i915/dsc is better

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Implementation of VDSC for YCbCr420.
> Add QP tables for 8,10,12 BPC from rc_tables.h in intel_qp_tables.c (Derived from C-
> Model, which is given along with DSC1.2a Spec from Vesa)
> intel_lookup_range_min/max_qp functons need to take into account the output
> format. Based on that appropriate qp table need to be chosen.
> Other rc_parameters need to be set where currently values for 444 format is
> hardcoded in calculate_rc_parameters( ).
> vdsc_cfg struct needs to be filled with output format information, where these are
> hardcoded for 444 format.
> Bspec: 49259
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
>  .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
>  drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
>  3 files changed, 180 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c
> b/drivers/gpu/drm/i915/display/intel_qp_tables.c
> index 6f8e4ec5c0fb..6e86c0971d24 100644
> --- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
> +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
> @@ -17,6 +17,15 @@
>  /* from BPP 6 to 36 in steps of 0.5 */
>  #define RC_RANGE_QP444_12BPC_MAX_NUM_BPP	61
> 
> +/* from BPP 6 to 24 in steps of 0.5 */
> +#define RC_RANGE_QP420_8BPC_MAX_NUM_BPP		17
> +
> +/* from BPP 6 to 30 in steps of 0.5 */
> +#define RC_RANGE_QP420_10BPC_MAX_NUM_BPP	23
> +
> +/* from BPP 6 to 36 in steps of 0.5 */
> +#define RC_RANGE_QP420_12BPC_MAX_NUM_BPP	29
> +
>  /*
>   * These qp tables are as per the C model
>   * and it has the rows pointing to bpps which increment @@ -283,26 +292,182 @@
> static const u8
> rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC
>  	  11, 11, 10, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4 }  };
> 
> -#define PARAM_TABLE(_minmax, _bpc, _row, _col)  do { \
> -	if (bpc == (_bpc)) \
> -		return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
> +static const u8
> rc_range_minqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MA
> X_NUM_BPP] = {
> +	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 },
> +	{ 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
> +	{ 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
> +	{ 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
> +	{ 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 0 },
> +	{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1 },
> +	{ 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 1, 1 },
> +	{ 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 2, 2, 1 },
> +	{ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 3, 3, 2, 1 },
> +	{ 9, 8, 8, 7, 7, 7, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 2 },
> +	{ 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3 } };
> +
> +static const u8
> rc_range_maxqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MA
> X_NUM_BPP] = {
> +	{ 4, 4, 3, 3, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 4, 4, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
> +	{ 5, 5, 5, 5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
> +	{ 6, 6, 6, 6, 6, 5, 4, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0 },
> +	{ 7, 7, 7, 7, 7, 5, 4, 3, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
> +	{ 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 2, 2, 2, 1, 1, 0 },
> +	{ 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1 },
> +	{ 8, 8, 8, 8, 8, 7, 6, 5, 4, 4, 4, 3, 3, 2, 2, 2, 1 },
> +	{ 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
> +	{ 10, 10, 9, 9, 9, 8, 7, 6, 5, 5, 5, 4, 4, 3, 3, 2, 2 },
> +	{ 10, 10, 10, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 2, 2 },
> +	{ 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2 },
> +	{ 11, 11, 11, 10, 9, 9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3, 2 },
> +	{ 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4, 4, 4, 3 },
> +	{ 14, 13, 13, 12, 11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4 } };
> +
> +static const u8
> rc_range_minqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_
> MAX_NUM_BPP] = {
> +	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0 },
> +	{ 7, 7, 7, 7, 7, 6, 5, 5, 5, 5, 5, 4, 3, 3, 2, 2, 1, 1, 1, 1, 1, 0, 0 },
> +	{ 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 2, 2, 1, 1, 1, 0 },
> +	{ 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 4, 4, 4, 3, 2, 2, 2, 1, 1, 1, 0 },
> +	{ 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 2, 1, 1 },
> +	{ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1 },
> +	{ 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
> +	{ 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 7, 6, 6, 5, 4, 4, 3, 3, 2, 1 },
> +	{ 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 2, 1 },
> +	{ 13, 12, 12, 11, 11, 11, 11, 11, 11, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4, 3, 3,
> +	  2, 2 },
> +	{ 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 10, 9, 8, 8, 7, 6, 6, 5,
> +	  5, 4, 4 }
> +};
> +
> +static const u8
> rc_range_maxqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_
> MAX_NUM_BPP] = {
> +	{ 8, 8, 7, 6, 4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 8, 8, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 9, 9, 9, 8, 8, 7, 6, 5, 4, 3, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0 },
> +	{ 10, 10, 10, 9, 9, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 0,
> +	  0 },
> +	{ 11, 11, 11, 10, 10, 8, 7, 6, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 1, 1, 1,
> +	  0 },
> +	{ 11, 11, 11, 10, 10, 9, 8, 7, 6, 6, 6, 5, 4, 4, 3, 3, 2, 2, 2, 2, 2, 1,
> +	  1 },
> +	{ 11, 11, 11, 11, 11, 10, 9, 8, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 3, 2, 2, 2,
> +	  1 },
> +	{ 12, 12, 12, 12, 12, 11, 10, 9, 8, 8, 8, 7, 6, 5, 5, 4, 3, 3, 3, 2, 2,
> +	  2, 1 },
> +	{ 13, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 3,
> +	  2, 2 },
> +	{ 14, 14, 13, 13, 13, 12, 11, 10, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3,
> +	  2, 2 },
> +	{ 14, 14, 14, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4, 4,
> +	  3, 3, 2 },
> +	{ 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4,
> +	  4, 3, 2 },
> +	{ 15, 15, 15, 14, 13, 13, 13, 12, 11, 11, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4,
> +	  4, 3, 2 },
> +	{ 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4,
> +	  4, 3, 3 },
> +	{ 18, 17, 17, 16, 15, 15, 14, 13, 13, 12, 11, 11, 11, 10, 9, 9, 8, 7, 7,
> +	  6, 6, 5, 5 }
> +};
> +
> +static const u8
> rc_range_minqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_
> MAX_NUM_BPP] = {
> +	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> +	  0, 0, 0, 0, 0 },
> +	{ 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0,
> +	  0, 0, 0, 0, 0 },
> +	{ 9, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 1, 0, 0, 0, 0, 0, 0,
> +	  0, 0, 0, 0, 0 },
> +	{ 10, 9, 9, 8, 8, 8, 7, 7, 6, 6, 6, 5, 5, 4, 4, 3, 2, 2, 1, 1, 1, 0, 0, 0,
> +	  0, 0, 0, 0, 0 },
> +	{ 11, 10, 10, 10, 10, 9, 9, 8, 7, 6, 6, 6, 6, 5, 5, 4, 3, 3, 3, 2, 2, 1,
> +	  0, 0, 0, 0, 0, 0, 0 },
> +	{ 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 7, 6, 5, 5, 4, 4, 3, 3, 3, 2,
> +	  1, 1, 0, 0, 0, 0, 0 },
> +	{ 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 7, 6, 5, 5, 5, 5, 4, 3, 3,
> +	  2, 1, 1, 1, 1, 1, 0 },
> +	{ 11, 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 8, 8, 7, 6, 6, 5, 4, 4,
> +	  3, 2, 2, 1, 1, 1, 1, 1 },
> +	{ 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5,
> +	  5, 4, 4, 2, 2, 1, 1, 1, 1 },
> +	{ 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6,
> +	  5, 4, 4, 3, 2, 2, 1, 1, 1 },
> +	{ 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7,
> +	  6, 5, 4, 3, 3, 2, 2, 1, 1 },
> +	{ 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12, 11, 10, 10, 9, 8, 8,
> +	  7, 7, 6, 5, 4, 3, 3, 2, 2, 1 },
> +	{ 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
> +	  7, 7, 6, 5, 4, 4, 3, 2, 2, 1 },
> +	{ 15, 15, 15, 15, 15, 15, 15, 15, 15, 14, 13, 13, 12, 11, 11, 10, 9, 9, 8,
> +	  8, 7, 6, 6, 5, 4, 4, 3, 3, 2 },
> +	{ 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 14, 13, 12, 12, 11, 10,
> +	  10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4 }
> +};
> +
> +static const u8
> rc_range_maxqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_
> MAX_NUM_BPP] = {
> +	{ 11, 10, 9, 8, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0,
> +	  0, 0, 0, 0, 0, 0 },
> +	{ 12, 11, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1,
> +	  1, 0, 0, 0, 0, 0, 0 },
> +	{ 13, 12, 12, 11, 11, 10, 9, 8, 7, 6, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1,
> +	  1, 0, 0, 0, 0, 0, 0 },
> +	{ 14, 13, 13, 12, 12, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1,
> +	  1, 1, 0, 0, 0, 0, 0 },
> +	{ 15, 14, 14, 13, 13, 11, 10, 9, 8, 7, 7, 7, 7, 6, 6, 5, 4, 4, 4, 3, 3, 2,
> +	  1, 1, 1, 0, 0, 0, 0 },
> +	{ 15, 15, 15, 14, 14, 13, 12, 11, 10, 10, 10, 9, 8, 7, 6, 6, 5, 5, 4, 4,
> +	  4, 3, 2, 2, 1, 1, 0, 0, 0 },
> +	{ 15, 15, 15, 15, 15, 14, 13, 12, 11, 11, 11, 10, 9, 8, 7, 6, 6, 6, 6, 5,
> +	  4, 4, 3, 2, 2, 2, 1, 1, 0 },
> +	{ 16, 16, 16, 16, 16, 15, 14, 13, 12, 12, 12, 11, 10, 9, 9, 8, 7, 7, 6, 5,
> +	  5, 4, 3, 3, 2, 2, 2, 1, 1 },
> +	{ 17, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8, 7,
> +	  6, 6, 5, 5, 3, 3, 2, 2, 1, 1 },
> +	{ 18, 18, 17, 17, 17, 16, 15, 14, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
> +	  7, 6, 5, 5, 4, 3, 3, 2, 2, 1 },
> +	{ 18, 18, 18, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 10, 9, 9, 8,
> +	  8, 7, 6, 5, 4, 4, 3, 3, 2, 2 },
> +	{ 19, 19, 18, 18, 17, 17, 16, 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 9,
> +	  9, 8, 8, 7, 6, 5, 4, 4, 3, 3, 2 },
> +	{ 19, 19, 19, 18, 17, 17, 17, 16, 15, 15, 14, 13, 13, 12, 12, 11, 10, 9,
> +	  9, 8, 8, 7, 6, 5, 5, 4, 3, 3, 2 },
> +	{ 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10,
> +	  9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3 },
> +	{ 22, 21, 21, 20, 19, 19, 18, 17, 17, 16, 15, 15, 15, 14, 13, 13, 12, 11,
> +	  11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5 } };
> +
> +#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420)  do { \
> +	if (bpc == (_bpc)) {	\
> +		if (_is_420)	\
> +			return
> rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
> +		else	\
> +			return
> rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
> +	}	\
>  } while (0)
> 
> -u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i)
> +u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool
> +is_420)
>  {
> -	PARAM_TABLE(min, 8, buf_i, bpp_i);
> -	PARAM_TABLE(min, 10, buf_i, bpp_i);
> -	PARAM_TABLE(min, 12, buf_i, bpp_i);
> +	PARAM_TABLE(min, 8, buf_i, bpp_i, is_420);
> +	PARAM_TABLE(min, 10, buf_i, bpp_i, is_420);
> +	PARAM_TABLE(min, 12, buf_i, bpp_i, is_420);
> 
>  	MISSING_CASE(bpc);
>  	return 0;
>  }
> 
> -u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i)
> +u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool
> +is_420)
>  {
> -	PARAM_TABLE(max, 8, buf_i, bpp_i);
> -	PARAM_TABLE(max, 10, buf_i, bpp_i);
> -	PARAM_TABLE(max, 12, buf_i, bpp_i);
> +	PARAM_TABLE(max, 8, buf_i, bpp_i, is_420);
> +	PARAM_TABLE(max, 10, buf_i, bpp_i, is_420);
> +	PARAM_TABLE(max, 12, buf_i, bpp_i, is_420);
> 
>  	MISSING_CASE(bpc);
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h
> b/drivers/gpu/drm/i915/display/intel_qp_tables.h
> index 9fb3c36bd7c6..a9ff9ca29938 100644
> --- a/drivers/gpu/drm/i915/display/intel_qp_tables.h
> +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h
> @@ -8,7 +8,7 @@
> 
>  #include <linux/types.h>
> 
> -u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i);
> -u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i);
> +u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool
> +is_420);
> +u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool
> +is_420);
> 
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 207b2a648d32..ed16f63d6355 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -422,9 +422,9 @@ calculate_rc_params(struct rc_parameters *rc,
>  	for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
>  		/* Read range_minqp and range_max_qp from qp tables */
>  		rc->rc_range_params[buf_i].range_min_qp =
> -			intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
> +			intel_lookup_range_min_qp(bpc, buf_i, bpp_i, vdsc_cfg-
> >native_420);
>  		rc->rc_range_params[buf_i].range_max_qp =
> -			intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
> +			intel_lookup_range_max_qp(bpc, buf_i, bpp_i, vdsc_cfg-
> >native_420);
> 
>  		/* Calculate range_bgp_offset */
>  		if (bpp <= 6) {
> --
> 2.25.1

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Enable YCbCr420 for VDSC

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, February 22, 2023 11:02 AM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>; Kulkarni,
> Vandita <vandita.kulkarni@intel.com>
> Subject: [PATCH 4/7] drm/i915: Enable YCbCr420 for VDSC

drm/i915/dsc is better

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Implementation of VDSC for YCbCr420.
> Add QP tables for 8,10,12 BPC from rc_tables.h in intel_qp_tables.c (Derived from C-
> Model, which is given along with DSC1.2a Spec from Vesa)
> intel_lookup_range_min/max_qp functons need to take into account the output
> format. Based on that appropriate qp table need to be chosen.
> Other rc_parameters need to be set where currently values for 444 format is
> hardcoded in calculate_rc_parameters( ).
> vdsc_cfg struct needs to be filled with output format information, where these are
> hardcoded for 444 format.
> Bspec: 49259
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
>  .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
>  drivers/gpu/drm/i915/display/intel_vdsc.c     |   4 +-
>  3 files changed, 180 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c
> b/drivers/gpu/drm/i915/display/intel_qp_tables.c
> index 6f8e4ec5c0fb..6e86c0971d24 100644
> --- a/drivers/gpu/drm/i915/display/intel_qp_tables.c
> +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
> @@ -17,6 +17,15 @@
>  /* from BPP 6 to 36 in steps of 0.5 */
>  #define RC_RANGE_QP444_12BPC_MAX_NUM_BPP	61
> 
> +/* from BPP 6 to 24 in steps of 0.5 */
> +#define RC_RANGE_QP420_8BPC_MAX_NUM_BPP		17
> +
> +/* from BPP 6 to 30 in steps of 0.5 */
> +#define RC_RANGE_QP420_10BPC_MAX_NUM_BPP	23
> +
> +/* from BPP 6 to 36 in steps of 0.5 */
> +#define RC_RANGE_QP420_12BPC_MAX_NUM_BPP	29
> +
>  /*
>   * These qp tables are as per the C model
>   * and it has the rows pointing to bpps which increment @@ -283,26 +292,182 @@
> static const u8
> rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC
>  	  11, 11, 10, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4 }  };
> 
> -#define PARAM_TABLE(_minmax, _bpc, _row, _col)  do { \
> -	if (bpc == (_bpc)) \
> -		return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
> +static const u8
> rc_range_minqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MA
> X_NUM_BPP] = {
> +	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 },
> +	{ 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
> +	{ 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
> +	{ 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
> +	{ 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 0 },
> +	{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1 },
> +	{ 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 1, 1 },
> +	{ 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 2, 2, 1 },
> +	{ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 3, 3, 2, 1 },
> +	{ 9, 8, 8, 7, 7, 7, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 2 },
> +	{ 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3 } };
> +
> +static const u8
> rc_range_maxqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MA
> X_NUM_BPP] = {
> +	{ 4, 4, 3, 3, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 4, 4, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
> +	{ 5, 5, 5, 5, 5, 4, 3, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
> +	{ 6, 6, 6, 6, 6, 5, 4, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0 },
> +	{ 7, 7, 7, 7, 7, 5, 4, 3, 2, 2, 2, 2, 2, 1, 1, 1, 0 },
> +	{ 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 2, 2, 2, 1, 1, 0 },
> +	{ 7, 7, 7, 7, 7, 6, 5, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1 },
> +	{ 8, 8, 8, 8, 8, 7, 6, 5, 4, 4, 4, 3, 3, 2, 2, 2, 1 },
> +	{ 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
> +	{ 10, 10, 9, 9, 9, 8, 7, 6, 5, 5, 5, 4, 4, 3, 3, 2, 2 },
> +	{ 10, 10, 10, 9, 9, 8, 8, 7, 6, 6, 5, 5, 4, 4, 3, 2, 2 },
> +	{ 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2 },
> +	{ 11, 11, 11, 10, 9, 9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3, 2 },
> +	{ 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4, 4, 4, 3 },
> +	{ 14, 13, 13, 12, 11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5, 5, 4 } };
> +
> +static const u8
> rc_range_minqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_
> MAX_NUM_BPP] = {
> +	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0 },
> +	{ 7, 7, 7, 7, 7, 6, 5, 5, 5, 5, 5, 4, 3, 3, 2, 2, 1, 1, 1, 1, 1, 0, 0 },
> +	{ 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 2, 2, 1, 1, 1, 0 },
> +	{ 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5, 4, 4, 4, 3, 2, 2, 2, 1, 1, 1, 0 },
> +	{ 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 2, 1, 1 },
> +	{ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1, 1 },
> +	{ 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 5, 5, 4, 4, 3, 3, 2, 2, 1 },
> +	{ 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 7, 6, 6, 5, 4, 4, 3, 3, 2, 1 },
> +	{ 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 2, 1 },
> +	{ 13, 12, 12, 11, 11, 11, 11, 11, 11, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4, 3, 3,
> +	  2, 2 },
> +	{ 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 10, 9, 8, 8, 7, 6, 6, 5,
> +	  5, 4, 4 }
> +};
> +
> +static const u8
> rc_range_maxqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_
> MAX_NUM_BPP] = {
> +	{ 8, 8, 7, 6, 4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 8, 8, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
> +	{ 9, 9, 9, 8, 8, 7, 6, 5, 4, 3, 3, 3, 3, 3, 2, 1, 1, 1, 0, 0, 0, 0, 0 },
> +	{ 10, 10, 10, 9, 9, 8, 7, 6, 5, 4, 4, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 0,
> +	  0 },
> +	{ 11, 11, 11, 10, 10, 8, 7, 6, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2, 1, 1, 1,
> +	  0 },
> +	{ 11, 11, 11, 10, 10, 9, 8, 7, 6, 6, 6, 5, 4, 4, 3, 3, 2, 2, 2, 2, 2, 1,
> +	  1 },
> +	{ 11, 11, 11, 11, 11, 10, 9, 8, 7, 7, 7, 6, 5, 5, 4, 3, 3, 3, 3, 2, 2, 2,
> +	  1 },
> +	{ 12, 12, 12, 12, 12, 11, 10, 9, 8, 8, 8, 7, 6, 5, 5, 4, 3, 3, 3, 2, 2,
> +	  2, 1 },
> +	{ 13, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3, 3,
> +	  2, 2 },
> +	{ 14, 14, 13, 13, 13, 12, 11, 10, 9, 9, 9, 8, 8, 7, 7, 6, 5, 4, 4, 3, 3,
> +	  2, 2 },
> +	{ 14, 14, 14, 13, 13, 12, 12, 11, 10, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4, 4,
> +	  3, 3, 2 },
> +	{ 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 10, 9, 9, 8, 7, 7, 6, 5, 5, 4,
> +	  4, 3, 2 },
> +	{ 15, 15, 15, 14, 13, 13, 13, 12, 11, 11, 10, 9, 9, 8, 8, 7, 6, 5, 5, 4,
> +	  4, 3, 2 },
> +	{ 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10, 9, 8, 8, 7, 6, 6, 5, 4,
> +	  4, 3, 3 },
> +	{ 18, 17, 17, 16, 15, 15, 14, 13, 13, 12, 11, 11, 11, 10, 9, 9, 8, 7, 7,
> +	  6, 6, 5, 5 }
> +};
> +
> +static const u8
> rc_range_minqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_
> MAX_NUM_BPP] = {
> +	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
> +	  0, 0, 0, 0, 0 },
> +	{ 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0,
> +	  0, 0, 0, 0, 0 },
> +	{ 9, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3, 3, 3, 2, 2, 1, 0, 0, 0, 0, 0, 0,
> +	  0, 0, 0, 0, 0 },
> +	{ 10, 9, 9, 8, 8, 8, 7, 7, 6, 6, 6, 5, 5, 4, 4, 3, 2, 2, 1, 1, 1, 0, 0, 0,
> +	  0, 0, 0, 0, 0 },
> +	{ 11, 10, 10, 10, 10, 9, 9, 8, 7, 6, 6, 6, 6, 5, 5, 4, 3, 3, 3, 2, 2, 1,
> +	  0, 0, 0, 0, 0, 0, 0 },
> +	{ 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 7, 6, 5, 5, 4, 4, 3, 3, 3, 2,
> +	  1, 1, 0, 0, 0, 0, 0 },
> +	{ 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 7, 6, 5, 5, 5, 5, 4, 3, 3,
> +	  2, 1, 1, 1, 1, 1, 0 },
> +	{ 11, 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 9, 8, 8, 8, 7, 6, 6, 5, 4, 4,
> +	  3, 2, 2, 1, 1, 1, 1, 1 },
> +	{ 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6, 5,
> +	  5, 4, 4, 2, 2, 1, 1, 1, 1 },
> +	{ 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7, 6,
> +	  5, 4, 4, 3, 2, 2, 1, 1, 1 },
> +	{ 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 11, 11, 10, 10, 9, 9, 8, 8, 7, 7,
> +	  6, 5, 4, 3, 3, 2, 2, 1, 1 },
> +	{ 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12, 11, 10, 10, 9, 8, 8,
> +	  7, 7, 6, 5, 4, 3, 3, 2, 2, 1 },
> +	{ 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
> +	  7, 7, 6, 5, 4, 4, 3, 2, 2, 1 },
> +	{ 15, 15, 15, 15, 15, 15, 15, 15, 15, 14, 13, 13, 12, 11, 11, 10, 9, 9, 8,
> +	  8, 7, 6, 6, 5, 4, 4, 3, 3, 2 },
> +	{ 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 14, 13, 12, 12, 11, 10,
> +	  10, 10, 9, 8, 8, 7, 6, 6, 5, 5, 4 }
> +};
> +
> +static const u8
> rc_range_maxqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_
> MAX_NUM_BPP] = {
> +	{ 11, 10, 9, 8, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0,
> +	  0, 0, 0, 0, 0, 0 },
> +	{ 12, 11, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1,
> +	  1, 0, 0, 0, 0, 0, 0 },
> +	{ 13, 12, 12, 11, 11, 10, 9, 8, 7, 6, 6, 6, 5, 5, 4, 3, 3, 2, 1, 1, 1, 1,
> +	  1, 0, 0, 0, 0, 0, 0 },
> +	{ 14, 13, 13, 12, 12, 11, 10, 9, 8, 7, 7, 6, 6, 5, 5, 4, 3, 3, 2, 2, 2, 1,
> +	  1, 1, 0, 0, 0, 0, 0 },
> +	{ 15, 14, 14, 13, 13, 11, 10, 9, 8, 7, 7, 7, 7, 6, 6, 5, 4, 4, 4, 3, 3, 2,
> +	  1, 1, 1, 0, 0, 0, 0 },
> +	{ 15, 15, 15, 14, 14, 13, 12, 11, 10, 10, 10, 9, 8, 7, 6, 6, 5, 5, 4, 4,
> +	  4, 3, 2, 2, 1, 1, 0, 0, 0 },
> +	{ 15, 15, 15, 15, 15, 14, 13, 12, 11, 11, 11, 10, 9, 8, 7, 6, 6, 6, 6, 5,
> +	  4, 4, 3, 2, 2, 2, 1, 1, 0 },
> +	{ 16, 16, 16, 16, 16, 15, 14, 13, 12, 12, 12, 11, 10, 9, 9, 8, 7, 7, 6, 5,
> +	  5, 4, 3, 3, 2, 2, 2, 1, 1 },
> +	{ 17, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8, 7,
> +	  6, 6, 5, 5, 3, 3, 2, 2, 1, 1 },
> +	{ 18, 18, 17, 17, 17, 16, 15, 14, 13, 13, 13, 12, 12, 11, 11, 10, 9, 8, 8,
> +	  7, 6, 5, 5, 4, 3, 3, 2, 2, 1 },
> +	{ 18, 18, 18, 17, 17, 16, 16, 15, 14, 14, 13, 13, 12, 12, 11, 10, 9, 9, 8,
> +	  8, 7, 6, 5, 4, 4, 3, 3, 2, 2 },
> +	{ 19, 19, 18, 18, 17, 17, 16, 15, 15, 14, 14, 13, 13, 12, 11, 11, 10, 9,
> +	  9, 8, 8, 7, 6, 5, 4, 4, 3, 3, 2 },
> +	{ 19, 19, 19, 18, 17, 17, 17, 16, 15, 15, 14, 13, 13, 12, 12, 11, 10, 9,
> +	  9, 8, 8, 7, 6, 5, 5, 4, 3, 3, 2 },
> +	{ 21, 20, 20, 19, 18, 18, 17, 16, 16, 15, 14, 14, 13, 12, 12, 11, 10, 10,
> +	  9, 9, 8, 7, 7, 6, 5, 5, 4, 4, 3 },
> +	{ 22, 21, 21, 20, 19, 19, 18, 17, 17, 16, 15, 15, 15, 14, 13, 13, 12, 11,
> +	  11, 11, 10, 9, 9, 8, 7, 7, 6, 6, 5 } };
> +
> +#define PARAM_TABLE(_minmax, _bpc, _row, _col, _is_420)  do { \
> +	if (bpc == (_bpc)) {	\
> +		if (_is_420)	\
> +			return
> rc_range_##_minmax##qp420_##_bpc##bpc[_row][_col]; \
> +		else	\
> +			return
> rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
> +	}	\
>  } while (0)
> 
> -u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i)
> +u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool
> +is_420)
>  {
> -	PARAM_TABLE(min, 8, buf_i, bpp_i);
> -	PARAM_TABLE(min, 10, buf_i, bpp_i);
> -	PARAM_TABLE(min, 12, buf_i, bpp_i);
> +	PARAM_TABLE(min, 8, buf_i, bpp_i, is_420);
> +	PARAM_TABLE(min, 10, buf_i, bpp_i, is_420);
> +	PARAM_TABLE(min, 12, buf_i, bpp_i, is_420);
> 
>  	MISSING_CASE(bpc);
>  	return 0;
>  }
> 
> -u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i)
> +u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool
> +is_420)
>  {
> -	PARAM_TABLE(max, 8, buf_i, bpp_i);
> -	PARAM_TABLE(max, 10, buf_i, bpp_i);
> -	PARAM_TABLE(max, 12, buf_i, bpp_i);
> +	PARAM_TABLE(max, 8, buf_i, bpp_i, is_420);
> +	PARAM_TABLE(max, 10, buf_i, bpp_i, is_420);
> +	PARAM_TABLE(max, 12, buf_i, bpp_i, is_420);
> 
>  	MISSING_CASE(bpc);
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h
> b/drivers/gpu/drm/i915/display/intel_qp_tables.h
> index 9fb3c36bd7c6..a9ff9ca29938 100644
> --- a/drivers/gpu/drm/i915/display/intel_qp_tables.h
> +++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h
> @@ -8,7 +8,7 @@
> 
>  #include <linux/types.h>
> 
> -u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i);
> -u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i);
> +u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i, bool
> +is_420);
> +u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i, bool
> +is_420);
> 
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 207b2a648d32..ed16f63d6355 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -422,9 +422,9 @@ calculate_rc_params(struct rc_parameters *rc,
>  	for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
>  		/* Read range_minqp and range_max_qp from qp tables */
>  		rc->rc_range_params[buf_i].range_min_qp =
> -			intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
> +			intel_lookup_range_min_qp(bpc, buf_i, bpp_i, vdsc_cfg-
> >native_420);
>  		rc->rc_range_params[buf_i].range_max_qp =
> -			intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
> +			intel_lookup_range_max_qp(bpc, buf_i, bpp_i, vdsc_cfg-
> >native_420);
> 
>  		/* Calculate range_bgp_offset */
>  		if (bpp <= 6) {
> --
> 2.25.1

RE: [PATCH v2 5/7] drm/i915/display: Fill in native_420 field

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Friday, March 3, 2023 11:05 AM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>; Jani Nikula
> <jani.nikula@linux.intel.com>
> Subject: [PATCH v2 5/7] drm/i915/display: Fill in native_420 field

I asked to add "display" but please change to "/drm/i915/dsc" as that is more relevant.
Use that for whole series.

Change Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Now that we have laid the groundwork for YUV420 Enablement we fill up native_420
> field in vdsc_cfg and add appropriate checks wherever required.
> 
> ---v2
> -adding native_422 field as 0 [Vandita]
> -filling in second_line_bpg_offset, second_line_offset_adj and nsl_bpg_offset in
> vds_cfg when native_420 is true
> 
> ---v3
> -adding display version check to solve igt issue
> 
> --v7
> -remove is_pipe_dsc check as its always true for D14 [Jani]
> 
> --v10
> -keep sink capability check [Jani]
> -move from !(x == y  || w == z) to x !=y && w != z [Jani]
> 
> --v11
> -avoid native_420 computation if not gen14 [Uma]
> 
> --v12
> -fix state mismatch issue of compressed_bpp
> 
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c    |  2 -
>  drivers/gpu/drm/i915/display/intel_dp.c   | 16 +++-
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 98 ++++++++++++++++++++---
>  3 files changed, 100 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index b5316715bb3b..fb7efab8e9e6 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1539,8 +1539,6 @@ static int gen11_dsi_dsc_compute_config(struct
> intel_encoder *encoder,
>  	if (crtc_state->dsc.slice_count > 1)
>  		crtc_state->dsc.dsc_split = true;
> 
> -	vdsc_cfg->convert_rgb = true;
> -
>  	/* FIXME: initialize from VBT */
>  	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2649e8b8ef57..86b9348b74bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1467,9 +1467,10 @@ static int intel_dp_dsc_compute_params(struct
> intel_encoder *encoder,
>  	vdsc_cfg->dsc_version_minor =
>  		min(intel_dp_source_dsc_version_minor(intel_dp),
>  		    intel_dp_sink_dsc_version_minor(intel_dp));
> -
> -	vdsc_cfg->convert_rgb = intel_dp-
> >dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
> -		DP_DSC_RGB;
> +	if (vdsc_cfg->convert_rgb)
> +		vdsc_cfg->convert_rgb =
> +			intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP -
> DP_DSC_SUPPORT] &
> +			DP_DSC_RGB;
> 
>  	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
>  	if (!line_buf_depth) {
> @@ -1587,6 +1588,15 @@ int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
>  							    pipe_config-
> >bigjoiner_pipes,
>  							    pipe_bpp,
>  							    timeslots);
> +			/*
> +			 * According to DSC 1.2a Section 4.1.1 Table 4.1 the
> maximum
> +			 * supported PPS value can be 63.9375 and with the further
> +			 * mention that bpp should be programmed double the
> target bpp
> +			 * restricting our target bpp to be 31.9375 at max
> +			 */
> +			if (pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> +				dsc_max_output_bpp = min_t(u16,
> dsc_max_output_bpp, 31 << 4);
> +
>  			if (!dsc_max_output_bpp) {
>  				drm_dbg_kms(&dev_priv->drm,
>  					    "Compressed BPP not supported\n"); diff
> --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index ed16f63d6355..44243fc81b46 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -460,14 +460,50 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
>  	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
>  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
>  					     pipe_config->dsc.slice_count);
> -
> -	/* Gen 11 does not support YCbCr */
> +	/*
> +	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
> +	 * else 1
> +	 */
> +	vdsc_cfg->convert_rgb = pipe_config->output_format !=
> INTEL_OUTPUT_FORMAT_YCBCR420 &&
> +				pipe_config->output_format !=
> INTEL_OUTPUT_FORMAT_YCBCR444;
> +
> +	if (DISPLAY_VER(dev_priv) >= 14 &&
> +	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> +		vdsc_cfg->native_420 = true;
> +	/* We do not support YcBCr422 as of now */
> +	vdsc_cfg->native_422 = false;
>  	vdsc_cfg->simple_422 = false;
>  	/* Gen 11 does not support VBR */
>  	vdsc_cfg->vbr_enable = false;
> 
>  	/* Gen 11 only supports integral values of bpp */
>  	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> +
> +	/*
> +	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set:
> +	 * -We need to double the current bpp.
> +	 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if
> slice
> +	 * height < 8.
> +	 * -second_line_offset_adj is 512 as shown by emperical values to yeild best
> chroma
> +	 * preservation in second line.
> +	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then
> rounded
> +	 * up to 16 fractional bits, we left shift second line offset by 11 to preserve
> 11
> +	 * fractional bits.
> +	 */
> +	if (vdsc_cfg->native_420) {
> +		vdsc_cfg->bits_per_pixel <<= 1;
> +
> +		if (vdsc_cfg->slice_height >= 8)
> +			vdsc_cfg->second_line_bpg_offset = 12;
> +		else
> +			vdsc_cfg->second_line_bpg_offset =
> +				2 * (vdsc_cfg->slice_height - 1);
> +
> +		vdsc_cfg->second_line_offset_adj = 512;
> +		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg-
> >second_line_bpg_offset << 11,
> +							vdsc_cfg->slice_height - 1);
> +	}
> +
>  	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> 
>  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { @@ -594,8 +630,13 @@
> static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>  		DSC_VER_MIN_SHIFT |
>  		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
>  		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
> -	if (vdsc_cfg->dsc_version_minor == 2)
> +	if (vdsc_cfg->dsc_version_minor == 2) {
>  		pps_val |= DSC_ALT_ICH_SEL;
> +		if (vdsc_cfg->native_420)
> +			pps_val |= DSC_NATIVE_420_ENABLE;
> +		if (vdsc_cfg->native_422)
> +			pps_val |= DSC_NATIVE_422_ENABLE;
> +	}
>  	if (vdsc_cfg->block_pred_enable)
>  		pps_val |= DSC_BLOCK_PREDICTION;
>  	if (vdsc_cfg->convert_rgb)
> @@ -906,6 +947,33 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  				       pps_val);
>  	}
> 
> +	if (DISPLAY_VER(dev_priv) >= 14) {
> +		/* Populate PICTURE_PARAMETER_SET_17 registers */
> +		pps_val = 0;
> +		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg-
> >second_line_bpg_offset);
> +		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
> +		intel_de_write(dev_priv,
> +			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
> +			       pps_val);
> +		if (crtc_state->dsc.dsc_split)
> +			intel_de_write(dev_priv,
> +
> MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
> +				       pps_val);
> +
> +		/* Populate PICTURE_PARAMETER_SET_18 registers */
> +		pps_val = 0;
> +		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
> +			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
> +		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
> +		intel_de_write(dev_priv,
> +			       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
> +			       pps_val);
> +		if (crtc_state->dsc.dsc_split)
> +			intel_de_write(dev_priv,
> +
> MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
> +				       pps_val);
> +	}
> +
>  	/* Populate the RC_BUF_THRESH registers */
>  	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
>  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { @@ -1180,7 +1248,7 @@
> void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>  	enum pipe pipe = crtc->pipe;
>  	enum intel_display_power_domain power_domain;
>  	intel_wakeref_t wakeref;
> -	u32 dss_ctl1, dss_ctl2, val;
> +	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0;
> 
>  	if (!intel_dsc_source_support(crtc_state))
>  		return;
> @@ -1203,13 +1271,21 @@ void intel_dsc_get_config(struct intel_crtc_state
> *crtc_state)
> 
>  	/* FIXME: add more state readout as needed */
> 
> -	/* PPS1 */
> -	if (!is_pipe_dsc(crtc, cpu_transcoder))
> -		val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
> -	else
> -		val = intel_de_read(dev_priv,
> -				    ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> -	vdsc_cfg->bits_per_pixel = val;
> +	/* PPS0 & PPS1 */
> +	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> +		pps1 = intel_de_read(dev_priv,
> DSCA_PICTURE_PARAMETER_SET_1);
> +	} else {
> +		pps0 = intel_de_read(dev_priv,
> +				     ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> +		pps1 = intel_de_read(dev_priv,
> +				     ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> +	}
> +
> +	vdsc_cfg->bits_per_pixel = pps1;
> +
> +	if (pps0 & DSC_NATIVE_420_ENABLE)
> +		vdsc_cfg->bits_per_pixel >>= 1;
> +
>  	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
>  out:
>  	intel_display_power_put(dev_priv, power_domain, wakeref);
> --
> 2.25.1

Re: [Intel-gfx] [PATCH v2 5/7] drm/i915/display: Fill in native_420 field

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Friday, March 3, 2023 11:05 AM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>; Jani Nikula
> <jani.nikula@linux.intel.com>
> Subject: [PATCH v2 5/7] drm/i915/display: Fill in native_420 field

I asked to add "display" but please change to "/drm/i915/dsc" as that is more relevant.
Use that for whole series.

Change Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Now that we have laid the groundwork for YUV420 Enablement we fill up native_420
> field in vdsc_cfg and add appropriate checks wherever required.
> 
> ---v2
> -adding native_422 field as 0 [Vandita]
> -filling in second_line_bpg_offset, second_line_offset_adj and nsl_bpg_offset in
> vds_cfg when native_420 is true
> 
> ---v3
> -adding display version check to solve igt issue
> 
> --v7
> -remove is_pipe_dsc check as its always true for D14 [Jani]
> 
> --v10
> -keep sink capability check [Jani]
> -move from !(x == y  || w == z) to x !=y && w != z [Jani]
> 
> --v11
> -avoid native_420 computation if not gen14 [Uma]
> 
> --v12
> -fix state mismatch issue of compressed_bpp
> 
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c    |  2 -
>  drivers/gpu/drm/i915/display/intel_dp.c   | 16 +++-
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 98 ++++++++++++++++++++---
>  3 files changed, 100 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index b5316715bb3b..fb7efab8e9e6 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1539,8 +1539,6 @@ static int gen11_dsi_dsc_compute_config(struct
> intel_encoder *encoder,
>  	if (crtc_state->dsc.slice_count > 1)
>  		crtc_state->dsc.dsc_split = true;
> 
> -	vdsc_cfg->convert_rgb = true;
> -
>  	/* FIXME: initialize from VBT */
>  	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 2649e8b8ef57..86b9348b74bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1467,9 +1467,10 @@ static int intel_dp_dsc_compute_params(struct
> intel_encoder *encoder,
>  	vdsc_cfg->dsc_version_minor =
>  		min(intel_dp_source_dsc_version_minor(intel_dp),
>  		    intel_dp_sink_dsc_version_minor(intel_dp));
> -
> -	vdsc_cfg->convert_rgb = intel_dp-
> >dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
> -		DP_DSC_RGB;
> +	if (vdsc_cfg->convert_rgb)
> +		vdsc_cfg->convert_rgb =
> +			intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP -
> DP_DSC_SUPPORT] &
> +			DP_DSC_RGB;
> 
>  	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
>  	if (!line_buf_depth) {
> @@ -1587,6 +1588,15 @@ int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
>  							    pipe_config-
> >bigjoiner_pipes,
>  							    pipe_bpp,
>  							    timeslots);
> +			/*
> +			 * According to DSC 1.2a Section 4.1.1 Table 4.1 the
> maximum
> +			 * supported PPS value can be 63.9375 and with the further
> +			 * mention that bpp should be programmed double the
> target bpp
> +			 * restricting our target bpp to be 31.9375 at max
> +			 */
> +			if (pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420)
> +				dsc_max_output_bpp = min_t(u16,
> dsc_max_output_bpp, 31 << 4);
> +
>  			if (!dsc_max_output_bpp) {
>  				drm_dbg_kms(&dev_priv->drm,
>  					    "Compressed BPP not supported\n"); diff
> --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index ed16f63d6355..44243fc81b46 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -460,14 +460,50 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
>  	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
>  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
>  					     pipe_config->dsc.slice_count);
> -
> -	/* Gen 11 does not support YCbCr */
> +	/*
> +	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
> +	 * else 1
> +	 */
> +	vdsc_cfg->convert_rgb = pipe_config->output_format !=
> INTEL_OUTPUT_FORMAT_YCBCR420 &&
> +				pipe_config->output_format !=
> INTEL_OUTPUT_FORMAT_YCBCR444;
> +
> +	if (DISPLAY_VER(dev_priv) >= 14 &&
> +	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> +		vdsc_cfg->native_420 = true;
> +	/* We do not support YcBCr422 as of now */
> +	vdsc_cfg->native_422 = false;
>  	vdsc_cfg->simple_422 = false;
>  	/* Gen 11 does not support VBR */
>  	vdsc_cfg->vbr_enable = false;
> 
>  	/* Gen 11 only supports integral values of bpp */
>  	vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
> +
> +	/*
> +	 * According to DSC 1.2 specs in Section 4.1 if native_420 is set:
> +	 * -We need to double the current bpp.
> +	 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if
> slice
> +	 * height < 8.
> +	 * -second_line_offset_adj is 512 as shown by emperical values to yeild best
> chroma
> +	 * preservation in second line.
> +	 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then
> rounded
> +	 * up to 16 fractional bits, we left shift second line offset by 11 to preserve
> 11
> +	 * fractional bits.
> +	 */
> +	if (vdsc_cfg->native_420) {
> +		vdsc_cfg->bits_per_pixel <<= 1;
> +
> +		if (vdsc_cfg->slice_height >= 8)
> +			vdsc_cfg->second_line_bpg_offset = 12;
> +		else
> +			vdsc_cfg->second_line_bpg_offset =
> +				2 * (vdsc_cfg->slice_height - 1);
> +
> +		vdsc_cfg->second_line_offset_adj = 512;
> +		vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg-
> >second_line_bpg_offset << 11,
> +							vdsc_cfg->slice_height - 1);
> +	}
> +
>  	vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
> 
>  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { @@ -594,8 +630,13 @@
> static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>  		DSC_VER_MIN_SHIFT |
>  		vdsc_cfg->bits_per_component << DSC_BPC_SHIFT |
>  		vdsc_cfg->line_buf_depth << DSC_LINE_BUF_DEPTH_SHIFT;
> -	if (vdsc_cfg->dsc_version_minor == 2)
> +	if (vdsc_cfg->dsc_version_minor == 2) {
>  		pps_val |= DSC_ALT_ICH_SEL;
> +		if (vdsc_cfg->native_420)
> +			pps_val |= DSC_NATIVE_420_ENABLE;
> +		if (vdsc_cfg->native_422)
> +			pps_val |= DSC_NATIVE_422_ENABLE;
> +	}
>  	if (vdsc_cfg->block_pred_enable)
>  		pps_val |= DSC_BLOCK_PREDICTION;
>  	if (vdsc_cfg->convert_rgb)
> @@ -906,6 +947,33 @@ static void intel_dsc_pps_configure(const struct
> intel_crtc_state *crtc_state)
>  				       pps_val);
>  	}
> 
> +	if (DISPLAY_VER(dev_priv) >= 14) {
> +		/* Populate PICTURE_PARAMETER_SET_17 registers */
> +		pps_val = 0;
> +		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg-
> >second_line_bpg_offset);
> +		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
> +		intel_de_write(dev_priv,
> +			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
> +			       pps_val);
> +		if (crtc_state->dsc.dsc_split)
> +			intel_de_write(dev_priv,
> +
> MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
> +				       pps_val);
> +
> +		/* Populate PICTURE_PARAMETER_SET_18 registers */
> +		pps_val = 0;
> +		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
> +			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
> +		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
> +		intel_de_write(dev_priv,
> +			       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
> +			       pps_val);
> +		if (crtc_state->dsc.dsc_split)
> +			intel_de_write(dev_priv,
> +
> MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
> +				       pps_val);
> +	}
> +
>  	/* Populate the RC_BUF_THRESH registers */
>  	memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
>  	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { @@ -1180,7 +1248,7 @@
> void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
>  	enum pipe pipe = crtc->pipe;
>  	enum intel_display_power_domain power_domain;
>  	intel_wakeref_t wakeref;
> -	u32 dss_ctl1, dss_ctl2, val;
> +	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0;
> 
>  	if (!intel_dsc_source_support(crtc_state))
>  		return;
> @@ -1203,13 +1271,21 @@ void intel_dsc_get_config(struct intel_crtc_state
> *crtc_state)
> 
>  	/* FIXME: add more state readout as needed */
> 
> -	/* PPS1 */
> -	if (!is_pipe_dsc(crtc, cpu_transcoder))
> -		val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
> -	else
> -		val = intel_de_read(dev_priv,
> -				    ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> -	vdsc_cfg->bits_per_pixel = val;
> +	/* PPS0 & PPS1 */
> +	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
> +		pps1 = intel_de_read(dev_priv,
> DSCA_PICTURE_PARAMETER_SET_1);
> +	} else {
> +		pps0 = intel_de_read(dev_priv,
> +				     ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
> +		pps1 = intel_de_read(dev_priv,
> +				     ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
> +	}
> +
> +	vdsc_cfg->bits_per_pixel = pps1;
> +
> +	if (pps0 & DSC_NATIVE_420_ENABLE)
> +		vdsc_cfg->bits_per_pixel >>= 1;
> +
>  	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
>  out:
>  	intel_display_power_put(dev_priv, power_domain, wakeref);
> --
> 2.25.1

RE: [PATCH 6/7] drm/i915/vdsc: Check slice design requirement

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, February 22, 2023 11:02 AM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH 6/7] drm/i915/vdsc: Check slice design requirement
> 
> Add function to check if slice design requirements are being met as defined in Bspec:
> 49259 in the section Slice Design Requirement
> 
> --v7
> -remove full bspec link [Jani]
> -rename intel_dsc_check_slice_design_req to intel_dsc_slice_dimensions_valid
> [Jani]
> 
> --v8
> -fix condition to check if slice width and height are of two -fix minimum pixel in slice
> condition
> 
> --v10
> -condition should be < rather then >= [Uma]

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 32997c9773aa..a9585f493318 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -447,6 +447,29 @@ calculate_rc_params(struct rc_parameters *rc,
>  	}
>  }
> 
> +static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config,
> +					    struct drm_dsc_config *vdsc_cfg) {
> +	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
> +	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> +		if (vdsc_cfg->slice_height > 4095)
> +			return -EINVAL;
> +		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000)
> +			return -EINVAL;
> +	} else if (pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420) {
> +		if (vdsc_cfg->slice_width % 2)
> +			return -EINVAL;
> +		if (vdsc_cfg->slice_height % 2)
> +			return -EINVAL;
> +		if (vdsc_cfg->slice_height > 4094)
> +			return -EINVAL;
> +		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000)
> +			return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)  {
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> @@ -455,11 +478,20 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
>  	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
>  	const struct rc_parameters *rc_params;
>  	struct rc_parameters *rc = NULL;
> +	int err;
>  	u8 i = 0;
> 
>  	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
>  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
>  					     pipe_config->dsc.slice_count);
> +
> +	err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
> +
> +	if (err) {
> +		drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not
> met\n");
> +		return err;
> +	}
> +
>  	/*
>  	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
>  	 * else 1
> --
> 2.25.1

Re: [Intel-gfx] [PATCH 6/7] drm/i915/vdsc: Check slice design requirement

[Shankar, Uma]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, February 22, 2023 11:02 AM
> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH 6/7] drm/i915/vdsc: Check slice design requirement
> 
> Add function to check if slice design requirements are being met as defined in Bspec:
> 49259 in the section Slice Design Requirement
> 
> --v7
> -remove full bspec link [Jani]
> -rename intel_dsc_check_slice_design_req to intel_dsc_slice_dimensions_valid
> [Jani]
> 
> --v8
> -fix condition to check if slice width and height are of two -fix minimum pixel in slice
> condition
> 
> --v10
> -condition should be < rather then >= [Uma]

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 32 +++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 32997c9773aa..a9585f493318 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -447,6 +447,29 @@ calculate_rc_params(struct rc_parameters *rc,
>  	}
>  }
> 
> +static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config,
> +					    struct drm_dsc_config *vdsc_cfg) {
> +	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
> +	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
> +		if (vdsc_cfg->slice_height > 4095)
> +			return -EINVAL;
> +		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000)
> +			return -EINVAL;
> +	} else if (pipe_config->output_format ==
> INTEL_OUTPUT_FORMAT_YCBCR420) {
> +		if (vdsc_cfg->slice_width % 2)
> +			return -EINVAL;
> +		if (vdsc_cfg->slice_height % 2)
> +			return -EINVAL;
> +		if (vdsc_cfg->slice_height > 4094)
> +			return -EINVAL;
> +		if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000)
> +			return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)  {
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> @@ -455,11 +478,20 @@ int intel_dsc_compute_params(struct intel_crtc_state
> *pipe_config)
>  	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
>  	const struct rc_parameters *rc_params;
>  	struct rc_parameters *rc = NULL;
> +	int err;
>  	u8 i = 0;
> 
>  	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
>  	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
>  					     pipe_config->dsc.slice_count);
> +
> +	err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
> +
> +	if (err) {
> +		drm_dbg_kms(&dev_priv->drm, "Slice dimension requirements not
> met\n");
> +		return err;
> +	}
> +
>  	/*
>  	 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
>  	 * else 1
> --
> 2.25.1

Re: [Intel-gfx] [PATCH 3/7] drm/i915: Adding the new registers for DSC

[Jani Nikula]

On Wed, 08 Mar 2023, "Shankar, Uma" <uma.shankar@intel.com> wrote:
>> -----Original Message-----
>> From: Kandpal, Suraj <suraj.kandpal@intel.com>
>> Sent: Wednesday, February 22, 2023 11:02 AM
>> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
>> <ankit.k.nautiyal@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>; Kulkarni,
>> Vandita <vandita.kulkarni@intel.com>
>> Subject: [PATCH 3/7] drm/i915: Adding the new registers for DSC
>
> Nit: drm/i915/dsc would be better.
>
> Looks Good to me.
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>

Except since c3f059483671 ("drm/i915/display: split out DSC and DSS
registers") the DSC registers need to go to display/intel_vdsc_regs.h.

BR,
Jani.

>
>> Adding new DSC register which are introducted MTL onwards
>> 
>> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
>>  1 file changed, 28 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 596efc940ee7..9e25e21d37e4 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7715,6 +7715,8 @@ enum skl_power_gate {
>>  #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)	_MMIO_PIPE((pipe) -
>> PIPE_B, \
>> 
>> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
>> 
>> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
>> +#define  DSC_NATIVE_422_ENABLE		BIT(23)
>> +#define  DSC_NATIVE_420_ENABLE		BIT(22)
>>  #define  DSC_ALT_ICH_SEL		(1 << 20)
>>  #define  DSC_VBR_ENABLE			(1 << 19)
>>  #define  DSC_422_ENABLE			(1 << 18)
>> @@ -7959,6 +7961,32 @@ enum skl_power_gate {
>>  #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
>>  #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size)
>> << 0)
>> 
>> +/* MTL Display Stream Compression registers */
>> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB	0x782B4
>> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB	0x783B4
>> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC	0x784B4
>> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC	0x785B4
>> +#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe)
>> 	_MMIO_PIPE((pipe) - PIPE_B, \
>> +
>> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
>> +
>> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
>> +#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)
>> 	_MMIO_PIPE((pipe) - PIPE_B, \
>> +
>> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
>> +
>> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
>> +#define DSC_SL_BPG_OFFSET(offset)		((offset) << 27)
>> +
>> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB	0x782B8
>> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB	0x783B8
>> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC	0x784B8
>> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC	0x785B8
>> +#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe)
>> 	_MMIO_PIPE((pipe) - PIPE_B, \
>> +
>> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
>> +
>> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
>> +#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)
>> 	_MMIO_PIPE((pipe) - PIPE_B, \
>> +
>> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
>> +
>> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
>> +#define DSC_NSL_BPG_OFFSET(offset)		((offset) << 16)
>> +#define DSC_SL_OFFSET_ADJ(offset)		((offset) << 0)
>> +
>>  /* Icelake Rate Control Buffer Threshold Registers */
>>  #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
>>  #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
>> --
>> 2.25.1
>

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [PATCH 0/7] Enable YCbCr420 format for VDSC

[Jani Nikula]

On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> This patch series aims to enable the YCbCr420 format
> for DSC. Changes are mostly compute params related for
> hdmi,dp and dsi along with the addition of new rc_tables
> for native_420 and corresponding changes to macros used to
> fetch them.
> There have been discussions prior to this series in which some patches
> have gotten rb and can be found in the below link
> https://patchwork.freedesktop.org/series/113729

I think it would be useful to get [1] from Dmitry merged to
drm-misc-next first, have that in drm-next, and again backmerged to
drm-intel-next before this. At least patches 1-5.

There's not much point in all drivers duplicating the parameters, and we
need to move towards common code. Dmitry has been helpful in
contributing this to us.

BR,
Jani.


[1] https://patchwork.freedesktop.org/series/114473/

>
> Ankit Nautiyal (2):
>   drm/dp_helper: Add helper to check DSC support with given o/p format
>   drm/i915/dp: Check if DSC supports the given output_format
>
> Suraj Kandpal (4):
>   drm/i915: Adding the new registers for DSC
>   drm/i915: Enable YCbCr420 for VDSC
>   drm/i915/display: Fill in native_420 field
>   drm/i915/vdsc: Check slice design requirement
>
> Swati Sharma (1):
>   drm/i915/dsc: Add debugfs entry to validate DSC output formats
>
>  drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
>  .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
>  .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
>  .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
>  .../drm/i915/display/intel_display_types.h    |   1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
>  .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
>  .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
>  drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
>  drivers/gpu/drm/i915/i915_reg.h               |  28 +++
>  include/drm/display/drm_dp_helper.h           |  13 ++
>  11 files changed, 442 insertions(+), 24 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 0/7] Enable YCbCr420 format for VDSC

[Jani Nikula]

On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> This patch series aims to enable the YCbCr420 format
> for DSC. Changes are mostly compute params related for
> hdmi,dp and dsi along with the addition of new rc_tables
> for native_420 and corresponding changes to macros used to
> fetch them.
> There have been discussions prior to this series in which some patches
> have gotten rb and can be found in the below link
> https://patchwork.freedesktop.org/series/113729

I think it would be useful to get [1] from Dmitry merged to
drm-misc-next first, have that in drm-next, and again backmerged to
drm-intel-next before this. At least patches 1-5.

There's not much point in all drivers duplicating the parameters, and we
need to move towards common code. Dmitry has been helpful in
contributing this to us.

BR,
Jani.


[1] https://patchwork.freedesktop.org/series/114473/

>
> Ankit Nautiyal (2):
>   drm/dp_helper: Add helper to check DSC support with given o/p format
>   drm/i915/dp: Check if DSC supports the given output_format
>
> Suraj Kandpal (4):
>   drm/i915: Adding the new registers for DSC
>   drm/i915: Enable YCbCr420 for VDSC
>   drm/i915/display: Fill in native_420 field
>   drm/i915/vdsc: Check slice design requirement
>
> Swati Sharma (1):
>   drm/i915/dsc: Add debugfs entry to validate DSC output formats
>
>  drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
>  .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
>  .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
>  .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
>  .../drm/i915/display/intel_display_types.h    |   1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
>  .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
>  .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
>  drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
>  drivers/gpu/drm/i915/i915_reg.h               |  28 +++
>  include/drm/display/drm_dp_helper.h           |  13 ++
>  11 files changed, 442 insertions(+), 24 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

RE: [Intel-gfx] [PATCH 3/7] drm/i915: Adding the new registers for DSC

[Shankar, Uma]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Wednesday, March 8, 2023 4:57 PM
> To: Shankar, Uma <uma.shankar@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>; dri-devel@lists.freedesktop.org; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 3/7] drm/i915: Adding the new registers for DSC
> 
> On Wed, 08 Mar 2023, "Shankar, Uma" <uma.shankar@intel.com> wrote:
> >> -----Original Message-----
> >> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> >> Sent: Wednesday, February 22, 2023 11:02 AM
> >> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> >> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> >> <ankit.k.nautiyal@intel.com>; Kandpal, Suraj
> >> <suraj.kandpal@intel.com>; Kulkarni, Vandita
> >> <vandita.kulkarni@intel.com>
> >> Subject: [PATCH 3/7] drm/i915: Adding the new registers for DSC
> >
> > Nit: drm/i915/dsc would be better.
> >
> > Looks Good to me.
> > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> 
> Except since c3f059483671 ("drm/i915/display: split out DSC and DSS
> registers") the DSC registers need to go to display/intel_vdsc_regs.h.

Oh ok, thanks Jani for spotting it.

Regards,
Uma Shankar

> BR,
> Jani.
> 
> >
> >> Adding new DSC register which are introducted MTL onwards
> >>
> >> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> >> Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
> >>  1 file changed, 28 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> b/drivers/gpu/drm/i915/i915_reg.h index 596efc940ee7..9e25e21d37e4
> >> 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -7715,6 +7715,8 @@ enum skl_power_gate {
> >>  #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)
> 	_MMIO_PIPE((pipe) -
> >> PIPE_B, \
> >>
> >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> >>
> >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> >> +#define  DSC_NATIVE_422_ENABLE		BIT(23)
> >> +#define  DSC_NATIVE_420_ENABLE		BIT(22)
> >>  #define  DSC_ALT_ICH_SEL		(1 << 20)
> >>  #define  DSC_VBR_ENABLE			(1 << 19)
> >>  #define  DSC_422_ENABLE			(1 << 18)
> >> @@ -7959,6 +7961,32 @@ enum skl_power_gate {
> >>  #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
> >>  #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size)
> >> << 0)
> >>
> >> +/* MTL Display Stream Compression registers */
> >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB	0x782B4
> >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB	0x783B4
> >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC	0x784B4
> >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC	0x785B4
> >> +#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe)
> >> 	_MMIO_PIPE((pipe) - PIPE_B, \
> >> +
> >> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
> >> +
> >> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
> >> +#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)
> >> 	_MMIO_PIPE((pipe) - PIPE_B, \
> >> +
> >> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
> >> +
> >> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
> >> +#define DSC_SL_BPG_OFFSET(offset)		((offset) << 27)
> >> +
> >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB	0x782B8
> >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB	0x783B8
> >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC	0x784B8
> >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC	0x785B8
> >> +#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe)
> >> 	_MMIO_PIPE((pipe) - PIPE_B, \
> >> +
> >> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
> >> +
> >> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
> >> +#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)
> >> 	_MMIO_PIPE((pipe) - PIPE_B, \
> >> +
> >> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
> >> +
> >> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
> >> +#define DSC_NSL_BPG_OFFSET(offset)		((offset) << 16)
> >> +#define DSC_SL_OFFSET_ADJ(offset)		((offset) << 0)
> >> +
> >>  /* Icelake Rate Control Buffer Threshold Registers */
> >>  #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
> >>  #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
> >> --
> >> 2.25.1
> >
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 3/7] drm/i915: Adding the new registers for DSC

[Shankar, Uma]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Wednesday, March 8, 2023 4:57 PM
> To: Shankar, Uma <uma.shankar@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>; dri-devel@lists.freedesktop.org; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 3/7] drm/i915: Adding the new registers for DSC
> 
> On Wed, 08 Mar 2023, "Shankar, Uma" <uma.shankar@intel.com> wrote:
> >> -----Original Message-----
> >> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> >> Sent: Wednesday, February 22, 2023 11:02 AM
> >> To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> >> Cc: Shankar, Uma <uma.shankar@intel.com>; Nautiyal, Ankit K
> >> <ankit.k.nautiyal@intel.com>; Kandpal, Suraj
> >> <suraj.kandpal@intel.com>; Kulkarni, Vandita
> >> <vandita.kulkarni@intel.com>
> >> Subject: [PATCH 3/7] drm/i915: Adding the new registers for DSC
> >
> > Nit: drm/i915/dsc would be better.
> >
> > Looks Good to me.
> > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> 
> Except since c3f059483671 ("drm/i915/display: split out DSC and DSS
> registers") the DSC registers need to go to display/intel_vdsc_regs.h.

Oh ok, thanks Jani for spotting it.

Regards,
Uma Shankar

> BR,
> Jani.
> 
> >
> >> Adding new DSC register which are introducted MTL onwards
> >>
> >> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> >> Reviewed-by: Vandita Kulkarni <Vandita.kulkarni@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
> >>  1 file changed, 28 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> b/drivers/gpu/drm/i915/i915_reg.h index 596efc940ee7..9e25e21d37e4
> >> 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -7715,6 +7715,8 @@ enum skl_power_gate {
> >>  #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)
> 	_MMIO_PIPE((pipe) -
> >> PIPE_B, \
> >>
> >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> >>
> >> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> >> +#define  DSC_NATIVE_422_ENABLE		BIT(23)
> >> +#define  DSC_NATIVE_420_ENABLE		BIT(22)
> >>  #define  DSC_ALT_ICH_SEL		(1 << 20)
> >>  #define  DSC_VBR_ENABLE			(1 << 19)
> >>  #define  DSC_422_ENABLE			(1 << 18)
> >> @@ -7959,6 +7961,32 @@ enum skl_power_gate {
> >>  #define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
> >>  #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size)
> >> << 0)
> >>
> >> +/* MTL Display Stream Compression registers */
> >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB	0x782B4
> >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB	0x783B4
> >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC	0x784B4
> >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC	0x785B4
> >> +#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe)
> >> 	_MMIO_PIPE((pipe) - PIPE_B, \
> >> +
> >> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
> >> +
> >> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
> >> +#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)
> >> 	_MMIO_PIPE((pipe) - PIPE_B, \
> >> +
> >> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
> >> +
> >> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
> >> +#define DSC_SL_BPG_OFFSET(offset)		((offset) << 27)
> >> +
> >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB	0x782B8
> >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB	0x783B8
> >> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC	0x784B8
> >> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC	0x785B8
> >> +#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe)
> >> 	_MMIO_PIPE((pipe) - PIPE_B, \
> >> +
> >> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
> >> +
> >> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
> >> +#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)
> >> 	_MMIO_PIPE((pipe) - PIPE_B, \
> >> +
> >> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
> >> +
> >> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
> >> +#define DSC_NSL_BPG_OFFSET(offset)		((offset) << 16)
> >> +#define DSC_SL_OFFSET_ADJ(offset)		((offset) << 0)
> >> +
> >>  /* Icelake Rate Control Buffer Threshold Registers */
> >>  #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
> >>  #define DSCA_RC_BUF_THRESH_0_UDW		_MMIO(0x6B230 + 4)
> >> --
> >> 2.25.1
> >
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [PATCH 0/7] Enable YCbCr420 format for VDSC

[Dmitry Baryshkov]

On 08/03/2023 13:30, Jani Nikula wrote:
> On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>> This patch series aims to enable the YCbCr420 format
>> for DSC. Changes are mostly compute params related for
>> hdmi,dp and dsi along with the addition of new rc_tables
>> for native_420 and corresponding changes to macros used to
>> fetch them.
>> There have been discussions prior to this series in which some patches
>> have gotten rb and can be found in the below link
>> https://patchwork.freedesktop.org/series/113729
> 
> I think it would be useful to get [1] from Dmitry merged to
> drm-misc-next first, have that in drm-next, and again backmerged to
> drm-intel-next before this. At least patches 1-5.
> 
> There's not much point in all drivers duplicating the parameters, and we
> need to move towards common code. Dmitry has been helpful in
> contributing this to us.

Note, while I slightly reworked the calculate_rc_params() function, I 
did not touch the intel_qp_tables (mostly since we do not need them for 
drm/msm (at least for now). Our current plan is to use fixed params (at 
least in the short notice). We might have to reconsider it at some point.

However it might be wise to merge them with amdgpu's qp tables. amdgpu 
driver also contains code to calculate RC params. It might be worth 
moving RC calculation to the common helper.

> 
> BR,
> Jani.
> 
> 
> [1] https://patchwork.freedesktop.org/series/114473/
> 
>>
>> Ankit Nautiyal (2):
>>    drm/dp_helper: Add helper to check DSC support with given o/p format
>>    drm/i915/dp: Check if DSC supports the given output_format
>>
>> Suraj Kandpal (4):
>>    drm/i915: Adding the new registers for DSC
>>    drm/i915: Enable YCbCr420 for VDSC
>>    drm/i915/display: Fill in native_420 field
>>    drm/i915/vdsc: Check slice design requirement
>>
>> Swati Sharma (1):
>>    drm/i915/dsc: Add debugfs entry to validate DSC output formats
>>
>>   drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
>>   .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
>>   .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
>>   .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
>>   .../drm/i915/display/intel_display_types.h    |   1 +
>>   drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
>>   .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
>>   .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
>>   drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
>>   drivers/gpu/drm/i915/i915_reg.h               |  28 +++
>>   include/drm/display/drm_dp_helper.h           |  13 ++
>>   11 files changed, 442 insertions(+), 24 deletions(-)
> 

-- 
With best wishes
Dmitry

Re: [Intel-gfx] [PATCH 0/7] Enable YCbCr420 format for VDSC

[Dmitry Baryshkov]

On 08/03/2023 13:30, Jani Nikula wrote:
> On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>> This patch series aims to enable the YCbCr420 format
>> for DSC. Changes are mostly compute params related for
>> hdmi,dp and dsi along with the addition of new rc_tables
>> for native_420 and corresponding changes to macros used to
>> fetch them.
>> There have been discussions prior to this series in which some patches
>> have gotten rb and can be found in the below link
>> https://patchwork.freedesktop.org/series/113729
> 
> I think it would be useful to get [1] from Dmitry merged to
> drm-misc-next first, have that in drm-next, and again backmerged to
> drm-intel-next before this. At least patches 1-5.
> 
> There's not much point in all drivers duplicating the parameters, and we
> need to move towards common code. Dmitry has been helpful in
> contributing this to us.

Note, while I slightly reworked the calculate_rc_params() function, I 
did not touch the intel_qp_tables (mostly since we do not need them for 
drm/msm (at least for now). Our current plan is to use fixed params (at 
least in the short notice). We might have to reconsider it at some point.

However it might be wise to merge them with amdgpu's qp tables. amdgpu 
driver also contains code to calculate RC params. It might be worth 
moving RC calculation to the common helper.

> 
> BR,
> Jani.
> 
> 
> [1] https://patchwork.freedesktop.org/series/114473/
> 
>>
>> Ankit Nautiyal (2):
>>    drm/dp_helper: Add helper to check DSC support with given o/p format
>>    drm/i915/dp: Check if DSC supports the given output_format
>>
>> Suraj Kandpal (4):
>>    drm/i915: Adding the new registers for DSC
>>    drm/i915: Enable YCbCr420 for VDSC
>>    drm/i915/display: Fill in native_420 field
>>    drm/i915/vdsc: Check slice design requirement
>>
>> Swati Sharma (1):
>>    drm/i915/dsc: Add debugfs entry to validate DSC output formats
>>
>>   drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
>>   .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
>>   .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
>>   .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
>>   .../drm/i915/display/intel_display_types.h    |   1 +
>>   drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
>>   .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
>>   .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
>>   drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
>>   drivers/gpu/drm/i915/i915_reg.h               |  28 +++
>>   include/drm/display/drm_dp_helper.h           |  13 ++
>>   11 files changed, 442 insertions(+), 24 deletions(-)
> 

-- 
With best wishes
Dmitry

Re: [PATCH 0/7] Enable YCbCr420 format for VDSC

[Jani Nikula]

On Wed, 08 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> On 08/03/2023 13:30, Jani Nikula wrote:
>> On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>>> This patch series aims to enable the YCbCr420 format
>>> for DSC. Changes are mostly compute params related for
>>> hdmi,dp and dsi along with the addition of new rc_tables
>>> for native_420 and corresponding changes to macros used to
>>> fetch them.
>>> There have been discussions prior to this series in which some patches
>>> have gotten rb and can be found in the below link
>>> https://patchwork.freedesktop.org/series/113729
>> 
>> I think it would be useful to get [1] from Dmitry merged to
>> drm-misc-next first, have that in drm-next, and again backmerged to
>> drm-intel-next before this. At least patches 1-5.
>> 
>> There's not much point in all drivers duplicating the parameters, and we
>> need to move towards common code. Dmitry has been helpful in
>> contributing this to us.
>
> Note, while I slightly reworked the calculate_rc_params() function, I 
> did not touch the intel_qp_tables (mostly since we do not need them for 
> drm/msm (at least for now). Our current plan is to use fixed params (at 
> least in the short notice). We might have to reconsider it at some point.

Yeah, this isn't a big conflict, but AFAICT it'll conflict in
intel_vdsc.c.

> However it might be wise to merge them with amdgpu's qp tables. amdgpu 
> driver also contains code to calculate RC params. It might be worth 
> moving RC calculation to the common helper.

Agreed.

BR,
Jani.


>
>> 
>> BR,
>> Jani.
>> 
>> 
>> [1] https://patchwork.freedesktop.org/series/114473/
>> 
>>>
>>> Ankit Nautiyal (2):
>>>    drm/dp_helper: Add helper to check DSC support with given o/p format
>>>    drm/i915/dp: Check if DSC supports the given output_format
>>>
>>> Suraj Kandpal (4):
>>>    drm/i915: Adding the new registers for DSC
>>>    drm/i915: Enable YCbCr420 for VDSC
>>>    drm/i915/display: Fill in native_420 field
>>>    drm/i915/vdsc: Check slice design requirement
>>>
>>> Swati Sharma (1):
>>>    drm/i915/dsc: Add debugfs entry to validate DSC output formats
>>>
>>>   drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
>>>   .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
>>>   .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
>>>   .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
>>>   .../drm/i915/display/intel_display_types.h    |   1 +
>>>   drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
>>>   .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
>>>   .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
>>>   drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
>>>   drivers/gpu/drm/i915/i915_reg.h               |  28 +++
>>>   include/drm/display/drm_dp_helper.h           |  13 ++
>>>   11 files changed, 442 insertions(+), 24 deletions(-)
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 0/7] Enable YCbCr420 format for VDSC

[Jani Nikula]

On Wed, 08 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> On 08/03/2023 13:30, Jani Nikula wrote:
>> On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>>> This patch series aims to enable the YCbCr420 format
>>> for DSC. Changes are mostly compute params related for
>>> hdmi,dp and dsi along with the addition of new rc_tables
>>> for native_420 and corresponding changes to macros used to
>>> fetch them.
>>> There have been discussions prior to this series in which some patches
>>> have gotten rb and can be found in the below link
>>> https://patchwork.freedesktop.org/series/113729
>> 
>> I think it would be useful to get [1] from Dmitry merged to
>> drm-misc-next first, have that in drm-next, and again backmerged to
>> drm-intel-next before this. At least patches 1-5.
>> 
>> There's not much point in all drivers duplicating the parameters, and we
>> need to move towards common code. Dmitry has been helpful in
>> contributing this to us.
>
> Note, while I slightly reworked the calculate_rc_params() function, I 
> did not touch the intel_qp_tables (mostly since we do not need them for 
> drm/msm (at least for now). Our current plan is to use fixed params (at 
> least in the short notice). We might have to reconsider it at some point.

Yeah, this isn't a big conflict, but AFAICT it'll conflict in
intel_vdsc.c.

> However it might be wise to merge them with amdgpu's qp tables. amdgpu 
> driver also contains code to calculate RC params. It might be worth 
> moving RC calculation to the common helper.

Agreed.

BR,
Jani.


>
>> 
>> BR,
>> Jani.
>> 
>> 
>> [1] https://patchwork.freedesktop.org/series/114473/
>> 
>>>
>>> Ankit Nautiyal (2):
>>>    drm/dp_helper: Add helper to check DSC support with given o/p format
>>>    drm/i915/dp: Check if DSC supports the given output_format
>>>
>>> Suraj Kandpal (4):
>>>    drm/i915: Adding the new registers for DSC
>>>    drm/i915: Enable YCbCr420 for VDSC
>>>    drm/i915/display: Fill in native_420 field
>>>    drm/i915/vdsc: Check slice design requirement
>>>
>>> Swati Sharma (1):
>>>    drm/i915/dsc: Add debugfs entry to validate DSC output formats
>>>
>>>   drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
>>>   .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
>>>   .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
>>>   .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
>>>   .../drm/i915/display/intel_display_types.h    |   1 +
>>>   drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
>>>   .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
>>>   .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
>>>   drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
>>>   drivers/gpu/drm/i915/i915_reg.h               |  28 +++
>>>   include/drm/display/drm_dp_helper.h           |  13 ++
>>>   11 files changed, 442 insertions(+), 24 deletions(-)
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

RE: [PATCH 0/7] Enable YCbCr420 format for VDSC

[Kandpal, Suraj]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Wednesday, March 8, 2023 5:00 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
> devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> 
> On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > This patch series aims to enable the YCbCr420 format for DSC. Changes
> > are mostly compute params related for hdmi,dp and dsi along with the
> > addition of new rc_tables for native_420 and corresponding changes to
> > macros used to fetch them.
> > There have been discussions prior to this series in which some patches
> > have gotten rb and can be found in the below link
> > https://patchwork.freedesktop.org/series/113729
> 
> I think it would be useful to get [1] from Dmitry merged to drm-misc-next
> first, have that in drm-next, and again backmerged to drm-intel-next before
> this. At least patches 1-5.
> 
> There's not much point in all drivers duplicating the parameters, and we
> need to move towards common code. Dmitry has been helpful in
> contributing this to us.
> 
> BR,
> Jani.
> 
> 

Hi Jani,
Maarten has acked the patch series to be merged through drm-intel and in the meantime
I will work with Dmitry to pull the common code to avoid duplication

Regards,
Suraj Kandpal

> [1] https://patchwork.freedesktop.org/series/114473/
> 
> >
> > Ankit Nautiyal (2):
> >   drm/dp_helper: Add helper to check DSC support with given o/p format
> >   drm/i915/dp: Check if DSC supports the given output_format
> >
> > Suraj Kandpal (4):
> >   drm/i915: Adding the new registers for DSC
> >   drm/i915: Enable YCbCr420 for VDSC
> >   drm/i915/display: Fill in native_420 field
> >   drm/i915/vdsc: Check slice design requirement
> >
> > Swati Sharma (1):
> >   drm/i915/dsc: Add debugfs entry to validate DSC output formats
> >
> >  drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
> >  .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
> >  .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
> >  .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
> >  .../drm/i915/display/intel_display_types.h    |   1 +
> >  drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
> >  .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
> >  .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
> >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
> >  drivers/gpu/drm/i915/i915_reg.h               |  28 +++
> >  include/drm/display/drm_dp_helper.h           |  13 ++
> >  11 files changed, 442 insertions(+), 24 deletions(-)
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 0/7] Enable YCbCr420 format for VDSC

[Kandpal, Suraj]

> -----Original Message-----
> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Wednesday, March 8, 2023 5:00 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
> devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> 
> On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > This patch series aims to enable the YCbCr420 format for DSC. Changes
> > are mostly compute params related for hdmi,dp and dsi along with the
> > addition of new rc_tables for native_420 and corresponding changes to
> > macros used to fetch them.
> > There have been discussions prior to this series in which some patches
> > have gotten rb and can be found in the below link
> > https://patchwork.freedesktop.org/series/113729
> 
> I think it would be useful to get [1] from Dmitry merged to drm-misc-next
> first, have that in drm-next, and again backmerged to drm-intel-next before
> this. At least patches 1-5.
> 
> There's not much point in all drivers duplicating the parameters, and we
> need to move towards common code. Dmitry has been helpful in
> contributing this to us.
> 
> BR,
> Jani.
> 
> 

Hi Jani,
Maarten has acked the patch series to be merged through drm-intel and in the meantime
I will work with Dmitry to pull the common code to avoid duplication

Regards,
Suraj Kandpal

> [1] https://patchwork.freedesktop.org/series/114473/
> 
> >
> > Ankit Nautiyal (2):
> >   drm/dp_helper: Add helper to check DSC support with given o/p format
> >   drm/i915/dp: Check if DSC supports the given output_format
> >
> > Suraj Kandpal (4):
> >   drm/i915: Adding the new registers for DSC
> >   drm/i915: Enable YCbCr420 for VDSC
> >   drm/i915/display: Fill in native_420 field
> >   drm/i915/vdsc: Check slice design requirement
> >
> > Swati Sharma (1):
> >   drm/i915/dsc: Add debugfs entry to validate DSC output formats
> >
> >  drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
> >  .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
> >  .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
> >  .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
> >  .../drm/i915/display/intel_display_types.h    |   1 +
> >  drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
> >  .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
> >  .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
> >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
> >  drivers/gpu/drm/i915/i915_reg.h               |  28 +++
> >  include/drm/display/drm_dp_helper.h           |  13 ++
> >  11 files changed, 442 insertions(+), 24 deletions(-)
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [PATCH 0/7] Enable YCbCr420 format for VDSC

[Dmitry Baryshkov]

On Tue, 28 Mar 2023 at 16:20, Kandpal, Suraj <suraj.kandpal@intel.com> wrote:
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani
> > Nikula
> > Sent: Wednesday, March 8, 2023 5:00 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
> > devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal, Ankit K
> > <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> > Kandpal, Suraj <suraj.kandpal@intel.com>
> > Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> >
> > On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > > This patch series aims to enable the YCbCr420 format for DSC. Changes
> > > are mostly compute params related for hdmi,dp and dsi along with the
> > > addition of new rc_tables for native_420 and corresponding changes to
> > > macros used to fetch them.
> > > There have been discussions prior to this series in which some patches
> > > have gotten rb and can be found in the below link
> > > https://patchwork.freedesktop.org/series/113729
> >
> > I think it would be useful to get [1] from Dmitry merged to drm-misc-next
> > first, have that in drm-next, and again backmerged to drm-intel-next before
> > this. At least patches 1-5.
> >
> > There's not much point in all drivers duplicating the parameters, and we
> > need to move towards common code. Dmitry has been helpful in
> > contributing this to us.
> >
> > BR,
> > Jani.
> >
> >
>
> Hi Jani,
> Maarten has acked the patch series to be merged through drm-intel and in the meantime
> I will work with Dmitry to pull the common code to avoid duplication

Thank you! If necessary feel free to ping me on IRC ('lumag').

>
> Regards,
> Suraj Kandpal
>
> > [1] https://patchwork.freedesktop.org/series/114473/
> >
> > >
> > > Ankit Nautiyal (2):
> > >   drm/dp_helper: Add helper to check DSC support with given o/p format
> > >   drm/i915/dp: Check if DSC supports the given output_format
> > >
> > > Suraj Kandpal (4):
> > >   drm/i915: Adding the new registers for DSC
> > >   drm/i915: Enable YCbCr420 for VDSC
> > >   drm/i915/display: Fill in native_420 field
> > >   drm/i915/vdsc: Check slice design requirement
> > >
> > > Swati Sharma (1):
> > >   drm/i915/dsc: Add debugfs entry to validate DSC output formats
> > >
> > >  drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
> > >  .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
> > >  .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
> > >  .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
> > >  .../drm/i915/display/intel_display_types.h    |   1 +
> > >  drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
> > >  .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
> > >  .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
> > >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
> > >  drivers/gpu/drm/i915/i915_reg.h               |  28 +++
> > >  include/drm/display/drm_dp_helper.h           |  13 ++
> > >  11 files changed, 442 insertions(+), 24 deletions(-)
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center



-- 
With best wishes
Dmitry

Re: [Intel-gfx] [PATCH 0/7] Enable YCbCr420 format for VDSC

[Dmitry Baryshkov]

On Tue, 28 Mar 2023 at 16:20, Kandpal, Suraj <suraj.kandpal@intel.com> wrote:
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani
> > Nikula
> > Sent: Wednesday, March 8, 2023 5:00 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
> > devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal, Ankit K
> > <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> > Kandpal, Suraj <suraj.kandpal@intel.com>
> > Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> >
> > On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > > This patch series aims to enable the YCbCr420 format for DSC. Changes
> > > are mostly compute params related for hdmi,dp and dsi along with the
> > > addition of new rc_tables for native_420 and corresponding changes to
> > > macros used to fetch them.
> > > There have been discussions prior to this series in which some patches
> > > have gotten rb and can be found in the below link
> > > https://patchwork.freedesktop.org/series/113729
> >
> > I think it would be useful to get [1] from Dmitry merged to drm-misc-next
> > first, have that in drm-next, and again backmerged to drm-intel-next before
> > this. At least patches 1-5.
> >
> > There's not much point in all drivers duplicating the parameters, and we
> > need to move towards common code. Dmitry has been helpful in
> > contributing this to us.
> >
> > BR,
> > Jani.
> >
> >
>
> Hi Jani,
> Maarten has acked the patch series to be merged through drm-intel and in the meantime
> I will work with Dmitry to pull the common code to avoid duplication

Thank you! If necessary feel free to ping me on IRC ('lumag').

>
> Regards,
> Suraj Kandpal
>
> > [1] https://patchwork.freedesktop.org/series/114473/
> >
> > >
> > > Ankit Nautiyal (2):
> > >   drm/dp_helper: Add helper to check DSC support with given o/p format
> > >   drm/i915/dp: Check if DSC supports the given output_format
> > >
> > > Suraj Kandpal (4):
> > >   drm/i915: Adding the new registers for DSC
> > >   drm/i915: Enable YCbCr420 for VDSC
> > >   drm/i915/display: Fill in native_420 field
> > >   drm/i915/vdsc: Check slice design requirement
> > >
> > > Swati Sharma (1):
> > >   drm/i915/dsc: Add debugfs entry to validate DSC output formats
> > >
> > >  drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
> > >  .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
> > >  .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
> > >  .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
> > >  .../drm/i915/display/intel_display_types.h    |   1 +
> > >  drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
> > >  .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
> > >  .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
> > >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
> > >  drivers/gpu/drm/i915/i915_reg.h               |  28 +++
> > >  include/drm/display/drm_dp_helper.h           |  13 ++
> > >  11 files changed, 442 insertions(+), 24 deletions(-)
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center



-- 
With best wishes
Dmitry

RE: [PATCH 0/7] Enable YCbCr420 format for VDSC

[Shankar, Uma]

> -----Original Message-----
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Sent: Tuesday, March 28, 2023 6:58 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>; dri-devel@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org; Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Maarten Lankhorst
> <maarten.lankhorst@linux.intel.com>
> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> 
> On Tue, 28 Mar 2023 at 16:20, Kandpal, Suraj <suraj.kandpal@intel.com> wrote:
> > > -----Original Message-----
> > > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> > > Of Jani Nikula
> > > Sent: Wednesday, March 8, 2023 5:00 PM
> > > To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
> > > devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > > Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal, Ankit
> > > K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > > <uma.shankar@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> > > Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> > >
> > > On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > > > This patch series aims to enable the YCbCr420 format for DSC.
> > > > Changes are mostly compute params related for hdmi,dp and dsi
> > > > along with the addition of new rc_tables for native_420 and
> > > > corresponding changes to macros used to fetch them.
> > > > There have been discussions prior to this series in which some
> > > > patches have gotten rb and can be found in the below link
> > > > https://patchwork.freedesktop.org/series/113729
> > >
> > > I think it would be useful to get [1] from Dmitry merged to
> > > drm-misc-next first, have that in drm-next, and again backmerged to
> > > drm-intel-next before this. At least patches 1-5.
> > >
> > > There's not much point in all drivers duplicating the parameters,
> > > and we need to move towards common code. Dmitry has been helpful in
> > > contributing this to us.
> > >
> > > BR,
> > > Jani.
> > >
> > >
> >
> > Hi Jani,
> > Maarten has acked the patch series to be merged through drm-intel and
> > in the meantime I will work with Dmitry to pull the common code to
> > avoid duplication
> 
> Thank you! If necessary feel free to ping me on IRC ('lumag').

Thanks guys, will help merge the change.

Regards,
Uma Shankar

> >
> > Regards,
> > Suraj Kandpal
> >
> > > [1] https://patchwork.freedesktop.org/series/114473/
> > >
> > > >
> > > > Ankit Nautiyal (2):
> > > >   drm/dp_helper: Add helper to check DSC support with given o/p format
> > > >   drm/i915/dp: Check if DSC supports the given output_format
> > > >
> > > > Suraj Kandpal (4):
> > > >   drm/i915: Adding the new registers for DSC
> > > >   drm/i915: Enable YCbCr420 for VDSC
> > > >   drm/i915/display: Fill in native_420 field
> > > >   drm/i915/vdsc: Check slice design requirement
> > > >
> > > > Swati Sharma (1):
> > > >   drm/i915/dsc: Add debugfs entry to validate DSC output formats
> > > >
> > > >  drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
> > > >  .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
> > > >  .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
> > > >  .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
> > > >  .../drm/i915/display/intel_display_types.h    |   1 +
> > > >  drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
> > > >  .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
> > > >  .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
> > > >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
> > > >  drivers/gpu/drm/i915/i915_reg.h               |  28 +++
> > > >  include/drm/display/drm_dp_helper.h           |  13 ++
> > > >  11 files changed, 442 insertions(+), 24 deletions(-)
> > >
> > > --
> > > Jani Nikula, Intel Open Source Graphics Center
> 
> 
> 
> --
> With best wishes
> Dmitry

Re: [Intel-gfx] [PATCH 0/7] Enable YCbCr420 format for VDSC

[Shankar, Uma]

> -----Original Message-----
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Sent: Tuesday, March 28, 2023 6:58 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>; dri-devel@lists.freedesktop.org;
> intel-gfx@lists.freedesktop.org; Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Maarten Lankhorst
> <maarten.lankhorst@linux.intel.com>
> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> 
> On Tue, 28 Mar 2023 at 16:20, Kandpal, Suraj <suraj.kandpal@intel.com> wrote:
> > > -----Original Message-----
> > > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> > > Of Jani Nikula
> > > Sent: Wednesday, March 8, 2023 5:00 PM
> > > To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
> > > devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > > Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal, Ankit
> > > K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > > <uma.shankar@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> > > Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> > >
> > > On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > > > This patch series aims to enable the YCbCr420 format for DSC.
> > > > Changes are mostly compute params related for hdmi,dp and dsi
> > > > along with the addition of new rc_tables for native_420 and
> > > > corresponding changes to macros used to fetch them.
> > > > There have been discussions prior to this series in which some
> > > > patches have gotten rb and can be found in the below link
> > > > https://patchwork.freedesktop.org/series/113729
> > >
> > > I think it would be useful to get [1] from Dmitry merged to
> > > drm-misc-next first, have that in drm-next, and again backmerged to
> > > drm-intel-next before this. At least patches 1-5.
> > >
> > > There's not much point in all drivers duplicating the parameters,
> > > and we need to move towards common code. Dmitry has been helpful in
> > > contributing this to us.
> > >
> > > BR,
> > > Jani.
> > >
> > >
> >
> > Hi Jani,
> > Maarten has acked the patch series to be merged through drm-intel and
> > in the meantime I will work with Dmitry to pull the common code to
> > avoid duplication
> 
> Thank you! If necessary feel free to ping me on IRC ('lumag').

Thanks guys, will help merge the change.

Regards,
Uma Shankar

> >
> > Regards,
> > Suraj Kandpal
> >
> > > [1] https://patchwork.freedesktop.org/series/114473/
> > >
> > > >
> > > > Ankit Nautiyal (2):
> > > >   drm/dp_helper: Add helper to check DSC support with given o/p format
> > > >   drm/i915/dp: Check if DSC supports the given output_format
> > > >
> > > > Suraj Kandpal (4):
> > > >   drm/i915: Adding the new registers for DSC
> > > >   drm/i915: Enable YCbCr420 for VDSC
> > > >   drm/i915/display: Fill in native_420 field
> > > >   drm/i915/vdsc: Check slice design requirement
> > > >
> > > > Swati Sharma (1):
> > > >   drm/i915/dsc: Add debugfs entry to validate DSC output formats
> > > >
> > > >  drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
> > > >  .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
> > > >  .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
> > > >  .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
> > > >  .../drm/i915/display/intel_display_types.h    |   1 +
> > > >  drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
> > > >  .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
> > > >  .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
> > > >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
> > > >  drivers/gpu/drm/i915/i915_reg.h               |  28 +++
> > > >  include/drm/display/drm_dp_helper.h           |  13 ++
> > > >  11 files changed, 442 insertions(+), 24 deletions(-)
> > >
> > > --
> > > Jani Nikula, Intel Open Source Graphics Center
> 
> 
> 
> --
> With best wishes
> Dmitry

RE: [PATCH 0/7] Enable YCbCr420 format for VDSC

[Shankar, Uma]

> > -----Original Message-----
> > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Sent: Tuesday, March 28, 2023 6:58 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>;
> > dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > <uma.shankar@intel.com>; Maarten Lankhorst
> > <maarten.lankhorst@linux.intel.com>
> > Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> >
> > On Tue, 28 Mar 2023 at 16:20, Kandpal, Suraj <suraj.kandpal@intel.com> wrote:
> > > > -----Original Message-----
> > > > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On
> > > > Behalf Of Jani Nikula
> > > > Sent: Wednesday, March 8, 2023 5:00 PM
> > > > To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
> > > > devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > > > Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal,
> > > > Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > > > <uma.shankar@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> > > > Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> > > >
> > > > On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > > > > This patch series aims to enable the YCbCr420 format for DSC.
> > > > > Changes are mostly compute params related for hdmi,dp and dsi
> > > > > along with the addition of new rc_tables for native_420 and
> > > > > corresponding changes to macros used to fetch them.
> > > > > There have been discussions prior to this series in which some
> > > > > patches have gotten rb and can be found in the below link
> > > > > https://patchwork.freedesktop.org/series/113729
> > > >
> > > > I think it would be useful to get [1] from Dmitry merged to
> > > > drm-misc-next first, have that in drm-next, and again backmerged
> > > > to drm-intel-next before this. At least patches 1-5.
> > > >
> > > > There's not much point in all drivers duplicating the parameters,
> > > > and we need to move towards common code. Dmitry has been helpful
> > > > in contributing this to us.
> > > >
> > > > BR,
> > > > Jani.
> > > >
> > > >
> > >
> > > Hi Jani,
> > > Maarten has acked the patch series to be merged through drm-intel
> > > and in the meantime I will work with Dmitry to pull the common code
> > > to avoid duplication
> >
> > Thank you! If necessary feel free to ping me on IRC ('lumag').
> 
> Thanks guys, will help merge the change.

Pushed the changes to drm-intel-next. Thanks for the patches and reviews.

Regards,
Uma Shankar
> 
> > >
> > > Regards,
> > > Suraj Kandpal
> > >
> > > > [1] https://patchwork.freedesktop.org/series/114473/
> > > >
> > > > >
> > > > > Ankit Nautiyal (2):
> > > > >   drm/dp_helper: Add helper to check DSC support with given o/p format
> > > > >   drm/i915/dp: Check if DSC supports the given output_format
> > > > >
> > > > > Suraj Kandpal (4):
> > > > >   drm/i915: Adding the new registers for DSC
> > > > >   drm/i915: Enable YCbCr420 for VDSC
> > > > >   drm/i915/display: Fill in native_420 field
> > > > >   drm/i915/vdsc: Check slice design requirement
> > > > >
> > > > > Swati Sharma (1):
> > > > >   drm/i915/dsc: Add debugfs entry to validate DSC output formats
> > > > >
> > > > >  drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
> > > > >  .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
> > > > >  .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
> > > > >  .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
> > > > >  .../drm/i915/display/intel_display_types.h    |   1 +
> > > > >  drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
> > > > >  .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
> > > > >  .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
> > > > >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
> > > > >  drivers/gpu/drm/i915/i915_reg.h               |  28 +++
> > > > >  include/drm/display/drm_dp_helper.h           |  13 ++
> > > > >  11 files changed, 442 insertions(+), 24 deletions(-)
> > > >
> > > > --
> > > > Jani Nikula, Intel Open Source Graphics Center
> >
> >
> >
> > --
> > With best wishes
> > Dmitry

Re: [Intel-gfx] [PATCH 0/7] Enable YCbCr420 format for VDSC

[Shankar, Uma]

> > -----Original Message-----
> > From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Sent: Tuesday, March 28, 2023 6:58 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>;
> > dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
> > Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > <uma.shankar@intel.com>; Maarten Lankhorst
> > <maarten.lankhorst@linux.intel.com>
> > Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> >
> > On Tue, 28 Mar 2023 at 16:20, Kandpal, Suraj <suraj.kandpal@intel.com> wrote:
> > > > -----Original Message-----
> > > > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On
> > > > Behalf Of Jani Nikula
> > > > Sent: Wednesday, March 8, 2023 5:00 PM
> > > > To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
> > > > devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > > > Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal,
> > > > Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> > > > <uma.shankar@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> > > > Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> > > >
> > > > On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > > > > This patch series aims to enable the YCbCr420 format for DSC.
> > > > > Changes are mostly compute params related for hdmi,dp and dsi
> > > > > along with the addition of new rc_tables for native_420 and
> > > > > corresponding changes to macros used to fetch them.
> > > > > There have been discussions prior to this series in which some
> > > > > patches have gotten rb and can be found in the below link
> > > > > https://patchwork.freedesktop.org/series/113729
> > > >
> > > > I think it would be useful to get [1] from Dmitry merged to
> > > > drm-misc-next first, have that in drm-next, and again backmerged
> > > > to drm-intel-next before this. At least patches 1-5.
> > > >
> > > > There's not much point in all drivers duplicating the parameters,
> > > > and we need to move towards common code. Dmitry has been helpful
> > > > in contributing this to us.
> > > >
> > > > BR,
> > > > Jani.
> > > >
> > > >
> > >
> > > Hi Jani,
> > > Maarten has acked the patch series to be merged through drm-intel
> > > and in the meantime I will work with Dmitry to pull the common code
> > > to avoid duplication
> >
> > Thank you! If necessary feel free to ping me on IRC ('lumag').
> 
> Thanks guys, will help merge the change.

Pushed the changes to drm-intel-next. Thanks for the patches and reviews.

Regards,
Uma Shankar
> 
> > >
> > > Regards,
> > > Suraj Kandpal
> > >
> > > > [1] https://patchwork.freedesktop.org/series/114473/
> > > >
> > > > >
> > > > > Ankit Nautiyal (2):
> > > > >   drm/dp_helper: Add helper to check DSC support with given o/p format
> > > > >   drm/i915/dp: Check if DSC supports the given output_format
> > > > >
> > > > > Suraj Kandpal (4):
> > > > >   drm/i915: Adding the new registers for DSC
> > > > >   drm/i915: Enable YCbCr420 for VDSC
> > > > >   drm/i915/display: Fill in native_420 field
> > > > >   drm/i915/vdsc: Check slice design requirement
> > > > >
> > > > > Swati Sharma (1):
> > > > >   drm/i915/dsc: Add debugfs entry to validate DSC output formats
> > > > >
> > > > >  drivers/gpu/drm/i915/display/icl_dsi.c        |   2 -
> > > > >  .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
> > > > >  .../drm/i915/display/intel_crtc_state_dump.h  |   2 +
> > > > >  .../drm/i915/display/intel_display_debugfs.c  |  78 ++++++++
> > > > >  .../drm/i915/display/intel_display_types.h    |   1 +
> > > > >  drivers/gpu/drm/i915/display/intel_dp.c       |  39 +++-
> > > > >  .../gpu/drm/i915/display/intel_qp_tables.c    | 187 ++++++++++++++++--
> > > > >  .../gpu/drm/i915/display/intel_qp_tables.h    |   4 +-
> > > > >  drivers/gpu/drm/i915/display/intel_vdsc.c     | 108 +++++++++-
> > > > >  drivers/gpu/drm/i915/i915_reg.h               |  28 +++
> > > > >  include/drm/display/drm_dp_helper.h           |  13 ++
> > > > >  11 files changed, 442 insertions(+), 24 deletions(-)
> > > >
> > > > --
> > > > Jani Nikula, Intel Open Source Graphics Center
> >
> >
> >
> > --
> > With best wishes
> > Dmitry

Re: [PATCH 0/7] Enable YCbCr420 format for VDSC

[Dmitry Baryshkov]

Hi Suraj

On 28/03/2023 16:20, Kandpal, Suraj wrote:
> 
> 
>> -----Original Message-----
>> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Wednesday, March 8, 2023 5:00 PM
>> To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
>> devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal, Ankit K
>> <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
>> Kandpal, Suraj <suraj.kandpal@intel.com>
>> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
>>
>> On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>>> This patch series aims to enable the YCbCr420 format for DSC. Changes
>>> are mostly compute params related for hdmi,dp and dsi along with the
>>> addition of new rc_tables for native_420 and corresponding changes to
>>> macros used to fetch them.
>>> There have been discussions prior to this series in which some patches
>>> have gotten rb and can be found in the below link
>>> https://patchwork.freedesktop.org/series/113729
>>
>> I think it would be useful to get [1] from Dmitry merged to drm-misc-next
>> first, have that in drm-next, and again backmerged to drm-intel-next before
>> this. At least patches 1-5.
>>
>> There's not much point in all drivers duplicating the parameters, and we
>> need to move towards common code. Dmitry has been helpful in
>> contributing this to us.
>>
>> BR,
>> Jani.
>>
>>
> 
> Hi Jani,
> Maarten has acked the patch series to be merged through drm-intel and in the meantime
> I will work with Dmitry to pull the common code to avoid duplication

I wanted to check, are there any updates from your side regarding the 
series at [1] ?

> 
> Regards,
> Suraj Kandpal
> 
>> [1] https://patchwork.freedesktop.org/series/114473/



-- 
With best wishes
Dmitry

Re: [Intel-gfx] [PATCH 0/7] Enable YCbCr420 format for VDSC

[Dmitry Baryshkov]

Hi Suraj

On 28/03/2023 16:20, Kandpal, Suraj wrote:
> 
> 
>> -----Original Message-----
>> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Wednesday, March 8, 2023 5:00 PM
>> To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
>> devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal, Ankit K
>> <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
>> Kandpal, Suraj <suraj.kandpal@intel.com>
>> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
>>
>> On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>>> This patch series aims to enable the YCbCr420 format for DSC. Changes
>>> are mostly compute params related for hdmi,dp and dsi along with the
>>> addition of new rc_tables for native_420 and corresponding changes to
>>> macros used to fetch them.
>>> There have been discussions prior to this series in which some patches
>>> have gotten rb and can be found in the below link
>>> https://patchwork.freedesktop.org/series/113729
>>
>> I think it would be useful to get [1] from Dmitry merged to drm-misc-next
>> first, have that in drm-next, and again backmerged to drm-intel-next before
>> this. At least patches 1-5.
>>
>> There's not much point in all drivers duplicating the parameters, and we
>> need to move towards common code. Dmitry has been helpful in
>> contributing this to us.
>>
>> BR,
>> Jani.
>>
>>
> 
> Hi Jani,
> Maarten has acked the patch series to be merged through drm-intel and in the meantime
> I will work with Dmitry to pull the common code to avoid duplication

I wanted to check, are there any updates from your side regarding the 
series at [1] ?

> 
> Regards,
> Suraj Kandpal
> 
>> [1] https://patchwork.freedesktop.org/series/114473/



-- 
With best wishes
Dmitry

RE: [PATCH 0/7] Enable YCbCr420 format for VDSC

[Kandpal, Suraj]

Hi Dmitry


> -----Original Message-----
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Sent: Friday, April 7, 2023 8:28 AM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; Jani Nikula
> <jani.nikula@linux.intel.com>; dri-devel@lists.freedesktop.org; intel-
> gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Maarten Lankhorst
> <maarten.lankhorst@linux.intel.com>
> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> 
> Hi Suraj
> 
> On 28/03/2023 16:20, Kandpal, Suraj wrote:
> >
> >
> >> -----Original Message-----
> >> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> >> Of Jani Nikula
> >> Sent: Wednesday, March 8, 2023 5:00 PM
> >> To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
> >> devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> >> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal, Ankit K
> >> <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> >> Kandpal, Suraj <suraj.kandpal@intel.com>
> >> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> >>
> >> On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> >>> This patch series aims to enable the YCbCr420 format for DSC.
> >>> Changes are mostly compute params related for hdmi,dp and dsi along
> >>> with the addition of new rc_tables for native_420 and corresponding
> >>> changes to macros used to fetch them.
> >>> There have been discussions prior to this series in which some
> >>> patches have gotten rb and can be found in the below link
> >>> https://patchwork.freedesktop.org/series/113729
> >>
> >> I think it would be useful to get [1] from Dmitry merged to
> >> drm-misc-next first, have that in drm-next, and again backmerged to
> >> drm-intel-next before this. At least patches 1-5.
> >>
> >> There's not much point in all drivers duplicating the parameters, and
> >> we need to move towards common code. Dmitry has been helpful in
> >> contributing this to us.
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >
> > Hi Jani,
> > Maarten has acked the patch series to be merged through drm-intel and
> > in the meantime I will work with Dmitry to pull the common code to
> > avoid duplication
> 
> I wanted to check, are there any updates from your side regarding the series
> at [1] ?
> 

Will have a look and float comments if any by  Monday

> >
> > Regards,
> > Suraj Kandpal
> >
> >> [1] https://patchwork.freedesktop.org/series/114473/
> 
> 
> 
> --
> With best wishes
> Dmitry

Regards,
Suraj Kandpal

Re: [Intel-gfx] [PATCH 0/7] Enable YCbCr420 format for VDSC

[Kandpal, Suraj]

Hi Dmitry


> -----Original Message-----
> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Sent: Friday, April 7, 2023 8:28 AM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; Jani Nikula
> <jani.nikula@linux.intel.com>; dri-devel@lists.freedesktop.org; intel-
> gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>; Maarten Lankhorst
> <maarten.lankhorst@linux.intel.com>
> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> 
> Hi Suraj
> 
> On 28/03/2023 16:20, Kandpal, Suraj wrote:
> >
> >
> >> -----Original Message-----
> >> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
> >> Of Jani Nikula
> >> Sent: Wednesday, March 8, 2023 5:00 PM
> >> To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
> >> devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> >> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal, Ankit K
> >> <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> >> Kandpal, Suraj <suraj.kandpal@intel.com>
> >> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
> >>
> >> On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> >>> This patch series aims to enable the YCbCr420 format for DSC.
> >>> Changes are mostly compute params related for hdmi,dp and dsi along
> >>> with the addition of new rc_tables for native_420 and corresponding
> >>> changes to macros used to fetch them.
> >>> There have been discussions prior to this series in which some
> >>> patches have gotten rb and can be found in the below link
> >>> https://patchwork.freedesktop.org/series/113729
> >>
> >> I think it would be useful to get [1] from Dmitry merged to
> >> drm-misc-next first, have that in drm-next, and again backmerged to
> >> drm-intel-next before this. At least patches 1-5.
> >>
> >> There's not much point in all drivers duplicating the parameters, and
> >> we need to move towards common code. Dmitry has been helpful in
> >> contributing this to us.
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >
> > Hi Jani,
> > Maarten has acked the patch series to be merged through drm-intel and
> > in the meantime I will work with Dmitry to pull the common code to
> > avoid duplication
> 
> I wanted to check, are there any updates from your side regarding the series
> at [1] ?
> 

Will have a look and float comments if any by  Monday

> >
> > Regards,
> > Suraj Kandpal
> >
> >> [1] https://patchwork.freedesktop.org/series/114473/
> 
> 
> 
> --
> With best wishes
> Dmitry

Regards,
Suraj Kandpal

Re: [PATCH 0/7] Enable YCbCr420 format for VDSC

[Dmitry Baryshkov]

Hi Suraj,

On 07/04/2023 06:11, Kandpal, Suraj wrote:
> Hi Dmitry
> 
> 
>> -----Original Message-----
>> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> Sent: Friday, April 7, 2023 8:28 AM
>> To: Kandpal, Suraj <suraj.kandpal@intel.com>; Jani Nikula
>> <jani.nikula@linux.intel.com>; dri-devel@lists.freedesktop.org; intel-
>> gfx@lists.freedesktop.org
>> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>; Maarten Lankhorst
>> <maarten.lankhorst@linux.intel.com>
>> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
>>
>> Hi Suraj
>>
>> On 28/03/2023 16:20, Kandpal, Suraj wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
>>>> Of Jani Nikula
>>>> Sent: Wednesday, March 8, 2023 5:00 PM
>>>> To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
>>>> devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>>>> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal, Ankit K
>>>> <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
>>>> Kandpal, Suraj <suraj.kandpal@intel.com>
>>>> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
>>>>
>>>> On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>>>>> This patch series aims to enable the YCbCr420 format for DSC.
>>>>> Changes are mostly compute params related for hdmi,dp and dsi along
>>>>> with the addition of new rc_tables for native_420 and corresponding
>>>>> changes to macros used to fetch them.
>>>>> There have been discussions prior to this series in which some
>>>>> patches have gotten rb and can be found in the below link
>>>>> https://patchwork.freedesktop.org/series/113729
>>>>
>>>> I think it would be useful to get [1] from Dmitry merged to
>>>> drm-misc-next first, have that in drm-next, and again backmerged to
>>>> drm-intel-next before this. At least patches 1-5.
>>>>
>>>> There's not much point in all drivers duplicating the parameters, and
>>>> we need to move towards common code. Dmitry has been helpful in
>>>> contributing this to us.
>>>>
>>>> BR,
>>>> Jani.
>>>>
>>>>
>>>
>>> Hi Jani,
>>> Maarten has acked the patch series to be merged through drm-intel and
>>> in the meantime I will work with Dmitry to pull the common code to
>>> avoid duplication
>>
>> I wanted to check, are there any updates from your side regarding the series
>> at [1] ?
>>
> 
> Will have a look and float comments if any by  Monday

Please excuse me for being slightly stubborn here. We are slowly getting 
other patches piled up with dependency on this series. It is fine that 
it doesn't get into 6.4 (which it probably definitely missed by now), 
but we would like to know if we have to redo/update anything or if it is 
fine as is and it is going to be merged by i915 in 6.5 cycle.

Thank you for the understanding.

> 
>>>
>>> Regards,
>>> Suraj Kandpal
>>>
>>>> [1] https://patchwork.freedesktop.org/series/114473/
>>
>>
>>
>> --
>> With best wishes
>> Dmitry
> 
> Regards,
> Suraj Kandpal

-- 
With best wishes
Dmitry

Re: [Intel-gfx] [PATCH 0/7] Enable YCbCr420 format for VDSC

[Dmitry Baryshkov]

Hi Suraj,

On 07/04/2023 06:11, Kandpal, Suraj wrote:
> Hi Dmitry
> 
> 
>> -----Original Message-----
>> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> Sent: Friday, April 7, 2023 8:28 AM
>> To: Kandpal, Suraj <suraj.kandpal@intel.com>; Jani Nikula
>> <jani.nikula@linux.intel.com>; dri-devel@lists.freedesktop.org; intel-
>> gfx@lists.freedesktop.org
>> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>; Maarten Lankhorst
>> <maarten.lankhorst@linux.intel.com>
>> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
>>
>> Hi Suraj
>>
>> On 28/03/2023 16:20, Kandpal, Suraj wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
>>>> Of Jani Nikula
>>>> Sent: Wednesday, March 8, 2023 5:00 PM
>>>> To: Kandpal, Suraj <suraj.kandpal@intel.com>; dri-
>>>> devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>>>> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>; Nautiyal, Ankit K
>>>> <ankit.k.nautiyal@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
>>>> Kandpal, Suraj <suraj.kandpal@intel.com>
>>>> Subject: Re: [PATCH 0/7] Enable YCbCr420 format for VDSC
>>>>
>>>> On Wed, 22 Feb 2023, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>>>>> This patch series aims to enable the YCbCr420 format for DSC.
>>>>> Changes are mostly compute params related for hdmi,dp and dsi along
>>>>> with the addition of new rc_tables for native_420 and corresponding
>>>>> changes to macros used to fetch them.
>>>>> There have been discussions prior to this series in which some
>>>>> patches have gotten rb and can be found in the below link
>>>>> https://patchwork.freedesktop.org/series/113729
>>>>
>>>> I think it would be useful to get [1] from Dmitry merged to
>>>> drm-misc-next first, have that in drm-next, and again backmerged to
>>>> drm-intel-next before this. At least patches 1-5.
>>>>
>>>> There's not much point in all drivers duplicating the parameters, and
>>>> we need to move towards common code. Dmitry has been helpful in
>>>> contributing this to us.
>>>>
>>>> BR,
>>>> Jani.
>>>>
>>>>
>>>
>>> Hi Jani,
>>> Maarten has acked the patch series to be merged through drm-intel and
>>> in the meantime I will work with Dmitry to pull the common code to
>>> avoid duplication
>>
>> I wanted to check, are there any updates from your side regarding the series
>> at [1] ?
>>
> 
> Will have a look and float comments if any by  Monday

Please excuse me for being slightly stubborn here. We are slowly getting 
other patches piled up with dependency on this series. It is fine that 
it doesn't get into 6.4 (which it probably definitely missed by now), 
but we would like to know if we have to redo/update anything or if it is 
fine as is and it is going to be merged by i915 in 6.5 cycle.

Thank you for the understanding.

> 
>>>
>>> Regards,
>>> Suraj Kandpal
>>>
>>>> [1] https://patchwork.freedesktop.org/series/114473/
>>
>>
>>
>> --
>> With best wishes
>> Dmitry
> 
> Regards,
> Suraj Kandpal

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With best wishes
Dmitry