From: Andrew Jones <ajones@ventanamicro.com> To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Conor Dooley ' <conor.dooley@microchip.com>, 'Paul Walmsley ' <paul.walmsley@sifive.com>, 'Palmer Dabbelt ' <palmer@dabbelt.com>, 'Sudip Mukherjee ' <sudip.mukherjee@codethink.co.uk>, 'Ben Dooks ' <ben.dooks@codethink.co.uk>, 'Atish Patra ' <atishp@rivosinc.com>, 'Albert Ou ' <aou@eecs.berkeley.edu>, 'Anup Patel ' <apatel@ventanamicro.com>, 'Krzysztof Kozlowski ' <krzysztof.kozlowski+dt@linaro.org>, 'Rob Herring ' <robh@kernel.org>, 'Jisheng Zhang ' <jszhang@kernel.org>, 'Heiko Stuebner ' <heiko@sntech.de>, Anup Patel <anup@brainfault.org> Subject: [PATCH v6 8/8] RISC-V: KVM: Expose Zicboz to the guest Date: Fri, 24 Feb 2023 17:26:31 +0100 [thread overview] Message-ID: <20230224162631.405473-9-ajones@ventanamicro.com> (raw) In-Reply-To: <20230224162631.405473-1-ajones@ventanamicro.com> Guests may use the cbo.zero instruction when the CPU has the Zicboz extension and the hypervisor sets henvcfg.CBZE. Add Zicboz support for KVM guests which may be enabled and disabled from KVM userspace using the ISA extension ONE_REG API. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index c1a1bb0fa91c..e44c1e90eaa7 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -106,6 +106,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_SVINVAL, KVM_RISCV_ISA_EXT_ZIHINTPAUSE, KVM_RISCV_ISA_EXT_ZICBOM, + KVM_RISCV_ISA_EXT_ZICBOZ, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index e5126cefbc87..198ee86cad38 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -63,6 +63,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(SVPBMT), KVM_ISA_EXT_ARR(ZIHINTPAUSE), KVM_ISA_EXT_ARR(ZICBOM), + KVM_ISA_EXT_ARR(ZICBOZ), }; static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext) @@ -865,6 +866,9 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa) if (riscv_isa_extension_available(isa, ZICBOM)) henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE); + if (riscv_isa_extension_available(isa, ZICBOZ)) + henvcfg |= ENVCFG_CBZE; + csr_write(CSR_HENVCFG, henvcfg); #ifdef CONFIG_32BIT csr_write(CSR_HENVCFGH, henvcfg >> 32); -- 2.39.1
WARNING: multiple messages have this Message-ID (diff)
From: Andrew Jones <ajones@ventanamicro.com> To: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, devicetree@vger.kernel.org Cc: 'Conor Dooley ' <conor.dooley@microchip.com>, 'Paul Walmsley ' <paul.walmsley@sifive.com>, 'Palmer Dabbelt ' <palmer@dabbelt.com>, 'Sudip Mukherjee ' <sudip.mukherjee@codethink.co.uk>, 'Ben Dooks ' <ben.dooks@codethink.co.uk>, 'Atish Patra ' <atishp@rivosinc.com>, 'Albert Ou ' <aou@eecs.berkeley.edu>, 'Anup Patel ' <apatel@ventanamicro.com>, 'Krzysztof Kozlowski ' <krzysztof.kozlowski+dt@linaro.org>, 'Rob Herring ' <robh@kernel.org>, 'Jisheng Zhang ' <jszhang@kernel.org>, 'Heiko Stuebner ' <heiko@sntech.de>, Anup Patel <anup@brainfault.org> Subject: [PATCH v6 8/8] RISC-V: KVM: Expose Zicboz to the guest Date: Fri, 24 Feb 2023 17:26:31 +0100 [thread overview] Message-ID: <20230224162631.405473-9-ajones@ventanamicro.com> (raw) In-Reply-To: <20230224162631.405473-1-ajones@ventanamicro.com> Guests may use the cbo.zero instruction when the CPU has the Zicboz extension and the hypervisor sets henvcfg.CBZE. Add Zicboz support for KVM guests which may be enabled and disabled from KVM userspace using the ISA extension ONE_REG API. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index c1a1bb0fa91c..e44c1e90eaa7 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -106,6 +106,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_SVINVAL, KVM_RISCV_ISA_EXT_ZIHINTPAUSE, KVM_RISCV_ISA_EXT_ZICBOM, + KVM_RISCV_ISA_EXT_ZICBOZ, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index e5126cefbc87..198ee86cad38 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -63,6 +63,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(SVPBMT), KVM_ISA_EXT_ARR(ZIHINTPAUSE), KVM_ISA_EXT_ARR(ZICBOM), + KVM_ISA_EXT_ARR(ZICBOZ), }; static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext) @@ -865,6 +866,9 @@ static void kvm_riscv_vcpu_update_config(const unsigned long *isa) if (riscv_isa_extension_available(isa, ZICBOM)) henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE); + if (riscv_isa_extension_available(isa, ZICBOZ)) + henvcfg |= ENVCFG_CBZE; + csr_write(CSR_HENVCFG, henvcfg); #ifdef CONFIG_32BIT csr_write(CSR_HENVCFGH, henvcfg >> 32); -- 2.39.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-02-24 16:27 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-02-24 16:26 [PATCH v6 0/8] RISC-V: Apply Zicboz to clear_page Andrew Jones 2023-02-24 16:26 ` Andrew Jones 2023-02-24 16:26 ` [PATCH v6 1/8] RISC-V: alternatives: Support patching multiple insns in assembly Andrew Jones 2023-02-24 16:26 ` Andrew Jones 2023-02-24 16:26 ` [PATCH v6 2/8] RISC-V: Factor out body of riscv_init_cbom_blocksize loop Andrew Jones 2023-02-24 16:26 ` Andrew Jones 2023-02-24 16:26 ` [PATCH v6 3/8] dt-bindings: riscv: Document cboz-block-size Andrew Jones 2023-02-24 16:26 ` Andrew Jones 2023-02-24 16:26 ` [PATCH v6 4/8] RISC-V: Add Zicboz detection and block size parsing Andrew Jones 2023-02-24 16:26 ` Andrew Jones 2023-02-24 16:26 ` [PATCH v6 5/8] RISC-V: cpufeatures: Put the upper 16 bits of patch ID to work Andrew Jones 2023-02-24 16:26 ` Andrew Jones 2023-02-24 16:26 ` [PATCH v6 6/8] RISC-V: Use Zicboz in clear_page when available Andrew Jones 2023-02-24 16:26 ` Andrew Jones 2023-02-24 16:26 ` [PATCH v6 7/8] RISC-V: KVM: Provide UAPI for Zicboz block size Andrew Jones 2023-02-24 16:26 ` Andrew Jones 2023-02-24 16:26 ` Andrew Jones [this message] 2023-02-24 16:26 ` [PATCH v6 8/8] RISC-V: KVM: Expose Zicboz to the guest Andrew Jones 2023-03-15 4:38 ` Palmer Dabbelt 2023-03-15 4:38 ` Palmer Dabbelt 2023-03-15 4:54 ` Anup Patel 2023-03-15 4:54 ` Anup Patel 2023-03-15 4:35 ` [PATCH v6 0/8] RISC-V: Apply Zicboz to clear_page Palmer Dabbelt 2023-03-15 4:35 ` Palmer Dabbelt 2023-03-15 8:53 ` Andrew Jones 2023-03-15 8:53 ` Andrew Jones 2023-03-18 1:00 ` patchwork-bot+linux-riscv 2023-03-18 1:00 ` patchwork-bot+linux-riscv
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20230224162631.405473-9-ajones@ventanamicro.com \ --to=ajones@ventanamicro.com \ --cc=anup@brainfault.org \ --cc=aou@eecs.berkeley.edu \ --cc=apatel@ventanamicro.com \ --cc=atishp@rivosinc.com \ --cc=ben.dooks@codethink.co.uk \ --cc=conor.dooley@microchip.com \ --cc=devicetree@vger.kernel.org \ --cc=heiko@sntech.de \ --cc=jszhang@kernel.org \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=kvm-riscv@lists.infradead.org \ --cc=linux-riscv@lists.infradead.org \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=robh@kernel.org \ --cc=sudip.mukherjee@codethink.co.uk \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.