* [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access
@ 2023-02-28 10:40 Bin Meng
2023-02-28 10:40 ` [PATCH v2 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR Bin Meng
` (17 more replies)
0 siblings, 18 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 10:40 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair Francis, Bin Meng, Daniel Henrique Barboza, Liu Zhiwei,
Palmer Dabbelt, Weiwei Li, qemu-riscv
At present gdbstub reports an incorrect / incomplete CSR list in the
target description XML, for example:
- menvcfg is reported in 'sifive_u' machine
- fcsr is missing in a F/D enabled processor
The issue is caused by:
- priv spec version check is missing when reporting CSRs
- CSR predicate() routine is called without turning on the debugger flag
This series aims to generate a correct and complete CSR list for gdbstub.
This series is rebased against Daniel's FEATURE_* clean-up series v7.
Based-on: 20230222185205.355361-1-dbarboza@ventanamicro.com
Changes in v2:
- keep the original priority policy, instead add some comments for clarification
- new patch: Use assert() for the predicate() NULL check
- keep the 'RV128 restriction check' todo comment
- move smstateen_acc_ok() to near {read,write}_xenvcfg()
- drop patch "target/riscv: Move configuration check to envcfg CSRs predicate()"
Bin Meng (18):
target/riscv: gdbstub: Check priv spec version before reporting CSR
target/riscv: Add some comments to clarify the priority policy of
riscv_csrrw_check()
target/riscv: Use g_assert() for the predicate() NULL check
target/riscv: gdbstub: Minor change for better readability
target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
target/riscv: Coding style fixes in csr.c
target/riscv: Use 'bool' type for read_only
target/riscv: Simplify {read,write}_pmpcfg() a little bit
target/riscv: Simplify getting RISCVCPU pointer from env
target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for
RV64
target/riscv: gdbstub: Turn on debugger mode before calling CSR
predicate()
target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml
target/riscv: Allow debugger to access user timer and counter CSRs
target/riscv: Allow debugger to access seed CSR
target/riscv: Allow debugger to access {h,s}stateen CSRs
target/riscv: Allow debugger to access sstc CSRs
target/riscv: Drop priv level check in mseccfg predicate()
target/riscv: Group all predicate() routines together
target/riscv/csr.c | 341 ++++++++++++++++++++++-------------------
target/riscv/gdbstub.c | 100 +++---------
2 files changed, 201 insertions(+), 240 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
@ 2023-02-28 10:40 ` Bin Meng
2023-02-28 10:40 ` [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() Bin Meng
` (16 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 10:40 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, LIU Zhiwei, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
The gdbstub CSR XML is dynamically generated according to the result
of the CSR predicate() result. This has been working fine until
commit 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12")
introduced the privilege spec version check in riscv_csrrw_check().
When debugging the 'sifive_u' machine whose priv spec is at 1.10,
gdbstub reports priv spec 1.12 CSRs like menvcfg in the XML, hence
we see "remote failure reply 'E14'" message when examining all CSRs
via "info register system" from gdb.
Add the priv spec version check in the CSR XML generation logic to
fix this issue.
Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/gdbstub.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 6e7bbdbd5e..e57372db38 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -290,6 +290,9 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.csr\">");
for (i = 0; i < CSR_TABLE_SIZE; i++) {
+ if (env->priv_ver < csr_ops[i].min_priv_ver) {
+ continue;
+ }
predicate = csr_ops[i].predicate;
if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {
if (csr_ops[i].name) {
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check()
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
2023-02-28 10:40 ` [PATCH v2 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR Bin Meng
@ 2023-02-28 10:40 ` Bin Meng
2023-02-28 12:07 ` liweiwei
2023-03-02 2:50 ` LIU Zhiwei
2023-02-28 10:40 ` [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check Bin Meng
` (15 subsequent siblings)
17 siblings, 2 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 10:40 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair Francis, Bin Meng, Daniel Henrique Barboza, Liu Zhiwei,
Palmer Dabbelt, Weiwei Li, qemu-riscv
The priority policy of riscv_csrrw_check() was once adjusted in
commit eacaf4401956 ("target/riscv: Fix priority of csr related check in riscv_csrrw_check")
whose commit message says the CSR existence check should come before
the access control check, but the code changes did not agree with
the commit message, that the predicate() check actually came after
the read / write check.
In fact this was intentional. Add some comments there so that people
won't bother trying to change it without a solid reason.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
Changes in v2:
- Keep the original priority policy, instead add some comments for clarification
target/riscv/csr.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 75a540bfcb..4cc2c6370f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3776,11 +3776,12 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
int read_only = get_field(csrno, 0xC00) == 3;
int csr_min_priv = csr_ops[csrno].min_priv_ver;
- /* ensure the CSR extension is enabled. */
+ /* ensure the CSR extension is enabled */
if (!cpu->cfg.ext_icsr) {
return RISCV_EXCP_ILLEGAL_INST;
}
+ /* privileged spec version check */
if (env->priv_ver < csr_min_priv) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -3790,10 +3791,18 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
return RISCV_EXCP_ILLEGAL_INST;
}
+ /* read / write check */
if (write_mask && read_only) {
return RISCV_EXCP_ILLEGAL_INST;
}
+ /*
+ * The predicate() not only does existence check but also does some
+ * access control check which triggers for example virtual instruction
+ * exception in some cases. When writing read-only CSRs in those cases
+ * illegal instruction exception should be triggered instead of virtual
+ * instruction exception. Hence this comes after the read / write check.
+ */
RISCVException ret = csr_ops[csrno].predicate(env, csrno);
if (ret != RISCV_EXCP_NONE) {
return ret;
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
2023-02-28 10:40 ` [PATCH v2 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR Bin Meng
2023-02-28 10:40 ` [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() Bin Meng
@ 2023-02-28 10:40 ` Bin Meng
2023-02-28 12:08 ` liweiwei
2023-03-02 2:50 ` LIU Zhiwei
2023-02-28 10:40 ` [PATCH v2 04/18] target/riscv: gdbstub: Minor change for better readability Bin Meng
` (14 subsequent siblings)
17 siblings, 2 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 10:40 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair Francis, Bin Meng, Daniel Henrique Barboza, Liu Zhiwei,
Palmer Dabbelt, Weiwei Li, qemu-riscv
At present riscv_csrrw_check() checks the CSR predicate() against
NULL and throws RISCV_EXCP_ILLEGAL_INST if it is NULL. But this is
a pure software check, and has nothing to do with the emulation of
the hardware behavior, thus it is inappropriate to return illegal
instruction exception when software forgets to install the hook.
Change to use g_assert() instead.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
Changes in v2:
- new patch: Use assert() for the predicate() NULL check
target/riscv/csr.c | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4cc2c6370f..cfd7ffc5c2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3786,11 +3786,6 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
return RISCV_EXCP_ILLEGAL_INST;
}
- /* check predicate */
- if (!csr_ops[csrno].predicate) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
/* read / write check */
if (write_mask && read_only) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -3803,6 +3798,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
* illegal instruction exception should be triggered instead of virtual
* instruction exception. Hence this comes after the read / write check.
*/
+ g_assert(csr_ops[csrno].predicate != NULL);
RISCVException ret = csr_ops[csrno].predicate(env, csrno);
if (ret != RISCV_EXCP_NONE) {
return ret;
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 04/18] target/riscv: gdbstub: Minor change for better readability
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (2 preceding siblings ...)
2023-02-28 10:40 ` [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check Bin Meng
@ 2023-02-28 10:40 ` Bin Meng
2023-02-28 10:40 ` [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled Bin Meng
` (13 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 10:40 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, LIU Zhiwei, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
Use a variable 'base_reg' to represent cs->gdb_num_regs so that
the call to ricsv_gen_dynamic_vector_xml() can be placed in one
single line for better readability.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/gdbstub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index e57372db38..704f3d6922 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -385,9 +385,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
32, "riscv-32bit-fpu.xml", 0);
}
if (env->misa_ext & RVV) {
+ int base_reg = cs->gdb_num_regs;
gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
- ricsv_gen_dynamic_vector_xml(cs,
- cs->gdb_num_regs),
+ ricsv_gen_dynamic_vector_xml(cs, base_reg),
"riscv-vector.xml", 0);
}
switch (env->misa_mxl_max) {
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (3 preceding siblings ...)
2023-02-28 10:40 ` [PATCH v2 04/18] target/riscv: gdbstub: Minor change for better readability Bin Meng
@ 2023-02-28 10:40 ` Bin Meng
2023-03-01 9:52 ` LIU Zhiwei
2023-02-28 10:40 ` [PATCH v2 06/18] target/riscv: Coding style fixes in csr.c Bin Meng
` (12 subsequent siblings)
17 siblings, 1 reply; 33+ messages in thread
From: Bin Meng @ 2023-02-28 10:40 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, LIU Zhiwei, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
There is no need to generate the CSR XML if the Zicsr extension
is not enabled.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/gdbstub.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 704f3d6922..294f0ceb1c 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -406,7 +406,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
g_assert_not_reached();
}
- gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
- riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
- "riscv-csr.xml", 0);
+ if (cpu->cfg.ext_icsr) {
+ int base_reg = cs->gdb_num_regs;
+ gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
+ riscv_gen_dynamic_csr_xml(cs, base_reg),
+ "riscv-csr.xml", 0);
+ }
}
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 06/18] target/riscv: Coding style fixes in csr.c
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (4 preceding siblings ...)
2023-02-28 10:40 ` [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled Bin Meng
@ 2023-02-28 10:40 ` Bin Meng
2023-02-28 10:40 ` [PATCH v2 07/18] target/riscv: Use 'bool' type for read_only Bin Meng
` (11 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 10:40 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, LIU Zhiwei, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
Fix various places that violate QEMU coding style:
- correct multi-line comment format
- indent to opening parenthesis
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/csr.c | 62 ++++++++++++++++++++++++----------------------
1 file changed, 32 insertions(+), 30 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index cfd7ffc5c2..6a82628749 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -963,7 +963,7 @@ static RISCVException sstc_32(CPURISCVState *env, int csrno)
}
static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
- target_ulong *val)
+ target_ulong *val)
{
*val = env->vstimecmp;
@@ -971,7 +971,7 @@ static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
}
static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
- target_ulong *val)
+ target_ulong *val)
{
*val = env->vstimecmp >> 32;
@@ -979,7 +979,7 @@ static RISCVException read_vstimecmph(CPURISCVState *env, int csrno,
}
static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
@@ -996,7 +996,7 @@ static RISCVException write_vstimecmp(CPURISCVState *env, int csrno,
}
static RISCVException write_vstimecmph(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
@@ -1020,7 +1020,7 @@ static RISCVException read_stimecmp(CPURISCVState *env, int csrno,
}
static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
- target_ulong *val)
+ target_ulong *val)
{
if (riscv_cpu_virt_enabled(env)) {
*val = env->vstimecmp >> 32;
@@ -1032,7 +1032,7 @@ static RISCVException read_stimecmph(CPURISCVState *env, int csrno,
}
static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
@@ -1055,7 +1055,7 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno,
}
static RISCVException write_stimecmph(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
RISCVCPU *cpu = env_archcpu(env);
@@ -1342,7 +1342,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
/* 'E' excludes all other extensions */
if (val & RVE) {
- /* when we support 'E' we can do "val = RVE;" however
+ /*
+ * when we support 'E' we can do "val = RVE;" however
* for now we just drop writes if 'E' is present.
*/
return RISCV_EXCP_NONE;
@@ -1361,7 +1362,8 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
val &= ~RVD;
}
- /* Suppress 'C' if next instruction is not aligned
+ /*
+ * Suppress 'C' if next instruction is not aligned
* TODO: this should check next_pc
*/
if ((val & RVC) && (GETPC() & ~3) != 0) {
@@ -1830,28 +1832,28 @@ static RISCVException write_mscratch(CPURISCVState *env, int csrno,
}
static RISCVException read_mepc(CPURISCVState *env, int csrno,
- target_ulong *val)
+ target_ulong *val)
{
*val = env->mepc;
return RISCV_EXCP_NONE;
}
static RISCVException write_mepc(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
env->mepc = val;
return RISCV_EXCP_NONE;
}
static RISCVException read_mcause(CPURISCVState *env, int csrno,
- target_ulong *val)
+ target_ulong *val)
{
*val = env->mcause;
return RISCV_EXCP_NONE;
}
static RISCVException write_mcause(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
env->mcause = val;
return RISCV_EXCP_NONE;
@@ -1873,14 +1875,14 @@ static RISCVException write_mtval(CPURISCVState *env, int csrno,
/* Execution environment configuration setup */
static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
- target_ulong *val)
+ target_ulong *val)
{
*val = env->menvcfg;
return RISCV_EXCP_NONE;
}
static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
@@ -1893,14 +1895,14 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
}
static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
- target_ulong *val)
+ target_ulong *val)
{
*val = env->menvcfg >> 32;
return RISCV_EXCP_NONE;
}
static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
uint64_t valh = (uint64_t)val << 32;
@@ -1911,7 +1913,7 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
}
static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
- target_ulong *val)
+ target_ulong *val)
{
RISCVException ret;
@@ -1925,7 +1927,7 @@ static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
}
static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
RISCVException ret;
@@ -1940,7 +1942,7 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
}
static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
- target_ulong *val)
+ target_ulong *val)
{
RISCVException ret;
@@ -1954,7 +1956,7 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
}
static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
RISCVException ret;
@@ -1974,7 +1976,7 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
}
static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
- target_ulong *val)
+ target_ulong *val)
{
RISCVException ret;
@@ -1988,7 +1990,7 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
}
static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
uint64_t valh = (uint64_t)val << 32;
@@ -2031,13 +2033,13 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
}
static RISCVException write_mstateen_1_3(CPURISCVState *env, int csrno,
- target_ulong new_val)
+ target_ulong new_val)
{
return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
}
static RISCVException read_mstateenh(CPURISCVState *env, int csrno,
- target_ulong *val)
+ target_ulong *val)
{
*val = env->mstateen[csrno - CSR_MSTATEEN0H] >> 32;
@@ -2058,7 +2060,7 @@ static RISCVException write_mstateenh(CPURISCVState *env, int csrno,
}
static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
- target_ulong new_val)
+ target_ulong new_val)
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
@@ -2066,7 +2068,7 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,
}
static RISCVException write_mstateenh_1_3(CPURISCVState *env, int csrno,
- target_ulong new_val)
+ target_ulong new_val)
{
return write_mstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
}
@@ -2103,7 +2105,7 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
}
static RISCVException write_hstateen_1_3(CPURISCVState *env, int csrno,
- target_ulong new_val)
+ target_ulong new_val)
{
return write_hstateen(env, csrno, SMSTATEEN_STATEEN, new_val);
}
@@ -2142,7 +2144,7 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,
}
static RISCVException write_hstateenh_1_3(CPURISCVState *env, int csrno,
- target_ulong new_val)
+ target_ulong new_val)
{
return write_hstateenh(env, csrno, SMSTATEEN_STATEEN, new_val);
}
@@ -3335,7 +3337,7 @@ static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
}
static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
- target_ulong val)
+ target_ulong val)
{
mseccfg_csr_write(env, val);
return RISCV_EXCP_NONE;
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 07/18] target/riscv: Use 'bool' type for read_only
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (5 preceding siblings ...)
2023-02-28 10:40 ` [PATCH v2 06/18] target/riscv: Coding style fixes in csr.c Bin Meng
@ 2023-02-28 10:40 ` Bin Meng
2023-02-28 10:40 ` [PATCH v2 08/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit Bin Meng
` (10 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 10:40 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, LIU Zhiwei, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 933 bytes --]
The read_only variable is currently declared as an 'int', but it
should really be a 'bool'.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6a82628749..9264db6110 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3775,7 +3775,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
RISCVCPU *cpu)
{
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
- int read_only = get_field(csrno, 0xC00) == 3;
+ bool read_only = get_field(csrno, 0xC00) == 3;
int csr_min_priv = csr_ops[csrno].min_priv_ver;
/* ensure the CSR extension is enabled */
--
2.25.1
‘\x02
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 08/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (6 preceding siblings ...)
2023-02-28 10:40 ` [PATCH v2 07/18] target/riscv: Use 'bool' type for read_only Bin Meng
@ 2023-02-28 10:40 ` Bin Meng
2023-02-28 10:40 ` [PATCH v2 09/18] target/riscv: Simplify getting RISCVCPU pointer from env Bin Meng
` (9 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 10:40 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, LIU Zhiwei, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
Use the register index that has already been calculated in the
pmpcfg_csr_{read,write} call.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9264db6110..a3e0e5755c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3360,7 +3360,7 @@ static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
if (!check_pmp_reg_index(env, reg_index)) {
return RISCV_EXCP_ILLEGAL_INST;
}
- *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
+ *val = pmpcfg_csr_read(env, reg_index);
return RISCV_EXCP_NONE;
}
@@ -3372,7 +3372,7 @@ static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
if (!check_pmp_reg_index(env, reg_index)) {
return RISCV_EXCP_ILLEGAL_INST;
}
- pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
+ pmpcfg_csr_write(env, reg_index, val);
return RISCV_EXCP_NONE;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 09/18] target/riscv: Simplify getting RISCVCPU pointer from env
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (7 preceding siblings ...)
2023-02-28 10:40 ` [PATCH v2 08/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit Bin Meng
@ 2023-02-28 10:40 ` Bin Meng
2023-02-28 10:40 ` [PATCH v2 10/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 Bin Meng
` (8 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 10:40 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, LIU Zhiwei, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
Use env_archcpu() to get RISCVCPU pointer from env directly.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/csr.c | 36 ++++++++++++------------------------
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a3e0e5755c..8e827362cc 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -46,8 +46,7 @@ static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
uint64_t bit)
{
bool virt = riscv_cpu_virt_enabled(env);
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPU *cpu = env_archcpu(env);
if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
return RISCV_EXCP_NONE;
@@ -90,8 +89,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
static RISCVException vs(CPURISCVState *env, int csrno)
{
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPU *cpu = env_archcpu(env);
if (env->misa_ext & RVV ||
cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
@@ -108,8 +106,7 @@ static RISCVException vs(CPURISCVState *env, int csrno)
static RISCVException ctr(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPU *cpu = env_archcpu(env);
int ctr_index;
target_ulong ctr_mask;
int base_csrno = CSR_CYCLE;
@@ -166,8 +163,7 @@ static RISCVException ctr32(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
static RISCVException mctr(CPURISCVState *env, int csrno)
{
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPU *cpu = env_archcpu(env);
int ctr_index;
int base_csrno = CSR_MHPMCOUNTER3;
@@ -195,8 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
static RISCVException sscofpmf(CPURISCVState *env, int csrno)
{
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_sscofpmf) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -321,8 +316,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno)
static RISCVException mstateen(CPURISCVState *env, int csrno)
{
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -333,8 +327,7 @@ static RISCVException mstateen(CPURISCVState *env, int csrno)
static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
{
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -363,8 +356,7 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
{
bool virt = riscv_cpu_virt_enabled(env);
int index = csrno - CSR_SSTATEEN0;
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPU *cpu = env_archcpu(env);
if (!cpu->cfg.ext_smstateen) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -918,8 +910,7 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
static RISCVException sstc(CPURISCVState *env, int csrno)
{
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPU *cpu = env_archcpu(env);
bool hmode_check = false;
if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
@@ -1152,8 +1143,7 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
target_ulong *val)
{
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPU *cpu = env_archcpu(env);
*val = cpu->cfg.mvendorid;
return RISCV_EXCP_NONE;
@@ -1162,8 +1152,7 @@ static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
static RISCVException read_marchid(CPURISCVState *env, int csrno,
target_ulong *val)
{
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPU *cpu = env_archcpu(env);
*val = cpu->cfg.marchid;
return RISCV_EXCP_NONE;
@@ -1172,8 +1161,7 @@ static RISCVException read_marchid(CPURISCVState *env, int csrno,
static RISCVException read_mimpid(CPURISCVState *env, int csrno,
target_ulong *val)
{
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPU *cpu = env_archcpu(env);
*val = cpu->cfg.mimpid;
return RISCV_EXCP_NONE;
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 10/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (8 preceding siblings ...)
2023-02-28 10:40 ` [PATCH v2 09/18] target/riscv: Simplify getting RISCVCPU pointer from env Bin Meng
@ 2023-02-28 10:40 ` Bin Meng
2023-02-28 10:40 ` [PATCH v2 11/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() Bin Meng
` (7 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 10:40 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, LIU Zhiwei, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
At present the odd-numbered PMP configuration registers for RV64 are
reported in the CSR XML by QEMU gdbstub. However these registers do
not exist on RV64 so trying to access them from gdb results in 'E14'.
Move the pmpcfgX index check from the actual read/write routine to
the PMP CSR predicate() routine, so that non-existent pmpcfgX won't
be reported in the CSR XML for RV64.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
Changes in v2:
- keep the 'RV128 restriction check' todo comment
target/riscv/csr.c | 24 +++++++++---------------
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 8e827362cc..7284fd8a0d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -412,6 +412,15 @@ static int aia_hmode32(CPURISCVState *env, int csrno)
static RISCVException pmp(CPURISCVState *env, int csrno)
{
if (riscv_cpu_cfg(env)->pmp) {
+ if (csrno <= CSR_PMPCFG3) {
+ uint32_t reg_index = csrno - CSR_PMPCFG0;
+
+ /* TODO: RV128 restriction check */
+ if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ }
+
return RISCV_EXCP_NONE;
}
@@ -3331,23 +3340,11 @@ static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
-{
- /* TODO: RV128 restriction check */
- if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) {
- return false;
- }
- return true;
-}
-
static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
target_ulong *val)
{
uint32_t reg_index = csrno - CSR_PMPCFG0;
- if (!check_pmp_reg_index(env, reg_index)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
*val = pmpcfg_csr_read(env, reg_index);
return RISCV_EXCP_NONE;
}
@@ -3357,9 +3354,6 @@ static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
{
uint32_t reg_index = csrno - CSR_PMPCFG0;
- if (!check_pmp_reg_index(env, reg_index)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
pmpcfg_csr_write(env, reg_index, val);
return RISCV_EXCP_NONE;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 11/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (9 preceding siblings ...)
2023-02-28 10:40 ` [PATCH v2 10/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 Bin Meng
@ 2023-02-28 10:40 ` Bin Meng
2023-02-28 13:45 ` [PATCH v2 12/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml Bin Meng
` (6 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 10:40 UTC (permalink / raw)
To: qemu-devel
Cc: Weiwei Li, LIU Zhiwei, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
Since commit 94452ac4cf26 ("target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml")
the 3 FPU CSRs are removed from the XML target decription. The
original intent of that commit was based on the assumption that
the 3 FPU CSRs will show up in the riscv-csr.xml so the ones in
riscv-*-fpu.xml are redundant. But unforuantely that is not true.
As the FPU CSR predicate() has a run-time check on MSTATUS.FS,
at the time when CSR XML is generated MSTATUS.FS is unset, hence
no FPU CSRs will be reported.
The FPU CSR predicate() already considered such a case of being
accessed by a debugger. All we need to do is to turn on debugger
mode before calling predicate().
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/gdbstub.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 294f0ceb1c..ef52f41460 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -280,6 +280,10 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
int bitsize = 16 << env->misa_mxl_max;
int i;
+#if !defined(CONFIG_USER_ONLY)
+ env->debugger = true;
+#endif
+
/* Until gdb knows about 128-bit registers */
if (bitsize > 64) {
bitsize = 64;
@@ -308,6 +312,11 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
g_string_append_printf(s, "</feature>");
cpu->dyn_csr_xml = g_string_free(s, false);
+
+#if !defined(CONFIG_USER_ONLY)
+ env->debugger = false;
+#endif
+
return CSR_TABLE_SIZE;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check()
2023-02-28 10:40 ` [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() Bin Meng
@ 2023-02-28 12:07 ` liweiwei
2023-03-02 2:50 ` LIU Zhiwei
1 sibling, 0 replies; 33+ messages in thread
From: liweiwei @ 2023-02-28 12:07 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Alistair Francis, Bin Meng, Daniel Henrique Barboza, Liu Zhiwei,
Palmer Dabbelt, qemu-riscv
On 2023/2/28 18:40, Bin Meng wrote:
> The priority policy of riscv_csrrw_check() was once adjusted in
> commit eacaf4401956 ("target/riscv: Fix priority of csr related check in riscv_csrrw_check")
> whose commit message says the CSR existence check should come before
> the access control check, but the code changes did not agree with
> the commit message, that the predicate() check actually came after
> the read / write check.
>
> In fact this was intentional. Add some comments there so that people
> won't bother trying to change it without a solid reason.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Weiwei Li
> ---
>
> Changes in v2:
> - Keep the original priority policy, instead add some comments for clarification
>
> target/riscv/csr.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 75a540bfcb..4cc2c6370f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3776,11 +3776,12 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> int read_only = get_field(csrno, 0xC00) == 3;
> int csr_min_priv = csr_ops[csrno].min_priv_ver;
>
> - /* ensure the CSR extension is enabled. */
> + /* ensure the CSR extension is enabled */
> if (!cpu->cfg.ext_icsr) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + /* privileged spec version check */
> if (env->priv_ver < csr_min_priv) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
> @@ -3790,10 +3791,18 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + /* read / write check */
> if (write_mask && read_only) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + /*
> + * The predicate() not only does existence check but also does some
> + * access control check which triggers for example virtual instruction
> + * exception in some cases. When writing read-only CSRs in those cases
> + * illegal instruction exception should be triggered instead of virtual
> + * instruction exception. Hence this comes after the read / write check.
> + */
> RISCVException ret = csr_ops[csrno].predicate(env, csrno);
> if (ret != RISCV_EXCP_NONE) {
> return ret;
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check
2023-02-28 10:40 ` [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check Bin Meng
@ 2023-02-28 12:08 ` liweiwei
2023-03-02 2:50 ` LIU Zhiwei
1 sibling, 0 replies; 33+ messages in thread
From: liweiwei @ 2023-02-28 12:08 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Alistair Francis, Bin Meng, Daniel Henrique Barboza, Liu Zhiwei,
Palmer Dabbelt, qemu-riscv
On 2023/2/28 18:40, Bin Meng wrote:
> At present riscv_csrrw_check() checks the CSR predicate() against
> NULL and throws RISCV_EXCP_ILLEGAL_INST if it is NULL. But this is
> a pure software check, and has nothing to do with the emulation of
> the hardware behavior, thus it is inappropriate to return illegal
> instruction exception when software forgets to install the hook.
>
> Change to use g_assert() instead.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li<liweiwei@iscas.ac.cn>
Weiwei Li
> ---
>
> Changes in v2:
> - new patch: Use assert() for the predicate() NULL check
>
> target/riscv/csr.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4cc2c6370f..cfd7ffc5c2 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3786,11 +3786,6 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> - /* check predicate */
> - if (!csr_ops[csrno].predicate) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -
> /* read / write check */
> if (write_mask && read_only) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -3803,6 +3798,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> * illegal instruction exception should be triggered instead of virtual
> * instruction exception. Hence this comes after the read / write check.
> */
> + g_assert(csr_ops[csrno].predicate != NULL);
> RISCVException ret = csr_ops[csrno].predicate(env, csrno);
> if (ret != RISCV_EXCP_NONE) {
> return ret;
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 12/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (10 preceding siblings ...)
2023-02-28 10:40 ` [PATCH v2 11/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() Bin Meng
@ 2023-02-28 13:45 ` Bin Meng
2023-02-28 13:45 ` [PATCH v2 13/18] target/riscv: Allow debugger to access user timer and counter CSRs Bin Meng
` (5 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 13:45 UTC (permalink / raw)
To: qemu-devel
Cc: Bin Meng, Weiwei Li, LIU Zhiwei, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
From: Bin Meng <bmeng@tinylab.org>
It's worth noting that the vector CSR predicate() has a similar
run-time check logic to the FPU CSR. With the previous patch our
gdbstub can correctly report these vector CSRs via the CSR xml.
Commit 719d3561b269 ("target/riscv: gdb: support vector registers for rv64 & rv32")
inserted these vector CSRs in an ad-hoc, non-standard way in the
riscv-vector.xml. Now we can treat these CSRs no different from
other CSRs.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/gdbstub.c | 75 ------------------------------------------
1 file changed, 75 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index ef52f41460..6048541606 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -127,40 +127,6 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
return 0;
}
-/*
- * Convert register index number passed by GDB to the correspond
- * vector CSR number. Vector CSRs are defined after vector registers
- * in dynamic generated riscv-vector.xml, thus the starting register index
- * of vector CSRs is 32.
- * Return 0 if register index number is out of range.
- */
-static int riscv_gdb_vector_csrno(int num_regs)
-{
- /*
- * The order of vector CSRs in the switch case
- * should match with the order defined in csr_ops[].
- */
- switch (num_regs) {
- case 32:
- return CSR_VSTART;
- case 33:
- return CSR_VXSAT;
- case 34:
- return CSR_VXRM;
- case 35:
- return CSR_VCSR;
- case 36:
- return CSR_VL;
- case 37:
- return CSR_VTYPE;
- case 38:
- return CSR_VLENB;
- default:
- /* Unknown register. */
- return 0;
- }
-}
-
static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
{
uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
@@ -174,19 +140,6 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
return cnt;
}
- int csrno = riscv_gdb_vector_csrno(n);
-
- if (!csrno) {
- return 0;
- }
-
- target_ulong val = 0;
- int result = riscv_csrrw_debug(env, csrno, &val, 0, 0);
-
- if (result == RISCV_EXCP_NONE) {
- return gdb_get_regl(buf, val);
- }
-
return 0;
}
@@ -201,19 +154,6 @@ static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
return vlenb;
}
- int csrno = riscv_gdb_vector_csrno(n);
-
- if (!csrno) {
- return 0;
- }
-
- target_ulong val = ldtul_p(mem_buf);
- int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
-
- if (result == RISCV_EXCP_NONE) {
- return sizeof(target_ulong);
- }
-
return 0;
}
@@ -361,21 +301,6 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg)
num_regs++;
}
- /* Define vector CSRs */
- const char *vector_csrs[7] = {
- "vstart", "vxsat", "vxrm", "vcsr",
- "vl", "vtype", "vlenb"
- };
-
- for (i = 0; i < 7; i++) {
- g_string_append_printf(s,
- "<reg name=\"%s\" bitsize=\"%d\""
- " regnum=\"%d\" group=\"vector\""
- " type=\"int\"/>",
- vector_csrs[i], TARGET_LONG_BITS, base_reg++);
- num_regs++;
- }
-
g_string_append_printf(s, "</feature>");
cpu->dyn_vreg_xml = g_string_free(s, false);
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 13/18] target/riscv: Allow debugger to access user timer and counter CSRs
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (11 preceding siblings ...)
2023-02-28 13:45 ` [PATCH v2 12/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml Bin Meng
@ 2023-02-28 13:45 ` Bin Meng
2023-02-28 13:45 ` [PATCH v2 14/18] target/riscv: Allow debugger to access seed CSR Bin Meng
` (4 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 13:45 UTC (permalink / raw)
To: qemu-devel
Cc: Bin Meng, Weiwei Li, LIU Zhiwei, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
From: Bin Meng <bmeng@tinylab.org>
At present user timer and counter CSRs are not reported in the
CSR XML hence gdb cannot access them.
Fix it by adding a debugger check in their predicate() routine.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/csr.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7284fd8a0d..10ae5df5e6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -131,6 +131,10 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
skip_ext_pmu_check:
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) {
return RISCV_EXCP_ILLEGAL_INST;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 14/18] target/riscv: Allow debugger to access seed CSR
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (12 preceding siblings ...)
2023-02-28 13:45 ` [PATCH v2 13/18] target/riscv: Allow debugger to access user timer and counter CSRs Bin Meng
@ 2023-02-28 13:45 ` Bin Meng
2023-02-28 13:45 ` [PATCH v2 15/18] target/riscv: Allow debugger to access {h, s}stateen CSRs Bin Meng
` (3 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Bin Meng @ 2023-02-28 13:45 UTC (permalink / raw)
To: qemu-devel
Cc: Bin Meng, Weiwei Li, LIU Zhiwei, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
From: Bin Meng <bmeng@tinylab.org>
At present seed CSR is not reported in the CSR XML hence gdb cannot
access it.
Fix it by adding a debugger check in its predicate() routine.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
(no changes since v1)
target/riscv/csr.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 10ae5df5e6..15b23b9b5a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -459,6 +459,10 @@ static RISCVException seed(CPURISCVState *env, int csrno)
}
#if !defined(CONFIG_USER_ONLY)
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
/*
* With a CSR read-write instruction:
* 1) The seed CSR is always available in machine mode as normal.
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 15/18] target/riscv: Allow debugger to access {h, s}stateen CSRs
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (13 preceding siblings ...)
2023-02-28 13:45 ` [PATCH v2 14/18] target/riscv: Allow debugger to access seed CSR Bin Meng
@ 2023-02-28 13:45 ` Bin Meng
2023-03-02 2:44 ` [PATCH v2 15/18] target/riscv: Allow debugger to access {h,s}stateen CSRs LIU Zhiwei
2023-02-28 13:45 ` [PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs Bin Meng
` (2 subsequent siblings)
17 siblings, 1 reply; 33+ messages in thread
From: Bin Meng @ 2023-02-28 13:45 UTC (permalink / raw)
To: qemu-devel
Cc: Bin Meng, Weiwei Li, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Liu Zhiwei, Palmer Dabbelt, qemu-riscv
From: Bin Meng <bmeng@tinylab.org>
At present {h,s}stateen CSRs are not reported in the CSR XML
hence gdb cannot access them.
Fix it by adjusting their predicate() routine logic so that the
static config check comes before the run-time check, as well as
adding a debugger check.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
---
(no changes since v1)
target/riscv/csr.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 15b23b9b5a..a0e70f5ba0 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -337,13 +337,22 @@ static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
return RISCV_EXCP_ILLEGAL_INST;
}
+ RISCVException ret = hmode(env, csrno);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
if (env->priv < PRV_M) {
if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) {
return RISCV_EXCP_ILLEGAL_INST;
}
}
- return hmode(env, csrno);
+ return RISCV_EXCP_NONE;
}
static RISCVException hstateen(CPURISCVState *env, int csrno)
@@ -366,6 +375,15 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+ RISCVException ret = smode(env, csrno);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
if (env->priv < PRV_M) {
if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -378,7 +396,7 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
}
}
- return smode(env, csrno);
+ return RISCV_EXCP_NONE;
}
/* Checks if PointerMasking registers could be accessed */
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (14 preceding siblings ...)
2023-02-28 13:45 ` [PATCH v2 15/18] target/riscv: Allow debugger to access {h, s}stateen CSRs Bin Meng
@ 2023-02-28 13:45 ` Bin Meng
2023-03-02 2:44 ` LIU Zhiwei
2023-02-28 13:45 ` [PATCH v2 17/18] target/riscv: Drop priv level check in mseccfg predicate() Bin Meng
2023-02-28 13:45 ` [PATCH v2 18/18] target/riscv: Group all predicate() routines together Bin Meng
17 siblings, 1 reply; 33+ messages in thread
From: Bin Meng @ 2023-02-28 13:45 UTC (permalink / raw)
To: qemu-devel
Cc: Bin Meng, Weiwei Li, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Liu Zhiwei, Palmer Dabbelt, qemu-riscv
From: Bin Meng <bmeng@tinylab.org>
At present with a debugger attached sstc CSRs can only be accssed
when CPU is in M-mode, or configured correctly.
Fix it by adjusting their predicate() routine logic so that the
static config check comes before the run-time check, as well as
adding a debugger check.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
---
(no changes since v1)
target/riscv/csr.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a0e70f5ba0..020c3f524f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -952,6 +952,19 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+ if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
+ hmode_check = true;
+ }
+
+ RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
if (env->priv == PRV_M) {
return RISCV_EXCP_NONE;
}
@@ -972,11 +985,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
}
}
- if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
- hmode_check = true;
- }
-
- return hmode_check ? hmode(env, csrno) : smode(env, csrno);
+ return RISCV_EXCP_NONE;
}
static RISCVException sstc_32(CPURISCVState *env, int csrno)
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 17/18] target/riscv: Drop priv level check in mseccfg predicate()
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (15 preceding siblings ...)
2023-02-28 13:45 ` [PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs Bin Meng
@ 2023-02-28 13:45 ` Bin Meng
2023-03-02 2:45 ` LIU Zhiwei
2023-02-28 13:45 ` [PATCH v2 18/18] target/riscv: Group all predicate() routines together Bin Meng
17 siblings, 1 reply; 33+ messages in thread
From: Bin Meng @ 2023-02-28 13:45 UTC (permalink / raw)
To: qemu-devel
Cc: Bin Meng, Weiwei Li, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Liu Zhiwei, Palmer Dabbelt, qemu-riscv
From: Bin Meng <bmeng@tinylab.org>
riscv_csrrw_check() already does the generic privilege level check
hence there is no need to do the specific M-mode access check in
the mseccfg predicate().
With this change debugger can access the mseccfg CSR anytime.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
---
(no changes since v1)
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 020c3f524f..785f6f4d45 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -451,7 +451,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
static RISCVException epmp(CPURISCVState *env, int csrno)
{
- if (env->priv == PRV_M && riscv_cpu_cfg(env)->epmp) {
+ if (riscv_cpu_cfg(env)->epmp) {
return RISCV_EXCP_NONE;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* [PATCH v2 18/18] target/riscv: Group all predicate() routines together
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
` (16 preceding siblings ...)
2023-02-28 13:45 ` [PATCH v2 17/18] target/riscv: Drop priv level check in mseccfg predicate() Bin Meng
@ 2023-02-28 13:45 ` Bin Meng
2023-03-02 2:47 ` LIU Zhiwei
17 siblings, 1 reply; 33+ messages in thread
From: Bin Meng @ 2023-02-28 13:45 UTC (permalink / raw)
To: qemu-devel
Cc: Bin Meng, Weiwei Li, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Liu Zhiwei, Palmer Dabbelt, qemu-riscv
From: Bin Meng <bmeng@tinylab.org>
Move sstc()/sstc32() to where all predicate() routines live, and
smstateen_acc_ok() to near {read,write}_xenvcfg().
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
---
Changes in v2:
- move smstateen_acc_ok() to near {read,write}_xenvcfg()
target/riscv/csr.c | 177 ++++++++++++++++++++++-----------------------
1 file changed, 87 insertions(+), 90 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 785f6f4d45..3a7e0217e2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -40,42 +40,6 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
}
-/* Predicates */
-#if !defined(CONFIG_USER_ONLY)
-static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
- uint64_t bit)
-{
- bool virt = riscv_cpu_virt_enabled(env);
- RISCVCPU *cpu = env_archcpu(env);
-
- if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
- return RISCV_EXCP_NONE;
- }
-
- if (!(env->mstateen[index] & bit)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
- if (virt) {
- if (!(env->hstateen[index] & bit)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
-
- if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
- }
-
- if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
- if (!(env->sstateen[index] & bit)) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
- }
-
- return RISCV_EXCP_NONE;
-}
-#endif
-
static RISCVException fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
@@ -399,6 +363,60 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
return RISCV_EXCP_NONE;
}
+static RISCVException sstc(CPURISCVState *env, int csrno)
+{
+ RISCVCPU *cpu = env_archcpu(env);
+ bool hmode_check = false;
+
+ if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
+ hmode_check = true;
+ }
+
+ RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
+ if (env->priv == PRV_M) {
+ return RISCV_EXCP_NONE;
+ }
+
+ /*
+ * No need of separate function for rv32 as menvcfg stores both menvcfg
+ * menvcfgh for RV32.
+ */
+ if (!(get_field(env->mcounteren, COUNTEREN_TM) &&
+ get_field(env->menvcfg, MENVCFG_STCE))) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ if (riscv_cpu_virt_enabled(env)) {
+ if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
+ get_field(env->henvcfg, HENVCFG_STCE))) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException sstc_32(CPURISCVState *env, int csrno)
+{
+ if (riscv_cpu_mxl(env) != MXL_RV32) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ return sstc(env, csrno);
+}
+
/* Checks if PointerMasking registers could be accessed */
static RISCVException pointer_masking(CPURISCVState *env, int csrno)
{
@@ -943,60 +961,6 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-static RISCVException sstc(CPURISCVState *env, int csrno)
-{
- RISCVCPU *cpu = env_archcpu(env);
- bool hmode_check = false;
-
- if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
- if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
- hmode_check = true;
- }
-
- RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
- if (ret != RISCV_EXCP_NONE) {
- return ret;
- }
-
- if (env->debugger) {
- return RISCV_EXCP_NONE;
- }
-
- if (env->priv == PRV_M) {
- return RISCV_EXCP_NONE;
- }
-
- /*
- * No need of separate function for rv32 as menvcfg stores both menvcfg
- * menvcfgh for RV32.
- */
- if (!(get_field(env->mcounteren, COUNTEREN_TM) &&
- get_field(env->menvcfg, MENVCFG_STCE))) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
- if (riscv_cpu_virt_enabled(env)) {
- if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
- get_field(env->henvcfg, HENVCFG_STCE))) {
- return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
- }
- }
-
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException sstc_32(CPURISCVState *env, int csrno)
-{
- if (riscv_cpu_mxl(env) != MXL_RV32) {
- return RISCV_EXCP_ILLEGAL_INST;
- }
-
- return sstc(env, csrno);
-}
-
static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1944,6 +1908,39 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
+ uint64_t bit)
+{
+ bool virt = riscv_cpu_virt_enabled(env);
+ RISCVCPU *cpu = env_archcpu(env);
+
+ if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
+ return RISCV_EXCP_NONE;
+ }
+
+ if (!(env->mstateen[index] & bit)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ if (virt) {
+ if (!(env->hstateen[index] & bit)) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+
+ if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
+ return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ }
+
+ if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
+ if (!(env->sstateen[index] & bit)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
target_ulong *val)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread
* Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
2023-02-28 10:40 ` [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled Bin Meng
@ 2023-03-01 9:52 ` LIU Zhiwei
2023-03-01 9:55 ` Bin Meng
0 siblings, 1 reply; 33+ messages in thread
From: LIU Zhiwei @ 2023-03-01 9:52 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Weiwei Li, Alistair Francis, Bin Meng, Daniel Henrique Barboza,
Palmer Dabbelt, qemu-riscv
On 2023/2/28 18:40, Bin Meng wrote:
> There is no need to generate the CSR XML if the Zicsr extension
> is not enabled.
Should we generate the FPU XML or Vector XML when Zicsr is not enabled?
Zhiwei
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
>
> (no changes since v1)
>
> target/riscv/gdbstub.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 704f3d6922..294f0ceb1c 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -406,7 +406,10 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
> g_assert_not_reached();
> }
>
> - gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> - riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
> - "riscv-csr.xml", 0);
> + if (cpu->cfg.ext_icsr) {
> + int base_reg = cs->gdb_num_regs;
> + gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> + riscv_gen_dynamic_csr_xml(cs, base_reg),
> + "riscv-csr.xml", 0);
> + }
> }
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
2023-03-01 9:52 ` LIU Zhiwei
@ 2023-03-01 9:55 ` Bin Meng
2023-03-01 23:43 ` Palmer Dabbelt
0 siblings, 1 reply; 33+ messages in thread
From: Bin Meng @ 2023-03-01 9:55 UTC (permalink / raw)
To: LIU Zhiwei
Cc: Bin Meng, qemu-devel, Weiwei Li, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
On Wed, Mar 1, 2023 at 5:52 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
>
> On 2023/2/28 18:40, Bin Meng wrote:
> > There is no need to generate the CSR XML if the Zicsr extension
> > is not enabled.
>
> Should we generate the FPU XML or Vector XML when Zicsr is not enabled?
Good point. I think we should disable that too.
>
> Zhiwei
>
Regards,
Bin
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
2023-03-01 9:55 ` Bin Meng
@ 2023-03-01 23:43 ` Palmer Dabbelt
2023-03-02 0:30 ` Bin Meng
0 siblings, 1 reply; 33+ messages in thread
From: Palmer Dabbelt @ 2023-03-01 23:43 UTC (permalink / raw)
To: Bin Meng
Cc: zhiwei_liu, bmeng, qemu-devel, liweiwei, Alistair Francis,
bin.meng, dbarboza, qemu-riscv
On Wed, 01 Mar 2023 01:55:34 PST (-0800), Bin Meng wrote:
> On Wed, Mar 1, 2023 at 5:52 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>>
>>
>> On 2023/2/28 18:40, Bin Meng wrote:
>> > There is no need to generate the CSR XML if the Zicsr extension
>> > is not enabled.
>>
>> Should we generate the FPU XML or Vector XML when Zicsr is not enabled?
>
> Good point. I think we should disable that too.
Seems reasonable. Did you want to do that as part of a v3, or just as a
follow-on fix?
>> Zhiwei
>>
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
2023-03-01 23:43 ` Palmer Dabbelt
@ 2023-03-02 0:30 ` Bin Meng
2023-03-02 0:58 ` Palmer Dabbelt
2023-03-02 2:43 ` LIU Zhiwei
0 siblings, 2 replies; 33+ messages in thread
From: Bin Meng @ 2023-03-02 0:30 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: zhiwei_liu, bmeng, qemu-devel, liweiwei, Alistair Francis,
bin.meng, dbarboza, qemu-riscv
On Thu, Mar 2, 2023 at 7:43 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Wed, 01 Mar 2023 01:55:34 PST (-0800), Bin Meng wrote:
> > On Wed, Mar 1, 2023 at 5:52 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
> >>
> >>
> >> On 2023/2/28 18:40, Bin Meng wrote:
> >> > There is no need to generate the CSR XML if the Zicsr extension
> >> > is not enabled.
> >>
> >> Should we generate the FPU XML or Vector XML when Zicsr is not enabled?
> >
> > Good point. I think we should disable that too.
>
> Seems reasonable. Did you want to do that as part of a v3, or just as a
> follow-on fix?
>
I looked at this further.
The FPU / Vector XML is guarded by the " env->misa_ext" check. If
Zicsr is disabled while F or V extension is off, QEMU will error out
in riscv_cpu_realize() earlier before the gdbstub init.
So current patch should be fine.
Regards,
Bin
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
2023-03-02 0:30 ` Bin Meng
@ 2023-03-02 0:58 ` Palmer Dabbelt
2023-03-02 2:43 ` LIU Zhiwei
1 sibling, 0 replies; 33+ messages in thread
From: Palmer Dabbelt @ 2023-03-02 0:58 UTC (permalink / raw)
To: Bin Meng
Cc: zhiwei_liu, bmeng, qemu-devel, liweiwei, Alistair Francis,
bin.meng, dbarboza, qemu-riscv
On Wed, 01 Mar 2023 16:30:52 PST (-0800), Bin Meng wrote:
> On Thu, Mar 2, 2023 at 7:43 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>>
>> On Wed, 01 Mar 2023 01:55:34 PST (-0800), Bin Meng wrote:
>> > On Wed, Mar 1, 2023 at 5:52 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>> >>
>> >>
>> >> On 2023/2/28 18:40, Bin Meng wrote:
>> >> > There is no need to generate the CSR XML if the Zicsr extension
>> >> > is not enabled.
>> >>
>> >> Should we generate the FPU XML or Vector XML when Zicsr is not enabled?
>> >
>> > Good point. I think we should disable that too.
>>
>> Seems reasonable. Did you want to do that as part of a v3, or just as a
>> follow-on fix?
>>
>
> I looked at this further.
>
> The FPU / Vector XML is guarded by the " env->misa_ext" check. If
> Zicsr is disabled while F or V extension is off, QEMU will error out
> in riscv_cpu_realize() earlier before the gdbstub init.
>
> So current patch should be fine.
There's a merge conflict that git auto-resolved as
diff --cc target/riscv/csr.c
index a1ecf62305,3a7e0217e2..a2cf3536f0
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@@ -90,10 -53,10 +53,9 @@@ static RISCVException fs(CPURISCVState
static RISCVException vs(CPURISCVState *env, int csrno)
{
- CPUState *cs = env_cpu(env);
- RISCVCPU *cpu = RISCV_CPU(cs);
+ RISCVCPU *cpu = env_archcpu(env);
- if (env->misa_ext & RVV ||
- cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
+ if (cpu->cfg.ext_zve32f) {
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
which looks correct to me. It's passing my tests and queued up, but LMK if
something looks wrong.
Thanks!
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
2023-03-02 0:30 ` Bin Meng
2023-03-02 0:58 ` Palmer Dabbelt
@ 2023-03-02 2:43 ` LIU Zhiwei
1 sibling, 0 replies; 33+ messages in thread
From: LIU Zhiwei @ 2023-03-02 2:43 UTC (permalink / raw)
To: Bin Meng, Palmer Dabbelt
Cc: bmeng, qemu-devel, liweiwei, Alistair Francis, bin.meng,
dbarboza, qemu-riscv
On 2023/3/2 8:30, Bin Meng wrote:
> On Thu, Mar 2, 2023 at 7:43 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>> On Wed, 01 Mar 2023 01:55:34 PST (-0800), Bin Meng wrote:
>>> On Wed, Mar 1, 2023 at 5:52 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>>>>
>>>> On 2023/2/28 18:40, Bin Meng wrote:
>>>>> There is no need to generate the CSR XML if the Zicsr extension
>>>>> is not enabled.
>>>> Should we generate the FPU XML or Vector XML when Zicsr is not enabled?
>>> Good point. I think we should disable that too.
>> Seems reasonable. Did you want to do that as part of a v3, or just as a
>> follow-on fix?
>>
> I looked at this further.
>
> The FPU / Vector XML is guarded by the " env->misa_ext" check. If
> Zicsr is disabled while F or V extension is off, QEMU will error out
> in riscv_cpu_realize() earlier before the gdbstub init.
Make sense.
Zhiwei
>
> So current patch should be fine.
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 15/18] target/riscv: Allow debugger to access {h,s}stateen CSRs
2023-02-28 13:45 ` [PATCH v2 15/18] target/riscv: Allow debugger to access {h, s}stateen CSRs Bin Meng
@ 2023-03-02 2:44 ` LIU Zhiwei
0 siblings, 0 replies; 33+ messages in thread
From: LIU Zhiwei @ 2023-03-02 2:44 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Bin Meng, Weiwei Li, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
On 2023/2/28 21:45, Bin Meng wrote:
> From: Bin Meng <bmeng@tinylab.org>
>
> At present {h,s}stateen CSRs are not reported in the CSR XML
> hence gdb cannot access them.
>
> Fix it by adjusting their predicate() routine logic so that the
> static config check comes before the run-time check, as well as
> adding a debugger check.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> ---
>
> (no changes since v1)
>
> target/riscv/csr.c | 22 ++++++++++++++++++++--
> 1 file changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 15b23b9b5a..a0e70f5ba0 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -337,13 +337,22 @@ static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + RISCVException ret = hmode(env, csrno);
> + if (ret != RISCV_EXCP_NONE) {
> + return ret;
> + }
> +
> + if (env->debugger) {
> + return RISCV_EXCP_NONE;
> + }
> +
> if (env->priv < PRV_M) {
> if (!(env->mstateen[csrno - base] & SMSTATEEN_STATEEN)) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
> }
>
> - return hmode(env, csrno);
> + return RISCV_EXCP_NONE;
> }
>
> static RISCVException hstateen(CPURISCVState *env, int csrno)
> @@ -366,6 +375,15 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + RISCVException ret = smode(env, csrno);
> + if (ret != RISCV_EXCP_NONE) {
> + return ret;
> + }
> +
> + if (env->debugger) {
> + return RISCV_EXCP_NONE;
> + }
> +
> if (env->priv < PRV_M) {
> if (!(env->mstateen[index] & SMSTATEEN_STATEEN)) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -378,7 +396,7 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
> }
> }
>
> - return smode(env, csrno);
> + return RISCV_EXCP_NONE;
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> }
>
> /* Checks if PointerMasking registers could be accessed */
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs
2023-02-28 13:45 ` [PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs Bin Meng
@ 2023-03-02 2:44 ` LIU Zhiwei
0 siblings, 0 replies; 33+ messages in thread
From: LIU Zhiwei @ 2023-03-02 2:44 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Bin Meng, Weiwei Li, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
On 2023/2/28 21:45, Bin Meng wrote:
> From: Bin Meng <bmeng@tinylab.org>
>
> At present with a debugger attached sstc CSRs can only be accssed
> when CPU is in M-mode, or configured correctly.
>
> Fix it by adjusting their predicate() routine logic so that the
> static config check comes before the run-time check, as well as
> adding a debugger check.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> ---
>
> (no changes since v1)
>
> target/riscv/csr.c | 19 ++++++++++++++-----
> 1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index a0e70f5ba0..020c3f524f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -952,6 +952,19 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
> + hmode_check = true;
> + }
> +
> + RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
> + if (ret != RISCV_EXCP_NONE) {
> + return ret;
> + }
> +
> + if (env->debugger) {
> + return RISCV_EXCP_NONE;
> + }
> +
> if (env->priv == PRV_M) {
> return RISCV_EXCP_NONE;
> }
> @@ -972,11 +985,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
> }
> }
>
> - if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
> - hmode_check = true;
> - }
> -
> - return hmode_check ? hmode(env, csrno) : smode(env, csrno);
> + return RISCV_EXCP_NONE;
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> }
>
> static RISCVException sstc_32(CPURISCVState *env, int csrno)
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 17/18] target/riscv: Drop priv level check in mseccfg predicate()
2023-02-28 13:45 ` [PATCH v2 17/18] target/riscv: Drop priv level check in mseccfg predicate() Bin Meng
@ 2023-03-02 2:45 ` LIU Zhiwei
0 siblings, 0 replies; 33+ messages in thread
From: LIU Zhiwei @ 2023-03-02 2:45 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Bin Meng, Weiwei Li, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
On 2023/2/28 21:45, Bin Meng wrote:
> From: Bin Meng <bmeng@tinylab.org>
>
> riscv_csrrw_check() already does the generic privilege level check
> hence there is no need to do the specific M-mode access check in
> the mseccfg predicate().
>
> With this change debugger can access the mseccfg CSR anytime.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> ---
>
> (no changes since v1)
>
> target/riscv/csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 020c3f524f..785f6f4d45 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -451,7 +451,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
>
> static RISCVException epmp(CPURISCVState *env, int csrno)
> {
> - if (env->priv == PRV_M && riscv_cpu_cfg(env)->epmp) {
> + if (riscv_cpu_cfg(env)->epmp) {
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> return RISCV_EXCP_NONE;
> }
>
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 18/18] target/riscv: Group all predicate() routines together
2023-02-28 13:45 ` [PATCH v2 18/18] target/riscv: Group all predicate() routines together Bin Meng
@ 2023-03-02 2:47 ` LIU Zhiwei
0 siblings, 0 replies; 33+ messages in thread
From: LIU Zhiwei @ 2023-03-02 2:47 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Bin Meng, Weiwei Li, Alistair Francis, Bin Meng,
Daniel Henrique Barboza, Palmer Dabbelt, qemu-riscv
On 2023/2/28 21:45, Bin Meng wrote:
> From: Bin Meng <bmeng@tinylab.org>
>
> Move sstc()/sstc32() to where all predicate() routines live, and
> smstateen_acc_ok() to near {read,write}_xenvcfg().
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> ---
>
> Changes in v2:
> - move smstateen_acc_ok() to near {read,write}_xenvcfg()
>
> target/riscv/csr.c | 177 ++++++++++++++++++++++-----------------------
> 1 file changed, 87 insertions(+), 90 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 785f6f4d45..3a7e0217e2 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -40,42 +40,6 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
> csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
> }
>
> -/* Predicates */
Don't remove this comment. Otherwise,
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> -#if !defined(CONFIG_USER_ONLY)
> -static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
> - uint64_t bit)
> -{
> - bool virt = riscv_cpu_virt_enabled(env);
> - RISCVCPU *cpu = env_archcpu(env);
> -
> - if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
> - return RISCV_EXCP_NONE;
> - }
> -
> - if (!(env->mstateen[index] & bit)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -
> - if (virt) {
> - if (!(env->hstateen[index] & bit)) {
> - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> - }
> -
> - if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
> - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> - }
> - }
> -
> - if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
> - if (!(env->sstateen[index] & bit)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> - }
> -
> - return RISCV_EXCP_NONE;
> -}
> -#endif
> -
> static RISCVException fs(CPURISCVState *env, int csrno)
> {
> #if !defined(CONFIG_USER_ONLY)
> @@ -399,6 +363,60 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException sstc(CPURISCVState *env, int csrno)
> +{
> + RISCVCPU *cpu = env_archcpu(env);
> + bool hmode_check = false;
> +
> + if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
> + hmode_check = true;
> + }
> +
> + RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
> + if (ret != RISCV_EXCP_NONE) {
> + return ret;
> + }
> +
> + if (env->debugger) {
> + return RISCV_EXCP_NONE;
> + }
> +
> + if (env->priv == PRV_M) {
> + return RISCV_EXCP_NONE;
> + }
> +
> + /*
> + * No need of separate function for rv32 as menvcfg stores both menvcfg
> + * menvcfgh for RV32.
> + */
> + if (!(get_field(env->mcounteren, COUNTEREN_TM) &&
> + get_field(env->menvcfg, MENVCFG_STCE))) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + if (riscv_cpu_virt_enabled(env)) {
> + if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
> + get_field(env->henvcfg, HENVCFG_STCE))) {
> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> + }
> + }
> +
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException sstc_32(CPURISCVState *env, int csrno)
> +{
> + if (riscv_cpu_mxl(env) != MXL_RV32) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + return sstc(env, csrno);
> +}
> +
> /* Checks if PointerMasking registers could be accessed */
> static RISCVException pointer_masking(CPURISCVState *env, int csrno)
> {
> @@ -943,60 +961,6 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static RISCVException sstc(CPURISCVState *env, int csrno)
> -{
> - RISCVCPU *cpu = env_archcpu(env);
> - bool hmode_check = false;
> -
> - if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -
> - if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
> - hmode_check = true;
> - }
> -
> - RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
> - if (ret != RISCV_EXCP_NONE) {
> - return ret;
> - }
> -
> - if (env->debugger) {
> - return RISCV_EXCP_NONE;
> - }
> -
> - if (env->priv == PRV_M) {
> - return RISCV_EXCP_NONE;
> - }
> -
> - /*
> - * No need of separate function for rv32 as menvcfg stores both menvcfg
> - * menvcfgh for RV32.
> - */
> - if (!(get_field(env->mcounteren, COUNTEREN_TM) &&
> - get_field(env->menvcfg, MENVCFG_STCE))) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -
> - if (riscv_cpu_virt_enabled(env)) {
> - if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
> - get_field(env->henvcfg, HENVCFG_STCE))) {
> - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> - }
> - }
> -
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException sstc_32(CPURISCVState *env, int csrno)
> -{
> - if (riscv_cpu_mxl(env) != MXL_RV32) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -
> - return sstc(env, csrno);
> -}
> -
> static RISCVException read_vstimecmp(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> @@ -1944,6 +1908,39 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException smstateen_acc_ok(CPURISCVState *env, int index,
> + uint64_t bit)
> +{
> + bool virt = riscv_cpu_virt_enabled(env);
> + RISCVCPU *cpu = env_archcpu(env);
> +
> + if (env->priv == PRV_M || !cpu->cfg.ext_smstateen) {
> + return RISCV_EXCP_NONE;
> + }
> +
> + if (!(env->mstateen[index] & bit)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + if (virt) {
> + if (!(env->hstateen[index] & bit)) {
> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> + }
> +
> + if (env->priv == PRV_U && !(env->sstateen[index] & bit)) {
> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> + }
> + }
> +
> + if (env->priv == PRV_U && riscv_has_ext(env, RVS)) {
> + if (!(env->sstateen[index] & bit)) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> + }
> +
> + return RISCV_EXCP_NONE;
> +}
> +
> static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check()
2023-02-28 10:40 ` [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() Bin Meng
2023-02-28 12:07 ` liweiwei
@ 2023-03-02 2:50 ` LIU Zhiwei
1 sibling, 0 replies; 33+ messages in thread
From: LIU Zhiwei @ 2023-03-02 2:50 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Alistair Francis, Bin Meng, Daniel Henrique Barboza,
Palmer Dabbelt, Weiwei Li, qemu-riscv
On 2023/2/28 18:40, Bin Meng wrote:
> The priority policy of riscv_csrrw_check() was once adjusted in
> commit eacaf4401956 ("target/riscv: Fix priority of csr related check in riscv_csrrw_check")
> whose commit message says the CSR existence check should come before
> the access control check, but the code changes did not agree with
> the commit message, that the predicate() check actually came after
> the read / write check.
>
> In fact this was intentional. Add some comments there so that people
> won't bother trying to change it without a solid reason.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
> Changes in v2:
> - Keep the original priority policy, instead add some comments for clarification
>
> target/riscv/csr.c | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 75a540bfcb..4cc2c6370f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3776,11 +3776,12 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> int read_only = get_field(csrno, 0xC00) == 3;
> int csr_min_priv = csr_ops[csrno].min_priv_ver;
>
> - /* ensure the CSR extension is enabled. */
> + /* ensure the CSR extension is enabled */
> if (!cpu->cfg.ext_icsr) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + /* privileged spec version check */
> if (env->priv_ver < csr_min_priv) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
> @@ -3790,10 +3791,18 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + /* read / write check */
> if (write_mask && read_only) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> + /*
> + * The predicate() not only does existence check but also does some
> + * access control check which triggers for example virtual instruction
> + * exception in some cases. When writing read-only CSRs in those cases
> + * illegal instruction exception should be triggered instead of virtual
> + * instruction exception. Hence this comes after the read / write check.
> + */
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> RISCVException ret = csr_ops[csrno].predicate(env, csrno);
> if (ret != RISCV_EXCP_NONE) {
> return ret;
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check
2023-02-28 10:40 ` [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check Bin Meng
2023-02-28 12:08 ` liweiwei
@ 2023-03-02 2:50 ` LIU Zhiwei
1 sibling, 0 replies; 33+ messages in thread
From: LIU Zhiwei @ 2023-03-02 2:50 UTC (permalink / raw)
To: Bin Meng, qemu-devel
Cc: Alistair Francis, Bin Meng, Daniel Henrique Barboza,
Palmer Dabbelt, Weiwei Li, qemu-riscv
On 2023/2/28 18:40, Bin Meng wrote:
> At present riscv_csrrw_check() checks the CSR predicate() against
> NULL and throws RISCV_EXCP_ILLEGAL_INST if it is NULL. But this is
> a pure software check, and has nothing to do with the emulation of
> the hardware behavior, thus it is inappropriate to return illegal
> instruction exception when software forgets to install the hook.
>
> Change to use g_assert() instead.
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
> Changes in v2:
> - new patch: Use assert() for the predicate() NULL check
>
> target/riscv/csr.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4cc2c6370f..cfd7ffc5c2 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3786,11 +3786,6 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> - /* check predicate */
> - if (!csr_ops[csrno].predicate) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - }
> -
> /* read / write check */
> if (write_mask && read_only) {
> return RISCV_EXCP_ILLEGAL_INST;
> @@ -3803,6 +3798,7 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
> * illegal instruction exception should be triggered instead of virtual
> * instruction exception. Hence this comes after the read / write check.
> */
> + g_assert(csr_ops[csrno].predicate != NULL);
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> RISCVException ret = csr_ops[csrno].predicate(env, csrno);
> if (ret != RISCV_EXCP_NONE) {
> return ret;
^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2023-03-02 2:51 UTC | newest]
Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-28 10:40 [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access Bin Meng
2023-02-28 10:40 ` [PATCH v2 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR Bin Meng
2023-02-28 10:40 ` [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() Bin Meng
2023-02-28 12:07 ` liweiwei
2023-03-02 2:50 ` LIU Zhiwei
2023-02-28 10:40 ` [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check Bin Meng
2023-02-28 12:08 ` liweiwei
2023-03-02 2:50 ` LIU Zhiwei
2023-02-28 10:40 ` [PATCH v2 04/18] target/riscv: gdbstub: Minor change for better readability Bin Meng
2023-02-28 10:40 ` [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled Bin Meng
2023-03-01 9:52 ` LIU Zhiwei
2023-03-01 9:55 ` Bin Meng
2023-03-01 23:43 ` Palmer Dabbelt
2023-03-02 0:30 ` Bin Meng
2023-03-02 0:58 ` Palmer Dabbelt
2023-03-02 2:43 ` LIU Zhiwei
2023-02-28 10:40 ` [PATCH v2 06/18] target/riscv: Coding style fixes in csr.c Bin Meng
2023-02-28 10:40 ` [PATCH v2 07/18] target/riscv: Use 'bool' type for read_only Bin Meng
2023-02-28 10:40 ` [PATCH v2 08/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit Bin Meng
2023-02-28 10:40 ` [PATCH v2 09/18] target/riscv: Simplify getting RISCVCPU pointer from env Bin Meng
2023-02-28 10:40 ` [PATCH v2 10/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 Bin Meng
2023-02-28 10:40 ` [PATCH v2 11/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() Bin Meng
2023-02-28 13:45 ` [PATCH v2 12/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml Bin Meng
2023-02-28 13:45 ` [PATCH v2 13/18] target/riscv: Allow debugger to access user timer and counter CSRs Bin Meng
2023-02-28 13:45 ` [PATCH v2 14/18] target/riscv: Allow debugger to access seed CSR Bin Meng
2023-02-28 13:45 ` [PATCH v2 15/18] target/riscv: Allow debugger to access {h, s}stateen CSRs Bin Meng
2023-03-02 2:44 ` [PATCH v2 15/18] target/riscv: Allow debugger to access {h,s}stateen CSRs LIU Zhiwei
2023-02-28 13:45 ` [PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs Bin Meng
2023-03-02 2:44 ` LIU Zhiwei
2023-02-28 13:45 ` [PATCH v2 17/18] target/riscv: Drop priv level check in mseccfg predicate() Bin Meng
2023-03-02 2:45 ` LIU Zhiwei
2023-02-28 13:45 ` [PATCH v2 18/18] target/riscv: Group all predicate() routines together Bin Meng
2023-03-02 2:47 ` LIU Zhiwei
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.