[PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Alexandre Ghiti]

This patchset intends to improve tlb utilization by using hugepages for
the linear mapping.

base-commit-tag: v6.2-rc7

v6:
- quiet LLVM warning by casting phys_ram_base into an unsigned long

v5:
- Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks
  Conor
- Add RB from Andrew

v4:
- Rebase on top of v6.2-rc3, as noted by Conor
- Add Acked-by Rob

v3:
- Change the comment about initrd_start VA conversion so that it fits
  ARM64 and RISCV64 (and others in the future if needed), as suggested
  by Rob

v2:
- Add a comment on why RISCV64 does not need to set initrd_start/end that
  early in the boot process, as asked by Rob

Alexandre Ghiti (2):
  riscv: Get rid of riscv_pfn_base variable
  riscv: Use PUD/P4D/PGD pages for the linear mapping

 arch/riscv/include/asm/page.h | 19 +++++++++++++++++--
 arch/riscv/mm/init.c          | 28 ++++++++++++++++++----------
 arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
 drivers/of/fdt.c              | 11 ++++++-----
 4 files changed, 57 insertions(+), 17 deletions(-)

--
2.37.2

[PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Alexandre Ghiti]

This patchset intends to improve tlb utilization by using hugepages for
the linear mapping.

base-commit-tag: v6.2-rc7

v6:
- quiet LLVM warning by casting phys_ram_base into an unsigned long

v5:
- Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks
  Conor
- Add RB from Andrew

v4:
- Rebase on top of v6.2-rc3, as noted by Conor
- Add Acked-by Rob

v3:
- Change the comment about initrd_start VA conversion so that it fits
  ARM64 and RISCV64 (and others in the future if needed), as suggested
  by Rob

v2:
- Add a comment on why RISCV64 does not need to set initrd_start/end that
  early in the boot process, as asked by Rob

Alexandre Ghiti (2):
  riscv: Get rid of riscv_pfn_base variable
  riscv: Use PUD/P4D/PGD pages for the linear mapping

 arch/riscv/include/asm/page.h | 19 +++++++++++++++++--
 arch/riscv/mm/init.c          | 28 ++++++++++++++++++----------
 arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
 drivers/of/fdt.c              | 11 ++++++-----
 4 files changed, 57 insertions(+), 17 deletions(-)

--
2.37.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v6 1/2] riscv: Get rid of riscv_pfn_base variable

[Alexandre Ghiti]

Use directly phys_ram_base instead, riscv_pfn_base is just the pfn of
the address contained in phys_ram_base.

Even if there is no functional change intended in this patch, actually
setting phys_ram_base that early changes the behaviour of
kernel_mapping_pa_to_va during the early boot: phys_ram_base used to be
zero before this patch and now it is set to the physical start address of
the kernel. But it does not break the conversion of a kernel physical
address into a virtual address since kernel_mapping_pa_to_va should only
be used on kernel physical addresses, i.e. addresses greater than the
physical start address of the kernel.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 arch/riscv/include/asm/page.h | 3 +--
 arch/riscv/mm/init.c          | 6 +-----
 2 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
index 9f432c1b5289..926af5a3d02e 100644
--- a/arch/riscv/include/asm/page.h
+++ b/arch/riscv/include/asm/page.h
@@ -91,8 +91,7 @@ typedef struct page *pgtable_t;
 #endif
 
 #ifdef CONFIG_MMU
-extern unsigned long riscv_pfn_base;
-#define ARCH_PFN_OFFSET		(riscv_pfn_base)
+#define ARCH_PFN_OFFSET		(PFN_DOWN((unsigned long)phys_ram_base))
 #else
 #define ARCH_PFN_OFFSET		(PAGE_OFFSET >> PAGE_SHIFT)
 #endif /* CONFIG_MMU */
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 04d20e41894e..bef639fa330b 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -271,9 +271,6 @@ static void __init setup_bootmem(void)
 #ifdef CONFIG_MMU
 struct pt_alloc_ops pt_ops __initdata;
 
-unsigned long riscv_pfn_base __ro_after_init;
-EXPORT_SYMBOL(riscv_pfn_base);
-
 pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_bss;
 pgd_t trampoline_pg_dir[PTRS_PER_PGD] __page_aligned_bss;
 static pte_t fixmap_pte[PTRS_PER_PTE] __page_aligned_bss;
@@ -285,7 +282,6 @@ static pmd_t __maybe_unused early_dtb_pmd[PTRS_PER_PMD] __initdata __aligned(PAG
 
 #ifdef CONFIG_XIP_KERNEL
 #define pt_ops			(*(struct pt_alloc_ops *)XIP_FIXUP(&pt_ops))
-#define riscv_pfn_base         (*(unsigned long  *)XIP_FIXUP(&riscv_pfn_base))
 #define trampoline_pg_dir      ((pgd_t *)XIP_FIXUP(trampoline_pg_dir))
 #define fixmap_pte             ((pte_t *)XIP_FIXUP(fixmap_pte))
 #define early_pg_dir           ((pgd_t *)XIP_FIXUP(early_pg_dir))
@@ -1009,7 +1005,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
 	kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr;
 	kernel_map.va_kernel_pa_offset = kernel_map.virt_addr - kernel_map.phys_addr;
 
-	riscv_pfn_base = PFN_DOWN(kernel_map.phys_addr);
+	phys_ram_base = kernel_map.phys_addr;
 
 	/*
 	 * The default maximal physical memory size is KERN_VIRT_SIZE for 32-bit
-- 
2.37.2

[PATCH v6 1/2] riscv: Get rid of riscv_pfn_base variable

[Alexandre Ghiti]

Use directly phys_ram_base instead, riscv_pfn_base is just the pfn of
the address contained in phys_ram_base.

Even if there is no functional change intended in this patch, actually
setting phys_ram_base that early changes the behaviour of
kernel_mapping_pa_to_va during the early boot: phys_ram_base used to be
zero before this patch and now it is set to the physical start address of
the kernel. But it does not break the conversion of a kernel physical
address into a virtual address since kernel_mapping_pa_to_va should only
be used on kernel physical addresses, i.e. addresses greater than the
physical start address of the kernel.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 arch/riscv/include/asm/page.h | 3 +--
 arch/riscv/mm/init.c          | 6 +-----
 2 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
index 9f432c1b5289..926af5a3d02e 100644
--- a/arch/riscv/include/asm/page.h
+++ b/arch/riscv/include/asm/page.h
@@ -91,8 +91,7 @@ typedef struct page *pgtable_t;
 #endif
 
 #ifdef CONFIG_MMU
-extern unsigned long riscv_pfn_base;
-#define ARCH_PFN_OFFSET		(riscv_pfn_base)
+#define ARCH_PFN_OFFSET		(PFN_DOWN((unsigned long)phys_ram_base))
 #else
 #define ARCH_PFN_OFFSET		(PAGE_OFFSET >> PAGE_SHIFT)
 #endif /* CONFIG_MMU */
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 04d20e41894e..bef639fa330b 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -271,9 +271,6 @@ static void __init setup_bootmem(void)
 #ifdef CONFIG_MMU
 struct pt_alloc_ops pt_ops __initdata;
 
-unsigned long riscv_pfn_base __ro_after_init;
-EXPORT_SYMBOL(riscv_pfn_base);
-
 pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_bss;
 pgd_t trampoline_pg_dir[PTRS_PER_PGD] __page_aligned_bss;
 static pte_t fixmap_pte[PTRS_PER_PTE] __page_aligned_bss;
@@ -285,7 +282,6 @@ static pmd_t __maybe_unused early_dtb_pmd[PTRS_PER_PMD] __initdata __aligned(PAG
 
 #ifdef CONFIG_XIP_KERNEL
 #define pt_ops			(*(struct pt_alloc_ops *)XIP_FIXUP(&pt_ops))
-#define riscv_pfn_base         (*(unsigned long  *)XIP_FIXUP(&riscv_pfn_base))
 #define trampoline_pg_dir      ((pgd_t *)XIP_FIXUP(trampoline_pg_dir))
 #define fixmap_pte             ((pte_t *)XIP_FIXUP(fixmap_pte))
 #define early_pg_dir           ((pgd_t *)XIP_FIXUP(early_pg_dir))
@@ -1009,7 +1005,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
 	kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr;
 	kernel_map.va_kernel_pa_offset = kernel_map.virt_addr - kernel_map.phys_addr;
 
-	riscv_pfn_base = PFN_DOWN(kernel_map.phys_addr);
+	phys_ram_base = kernel_map.phys_addr;
 
 	/*
 	 * The default maximal physical memory size is KERN_VIRT_SIZE for 32-bit
-- 
2.37.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v6 2/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Alexandre Ghiti]

During the early page table creation, we used to set the mapping for
PAGE_OFFSET to the kernel load address: but the kernel load address is
always offseted by PMD_SIZE which makes it impossible to use PUD/P4D/PGD
pages as this physical address is not aligned on PUD/P4D/PGD size (whereas
PAGE_OFFSET is).

But actually we don't have to establish this mapping (ie set va_pa_offset)
that early in the boot process because:

- first, setup_vm installs a temporary kernel mapping and among other
  things, discovers the system memory,
- then, setup_vm_final creates the final kernel mapping and takes
  advantage of the discovered system memory to create the linear
  mapping.

During the first phase, we don't know the start of the system memory and
then until the second phase is finished, we can't use the linear mapping at
all and phys_to_virt/virt_to_phys translations must not be used because it
would result in a different translation from the 'real' one once the final
mapping is installed.

So here we simply delay the initialization of va_pa_offset to after the
system memory discovery. But to make sure noone uses the linear mapping
before, we add some guard in the DEBUG_VIRTUAL config.

Finally we can use PUD/P4D/PGD hugepages when possible, which will result
in a better TLB utilization.

Note that we rely on the firmware to protect itself using PMP.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Acked-by: Rob Herring <robh@kernel.org> # DT bits
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 arch/riscv/include/asm/page.h | 16 ++++++++++++++++
 arch/riscv/mm/init.c          | 24 ++++++++++++++++++------
 arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
 drivers/of/fdt.c              | 11 ++++++-----
 4 files changed, 56 insertions(+), 11 deletions(-)

diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
index 926af5a3d02e..f670466b84a8 100644
--- a/arch/riscv/include/asm/page.h
+++ b/arch/riscv/include/asm/page.h
@@ -90,6 +90,14 @@ typedef struct page *pgtable_t;
 #define PTE_FMT "%08lx"
 #endif
 
+#ifdef CONFIG_64BIT
+/*
+ * We override this value as its generic definition uses __pa too early in
+ * the boot process (before kernel_map.va_pa_offset is set).
+ */
+#define MIN_MEMBLOCK_ADDR      0
+#endif
+
 #ifdef CONFIG_MMU
 #define ARCH_PFN_OFFSET		(PFN_DOWN((unsigned long)phys_ram_base))
 #else
@@ -121,7 +129,11 @@ extern phys_addr_t phys_ram_base;
 #define is_linear_mapping(x)	\
 	((x) >= PAGE_OFFSET && (!IS_ENABLED(CONFIG_64BIT) || (x) < PAGE_OFFSET + KERN_VIRT_SIZE))
 
+#ifndef CONFIG_DEBUG_VIRTUAL
 #define linear_mapping_pa_to_va(x)	((void *)((unsigned long)(x) + kernel_map.va_pa_offset))
+#else
+void *linear_mapping_pa_to_va(unsigned long x);
+#endif
 #define kernel_mapping_pa_to_va(y)	({					\
 	unsigned long _y = (unsigned long)(y);					\
 	(IS_ENABLED(CONFIG_XIP_KERNEL) && _y < phys_ram_base) ?			\
@@ -130,7 +142,11 @@ extern phys_addr_t phys_ram_base;
 	})
 #define __pa_to_va_nodebug(x)		linear_mapping_pa_to_va(x)
 
+#ifndef CONFIG_DEBUG_VIRTUAL
 #define linear_mapping_va_to_pa(x)	((unsigned long)(x) - kernel_map.va_pa_offset)
+#else
+phys_addr_t linear_mapping_va_to_pa(unsigned long x);
+#endif
 #define kernel_mapping_va_to_pa(y) ({						\
 	unsigned long _y = (unsigned long)(y);					\
 	(IS_ENABLED(CONFIG_XIP_KERNEL) && _y < kernel_map.virt_addr + XIP_OFFSET) ? \
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index bef639fa330b..fb19c80ac0c4 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -213,6 +213,13 @@ static void __init setup_bootmem(void)
 	phys_ram_end = memblock_end_of_DRAM();
 	if (!IS_ENABLED(CONFIG_XIP_KERNEL))
 		phys_ram_base = memblock_start_of_DRAM();
+
+	/*
+	 * Any use of __va/__pa before this point is wrong as we did not know the
+	 * start of DRAM before.
+	 */
+	kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base;
+
 	/*
 	 * memblock allocator is not aware of the fact that last 4K bytes of
 	 * the addressable memory can not be mapped because of IS_ERR_VALUE
@@ -667,9 +674,16 @@ void __init create_pgd_mapping(pgd_t *pgdp,
 
 static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size)
 {
-	/* Upgrade to PMD_SIZE mappings whenever possible */
-	base &= PMD_SIZE - 1;
-	if (!base && size >= PMD_SIZE)
+	if (!(base & (PGDIR_SIZE - 1)) && size >= PGDIR_SIZE)
+		return PGDIR_SIZE;
+
+	if (!(base & (P4D_SIZE - 1)) && size >= P4D_SIZE)
+		return P4D_SIZE;
+
+	if (!(base & (PUD_SIZE - 1)) && size >= PUD_SIZE)
+		return PUD_SIZE;
+
+	if (!(base & (PMD_SIZE - 1)) && size >= PMD_SIZE)
 		return PMD_SIZE;
 
 	return PAGE_SIZE;
@@ -1002,11 +1016,9 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
 	set_satp_mode(dtb_pa);
 #endif
 
-	kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr;
+	kernel_map.va_pa_offset = 0UL;
 	kernel_map.va_kernel_pa_offset = kernel_map.virt_addr - kernel_map.phys_addr;
 
-	phys_ram_base = kernel_map.phys_addr;
-
 	/*
 	 * The default maximal physical memory size is KERN_VIRT_SIZE for 32-bit
 	 * kernel, whereas for 64-bit kernel, the end of the virtual address
diff --git a/arch/riscv/mm/physaddr.c b/arch/riscv/mm/physaddr.c
index 9b18bda74154..18706f457da7 100644
--- a/arch/riscv/mm/physaddr.c
+++ b/arch/riscv/mm/physaddr.c
@@ -33,3 +33,19 @@ phys_addr_t __phys_addr_symbol(unsigned long x)
 	return __va_to_pa_nodebug(x);
 }
 EXPORT_SYMBOL(__phys_addr_symbol);
+
+phys_addr_t linear_mapping_va_to_pa(unsigned long x)
+{
+	BUG_ON(!kernel_map.va_pa_offset);
+
+	return ((unsigned long)(x) - kernel_map.va_pa_offset);
+}
+EXPORT_SYMBOL(linear_mapping_va_to_pa);
+
+void *linear_mapping_pa_to_va(unsigned long x)
+{
+	BUG_ON(!kernel_map.va_pa_offset);
+
+	return ((void *)((unsigned long)(x) + kernel_map.va_pa_offset));
+}
+EXPORT_SYMBOL(linear_mapping_pa_to_va);
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index d1a68b6d03b3..d14735a81301 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -887,12 +887,13 @@ const void * __init of_flat_dt_match_machine(const void *default_match,
 static void __early_init_dt_declare_initrd(unsigned long start,
 					   unsigned long end)
 {
-	/* ARM64 would cause a BUG to occur here when CONFIG_DEBUG_VM is
-	 * enabled since __va() is called too early. ARM64 does make use
-	 * of phys_initrd_start/phys_initrd_size so we can skip this
-	 * conversion.
+	/*
+	 * __va() is not yet available this early on some platforms. In that
+	 * case, the platform uses phys_initrd_start/phys_initrd_size instead
+	 * and does the VA conversion itself.
 	 */
-	if (!IS_ENABLED(CONFIG_ARM64)) {
+	if (!IS_ENABLED(CONFIG_ARM64) &&
+	    !(IS_ENABLED(CONFIG_RISCV) && IS_ENABLED(CONFIG_64BIT))) {
 		initrd_start = (unsigned long)__va(start);
 		initrd_end = (unsigned long)__va(end);
 		initrd_below_start_ok = 1;
-- 
2.37.2

[PATCH v6 2/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Alexandre Ghiti]

During the early page table creation, we used to set the mapping for
PAGE_OFFSET to the kernel load address: but the kernel load address is
always offseted by PMD_SIZE which makes it impossible to use PUD/P4D/PGD
pages as this physical address is not aligned on PUD/P4D/PGD size (whereas
PAGE_OFFSET is).

But actually we don't have to establish this mapping (ie set va_pa_offset)
that early in the boot process because:

- first, setup_vm installs a temporary kernel mapping and among other
  things, discovers the system memory,
- then, setup_vm_final creates the final kernel mapping and takes
  advantage of the discovered system memory to create the linear
  mapping.

During the first phase, we don't know the start of the system memory and
then until the second phase is finished, we can't use the linear mapping at
all and phys_to_virt/virt_to_phys translations must not be used because it
would result in a different translation from the 'real' one once the final
mapping is installed.

So here we simply delay the initialization of va_pa_offset to after the
system memory discovery. But to make sure noone uses the linear mapping
before, we add some guard in the DEBUG_VIRTUAL config.

Finally we can use PUD/P4D/PGD hugepages when possible, which will result
in a better TLB utilization.

Note that we rely on the firmware to protect itself using PMP.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Acked-by: Rob Herring <robh@kernel.org> # DT bits
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 arch/riscv/include/asm/page.h | 16 ++++++++++++++++
 arch/riscv/mm/init.c          | 24 ++++++++++++++++++------
 arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
 drivers/of/fdt.c              | 11 ++++++-----
 4 files changed, 56 insertions(+), 11 deletions(-)

diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
index 926af5a3d02e..f670466b84a8 100644
--- a/arch/riscv/include/asm/page.h
+++ b/arch/riscv/include/asm/page.h
@@ -90,6 +90,14 @@ typedef struct page *pgtable_t;
 #define PTE_FMT "%08lx"
 #endif
 
+#ifdef CONFIG_64BIT
+/*
+ * We override this value as its generic definition uses __pa too early in
+ * the boot process (before kernel_map.va_pa_offset is set).
+ */
+#define MIN_MEMBLOCK_ADDR      0
+#endif
+
 #ifdef CONFIG_MMU
 #define ARCH_PFN_OFFSET		(PFN_DOWN((unsigned long)phys_ram_base))
 #else
@@ -121,7 +129,11 @@ extern phys_addr_t phys_ram_base;
 #define is_linear_mapping(x)	\
 	((x) >= PAGE_OFFSET && (!IS_ENABLED(CONFIG_64BIT) || (x) < PAGE_OFFSET + KERN_VIRT_SIZE))
 
+#ifndef CONFIG_DEBUG_VIRTUAL
 #define linear_mapping_pa_to_va(x)	((void *)((unsigned long)(x) + kernel_map.va_pa_offset))
+#else
+void *linear_mapping_pa_to_va(unsigned long x);
+#endif
 #define kernel_mapping_pa_to_va(y)	({					\
 	unsigned long _y = (unsigned long)(y);					\
 	(IS_ENABLED(CONFIG_XIP_KERNEL) && _y < phys_ram_base) ?			\
@@ -130,7 +142,11 @@ extern phys_addr_t phys_ram_base;
 	})
 #define __pa_to_va_nodebug(x)		linear_mapping_pa_to_va(x)
 
+#ifndef CONFIG_DEBUG_VIRTUAL
 #define linear_mapping_va_to_pa(x)	((unsigned long)(x) - kernel_map.va_pa_offset)
+#else
+phys_addr_t linear_mapping_va_to_pa(unsigned long x);
+#endif
 #define kernel_mapping_va_to_pa(y) ({						\
 	unsigned long _y = (unsigned long)(y);					\
 	(IS_ENABLED(CONFIG_XIP_KERNEL) && _y < kernel_map.virt_addr + XIP_OFFSET) ? \
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index bef639fa330b..fb19c80ac0c4 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -213,6 +213,13 @@ static void __init setup_bootmem(void)
 	phys_ram_end = memblock_end_of_DRAM();
 	if (!IS_ENABLED(CONFIG_XIP_KERNEL))
 		phys_ram_base = memblock_start_of_DRAM();
+
+	/*
+	 * Any use of __va/__pa before this point is wrong as we did not know the
+	 * start of DRAM before.
+	 */
+	kernel_map.va_pa_offset = PAGE_OFFSET - phys_ram_base;
+
 	/*
 	 * memblock allocator is not aware of the fact that last 4K bytes of
 	 * the addressable memory can not be mapped because of IS_ERR_VALUE
@@ -667,9 +674,16 @@ void __init create_pgd_mapping(pgd_t *pgdp,
 
 static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size)
 {
-	/* Upgrade to PMD_SIZE mappings whenever possible */
-	base &= PMD_SIZE - 1;
-	if (!base && size >= PMD_SIZE)
+	if (!(base & (PGDIR_SIZE - 1)) && size >= PGDIR_SIZE)
+		return PGDIR_SIZE;
+
+	if (!(base & (P4D_SIZE - 1)) && size >= P4D_SIZE)
+		return P4D_SIZE;
+
+	if (!(base & (PUD_SIZE - 1)) && size >= PUD_SIZE)
+		return PUD_SIZE;
+
+	if (!(base & (PMD_SIZE - 1)) && size >= PMD_SIZE)
 		return PMD_SIZE;
 
 	return PAGE_SIZE;
@@ -1002,11 +1016,9 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
 	set_satp_mode(dtb_pa);
 #endif
 
-	kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr;
+	kernel_map.va_pa_offset = 0UL;
 	kernel_map.va_kernel_pa_offset = kernel_map.virt_addr - kernel_map.phys_addr;
 
-	phys_ram_base = kernel_map.phys_addr;
-
 	/*
 	 * The default maximal physical memory size is KERN_VIRT_SIZE for 32-bit
 	 * kernel, whereas for 64-bit kernel, the end of the virtual address
diff --git a/arch/riscv/mm/physaddr.c b/arch/riscv/mm/physaddr.c
index 9b18bda74154..18706f457da7 100644
--- a/arch/riscv/mm/physaddr.c
+++ b/arch/riscv/mm/physaddr.c
@@ -33,3 +33,19 @@ phys_addr_t __phys_addr_symbol(unsigned long x)
 	return __va_to_pa_nodebug(x);
 }
 EXPORT_SYMBOL(__phys_addr_symbol);
+
+phys_addr_t linear_mapping_va_to_pa(unsigned long x)
+{
+	BUG_ON(!kernel_map.va_pa_offset);
+
+	return ((unsigned long)(x) - kernel_map.va_pa_offset);
+}
+EXPORT_SYMBOL(linear_mapping_va_to_pa);
+
+void *linear_mapping_pa_to_va(unsigned long x)
+{
+	BUG_ON(!kernel_map.va_pa_offset);
+
+	return ((void *)((unsigned long)(x) + kernel_map.va_pa_offset));
+}
+EXPORT_SYMBOL(linear_mapping_pa_to_va);
diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
index d1a68b6d03b3..d14735a81301 100644
--- a/drivers/of/fdt.c
+++ b/drivers/of/fdt.c
@@ -887,12 +887,13 @@ const void * __init of_flat_dt_match_machine(const void *default_match,
 static void __early_init_dt_declare_initrd(unsigned long start,
 					   unsigned long end)
 {
-	/* ARM64 would cause a BUG to occur here when CONFIG_DEBUG_VM is
-	 * enabled since __va() is called too early. ARM64 does make use
-	 * of phys_initrd_start/phys_initrd_size so we can skip this
-	 * conversion.
+	/*
+	 * __va() is not yet available this early on some platforms. In that
+	 * case, the platform uses phys_initrd_start/phys_initrd_size instead
+	 * and does the VA conversion itself.
 	 */
-	if (!IS_ENABLED(CONFIG_ARM64)) {
+	if (!IS_ENABLED(CONFIG_ARM64) &&
+	    !(IS_ENABLED(CONFIG_RISCV) && IS_ENABLED(CONFIG_64BIT))) {
 		initrd_start = (unsigned long)__va(start);
 		initrd_end = (unsigned long)__va(end);
 		initrd_below_start_ok = 1;
-- 
2.37.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Anup Patel]

On Wed, Mar 1, 2023 at 1:56 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
>
> This patchset intends to improve tlb utilization by using hugepages for
> the linear mapping.
>
> base-commit-tag: v6.2-rc7
>
> v6:
> - quiet LLVM warning by casting phys_ram_base into an unsigned long
>
> v5:
> - Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks
>   Conor
> - Add RB from Andrew
>
> v4:
> - Rebase on top of v6.2-rc3, as noted by Conor
> - Add Acked-by Rob
>
> v3:
> - Change the comment about initrd_start VA conversion so that it fits
>   ARM64 and RISCV64 (and others in the future if needed), as suggested
>   by Rob
>
> v2:
> - Add a comment on why RISCV64 does not need to set initrd_start/end that
>   early in the boot process, as asked by Rob
>
> Alexandre Ghiti (2):
>   riscv: Get rid of riscv_pfn_base variable
>   riscv: Use PUD/P4D/PGD pages for the linear mapping

I tried this series but it is getting stuck after reaching user space.

Does this series require some other dependent patches ?

Regards,
Anup

>
>  arch/riscv/include/asm/page.h | 19 +++++++++++++++++--
>  arch/riscv/mm/init.c          | 28 ++++++++++++++++++----------
>  arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
>  drivers/of/fdt.c              | 11 ++++++-----
>  4 files changed, 57 insertions(+), 17 deletions(-)
>
> --
> 2.37.2
>

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Anup Patel]

On Wed, Mar 1, 2023 at 1:56 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
>
> This patchset intends to improve tlb utilization by using hugepages for
> the linear mapping.
>
> base-commit-tag: v6.2-rc7
>
> v6:
> - quiet LLVM warning by casting phys_ram_base into an unsigned long
>
> v5:
> - Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks
>   Conor
> - Add RB from Andrew
>
> v4:
> - Rebase on top of v6.2-rc3, as noted by Conor
> - Add Acked-by Rob
>
> v3:
> - Change the comment about initrd_start VA conversion so that it fits
>   ARM64 and RISCV64 (and others in the future if needed), as suggested
>   by Rob
>
> v2:
> - Add a comment on why RISCV64 does not need to set initrd_start/end that
>   early in the boot process, as asked by Rob
>
> Alexandre Ghiti (2):
>   riscv: Get rid of riscv_pfn_base variable
>   riscv: Use PUD/P4D/PGD pages for the linear mapping

I tried this series but it is getting stuck after reaching user space.

Does this series require some other dependent patches ?

Regards,
Anup

>
>  arch/riscv/include/asm/page.h | 19 +++++++++++++++++--
>  arch/riscv/mm/init.c          | 28 ++++++++++++++++++----------
>  arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
>  drivers/of/fdt.c              | 11 ++++++-----
>  4 files changed, 57 insertions(+), 17 deletions(-)
>
> --
> 2.37.2
>

Re: [PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Alexandre Ghiti]

Hi Anup,

On Mon, Mar 6, 2023 at 5:33 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> On Wed, Mar 1, 2023 at 1:56 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> >
> > This patchset intends to improve tlb utilization by using hugepages for
> > the linear mapping.
> >
> > base-commit-tag: v6.2-rc7
> >
> > v6:
> > - quiet LLVM warning by casting phys_ram_base into an unsigned long
> >
> > v5:
> > - Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks
> >   Conor
> > - Add RB from Andrew
> >
> > v4:
> > - Rebase on top of v6.2-rc3, as noted by Conor
> > - Add Acked-by Rob
> >
> > v3:
> > - Change the comment about initrd_start VA conversion so that it fits
> >   ARM64 and RISCV64 (and others in the future if needed), as suggested
> >   by Rob
> >
> > v2:
> > - Add a comment on why RISCV64 does not need to set initrd_start/end that
> >   early in the boot process, as asked by Rob
> >
> > Alexandre Ghiti (2):
> >   riscv: Get rid of riscv_pfn_base variable
> >   riscv: Use PUD/P4D/PGD pages for the linear mapping
>
> I tried this series but it is getting stuck after reaching user space.
>
> Does this series require some other dependent patches ?

No it should not. Let me take a look: what's your config and the base commit?

>
> Regards,
> Anup
>
> >
> >  arch/riscv/include/asm/page.h | 19 +++++++++++++++++--
> >  arch/riscv/mm/init.c          | 28 ++++++++++++++++++----------
> >  arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
> >  drivers/of/fdt.c              | 11 ++++++-----
> >  4 files changed, 57 insertions(+), 17 deletions(-)
> >
> > --
> > 2.37.2
> >

Re: [PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Alexandre Ghiti]

Hi Anup,

On Mon, Mar 6, 2023 at 5:33 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> On Wed, Mar 1, 2023 at 1:56 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> >
> > This patchset intends to improve tlb utilization by using hugepages for
> > the linear mapping.
> >
> > base-commit-tag: v6.2-rc7
> >
> > v6:
> > - quiet LLVM warning by casting phys_ram_base into an unsigned long
> >
> > v5:
> > - Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks
> >   Conor
> > - Add RB from Andrew
> >
> > v4:
> > - Rebase on top of v6.2-rc3, as noted by Conor
> > - Add Acked-by Rob
> >
> > v3:
> > - Change the comment about initrd_start VA conversion so that it fits
> >   ARM64 and RISCV64 (and others in the future if needed), as suggested
> >   by Rob
> >
> > v2:
> > - Add a comment on why RISCV64 does not need to set initrd_start/end that
> >   early in the boot process, as asked by Rob
> >
> > Alexandre Ghiti (2):
> >   riscv: Get rid of riscv_pfn_base variable
> >   riscv: Use PUD/P4D/PGD pages for the linear mapping
>
> I tried this series but it is getting stuck after reaching user space.
>
> Does this series require some other dependent patches ?

No it should not. Let me take a look: what's your config and the base commit?

>
> Regards,
> Anup
>
> >
> >  arch/riscv/include/asm/page.h | 19 +++++++++++++++++--
> >  arch/riscv/mm/init.c          | 28 ++++++++++++++++++----------
> >  arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
> >  drivers/of/fdt.c              | 11 ++++++-----
> >  4 files changed, 57 insertions(+), 17 deletions(-)
> >
> > --
> > 2.37.2
> >

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Anup Patel]

Hi Alex,

On Tue, Mar 7, 2023 at 12:22 AM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
>
> Hi Anup,
>
> On Mon, Mar 6, 2023 at 5:33 PM Anup Patel <apatel@ventanamicro.com> wrote:
> >
> > On Wed, Mar 1, 2023 at 1:56 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> > >
> > > This patchset intends to improve tlb utilization by using hugepages for
> > > the linear mapping.
> > >
> > > base-commit-tag: v6.2-rc7
> > >
> > > v6:
> > > - quiet LLVM warning by casting phys_ram_base into an unsigned long
> > >
> > > v5:
> > > - Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks
> > >   Conor
> > > - Add RB from Andrew
> > >
> > > v4:
> > > - Rebase on top of v6.2-rc3, as noted by Conor
> > > - Add Acked-by Rob
> > >
> > > v3:
> > > - Change the comment about initrd_start VA conversion so that it fits
> > >   ARM64 and RISCV64 (and others in the future if needed), as suggested
> > >   by Rob
> > >
> > > v2:
> > > - Add a comment on why RISCV64 does not need to set initrd_start/end that
> > >   early in the boot process, as asked by Rob
> > >
> > > Alexandre Ghiti (2):
> > >   riscv: Get rid of riscv_pfn_base variable
> > >   riscv: Use PUD/P4D/PGD pages for the linear mapping
> >
> > I tried this series but it is getting stuck after reaching user space.
> >
> > Does this series require some other dependent patches ?
>
> No it should not. Let me take a look: what's your config and the base commit?

Please try the alexghiti_test branch at:
https://github.com/avpatel/linux.git

Compile the kernel with defconfig and launch QEMU as follows:
qemu-system-riscv64 -M virt -m 1G -nographic -bios
opensbi/build/platform/generic/firmware/fw_jump.bin -kernel
./build-riscv64/arch/riscv/boot/Image -append "root=/dev/ram rw
console=ttyS0 earlycon" -initrd ./rootfs_riscv64.img

In the above command, rootfs_riscv64.img is a busybox based rootfs.

Regards,
Anup

>
> >
> > Regards,
> > Anup
> >
> > >
> > >  arch/riscv/include/asm/page.h | 19 +++++++++++++++++--
> > >  arch/riscv/mm/init.c          | 28 ++++++++++++++++++----------
> > >  arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
> > >  drivers/of/fdt.c              | 11 ++++++-----
> > >  4 files changed, 57 insertions(+), 17 deletions(-)
> > >
> > > --
> > > 2.37.2
> > >

Re: [PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Anup Patel]

Hi Alex,

On Tue, Mar 7, 2023 at 12:22 AM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
>
> Hi Anup,
>
> On Mon, Mar 6, 2023 at 5:33 PM Anup Patel <apatel@ventanamicro.com> wrote:
> >
> > On Wed, Mar 1, 2023 at 1:56 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> > >
> > > This patchset intends to improve tlb utilization by using hugepages for
> > > the linear mapping.
> > >
> > > base-commit-tag: v6.2-rc7
> > >
> > > v6:
> > > - quiet LLVM warning by casting phys_ram_base into an unsigned long
> > >
> > > v5:
> > > - Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks
> > >   Conor
> > > - Add RB from Andrew
> > >
> > > v4:
> > > - Rebase on top of v6.2-rc3, as noted by Conor
> > > - Add Acked-by Rob
> > >
> > > v3:
> > > - Change the comment about initrd_start VA conversion so that it fits
> > >   ARM64 and RISCV64 (and others in the future if needed), as suggested
> > >   by Rob
> > >
> > > v2:
> > > - Add a comment on why RISCV64 does not need to set initrd_start/end that
> > >   early in the boot process, as asked by Rob
> > >
> > > Alexandre Ghiti (2):
> > >   riscv: Get rid of riscv_pfn_base variable
> > >   riscv: Use PUD/P4D/PGD pages for the linear mapping
> >
> > I tried this series but it is getting stuck after reaching user space.
> >
> > Does this series require some other dependent patches ?
>
> No it should not. Let me take a look: what's your config and the base commit?

Please try the alexghiti_test branch at:
https://github.com/avpatel/linux.git

Compile the kernel with defconfig and launch QEMU as follows:
qemu-system-riscv64 -M virt -m 1G -nographic -bios
opensbi/build/platform/generic/firmware/fw_jump.bin -kernel
./build-riscv64/arch/riscv/boot/Image -append "root=/dev/ram rw
console=ttyS0 earlycon" -initrd ./rootfs_riscv64.img

In the above command, rootfs_riscv64.img is a busybox based rootfs.

Regards,
Anup

>
> >
> > Regards,
> > Anup
> >
> > >
> > >  arch/riscv/include/asm/page.h | 19 +++++++++++++++++--
> > >  arch/riscv/mm/init.c          | 28 ++++++++++++++++++----------
> > >  arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
> > >  drivers/of/fdt.c              | 11 ++++++-----
> > >  4 files changed, 57 insertions(+), 17 deletions(-)
> > >
> > > --
> > > 2.37.2
> > >

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Alexandre Ghiti]

On Tue, Mar 7, 2023 at 2:19 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> Hi Alex,
>
> On Tue, Mar 7, 2023 at 12:22 AM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> >
> > Hi Anup,
> >
> > On Mon, Mar 6, 2023 at 5:33 PM Anup Patel <apatel@ventanamicro.com> wrote:
> > >
> > > On Wed, Mar 1, 2023 at 1:56 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> > > >
> > > > This patchset intends to improve tlb utilization by using hugepages for
> > > > the linear mapping.
> > > >
> > > > base-commit-tag: v6.2-rc7
> > > >
> > > > v6:
> > > > - quiet LLVM warning by casting phys_ram_base into an unsigned long
> > > >
> > > > v5:
> > > > - Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks
> > > >   Conor
> > > > - Add RB from Andrew
> > > >
> > > > v4:
> > > > - Rebase on top of v6.2-rc3, as noted by Conor
> > > > - Add Acked-by Rob
> > > >
> > > > v3:
> > > > - Change the comment about initrd_start VA conversion so that it fits
> > > >   ARM64 and RISCV64 (and others in the future if needed), as suggested
> > > >   by Rob
> > > >
> > > > v2:
> > > > - Add a comment on why RISCV64 does not need to set initrd_start/end that
> > > >   early in the boot process, as asked by Rob
> > > >
> > > > Alexandre Ghiti (2):
> > > >   riscv: Get rid of riscv_pfn_base variable
> > > >   riscv: Use PUD/P4D/PGD pages for the linear mapping
> > >
> > > I tried this series but it is getting stuck after reaching user space.
> > >
> > > Does this series require some other dependent patches ?
> >
> > No it should not. Let me take a look: what's your config and the base commit?
>
> Please try the alexghiti_test branch at:
> https://github.com/avpatel/linux.git
>
> Compile the kernel with defconfig and launch QEMU as follows:
> qemu-system-riscv64 -M virt -m 1G -nographic -bios
> opensbi/build/platform/generic/firmware/fw_jump.bin -kernel
> ./build-riscv64/arch/riscv/boot/Image -append "root=/dev/ram rw
> console=ttyS0 earlycon" -initrd ./rootfs_riscv64.img
>
> In the above command, rootfs_riscv64.img is a busybox based rootfs.

Ok I can reproduce the problem. I'll debug that a bit further but
increasing memory allows booting to userspace.

>
> Regards,
> Anup
>
> >
> > >
> > > Regards,
> > > Anup
> > >
> > > >
> > > >  arch/riscv/include/asm/page.h | 19 +++++++++++++++++--
> > > >  arch/riscv/mm/init.c          | 28 ++++++++++++++++++----------
> > > >  arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
> > > >  drivers/of/fdt.c              | 11 ++++++-----
> > > >  4 files changed, 57 insertions(+), 17 deletions(-)
> > > >
> > > > --
> > > > 2.37.2
> > > >

Re: [PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Alexandre Ghiti]

On Tue, Mar 7, 2023 at 2:19 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> Hi Alex,
>
> On Tue, Mar 7, 2023 at 12:22 AM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> >
> > Hi Anup,
> >
> > On Mon, Mar 6, 2023 at 5:33 PM Anup Patel <apatel@ventanamicro.com> wrote:
> > >
> > > On Wed, Mar 1, 2023 at 1:56 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> > > >
> > > > This patchset intends to improve tlb utilization by using hugepages for
> > > > the linear mapping.
> > > >
> > > > base-commit-tag: v6.2-rc7
> > > >
> > > > v6:
> > > > - quiet LLVM warning by casting phys_ram_base into an unsigned long
> > > >
> > > > v5:
> > > > - Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks
> > > >   Conor
> > > > - Add RB from Andrew
> > > >
> > > > v4:
> > > > - Rebase on top of v6.2-rc3, as noted by Conor
> > > > - Add Acked-by Rob
> > > >
> > > > v3:
> > > > - Change the comment about initrd_start VA conversion so that it fits
> > > >   ARM64 and RISCV64 (and others in the future if needed), as suggested
> > > >   by Rob
> > > >
> > > > v2:
> > > > - Add a comment on why RISCV64 does not need to set initrd_start/end that
> > > >   early in the boot process, as asked by Rob
> > > >
> > > > Alexandre Ghiti (2):
> > > >   riscv: Get rid of riscv_pfn_base variable
> > > >   riscv: Use PUD/P4D/PGD pages for the linear mapping
> > >
> > > I tried this series but it is getting stuck after reaching user space.
> > >
> > > Does this series require some other dependent patches ?
> >
> > No it should not. Let me take a look: what's your config and the base commit?
>
> Please try the alexghiti_test branch at:
> https://github.com/avpatel/linux.git
>
> Compile the kernel with defconfig and launch QEMU as follows:
> qemu-system-riscv64 -M virt -m 1G -nographic -bios
> opensbi/build/platform/generic/firmware/fw_jump.bin -kernel
> ./build-riscv64/arch/riscv/boot/Image -append "root=/dev/ram rw
> console=ttyS0 earlycon" -initrd ./rootfs_riscv64.img
>
> In the above command, rootfs_riscv64.img is a busybox based rootfs.

Ok I can reproduce the problem. I'll debug that a bit further but
increasing memory allows booting to userspace.

>
> Regards,
> Anup
>
> >
> > >
> > > Regards,
> > > Anup
> > >
> > > >
> > > >  arch/riscv/include/asm/page.h | 19 +++++++++++++++++--
> > > >  arch/riscv/mm/init.c          | 28 ++++++++++++++++++----------
> > > >  arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
> > > >  drivers/of/fdt.c              | 11 ++++++-----
> > > >  4 files changed, 57 insertions(+), 17 deletions(-)
> > > >
> > > > --
> > > > 2.37.2
> > > >

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Alexandre Ghiti]

On Tue, Mar 7, 2023 at 2:36 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
>
> On Tue, Mar 7, 2023 at 2:19 PM Anup Patel <apatel@ventanamicro.com> wrote:
> >
> > Hi Alex,
> >
> > On Tue, Mar 7, 2023 at 12:22 AM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> > >
> > > Hi Anup,
> > >
> > > On Mon, Mar 6, 2023 at 5:33 PM Anup Patel <apatel@ventanamicro.com> wrote:
> > > >
> > > > On Wed, Mar 1, 2023 at 1:56 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> > > > >
> > > > > This patchset intends to improve tlb utilization by using hugepages for
> > > > > the linear mapping.
> > > > >
> > > > > base-commit-tag: v6.2-rc7
> > > > >
> > > > > v6:
> > > > > - quiet LLVM warning by casting phys_ram_base into an unsigned long
> > > > >
> > > > > v5:
> > > > > - Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks
> > > > >   Conor
> > > > > - Add RB from Andrew
> > > > >
> > > > > v4:
> > > > > - Rebase on top of v6.2-rc3, as noted by Conor
> > > > > - Add Acked-by Rob
> > > > >
> > > > > v3:
> > > > > - Change the comment about initrd_start VA conversion so that it fits
> > > > >   ARM64 and RISCV64 (and others in the future if needed), as suggested
> > > > >   by Rob
> > > > >
> > > > > v2:
> > > > > - Add a comment on why RISCV64 does not need to set initrd_start/end that
> > > > >   early in the boot process, as asked by Rob
> > > > >
> > > > > Alexandre Ghiti (2):
> > > > >   riscv: Get rid of riscv_pfn_base variable
> > > > >   riscv: Use PUD/P4D/PGD pages for the linear mapping
> > > >
> > > > I tried this series but it is getting stuck after reaching user space.
> > > >
> > > > Does this series require some other dependent patches ?
> > >
> > > No it should not. Let me take a look: what's your config and the base commit?
> >
> > Please try the alexghiti_test branch at:
> > https://github.com/avpatel/linux.git
> >
> > Compile the kernel with defconfig and launch QEMU as follows:
> > qemu-system-riscv64 -M virt -m 1G -nographic -bios
> > opensbi/build/platform/generic/firmware/fw_jump.bin -kernel
> > ./build-riscv64/arch/riscv/boot/Image -append "root=/dev/ram rw
> > console=ttyS0 earlycon" -initrd ./rootfs_riscv64.img
> >
> > In the above command, rootfs_riscv64.img is a busybox based rootfs.
>
> Ok I can reproduce the problem. I'll debug that a bit further but
> increasing memory allows booting to userspace.
>

This is a real bug and that's because I should split the 1G page that
contains the kernel text alias (and anything that we map with stricter
rights) or something similar. I'll get back soon with a fix.

Thanks Anup for the report,

Alex

> >
> > Regards,
> > Anup
> >
> > >
> > > >
> > > > Regards,
> > > > Anup
> > > >
> > > > >
> > > > >  arch/riscv/include/asm/page.h | 19 +++++++++++++++++--
> > > > >  arch/riscv/mm/init.c          | 28 ++++++++++++++++++----------
> > > > >  arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
> > > > >  drivers/of/fdt.c              | 11 ++++++-----
> > > > >  4 files changed, 57 insertions(+), 17 deletions(-)
> > > > >
> > > > > --
> > > > > 2.37.2
> > > > >

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v6 0/2] riscv: Use PUD/P4D/PGD pages for the linear mapping

[Alexandre Ghiti]

On Tue, Mar 7, 2023 at 2:36 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
>
> On Tue, Mar 7, 2023 at 2:19 PM Anup Patel <apatel@ventanamicro.com> wrote:
> >
> > Hi Alex,
> >
> > On Tue, Mar 7, 2023 at 12:22 AM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> > >
> > > Hi Anup,
> > >
> > > On Mon, Mar 6, 2023 at 5:33 PM Anup Patel <apatel@ventanamicro.com> wrote:
> > > >
> > > > On Wed, Mar 1, 2023 at 1:56 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
> > > > >
> > > > > This patchset intends to improve tlb utilization by using hugepages for
> > > > > the linear mapping.
> > > > >
> > > > > base-commit-tag: v6.2-rc7
> > > > >
> > > > > v6:
> > > > > - quiet LLVM warning by casting phys_ram_base into an unsigned long
> > > > >
> > > > > v5:
> > > > > - Fix nommu builds by getting rid of riscv_pfn_base in patch 1, thanks
> > > > >   Conor
> > > > > - Add RB from Andrew
> > > > >
> > > > > v4:
> > > > > - Rebase on top of v6.2-rc3, as noted by Conor
> > > > > - Add Acked-by Rob
> > > > >
> > > > > v3:
> > > > > - Change the comment about initrd_start VA conversion so that it fits
> > > > >   ARM64 and RISCV64 (and others in the future if needed), as suggested
> > > > >   by Rob
> > > > >
> > > > > v2:
> > > > > - Add a comment on why RISCV64 does not need to set initrd_start/end that
> > > > >   early in the boot process, as asked by Rob
> > > > >
> > > > > Alexandre Ghiti (2):
> > > > >   riscv: Get rid of riscv_pfn_base variable
> > > > >   riscv: Use PUD/P4D/PGD pages for the linear mapping
> > > >
> > > > I tried this series but it is getting stuck after reaching user space.
> > > >
> > > > Does this series require some other dependent patches ?
> > >
> > > No it should not. Let me take a look: what's your config and the base commit?
> >
> > Please try the alexghiti_test branch at:
> > https://github.com/avpatel/linux.git
> >
> > Compile the kernel with defconfig and launch QEMU as follows:
> > qemu-system-riscv64 -M virt -m 1G -nographic -bios
> > opensbi/build/platform/generic/firmware/fw_jump.bin -kernel
> > ./build-riscv64/arch/riscv/boot/Image -append "root=/dev/ram rw
> > console=ttyS0 earlycon" -initrd ./rootfs_riscv64.img
> >
> > In the above command, rootfs_riscv64.img is a busybox based rootfs.
>
> Ok I can reproduce the problem. I'll debug that a bit further but
> increasing memory allows booting to userspace.
>

This is a real bug and that's because I should split the 1G page that
contains the kernel text alias (and anything that we map with stricter
rights) or something similar. I'll get back soon with a fix.

Thanks Anup for the report,

Alex

> >
> > Regards,
> > Anup
> >
> > >
> > > >
> > > > Regards,
> > > > Anup
> > > >
> > > > >
> > > > >  arch/riscv/include/asm/page.h | 19 +++++++++++++++++--
> > > > >  arch/riscv/mm/init.c          | 28 ++++++++++++++++++----------
> > > > >  arch/riscv/mm/physaddr.c      | 16 ++++++++++++++++
> > > > >  drivers/of/fdt.c              | 11 ++++++-----
> > > > >  4 files changed, 57 insertions(+), 17 deletions(-)
> > > > >
> > > > > --
> > > > > 2.37.2
> > > > >