* [Intel-gfx] [PATCH] drm/i915/display: split out DSC and DSS registers
@ 2023-03-01 15:19 Jani Nikula
2023-03-01 22:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Jani Nikula @ 2023-03-01 15:19 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Relatively few places need the DSC and DSS register definitions. Move
them to intel_vdsc_regs.h.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_vdsc.c | 1 +
.../gpu/drm/i915/display/intel_vdsc_regs.h | 462 ++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 450 -----------------
6 files changed, 466 insertions(+), 450 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_vdsc_regs.h
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index b5316715bb3b..9b83fdc89fa2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -45,6 +45,7 @@
#include "intel_dsi_vbt.h"
#include "intel_panel.h"
#include "intel_vdsc.h"
+#include "intel_vdsc_regs.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e5979427b38b..0c58f042cc7e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -68,6 +68,7 @@
#include "intel_sprite.h"
#include "intel_tc.h"
#include "intel_vdsc.h"
+#include "intel_vdsc_regs.h"
#include "intel_vrr.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a1fbdf32bd21..edbcb1273ca2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -116,6 +116,7 @@
#include "intel_tv.h"
#include "intel_vblank.h"
#include "intel_vdsc.h"
+#include "intel_vdsc_regs.h"
#include "intel_vga.h"
#include "intel_vrr.h"
#include "intel_wm.h"
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..09b32ffdc552 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -17,6 +17,7 @@
#include "intel_dsi.h"
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
+#include "intel_vdsc_regs.h"
enum ROW_INDEX_BPP {
ROW_INDEX_6BPP = 0,
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
new file mode 100644
index 000000000000..02cd89077eb6
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -0,0 +1,462 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_VDSC_REGS_H__
+#define __INTEL_VDSC_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+/* Display Stream Splitter Control */
+#define DSS_CTL1 _MMIO(0x67400)
+#define SPLITTER_ENABLE (1 << 31)
+#define JOINER_ENABLE (1 << 30)
+#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
+#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
+#define OVERLAP_PIXELS_MASK (0xf << 16)
+#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
+#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
+#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
+#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
+
+#define DSS_CTL2 _MMIO(0x67404)
+#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
+#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
+#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
+#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
+
+#define _ICL_PIPE_DSS_CTL1_PB 0x78200
+#define _ICL_PIPE_DSS_CTL1_PC 0x78400
+#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_PIPE_DSS_CTL1_PB, \
+ _ICL_PIPE_DSS_CTL1_PC)
+#define BIG_JOINER_ENABLE (1 << 29)
+#define MASTER_BIG_JOINER_ENABLE (1 << 28)
+#define VGA_CENTERING_ENABLE (1 << 27)
+#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
+#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
+#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
+#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
+#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
+
+#define _ICL_PIPE_DSS_CTL2_PB 0x78204
+#define _ICL_PIPE_DSS_CTL2_PC 0x78404
+#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_PIPE_DSS_CTL2_PB, \
+ _ICL_PIPE_DSS_CTL2_PC)
+
+/* Icelake Display Stream Compression Registers */
+#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
+#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
+#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
+#define DSC_ALT_ICH_SEL (1 << 20)
+#define DSC_VBR_ENABLE (1 << 19)
+#define DSC_422_ENABLE (1 << 18)
+#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
+#define DSC_BLOCK_PREDICTION (1 << 16)
+#define DSC_LINE_BUF_DEPTH_SHIFT 12
+#define DSC_BPC_SHIFT 8
+#define DSC_VER_MIN_SHIFT 4
+#define DSC_VER_MAJ (0x1 << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
+#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
+#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
+#define DSC_BPP(bpp) ((bpp) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
+#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
+#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
+#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
+#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
+#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
+#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
+#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
+#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
+#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
+#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
+#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
+#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
+#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
+#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
+#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
+#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
+#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
+#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
+#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
+#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
+#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
+#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
+#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
+#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
+#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
+#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
+#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
+#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
+#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
+#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
+#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
+#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
+#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
+#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
+#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
+#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
+#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
+#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
+#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
+#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
+
+#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
+#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
+#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
+
+#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
+#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
+#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
+
+#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
+#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
+#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
+
+#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
+#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
+#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
+
+#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
+#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
+#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
+
+#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
+#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
+#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
+#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
+#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
+ _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
+#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
+#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
+#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
+#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
+
+/* Icelake Rate Control Buffer Threshold Registers */
+#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
+#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
+#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
+#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
+#define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
+#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
+#define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
+#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
+#define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
+#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
+#define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
+#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
+#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_BUF_THRESH_0_PB, \
+ _ICL_DSC0_RC_BUF_THRESH_0_PC)
+#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
+ _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
+#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_BUF_THRESH_0_PB, \
+ _ICL_DSC1_RC_BUF_THRESH_0_PC)
+#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
+ _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
+
+#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
+#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
+#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
+#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
+#define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
+#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
+#define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
+#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
+#define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
+#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
+#define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
+#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
+#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_BUF_THRESH_1_PB, \
+ _ICL_DSC0_RC_BUF_THRESH_1_PC)
+#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
+ _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
+#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_BUF_THRESH_1_PB, \
+ _ICL_DSC1_RC_BUF_THRESH_1_PC)
+#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
+ _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
+
+/* Icelake DSC Rate Control Range Parameter Registers */
+#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
+#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
+#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
+#define RC_BPG_OFFSET_SHIFT 10
+#define RC_MAX_QP_SHIFT 5
+#define RC_MIN_QP_SHIFT 0
+
+#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
+#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
+#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
+
+#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
+#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
+#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
+
+#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
+#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
+#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
+#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
+#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
+#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
+#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
+ _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
+#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
+ _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
+
+
+#endif /* __INTEL_VDSC_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c1efa655fb68..f2ce4bde6a68 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2298,110 +2298,6 @@
#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
-/* Icelake DSC Rate Control Range Parameter Registers */
-#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
-#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
-#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
-#define RC_BPG_OFFSET_SHIFT 10
-#define RC_MAX_QP_SHIFT 5
-#define RC_MIN_QP_SHIFT 0
-
-#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
-#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
-#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
-
-#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
-#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
-#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
-
-#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
-#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
-#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
-#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
-#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
-#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
-#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
- _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
-#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
- _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
-
/* VGA port control */
#define ADPA _MMIO(0x61100)
#define PCH_ADPA _MMIO(0xe1100)
@@ -7669,44 +7565,6 @@ enum skl_power_gate {
#define PIPE_FRMTMSTMP(pipe) \
_MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
-/* Display Stream Splitter Control */
-#define DSS_CTL1 _MMIO(0x67400)
-#define SPLITTER_ENABLE (1 << 31)
-#define JOINER_ENABLE (1 << 30)
-#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
-#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
-#define OVERLAP_PIXELS_MASK (0xf << 16)
-#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
-#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
-#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
-#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
-
-#define DSS_CTL2 _MMIO(0x67404)
-#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
-#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
-#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
-#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
-
-#define _ICL_PIPE_DSS_CTL1_PB 0x78200
-#define _ICL_PIPE_DSS_CTL1_PC 0x78400
-#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_PIPE_DSS_CTL1_PB, \
- _ICL_PIPE_DSS_CTL1_PC)
-#define BIG_JOINER_ENABLE (1 << 29)
-#define MASTER_BIG_JOINER_ENABLE (1 << 28)
-#define VGA_CENTERING_ENABLE (1 << 27)
-#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
-#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
-#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
-#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
-#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
-
-#define _ICL_PIPE_DSS_CTL2_PB 0x78204
-#define _ICL_PIPE_DSS_CTL2_PC 0x78404
-#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_PIPE_DSS_CTL2_PB, \
- _ICL_PIPE_DSS_CTL2_PC)
-
#define GGC _MMIO(0x108040)
#define GMS_MASK REG_GENMASK(15, 8)
#define GGMS_MASK REG_GENMASK(7, 6)
@@ -7730,314 +7588,6 @@ enum skl_power_gate {
#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
-/* Icelake Display Stream Compression Registers */
-#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
-#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
-#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
-#define DSC_ALT_ICH_SEL (1 << 20)
-#define DSC_VBR_ENABLE (1 << 19)
-#define DSC_422_ENABLE (1 << 18)
-#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
-#define DSC_BLOCK_PREDICTION (1 << 16)
-#define DSC_LINE_BUF_DEPTH_SHIFT 12
-#define DSC_BPC_SHIFT 8
-#define DSC_VER_MIN_SHIFT 4
-#define DSC_VER_MAJ (0x1 << 0)
-
-#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
-#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
-#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
-#define DSC_BPP(bpp) ((bpp) << 0)
-
-#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
-#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
-#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
-#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
-#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
-
-#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
-#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
-#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
-#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
-#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
-
-#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
-#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
-#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
-#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
-#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
-
-#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
-#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
-#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
-#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
-#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
-
-#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
-#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
-#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
-#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
-#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
-#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
-#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
-
-#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
-#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
-#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
-#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
-#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
-
-#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
-#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
-#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
-#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
-#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
-
-#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
-#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
-#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
-#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
-#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
-
-#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
-#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
-#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
-#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
-#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
-#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
-#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
-
-#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
-#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
-#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
-
-#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
-#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
-#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
-
-#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
-#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
-#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
-
-#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
-#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
-#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
-
-#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
-#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
-#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
-
-#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
-#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
-#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
-#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
-#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
-#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
-#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
-#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
-#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
-
-/* Icelake Rate Control Buffer Threshold Registers */
-#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
-#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
-#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
-#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
-#define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
-#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
-#define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
-#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
-#define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
-#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
-#define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
-#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
-#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_BUF_THRESH_0_PB, \
- _ICL_DSC0_RC_BUF_THRESH_0_PC)
-#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
- _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
-#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_BUF_THRESH_0_PB, \
- _ICL_DSC1_RC_BUF_THRESH_0_PC)
-#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
- _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
-
-#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
-#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
-#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
-#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
-#define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
-#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
-#define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
-#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
-#define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
-#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
-#define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
-#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
-#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_BUF_THRESH_1_PB, \
- _ICL_DSC0_RC_BUF_THRESH_1_PC)
-#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
- _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
-#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_BUF_THRESH_1_PB, \
- _ICL_DSC1_RC_BUF_THRESH_1_PC)
-#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
- _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
-
#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
#define MODULAR_FIA_MASK (1 << 4)
#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
--
2.39.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: split out DSC and DSS registers
2023-03-01 15:19 [Intel-gfx] [PATCH] drm/i915/display: split out DSC and DSS registers Jani Nikula
@ 2023-03-01 22:04 ` Patchwork
2023-03-04 21:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-03-06 14:50 ` [Intel-gfx] [PATCH] " Ville Syrjälä
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-03-01 22:04 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3707 bytes --]
== Series Details ==
Series: drm/i915/display: split out DSC and DSS registers
URL : https://patchwork.freedesktop.org/series/114523/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12799 -> Patchwork_114523v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/index.html
Participating hosts (40 -> 38)
------------------------------
Missing (2): fi-snb-2520m fi-pnv-d510
Known issues
------------
Here are the changes found in Patchwork_114523v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: NOTRUN -> [ABORT][1] ([i915#6687] / [i915#7978])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@gt_heartbeat:
- bat-jsl-1: [PASS][2] -> [DMESG-FAIL][3] ([i915#5334])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/bat-jsl-1/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@slpc:
- bat-rpls-1: NOTRUN -> [DMESG-FAIL][4] ([i915#6367])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/bat-rpls-1/igt@i915_selftest@live@slpc.html
#### Possible fixes ####
* igt@i915_selftest@live@migrate:
- bat-atsm-1: [DMESG-FAIL][5] ([i915#7699]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-atsm-1/igt@i915_selftest@live@migrate.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/bat-atsm-1/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [ABORT][7] ([i915#4983]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_selftest@live@reset.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/bat-rpls-1/igt@i915_selftest@live@reset.html
#### Warnings ####
* igt@i915_selftest@live@slpc:
- bat-rpls-2: [DMESG-FAIL][9] ([i915#6997] / [i915#7913]) -> [DMESG-FAIL][10] ([i915#6367] / [i915#7913])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-2/igt@i915_selftest@live@slpc.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/bat-rpls-2/igt@i915_selftest@live@slpc.html
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
Build changes
-------------
* Linux: CI_DRM_12799 -> Patchwork_114523v1
CI-20190529: 20190529
CI_DRM_12799: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7178: ffe3f6670b91ab975f90799ab3fd0941b6eae019 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_114523v1: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
0e112008e261 drm/i915/display: split out DSC and DSS registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/index.html
[-- Attachment #2: Type: text/html, Size: 4579 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: split out DSC and DSS registers
2023-03-01 15:19 [Intel-gfx] [PATCH] drm/i915/display: split out DSC and DSS registers Jani Nikula
2023-03-01 22:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
@ 2023-03-04 21:23 ` Patchwork
2023-03-06 14:50 ` [Intel-gfx] [PATCH] " Ville Syrjälä
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2023-03-04 21:23 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 45176 bytes --]
== Series Details ==
Series: drm/i915/display: split out DSC and DSS registers
URL : https://patchwork.freedesktop.org/series/114523/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12799_full -> Patchwork_114523v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_114523v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_114523v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (19 -> 19)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_114523v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-snb1/igt@i915_pm_rps@reset.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-snb5/igt@i915_pm_rps@reset.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_create@create-clear@smem0:
- {shard-rkl}: NOTRUN -> [ABORT][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-rkl-4/igt@gem_create@create-clear@smem0.html
* igt@gem_create@create-ext-cpu-access-big:
- {shard-dg2-7}: NOTRUN -> [ABORT][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-dg2-7/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_eio@hibernate:
- {shard-dg2-6}: NOTRUN -> [ABORT][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-dg2-6/igt@gem_eio@hibernate.html
* igt@kms_content_protection@srm@pipe-a-dp-2:
- {shard-dg2-12}: NOTRUN -> [TIMEOUT][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-dg2-12/igt@kms_content_protection@srm@pipe-a-dp-2.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@d-dp3:
- {shard-dg2-11}: NOTRUN -> [FAIL][7] +5 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-dg2-11/igt@kms_flip@flip-vs-blocking-wf-vblank@d-dp3.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
- {shard-dg2-12}: NOTRUN -> [FAIL][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-badstride:
- {shard-dg2-1}: NOTRUN -> [FAIL][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-badstride.html
New tests
---------
New tests have been introduced between CI_DRM_12799_full and Patchwork_114523v1_full:
### New IGT tests (37) ###
* igt@kms_cursor_crc@cursor-onscreen-128x42@pipe-d-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-random-64x64@pipe-d-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_crc@cursor-suspend@pipe-d-dp-4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@ab-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@ab-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@ab-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@ac-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@ac-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@ac-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@ad-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@ad-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@ad-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@bc-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@bd-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@cd-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ac-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ac-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ac-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ad-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ad-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ad-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@bc-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@bc-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@bc-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@bd-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@bd-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@bd-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@cd-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@cd-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@cd-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_lowres@tiling-4@pipe-a-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_lowres@tiling-4@pipe-b-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_lowres@tiling-4@pipe-c-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_lowres@tiling-4@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_114523v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_buddy@all-tests:
- shard-tglu-9: NOTRUN -> [SKIP][10] ([i915#6433])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@drm_buddy@all-tests.html
* igt@fbdev@unaligned-write:
- shard-tglu-9: NOTRUN -> [SKIP][11] ([i915#2582])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@fbdev@unaligned-write.html
* igt@feature_discovery@display-3x:
- shard-tglu-10: NOTRUN -> [SKIP][12] ([i915#1839])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@feature_discovery@display-3x.html
* igt@gem_create@create-ext-cpu-access-big:
- shard-tglu-9: NOTRUN -> [SKIP][13] ([i915#6335])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_ctx_persistence@engines-cleanup:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#1099]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-snb5/igt@gem_ctx_persistence@engines-cleanup.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-tglu-9: NOTRUN -> [FAIL][15] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-glk5/igt@gem_exec_fair@basic-none-share@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-glk7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-tglu-10: NOTRUN -> [FAIL][18] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_gttfill@multigpu-basic:
- shard-tglu-10: NOTRUN -> [SKIP][19] ([i915#7697]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@gem_exec_gttfill@multigpu-basic.html
* igt@gem_exec_schedule@thriceslice:
- shard-snb: NOTRUN -> [SKIP][20] ([fdo#109271]) +170 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-snb5/igt@gem_exec_schedule@thriceslice.html
* igt@gem_huc_copy@huc-copy:
- shard-tglu-9: NOTRUN -> [SKIP][21] ([i915#2190])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-tglu-10: NOTRUN -> [SKIP][22] ([i915#4613])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-tglu-9: NOTRUN -> [SKIP][23] ([i915#4613]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_media_vme:
- shard-tglu-10: NOTRUN -> [SKIP][24] ([i915#284])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@gem_media_vme.html
* igt@gem_mmap_gtt@coherency:
- shard-tglu-9: NOTRUN -> [SKIP][25] ([fdo#111656])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@gem_mmap_gtt@coherency.html
* igt@gem_pread@exhaustion:
- shard-tglu-10: NOTRUN -> [WARN][26] ([i915#2658])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@gem_pread@exhaustion.html
* igt@gem_pxp@reject-modify-context-protection-on:
- shard-tglu-9: NOTRUN -> [SKIP][27] ([i915#4270]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@gem_pxp@reject-modify-context-protection-on.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-tglu-10: NOTRUN -> [SKIP][28] ([i915#4270]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_userptr_blits@coherency-unsync:
- shard-tglu-10: NOTRUN -> [SKIP][29] ([i915#3297])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@gem_userptr_blits@coherency-unsync.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-tglu-9: NOTRUN -> [SKIP][30] ([i915#3297]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gen7_exec_parse@basic-rejected:
- shard-tglu-10: NOTRUN -> [SKIP][31] ([fdo#109289])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@gen7_exec_parse@basic-rejected.html
* igt@gen7_exec_parse@load-register-reg:
- shard-tglu-9: NOTRUN -> [SKIP][32] ([fdo#109289]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@gen7_exec_parse@load-register-reg.html
* igt@gen9_exec_parse@bb-chained:
- shard-tglu-10: NOTRUN -> [SKIP][33] ([i915#2527] / [i915#2856]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@gen9_exec_parse@bb-chained.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-tglu-10: NOTRUN -> [SKIP][34] ([fdo#111644] / [i915#1397])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_pm_sseu@full-enable:
- shard-tglu-9: NOTRUN -> [SKIP][35] ([i915#4387])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@i915_pm_sseu@full-enable.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-tglu-10: NOTRUN -> [INCOMPLETE][36] ([i915#7443])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
- shard-tglu-10: NOTRUN -> [SKIP][37] ([i915#5286]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-tglu-10: NOTRUN -> [SKIP][38] ([fdo#111614])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
- shard-tglu-9: NOTRUN -> [SKIP][39] ([fdo#111615] / [i915#1845] / [i915#7651]) +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
- shard-tglu-10: NOTRUN -> [SKIP][40] ([fdo#111615]) +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_joiner@invalid-modeset:
- shard-tglu-10: NOTRUN -> [SKIP][41] ([i915#2705])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][42] ([i915#3689] / [i915#3886]) +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_mc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][43] ([i915#3689] / [i915#6095])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_ccs@pipe-b-bad-pixel-format-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_rc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][44] ([i915#6095]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][45] ([i915#3689]) +4 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-d-bad-pixel-format-yf_tiled_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][46] ([fdo#111615] / [i915#3689]) +2 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_ccs@pipe-d-bad-pixel-format-yf_tiled_ccs.html
* igt@kms_cdclk@plane-scaling:
- shard-tglu-9: NOTRUN -> [SKIP][47] ([i915#3742])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_color@ctm-red-to-blue:
- shard-tglu-9: NOTRUN -> [SKIP][48] ([fdo#111827]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_chamelium_color@ctm-red-to-blue.html
* igt@kms_chamelium_frames@vga-frame-dump:
- shard-tglu-9: NOTRUN -> [SKIP][49] ([i915#7828]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_chamelium_frames@vga-frame-dump.html
* igt@kms_chamelium_hpd@hdmi-hpd:
- shard-tglu-10: NOTRUN -> [SKIP][50] ([i915#7828]) +4 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_chamelium_hpd@hdmi-hpd.html
* igt@kms_color@ctm-negative:
- shard-tglu-9: NOTRUN -> [SKIP][51] ([i915#3546])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_color@ctm-negative.html
* igt@kms_content_protection@content_type_change:
- shard-tglu-10: NOTRUN -> [SKIP][52] ([i915#6944] / [i915#7116] / [i915#7118])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_content_protection@content_type_change.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-tglu-10: NOTRUN -> [SKIP][53] ([i915#3359])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-sliding-32x32:
- shard-tglu-10: NOTRUN -> [SKIP][54] ([i915#3555]) +4 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_cursor_crc@cursor-sliding-32x32.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][55] -> [FAIL][56] ([i915#72])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-tglu-10: NOTRUN -> [SKIP][57] ([i915#4103])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-tglu-10: NOTRUN -> [SKIP][58] ([fdo#109274]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-tglu-9: NOTRUN -> [SKIP][59] ([i915#1845]) +15 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][60] -> [FAIL][61] ([i915#2346])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-tglu-10: NOTRUN -> [SKIP][62] ([i915#3840])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-tglu-9: NOTRUN -> [SKIP][63] ([i915#3469])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-tglu-10: NOTRUN -> [SKIP][64] ([fdo#109274] / [i915#3637] / [i915#3966])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-tglu-10: NOTRUN -> [SKIP][65] ([fdo#109274] / [i915#3637]) +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-nonexisting-fb-interruptible:
- shard-tglu-9: NOTRUN -> [SKIP][66] ([fdo#109274] / [i915#3637]) +4 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_flip@2x-nonexisting-fb-interruptible.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-tglu-9: NOTRUN -> [SKIP][67] ([i915#3637]) +4 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-tglu-10: NOTRUN -> [SKIP][68] ([i915#2587] / [i915#2672]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
- shard-tglu-9: NOTRUN -> [SKIP][69] ([i915#3555]) +7 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-tglu-10: NOTRUN -> [SKIP][70] ([fdo#110189]) +18 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
- shard-tglu-9: NOTRUN -> [SKIP][71] ([i915#1849]) +35 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-tglu-10: NOTRUN -> [SKIP][72] ([fdo#109280]) +19 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_lease@lease_unleased_connector:
- shard-tglu-9: NOTRUN -> [SKIP][73] ([i915#1845] / [i915#7651]) +44 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_lease@lease_unleased_connector.html
* igt@kms_plane@plane-panning-top-left@pipe-a-planes:
- shard-tglu-9: NOTRUN -> [SKIP][74] ([i915#1849] / [i915#3558]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_plane@plane-panning-top-left@pipe-a-planes.html
* igt@kms_plane_alpha_blend@alpha-transparent-fb:
- shard-tglu-9: NOTRUN -> [SKIP][75] ([i915#7128] / [i915#7294])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_plane_alpha_blend@alpha-transparent-fb.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5:
- shard-tglu-9: NOTRUN -> [SKIP][76] ([i915#6953] / [i915#8152])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75:
- shard-tglu-9: NOTRUN -> [SKIP][77] ([i915#3555] / [i915#6953])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1:
- shard-tglu-10: NOTRUN -> [SKIP][78] ([i915#5235]) +3 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_prime@d3hot:
- shard-tglu-9: NOTRUN -> [SKIP][79] ([i915#6524])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_prime@d3hot.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-tglu-9: NOTRUN -> [SKIP][80] ([i915#658]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-tglu-10: NOTRUN -> [SKIP][81] ([fdo#111068] / [i915#658])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-tglu-10: NOTRUN -> [SKIP][82] ([fdo#109642] / [fdo#111068] / [i915#658])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@cursor_blt:
- shard-tglu-9: NOTRUN -> [SKIP][83] ([fdo#110189]) +2 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@kms_psr@cursor_blt.html
* igt@kms_setmode@basic@pipe-a-vga-1:
- shard-snb: NOTRUN -> [FAIL][84] ([i915#5465]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-snb5/igt@kms_setmode@basic@pipe-a-vga-1.html
* igt@prime_vgem@fence-write-hang:
- shard-tglu-9: NOTRUN -> [SKIP][85] ([fdo#109295])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@prime_vgem@fence-write-hang.html
* igt@tools_test@sysfs_l3_parity:
- shard-tglu-9: NOTRUN -> [SKIP][86] ([fdo#109307])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@tools_test@sysfs_l3_parity.html
* igt@v3d/v3d_perfmon@destroy-valid-perfmon:
- shard-tglu-10: NOTRUN -> [SKIP][87] ([fdo#109315] / [i915#2575]) +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@v3d/v3d_perfmon@destroy-valid-perfmon.html
* igt@v3d/v3d_perfmon@get-values-invalid-pad:
- shard-tglu-9: NOTRUN -> [SKIP][88] ([fdo#109315] / [i915#2575]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@v3d/v3d_perfmon@get-values-invalid-pad.html
* igt@vc4/vc4_perfmon@create-single-perfmon:
- shard-tglu-9: NOTRUN -> [SKIP][89] ([i915#2575]) +2 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-9/igt@vc4/vc4_perfmon@create-single-perfmon.html
* igt@vc4/vc4_perfmon@create-two-perfmon:
- shard-tglu-10: NOTRUN -> [SKIP][90] ([i915#2575]) +5 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-tglu-10/igt@vc4/vc4_perfmon@create-two-perfmon.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- {shard-rkl}: [FAIL][91] ([i915#2842]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-rkl-5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-apl: [FAIL][93] ([i915#2842]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-apl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@i915_pm_rpm@drm-resources-equal:
- {shard-rkl}: [SKIP][95] ([fdo#109308]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@i915_pm_rpm@drm-resources-equal.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-rkl-6/igt@i915_pm_rpm@drm-resources-equal.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- {shard-rkl}: [SKIP][97] ([i915#1845] / [i915#4098]) -> [PASS][98] +7 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
- shard-glk: [FAIL][99] ([i915#79]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- {shard-rkl}: [SKIP][101] ([i915#1849] / [i915#4098]) -> [PASS][102] +6 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_psr@sprite_plane_onoff:
- {shard-rkl}: [SKIP][103] ([i915#1072]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@kms_psr@sprite_plane_onoff.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/shard-rkl-6/igt@kms_psr@sprite_plane_onoff.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#5107]: https://gitlab.freedesktop.org/drm/intel/issues/5107
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5410]: https://gitlab.freedesktop.org/drm/intel/issues/5410
[i915#5431]: https://gitlab.freedesktop.org/drm/intel/issues/5431
[i915#5433]: https://gitlab.freedesktop.org/drm/intel/issues/5433
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5445]: https://gitlab.freedesktop.org/drm/intel/issues/5445
[i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5464]: https://gitlab.freedesktop.org/drm/intel/issues/5464
[i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5793]: https://gitlab.freedesktop.org/drm/intel/issues/5793
[i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882
[i915#5889]: https://gitlab.freedesktop.org/drm/intel/issues/5889
[i915#5892]: https://gitlab.freedesktop.org/drm/intel/issues/5892
[i915#5978]: https://gitlab.freedesktop.org/drm/intel/issues/5978
[i915#6032]: https://gitlab.freedesktop.org/drm/intel/issues/6032
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6118]: https://gitlab.freedesktop.org/drm/intel/issues/6118
[i915#6122]: https://gitlab.freedesktop.org/drm/intel/issues/6122
[i915#6188]: https://gitlab.freedesktop.org/drm/intel/issues/6188
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6228]: https://gitlab.freedesktop.org/drm/intel/issues/6228
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6403]: https://gitlab.freedesktop.org/drm/intel/issues/6403
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#6530]: https://gitlab.freedesktop.org/drm/intel/issues/6530
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
[i915#7091]: https://gitlab.freedesktop.org/drm/intel/issues/7091
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7507]: https://gitlab.freedesktop.org/drm/intel/issues/7507
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7679]: https://gitlab.freedesktop.org/drm/intel/issues/7679
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#7997]: https://gitlab.freedesktop.org/drm/intel/issues/7997
[i915#8077]: https://gitlab.freedesktop.org/drm/intel/issues/8077
[i915#8150]: https://gitlab.freedesktop.org/drm/intel/issues/8150
[i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
[i915#8154]: https://gitlab.freedesktop.org/drm/intel/issues/8154
[i915#8155]: https://gitlab.freedesktop.org/drm/intel/issues/8155
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8231]: https://gitlab.freedesktop.org/drm/intel/issues/8231
Build changes
-------------
* Linux: CI_DRM_12799 -> Patchwork_114523v1
CI-20190529: 20190529
CI_DRM_12799: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7178: ffe3f6670b91ab975f90799ab3fd0941b6eae019 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_114523v1: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114523v1/index.html
[-- Attachment #2: Type: text/html, Size: 42918 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display: split out DSC and DSS registers
2023-03-01 15:19 [Intel-gfx] [PATCH] drm/i915/display: split out DSC and DSS registers Jani Nikula
2023-03-01 22:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-03-04 21:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2023-03-06 14:50 ` Ville Syrjälä
2023-03-06 16:24 ` Jani Nikula
2 siblings, 1 reply; 5+ messages in thread
From: Ville Syrjälä @ 2023-03-06 14:50 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Mar 01, 2023 at 05:19:49PM +0200, Jani Nikula wrote:
> Relatively few places need the DSC and DSS register definitions. Move
> them to intel_vdsc_regs.h.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_vdsc.c | 1 +
> .../gpu/drm/i915/display/intel_vdsc_regs.h | 462 ++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 450 -----------------
> 6 files changed, 466 insertions(+), 450 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index b5316715bb3b..9b83fdc89fa2 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -45,6 +45,7 @@
> #include "intel_dsi_vbt.h"
> #include "intel_panel.h"
> #include "intel_vdsc.h"
> +#include "intel_vdsc_regs.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index e5979427b38b..0c58f042cc7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -68,6 +68,7 @@
> #include "intel_sprite.h"
> #include "intel_tc.h"
> #include "intel_vdsc.h"
> +#include "intel_vdsc_regs.h"
> #include "intel_vrr.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a1fbdf32bd21..edbcb1273ca2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -116,6 +116,7 @@
> #include "intel_tv.h"
> #include "intel_vblank.h"
> #include "intel_vdsc.h"
> +#include "intel_vdsc_regs.h"
> #include "intel_vga.h"
> #include "intel_vrr.h"
> #include "intel_wm.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 207b2a648d32..09b32ffdc552 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -17,6 +17,7 @@
> #include "intel_dsi.h"
> #include "intel_qp_tables.h"
> #include "intel_vdsc.h"
> +#include "intel_vdsc_regs.h"
>
> enum ROW_INDEX_BPP {
> ROW_INDEX_6BPP = 0,
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> new file mode 100644
> index 000000000000..02cd89077eb6
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
> @@ -0,0 +1,462 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef __INTEL_VDSC_REGS_H__
> +#define __INTEL_VDSC_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +/* Display Stream Splitter Control */
> +#define DSS_CTL1 _MMIO(0x67400)
> +#define SPLITTER_ENABLE (1 << 31)
> +#define JOINER_ENABLE (1 << 30)
> +#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
> +#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
> +#define OVERLAP_PIXELS_MASK (0xf << 16)
> +#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
> +#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> +#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
> +
> +#define DSS_CTL2 _MMIO(0x67404)
> +#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
> +#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
> +#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> +#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> +
> +#define _ICL_PIPE_DSS_CTL1_PB 0x78200
> +#define _ICL_PIPE_DSS_CTL1_PC 0x78400
> +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_PIPE_DSS_CTL1_PB, \
> + _ICL_PIPE_DSS_CTL1_PC)
> +#define BIG_JOINER_ENABLE (1 << 29)
> +#define MASTER_BIG_JOINER_ENABLE (1 << 28)
> +#define VGA_CENTERING_ENABLE (1 << 27)
> +#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
> +#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
> +#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
> +#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
> +#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
> +
> +#define _ICL_PIPE_DSS_CTL2_PB 0x78204
> +#define _ICL_PIPE_DSS_CTL2_PC 0x78404
> +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_PIPE_DSS_CTL2_PB, \
> + _ICL_PIPE_DSS_CTL2_PC)
> +
> +/* Icelake Display Stream Compression Registers */
> +#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
> +#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> +#define DSC_ALT_ICH_SEL (1 << 20)
> +#define DSC_VBR_ENABLE (1 << 19)
> +#define DSC_422_ENABLE (1 << 18)
> +#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
> +#define DSC_BLOCK_PREDICTION (1 << 16)
> +#define DSC_LINE_BUF_DEPTH_SHIFT 12
> +#define DSC_BPC_SHIFT 8
> +#define DSC_VER_MIN_SHIFT 4
> +#define DSC_VER_MAJ (0x1 << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
> +#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
> +#define DSC_BPP(bpp) ((bpp) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
> +#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
> +#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
> +#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
> +#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
> +#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
> +#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
> +#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
> +#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
> +#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
> +#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
> +#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
> +#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
> +#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
> +#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
> +#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
> +#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
> +#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
> +#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
> +#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
> +#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
> +#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
> +#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
> +#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
> +#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
> +#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
> +#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
> +#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
> +#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
> +#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
> +#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
> +#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
> +#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
> +#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
> +#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
> +#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
> +#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
> +#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
> +#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
> +#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
> +#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
> +
> +/* Icelake Rate Control Buffer Threshold Registers */
> +#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
> +#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
> +#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
> +#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
> +#define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
> +#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
> +#define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
> +#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
> +#define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
> +#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
> +#define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
> +#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
> +#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_BUF_THRESH_0_PB, \
> + _ICL_DSC0_RC_BUF_THRESH_0_PC)
> +#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
> + _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
> +#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_BUF_THRESH_0_PB, \
> + _ICL_DSC1_RC_BUF_THRESH_0_PC)
> +#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
> + _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
> +
> +#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
> +#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
> +#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
> +#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
> +#define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
> +#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
> +#define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
> +#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
> +#define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
> +#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
> +#define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
> +#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
> +#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_BUF_THRESH_1_PB, \
> + _ICL_DSC0_RC_BUF_THRESH_1_PC)
> +#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
> + _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
> +#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_BUF_THRESH_1_PB, \
> + _ICL_DSC1_RC_BUF_THRESH_1_PC)
> +#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
> + _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
> +
> +/* Icelake DSC Rate Control Range Parameter Registers */
> +#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
> +#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
> +#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
> +#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
> +#define RC_BPG_OFFSET_SHIFT 10
> +#define RC_MAX_QP_SHIFT 5
> +#define RC_MIN_QP_SHIFT 0
> +
> +#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
> +#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
> +#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
> +#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
> +
> +#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
> +#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
> +#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
> +#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
> +
> +#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
> +#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
> +#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
> +#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
> +#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
> + _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
> +#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
> + _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
> +
> +
> +#endif /* __INTEL_VDSC_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c1efa655fb68..f2ce4bde6a68 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2298,110 +2298,6 @@
> #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
> #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
>
> -/* Icelake DSC Rate Control Range Parameter Registers */
> -#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
> -#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
> -#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
> -#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
> -#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
> -#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
> -#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
> -#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
> -#define RC_BPG_OFFSET_SHIFT 10
> -#define RC_MAX_QP_SHIFT 5
> -#define RC_MIN_QP_SHIFT 0
> -
> -#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
> -#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
> -#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
> -#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
> -#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
> -#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
> -#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
> -#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
> -
> -#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
> -#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
> -#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
> -#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
> -#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
> -#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
> -#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
> -#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
> -
> -#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
> -#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
> -#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
> -#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
> -#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
> -#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
> - _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
> -#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
> -#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
> - _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
> -
> /* VGA port control */
> #define ADPA _MMIO(0x61100)
> #define PCH_ADPA _MMIO(0xe1100)
> @@ -7669,44 +7565,6 @@ enum skl_power_gate {
> #define PIPE_FRMTMSTMP(pipe) \
> _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
>
> -/* Display Stream Splitter Control */
> -#define DSS_CTL1 _MMIO(0x67400)
> -#define SPLITTER_ENABLE (1 << 31)
> -#define JOINER_ENABLE (1 << 30)
> -#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
> -#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
> -#define OVERLAP_PIXELS_MASK (0xf << 16)
> -#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
> -#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> -#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> -#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
> -
> -#define DSS_CTL2 _MMIO(0x67404)
> -#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
> -#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
> -#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> -#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> -
> -#define _ICL_PIPE_DSS_CTL1_PB 0x78200
> -#define _ICL_PIPE_DSS_CTL1_PC 0x78400
> -#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_PIPE_DSS_CTL1_PB, \
> - _ICL_PIPE_DSS_CTL1_PC)
> -#define BIG_JOINER_ENABLE (1 << 29)
> -#define MASTER_BIG_JOINER_ENABLE (1 << 28)
> -#define VGA_CENTERING_ENABLE (1 << 27)
> -#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
> -#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
> -#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
> -#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
> -#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
> -
> -#define _ICL_PIPE_DSS_CTL2_PB 0x78204
> -#define _ICL_PIPE_DSS_CTL2_PC 0x78404
> -#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_PIPE_DSS_CTL2_PB, \
> - _ICL_PIPE_DSS_CTL2_PC)
> -
> #define GGC _MMIO(0x108040)
> #define GMS_MASK REG_GENMASK(15, 8)
> #define GGMS_MASK REG_GENMASK(7, 6)
> @@ -7730,314 +7588,6 @@ enum skl_power_gate {
> #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
> #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
>
> -/* Icelake Display Stream Compression Registers */
> -#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
> -#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> -#define DSC_ALT_ICH_SEL (1 << 20)
> -#define DSC_VBR_ENABLE (1 << 19)
> -#define DSC_422_ENABLE (1 << 18)
> -#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
> -#define DSC_BLOCK_PREDICTION (1 << 16)
> -#define DSC_LINE_BUF_DEPTH_SHIFT 12
> -#define DSC_BPC_SHIFT 8
> -#define DSC_VER_MIN_SHIFT 4
> -#define DSC_VER_MAJ (0x1 << 0)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
> -#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
> -#define DSC_BPP(bpp) ((bpp) << 0)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
> -#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
> -#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
> -#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
> -#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
> -#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
> -#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
> -#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
> -#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
> -#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
> -#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
> -#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
> -#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
> -#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
> -#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
> -#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
> -#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
> -#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
> -#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
> -#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
> -#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
> -#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
> -#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
> -#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
> -#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
> -#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
> -#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
> -#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
> -#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
> -#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
> -#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
> -#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
> -#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
> -#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
> -#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
> -#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
> -#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
> -
> -#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
> -#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
> -#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
> -#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
> -#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
> -#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
> -#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
> -
> -/* Icelake Rate Control Buffer Threshold Registers */
> -#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
> -#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
> -#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
> -#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
> -#define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
> -#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
> -#define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
> -#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
> -#define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
> -#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
> -#define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
> -#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
> -#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_RC_BUF_THRESH_0_PB, \
> - _ICL_DSC0_RC_BUF_THRESH_0_PC)
> -#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
> - _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
> -#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_RC_BUF_THRESH_0_PB, \
> - _ICL_DSC1_RC_BUF_THRESH_0_PC)
> -#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
> - _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
> -
> -#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
> -#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
> -#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
> -#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
> -#define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
> -#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
> -#define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
> -#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
> -#define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
> -#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
> -#define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
> -#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
> -#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_RC_BUF_THRESH_1_PB, \
> - _ICL_DSC0_RC_BUF_THRESH_1_PC)
> -#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
> - _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
> -#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_RC_BUF_THRESH_1_PB, \
> - _ICL_DSC1_RC_BUF_THRESH_1_PC)
> -#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
> - _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
> -
> #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
> #define MODULAR_FIA_MASK (1 << 4)
> #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
> --
> 2.39.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display: split out DSC and DSS registers
2023-03-06 14:50 ` [Intel-gfx] [PATCH] " Ville Syrjälä
@ 2023-03-06 16:24 ` Jani Nikula
0 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2023-03-06 16:24 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, 06 Mar 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Mar 01, 2023 at 05:19:49PM +0200, Jani Nikula wrote:
>> Relatively few places need the DSC and DSS register definitions. Move
>> them to intel_vdsc_regs.h.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Thanks, pushed to din.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
>> drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
>> drivers/gpu/drm/i915/display/intel_display.c | 1 +
>> drivers/gpu/drm/i915/display/intel_vdsc.c | 1 +
>> .../gpu/drm/i915/display/intel_vdsc_regs.h | 462 ++++++++++++++++++
>> drivers/gpu/drm/i915/i915_reg.h | 450 -----------------
>> 6 files changed, 466 insertions(+), 450 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>>
>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>> index b5316715bb3b..9b83fdc89fa2 100644
>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> @@ -45,6 +45,7 @@
>> #include "intel_dsi_vbt.h"
>> #include "intel_panel.h"
>> #include "intel_vdsc.h"
>> +#include "intel_vdsc_regs.h"
>> #include "skl_scaler.h"
>> #include "skl_universal_plane.h"
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index e5979427b38b..0c58f042cc7e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -68,6 +68,7 @@
>> #include "intel_sprite.h"
>> #include "intel_tc.h"
>> #include "intel_vdsc.h"
>> +#include "intel_vdsc_regs.h"
>> #include "intel_vrr.h"
>> #include "skl_scaler.h"
>> #include "skl_universal_plane.h"
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index a1fbdf32bd21..edbcb1273ca2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -116,6 +116,7 @@
>> #include "intel_tv.h"
>> #include "intel_vblank.h"
>> #include "intel_vdsc.h"
>> +#include "intel_vdsc_regs.h"
>> #include "intel_vga.h"
>> #include "intel_vrr.h"
>> #include "intel_wm.h"
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index 207b2a648d32..09b32ffdc552 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -17,6 +17,7 @@
>> #include "intel_dsi.h"
>> #include "intel_qp_tables.h"
>> #include "intel_vdsc.h"
>> +#include "intel_vdsc_regs.h"
>>
>> enum ROW_INDEX_BPP {
>> ROW_INDEX_6BPP = 0,
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>> new file mode 100644
>> index 000000000000..02cd89077eb6
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
>> @@ -0,0 +1,462 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_VDSC_REGS_H__
>> +#define __INTEL_VDSC_REGS_H__
>> +
>> +#include "intel_display_reg_defs.h"
>> +
>> +/* Display Stream Splitter Control */
>> +#define DSS_CTL1 _MMIO(0x67400)
>> +#define SPLITTER_ENABLE (1 << 31)
>> +#define JOINER_ENABLE (1 << 30)
>> +#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
>> +#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
>> +#define OVERLAP_PIXELS_MASK (0xf << 16)
>> +#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
>> +#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
>> +#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
>> +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
>> +
>> +#define DSS_CTL2 _MMIO(0x67404)
>> +#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
>> +#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
>> +#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
>> +#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
>> +
>> +#define _ICL_PIPE_DSS_CTL1_PB 0x78200
>> +#define _ICL_PIPE_DSS_CTL1_PC 0x78400
>> +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_PIPE_DSS_CTL1_PB, \
>> + _ICL_PIPE_DSS_CTL1_PC)
>> +#define BIG_JOINER_ENABLE (1 << 29)
>> +#define MASTER_BIG_JOINER_ENABLE (1 << 28)
>> +#define VGA_CENTERING_ENABLE (1 << 27)
>> +#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
>> +#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
>> +#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
>> +#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
>> +#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
>> +
>> +#define _ICL_PIPE_DSS_CTL2_PB 0x78204
>> +#define _ICL_PIPE_DSS_CTL2_PC 0x78404
>> +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_PIPE_DSS_CTL2_PB, \
>> + _ICL_PIPE_DSS_CTL2_PC)
>> +
>> +/* Icelake Display Stream Compression Registers */
>> +#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
>> +#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
>> +#define DSC_ALT_ICH_SEL (1 << 20)
>> +#define DSC_VBR_ENABLE (1 << 19)
>> +#define DSC_422_ENABLE (1 << 18)
>> +#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
>> +#define DSC_BLOCK_PREDICTION (1 << 16)
>> +#define DSC_LINE_BUF_DEPTH_SHIFT 12
>> +#define DSC_BPC_SHIFT 8
>> +#define DSC_VER_MIN_SHIFT 4
>> +#define DSC_VER_MAJ (0x1 << 0)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
>> +#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
>> +#define DSC_BPP(bpp) ((bpp) << 0)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
>> +#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
>> +#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
>> +#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
>> +#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
>> +#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
>> +#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
>> +#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
>> +#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
>> +#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
>> +#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
>> +#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
>> +#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
>> +#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
>> +#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
>> +#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
>> +#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
>> +#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
>> +#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
>> +#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
>> +#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
>> +#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
>> +#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
>> +#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
>> +#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
>> +#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
>> +#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
>> +#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
>> +#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
>> +#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
>> +#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
>> +#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
>> +#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
>> +#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
>> +#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
>> +#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
>> +#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
>> +
>> +#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
>> +#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
>> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
>> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
>> +#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
>> + _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
>> +#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
>> + _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
>> +#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
>> +#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
>> +#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
>> +
>> +/* Icelake Rate Control Buffer Threshold Registers */
>> +#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
>> +#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
>> +#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
>> +#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
>> +#define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
>> +#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
>> +#define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
>> +#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
>> +#define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
>> +#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
>> +#define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
>> +#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
>> +#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_RC_BUF_THRESH_0_PB, \
>> + _ICL_DSC0_RC_BUF_THRESH_0_PC)
>> +#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
>> + _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
>> +#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_RC_BUF_THRESH_0_PB, \
>> + _ICL_DSC1_RC_BUF_THRESH_0_PC)
>> +#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
>> + _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
>> +
>> +#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
>> +#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
>> +#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
>> +#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
>> +#define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
>> +#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
>> +#define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
>> +#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
>> +#define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
>> +#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
>> +#define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
>> +#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
>> +#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_RC_BUF_THRESH_1_PB, \
>> + _ICL_DSC0_RC_BUF_THRESH_1_PC)
>> +#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
>> + _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
>> +#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_RC_BUF_THRESH_1_PB, \
>> + _ICL_DSC1_RC_BUF_THRESH_1_PC)
>> +#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
>> + _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>> +
>> +/* Icelake DSC Rate Control Range Parameter Registers */
>> +#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
>> +#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
>> +#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
>> +#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
>> +#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
>> +#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
>> +#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
>> +#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
>> +#define RC_BPG_OFFSET_SHIFT 10
>> +#define RC_MAX_QP_SHIFT 5
>> +#define RC_MIN_QP_SHIFT 0
>> +
>> +#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
>> +#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
>> +#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
>> +#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
>> +#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
>> +#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
>> +#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
>> +#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
>> +
>> +#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
>> +#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
>> +#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
>> +#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
>> +#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
>> +#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
>> +#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
>> +#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
>> +
>> +#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
>> +#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
>> +#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
>> +#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
>> +#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
>> +#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
>> +#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
>> +#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
>> + _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
>> +#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
>> +#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
>> + _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
>> +
>> +
>> +#endif /* __INTEL_VDSC_REGS_H__ */
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index c1efa655fb68..f2ce4bde6a68 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2298,110 +2298,6 @@
>> #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14)
>> #define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13)
>>
>> -/* Icelake DSC Rate Control Range Parameter Registers */
>> -#define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240)
>> -#define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4)
>> -#define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40)
>> -#define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4)
>> -#define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC)
>> -#define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC)
>> -#define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC)
>> -#define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC)
>> -#define RC_BPG_OFFSET_SHIFT 10
>> -#define RC_MAX_QP_SHIFT 5
>> -#define RC_MIN_QP_SHIFT 0
>> -
>> -#define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248)
>> -#define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4)
>> -#define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48)
>> -#define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4)
>> -#define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC)
>> -#define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC)
>> -#define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC)
>> -#define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC)
>> -
>> -#define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250)
>> -#define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4)
>> -#define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50)
>> -#define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4)
>> -#define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC)
>> -#define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC)
>> -#define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC)
>> -#define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC)
>> -
>> -#define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258)
>> -#define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4)
>> -#define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58)
>> -#define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420)
>> -#define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520)
>> -#define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4)
>> -#define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC)
>> -#define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \
>> - _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC)
>> -#define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC)
>> -#define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \
>> - _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC)
>> -
>> /* VGA port control */
>> #define ADPA _MMIO(0x61100)
>> #define PCH_ADPA _MMIO(0xe1100)
>> @@ -7669,44 +7565,6 @@ enum skl_power_gate {
>> #define PIPE_FRMTMSTMP(pipe) \
>> _MMIO_PIPE2(pipe, _PIPE_FRMTMSTMP_A)
>>
>> -/* Display Stream Splitter Control */
>> -#define DSS_CTL1 _MMIO(0x67400)
>> -#define SPLITTER_ENABLE (1 << 31)
>> -#define JOINER_ENABLE (1 << 30)
>> -#define DUAL_LINK_MODE_INTERLEAVE (1 << 24)
>> -#define DUAL_LINK_MODE_FRONTBACK (0 << 24)
>> -#define OVERLAP_PIXELS_MASK (0xf << 16)
>> -#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
>> -#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
>> -#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
>> -#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
>> -
>> -#define DSS_CTL2 _MMIO(0x67404)
>> -#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
>> -#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15)
>> -#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
>> -#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
>> -
>> -#define _ICL_PIPE_DSS_CTL1_PB 0x78200
>> -#define _ICL_PIPE_DSS_CTL1_PC 0x78400
>> -#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_PIPE_DSS_CTL1_PB, \
>> - _ICL_PIPE_DSS_CTL1_PC)
>> -#define BIG_JOINER_ENABLE (1 << 29)
>> -#define MASTER_BIG_JOINER_ENABLE (1 << 28)
>> -#define VGA_CENTERING_ENABLE (1 << 27)
>> -#define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25)
>> -#define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0)
>> -#define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1)
>> -#define UNCOMPRESSED_JOINER_MASTER (1 << 21)
>> -#define UNCOMPRESSED_JOINER_SLAVE (1 << 20)
>> -
>> -#define _ICL_PIPE_DSS_CTL2_PB 0x78204
>> -#define _ICL_PIPE_DSS_CTL2_PC 0x78404
>> -#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_PIPE_DSS_CTL2_PB, \
>> - _ICL_PIPE_DSS_CTL2_PC)
>> -
>> #define GGC _MMIO(0x108040)
>> #define GMS_MASK REG_GENMASK(15, 8)
>> #define GGMS_MASK REG_GENMASK(7, 6)
>> @@ -7730,314 +7588,6 @@ enum skl_power_gate {
>> #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
>> #define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
>>
>> -/* Icelake Display Stream Compression Registers */
>> -#define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200)
>> -#define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
>> -#define DSC_ALT_ICH_SEL (1 << 20)
>> -#define DSC_VBR_ENABLE (1 << 19)
>> -#define DSC_422_ENABLE (1 << 18)
>> -#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
>> -#define DSC_BLOCK_PREDICTION (1 << 16)
>> -#define DSC_LINE_BUF_DEPTH_SHIFT 12
>> -#define DSC_BPC_SHIFT 8
>> -#define DSC_VER_MIN_SHIFT 4
>> -#define DSC_VER_MAJ (0x1 << 0)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204)
>> -#define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
>> -#define DSC_BPP(bpp) ((bpp) << 0)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208)
>> -#define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
>> -#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
>> -#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C)
>> -#define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
>> -#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
>> -#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210)
>> -#define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
>> -#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
>> -#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214)
>> -#define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
>> -#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
>> -#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218)
>> -#define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
>> -#define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24)
>> -#define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16)
>> -#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
>> -#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C)
>> -#define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
>> -#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
>> -#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220)
>> -#define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
>> -#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
>> -#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224)
>> -#define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
>> -#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
>> -#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228)
>> -#define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
>> -#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
>> -#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
>> -#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
>> -#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C)
>> -#define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260)
>> -#define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264)
>> -#define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268)
>> -#define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C)
>> -#define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
>> -
>> -#define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270)
>> -#define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70)
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
>> -#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
>> -#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
>> -#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
>> - _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
>> -#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
>> - _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
>> -#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20)
>> -#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
>> -#define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0)
>> -
>> -/* Icelake Rate Control Buffer Threshold Registers */
>> -#define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
>> -#define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
>> -#define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30)
>> -#define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4)
>> -#define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254)
>> -#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4)
>> -#define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354)
>> -#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4)
>> -#define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454)
>> -#define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4)
>> -#define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554)
>> -#define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4)
>> -#define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_RC_BUF_THRESH_0_PB, \
>> - _ICL_DSC0_RC_BUF_THRESH_0_PC)
>> -#define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \
>> - _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC)
>> -#define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_RC_BUF_THRESH_0_PB, \
>> - _ICL_DSC1_RC_BUF_THRESH_0_PC)
>> -#define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \
>> - _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC)
>> -
>> -#define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238)
>> -#define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4)
>> -#define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38)
>> -#define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4)
>> -#define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C)
>> -#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4)
>> -#define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C)
>> -#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4)
>> -#define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C)
>> -#define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4)
>> -#define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C)
>> -#define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4)
>> -#define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_RC_BUF_THRESH_1_PB, \
>> - _ICL_DSC0_RC_BUF_THRESH_1_PC)
>> -#define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \
>> - _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC)
>> -#define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_RC_BUF_THRESH_1_PB, \
>> - _ICL_DSC1_RC_BUF_THRESH_1_PC)
>> -#define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \
>> - _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC)
>> -
>> #define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
>> #define MODULAR_FIA_MASK (1 << 4)
>> #define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
>> --
>> 2.39.1
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-03-06 16:27 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-01 15:19 [Intel-gfx] [PATCH] drm/i915/display: split out DSC and DSS registers Jani Nikula
2023-03-01 22:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-03-04 21:23 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-03-06 14:50 ` [Intel-gfx] [PATCH] " Ville Syrjälä
2023-03-06 16:24 ` Jani Nikula
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