* [PATCHv3 0/2] DP2.0 SDP CRC16 for 128/132b link layer
@ 2023-03-02 8:15 ` Arun R Murthy
0 siblings, 0 replies; 19+ messages in thread
From: Arun R Murthy @ 2023-03-02 8:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Arun R Murthy
*** BLURB HERE ***
Arun R Murthy (2):
drm: Add SDP Error Detection Configuration Register
i915/display/dp: SDP CRC16 for 128b132b link layer
.../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++++
include/drm/display/drm_dp.h | 3 +++
2 files changed, 15 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCHv3 0/2] DP2.0 SDP CRC16 for 128/132b link layer
@ 2023-03-02 8:15 ` Arun R Murthy
0 siblings, 0 replies; 19+ messages in thread
From: Arun R Murthy @ 2023-03-02 8:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula
*** BLURB HERE ***
Arun R Murthy (2):
drm: Add SDP Error Detection Configuration Register
i915/display/dp: SDP CRC16 for 128b132b link layer
.../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++++
include/drm/display/drm_dp.h | 3 +++
2 files changed, 15 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [RESEND PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
2023-03-02 8:15 ` [Intel-gfx] " Arun R Murthy
@ 2023-03-02 8:15 ` Arun R Murthy
-1 siblings, 0 replies; 19+ messages in thread
From: Arun R Murthy @ 2023-03-02 8:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Arun R Murthy
DP2.0 E11 defines a new register to facilitate SDP error detection by a
128B/132B capable DPRX device.
v2: Update the macro name to reflect the DP spec(Harry)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
include/drm/display/drm_dp.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 632376c291db..358db4a9f167 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -692,6 +692,9 @@
# define DP_FEC_LANE_2_SELECT (2 << 4)
# define DP_FEC_LANE_3_SELECT (3 << 4)
+#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */
+#define DP_SDP_CRC16_128B132B_EN BIT(0)
+
#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [RESEND PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register
@ 2023-03-02 8:15 ` Arun R Murthy
0 siblings, 0 replies; 19+ messages in thread
From: Arun R Murthy @ 2023-03-02 8:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Harry Wentland
DP2.0 E11 defines a new register to facilitate SDP error detection by a
128B/132B capable DPRX device.
v2: Update the macro name to reflect the DP spec(Harry)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
include/drm/display/drm_dp.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index 632376c291db..358db4a9f167 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -692,6 +692,9 @@
# define DP_FEC_LANE_2_SELECT (2 << 4)
# define DP_FEC_LANE_3_SELECT (3 << 4)
+#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */
+#define DP_SDP_CRC16_128B132B_EN BIT(0)
+
#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCHv4 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
2023-03-02 8:15 ` [Intel-gfx] " Arun R Murthy
@ 2023-03-02 8:15 ` Arun R Murthy
-1 siblings, 0 replies; 19+ messages in thread
From: Arun R Murthy @ 2023-03-02 8:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Arun R Murthy
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping this write.
Corrective actions on SDP corruption is yet to be defined.
v2: Moved the CRC enable to link training init(Jani N)
v3: Moved crc enable to ddi pre enable <Jani N>
v4: Separate function for SDP CRC16 (Jani N)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++
.../drm/i915/display/intel_dp_link_training.c | 20 +++++++++++++++++++
.../drm/i915/display/intel_dp_link_training.h | 2 ++
3 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e5979427b38b..127b3035f92d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2519,6 +2519,10 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ if (HAS_DP20(dev_priv))
+ intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
+ crtc_state);
+
if (DISPLAY_VER(dev_priv) >= 12)
tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
else
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 3d3efcf02011..35d31e4efab9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1454,3 +1454,23 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
if (!passed)
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
}
+
+void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ /*
+ * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
+ * disable SDP CRC. This is applicable for Display version 13.
+ * Default value of bit 31 is '0' hence discarding the write
+ * TODO: Corrective actions on SDP corruption yet to be defined
+ */
+ if (intel_dp_is_uhbr(crtc_state))
+ /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
+ drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_SDP_ERROR_DETECTION_CONFIGURATION,
+ DP_SDP_CRC16_128B132B_EN);
+
+ drm_dbg_kms(&i915->drm, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 7fa1c0833096..2c8f2775891b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -39,4 +39,6 @@ static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
}
+void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_DP_LINK_TRAINING_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCHv4 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
@ 2023-03-02 8:15 ` Arun R Murthy
0 siblings, 0 replies; 19+ messages in thread
From: Arun R Murthy @ 2023-03-02 8:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula
Enable SDP error detection configuration, this will set CRC16 in
128b/132b link layer.
For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
added to enable/disable SDP CRC applicable for DP2.0 only, but the
default value of this bit will enable CRC16 in 128b/132b hence
skipping this write.
Corrective actions on SDP corruption is yet to be defined.
v2: Moved the CRC enable to link training init(Jani N)
v3: Moved crc enable to ddi pre enable <Jani N>
v4: Separate function for SDP CRC16 (Jani N)
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++
.../drm/i915/display/intel_dp_link_training.c | 20 +++++++++++++++++++
.../drm/i915/display/intel_dp_link_training.h | 2 ++
3 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e5979427b38b..127b3035f92d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2519,6 +2519,10 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ if (HAS_DP20(dev_priv))
+ intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
+ crtc_state);
+
if (DISPLAY_VER(dev_priv) >= 12)
tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
else
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 3d3efcf02011..35d31e4efab9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1454,3 +1454,23 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
if (!passed)
intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
}
+
+void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ /*
+ * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
+ * disable SDP CRC. This is applicable for Display version 13.
+ * Default value of bit 31 is '0' hence discarding the write
+ * TODO: Corrective actions on SDP corruption yet to be defined
+ */
+ if (intel_dp_is_uhbr(crtc_state))
+ /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
+ drm_dp_dpcd_writeb(&intel_dp->aux,
+ DP_SDP_ERROR_DETECTION_CONFIGURATION,
+ DP_SDP_CRC16_128B132B_EN);
+
+ drm_dbg_kms(&i915->drm, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index 7fa1c0833096..2c8f2775891b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -39,4 +39,6 @@ static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
}
+void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_DP_LINK_TRAINING_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for DP2.0 SDP CRC16 for 128/132b link layer (rev3)
2023-03-02 8:15 ` [Intel-gfx] " Arun R Murthy
` (2 preceding siblings ...)
(?)
@ 2023-03-02 8:46 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-03-02 8:46 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx
== Series Details ==
Series: DP2.0 SDP CRC16 for 128/132b link layer (rev3)
URL : https://patchwork.freedesktop.org/series/113134/
State : warning
== Summary ==
Error: patch https://patchwork.freedesktop.org/api/1.0/series/113134/revisions/3/mbox/ not found
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for DP2.0 SDP CRC16 for 128/132b link layer (rev3)
2023-03-02 8:15 ` [Intel-gfx] " Arun R Murthy
` (3 preceding siblings ...)
(?)
@ 2023-03-02 8:57 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-03-02 8:57 UTC (permalink / raw)
To: Murthy, Arun R; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7094 bytes --]
== Series Details ==
Series: DP2.0 SDP CRC16 for 128/132b link layer (rev3)
URL : https://patchwork.freedesktop.org/series/113134/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12800 -> Patchwork_113134v3
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_113134v3 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_113134v3, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/index.html
Participating hosts (38 -> 3)
------------------------------
ERROR: It appears as if the changes made in Patchwork_113134v3 prevented too many machines from booting.
Additional (1): bat-atsm-1
Missing (36): fi-rkl-11600 bat-adls-5 bat-dg1-5 bat-adlp-6 fi-apl-guc fi-snb-2520m bat-rpls-1 fi-blb-e6850 bat-rpls-2 fi-skl-6600u fi-bsw-n3050 bat-dg2-8 bat-adlm-1 bat-dg2-9 fi-ilk-650 fi-hsw-4770 bat-adln-1 fi-ivb-3770 bat-jsl-3 bat-rplp-1 fi-elk-e7500 bat-dg2-11 fi-bsw-nick fi-kbl-7567u bat-dg1-7 bat-kbl-2 bat-adlp-9 fi-skl-guc fi-cfl-8700k fi-glk-j4005 bat-jsl-1 fi-tgl-1115g4 fi-cfl-guc fi-kbl-guc fi-kbl-x1275 fi-cfl-8109u
Known issues
------------
Here are the changes found in Patchwork_113134v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@eof:
- bat-atsm-1: NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@fbdev@eof.html
* igt@gem_mmap@basic:
- bat-atsm-1: NOTRUN -> [SKIP][2] ([i915#4083])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@gem_mmap@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-atsm-1: NOTRUN -> [SKIP][3] ([i915#4077]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-atsm-1: NOTRUN -> [SKIP][4] ([i915#4079]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-atsm-1: NOTRUN -> [SKIP][5] ([i915#6621])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@i915_pm_rps@basic-api.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-atsm-1: NOTRUN -> [SKIP][6] ([i915#6645])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@size-max:
- bat-atsm-1: NOTRUN -> [SKIP][7] ([i915#6077]) +36 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@kms_addfb_basic@size-max.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- bat-atsm-1: NOTRUN -> [SKIP][8] ([i915#6078]) +19 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
* igt@kms_flip@basic-plain-flip:
- bat-atsm-1: NOTRUN -> [SKIP][9] ([i915#6166]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@kms_flip@basic-plain-flip.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-atsm-1: NOTRUN -> [SKIP][10] ([i915#6093]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_pipe_crc_basic@hang-read-crc:
- bat-atsm-1: NOTRUN -> [SKIP][11] ([i915#1836]) +6 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@kms_pipe_crc_basic@hang-read-crc.html
* igt@kms_prop_blob@basic:
- bat-atsm-1: NOTRUN -> [SKIP][12] ([i915#7357])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@kms_prop_blob@basic.html
* igt@kms_psr@sprite_plane_onoff:
- bat-atsm-1: NOTRUN -> [SKIP][13] ([i915#1072]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-atsm-1: NOTRUN -> [SKIP][14] ([i915#6094])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-atsm-1: NOTRUN -> [SKIP][15] ([fdo#109295] / [i915#6078])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-atsm-1: NOTRUN -> [SKIP][16] ([fdo#109295] / [i915#4077]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-write:
- bat-atsm-1: NOTRUN -> [SKIP][17] ([fdo#109295]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/bat-atsm-1/igt@prime_vgem@basic-write.html
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#6077]: https://gitlab.freedesktop.org/drm/intel/issues/6077
[i915#6078]: https://gitlab.freedesktop.org/drm/intel/issues/6078
[i915#6093]: https://gitlab.freedesktop.org/drm/intel/issues/6093
[i915#6094]: https://gitlab.freedesktop.org/drm/intel/issues/6094
[i915#6166]: https://gitlab.freedesktop.org/drm/intel/issues/6166
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7357]: https://gitlab.freedesktop.org/drm/intel/issues/7357
Build changes
-------------
* Linux: CI_DRM_12800 -> Patchwork_113134v3
CI-20190529: 20190529
CI_DRM_12800: 648a70b879daba67a6e7c69f191e846c4e043854 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7178: ffe3f6670b91ab975f90799ab3fd0941b6eae019 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113134v3: 648a70b879daba67a6e7c69f191e846c4e043854 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
7fa3d77e2e1e i915/display/dp: SDP CRC16 for 128b132b link layer
fe6f3da451ff drm: Add SDP Error Detection Configuration Register
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v3/index.html
[-- Attachment #2: Type: text/html, Size: 8428 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCHv4 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
2023-03-02 8:15 ` [Intel-gfx] " Arun R Murthy
@ 2023-03-07 9:09 ` Jani Nikula
-1 siblings, 0 replies; 19+ messages in thread
From: Jani Nikula @ 2023-03-07 9:09 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx, dri-devel; +Cc: Arun R Murthy
On Thu, 02 Mar 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> Enable SDP error detection configuration, this will set CRC16 in
> 128b/132b link layer.
> For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
> added to enable/disable SDP CRC applicable for DP2.0 only, but the
> default value of this bit will enable CRC16 in 128b/132b hence
> skipping this write.
> Corrective actions on SDP corruption is yet to be defined.
>
> v2: Moved the CRC enable to link training init(Jani N)
> v3: Moved crc enable to ddi pre enable <Jani N>
> v4: Separate function for SDP CRC16 (Jani N)
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++
> .../drm/i915/display/intel_dp_link_training.c | 20 +++++++++++++++++++
> .../drm/i915/display/intel_dp_link_training.h | 2 ++
> 3 files changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index e5979427b38b..127b3035f92d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2519,6 +2519,10 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> + if (HAS_DP20(dev_priv))
> + intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
> + crtc_state);
> +
> if (DISPLAY_VER(dev_priv) >= 12)
> tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
> else
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 3d3efcf02011..35d31e4efab9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1454,3 +1454,23 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
> if (!passed)
> intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
> }
> +
> +void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + /*
> + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
> + * disable SDP CRC. This is applicable for Display version 13.
> + * Default value of bit 31 is '0' hence discarding the write
> + * TODO: Corrective actions on SDP corruption yet to be defined
> + */
> + if (intel_dp_is_uhbr(crtc_state))
> + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
> + drm_dp_dpcd_writeb(&intel_dp->aux,
> + DP_SDP_ERROR_DETECTION_CONFIGURATION,
> + DP_SDP_CRC16_128B132B_EN);
> +
> + drm_dbg_kms(&i915->drm, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> index 7fa1c0833096..2c8f2775891b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> @@ -39,4 +39,6 @@ static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
> return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
> }
>
> +void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state);
> #endif /* __INTEL_DP_LINK_TRAINING_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCHv4 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
@ 2023-03-07 9:09 ` Jani Nikula
0 siblings, 0 replies; 19+ messages in thread
From: Jani Nikula @ 2023-03-07 9:09 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx, dri-devel
On Thu, 02 Mar 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
> Enable SDP error detection configuration, this will set CRC16 in
> 128b/132b link layer.
> For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
> added to enable/disable SDP CRC applicable for DP2.0 only, but the
> default value of this bit will enable CRC16 in 128b/132b hence
> skipping this write.
> Corrective actions on SDP corruption is yet to be defined.
>
> v2: Moved the CRC enable to link training init(Jani N)
> v3: Moved crc enable to ddi pre enable <Jani N>
> v4: Separate function for SDP CRC16 (Jani N)
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++
> .../drm/i915/display/intel_dp_link_training.c | 20 +++++++++++++++++++
> .../drm/i915/display/intel_dp_link_training.h | 2 ++
> 3 files changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index e5979427b38b..127b3035f92d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2519,6 +2519,10 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> + if (HAS_DP20(dev_priv))
> + intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
> + crtc_state);
> +
> if (DISPLAY_VER(dev_priv) >= 12)
> tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
> else
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 3d3efcf02011..35d31e4efab9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -1454,3 +1454,23 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
> if (!passed)
> intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
> }
> +
> +void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + /*
> + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
> + * disable SDP CRC. This is applicable for Display version 13.
> + * Default value of bit 31 is '0' hence discarding the write
> + * TODO: Corrective actions on SDP corruption yet to be defined
> + */
> + if (intel_dp_is_uhbr(crtc_state))
> + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
> + drm_dp_dpcd_writeb(&intel_dp->aux,
> + DP_SDP_ERROR_DETECTION_CONFIGURATION,
> + DP_SDP_CRC16_128B132B_EN);
> +
> + drm_dbg_kms(&i915->drm, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> index 7fa1c0833096..2c8f2775891b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> @@ -39,4 +39,6 @@ static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
> return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
> }
>
> +void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state);
> #endif /* __INTEL_DP_LINK_TRAINING_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCHv4 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
2023-03-07 9:09 ` [Intel-gfx] " Jani Nikula
@ 2023-03-07 9:10 ` Jani Nikula
-1 siblings, 0 replies; 19+ messages in thread
From: Jani Nikula @ 2023-03-07 9:10 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx, dri-devel; +Cc: Arun R Murthy
On Tue, 07 Mar 2023, Jani Nikula <jani.nikula@intel.com> wrote:
> On Thu, 02 Mar 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>> Enable SDP error detection configuration, this will set CRC16 in
>> 128b/132b link layer.
>> For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
>> added to enable/disable SDP CRC applicable for DP2.0 only, but the
>> default value of this bit will enable CRC16 in 128b/132b hence
>> skipping this write.
>> Corrective actions on SDP corruption is yet to be defined.
>>
>> v2: Moved the CRC enable to link training init(Jani N)
>> v3: Moved crc enable to ddi pre enable <Jani N>
>> v4: Separate function for SDP CRC16 (Jani N)
>>
>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
PS. I've queued retest on this one, need to wait for results before
applying.
>
>> ---
>> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++
>> .../drm/i915/display/intel_dp_link_training.c | 20 +++++++++++++++++++
>> .../drm/i915/display/intel_dp_link_training.h | 2 ++
>> 3 files changed, 26 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index e5979427b38b..127b3035f92d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2519,6 +2519,10 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
>> {
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>
>> + if (HAS_DP20(dev_priv))
>> + intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
>> + crtc_state);
>> +
>> if (DISPLAY_VER(dev_priv) >= 12)
>> tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
>> else
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 3d3efcf02011..35d31e4efab9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -1454,3 +1454,23 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
>> if (!passed)
>> intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
>> }
>> +
>> +void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
>> + const struct intel_crtc_state *crtc_state)
>> +{
>> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> +
>> + /*
>> + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
>> + * disable SDP CRC. This is applicable for Display version 13.
>> + * Default value of bit 31 is '0' hence discarding the write
>> + * TODO: Corrective actions on SDP corruption yet to be defined
>> + */
>> + if (intel_dp_is_uhbr(crtc_state))
>> + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
>> + drm_dp_dpcd_writeb(&intel_dp->aux,
>> + DP_SDP_ERROR_DETECTION_CONFIGURATION,
>> + DP_SDP_CRC16_128B132B_EN);
>> +
>> + drm_dbg_kms(&i915->drm, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> index 7fa1c0833096..2c8f2775891b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> @@ -39,4 +39,6 @@ static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
>> return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
>> }
>>
>> +void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
>> + const struct intel_crtc_state *crtc_state);
>> #endif /* __INTEL_DP_LINK_TRAINING_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCHv4 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
@ 2023-03-07 9:10 ` Jani Nikula
0 siblings, 0 replies; 19+ messages in thread
From: Jani Nikula @ 2023-03-07 9:10 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx, dri-devel
On Tue, 07 Mar 2023, Jani Nikula <jani.nikula@intel.com> wrote:
> On Thu, 02 Mar 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>> Enable SDP error detection configuration, this will set CRC16 in
>> 128b/132b link layer.
>> For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
>> added to enable/disable SDP CRC applicable for DP2.0 only, but the
>> default value of this bit will enable CRC16 in 128b/132b hence
>> skipping this write.
>> Corrective actions on SDP corruption is yet to be defined.
>>
>> v2: Moved the CRC enable to link training init(Jani N)
>> v3: Moved crc enable to ddi pre enable <Jani N>
>> v4: Separate function for SDP CRC16 (Jani N)
>>
>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
PS. I've queued retest on this one, need to wait for results before
applying.
>
>> ---
>> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++
>> .../drm/i915/display/intel_dp_link_training.c | 20 +++++++++++++++++++
>> .../drm/i915/display/intel_dp_link_training.h | 2 ++
>> 3 files changed, 26 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index e5979427b38b..127b3035f92d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2519,6 +2519,10 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
>> {
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>
>> + if (HAS_DP20(dev_priv))
>> + intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
>> + crtc_state);
>> +
>> if (DISPLAY_VER(dev_priv) >= 12)
>> tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
>> else
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> index 3d3efcf02011..35d31e4efab9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>> @@ -1454,3 +1454,23 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
>> if (!passed)
>> intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
>> }
>> +
>> +void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
>> + const struct intel_crtc_state *crtc_state)
>> +{
>> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>> +
>> + /*
>> + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
>> + * disable SDP CRC. This is applicable for Display version 13.
>> + * Default value of bit 31 is '0' hence discarding the write
>> + * TODO: Corrective actions on SDP corruption yet to be defined
>> + */
>> + if (intel_dp_is_uhbr(crtc_state))
>> + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
>> + drm_dp_dpcd_writeb(&intel_dp->aux,
>> + DP_SDP_ERROR_DETECTION_CONFIGURATION,
>> + DP_SDP_CRC16_128B132B_EN);
>> +
>> + drm_dbg_kms(&i915->drm, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> index 7fa1c0833096..2c8f2775891b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>> @@ -39,4 +39,6 @@ static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
>> return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
>> }
>>
>> +void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
>> + const struct intel_crtc_state *crtc_state);
>> #endif /* __INTEL_DP_LINK_TRAINING_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for DP2.0 SDP CRC16 for 128/132b link layer (rev5)
2023-03-02 8:15 ` [Intel-gfx] " Arun R Murthy
` (4 preceding siblings ...)
(?)
@ 2023-03-14 13:52 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-03-14 13:52 UTC (permalink / raw)
To: Murthy, Arun R; +Cc: intel-gfx
== Series Details ==
Series: DP2.0 SDP CRC16 for 128/132b link layer (rev5)
URL : https://patchwork.freedesktop.org/series/113134/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for DP2.0 SDP CRC16 for 128/132b link layer (rev5)
2023-03-02 8:15 ` [Intel-gfx] " Arun R Murthy
` (5 preceding siblings ...)
(?)
@ 2023-03-14 15:10 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-03-14 15:10 UTC (permalink / raw)
To: Murthy, Arun R; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3761 bytes --]
== Series Details ==
Series: DP2.0 SDP CRC16 for 128/132b link layer (rev5)
URL : https://patchwork.freedesktop.org/series/113134/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12829 -> Patchwork_113134v5
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/index.html
Participating hosts (36 -> 32)
------------------------------
Missing (4): fi-kbl-soraka bat-rpls-2 fi-snb-2520m fi-bsw-n3050
Known issues
------------
Here are the changes found in Patchwork_113134v5 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@dmabuf@all-tests@dma_fence:
- bat-rplp-1: [PASS][1] -> [DMESG-FAIL][2] ([i915#8216])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/bat-rplp-1/igt@dmabuf@all-tests@dma_fence.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/bat-rplp-1/igt@dmabuf@all-tests@dma_fence.html
* igt@dmabuf@all-tests@sanitycheck:
- bat-rplp-1: [PASS][3] -> [ABORT][4] ([i915#8216])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/bat-rplp-1/igt@dmabuf@all-tests@sanitycheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/bat-rplp-1/igt@dmabuf@all-tests@sanitycheck.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-1: NOTRUN -> [SKIP][5] ([i915#7828])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/bat-rpls-1/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-1: NOTRUN -> [SKIP][6] ([i915#1845])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/bat-rpls-1/igt@kms_pipe_crc_basic@suspend-read-crc.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: [ABORT][7] ([i915#6687] / [i915#7978]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
#### Warnings ####
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][9] ([i915#6367]) -> [DMESG-FAIL][10] ([i915#6367] / [i915#7996])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/bat-rpls-1/igt@i915_selftest@live@slpc.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/bat-rpls-1/igt@i915_selftest@live@slpc.html
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
[i915#8216]: https://gitlab.freedesktop.org/drm/intel/issues/8216
Build changes
-------------
* Linux: CI_DRM_12829 -> Patchwork_113134v5
CI-20190529: 20190529
CI_DRM_12829: d947159409deea43f404f35cc758740c714c8888 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7185: 6707461ddb214bb8a75c5fcf2747941c9d9b11ae @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113134v5: d947159409deea43f404f35cc758740c714c8888 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
d8663bc967f4 i915/display/dp: SDP CRC16 for 128b132b link layer
950cffbd5160 drm: Add SDP Error Detection Configuration Register
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/index.html
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for DP2.0 SDP CRC16 for 128/132b link layer (rev5)
2023-03-02 8:15 ` [Intel-gfx] " Arun R Murthy
` (6 preceding siblings ...)
(?)
@ 2023-03-15 18:58 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2023-03-15 18:58 UTC (permalink / raw)
To: Murthy, Arun R; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 22353 bytes --]
== Series Details ==
Series: DP2.0 SDP CRC16 for 128/132b link layer (rev5)
URL : https://patchwork.freedesktop.org/series/113134/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12829_full -> Patchwork_113134v5_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (8 -> 8)
------------------------------
Additional (1): shard-rkl0
Missing (1): shard-tglu0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_113134v5_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_suspend@basic-s3-without-i915:
- {shard-tglu}: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-tglu-5/igt@i915_suspend@basic-s3-without-i915.html
* {igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling}:
- {shard-tglu}: NOTRUN -> [SKIP][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-tglu-10/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling.html
Known issues
------------
Here are the changes found in Patchwork_113134v5_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-glk8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_lmem_swapping@heavy-random:
- shard-apl: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-apl2/igt@gem_lmem_swapping@heavy-random.html
* igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][6] ([fdo#109271]) +16 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-apl2/igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#72])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-glk1/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-glk3/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: NOTRUN -> [ABORT][9] ([i915#180])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
#### Possible fixes ####
* igt@drm_fdinfo@virtual-idle:
- {shard-rkl}: [FAIL][10] ([i915#7742]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-4/igt@drm_fdinfo@virtual-idle.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-4/igt@drm_fdinfo@virtual-idle.html
* igt@drm_read@invalid-buffer:
- {shard-tglu}: [SKIP][12] ([i915#1845]) -> [PASS][13] +3 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-tglu-6/igt@drm_read@invalid-buffer.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-tglu-2/igt@drm_read@invalid-buffer.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][14] ([i915#6268]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-tglu-6/igt@gem_ctx_exec@basic-nohangcheck.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-tglu-9/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@suspend:
- {shard-rkl}: [FAIL][16] ([i915#5115] / [i915#7052]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-3/igt@gem_eio@suspend.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-1/igt@gem_eio@suspend.html
* igt@gem_exec_balancer@fairslice:
- {shard-rkl}: [SKIP][18] ([i915#6259]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-5/igt@gem_exec_balancer@fairslice.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-2/igt@gem_exec_balancer@fairslice.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][20] ([i915#2842]) -> [PASS][21] +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- {shard-tglu}: [FAIL][22] ([i915#2842]) -> [PASS][23] +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-tglu-3/igt@gem_exec_fair@basic-throttle@rcs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-tglu-7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_reloc@basic-cpu-noreloc:
- {shard-rkl}: [SKIP][24] ([i915#3281]) -> [PASS][25] +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-4/igt@gem_exec_reloc@basic-cpu-noreloc.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-5/igt@gem_exec_reloc@basic-cpu-noreloc.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- {shard-dg1}: [DMESG-WARN][26] ([i915#4936]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_readwrite@beyond-eob:
- {shard-rkl}: [SKIP][28] ([i915#3282]) -> [PASS][29] +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-1/igt@gem_readwrite@beyond-eob.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-5/igt@gem_readwrite@beyond-eob.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [ABORT][30] ([i915#5566]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-apl2/igt@gen9_exec_parse@allowed-single.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-apl1/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@valid-registers:
- {shard-rkl}: [SKIP][32] ([i915#2527]) -> [PASS][33] +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-1/igt@gen9_exec_parse@valid-registers.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-5/igt@gen9_exec_parse@valid-registers.html
* {igt@i915_pm_dc@dc5-dpms-negative}:
- {shard-tglu}: [SKIP][34] ([i915#8018]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-tglu-6/igt@i915_pm_dc@dc5-dpms-negative.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-tglu-6/igt@i915_pm_dc@dc5-dpms-negative.html
* igt@i915_pm_dc@dc6-dpms:
- {shard-rkl}: [SKIP][36] ([i915#3361]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-5/igt@i915_pm_dc@dc6-dpms.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@system-suspend:
- {shard-rkl}: [FAIL][38] ([fdo#103375]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-3/igt@i915_pm_rpm@system-suspend.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-1/igt@i915_pm_rpm@system-suspend.html
* igt@i915_pm_rpm@system-suspend-modeset:
- {shard-rkl}: [SKIP][40] ([fdo#109308]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-3/igt@i915_pm_rpm@system-suspend-modeset.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-6/igt@i915_pm_rpm@system-suspend-modeset.html
* igt@i915_suspend@forcewake:
- shard-apl: [ABORT][42] ([i915#180]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-apl4/igt@i915_suspend@forcewake.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-apl2/igt@i915_suspend@forcewake.html
* igt@kms_atomic@atomic_plane_damage:
- {shard-rkl}: [SKIP][44] ([i915#4098]) -> [PASS][45] +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-3/igt@kms_atomic@atomic_plane_damage.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-6/igt@kms_atomic@atomic_plane_damage.html
* igt@kms_atomic@plane-overlay-legacy:
- {shard-rkl}: [SKIP][46] ([i915#1845] / [i915#4098]) -> [PASS][47] +23 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-1/igt@kms_atomic@plane-overlay-legacy.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-6/igt@kms_atomic@plane-overlay-legacy.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- {shard-tglu}: [SKIP][48] ([i915#1845] / [i915#7651]) -> [PASS][49] +26 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-tglu-6/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-tglu-6/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cursor_legacy@torture-bo@pipe-c:
- {shard-tglu}: [INCOMPLETE][50] ([i915#8011]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-tglu-1/igt@kms_cursor_legacy@torture-bo@pipe-c.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-tglu-9/igt@kms_cursor_legacy@torture-bo@pipe-c.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite:
- {shard-tglu}: [SKIP][52] ([i915#1849]) -> [PASS][53] +9 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-tglu-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-tglu-4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- {shard-rkl}: [SKIP][54] ([i915#1849] / [i915#4098]) -> [PASS][55] +22 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_psr@cursor_mmap_cpu:
- {shard-rkl}: [SKIP][56] ([i915#1072]) -> [PASS][57] +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-1/igt@kms_psr@cursor_mmap_cpu.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-6/igt@kms_psr@cursor_mmap_cpu.html
* igt@perf@mi-rpc:
- {shard-rkl}: [SKIP][58] ([i915#2434]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12829/shard-rkl-4/igt@perf@mi-rpc.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/shard-rkl-5/igt@perf@mi-rpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5115]: https://gitlab.freedesktop.org/drm/intel/issues/5115
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5431]: https://gitlab.freedesktop.org/drm/intel/issues/5431
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6259]: https://gitlab.freedesktop.org/drm/intel/issues/6259
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7330]: https://gitlab.freedesktop.org/drm/intel/issues/7330
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8018]: https://gitlab.freedesktop.org/drm/intel/issues/8018
[i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
[i915#8154]: https://gitlab.freedesktop.org/drm/intel/issues/8154
[i915#8275]: https://gitlab.freedesktop.org/drm/intel/issues/8275
Build changes
-------------
* Linux: CI_DRM_12829 -> Patchwork_113134v5
CI-20190529: 20190529
CI_DRM_12829: d947159409deea43f404f35cc758740c714c8888 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7185: 6707461ddb214bb8a75c5fcf2747941c9d9b11ae @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113134v5: d947159409deea43f404f35cc758740c714c8888 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113134v5/index.html
[-- Attachment #2: Type: text/html, Size: 16425 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCHv4 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
2023-03-07 9:10 ` [Intel-gfx] " Jani Nikula
@ 2023-03-21 14:49 ` Jani Nikula
-1 siblings, 0 replies; 19+ messages in thread
From: Jani Nikula @ 2023-03-21 14:49 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx, dri-devel; +Cc: Arun R Murthy
On Tue, 07 Mar 2023, Jani Nikula <jani.nikula@intel.com> wrote:
> On Tue, 07 Mar 2023, Jani Nikula <jani.nikula@intel.com> wrote:
>> On Thu, 02 Mar 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>>> Enable SDP error detection configuration, this will set CRC16 in
>>> 128b/132b link layer.
>>> For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
>>> added to enable/disable SDP CRC applicable for DP2.0 only, but the
>>> default value of this bit will enable CRC16 in 128b/132b hence
>>> skipping this write.
>>> Corrective actions on SDP corruption is yet to be defined.
>>>
>>> v2: Moved the CRC enable to link training init(Jani N)
>>> v3: Moved crc enable to ddi pre enable <Jani N>
>>> v4: Separate function for SDP CRC16 (Jani N)
>>>
>>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>>
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> PS. I've queued retest on this one, need to wait for results before
> applying.
And finally pushed to drm-intel-next. Thanks for the patches & patience.
BR,
Jani.
>
>
>>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++
>>> .../drm/i915/display/intel_dp_link_training.c | 20 +++++++++++++++++++
>>> .../drm/i915/display/intel_dp_link_training.h | 2 ++
>>> 3 files changed, 26 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>>> index e5979427b38b..127b3035f92d 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>>> @@ -2519,6 +2519,10 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
>>> {
>>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>>
>>> + if (HAS_DP20(dev_priv))
>>> + intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
>>> + crtc_state);
>>> +
>>> if (DISPLAY_VER(dev_priv) >= 12)
>>> tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
>>> else
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>> index 3d3efcf02011..35d31e4efab9 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>> @@ -1454,3 +1454,23 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
>>> if (!passed)
>>> intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
>>> }
>>> +
>>> +void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
>>> + const struct intel_crtc_state *crtc_state)
>>> +{
>>> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>>> +
>>> + /*
>>> + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
>>> + * disable SDP CRC. This is applicable for Display version 13.
>>> + * Default value of bit 31 is '0' hence discarding the write
>>> + * TODO: Corrective actions on SDP corruption yet to be defined
>>> + */
>>> + if (intel_dp_is_uhbr(crtc_state))
>>> + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
>>> + drm_dp_dpcd_writeb(&intel_dp->aux,
>>> + DP_SDP_ERROR_DETECTION_CONFIGURATION,
>>> + DP_SDP_CRC16_128B132B_EN);
>>> +
>>> + drm_dbg_kms(&i915->drm, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
>>> +}
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>>> index 7fa1c0833096..2c8f2775891b 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>>> @@ -39,4 +39,6 @@ static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
>>> return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
>>> }
>>>
>>> +void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
>>> + const struct intel_crtc_state *crtc_state);
>>> #endif /* __INTEL_DP_LINK_TRAINING_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCHv4 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer
@ 2023-03-21 14:49 ` Jani Nikula
0 siblings, 0 replies; 19+ messages in thread
From: Jani Nikula @ 2023-03-21 14:49 UTC (permalink / raw)
To: Arun R Murthy, intel-gfx, dri-devel
On Tue, 07 Mar 2023, Jani Nikula <jani.nikula@intel.com> wrote:
> On Tue, 07 Mar 2023, Jani Nikula <jani.nikula@intel.com> wrote:
>> On Thu, 02 Mar 2023, Arun R Murthy <arun.r.murthy@intel.com> wrote:
>>> Enable SDP error detection configuration, this will set CRC16 in
>>> 128b/132b link layer.
>>> For Display version 13 a hardware bit31 in register VIDEO_DIP_CTL is
>>> added to enable/disable SDP CRC applicable for DP2.0 only, but the
>>> default value of this bit will enable CRC16 in 128b/132b hence
>>> skipping this write.
>>> Corrective actions on SDP corruption is yet to be defined.
>>>
>>> v2: Moved the CRC enable to link training init(Jani N)
>>> v3: Moved crc enable to ddi pre enable <Jani N>
>>> v4: Separate function for SDP CRC16 (Jani N)
>>>
>>> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
>>
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> PS. I've queued retest on this one, need to wait for results before
> applying.
And finally pushed to drm-intel-next. Thanks for the patches & patience.
BR,
Jani.
>
>
>>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++++
>>> .../drm/i915/display/intel_dp_link_training.c | 20 +++++++++++++++++++
>>> .../drm/i915/display/intel_dp_link_training.h | 2 ++
>>> 3 files changed, 26 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>>> index e5979427b38b..127b3035f92d 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>>> @@ -2519,6 +2519,10 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
>>> {
>>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>>
>>> + if (HAS_DP20(dev_priv))
>>> + intel_dp_128b132b_sdp_crc16(enc_to_intel_dp(encoder),
>>> + crtc_state);
>>> +
>>> if (DISPLAY_VER(dev_priv) >= 12)
>>> tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
>>> else
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>> index 3d3efcf02011..35d31e4efab9 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
>>> @@ -1454,3 +1454,23 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
>>> if (!passed)
>>> intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
>>> }
>>> +
>>> +void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
>>> + const struct intel_crtc_state *crtc_state)
>>> +{
>>> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>>> +
>>> + /*
>>> + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
>>> + * disable SDP CRC. This is applicable for Display version 13.
>>> + * Default value of bit 31 is '0' hence discarding the write
>>> + * TODO: Corrective actions on SDP corruption yet to be defined
>>> + */
>>> + if (intel_dp_is_uhbr(crtc_state))
>>> + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
>>> + drm_dp_dpcd_writeb(&intel_dp->aux,
>>> + DP_SDP_ERROR_DETECTION_CONFIGURATION,
>>> + DP_SDP_CRC16_128B132B_EN);
>>> +
>>> + drm_dbg_kms(&i915->drm, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
>>> +}
>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>>> index 7fa1c0833096..2c8f2775891b 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
>>> @@ -39,4 +39,6 @@ static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
>>> return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
>>> }
>>>
>>> +void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
>>> + const struct intel_crtc_state *crtc_state);
>>> #endif /* __INTEL_DP_LINK_TRAINING_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCHv3 0/2] DP2.0 SDP CRC16 for 128/132b link layer
@ 2023-02-14 9:34 Arun R Murthy
0 siblings, 0 replies; 19+ messages in thread
From: Arun R Murthy @ 2023-02-14 9:34 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Arun R Murthy
*** BLURB HERE ***
Arun R Murthy (2):
drm: Add SDP Error Detection Configuration Register
i915/display/dp: SDP CRC16 for 128b132b link layer
.../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++++
include/drm/display/drm_dp.h | 3 +++
2 files changed, 15 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCHv3 0/2] DP2.0 SDP CRC16 for 128/132b link layer
2023-01-20 6:15 [PATCHv2 " Arun R Murthy
@ 2023-02-07 5:26 ` Arun R Murthy
0 siblings, 0 replies; 19+ messages in thread
From: Arun R Murthy @ 2023-02-07 5:26 UTC (permalink / raw)
To: intel-gfx, dri-devel, jani.nikula; +Cc: Arun R Murthy
*** BLURB HERE ***
Arun R Murthy (2):
drm: Add SDP Error Detection Configuration Register
i915/display/dp: SDP CRC16 for 128b132b link layer
.../gpu/drm/i915/display/intel_dp_link_training.c | 12 ++++++++++++
include/drm/display/drm_dp.h | 3 +++
2 files changed, 15 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2023-03-21 14:49 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-02 8:15 [PATCHv3 0/2] DP2.0 SDP CRC16 for 128/132b link layer Arun R Murthy
2023-03-02 8:15 ` [Intel-gfx] " Arun R Murthy
2023-03-02 8:15 ` [RESEND PATCHv2 1/2] drm: Add SDP Error Detection Configuration Register Arun R Murthy
2023-03-02 8:15 ` [Intel-gfx] " Arun R Murthy
2023-03-02 8:15 ` [PATCHv4 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer Arun R Murthy
2023-03-02 8:15 ` [Intel-gfx] " Arun R Murthy
2023-03-07 9:09 ` Jani Nikula
2023-03-07 9:09 ` [Intel-gfx] " Jani Nikula
2023-03-07 9:10 ` Jani Nikula
2023-03-07 9:10 ` [Intel-gfx] " Jani Nikula
2023-03-21 14:49 ` Jani Nikula
2023-03-21 14:49 ` [Intel-gfx] " Jani Nikula
2023-03-02 8:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for DP2.0 SDP CRC16 for 128/132b link layer (rev3) Patchwork
2023-03-02 8:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-03-14 13:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for DP2.0 SDP CRC16 for 128/132b link layer (rev5) Patchwork
2023-03-14 15:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-15 18:58 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-02-14 9:34 [PATCHv3 0/2] DP2.0 SDP CRC16 for 128/132b link layer Arun R Murthy
2023-01-20 6:15 [PATCHv2 " Arun R Murthy
2023-02-07 5:26 ` [PATCHv3 " Arun R Murthy
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