From: Jonathan Cameron <Jonathan.Cameron@huawei.com> To: <qemu-devel@nongnu.org>, Michael Tsirkin <mst@redhat.com>, Fan Ni <fan.ni@samsung.com> Cc: linux-cxl@vger.kernel.org, linuxarm@huawei.com, "Ira Weiny" <ira.weiny@intel.com>, "Alison Schofield" <alison.schofield@intel.com>, "Michael Roth" <michael.roth@amd.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, "Dave Jiang" <dave.jiang@intel.com>, "Markus Armbruster" <armbru@redhat.com>, "Daniel P . Berrangé" <berrange@redhat.com>, "Eric Blake" <eblake@redhat.com>, "Mike Maslenkin" <mike.maslenkin@gmail.com>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, "Thomas Huth" <thuth@redhat.com> Subject: [RESEND PATCH v6 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Date: Thu, 2 Mar 2023 13:37:02 +0000 [thread overview] Message-ID: <20230302133709.30373-2-Jonathan.Cameron@huawei.com> (raw) In-Reply-To: <20230302133709.30373-1-Jonathan.Cameron@huawei.com> This register in AER should be both writeable and should have a default value with a couple of the errors masked including the Uncorrectable Internal Error used by CXL for it's error reporting. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> --- hw/pci/pcie_aer.c | 4 ++++ include/hw/pci/pcie_regs.h | 3 +++ 2 files changed, 7 insertions(+) diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c index 9a19be44ae..909e027d99 100644 --- a/hw/pci/pcie_aer.c +++ b/hw/pci/pcie_aer.c @@ -112,6 +112,10 @@ int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset, pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS, PCI_ERR_UNC_SUPPORTED); + pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK, + PCI_ERR_UNC_MASK_DEFAULT); + pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK, + PCI_ERR_UNC_SUPPORTED); pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER, PCI_ERR_UNC_SEVERITY_DEFAULT); diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 963dc2e170..6ec4785448 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -155,6 +155,9 @@ typedef enum PCIExpLinkWidth { PCI_ERR_UNC_ATOP_EBLOCKED | \ PCI_ERR_UNC_TLP_PRF_BLOCKED) +#define PCI_ERR_UNC_MASK_DEFAULT (PCI_ERR_UNC_INTN | \ + PCI_ERR_UNC_TLP_PRF_BLOCKED) + #define PCI_ERR_UNC_SEVERITY_DEFAULT (PCI_ERR_UNC_DLP | \ PCI_ERR_UNC_SDN | \ PCI_ERR_UNC_FCP | \ -- 2.37.2
WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org> To: <qemu-devel@nongnu.org>, Michael Tsirkin <mst@redhat.com>, Fan Ni <fan.ni@samsung.com> Cc: linux-cxl@vger.kernel.org, linuxarm@huawei.com, "Ira Weiny" <ira.weiny@intel.com>, "Alison Schofield" <alison.schofield@intel.com>, "Michael Roth" <michael.roth@amd.com>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, "Dave Jiang" <dave.jiang@intel.com>, "Markus Armbruster" <armbru@redhat.com>, "Daniel P . Berrangé" <berrange@redhat.com>, "Eric Blake" <eblake@redhat.com>, "Mike Maslenkin" <mike.maslenkin@gmail.com>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, "Thomas Huth" <thuth@redhat.com> Subject: [RESEND PATCH v6 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Date: Thu, 2 Mar 2023 13:37:02 +0000 [thread overview] Message-ID: <20230302133709.30373-2-Jonathan.Cameron@huawei.com> (raw) In-Reply-To: <20230302133709.30373-1-Jonathan.Cameron@huawei.com> This register in AER should be both writeable and should have a default value with a couple of the errors masked including the Uncorrectable Internal Error used by CXL for it's error reporting. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> --- hw/pci/pcie_aer.c | 4 ++++ include/hw/pci/pcie_regs.h | 3 +++ 2 files changed, 7 insertions(+) diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c index 9a19be44ae..909e027d99 100644 --- a/hw/pci/pcie_aer.c +++ b/hw/pci/pcie_aer.c @@ -112,6 +112,10 @@ int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset, pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS, PCI_ERR_UNC_SUPPORTED); + pci_set_long(dev->config + offset + PCI_ERR_UNCOR_MASK, + PCI_ERR_UNC_MASK_DEFAULT); + pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_MASK, + PCI_ERR_UNC_SUPPORTED); pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER, PCI_ERR_UNC_SEVERITY_DEFAULT); diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 963dc2e170..6ec4785448 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -155,6 +155,9 @@ typedef enum PCIExpLinkWidth { PCI_ERR_UNC_ATOP_EBLOCKED | \ PCI_ERR_UNC_TLP_PRF_BLOCKED) +#define PCI_ERR_UNC_MASK_DEFAULT (PCI_ERR_UNC_INTN | \ + PCI_ERR_UNC_TLP_PRF_BLOCKED) + #define PCI_ERR_UNC_SEVERITY_DEFAULT (PCI_ERR_UNC_DLP | \ PCI_ERR_UNC_SDN | \ PCI_ERR_UNC_FCP | \ -- 2.37.2
next prev parent reply other threads:[~2023-03-02 13:37 UTC|newest] Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-02 13:37 [RESEND PATCH v6 0/8] hw/cxl: RAS error emulation and injection Jonathan Cameron 2023-03-02 13:37 ` Jonathan Cameron via 2023-03-02 13:37 ` Jonathan Cameron [this message] 2023-03-02 13:37 ` [RESEND PATCH v6 1/8] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register Jonathan Cameron via [not found] ` <CGME20230306172108uscas1p1b96bacd10b120f3fd93c3309ac2b8880@uscas1p1.samsung.com> 2023-03-06 17:21 ` Fan Ni 2023-05-02 8:54 ` Michael S. Tsirkin 2023-03-02 13:37 ` [RESEND PATCH v6 2/8] hw/pci/aer: Add missing routing for AER errors Jonathan Cameron 2023-03-02 13:37 ` Jonathan Cameron via [not found] ` <CGME20230306172146uscas1p2e9446294d8b850a1bbcd0e0d4302b603@uscas1p2.samsung.com> 2023-03-06 17:21 ` Fan Ni 2023-03-02 13:37 ` [RESEND PATCH v6 3/8] hw/pci-bridge/cxl_root_port: Wire up AER Jonathan Cameron 2023-03-02 13:37 ` Jonathan Cameron via [not found] ` <CGME20230306173743uscas1p1f464bb8a53859927472b90f7f9e017c9@uscas1p1.samsung.com> 2023-03-06 17:37 ` Fan Ni 2023-03-02 13:37 ` [RESEND PATCH v6 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI Jonathan Cameron 2023-03-02 13:37 ` Jonathan Cameron via [not found] ` <CGME20230306175133uscas1p163baf7c881e373c5a5db0805fa83fdd1@uscas1p1.samsung.com> 2023-03-06 17:51 ` Fan Ni 2023-03-02 13:37 ` [RESEND PATCH v6 5/8] hw/mem/cxl-type3: Add AER extended capability Jonathan Cameron 2023-03-02 13:37 ` Jonathan Cameron via [not found] ` <CGME20230306175209uscas1p2be7df0b3ca2b2002f1a47b2125e35c08@uscas1p2.samsung.com> 2023-03-06 17:52 ` Fan Ni 2023-03-02 13:37 ` [RESEND PATCH v6 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks Jonathan Cameron 2023-03-02 13:37 ` Jonathan Cameron via [not found] ` <CGME20230306175232uscas1p18d8022fab9b5bd5a10a367a6b597aee4@uscas1p1.samsung.com> 2023-03-06 17:52 ` Fan Ni 2023-03-02 13:37 ` [RESEND PATCH v6 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use Jonathan Cameron 2023-03-02 13:37 ` Jonathan Cameron via [not found] ` <CGME20230306175327uscas1p15622b1d859a60b2cc5d9df70182e35fe@uscas1p1.samsung.com> 2023-03-06 17:53 ` Fan Ni 2023-03-02 13:37 ` [RESEND PATCH v6 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support Jonathan Cameron 2023-03-02 13:37 ` Jonathan Cameron via 2023-03-07 17:22 ` Michael S. Tsirkin [not found] ` <CGME20230307192642uscas1p15caa7ff372247e96544265fbd031d83e@uscas1p1.samsung.com> 2023-03-07 19:26 ` Fan Ni 2023-03-08 1:34 ` Michael S. Tsirkin 2023-03-14 11:53 ` Jonathan Cameron 2023-03-14 11:53 ` Jonathan Cameron via 2023-03-06 21:57 ` [RESEND PATCH v6 0/8] hw/cxl: RAS error emulation and injection Michael S. Tsirkin
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