* [PATCH v3 0/2] arm64/sysregs: Generate definitions fine grained traps control registers
@ 2023-03-23 20:44 ` Mark Brown
0 siblings, 0 replies; 16+ messages in thread
From: Mark Brown @ 2023-03-23 20:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Joey Gouly, Anshuman Khandual, linux-arm-kernel, linux-kernel,
Mark Brown
This series converts the fine grained traps control registers to
automatic generation as per DDI0601 2022-12.
I previously sent this with just the read/write trap registers, there
have been no changes in that patch since v2.
Changes in v3:
- Add HFGITR_EL2.
Changes in v2:
- Correct naming of nPIRE0_EL1.
- Link to v1: https://lore.kernel.org/r/20230306-arm64-fgt-reg-gen-v1-1-95bc0c97cfed@kernel.org
---
Mark Brown (2):
arm64/sysreg: Convert HFG[RW]TR_EL2 to automatic generation
arm64/sysreg: Convert HFGITR_EL2 to automatic generation
arch/arm64/include/asm/sysreg.h | 9 ---
arch/arm64/tools/sysreg | 140 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 140 insertions(+), 9 deletions(-)
---
base-commit: e8d018dd0257f744ca50a729e3d042cf2ec9da65
change-id: 20230306-arm64-fgt-reg-gen-bf2735efa4df
Best regards,
--
Mark Brown <broonie@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 0/2] arm64/sysregs: Generate definitions fine grained traps control registers
@ 2023-03-23 20:44 ` Mark Brown
0 siblings, 0 replies; 16+ messages in thread
From: Mark Brown @ 2023-03-23 20:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Joey Gouly, Anshuman Khandual, linux-arm-kernel, linux-kernel,
Mark Brown
This series converts the fine grained traps control registers to
automatic generation as per DDI0601 2022-12.
I previously sent this with just the read/write trap registers, there
have been no changes in that patch since v2.
Changes in v3:
- Add HFGITR_EL2.
Changes in v2:
- Correct naming of nPIRE0_EL1.
- Link to v1: https://lore.kernel.org/r/20230306-arm64-fgt-reg-gen-v1-1-95bc0c97cfed@kernel.org
---
Mark Brown (2):
arm64/sysreg: Convert HFG[RW]TR_EL2 to automatic generation
arm64/sysreg: Convert HFGITR_EL2 to automatic generation
arch/arm64/include/asm/sysreg.h | 9 ---
arch/arm64/tools/sysreg | 140 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 140 insertions(+), 9 deletions(-)
---
base-commit: e8d018dd0257f744ca50a729e3d042cf2ec9da65
change-id: 20230306-arm64-fgt-reg-gen-bf2735efa4df
Best regards,
--
Mark Brown <broonie@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/2] arm64/sysreg: Convert HFG[RW]TR_EL2 to automatic generation
2023-03-23 20:44 ` Mark Brown
@ 2023-03-23 20:44 ` Mark Brown
-1 siblings, 0 replies; 16+ messages in thread
From: Mark Brown @ 2023-03-23 20:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Joey Gouly, Anshuman Khandual, linux-arm-kernel, linux-kernel,
Mark Brown
Convert the fine grained traps read and write control registers to
automatic generation as per DDI0601 2022-12. No functional changes.
Reviewed-by: Joey Gouly <joey.gouly@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 8 -----
arch/arm64/tools/sysreg | 75 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 75 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 9e3ecba3c4e6..e5ca9ece1606 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -419,8 +419,6 @@
#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
#define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
-#define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4)
-#define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5)
#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
#define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
@@ -758,12 +756,6 @@
#define ICH_VTR_TDS_SHIFT 19
#define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)
-/* HFG[WR]TR_EL2 bit definitions */
-#define HFGxTR_EL2_nTPIDR2_EL0_SHIFT 55
-#define HFGxTR_EL2_nTPIDR2_EL0_MASK BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT)
-#define HFGxTR_EL2_nSMPRI_EL1_SHIFT 54
-#define HFGxTR_EL2_nSMPRI_EL1_MASK BIT_MASK(HFGxTR_EL2_nSMPRI_EL1_SHIFT)
-
#define ARM64_FEATURE_FIELD_BITS 4
/* Defined for compatibility only, do not add new users. */
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index dd5a9c7e310f..60829a9409f0 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1866,6 +1866,81 @@ Field 1 ZA
Field 0 SM
EndSysreg
+SysregFields HFGxTR_EL2
+Field 63 nAMIAIR2_EL1
+Field 62 nMAIR2_EL1
+Field 61 nS2POR_EL1
+Field 60 nPOR_EL1
+Field 59 nPOR_EL0
+Field 58 nPIR_EL1
+Field 57 nPIRE0_EL1
+Field 56 nRCWMASK_EL1
+Field 55 nTPIDR2_EL0
+Field 54 nSMPRI_EL1
+Field 53 nGCS_EL1
+Field 52 nGCS_EL0
+Res0 51
+Field 50 nACCDATA_EL1
+Field 49 ERXADDR_EL1
+Field 48 EXRPFGCDN_EL1
+Field 47 EXPFGCTL_EL1
+Field 46 EXPFGF_EL1
+Field 45 ERXMISCn_EL1
+Field 44 ERXSTATUS_EL1
+Field 43 ERXCTLR_EL1
+Field 42 ERXFR_EL1
+Field 41 ERRSELR_EL1
+Field 40 ERRIDR_EL1
+Field 39 ICC_IGRPENn_EL1
+Field 38 VBAR_EL1
+Field 37 TTBR1_EL1
+Field 36 TTBR0_EL1
+Field 35 TPIDR_EL0
+Field 34 TPIDRRO_EL0
+Field 33 TPIDR_EL1
+Field 32 TCR_EL1
+Field 31 SCTXNUM_EL0
+Field 30 SCTXNUM_EL1
+Field 29 SCTLR_EL1
+Field 28 REVIDR_EL1
+Field 27 PAR_EL1
+Field 26 MPIDR_EL1
+Field 25 MIDR_EL1
+Field 24 MAIR_EL1
+Field 23 LORSA_EL1
+Field 22 LORN_EL1
+Field 21 LORID_EL1
+Field 20 LOREA_EL1
+Field 19 LORC_EL1
+Field 18 ISR_EL1
+Field 17 FAR_EL1
+Field 16 ESR_EL1
+Field 15 DCZID_EL0
+Field 14 CTR_EL0
+Field 13 CSSELR_EL1
+Field 12 CPACR_EL1
+Field 11 CONTEXTIDR_EL1
+Field 10 CLIDR_EL1
+Field 9 CCSIDR_EL1
+Field 8 APIBKey
+Field 7 APIAKey
+Field 6 APGAKey
+Field 5 APDBKey
+Field 4 APDAKey
+Field 3 AMAIR_EL1
+Field 2 AIDR_EL1
+Field 1 AFSR1_EL1
+Field 0 AFSR0_EL1
+EndSysregFields
+
+Sysreg HFGRTR_EL2 3 4 1 1 4
+Fields HFGxTR_EL2
+EndSysreg
+
+Sysreg HFGWTR_EL2 3 4 1 1 5
+Fields HFGxTR_EL2
+EndSysreg
+
Sysreg ZCR_EL2 3 4 1 2 0
Fields ZCR_ELx
EndSysreg
--
2.30.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 1/2] arm64/sysreg: Convert HFG[RW]TR_EL2 to automatic generation
@ 2023-03-23 20:44 ` Mark Brown
0 siblings, 0 replies; 16+ messages in thread
From: Mark Brown @ 2023-03-23 20:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Joey Gouly, Anshuman Khandual, linux-arm-kernel, linux-kernel,
Mark Brown
Convert the fine grained traps read and write control registers to
automatic generation as per DDI0601 2022-12. No functional changes.
Reviewed-by: Joey Gouly <joey.gouly@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 8 -----
arch/arm64/tools/sysreg | 75 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 75 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 9e3ecba3c4e6..e5ca9ece1606 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -419,8 +419,6 @@
#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
#define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
-#define SYS_HFGRTR_EL2 sys_reg(3, 4, 1, 1, 4)
-#define SYS_HFGWTR_EL2 sys_reg(3, 4, 1, 1, 5)
#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
#define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
@@ -758,12 +756,6 @@
#define ICH_VTR_TDS_SHIFT 19
#define ICH_VTR_TDS_MASK (1 << ICH_VTR_TDS_SHIFT)
-/* HFG[WR]TR_EL2 bit definitions */
-#define HFGxTR_EL2_nTPIDR2_EL0_SHIFT 55
-#define HFGxTR_EL2_nTPIDR2_EL0_MASK BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT)
-#define HFGxTR_EL2_nSMPRI_EL1_SHIFT 54
-#define HFGxTR_EL2_nSMPRI_EL1_MASK BIT_MASK(HFGxTR_EL2_nSMPRI_EL1_SHIFT)
-
#define ARM64_FEATURE_FIELD_BITS 4
/* Defined for compatibility only, do not add new users. */
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index dd5a9c7e310f..60829a9409f0 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1866,6 +1866,81 @@ Field 1 ZA
Field 0 SM
EndSysreg
+SysregFields HFGxTR_EL2
+Field 63 nAMIAIR2_EL1
+Field 62 nMAIR2_EL1
+Field 61 nS2POR_EL1
+Field 60 nPOR_EL1
+Field 59 nPOR_EL0
+Field 58 nPIR_EL1
+Field 57 nPIRE0_EL1
+Field 56 nRCWMASK_EL1
+Field 55 nTPIDR2_EL0
+Field 54 nSMPRI_EL1
+Field 53 nGCS_EL1
+Field 52 nGCS_EL0
+Res0 51
+Field 50 nACCDATA_EL1
+Field 49 ERXADDR_EL1
+Field 48 EXRPFGCDN_EL1
+Field 47 EXPFGCTL_EL1
+Field 46 EXPFGF_EL1
+Field 45 ERXMISCn_EL1
+Field 44 ERXSTATUS_EL1
+Field 43 ERXCTLR_EL1
+Field 42 ERXFR_EL1
+Field 41 ERRSELR_EL1
+Field 40 ERRIDR_EL1
+Field 39 ICC_IGRPENn_EL1
+Field 38 VBAR_EL1
+Field 37 TTBR1_EL1
+Field 36 TTBR0_EL1
+Field 35 TPIDR_EL0
+Field 34 TPIDRRO_EL0
+Field 33 TPIDR_EL1
+Field 32 TCR_EL1
+Field 31 SCTXNUM_EL0
+Field 30 SCTXNUM_EL1
+Field 29 SCTLR_EL1
+Field 28 REVIDR_EL1
+Field 27 PAR_EL1
+Field 26 MPIDR_EL1
+Field 25 MIDR_EL1
+Field 24 MAIR_EL1
+Field 23 LORSA_EL1
+Field 22 LORN_EL1
+Field 21 LORID_EL1
+Field 20 LOREA_EL1
+Field 19 LORC_EL1
+Field 18 ISR_EL1
+Field 17 FAR_EL1
+Field 16 ESR_EL1
+Field 15 DCZID_EL0
+Field 14 CTR_EL0
+Field 13 CSSELR_EL1
+Field 12 CPACR_EL1
+Field 11 CONTEXTIDR_EL1
+Field 10 CLIDR_EL1
+Field 9 CCSIDR_EL1
+Field 8 APIBKey
+Field 7 APIAKey
+Field 6 APGAKey
+Field 5 APDBKey
+Field 4 APDAKey
+Field 3 AMAIR_EL1
+Field 2 AIDR_EL1
+Field 1 AFSR1_EL1
+Field 0 AFSR0_EL1
+EndSysregFields
+
+Sysreg HFGRTR_EL2 3 4 1 1 4
+Fields HFGxTR_EL2
+EndSysreg
+
+Sysreg HFGWTR_EL2 3 4 1 1 5
+Fields HFGxTR_EL2
+EndSysreg
+
Sysreg ZCR_EL2 3 4 1 2 0
Fields ZCR_ELx
EndSysreg
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/2] arm64/sysreg: Convert HFGITR_EL2 to automatic generation
2023-03-23 20:44 ` Mark Brown
@ 2023-03-23 20:44 ` Mark Brown
-1 siblings, 0 replies; 16+ messages in thread
From: Mark Brown @ 2023-03-23 20:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Joey Gouly, Anshuman Khandual, linux-arm-kernel, linux-kernel,
Mark Brown
Automatically generate the Hypervisor Fine-Grained Instruction Trap
Register as per DDI0601 2022-12, currently we only have a definition for
the register name not any of the contents. No functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 65 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index e5ca9ece1606..c48b41c9b0cc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -419,7 +419,6 @@
#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
#define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
-#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
#define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
#define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 60829a9409f0..c06097a8b921 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1941,6 +1941,71 @@ Sysreg HFGWTR_EL2 3 4 1 1 5
Fields HFGxTR_EL2
EndSysreg
+Sysreg HFGITR_EL2 3 4 1 1 6
+Res0 63:61
+Field 60 COSPRCTX
+Field 59 nGCSEPP
+Field 58 nGCSSTR_EL1
+Field 57 nGCSPUSHM_EL1
+Field 56 nBRBIALL
+Field 55 nBRBINJ
+Field 54 DCCVAC
+Field 53 SVC_EL1
+Field 52 SVC_EL0
+Field 51 ERET
+Field 50 CPPRCTX
+Field 49 DVPRCTX
+Field 48 CFPRCTX
+Field 47 TLBIVAALE1
+Field 46 TLBIVALE1
+Field 45 TLBIVAAE1
+Field 44 TLBSIDE1
+Field 43 TLBIVAE1
+Field 42 TLBIVMALLE1
+Field 41 TLBIRVAALE1
+Field 40 TLBIRVALE1
+Field 39 TLBIRVAAE1
+Field 38 TLBIRVAE1
+Field 37 TLBIRVAALE1IS
+Field 36 TLBIRVALE1IS
+Field 35 TLBIRVAAE1IS
+Field 34 TLBIRAALE1IS
+Field 33 TLBIVAALE1IS
+Field 32 TLBIVALE1IS
+Field 31 TLBIVAAE1IS
+Field 30 TLBIASIDE1IS
+Field 29 TLBIVAE1IS
+Field 28 TLBIVVMALLE1IS
+Field 27 TLBIRVAALE1OS
+Field 26 TLBIRVALE1OS
+Field 25 TLBIRVAAE1OS
+Field 24 TLBIRVAE1OS
+Field 23 TLBIVAALE1OS
+Field 22 TLBIVALE1OS
+Field 21 TLBIVAAE1OS
+Field 20 TLVIASIDE1OS
+Field 19 TLBIVAE1OS
+Field 18 TLBIVMALLE1OS
+Field 17 ATS1E1WP
+Field 16 ATS1E1RP
+Field 15 ATS1E0W
+Field 14 ATS1E0R
+Field 13 ATS1E1W
+Field 12 ATS1E1R
+Field 11 DCZVA
+Field 10 DCCIVAC
+Field 9 DCCVADP
+Field 8 DCCVAP
+Field 7 DCCVAU
+Field 6 DCCISW
+Field 5 DCCSW
+Field 4 DCISW
+Field 3 DCIVAC
+Field 2 ICIVAU
+Field 1 ICIALLU
+Field 0 ICIALLUIS
+EndSysreg
+
Sysreg ZCR_EL2 3 4 1 2 0
Fields ZCR_ELx
EndSysreg
--
2.30.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/2] arm64/sysreg: Convert HFGITR_EL2 to automatic generation
@ 2023-03-23 20:44 ` Mark Brown
0 siblings, 0 replies; 16+ messages in thread
From: Mark Brown @ 2023-03-23 20:44 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Joey Gouly, Anshuman Khandual, linux-arm-kernel, linux-kernel,
Mark Brown
Automatically generate the Hypervisor Fine-Grained Instruction Trap
Register as per DDI0601 2022-12, currently we only have a definition for
the register name not any of the contents. No functional change.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/sysreg.h | 1 -
arch/arm64/tools/sysreg | 65 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 65 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index e5ca9ece1606..c48b41c9b0cc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -419,7 +419,6 @@
#define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
#define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
#define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
-#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
#define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
#define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 60829a9409f0..c06097a8b921 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1941,6 +1941,71 @@ Sysreg HFGWTR_EL2 3 4 1 1 5
Fields HFGxTR_EL2
EndSysreg
+Sysreg HFGITR_EL2 3 4 1 1 6
+Res0 63:61
+Field 60 COSPRCTX
+Field 59 nGCSEPP
+Field 58 nGCSSTR_EL1
+Field 57 nGCSPUSHM_EL1
+Field 56 nBRBIALL
+Field 55 nBRBINJ
+Field 54 DCCVAC
+Field 53 SVC_EL1
+Field 52 SVC_EL0
+Field 51 ERET
+Field 50 CPPRCTX
+Field 49 DVPRCTX
+Field 48 CFPRCTX
+Field 47 TLBIVAALE1
+Field 46 TLBIVALE1
+Field 45 TLBIVAAE1
+Field 44 TLBSIDE1
+Field 43 TLBIVAE1
+Field 42 TLBIVMALLE1
+Field 41 TLBIRVAALE1
+Field 40 TLBIRVALE1
+Field 39 TLBIRVAAE1
+Field 38 TLBIRVAE1
+Field 37 TLBIRVAALE1IS
+Field 36 TLBIRVALE1IS
+Field 35 TLBIRVAAE1IS
+Field 34 TLBIRAALE1IS
+Field 33 TLBIVAALE1IS
+Field 32 TLBIVALE1IS
+Field 31 TLBIVAAE1IS
+Field 30 TLBIASIDE1IS
+Field 29 TLBIVAE1IS
+Field 28 TLBIVVMALLE1IS
+Field 27 TLBIRVAALE1OS
+Field 26 TLBIRVALE1OS
+Field 25 TLBIRVAAE1OS
+Field 24 TLBIRVAE1OS
+Field 23 TLBIVAALE1OS
+Field 22 TLBIVALE1OS
+Field 21 TLBIVAAE1OS
+Field 20 TLVIASIDE1OS
+Field 19 TLBIVAE1OS
+Field 18 TLBIVMALLE1OS
+Field 17 ATS1E1WP
+Field 16 ATS1E1RP
+Field 15 ATS1E0W
+Field 14 ATS1E0R
+Field 13 ATS1E1W
+Field 12 ATS1E1R
+Field 11 DCZVA
+Field 10 DCCIVAC
+Field 9 DCCVADP
+Field 8 DCCVAP
+Field 7 DCCVAU
+Field 6 DCCISW
+Field 5 DCCSW
+Field 4 DCISW
+Field 3 DCIVAC
+Field 2 ICIVAU
+Field 1 ICIALLU
+Field 0 ICIALLUIS
+EndSysreg
+
Sysreg ZCR_EL2 3 4 1 2 0
Fields ZCR_ELx
EndSysreg
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/2] arm64/sysreg: Convert HFGITR_EL2 to automatic generation
2023-03-23 20:44 ` Mark Brown
@ 2023-04-06 14:46 ` Will Deacon
-1 siblings, 0 replies; 16+ messages in thread
From: Will Deacon @ 2023-04-06 14:46 UTC (permalink / raw)
To: Mark Brown
Cc: Catalin Marinas, Joey Gouly, Anshuman Khandual, linux-arm-kernel,
linux-kernel
On Thu, Mar 23, 2023 at 08:44:54PM +0000, Mark Brown wrote:
> Automatically generate the Hypervisor Fine-Grained Instruction Trap
> Register as per DDI0601 2022-12, currently we only have a definition for
> the register name not any of the contents. No functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 1 -
> arch/arm64/tools/sysreg | 65 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 65 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index e5ca9ece1606..c48b41c9b0cc 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -419,7 +419,6 @@
> #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
> #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
> #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
> -#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
> #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
>
> #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 60829a9409f0..c06097a8b921 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -1941,6 +1941,71 @@ Sysreg HFGWTR_EL2 3 4 1 1 5
> Fields HFGxTR_EL2
> EndSysreg
>
> +Sysreg HFGITR_EL2 3 4 1 1 6
> +Res0 63:61
> +Field 60 COSPRCTX
> +Field 59 nGCSEPP
> +Field 58 nGCSSTR_EL1
> +Field 57 nGCSPUSHM_EL1
These aren't in the Arm ARM afaict ^^^
> +Field 56 nBRBIALL
> +Field 55 nBRBINJ
> +Field 54 DCCVAC
> +Field 53 SVC_EL1
> +Field 52 SVC_EL0
> +Field 51 ERET
> +Field 50 CPPRCTX
> +Field 49 DVPRCTX
> +Field 48 CFPRCTX
> +Field 47 TLBIVAALE1
> +Field 46 TLBIVALE1
> +Field 45 TLBIVAAE1
> +Field 44 TLBSIDE1
This is a typo ^^^
(I stopped reviewing at this point)
Can't we generate this file from the architecture xml? That would hopefully
avoid typos like this and make review less tedious.
Will
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/2] arm64/sysreg: Convert HFGITR_EL2 to automatic generation
@ 2023-04-06 14:46 ` Will Deacon
0 siblings, 0 replies; 16+ messages in thread
From: Will Deacon @ 2023-04-06 14:46 UTC (permalink / raw)
To: Mark Brown
Cc: Catalin Marinas, Joey Gouly, Anshuman Khandual, linux-arm-kernel,
linux-kernel
On Thu, Mar 23, 2023 at 08:44:54PM +0000, Mark Brown wrote:
> Automatically generate the Hypervisor Fine-Grained Instruction Trap
> Register as per DDI0601 2022-12, currently we only have a definition for
> the register name not any of the contents. No functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 1 -
> arch/arm64/tools/sysreg | 65 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 65 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index e5ca9ece1606..c48b41c9b0cc 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -419,7 +419,6 @@
> #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
> #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
> #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
> -#define SYS_HFGITR_EL2 sys_reg(3, 4, 1, 1, 6)
> #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
>
> #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 60829a9409f0..c06097a8b921 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -1941,6 +1941,71 @@ Sysreg HFGWTR_EL2 3 4 1 1 5
> Fields HFGxTR_EL2
> EndSysreg
>
> +Sysreg HFGITR_EL2 3 4 1 1 6
> +Res0 63:61
> +Field 60 COSPRCTX
> +Field 59 nGCSEPP
> +Field 58 nGCSSTR_EL1
> +Field 57 nGCSPUSHM_EL1
These aren't in the Arm ARM afaict ^^^
> +Field 56 nBRBIALL
> +Field 55 nBRBINJ
> +Field 54 DCCVAC
> +Field 53 SVC_EL1
> +Field 52 SVC_EL0
> +Field 51 ERET
> +Field 50 CPPRCTX
> +Field 49 DVPRCTX
> +Field 48 CFPRCTX
> +Field 47 TLBIVAALE1
> +Field 46 TLBIVALE1
> +Field 45 TLBIVAAE1
> +Field 44 TLBSIDE1
This is a typo ^^^
(I stopped reviewing at this point)
Can't we generate this file from the architecture xml? That would hopefully
avoid typos like this and make review less tedious.
Will
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/2] arm64/sysreg: Convert HFGITR_EL2 to automatic generation
2023-04-06 14:46 ` Will Deacon
@ 2023-04-06 15:02 ` Mark Brown
-1 siblings, 0 replies; 16+ messages in thread
From: Mark Brown @ 2023-04-06 15:02 UTC (permalink / raw)
To: Will Deacon
Cc: Catalin Marinas, Joey Gouly, Anshuman Khandual, linux-arm-kernel,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1667 bytes --]
On Thu, Apr 06, 2023 at 03:46:54PM +0100, Will Deacon wrote:
> On Thu, Mar 23, 2023 at 08:44:54PM +0000, Mark Brown wrote:
> > Automatically generate the Hypervisor Fine-Grained Instruction Trap
> > Register as per DDI0601 2022-12, currently we only have a definition for
> > the register name not any of the contents. No functional change.
> > +Res0 63:61
> > +Field 60 COSPRCTX
> > +Field 59 nGCSEPP
> > +Field 58 nGCSSTR_EL1
> > +Field 57 nGCSPUSHM_EL1
> These aren't in the Arm ARM afaict ^^^
Yes, as mentioned in the cover letter these are as per DDI0601 2022-12,
the current at time of posting the patch latest release of the
architecture XML. They should appear in the next release of the ARM,
the XML is updated more frequently. The XML can be seen on the web
here:
https://developer.arm.com/documentation/ddi0601/2022-12/AArch64-Registers/HFGITR-EL2--Hypervisor-Fine-Grained-Instruction-Trap-Register?lang=en
> Can't we generate this file from the architecture xml? That would hopefully
> avoid typos like this and make review less tedious.
I agree that this seems like a sensible idea however there has
previously been pushback on the idea of providing tooling to do that,
and we would want to manually integrate the output of any such tool
since there are a number of cases where for legacy or usability reasons
we rename or combine fields. The cases where we use a Fields block to
cover identical ELx versions are another issue.
I also note that while the XML is viewable on the web AFAICT the only
directly downloadable version of the architecture XML available
externally is in PDF format which is not entirely helpful for this
purpose.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/2] arm64/sysreg: Convert HFGITR_EL2 to automatic generation
@ 2023-04-06 15:02 ` Mark Brown
0 siblings, 0 replies; 16+ messages in thread
From: Mark Brown @ 2023-04-06 15:02 UTC (permalink / raw)
To: Will Deacon
Cc: Catalin Marinas, Joey Gouly, Anshuman Khandual, linux-arm-kernel,
linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 1667 bytes --]
On Thu, Apr 06, 2023 at 03:46:54PM +0100, Will Deacon wrote:
> On Thu, Mar 23, 2023 at 08:44:54PM +0000, Mark Brown wrote:
> > Automatically generate the Hypervisor Fine-Grained Instruction Trap
> > Register as per DDI0601 2022-12, currently we only have a definition for
> > the register name not any of the contents. No functional change.
> > +Res0 63:61
> > +Field 60 COSPRCTX
> > +Field 59 nGCSEPP
> > +Field 58 nGCSSTR_EL1
> > +Field 57 nGCSPUSHM_EL1
> These aren't in the Arm ARM afaict ^^^
Yes, as mentioned in the cover letter these are as per DDI0601 2022-12,
the current at time of posting the patch latest release of the
architecture XML. They should appear in the next release of the ARM,
the XML is updated more frequently. The XML can be seen on the web
here:
https://developer.arm.com/documentation/ddi0601/2022-12/AArch64-Registers/HFGITR-EL2--Hypervisor-Fine-Grained-Instruction-Trap-Register?lang=en
> Can't we generate this file from the architecture xml? That would hopefully
> avoid typos like this and make review less tedious.
I agree that this seems like a sensible idea however there has
previously been pushback on the idea of providing tooling to do that,
and we would want to manually integrate the output of any such tool
since there are a number of cases where for legacy or usability reasons
we rename or combine fields. The cases where we use a Fields block to
cover identical ELx versions are another issue.
I also note that while the XML is viewable on the web AFAICT the only
directly downloadable version of the architecture XML available
externally is in PDF format which is not entirely helpful for this
purpose.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/2] arm64/sysreg: Convert HFGITR_EL2 to automatic generation
2023-04-06 15:02 ` Mark Brown
@ 2023-04-06 15:04 ` Will Deacon
-1 siblings, 0 replies; 16+ messages in thread
From: Will Deacon @ 2023-04-06 15:04 UTC (permalink / raw)
To: Mark Brown
Cc: Catalin Marinas, Joey Gouly, Anshuman Khandual, linux-arm-kernel,
linux-kernel
On Thu, Apr 06, 2023 at 04:02:18PM +0100, Mark Brown wrote:
> On Thu, Apr 06, 2023 at 03:46:54PM +0100, Will Deacon wrote:
> > On Thu, Mar 23, 2023 at 08:44:54PM +0000, Mark Brown wrote:
>
> > > Automatically generate the Hypervisor Fine-Grained Instruction Trap
> > > Register as per DDI0601 2022-12, currently we only have a definition for
> > > the register name not any of the contents. No functional change.
>
> > > +Res0 63:61
> > > +Field 60 COSPRCTX
> > > +Field 59 nGCSEPP
> > > +Field 58 nGCSSTR_EL1
> > > +Field 57 nGCSPUSHM_EL1
>
> > These aren't in the Arm ARM afaict ^^^
>
> Yes, as mentioned in the cover letter these are as per DDI0601 2022-12,
> the current at time of posting the patch latest release of the
> architecture XML. They should appear in the next release of the ARM,
> the XML is updated more frequently. The XML can be seen on the web
> here:
>
> https://developer.arm.com/documentation/ddi0601/2022-12/AArch64-Registers/HFGITR-EL2--Hypervisor-Fine-Grained-Instruction-Trap-Register?lang=en
Thanks -- I just wanted to check that they were final. Happy to trust that
xml.
> > Can't we generate this file from the architecture xml? That would hopefully
> > avoid typos like this and make review less tedious.
>
> I agree that this seems like a sensible idea however there has
> previously been pushback on the idea of providing tooling to do that,
> and we would want to manually integrate the output of any such tool
> since there are a number of cases where for legacy or usability reasons
> we rename or combine fields. The cases where we use a Fields block to
> cover identical ELx versions are another issue.
>
> I also note that while the XML is viewable on the web AFAICT the only
> directly downloadable version of the architecture XML available
> externally is in PDF format which is not entirely helpful for this
> purpose.
Sorry, I didn't mean to automate this in the tree, just that you could
do it locally when you generate the patch (as I suspect this must be
tedious for you to write out by hand too!). We've had a string of typos
in the definitions so far, and it would be nice to take steps to avoid
that for future changes.
Will
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/2] arm64/sysreg: Convert HFGITR_EL2 to automatic generation
@ 2023-04-06 15:04 ` Will Deacon
0 siblings, 0 replies; 16+ messages in thread
From: Will Deacon @ 2023-04-06 15:04 UTC (permalink / raw)
To: Mark Brown
Cc: Catalin Marinas, Joey Gouly, Anshuman Khandual, linux-arm-kernel,
linux-kernel
On Thu, Apr 06, 2023 at 04:02:18PM +0100, Mark Brown wrote:
> On Thu, Apr 06, 2023 at 03:46:54PM +0100, Will Deacon wrote:
> > On Thu, Mar 23, 2023 at 08:44:54PM +0000, Mark Brown wrote:
>
> > > Automatically generate the Hypervisor Fine-Grained Instruction Trap
> > > Register as per DDI0601 2022-12, currently we only have a definition for
> > > the register name not any of the contents. No functional change.
>
> > > +Res0 63:61
> > > +Field 60 COSPRCTX
> > > +Field 59 nGCSEPP
> > > +Field 58 nGCSSTR_EL1
> > > +Field 57 nGCSPUSHM_EL1
>
> > These aren't in the Arm ARM afaict ^^^
>
> Yes, as mentioned in the cover letter these are as per DDI0601 2022-12,
> the current at time of posting the patch latest release of the
> architecture XML. They should appear in the next release of the ARM,
> the XML is updated more frequently. The XML can be seen on the web
> here:
>
> https://developer.arm.com/documentation/ddi0601/2022-12/AArch64-Registers/HFGITR-EL2--Hypervisor-Fine-Grained-Instruction-Trap-Register?lang=en
Thanks -- I just wanted to check that they were final. Happy to trust that
xml.
> > Can't we generate this file from the architecture xml? That would hopefully
> > avoid typos like this and make review less tedious.
>
> I agree that this seems like a sensible idea however there has
> previously been pushback on the idea of providing tooling to do that,
> and we would want to manually integrate the output of any such tool
> since there are a number of cases where for legacy or usability reasons
> we rename or combine fields. The cases where we use a Fields block to
> cover identical ELx versions are another issue.
>
> I also note that while the XML is viewable on the web AFAICT the only
> directly downloadable version of the architecture XML available
> externally is in PDF format which is not entirely helpful for this
> purpose.
Sorry, I didn't mean to automate this in the tree, just that you could
do it locally when you generate the patch (as I suspect this must be
tedious for you to write out by hand too!). We've had a string of typos
in the definitions so far, and it would be nice to take steps to avoid
that for future changes.
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/2] arm64/sysreg: Convert HFGITR_EL2 to automatic generation
2023-04-06 15:04 ` Will Deacon
@ 2023-04-06 15:25 ` Mark Brown
-1 siblings, 0 replies; 16+ messages in thread
From: Mark Brown @ 2023-04-06 15:25 UTC (permalink / raw)
To: Will Deacon
Cc: Catalin Marinas, Joey Gouly, Anshuman Khandual, linux-arm-kernel,
linux-kernel
[-- Attachment #1.1: Type: text/plain, Size: 1795 bytes --]
On Thu, Apr 06, 2023 at 04:04:57PM +0100, Will Deacon wrote:
> On Thu, Apr 06, 2023 at 04:02:18PM +0100, Mark Brown wrote:
> > On Thu, Apr 06, 2023 at 03:46:54PM +0100, Will Deacon wrote:
> > > Can't we generate this file from the architecture xml? That would hopefully
> > > avoid typos like this and make review less tedious.
> > I agree that this seems like a sensible idea however there has
> > previously been pushback on the idea of providing tooling to do that,
> > and we would want to manually integrate the output of any such tool
> > since there are a number of cases where for legacy or usability reasons
> > we rename or combine fields. The cases where we use a Fields block to
> > cover identical ELx versions are another issue.
> > I also note that while the XML is viewable on the web AFAICT the only
> > directly downloadable version of the architecture XML available
> > externally is in PDF format which is not entirely helpful for this
> > purpose.
> Sorry, I didn't mean to automate this in the tree, just that you could
> do it locally when you generate the patch (as I suspect this must be
> tedious for you to write out by hand too!). We've had a string of typos
> in the definitions so far, and it would be nice to take steps to avoid
> that for future changes.
Yeah, normally it's not too bad (and it can be useful to make sure
you've actually looked at the entire register definition properly) but I
did just about get annoyed enough to write something locally while doing
this register. You could certainly get a good chunk of the way there,
especially for simple fields (enums would need manual naming IIRC) - if
it hadn't been for the pushback mentioned above combined with what's on
developer.arm.com I'd probably have got round to doing something
already.
[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/2] arm64/sysreg: Convert HFGITR_EL2 to automatic generation
@ 2023-04-06 15:25 ` Mark Brown
0 siblings, 0 replies; 16+ messages in thread
From: Mark Brown @ 2023-04-06 15:25 UTC (permalink / raw)
To: Will Deacon
Cc: Catalin Marinas, Joey Gouly, Anshuman Khandual, linux-arm-kernel,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1795 bytes --]
On Thu, Apr 06, 2023 at 04:04:57PM +0100, Will Deacon wrote:
> On Thu, Apr 06, 2023 at 04:02:18PM +0100, Mark Brown wrote:
> > On Thu, Apr 06, 2023 at 03:46:54PM +0100, Will Deacon wrote:
> > > Can't we generate this file from the architecture xml? That would hopefully
> > > avoid typos like this and make review less tedious.
> > I agree that this seems like a sensible idea however there has
> > previously been pushback on the idea of providing tooling to do that,
> > and we would want to manually integrate the output of any such tool
> > since there are a number of cases where for legacy or usability reasons
> > we rename or combine fields. The cases where we use a Fields block to
> > cover identical ELx versions are another issue.
> > I also note that while the XML is viewable on the web AFAICT the only
> > directly downloadable version of the architecture XML available
> > externally is in PDF format which is not entirely helpful for this
> > purpose.
> Sorry, I didn't mean to automate this in the tree, just that you could
> do it locally when you generate the patch (as I suspect this must be
> tedious for you to write out by hand too!). We've had a string of typos
> in the definitions so far, and it would be nice to take steps to avoid
> that for future changes.
Yeah, normally it's not too bad (and it can be useful to make sure
you've actually looked at the entire register definition properly) but I
did just about get annoyed enough to write something locally while doing
this register. You could certainly get a good chunk of the way there,
especially for simple fields (enums would need manual naming IIRC) - if
it hadn't been for the pushback mentioned above combined with what's on
developer.arm.com I'd probably have got round to doing something
already.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/2] arm64/sysregs: Generate definitions fine grained traps control registers
2023-03-23 20:44 ` Mark Brown
@ 2023-04-06 15:51 ` Will Deacon
-1 siblings, 0 replies; 16+ messages in thread
From: Will Deacon @ 2023-04-06 15:51 UTC (permalink / raw)
To: Mark Brown, Catalin Marinas
Cc: kernel-team, Will Deacon, Anshuman Khandual, Joey Gouly,
linux-arm-kernel, linux-kernel
On Thu, 23 Mar 2023 20:44:52 +0000, Mark Brown wrote:
> This series converts the fine grained traps control registers to
> automatic generation as per DDI0601 2022-12.
>
> I previously sent this with just the read/write trap registers, there
> have been no changes in that patch since v2.
>
> Changes in v3:
> - Add HFGITR_EL2.
> Changes in v2:
> - Correct naming of nPIRE0_EL1.
> - Link to v1: https://lore.kernel.org/r/20230306-arm64-fgt-reg-gen-v1-1-95bc0c97cfed@kernel.org
>
> [...]
Applied first patch to arm64 (for-next/sysreg), thanks!
[1/2] arm64/sysreg: Convert HFG[RW]TR_EL2 to automatic generation
https://git.kernel.org/arm64/c/cc077e7facbe
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/2] arm64/sysregs: Generate definitions fine grained traps control registers
@ 2023-04-06 15:51 ` Will Deacon
0 siblings, 0 replies; 16+ messages in thread
From: Will Deacon @ 2023-04-06 15:51 UTC (permalink / raw)
To: Mark Brown, Catalin Marinas
Cc: kernel-team, Will Deacon, Anshuman Khandual, Joey Gouly,
linux-arm-kernel, linux-kernel
On Thu, 23 Mar 2023 20:44:52 +0000, Mark Brown wrote:
> This series converts the fine grained traps control registers to
> automatic generation as per DDI0601 2022-12.
>
> I previously sent this with just the read/write trap registers, there
> have been no changes in that patch since v2.
>
> Changes in v3:
> - Add HFGITR_EL2.
> Changes in v2:
> - Correct naming of nPIRE0_EL1.
> - Link to v1: https://lore.kernel.org/r/20230306-arm64-fgt-reg-gen-v1-1-95bc0c97cfed@kernel.org
>
> [...]
Applied first patch to arm64 (for-next/sysreg), thanks!
[1/2] arm64/sysreg: Convert HFG[RW]TR_EL2 to automatic generation
https://git.kernel.org/arm64/c/cc077e7facbe
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2023-04-06 15:52 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-23 20:44 [PATCH v3 0/2] arm64/sysregs: Generate definitions fine grained traps control registers Mark Brown
2023-03-23 20:44 ` Mark Brown
2023-03-23 20:44 ` [PATCH v3 1/2] arm64/sysreg: Convert HFG[RW]TR_EL2 to automatic generation Mark Brown
2023-03-23 20:44 ` Mark Brown
2023-03-23 20:44 ` [PATCH v3 2/2] arm64/sysreg: Convert HFGITR_EL2 " Mark Brown
2023-03-23 20:44 ` Mark Brown
2023-04-06 14:46 ` Will Deacon
2023-04-06 14:46 ` Will Deacon
2023-04-06 15:02 ` Mark Brown
2023-04-06 15:02 ` Mark Brown
2023-04-06 15:04 ` Will Deacon
2023-04-06 15:04 ` Will Deacon
2023-04-06 15:25 ` Mark Brown
2023-04-06 15:25 ` Mark Brown
2023-04-06 15:51 ` [PATCH v3 0/2] arm64/sysregs: Generate definitions fine grained traps control registers Will Deacon
2023-04-06 15:51 ` Will Deacon
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