* [PATCH v2 00/10] drm/i915: move DSC RC tables to drm_dsc_helper.c
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Other platforms (msm) will benefit from sharing the DSC config setup
functions. This series moves parts of static DSC config data from the
i915 driver to the common helpers to be used by other drivers.
Note: the RC parameters were cross-checked against config files found in
DSC model 2021062, 20161212 (and 20150914). The first patch modifies
tables according to those config files, while preserving parameter
values using the code. I have not changed one of the values in the
pre-SCR config file as it clearly looks like a typo in the config file,
considering the table E in DSC 1.1 and in the DSC 1.1 SCR.
Chances since v1:
- Made drm_dsc_rc_buf_thresh static rather than exporting it
- Switched drm_dsc_rc_buf_thresh loop to use ARRAY_SIZE. Added
BUILD_BUG_ON's to be sure that array sizes are correct
- Fixed rc_parameters_data indentation to be logical and tidy
- Fixed drm_dsc_setup_rc_params() kerneldoc
- Added a clause to drm_dsc_setup_rc_params() to verify bpp and bpc
being set.
- Fixed range_bpg_offset programming in calculate_rc_params()
- Fixed bpp vs bpc bug in intel_dsc_compute_params()
- Added FIXME comment next to the customizations in
intel_dsc_compute_params().
Dmitry Baryshkov (10):
drm/i915/dsc: change DSC param tables to follow the DSC model
drm/i915/dsc: move rc_buf_thresh values to common helper
drm/i915/dsc: move DSC tables to DRM DSC helper
drm/i915/dsc: stop using interim structure for calculated params
drm/display/dsc: use flat array for rc_parameters lookup
drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
drm/display/dsc: include the rest of pre-SCR parameters
drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
drm/display/dsc: add helper to set semi-const parameters
drm/msm/dsi: use new helpers for DSC setup
drivers/gpu/drm/display/drm_dsc_helper.c | 1007 +++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 443 +--------
drivers/gpu/drm/msm/dsi/dsi_host.c | 61 +-
include/drm/display/drm_dsc_helper.h | 10 +
4 files changed, 1072 insertions(+), 449 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v2 00/10] drm/i915: move DSC RC tables to drm_dsc_helper.c
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Other platforms (msm) will benefit from sharing the DSC config setup
functions. This series moves parts of static DSC config data from the
i915 driver to the common helpers to be used by other drivers.
Note: the RC parameters were cross-checked against config files found in
DSC model 2021062, 20161212 (and 20150914). The first patch modifies
tables according to those config files, while preserving parameter
values using the code. I have not changed one of the values in the
pre-SCR config file as it clearly looks like a typo in the config file,
considering the table E in DSC 1.1 and in the DSC 1.1 SCR.
Chances since v1:
- Made drm_dsc_rc_buf_thresh static rather than exporting it
- Switched drm_dsc_rc_buf_thresh loop to use ARRAY_SIZE. Added
BUILD_BUG_ON's to be sure that array sizes are correct
- Fixed rc_parameters_data indentation to be logical and tidy
- Fixed drm_dsc_setup_rc_params() kerneldoc
- Added a clause to drm_dsc_setup_rc_params() to verify bpp and bpc
being set.
- Fixed range_bpg_offset programming in calculate_rc_params()
- Fixed bpp vs bpc bug in intel_dsc_compute_params()
- Added FIXME comment next to the customizations in
intel_dsc_compute_params().
Dmitry Baryshkov (10):
drm/i915/dsc: change DSC param tables to follow the DSC model
drm/i915/dsc: move rc_buf_thresh values to common helper
drm/i915/dsc: move DSC tables to DRM DSC helper
drm/i915/dsc: stop using interim structure for calculated params
drm/display/dsc: use flat array for rc_parameters lookup
drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
drm/display/dsc: include the rest of pre-SCR parameters
drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
drm/display/dsc: add helper to set semi-const parameters
drm/msm/dsi: use new helpers for DSC setup
drivers/gpu/drm/display/drm_dsc_helper.c | 1007 +++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 443 +--------
drivers/gpu/drm/msm/dsi/dsi_host.c | 61 +-
include/drm/display/drm_dsc_helper.h | 10 +
4 files changed, 1072 insertions(+), 449 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v2 00/10] drm/i915: move DSC RC tables to drm_dsc_helper.c
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
Other platforms (msm) will benefit from sharing the DSC config setup
functions. This series moves parts of static DSC config data from the
i915 driver to the common helpers to be used by other drivers.
Note: the RC parameters were cross-checked against config files found in
DSC model 2021062, 20161212 (and 20150914). The first patch modifies
tables according to those config files, while preserving parameter
values using the code. I have not changed one of the values in the
pre-SCR config file as it clearly looks like a typo in the config file,
considering the table E in DSC 1.1 and in the DSC 1.1 SCR.
Chances since v1:
- Made drm_dsc_rc_buf_thresh static rather than exporting it
- Switched drm_dsc_rc_buf_thresh loop to use ARRAY_SIZE. Added
BUILD_BUG_ON's to be sure that array sizes are correct
- Fixed rc_parameters_data indentation to be logical and tidy
- Fixed drm_dsc_setup_rc_params() kerneldoc
- Added a clause to drm_dsc_setup_rc_params() to verify bpp and bpc
being set.
- Fixed range_bpg_offset programming in calculate_rc_params()
- Fixed bpp vs bpc bug in intel_dsc_compute_params()
- Added FIXME comment next to the customizations in
intel_dsc_compute_params().
Dmitry Baryshkov (10):
drm/i915/dsc: change DSC param tables to follow the DSC model
drm/i915/dsc: move rc_buf_thresh values to common helper
drm/i915/dsc: move DSC tables to DRM DSC helper
drm/i915/dsc: stop using interim structure for calculated params
drm/display/dsc: use flat array for rc_parameters lookup
drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
drm/display/dsc: include the rest of pre-SCR parameters
drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
drm/display/dsc: add helper to set semi-const parameters
drm/msm/dsi: use new helpers for DSC setup
drivers/gpu/drm/display/drm_dsc_helper.c | 1007 +++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 443 +--------
drivers/gpu/drm/msm/dsi/dsi_host.c | 61 +-
include/drm/display/drm_dsc_helper.h | 10 +
4 files changed, 1072 insertions(+), 449 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v2 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
(?)
@ 2023-03-07 13:48 ` Dmitry Baryshkov
-1 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Jani Nikula, linux-arm-msm, intel-gfx, dri-devel, freedreno
After cross-checking DSC models (20150914, 20161212, 20210623) change
values in rc_parameters tables to follow config files present inside
the DSC model. Handle two places, where i915 tables diverged from the
model, by patching the rc values in the code.
Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because
the table in the VESA DSC 1.1 sets it to 4.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..a91b70301640 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -86,7 +86,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
}
},
/* 6BPP/14BPC */
- { 768, 15, 6144, 15, 25, 23, 27, {
+ { 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
@@ -115,6 +115,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/10BPC */
{ 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
@@ -132,7 +136,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/14BPC */
{ 512, 12, 6144, 15, 24, 23, 23, {
- { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
@@ -529,6 +533,20 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
DSC_RANGE_BPG_OFFSET_MASK;
}
+ if (DISPLAY_VER(dev_priv) < 13) {
+ /*
+ * FIXME: verify that the hardware actually needs these
+ * modifications rather than them being simple typos.
+ */
+ if (compressed_bpp == 6 &&
+ vdsc_cfg->bits_per_component == 8)
+ vdsc_cfg->rc_quant_incr_limit1 = 23;
+
+ if (compressed_bpp == 8 &&
+ vdsc_cfg->bits_per_component == 14)
+ vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
+ }
+
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v2 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Jani Nikula, linux-arm-msm, intel-gfx, dri-devel, freedreno
After cross-checking DSC models (20150914, 20161212, 20210623) change
values in rc_parameters tables to follow config files present inside
the DSC model. Handle two places, where i915 tables diverged from the
model, by patching the rc values in the code.
Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because
the table in the VESA DSC 1.1 sets it to 4.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..a91b70301640 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -86,7 +86,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
}
},
/* 6BPP/14BPC */
- { 768, 15, 6144, 15, 25, 23, 27, {
+ { 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
@@ -115,6 +115,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/10BPC */
{ 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
@@ -132,7 +136,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/14BPC */
{ 512, 12, 6144, 15, 24, 23, 23, {
- { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
@@ -529,6 +533,20 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
DSC_RANGE_BPG_OFFSET_MASK;
}
+ if (DISPLAY_VER(dev_priv) < 13) {
+ /*
+ * FIXME: verify that the hardware actually needs these
+ * modifications rather than them being simple typos.
+ */
+ if (compressed_bpp == 6 &&
+ vdsc_cfg->bits_per_component == 8)
+ vdsc_cfg->rc_quant_incr_limit1 = 23;
+
+ if (compressed_bpp == 8 &&
+ vdsc_cfg->bits_per_component == 14)
+ vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
+ }
+
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä,
dri-devel, intel-gfx, linux-arm-msm, freedreno, Jani Nikula
After cross-checking DSC models (20150914, 20161212, 20210623) change
values in rc_parameters tables to follow config files present inside
the DSC model. Handle two places, where i915 tables diverged from the
model, by patching the rc values in the code.
Note: I left one case uncorrected, 8bpp/10bpc/range_max_qp[0], because
the table in the VESA DSC 1.1 sets it to 4.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 207b2a648d32..a91b70301640 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -86,7 +86,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
}
},
/* 6BPP/14BPC */
- { 768, 15, 6144, 15, 25, 23, 27, {
+ { 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
{ 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
@@ -115,6 +115,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/10BPC */
{ 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
{ 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
@@ -132,7 +136,7 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
},
/* 8BPP/14BPC */
{ 512, 12, 6144, 15, 24, 23, 23, {
- { 0, 12, 0 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
{ 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
@@ -529,6 +533,20 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
DSC_RANGE_BPG_OFFSET_MASK;
}
+ if (DISPLAY_VER(dev_priv) < 13) {
+ /*
+ * FIXME: verify that the hardware actually needs these
+ * modifications rather than them being simple typos.
+ */
+ if (compressed_bpp == 6 &&
+ vdsc_cfg->bits_per_component == 8)
+ vdsc_cfg->rc_quant_incr_limit1 = 23;
+
+ if (compressed_bpp == 8 &&
+ vdsc_cfg->bits_per_component == 14)
+ vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
+ }
+
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v2 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
(?)
@ 2023-03-07 13:48 ` Dmitry Baryshkov
-1 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Jani Nikula, linux-arm-msm, intel-gfx, dri-devel, freedreno
The rc_buf_thresh values are common to all DSC implementations. Move
them to the common helper together with the code to propagage them to
the drm_dsc_config.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 35 +++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +---------------
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 37 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index c869c6e51e2b..be91abe2cfb2 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -270,6 +270,41 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
}
EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
+static const u16 drm_dsc_rc_buf_thresh[] = {
+ 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
+ 7744, 7872, 8000, 8064
+};
+
+/**
+ * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
+ * in accordance with the DSC 1.2 specification.
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ */
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
+{
+ int i;
+
+ BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
+ DSC_NUM_BUF_RANGES - 1);
+ BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
+ ARRAY_SIZE(vdsc_cfg->rc_buf_thresh));
+
+ for (i = 0; i < ARRAY_SIZE(drm_dsc_rc_buf_thresh); i++)
+ vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
+
+ /*
+ * For 6bpp, RC Buffer threshold 12 and 13 need a different value
+ * as per C Model
+ */
+ if (vdsc_cfg->bits_per_pixel == 6 << 4) {
+ vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
+ vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
+ }
+}
+EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index a91b70301640..38cc4b43f1cb 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
MAX_COLUMN_INDEX
};
-/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
-static const u16 rc_buf_thresh[] = {
- 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
- 7744, 7872, 8000, 8064
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
- for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
- /*
- * six 0s are appended to the lsb of each threshold value
- * internally in h/w.
- * Only 8 bits are allowed for programming RcBufThreshold
- */
- vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
- }
-
- /*
- * For 6bpp, RC Buffer threshold 12 and 13 need a different value
- * as per C Model
- */
- if (compressed_bpp == 6) {
- vdsc_cfg->rc_buf_thresh[12] = 0x7C;
- vdsc_cfg->rc_buf_thresh[13] = 0x7D;
- }
+ drm_dsc_set_rc_buf_thresh(vdsc_cfg);
/*
* From XE_LPD onwards we supports compression bpps in steps of 1
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 8b41edbbabab..706ba1d34742 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Jani Nikula, linux-arm-msm, intel-gfx, dri-devel, freedreno
The rc_buf_thresh values are common to all DSC implementations. Move
them to the common helper together with the code to propagage them to
the drm_dsc_config.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 35 +++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +---------------
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 37 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index c869c6e51e2b..be91abe2cfb2 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -270,6 +270,41 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
}
EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
+static const u16 drm_dsc_rc_buf_thresh[] = {
+ 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
+ 7744, 7872, 8000, 8064
+};
+
+/**
+ * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
+ * in accordance with the DSC 1.2 specification.
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ */
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
+{
+ int i;
+
+ BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
+ DSC_NUM_BUF_RANGES - 1);
+ BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
+ ARRAY_SIZE(vdsc_cfg->rc_buf_thresh));
+
+ for (i = 0; i < ARRAY_SIZE(drm_dsc_rc_buf_thresh); i++)
+ vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
+
+ /*
+ * For 6bpp, RC Buffer threshold 12 and 13 need a different value
+ * as per C Model
+ */
+ if (vdsc_cfg->bits_per_pixel == 6 << 4) {
+ vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
+ vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
+ }
+}
+EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index a91b70301640..38cc4b43f1cb 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
MAX_COLUMN_INDEX
};
-/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
-static const u16 rc_buf_thresh[] = {
- 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
- 7744, 7872, 8000, 8064
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
- for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
- /*
- * six 0s are appended to the lsb of each threshold value
- * internally in h/w.
- * Only 8 bits are allowed for programming RcBufThreshold
- */
- vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
- }
-
- /*
- * For 6bpp, RC Buffer threshold 12 and 13 need a different value
- * as per C Model
- */
- if (compressed_bpp == 6) {
- vdsc_cfg->rc_buf_thresh[12] = 0x7C;
- vdsc_cfg->rc_buf_thresh[13] = 0x7D;
- }
+ drm_dsc_set_rc_buf_thresh(vdsc_cfg);
/*
* From XE_LPD onwards we supports compression bpps in steps of 1
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 8b41edbbabab..706ba1d34742 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä,
dri-devel, intel-gfx, linux-arm-msm, freedreno, Jani Nikula
The rc_buf_thresh values are common to all DSC implementations. Move
them to the common helper together with the code to propagage them to
the drm_dsc_config.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 35 +++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 24 +---------------
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 37 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index c869c6e51e2b..be91abe2cfb2 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -270,6 +270,41 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
}
EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
+static const u16 drm_dsc_rc_buf_thresh[] = {
+ 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
+ 7744, 7872, 8000, 8064
+};
+
+/**
+ * drm_dsc_set_rc_buf_thresh() - Set thresholds for the RC model
+ * in accordance with the DSC 1.2 specification.
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ */
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
+{
+ int i;
+
+ BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
+ DSC_NUM_BUF_RANGES - 1);
+ BUILD_BUG_ON(ARRAY_SIZE(drm_dsc_rc_buf_thresh) !=
+ ARRAY_SIZE(vdsc_cfg->rc_buf_thresh));
+
+ for (i = 0; i < ARRAY_SIZE(drm_dsc_rc_buf_thresh); i++)
+ vdsc_cfg->rc_buf_thresh[i] = drm_dsc_rc_buf_thresh[i] >> 6;
+
+ /*
+ * For 6bpp, RC Buffer threshold 12 and 13 need a different value
+ * as per C Model
+ */
+ if (vdsc_cfg->bits_per_pixel == 6 << 4) {
+ vdsc_cfg->rc_buf_thresh[12] = 7936 >> 6;
+ vdsc_cfg->rc_buf_thresh[13] = 8000 >> 6;
+ }
+}
+EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index a91b70301640..38cc4b43f1cb 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -36,12 +36,6 @@ enum COLUMN_INDEX_BPC {
MAX_COLUMN_INDEX
};
-/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
-static const u16 rc_buf_thresh[] = {
- 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
- 7744, 7872, 8000, 8064
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -474,23 +468,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->bits_per_pixel = compressed_bpp << 4;
vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
- for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
- /*
- * six 0s are appended to the lsb of each threshold value
- * internally in h/w.
- * Only 8 bits are allowed for programming RcBufThreshold
- */
- vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] >> 6;
- }
-
- /*
- * For 6bpp, RC Buffer threshold 12 and 13 need a different value
- * as per C Model
- */
- if (compressed_bpp == 6) {
- vdsc_cfg->rc_buf_thresh[12] = 0x7C;
- vdsc_cfg->rc_buf_thresh[13] = 0x7D;
- }
+ drm_dsc_set_rc_buf_thresh(vdsc_cfg);
/*
* From XE_LPD onwards we supports compression bpps in steps of 1
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 8b41edbbabab..706ba1d34742 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -14,6 +14,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
+void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v2 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
(?)
@ 2023-03-07 13:48 ` Dmitry Baryshkov
-1 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Jani Nikula, linux-arm-msm, intel-gfx, dri-devel, freedreno
Move DSC RC tables to DRM DSC helper. No additional code changes
and/or cleanups are a part of this commit, it will be cleaned up in the
followup commits.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 372 ++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +------------------
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 380 insertions(+), 312 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index be91abe2cfb2..122a292bbc8f 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -305,6 +305,378 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+ MAX_COLUMN_INDEX
+};
+
+struct rc_parameters {
+ u16 initial_xmit_delay;
+ u8 first_line_bpg_offset;
+ u16 initial_offset;
+ u8 flatness_min_qp;
+ u8 flatness_max_qp;
+ u8 rc_quant_incr_limit0;
+ u8 rc_quant_incr_limit1;
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+};
+
+/*
+ * Selected Rate Control Related Parameter Recommended Values
+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212
+ */
+static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
+ {
+ /* 6BPP/8BPC */
+ { 768, 15, 6144, 3, 13, 11, 11, {
+ { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
+ { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
+ { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
+ { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
+ }
+ },
+ /* 6BPP/10BPC */
+ { 768, 15, 6144, 7, 17, 15, 15, {
+ { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
+ { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
+ { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
+ { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
+ { 17, 18, -12 }
+ }
+ },
+ /* 6BPP/12BPC */
+ { 768, 15, 6144, 11, 21, 19, 19, {
+ { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
+ { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
+ { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
+ { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
+ { 21, 22, -12 }
+ }
+ },
+ /* 6BPP/14BPC */
+ { 768, 15, 6144, 15, 25, 23, 23, {
+ { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
+ { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
+ { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
+ { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
+ { 25, 26, -12 }
+ }
+ },
+ /* 6BPP/16BPC */
+ { 768, 15, 6144, 19, 29, 27, 27, {
+ { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
+ { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
+ { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
+ { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
+ { 29, 30, -12 }
+ }
+ },
+ },
+ {
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ },
+ /* 8BPP/12BPC */
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ },
+ /* 8BPP/14BPC */
+ { 512, 12, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ },
+ /* 8BPP/16BPC */
+ { 512, 12, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ },
+ },
+ {
+ /* 10BPP/8BPC */
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ },
+ /* 10BPP/10BPC */
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ },
+ /* 10BPP/12BPC */
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ },
+ /* 10BPP/14BPC */
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ },
+ /* 10BPP/16BPC */
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ },
+ },
+ {
+ /* 12BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 12BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ },
+ /* 12BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ },
+ /* 12BPP/14BPC */
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ },
+ /* 12BPP/16BPC */
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ },
+ },
+ {
+ /* 15BPP/8BPC */
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ },
+ /* 15BPP/10BPC */
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ },
+ /* 15BPP/12BPC */
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ },
+ /* 15BPP/14BPC */
+ { 273, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ },
+ /* 15BPP/16BPC */
+ { 273, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ }
+};
+
+static int get_row_index_for_rc_params(u16 compressed_bpp)
+{
+ switch (compressed_bpp) {
+ case 6:
+ return ROW_INDEX_6BPP;
+ case 8:
+ return ROW_INDEX_8BPP;
+ case 10:
+ return ROW_INDEX_10BPP;
+ case 12:
+ return ROW_INDEX_12BPP;
+ case 15:
+ return ROW_INDEX_15BPP;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int get_column_index_for_rc_params(u8 bits_per_component)
+{
+ switch (bits_per_component) {
+ case 8:
+ return COLUMN_INDEX_8BPC;
+ case 10:
+ return COLUMN_INDEX_10BPC;
+ case 12:
+ return COLUMN_INDEX_12BPC;
+ case 14:
+ return COLUMN_INDEX_14BPC;
+ case 16:
+ return COLUMN_INDEX_16BPC;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
+ u8 bits_per_component)
+{
+ int row_index, column_index;
+
+ row_index = get_row_index_for_rc_params(compressed_bpp);
+ if (row_index < 0)
+ return NULL;
+
+ column_index = get_column_index_for_rc_params(bits_per_component);
+ if (column_index < 0)
+ return NULL;
+
+ return &rc_parameters[row_index][column_index];
+}
+
+/**
+ * drm_dsc_setup_rc_params() - Set parameters and limits for RC model in
+ * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
+ * Required bits_per_pixel and bits_per_component to be set before calling this
+ * function.
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ *
+ * Return: 0 or -error code in case of an error
+ */
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
+{
+ const struct rc_parameters *rc_params;
+ int i;
+
+ if (WARN_ON_ONCE(!vdsc_cfg->bits_per_pixel ||
+ !vdsc_cfg->bits_per_component))
+ return -EINVAL;
+
+ /* fractional BPP is not supported */
+ if (vdsc_cfg->bits_per_pixel & 0xf)
+ return -EINVAL;
+
+ rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
+ vdsc_cfg->bits_per_component);
+ if (!rc_params)
+ return -EINVAL;
+
+ vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
+ vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
+ vdsc_cfg->initial_offset = rc_params->initial_offset;
+ vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
+ vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
+ vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
+ vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
+
+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+ vdsc_cfg->rc_range_params[i].range_min_qp =
+ rc_params->rc_range_params[i].range_min_qp;
+ vdsc_cfg->rc_range_params[i].range_max_qp =
+ rc_params->rc_range_params[i].range_max_qp;
+ /*
+ * Range BPG Offset uses 2's complement and is only a 6 bits. So
+ * mask it to get only 6 bits.
+ */
+ vdsc_cfg->rc_range_params[i].range_bpg_offset =
+ rc_params->rc_range_params[i].range_bpg_offset &
+ DSC_RANGE_BPG_OFFSET_MASK;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dsc_setup_rc_params);
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 38cc4b43f1cb..8f99434c4ebc 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -18,24 +18,6 @@
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
-enum ROW_INDEX_BPP {
- ROW_INDEX_6BPP = 0,
- ROW_INDEX_8BPP,
- ROW_INDEX_10BPP,
- ROW_INDEX_12BPP,
- ROW_INDEX_15BPP,
- MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
- COLUMN_INDEX_8BPC = 0,
- COLUMN_INDEX_10BPC,
- COLUMN_INDEX_12BPC,
- COLUMN_INDEX_14BPC,
- COLUMN_INDEX_16BPC,
- MAX_COLUMN_INDEX
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -47,296 +29,6 @@ struct rc_parameters {
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};
-/*
- * Selected Rate Control Related Parameter Recommended Values
- * from DSC_v1.11 spec & C Model release: DSC_model_20161212
- */
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
-{
- /* 6BPP/8BPC */
- { 768, 15, 6144, 3, 13, 11, 11, {
- { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
- { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
- { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
- { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
- }
- },
- /* 6BPP/10BPC */
- { 768, 15, 6144, 7, 17, 15, 15, {
- { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
- { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
- { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
- { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
- { 17, 18, -12 }
- }
- },
- /* 6BPP/12BPC */
- { 768, 15, 6144, 11, 21, 19, 19, {
- { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
- { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
- { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
- { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
- { 21, 22, -12 }
- }
- },
- /* 6BPP/14BPC */
- { 768, 15, 6144, 15, 25, 23, 23, {
- { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
- { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
- { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
- { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
- { 25, 26, -12 }
- }
- },
- /* 6BPP/16BPC */
- { 768, 15, 6144, 19, 29, 27, 27, {
- { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
- { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
- { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
- { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
- { 29, 30, -12 }
- }
- },
-},
-{
- /* 8BPP/8BPC */
- { 512, 12, 6144, 3, 12, 11, 11, {
- { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
- { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
- }
- },
- /* 8BPP/10BPC */
- { 512, 12, 6144, 7, 16, 15, 15, {
- /*
- * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
- * VESA DSC 1.1 Table E-5 sets it to 4.
- */
- { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
- { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
- }
- },
- /* 8BPP/12BPC */
- { 512, 12, 6144, 11, 20, 19, 19, {
- { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
- { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
- }
- },
- /* 8BPP/14BPC */
- { 512, 12, 6144, 15, 24, 23, 23, {
- { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
- { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
- { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
- { 24, 25, -12 }
- }
- },
- /* 8BPP/16BPC */
- { 512, 12, 6144, 19, 28, 27, 27, {
- { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
- { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
- { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
- { 28, 29, -12 }
- }
- },
-},
-{
- /* 10BPP/8BPC */
- { 410, 15, 5632, 3, 12, 11, 11, {
- { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
- { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
- }
- },
- /* 10BPP/10BPC */
- { 410, 15, 5632, 7, 16, 15, 15, {
- { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
- { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
- { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
- }
- },
- /* 10BPP/12BPC */
- { 410, 15, 5632, 11, 20, 19, 19, {
- { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
- { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
- { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
- { 19, 20, -12 }
- }
- },
- /* 10BPP/14BPC */
- { 410, 15, 5632, 15, 24, 23, 23, {
- { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
- { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
- { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
- { 23, 24, -12 }
- }
- },
- /* 10BPP/16BPC */
- { 410, 15, 5632, 19, 28, 27, 27, {
- { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
- { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
- { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
- { 27, 28, -12 }
- }
- },
-},
-{
- /* 12BPP/8BPC */
- { 341, 15, 2048, 3, 12, 11, 11, {
- { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
- { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
- }
- },
- /* 12BPP/10BPC */
- { 341, 15, 2048, 7, 16, 15, 15, {
- { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
- { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
- }
- },
- /* 12BPP/12BPC */
- { 341, 15, 2048, 11, 20, 19, 19, {
- { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
- { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
- }
- },
- /* 12BPP/14BPC */
- { 341, 15, 2048, 15, 24, 23, 23, {
- { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
- { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
- { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
- { 22, 23, -12 }
- }
- },
- /* 12BPP/16BPC */
- { 341, 15, 2048, 19, 28, 27, 27, {
- { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
- { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
- { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
- { 26, 27, -12 }
- }
- },
-},
-{
- /* 15BPP/8BPC */
- { 273, 15, 2048, 3, 12, 11, 11, {
- { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
- { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
- { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
- { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
- }
- },
- /* 15BPP/10BPC */
- { 273, 15, 2048, 7, 16, 15, 15, {
- { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
- { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
- { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
- { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
- }
- },
- /* 15BPP/12BPC */
- { 273, 15, 2048, 11, 20, 19, 19, {
- { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
- { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
- { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
- { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
- { 16, 17, -12 }
- }
- },
- /* 15BPP/14BPC */
- { 273, 15, 2048, 15, 24, 23, 23, {
- { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
- { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
- { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
- { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
- { 20, 21, -12 }
- }
- },
- /* 15BPP/16BPC */
- { 273, 15, 2048, 19, 28, 27, 27, {
- { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
- { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
- { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
- { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
- { 24, 25, -12 }
- }
- }
-}
-
-};
-
-static int get_row_index_for_rc_params(u16 compressed_bpp)
-{
- switch (compressed_bpp) {
- case 6:
- return ROW_INDEX_6BPP;
- case 8:
- return ROW_INDEX_8BPP;
- case 10:
- return ROW_INDEX_10BPP;
- case 12:
- return ROW_INDEX_12BPP;
- case 15:
- return ROW_INDEX_15BPP;
- default:
- return -EINVAL;
- }
-}
-
-static int get_column_index_for_rc_params(u8 bits_per_component)
-{
- switch (bits_per_component) {
- case 8:
- return COLUMN_INDEX_8BPC;
- case 10:
- return COLUMN_INDEX_10BPC;
- case 12:
- return COLUMN_INDEX_12BPC;
- case 14:
- return COLUMN_INDEX_14BPC;
- case 16:
- return COLUMN_INDEX_16BPC;
- default:
- return -EINVAL;
- }
-}
-
-static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
- u8 bits_per_component)
-{
- int row_index, column_index;
-
- row_index = get_row_index_for_rc_params(compressed_bpp);
- if (row_index < 0)
- return NULL;
-
- column_index = get_column_index_for_rc_params(bits_per_component);
- if (column_index < 0)
- return NULL;
-
- return &rc_parameters[row_index][column_index];
-}
-
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -454,6 +146,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
const struct rc_parameters *rc_params;
struct rc_parameters *rc = NULL;
u8 i = 0;
+ int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
@@ -483,10 +176,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
calculate_rc_params(rc, vdsc_cfg);
rc_params = rc;
} else {
- rc_params = get_rc_params(compressed_bpp,
- vdsc_cfg->bits_per_component);
- if (!rc_params)
- return -EINVAL;
+ ret = drm_dsc_setup_rc_params(vdsc_cfg);
+ if (ret)
+ return ret;
+
+ goto out;
}
vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
@@ -525,6 +219,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
}
+out:
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 706ba1d34742..1681791f65a5 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -15,6 +15,7 @@ int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Jani Nikula, linux-arm-msm, intel-gfx, dri-devel, freedreno
Move DSC RC tables to DRM DSC helper. No additional code changes
and/or cleanups are a part of this commit, it will be cleaned up in the
followup commits.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 372 ++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +------------------
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 380 insertions(+), 312 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index be91abe2cfb2..122a292bbc8f 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -305,6 +305,378 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+ MAX_COLUMN_INDEX
+};
+
+struct rc_parameters {
+ u16 initial_xmit_delay;
+ u8 first_line_bpg_offset;
+ u16 initial_offset;
+ u8 flatness_min_qp;
+ u8 flatness_max_qp;
+ u8 rc_quant_incr_limit0;
+ u8 rc_quant_incr_limit1;
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+};
+
+/*
+ * Selected Rate Control Related Parameter Recommended Values
+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212
+ */
+static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
+ {
+ /* 6BPP/8BPC */
+ { 768, 15, 6144, 3, 13, 11, 11, {
+ { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
+ { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
+ { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
+ { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
+ }
+ },
+ /* 6BPP/10BPC */
+ { 768, 15, 6144, 7, 17, 15, 15, {
+ { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
+ { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
+ { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
+ { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
+ { 17, 18, -12 }
+ }
+ },
+ /* 6BPP/12BPC */
+ { 768, 15, 6144, 11, 21, 19, 19, {
+ { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
+ { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
+ { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
+ { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
+ { 21, 22, -12 }
+ }
+ },
+ /* 6BPP/14BPC */
+ { 768, 15, 6144, 15, 25, 23, 23, {
+ { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
+ { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
+ { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
+ { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
+ { 25, 26, -12 }
+ }
+ },
+ /* 6BPP/16BPC */
+ { 768, 15, 6144, 19, 29, 27, 27, {
+ { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
+ { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
+ { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
+ { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
+ { 29, 30, -12 }
+ }
+ },
+ },
+ {
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ },
+ /* 8BPP/12BPC */
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ },
+ /* 8BPP/14BPC */
+ { 512, 12, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ },
+ /* 8BPP/16BPC */
+ { 512, 12, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ },
+ },
+ {
+ /* 10BPP/8BPC */
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ },
+ /* 10BPP/10BPC */
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ },
+ /* 10BPP/12BPC */
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ },
+ /* 10BPP/14BPC */
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ },
+ /* 10BPP/16BPC */
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ },
+ },
+ {
+ /* 12BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 12BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ },
+ /* 12BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ },
+ /* 12BPP/14BPC */
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ },
+ /* 12BPP/16BPC */
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ },
+ },
+ {
+ /* 15BPP/8BPC */
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ },
+ /* 15BPP/10BPC */
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ },
+ /* 15BPP/12BPC */
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ },
+ /* 15BPP/14BPC */
+ { 273, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ },
+ /* 15BPP/16BPC */
+ { 273, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ }
+};
+
+static int get_row_index_for_rc_params(u16 compressed_bpp)
+{
+ switch (compressed_bpp) {
+ case 6:
+ return ROW_INDEX_6BPP;
+ case 8:
+ return ROW_INDEX_8BPP;
+ case 10:
+ return ROW_INDEX_10BPP;
+ case 12:
+ return ROW_INDEX_12BPP;
+ case 15:
+ return ROW_INDEX_15BPP;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int get_column_index_for_rc_params(u8 bits_per_component)
+{
+ switch (bits_per_component) {
+ case 8:
+ return COLUMN_INDEX_8BPC;
+ case 10:
+ return COLUMN_INDEX_10BPC;
+ case 12:
+ return COLUMN_INDEX_12BPC;
+ case 14:
+ return COLUMN_INDEX_14BPC;
+ case 16:
+ return COLUMN_INDEX_16BPC;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
+ u8 bits_per_component)
+{
+ int row_index, column_index;
+
+ row_index = get_row_index_for_rc_params(compressed_bpp);
+ if (row_index < 0)
+ return NULL;
+
+ column_index = get_column_index_for_rc_params(bits_per_component);
+ if (column_index < 0)
+ return NULL;
+
+ return &rc_parameters[row_index][column_index];
+}
+
+/**
+ * drm_dsc_setup_rc_params() - Set parameters and limits for RC model in
+ * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
+ * Required bits_per_pixel and bits_per_component to be set before calling this
+ * function.
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ *
+ * Return: 0 or -error code in case of an error
+ */
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
+{
+ const struct rc_parameters *rc_params;
+ int i;
+
+ if (WARN_ON_ONCE(!vdsc_cfg->bits_per_pixel ||
+ !vdsc_cfg->bits_per_component))
+ return -EINVAL;
+
+ /* fractional BPP is not supported */
+ if (vdsc_cfg->bits_per_pixel & 0xf)
+ return -EINVAL;
+
+ rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
+ vdsc_cfg->bits_per_component);
+ if (!rc_params)
+ return -EINVAL;
+
+ vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
+ vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
+ vdsc_cfg->initial_offset = rc_params->initial_offset;
+ vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
+ vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
+ vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
+ vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
+
+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+ vdsc_cfg->rc_range_params[i].range_min_qp =
+ rc_params->rc_range_params[i].range_min_qp;
+ vdsc_cfg->rc_range_params[i].range_max_qp =
+ rc_params->rc_range_params[i].range_max_qp;
+ /*
+ * Range BPG Offset uses 2's complement and is only a 6 bits. So
+ * mask it to get only 6 bits.
+ */
+ vdsc_cfg->rc_range_params[i].range_bpg_offset =
+ rc_params->rc_range_params[i].range_bpg_offset &
+ DSC_RANGE_BPG_OFFSET_MASK;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dsc_setup_rc_params);
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 38cc4b43f1cb..8f99434c4ebc 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -18,24 +18,6 @@
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
-enum ROW_INDEX_BPP {
- ROW_INDEX_6BPP = 0,
- ROW_INDEX_8BPP,
- ROW_INDEX_10BPP,
- ROW_INDEX_12BPP,
- ROW_INDEX_15BPP,
- MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
- COLUMN_INDEX_8BPC = 0,
- COLUMN_INDEX_10BPC,
- COLUMN_INDEX_12BPC,
- COLUMN_INDEX_14BPC,
- COLUMN_INDEX_16BPC,
- MAX_COLUMN_INDEX
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -47,296 +29,6 @@ struct rc_parameters {
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};
-/*
- * Selected Rate Control Related Parameter Recommended Values
- * from DSC_v1.11 spec & C Model release: DSC_model_20161212
- */
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
-{
- /* 6BPP/8BPC */
- { 768, 15, 6144, 3, 13, 11, 11, {
- { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
- { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
- { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
- { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
- }
- },
- /* 6BPP/10BPC */
- { 768, 15, 6144, 7, 17, 15, 15, {
- { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
- { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
- { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
- { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
- { 17, 18, -12 }
- }
- },
- /* 6BPP/12BPC */
- { 768, 15, 6144, 11, 21, 19, 19, {
- { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
- { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
- { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
- { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
- { 21, 22, -12 }
- }
- },
- /* 6BPP/14BPC */
- { 768, 15, 6144, 15, 25, 23, 23, {
- { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
- { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
- { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
- { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
- { 25, 26, -12 }
- }
- },
- /* 6BPP/16BPC */
- { 768, 15, 6144, 19, 29, 27, 27, {
- { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
- { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
- { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
- { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
- { 29, 30, -12 }
- }
- },
-},
-{
- /* 8BPP/8BPC */
- { 512, 12, 6144, 3, 12, 11, 11, {
- { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
- { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
- }
- },
- /* 8BPP/10BPC */
- { 512, 12, 6144, 7, 16, 15, 15, {
- /*
- * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
- * VESA DSC 1.1 Table E-5 sets it to 4.
- */
- { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
- { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
- }
- },
- /* 8BPP/12BPC */
- { 512, 12, 6144, 11, 20, 19, 19, {
- { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
- { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
- }
- },
- /* 8BPP/14BPC */
- { 512, 12, 6144, 15, 24, 23, 23, {
- { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
- { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
- { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
- { 24, 25, -12 }
- }
- },
- /* 8BPP/16BPC */
- { 512, 12, 6144, 19, 28, 27, 27, {
- { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
- { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
- { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
- { 28, 29, -12 }
- }
- },
-},
-{
- /* 10BPP/8BPC */
- { 410, 15, 5632, 3, 12, 11, 11, {
- { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
- { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
- }
- },
- /* 10BPP/10BPC */
- { 410, 15, 5632, 7, 16, 15, 15, {
- { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
- { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
- { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
- }
- },
- /* 10BPP/12BPC */
- { 410, 15, 5632, 11, 20, 19, 19, {
- { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
- { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
- { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
- { 19, 20, -12 }
- }
- },
- /* 10BPP/14BPC */
- { 410, 15, 5632, 15, 24, 23, 23, {
- { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
- { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
- { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
- { 23, 24, -12 }
- }
- },
- /* 10BPP/16BPC */
- { 410, 15, 5632, 19, 28, 27, 27, {
- { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
- { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
- { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
- { 27, 28, -12 }
- }
- },
-},
-{
- /* 12BPP/8BPC */
- { 341, 15, 2048, 3, 12, 11, 11, {
- { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
- { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
- }
- },
- /* 12BPP/10BPC */
- { 341, 15, 2048, 7, 16, 15, 15, {
- { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
- { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
- }
- },
- /* 12BPP/12BPC */
- { 341, 15, 2048, 11, 20, 19, 19, {
- { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
- { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
- }
- },
- /* 12BPP/14BPC */
- { 341, 15, 2048, 15, 24, 23, 23, {
- { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
- { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
- { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
- { 22, 23, -12 }
- }
- },
- /* 12BPP/16BPC */
- { 341, 15, 2048, 19, 28, 27, 27, {
- { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
- { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
- { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
- { 26, 27, -12 }
- }
- },
-},
-{
- /* 15BPP/8BPC */
- { 273, 15, 2048, 3, 12, 11, 11, {
- { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
- { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
- { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
- { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
- }
- },
- /* 15BPP/10BPC */
- { 273, 15, 2048, 7, 16, 15, 15, {
- { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
- { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
- { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
- { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
- }
- },
- /* 15BPP/12BPC */
- { 273, 15, 2048, 11, 20, 19, 19, {
- { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
- { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
- { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
- { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
- { 16, 17, -12 }
- }
- },
- /* 15BPP/14BPC */
- { 273, 15, 2048, 15, 24, 23, 23, {
- { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
- { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
- { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
- { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
- { 20, 21, -12 }
- }
- },
- /* 15BPP/16BPC */
- { 273, 15, 2048, 19, 28, 27, 27, {
- { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
- { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
- { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
- { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
- { 24, 25, -12 }
- }
- }
-}
-
-};
-
-static int get_row_index_for_rc_params(u16 compressed_bpp)
-{
- switch (compressed_bpp) {
- case 6:
- return ROW_INDEX_6BPP;
- case 8:
- return ROW_INDEX_8BPP;
- case 10:
- return ROW_INDEX_10BPP;
- case 12:
- return ROW_INDEX_12BPP;
- case 15:
- return ROW_INDEX_15BPP;
- default:
- return -EINVAL;
- }
-}
-
-static int get_column_index_for_rc_params(u8 bits_per_component)
-{
- switch (bits_per_component) {
- case 8:
- return COLUMN_INDEX_8BPC;
- case 10:
- return COLUMN_INDEX_10BPC;
- case 12:
- return COLUMN_INDEX_12BPC;
- case 14:
- return COLUMN_INDEX_14BPC;
- case 16:
- return COLUMN_INDEX_16BPC;
- default:
- return -EINVAL;
- }
-}
-
-static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
- u8 bits_per_component)
-{
- int row_index, column_index;
-
- row_index = get_row_index_for_rc_params(compressed_bpp);
- if (row_index < 0)
- return NULL;
-
- column_index = get_column_index_for_rc_params(bits_per_component);
- if (column_index < 0)
- return NULL;
-
- return &rc_parameters[row_index][column_index];
-}
-
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -454,6 +146,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
const struct rc_parameters *rc_params;
struct rc_parameters *rc = NULL;
u8 i = 0;
+ int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
@@ -483,10 +176,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
calculate_rc_params(rc, vdsc_cfg);
rc_params = rc;
} else {
- rc_params = get_rc_params(compressed_bpp,
- vdsc_cfg->bits_per_component);
- if (!rc_params)
- return -EINVAL;
+ ret = drm_dsc_setup_rc_params(vdsc_cfg);
+ if (ret)
+ return ret;
+
+ goto out;
}
vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
@@ -525,6 +219,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
}
+out:
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 706ba1d34742..1681791f65a5 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -15,6 +15,7 @@ int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä,
dri-devel, intel-gfx, linux-arm-msm, freedreno, Jani Nikula
Move DSC RC tables to DRM DSC helper. No additional code changes
and/or cleanups are a part of this commit, it will be cleaned up in the
followup commits.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 372 ++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vdsc.c | 319 +------------------
include/drm/display/drm_dsc_helper.h | 1 +
3 files changed, 380 insertions(+), 312 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index be91abe2cfb2..122a292bbc8f 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -305,6 +305,378 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
+enum ROW_INDEX_BPP {
+ ROW_INDEX_6BPP = 0,
+ ROW_INDEX_8BPP,
+ ROW_INDEX_10BPP,
+ ROW_INDEX_12BPP,
+ ROW_INDEX_15BPP,
+ MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+ COLUMN_INDEX_8BPC = 0,
+ COLUMN_INDEX_10BPC,
+ COLUMN_INDEX_12BPC,
+ COLUMN_INDEX_14BPC,
+ COLUMN_INDEX_16BPC,
+ MAX_COLUMN_INDEX
+};
+
+struct rc_parameters {
+ u16 initial_xmit_delay;
+ u8 first_line_bpg_offset;
+ u16 initial_offset;
+ u8 flatness_min_qp;
+ u8 flatness_max_qp;
+ u8 rc_quant_incr_limit0;
+ u8 rc_quant_incr_limit1;
+ struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
+};
+
+/*
+ * Selected Rate Control Related Parameter Recommended Values
+ * from DSC_v1.11 spec & C Model release: DSC_model_20161212
+ */
+static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
+ {
+ /* 6BPP/8BPC */
+ { 768, 15, 6144, 3, 13, 11, 11, {
+ { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
+ { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
+ { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
+ { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
+ }
+ },
+ /* 6BPP/10BPC */
+ { 768, 15, 6144, 7, 17, 15, 15, {
+ { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
+ { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
+ { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
+ { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
+ { 17, 18, -12 }
+ }
+ },
+ /* 6BPP/12BPC */
+ { 768, 15, 6144, 11, 21, 19, 19, {
+ { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
+ { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
+ { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
+ { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
+ { 21, 22, -12 }
+ }
+ },
+ /* 6BPP/14BPC */
+ { 768, 15, 6144, 15, 25, 23, 23, {
+ { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
+ { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
+ { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
+ { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
+ { 25, 26, -12 }
+ }
+ },
+ /* 6BPP/16BPC */
+ { 768, 15, 6144, 19, 29, 27, 27, {
+ { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
+ { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
+ { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
+ { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
+ { 29, 30, -12 }
+ }
+ },
+ },
+ {
+ /* 8BPP/8BPC */
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 8BPP/10BPC */
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ },
+ /* 8BPP/12BPC */
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ },
+ /* 8BPP/14BPC */
+ { 512, 12, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ },
+ /* 8BPP/16BPC */
+ { 512, 12, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ },
+ },
+ {
+ /* 10BPP/8BPC */
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ },
+ /* 10BPP/10BPC */
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ },
+ /* 10BPP/12BPC */
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ },
+ /* 10BPP/14BPC */
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ },
+ /* 10BPP/16BPC */
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ },
+ },
+ {
+ /* 12BPP/8BPC */
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ },
+ /* 12BPP/10BPC */
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ },
+ /* 12BPP/12BPC */
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ },
+ /* 12BPP/14BPC */
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ },
+ /* 12BPP/16BPC */
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ },
+ },
+ {
+ /* 15BPP/8BPC */
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ },
+ /* 15BPP/10BPC */
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ },
+ /* 15BPP/12BPC */
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ },
+ /* 15BPP/14BPC */
+ { 273, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ },
+ /* 15BPP/16BPC */
+ { 273, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ }
+};
+
+static int get_row_index_for_rc_params(u16 compressed_bpp)
+{
+ switch (compressed_bpp) {
+ case 6:
+ return ROW_INDEX_6BPP;
+ case 8:
+ return ROW_INDEX_8BPP;
+ case 10:
+ return ROW_INDEX_10BPP;
+ case 12:
+ return ROW_INDEX_12BPP;
+ case 15:
+ return ROW_INDEX_15BPP;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int get_column_index_for_rc_params(u8 bits_per_component)
+{
+ switch (bits_per_component) {
+ case 8:
+ return COLUMN_INDEX_8BPC;
+ case 10:
+ return COLUMN_INDEX_10BPC;
+ case 12:
+ return COLUMN_INDEX_12BPC;
+ case 14:
+ return COLUMN_INDEX_14BPC;
+ case 16:
+ return COLUMN_INDEX_16BPC;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
+ u8 bits_per_component)
+{
+ int row_index, column_index;
+
+ row_index = get_row_index_for_rc_params(compressed_bpp);
+ if (row_index < 0)
+ return NULL;
+
+ column_index = get_column_index_for_rc_params(bits_per_component);
+ if (column_index < 0)
+ return NULL;
+
+ return &rc_parameters[row_index][column_index];
+}
+
+/**
+ * drm_dsc_setup_rc_params() - Set parameters and limits for RC model in
+ * accordance with the DSC 1.1 or 1.2 specification and DSC C Model
+ * Required bits_per_pixel and bits_per_component to be set before calling this
+ * function.
+ *
+ * @vdsc_cfg: DSC Configuration data partially filled by driver
+ *
+ * Return: 0 or -error code in case of an error
+ */
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
+{
+ const struct rc_parameters *rc_params;
+ int i;
+
+ if (WARN_ON_ONCE(!vdsc_cfg->bits_per_pixel ||
+ !vdsc_cfg->bits_per_component))
+ return -EINVAL;
+
+ /* fractional BPP is not supported */
+ if (vdsc_cfg->bits_per_pixel & 0xf)
+ return -EINVAL;
+
+ rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
+ vdsc_cfg->bits_per_component);
+ if (!rc_params)
+ return -EINVAL;
+
+ vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
+ vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
+ vdsc_cfg->initial_offset = rc_params->initial_offset;
+ vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
+ vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
+ vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
+ vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
+
+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+ vdsc_cfg->rc_range_params[i].range_min_qp =
+ rc_params->rc_range_params[i].range_min_qp;
+ vdsc_cfg->rc_range_params[i].range_max_qp =
+ rc_params->rc_range_params[i].range_max_qp;
+ /*
+ * Range BPG Offset uses 2's complement and is only a 6 bits. So
+ * mask it to get only 6 bits.
+ */
+ vdsc_cfg->rc_range_params[i].range_bpg_offset =
+ rc_params->rc_range_params[i].range_bpg_offset &
+ DSC_RANGE_BPG_OFFSET_MASK;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dsc_setup_rc_params);
+
/**
* drm_dsc_compute_rc_parameters() - Write rate control
* parameters to the dsc configuration defined in
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 38cc4b43f1cb..8f99434c4ebc 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -18,24 +18,6 @@
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
-enum ROW_INDEX_BPP {
- ROW_INDEX_6BPP = 0,
- ROW_INDEX_8BPP,
- ROW_INDEX_10BPP,
- ROW_INDEX_12BPP,
- ROW_INDEX_15BPP,
- MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
- COLUMN_INDEX_8BPC = 0,
- COLUMN_INDEX_10BPC,
- COLUMN_INDEX_12BPC,
- COLUMN_INDEX_14BPC,
- COLUMN_INDEX_16BPC,
- MAX_COLUMN_INDEX
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -47,296 +29,6 @@ struct rc_parameters {
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};
-/*
- * Selected Rate Control Related Parameter Recommended Values
- * from DSC_v1.11 spec & C Model release: DSC_model_20161212
- */
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
-{
- /* 6BPP/8BPC */
- { 768, 15, 6144, 3, 13, 11, 11, {
- { 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
- { 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
- { 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
- { 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
- }
- },
- /* 6BPP/10BPC */
- { 768, 15, 6144, 7, 17, 15, 15, {
- { 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
- { 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
- { 11, 15, -8 }, { 12, 16, -10 }, { 13, 16, -10 },
- { 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
- { 17, 18, -12 }
- }
- },
- /* 6BPP/12BPC */
- { 768, 15, 6144, 11, 21, 19, 19, {
- { 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
- { 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
- { 15, 19, -8 }, { 16, 20, -10 }, { 17, 20, -10 },
- { 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
- { 21, 22, -12 }
- }
- },
- /* 6BPP/14BPC */
- { 768, 15, 6144, 15, 25, 23, 23, {
- { 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
- { 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
- { 19, 23, -8 }, { 20, 24, -10 }, { 21, 24, -10 },
- { 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
- { 25, 26, -12 }
- }
- },
- /* 6BPP/16BPC */
- { 768, 15, 6144, 19, 29, 27, 27, {
- { 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
- { 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
- { 23, 27, -8 }, { 24, 28, -10 }, { 25, 28, -10 },
- { 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
- { 29, 30, -12 }
- }
- },
-},
-{
- /* 8BPP/8BPC */
- { 512, 12, 6144, 3, 12, 11, 11, {
- { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
- { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
- }
- },
- /* 8BPP/10BPC */
- { 512, 12, 6144, 7, 16, 15, 15, {
- /*
- * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
- * VESA DSC 1.1 Table E-5 sets it to 4.
- */
- { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
- { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
- }
- },
- /* 8BPP/12BPC */
- { 512, 12, 6144, 11, 20, 19, 19, {
- { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
- { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
- }
- },
- /* 8BPP/14BPC */
- { 512, 12, 6144, 15, 24, 23, 23, {
- { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
- { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
- { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
- { 24, 25, -12 }
- }
- },
- /* 8BPP/16BPC */
- { 512, 12, 6144, 19, 28, 27, 27, {
- { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
- { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
- { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
- { 28, 29, -12 }
- }
- },
-},
-{
- /* 10BPP/8BPC */
- { 410, 15, 5632, 3, 12, 11, 11, {
- { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
- { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
- }
- },
- /* 10BPP/10BPC */
- { 410, 15, 5632, 7, 16, 15, 15, {
- { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
- { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
- { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
- }
- },
- /* 10BPP/12BPC */
- { 410, 15, 5632, 11, 20, 19, 19, {
- { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
- { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
- { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
- { 19, 20, -12 }
- }
- },
- /* 10BPP/14BPC */
- { 410, 15, 5632, 15, 24, 23, 23, {
- { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
- { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
- { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
- { 23, 24, -12 }
- }
- },
- /* 10BPP/16BPC */
- { 410, 15, 5632, 19, 28, 27, 27, {
- { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
- { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
- { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
- { 27, 28, -12 }
- }
- },
-},
-{
- /* 12BPP/8BPC */
- { 341, 15, 2048, 3, 12, 11, 11, {
- { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
- { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
- { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
- }
- },
- /* 12BPP/10BPC */
- { 341, 15, 2048, 7, 16, 15, 15, {
- { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
- { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
- }
- },
- /* 12BPP/12BPC */
- { 341, 15, 2048, 11, 20, 19, 19, {
- { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
- { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
- }
- },
- /* 12BPP/14BPC */
- { 341, 15, 2048, 15, 24, 23, 23, {
- { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
- { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
- { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
- { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
- { 22, 23, -12 }
- }
- },
- /* 12BPP/16BPC */
- { 341, 15, 2048, 19, 28, 27, 27, {
- { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
- { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
- { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
- { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
- { 26, 27, -12 }
- }
- },
-},
-{
- /* 15BPP/8BPC */
- { 273, 15, 2048, 3, 12, 11, 11, {
- { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
- { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
- { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
- { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
- }
- },
- /* 15BPP/10BPC */
- { 273, 15, 2048, 7, 16, 15, 15, {
- { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
- { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
- { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
- { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
- }
- },
- /* 15BPP/12BPC */
- { 273, 15, 2048, 11, 20, 19, 19, {
- { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
- { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
- { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
- { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
- { 16, 17, -12 }
- }
- },
- /* 15BPP/14BPC */
- { 273, 15, 2048, 15, 24, 23, 23, {
- { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
- { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
- { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
- { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
- { 20, 21, -12 }
- }
- },
- /* 15BPP/16BPC */
- { 273, 15, 2048, 19, 28, 27, 27, {
- { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
- { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
- { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
- { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
- { 24, 25, -12 }
- }
- }
-}
-
-};
-
-static int get_row_index_for_rc_params(u16 compressed_bpp)
-{
- switch (compressed_bpp) {
- case 6:
- return ROW_INDEX_6BPP;
- case 8:
- return ROW_INDEX_8BPP;
- case 10:
- return ROW_INDEX_10BPP;
- case 12:
- return ROW_INDEX_12BPP;
- case 15:
- return ROW_INDEX_15BPP;
- default:
- return -EINVAL;
- }
-}
-
-static int get_column_index_for_rc_params(u8 bits_per_component)
-{
- switch (bits_per_component) {
- case 8:
- return COLUMN_INDEX_8BPC;
- case 10:
- return COLUMN_INDEX_10BPC;
- case 12:
- return COLUMN_INDEX_12BPC;
- case 14:
- return COLUMN_INDEX_14BPC;
- case 16:
- return COLUMN_INDEX_16BPC;
- default:
- return -EINVAL;
- }
-}
-
-static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
- u8 bits_per_component)
-{
- int row_index, column_index;
-
- row_index = get_row_index_for_rc_params(compressed_bpp);
- if (row_index < 0)
- return NULL;
-
- column_index = get_column_index_for_rc_params(bits_per_component);
- if (column_index < 0)
- return NULL;
-
- return &rc_parameters[row_index][column_index];
-}
-
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -454,6 +146,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
const struct rc_parameters *rc_params;
struct rc_parameters *rc = NULL;
u8 i = 0;
+ int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
@@ -483,10 +176,11 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
calculate_rc_params(rc, vdsc_cfg);
rc_params = rc;
} else {
- rc_params = get_rc_params(compressed_bpp,
- vdsc_cfg->bits_per_component);
- if (!rc_params)
- return -EINVAL;
+ ret = drm_dsc_setup_rc_params(vdsc_cfg);
+ if (ret)
+ return ret;
+
+ goto out;
}
vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
@@ -525,6 +219,7 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
}
+out:
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 706ba1d34742..1681791f65a5 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -15,6 +15,7 @@ int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 04/10] drm/i915/dsc: stop using interim structure for calculated params
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
(?)
@ 2023-03-07 13:48 ` Dmitry Baryshkov
-1 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Jani Nikula, linux-arm-msm, intel-gfx, dri-devel, freedreno
Stop using an interim structure rc_parameters for storing calculated
params and then setting drm_dsc_config using that structure. Instead put
calculated params into the struct drm_dsc_config directly.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 100 ++++++----------------
1 file changed, 26 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 8f99434c4ebc..20a4c2f343fe 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -18,17 +18,6 @@
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
-struct rc_parameters {
- u16 initial_xmit_delay;
- u8 first_line_bpg_offset;
- u16 initial_offset;
- u8 flatness_min_qp;
- u8 flatness_max_qp;
- u8 rc_quant_incr_limit0;
- u8 rc_quant_incr_limit1;
- struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
-};
-
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -63,8 +52,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
}
static void
-calculate_rc_params(struct rc_parameters *rc,
- struct drm_dsc_config *vdsc_cfg)
+calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
{
int bpc = vdsc_cfg->bits_per_component;
int bpp = vdsc_cfg->bits_per_pixel >> 4;
@@ -84,56 +72,57 @@ calculate_rc_params(struct rc_parameters *rc,
u32 res, buf_i, bpp_i;
if (vdsc_cfg->slice_height >= 8)
- rc->first_line_bpg_offset =
+ vdsc_cfg->first_line_bpg_offset =
12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
else
- rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
+ vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
/* Our hw supports only 444 modes as of today */
if (bpp >= 12)
- rc->initial_offset = 2048;
+ vdsc_cfg->initial_offset = 2048;
else if (bpp >= 10)
- rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
+ vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
else if (bpp >= 8)
- rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
+ vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
else
- rc->initial_offset = 6144;
+ vdsc_cfg->initial_offset = 6144;
/* initial_xmit_delay = rc_model_size/2/compression_bpp */
- rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
+ vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
- rc->flatness_min_qp = 3 + qp_bpc_modifier;
- rc->flatness_max_qp = 12 + qp_bpc_modifier;
+ vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
+ vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
- rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
- rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
bpp_i = (2 * (bpp - 6));
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
+ u8 range_bpg_offset;
+
/* Read range_minqp and range_max_qp from qp tables */
- rc->rc_range_params[buf_i].range_min_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_min_qp =
intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
- rc->rc_range_params[buf_i].range_max_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_max_qp =
intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
- /* Calculate range_bgp_offset */
+ /* Calculate range_bpg_offset */
if (bpp <= 6) {
- rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
+ range_bpg_offset = ofs_und6[buf_i];
} else if (bpp <= 8) {
res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und6[buf_i] + res;
+ range_bpg_offset = ofs_und6[buf_i] + res;
} else if (bpp <= 12) {
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und8[buf_i];
+ range_bpg_offset = ofs_und8[buf_i];
} else if (bpp <= 15) {
res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und12[buf_i] + res;
+ range_bpg_offset = ofs_und12[buf_i] + res;
} else {
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und15[buf_i];
+ range_bpg_offset = ofs_und15[buf_i];
}
+
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
+ range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
}
}
@@ -143,9 +132,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
- const struct rc_parameters *rc_params;
- struct rc_parameters *rc = NULL;
- u8 i = 0;
int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
@@ -169,43 +155,12 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
* parameters
*/
if (DISPLAY_VER(dev_priv) >= 13) {
- rc = kmalloc(sizeof(*rc), GFP_KERNEL);
- if (!rc)
- return -ENOMEM;
-
- calculate_rc_params(rc, vdsc_cfg);
- rc_params = rc;
+ calculate_rc_params(vdsc_cfg);
} else {
ret = drm_dsc_setup_rc_params(vdsc_cfg);
if (ret)
return ret;
- goto out;
- }
-
- vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
- vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
- vdsc_cfg->initial_offset = rc_params->initial_offset;
- vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
- vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
- vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
- vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
-
- for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
- vdsc_cfg->rc_range_params[i].range_min_qp =
- rc_params->rc_range_params[i].range_min_qp;
- vdsc_cfg->rc_range_params[i].range_max_qp =
- rc_params->rc_range_params[i].range_max_qp;
- /*
- * Range BPG Offset uses 2's complement and is only a 6 bits. So
- * mask it to get only 6 bits.
- */
- vdsc_cfg->rc_range_params[i].range_bpg_offset =
- rc_params->rc_range_params[i].range_bpg_offset &
- DSC_RANGE_BPG_OFFSET_MASK;
- }
-
- if (DISPLAY_VER(dev_priv) < 13) {
/*
* FIXME: verify that the hardware actually needs these
* modifications rather than them being simple typos.
@@ -219,7 +174,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
}
-out:
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
@@ -234,8 +188,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
- kfree(rc);
-
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v2 04/10] drm/i915/dsc: stop using interim structure for calculated params
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Jani Nikula, linux-arm-msm, intel-gfx, dri-devel, freedreno
Stop using an interim structure rc_parameters for storing calculated
params and then setting drm_dsc_config using that structure. Instead put
calculated params into the struct drm_dsc_config directly.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 100 ++++++----------------
1 file changed, 26 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 8f99434c4ebc..20a4c2f343fe 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -18,17 +18,6 @@
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
-struct rc_parameters {
- u16 initial_xmit_delay;
- u8 first_line_bpg_offset;
- u16 initial_offset;
- u8 flatness_min_qp;
- u8 flatness_max_qp;
- u8 rc_quant_incr_limit0;
- u8 rc_quant_incr_limit1;
- struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
-};
-
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -63,8 +52,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
}
static void
-calculate_rc_params(struct rc_parameters *rc,
- struct drm_dsc_config *vdsc_cfg)
+calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
{
int bpc = vdsc_cfg->bits_per_component;
int bpp = vdsc_cfg->bits_per_pixel >> 4;
@@ -84,56 +72,57 @@ calculate_rc_params(struct rc_parameters *rc,
u32 res, buf_i, bpp_i;
if (vdsc_cfg->slice_height >= 8)
- rc->first_line_bpg_offset =
+ vdsc_cfg->first_line_bpg_offset =
12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
else
- rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
+ vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
/* Our hw supports only 444 modes as of today */
if (bpp >= 12)
- rc->initial_offset = 2048;
+ vdsc_cfg->initial_offset = 2048;
else if (bpp >= 10)
- rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
+ vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
else if (bpp >= 8)
- rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
+ vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
else
- rc->initial_offset = 6144;
+ vdsc_cfg->initial_offset = 6144;
/* initial_xmit_delay = rc_model_size/2/compression_bpp */
- rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
+ vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
- rc->flatness_min_qp = 3 + qp_bpc_modifier;
- rc->flatness_max_qp = 12 + qp_bpc_modifier;
+ vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
+ vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
- rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
- rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
bpp_i = (2 * (bpp - 6));
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
+ u8 range_bpg_offset;
+
/* Read range_minqp and range_max_qp from qp tables */
- rc->rc_range_params[buf_i].range_min_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_min_qp =
intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
- rc->rc_range_params[buf_i].range_max_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_max_qp =
intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
- /* Calculate range_bgp_offset */
+ /* Calculate range_bpg_offset */
if (bpp <= 6) {
- rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
+ range_bpg_offset = ofs_und6[buf_i];
} else if (bpp <= 8) {
res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und6[buf_i] + res;
+ range_bpg_offset = ofs_und6[buf_i] + res;
} else if (bpp <= 12) {
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und8[buf_i];
+ range_bpg_offset = ofs_und8[buf_i];
} else if (bpp <= 15) {
res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und12[buf_i] + res;
+ range_bpg_offset = ofs_und12[buf_i] + res;
} else {
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und15[buf_i];
+ range_bpg_offset = ofs_und15[buf_i];
}
+
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
+ range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
}
}
@@ -143,9 +132,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
- const struct rc_parameters *rc_params;
- struct rc_parameters *rc = NULL;
- u8 i = 0;
int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
@@ -169,43 +155,12 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
* parameters
*/
if (DISPLAY_VER(dev_priv) >= 13) {
- rc = kmalloc(sizeof(*rc), GFP_KERNEL);
- if (!rc)
- return -ENOMEM;
-
- calculate_rc_params(rc, vdsc_cfg);
- rc_params = rc;
+ calculate_rc_params(vdsc_cfg);
} else {
ret = drm_dsc_setup_rc_params(vdsc_cfg);
if (ret)
return ret;
- goto out;
- }
-
- vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
- vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
- vdsc_cfg->initial_offset = rc_params->initial_offset;
- vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
- vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
- vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
- vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
-
- for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
- vdsc_cfg->rc_range_params[i].range_min_qp =
- rc_params->rc_range_params[i].range_min_qp;
- vdsc_cfg->rc_range_params[i].range_max_qp =
- rc_params->rc_range_params[i].range_max_qp;
- /*
- * Range BPG Offset uses 2's complement and is only a 6 bits. So
- * mask it to get only 6 bits.
- */
- vdsc_cfg->rc_range_params[i].range_bpg_offset =
- rc_params->rc_range_params[i].range_bpg_offset &
- DSC_RANGE_BPG_OFFSET_MASK;
- }
-
- if (DISPLAY_VER(dev_priv) < 13) {
/*
* FIXME: verify that the hardware actually needs these
* modifications rather than them being simple typos.
@@ -219,7 +174,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
}
-out:
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
@@ -234,8 +188,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
- kfree(rc);
-
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 04/10] drm/i915/dsc: stop using interim structure for calculated params
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä,
dri-devel, intel-gfx, linux-arm-msm, freedreno, Jani Nikula
Stop using an interim structure rc_parameters for storing calculated
params and then setting drm_dsc_config using that structure. Instead put
calculated params into the struct drm_dsc_config directly.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 100 ++++++----------------
1 file changed, 26 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 8f99434c4ebc..20a4c2f343fe 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -18,17 +18,6 @@
#include "intel_qp_tables.h"
#include "intel_vdsc.h"
-struct rc_parameters {
- u16 initial_xmit_delay;
- u8 first_line_bpg_offset;
- u16 initial_offset;
- u8 flatness_min_qp;
- u8 flatness_max_qp;
- u8 rc_quant_incr_limit0;
- u8 rc_quant_incr_limit1;
- struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
-};
-
bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
{
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -63,8 +52,7 @@ static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
}
static void
-calculate_rc_params(struct rc_parameters *rc,
- struct drm_dsc_config *vdsc_cfg)
+calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
{
int bpc = vdsc_cfg->bits_per_component;
int bpp = vdsc_cfg->bits_per_pixel >> 4;
@@ -84,56 +72,57 @@ calculate_rc_params(struct rc_parameters *rc,
u32 res, buf_i, bpp_i;
if (vdsc_cfg->slice_height >= 8)
- rc->first_line_bpg_offset =
+ vdsc_cfg->first_line_bpg_offset =
12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
else
- rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
+ vdsc_cfg->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
/* Our hw supports only 444 modes as of today */
if (bpp >= 12)
- rc->initial_offset = 2048;
+ vdsc_cfg->initial_offset = 2048;
else if (bpp >= 10)
- rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
+ vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
else if (bpp >= 8)
- rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
+ vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
else
- rc->initial_offset = 6144;
+ vdsc_cfg->initial_offset = 6144;
/* initial_xmit_delay = rc_model_size/2/compression_bpp */
- rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
+ vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
- rc->flatness_min_qp = 3 + qp_bpc_modifier;
- rc->flatness_max_qp = 12 + qp_bpc_modifier;
+ vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
+ vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
- rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
- rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
+ vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
bpp_i = (2 * (bpp - 6));
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
+ u8 range_bpg_offset;
+
/* Read range_minqp and range_max_qp from qp tables */
- rc->rc_range_params[buf_i].range_min_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_min_qp =
intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
- rc->rc_range_params[buf_i].range_max_qp =
+ vdsc_cfg->rc_range_params[buf_i].range_max_qp =
intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
- /* Calculate range_bgp_offset */
+ /* Calculate range_bpg_offset */
if (bpp <= 6) {
- rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
+ range_bpg_offset = ofs_und6[buf_i];
} else if (bpp <= 8) {
res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und6[buf_i] + res;
+ range_bpg_offset = ofs_und6[buf_i] + res;
} else if (bpp <= 12) {
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und8[buf_i];
+ range_bpg_offset = ofs_und8[buf_i];
} else if (bpp <= 15) {
res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und12[buf_i] + res;
+ range_bpg_offset = ofs_und12[buf_i] + res;
} else {
- rc->rc_range_params[buf_i].range_bpg_offset =
- ofs_und15[buf_i];
+ range_bpg_offset = ofs_und15[buf_i];
}
+
+ vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
+ range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
}
}
@@ -143,9 +132,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
- const struct rc_parameters *rc_params;
- struct rc_parameters *rc = NULL;
- u8 i = 0;
int ret;
vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
@@ -169,43 +155,12 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
* parameters
*/
if (DISPLAY_VER(dev_priv) >= 13) {
- rc = kmalloc(sizeof(*rc), GFP_KERNEL);
- if (!rc)
- return -ENOMEM;
-
- calculate_rc_params(rc, vdsc_cfg);
- rc_params = rc;
+ calculate_rc_params(vdsc_cfg);
} else {
ret = drm_dsc_setup_rc_params(vdsc_cfg);
if (ret)
return ret;
- goto out;
- }
-
- vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
- vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
- vdsc_cfg->initial_offset = rc_params->initial_offset;
- vdsc_cfg->flatness_min_qp = rc_params->flatness_min_qp;
- vdsc_cfg->flatness_max_qp = rc_params->flatness_max_qp;
- vdsc_cfg->rc_quant_incr_limit0 = rc_params->rc_quant_incr_limit0;
- vdsc_cfg->rc_quant_incr_limit1 = rc_params->rc_quant_incr_limit1;
-
- for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
- vdsc_cfg->rc_range_params[i].range_min_qp =
- rc_params->rc_range_params[i].range_min_qp;
- vdsc_cfg->rc_range_params[i].range_max_qp =
- rc_params->rc_range_params[i].range_max_qp;
- /*
- * Range BPG Offset uses 2's complement and is only a 6 bits. So
- * mask it to get only 6 bits.
- */
- vdsc_cfg->rc_range_params[i].range_bpg_offset =
- rc_params->rc_range_params[i].range_bpg_offset &
- DSC_RANGE_BPG_OFFSET_MASK;
- }
-
- if (DISPLAY_VER(dev_priv) < 13) {
/*
* FIXME: verify that the hardware actually needs these
* modifications rather than them being simple typos.
@@ -219,7 +174,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->rc_range_params[0].range_bpg_offset = 0;
}
-out:
/*
* BitsPerComponent value determines mux_word_size:
* When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
@@ -234,8 +188,6 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
- kfree(rc);
-
return 0;
}
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v2 05/10] drm/display/dsc: use flat array for rc_parameters lookup
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
(?)
@ 2023-03-07 13:48 ` Dmitry Baryshkov
-1 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Jani Nikula, linux-arm-msm, intel-gfx, dri-devel, freedreno
Next commits are going to add support for additional RC parameter lookup
tables. These tables are going to use different bpp/bpc combinations,
thus it makes little sense to keep the 2d array for RC parameters.
Switch to using the flat array.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 228 +++++++++++------------
1 file changed, 108 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 122a292bbc8f..acb93d4116e0 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -305,24 +305,6 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
-enum ROW_INDEX_BPP {
- ROW_INDEX_6BPP = 0,
- ROW_INDEX_8BPP,
- ROW_INDEX_10BPP,
- ROW_INDEX_12BPP,
- ROW_INDEX_15BPP,
- MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
- COLUMN_INDEX_8BPC = 0,
- COLUMN_INDEX_10BPC,
- COLUMN_INDEX_12BPC,
- COLUMN_INDEX_14BPC,
- COLUMN_INDEX_16BPC,
- MAX_COLUMN_INDEX
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -334,21 +316,31 @@ struct rc_parameters {
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};
+struct rc_parameters_data {
+ u8 bpp;
+ u8 bpc;
+ struct rc_parameters params;
+};
+
+#define DSC_BPP(bpp) ((bpp) << 4)
+
/*
* Selected Rate Control Related Parameter Recommended Values
* from DSC_v1.11 spec & C Model release: DSC_model_20161212
*/
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
+static const struct rc_parameters_data rc_parameters[] = {
{
- /* 6BPP/8BPC */
+ .bpp = DSC_BPP(6), .bpc = 8,
{ 768, 15, 6144, 3, 13, 11, 11, {
{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
{ 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
}
- },
- /* 6BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 10,
{ 768, 15, 6144, 7, 17, 15, 15, {
{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
{ 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
@@ -356,8 +348,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
{ 17, 18, -12 }
}
- },
- /* 6BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 12,
{ 768, 15, 6144, 11, 21, 19, 19, {
{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
{ 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
@@ -365,8 +359,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
{ 21, 22, -12 }
}
- },
- /* 6BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 14,
{ 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
@@ -374,8 +370,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
{ 25, 26, -12 }
}
- },
- /* 6BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 16,
{ 768, 15, 6144, 19, 29, 27, 27, {
{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
{ 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
@@ -383,18 +381,20 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
{ 29, 30, -12 }
}
- },
+ }
},
{
- /* 8BPP/8BPC */
+ .bpp = DSC_BPP(8), .bpc = 8,
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
}
- },
- /* 8BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
{ 512, 12, 6144, 7, 16, 15, 15, {
/*
* DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
@@ -405,8 +405,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
}
- },
- /* 8BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
{ 512, 12, 6144, 11, 20, 19, 19, {
{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
@@ -414,8 +416,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
{ 21, 23, -12 }
}
- },
- /* 8BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 14,
{ 512, 12, 6144, 15, 24, 23, 23, {
{ 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
@@ -423,8 +427,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
{ 24, 25, -12 }
}
- },
- /* 8BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 16,
{ 512, 12, 6144, 19, 28, 27, 27, {
{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
@@ -432,26 +438,30 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
{ 28, 29, -12 }
}
- },
+ }
},
{
- /* 10BPP/8BPC */
+ .bpp = DSC_BPP(10), .bpc = 8,
{ 410, 15, 5632, 3, 12, 11, 11, {
{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
}
- },
- /* 10BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 10,
{ 410, 15, 5632, 7, 16, 15, 15, {
{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
}
- },
- /* 10BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 12,
{ 410, 15, 5632, 11, 20, 19, 19, {
{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
@@ -459,8 +469,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
{ 19, 20, -12 }
}
- },
- /* 10BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 14,
{ 410, 15, 5632, 15, 24, 23, 23, {
{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
@@ -468,8 +480,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
{ 23, 24, -12 }
}
- },
- /* 10BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 16,
{ 410, 15, 5632, 19, 28, 27, 27, {
{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
@@ -477,26 +491,30 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
{ 27, 28, -12 }
}
- },
+ }
},
{
- /* 12BPP/8BPC */
+ .bpp = DSC_BPP(12), .bpc = 8,
{ 341, 15, 2048, 3, 12, 11, 11, {
{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
{ 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
}
- },
- /* 12BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 10,
{ 341, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
}
- },
- /* 12BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 12,
{ 341, 15, 2048, 11, 20, 19, 19, {
{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
@@ -504,8 +522,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
{ 21, 23, -12 }
}
- },
- /* 12BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 14,
{ 341, 15, 2048, 15, 24, 23, 23, {
{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
{ 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
@@ -513,8 +533,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
{ 22, 23, -12 }
}
- },
- /* 12BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 16,
{ 341, 15, 2048, 19, 28, 27, 27, {
{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
{ 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
@@ -522,26 +544,30 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
{ 26, 27, -12 }
}
- },
+ }
},
{
- /* 15BPP/8BPC */
+ .bpp = DSC_BPP(15), .bpc = 8,
{ 273, 15, 2048, 3, 12, 11, 11, {
{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
{ 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
}
- },
- /* 15BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 10,
{ 273, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
{ 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
}
- },
- /* 15BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 12,
{ 273, 15, 2048, 11, 20, 19, 19, {
{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
{ 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
@@ -549,8 +575,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
{ 16, 17, -12 }
}
- },
- /* 15BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 14,
{ 273, 15, 2048, 15, 24, 23, 23, {
{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
{ 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
@@ -558,8 +586,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
{ 20, 21, -12 }
}
- },
- /* 15BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 16,
{ 273, 15, 2048, 19, 28, 27, 27, {
{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
{ 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
@@ -568,59 +598,21 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 24, 25, -12 }
}
}
- }
+ },
+ { /* sentinel */ }
};
-static int get_row_index_for_rc_params(u16 compressed_bpp)
-{
- switch (compressed_bpp) {
- case 6:
- return ROW_INDEX_6BPP;
- case 8:
- return ROW_INDEX_8BPP;
- case 10:
- return ROW_INDEX_10BPP;
- case 12:
- return ROW_INDEX_12BPP;
- case 15:
- return ROW_INDEX_15BPP;
- default:
- return -EINVAL;
- }
-}
-
-static int get_column_index_for_rc_params(u8 bits_per_component)
-{
- switch (bits_per_component) {
- case 8:
- return COLUMN_INDEX_8BPC;
- case 10:
- return COLUMN_INDEX_10BPC;
- case 12:
- return COLUMN_INDEX_12BPC;
- case 14:
- return COLUMN_INDEX_14BPC;
- case 16:
- return COLUMN_INDEX_16BPC;
- default:
- return -EINVAL;
- }
-}
-
-static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
+static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
u8 bits_per_component)
{
- int row_index, column_index;
-
- row_index = get_row_index_for_rc_params(compressed_bpp);
- if (row_index < 0)
- return NULL;
+ int i;
- column_index = get_column_index_for_rc_params(bits_per_component);
- if (column_index < 0)
- return NULL;
+ for (i = 0; rc_parameters[i].bpp; i++)
+ if (rc_parameters[i].bpp == dsc_bpp &&
+ rc_parameters[i].bpc == bits_per_component)
+ return &rc_parameters[i].params;
- return &rc_parameters[row_index][column_index];
+ return NULL;
}
/**
@@ -642,11 +634,7 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
!vdsc_cfg->bits_per_component))
return -EINVAL;
- /* fractional BPP is not supported */
- if (vdsc_cfg->bits_per_pixel & 0xf)
- return -EINVAL;
-
- rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
+ rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_component);
if (!rc_params)
return -EINVAL;
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 05/10] drm/display/dsc: use flat array for rc_parameters lookup
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Jani Nikula, linux-arm-msm, intel-gfx, dri-devel, freedreno
Next commits are going to add support for additional RC parameter lookup
tables. These tables are going to use different bpp/bpc combinations,
thus it makes little sense to keep the 2d array for RC parameters.
Switch to using the flat array.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 228 +++++++++++------------
1 file changed, 108 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 122a292bbc8f..acb93d4116e0 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -305,24 +305,6 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
-enum ROW_INDEX_BPP {
- ROW_INDEX_6BPP = 0,
- ROW_INDEX_8BPP,
- ROW_INDEX_10BPP,
- ROW_INDEX_12BPP,
- ROW_INDEX_15BPP,
- MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
- COLUMN_INDEX_8BPC = 0,
- COLUMN_INDEX_10BPC,
- COLUMN_INDEX_12BPC,
- COLUMN_INDEX_14BPC,
- COLUMN_INDEX_16BPC,
- MAX_COLUMN_INDEX
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -334,21 +316,31 @@ struct rc_parameters {
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};
+struct rc_parameters_data {
+ u8 bpp;
+ u8 bpc;
+ struct rc_parameters params;
+};
+
+#define DSC_BPP(bpp) ((bpp) << 4)
+
/*
* Selected Rate Control Related Parameter Recommended Values
* from DSC_v1.11 spec & C Model release: DSC_model_20161212
*/
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
+static const struct rc_parameters_data rc_parameters[] = {
{
- /* 6BPP/8BPC */
+ .bpp = DSC_BPP(6), .bpc = 8,
{ 768, 15, 6144, 3, 13, 11, 11, {
{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
{ 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
}
- },
- /* 6BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 10,
{ 768, 15, 6144, 7, 17, 15, 15, {
{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
{ 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
@@ -356,8 +348,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
{ 17, 18, -12 }
}
- },
- /* 6BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 12,
{ 768, 15, 6144, 11, 21, 19, 19, {
{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
{ 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
@@ -365,8 +359,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
{ 21, 22, -12 }
}
- },
- /* 6BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 14,
{ 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
@@ -374,8 +370,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
{ 25, 26, -12 }
}
- },
- /* 6BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 16,
{ 768, 15, 6144, 19, 29, 27, 27, {
{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
{ 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
@@ -383,18 +381,20 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
{ 29, 30, -12 }
}
- },
+ }
},
{
- /* 8BPP/8BPC */
+ .bpp = DSC_BPP(8), .bpc = 8,
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
}
- },
- /* 8BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
{ 512, 12, 6144, 7, 16, 15, 15, {
/*
* DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
@@ -405,8 +405,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
}
- },
- /* 8BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
{ 512, 12, 6144, 11, 20, 19, 19, {
{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
@@ -414,8 +416,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
{ 21, 23, -12 }
}
- },
- /* 8BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 14,
{ 512, 12, 6144, 15, 24, 23, 23, {
{ 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
@@ -423,8 +427,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
{ 24, 25, -12 }
}
- },
- /* 8BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 16,
{ 512, 12, 6144, 19, 28, 27, 27, {
{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
@@ -432,26 +438,30 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
{ 28, 29, -12 }
}
- },
+ }
},
{
- /* 10BPP/8BPC */
+ .bpp = DSC_BPP(10), .bpc = 8,
{ 410, 15, 5632, 3, 12, 11, 11, {
{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
}
- },
- /* 10BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 10,
{ 410, 15, 5632, 7, 16, 15, 15, {
{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
}
- },
- /* 10BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 12,
{ 410, 15, 5632, 11, 20, 19, 19, {
{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
@@ -459,8 +469,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
{ 19, 20, -12 }
}
- },
- /* 10BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 14,
{ 410, 15, 5632, 15, 24, 23, 23, {
{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
@@ -468,8 +480,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
{ 23, 24, -12 }
}
- },
- /* 10BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 16,
{ 410, 15, 5632, 19, 28, 27, 27, {
{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
@@ -477,26 +491,30 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
{ 27, 28, -12 }
}
- },
+ }
},
{
- /* 12BPP/8BPC */
+ .bpp = DSC_BPP(12), .bpc = 8,
{ 341, 15, 2048, 3, 12, 11, 11, {
{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
{ 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
}
- },
- /* 12BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 10,
{ 341, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
}
- },
- /* 12BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 12,
{ 341, 15, 2048, 11, 20, 19, 19, {
{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
@@ -504,8 +522,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
{ 21, 23, -12 }
}
- },
- /* 12BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 14,
{ 341, 15, 2048, 15, 24, 23, 23, {
{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
{ 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
@@ -513,8 +533,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
{ 22, 23, -12 }
}
- },
- /* 12BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 16,
{ 341, 15, 2048, 19, 28, 27, 27, {
{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
{ 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
@@ -522,26 +544,30 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
{ 26, 27, -12 }
}
- },
+ }
},
{
- /* 15BPP/8BPC */
+ .bpp = DSC_BPP(15), .bpc = 8,
{ 273, 15, 2048, 3, 12, 11, 11, {
{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
{ 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
}
- },
- /* 15BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 10,
{ 273, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
{ 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
}
- },
- /* 15BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 12,
{ 273, 15, 2048, 11, 20, 19, 19, {
{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
{ 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
@@ -549,8 +575,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
{ 16, 17, -12 }
}
- },
- /* 15BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 14,
{ 273, 15, 2048, 15, 24, 23, 23, {
{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
{ 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
@@ -558,8 +586,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
{ 20, 21, -12 }
}
- },
- /* 15BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 16,
{ 273, 15, 2048, 19, 28, 27, 27, {
{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
{ 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
@@ -568,59 +598,21 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 24, 25, -12 }
}
}
- }
+ },
+ { /* sentinel */ }
};
-static int get_row_index_for_rc_params(u16 compressed_bpp)
-{
- switch (compressed_bpp) {
- case 6:
- return ROW_INDEX_6BPP;
- case 8:
- return ROW_INDEX_8BPP;
- case 10:
- return ROW_INDEX_10BPP;
- case 12:
- return ROW_INDEX_12BPP;
- case 15:
- return ROW_INDEX_15BPP;
- default:
- return -EINVAL;
- }
-}
-
-static int get_column_index_for_rc_params(u8 bits_per_component)
-{
- switch (bits_per_component) {
- case 8:
- return COLUMN_INDEX_8BPC;
- case 10:
- return COLUMN_INDEX_10BPC;
- case 12:
- return COLUMN_INDEX_12BPC;
- case 14:
- return COLUMN_INDEX_14BPC;
- case 16:
- return COLUMN_INDEX_16BPC;
- default:
- return -EINVAL;
- }
-}
-
-static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
+static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
u8 bits_per_component)
{
- int row_index, column_index;
-
- row_index = get_row_index_for_rc_params(compressed_bpp);
- if (row_index < 0)
- return NULL;
+ int i;
- column_index = get_column_index_for_rc_params(bits_per_component);
- if (column_index < 0)
- return NULL;
+ for (i = 0; rc_parameters[i].bpp; i++)
+ if (rc_parameters[i].bpp == dsc_bpp &&
+ rc_parameters[i].bpc == bits_per_component)
+ return &rc_parameters[i].params;
- return &rc_parameters[row_index][column_index];
+ return NULL;
}
/**
@@ -642,11 +634,7 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
!vdsc_cfg->bits_per_component))
return -EINVAL;
- /* fractional BPP is not supported */
- if (vdsc_cfg->bits_per_pixel & 0xf)
- return -EINVAL;
-
- rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
+ rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_component);
if (!rc_params)
return -EINVAL;
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 05/10] drm/display/dsc: use flat array for rc_parameters lookup
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä,
dri-devel, intel-gfx, linux-arm-msm, freedreno, Jani Nikula
Next commits are going to add support for additional RC parameter lookup
tables. These tables are going to use different bpp/bpc combinations,
thus it makes little sense to keep the 2d array for RC parameters.
Switch to using the flat array.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 228 +++++++++++------------
1 file changed, 108 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 122a292bbc8f..acb93d4116e0 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -305,24 +305,6 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg)
}
EXPORT_SYMBOL(drm_dsc_set_rc_buf_thresh);
-enum ROW_INDEX_BPP {
- ROW_INDEX_6BPP = 0,
- ROW_INDEX_8BPP,
- ROW_INDEX_10BPP,
- ROW_INDEX_12BPP,
- ROW_INDEX_15BPP,
- MAX_ROW_INDEX
-};
-
-enum COLUMN_INDEX_BPC {
- COLUMN_INDEX_8BPC = 0,
- COLUMN_INDEX_10BPC,
- COLUMN_INDEX_12BPC,
- COLUMN_INDEX_14BPC,
- COLUMN_INDEX_16BPC,
- MAX_COLUMN_INDEX
-};
-
struct rc_parameters {
u16 initial_xmit_delay;
u8 first_line_bpg_offset;
@@ -334,21 +316,31 @@ struct rc_parameters {
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
};
+struct rc_parameters_data {
+ u8 bpp;
+ u8 bpc;
+ struct rc_parameters params;
+};
+
+#define DSC_BPP(bpp) ((bpp) << 4)
+
/*
* Selected Rate Control Related Parameter Recommended Values
* from DSC_v1.11 spec & C Model release: DSC_model_20161212
*/
-static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
+static const struct rc_parameters_data rc_parameters[] = {
{
- /* 6BPP/8BPC */
+ .bpp = DSC_BPP(6), .bpc = 8,
{ 768, 15, 6144, 3, 13, 11, 11, {
{ 0, 4, 0 }, { 1, 6, -2 }, { 3, 8, -2 }, { 4, 8, -4 },
{ 5, 9, -6 }, { 5, 9, -6 }, { 6, 9, -6 }, { 6, 10, -8 },
{ 7, 11, -8 }, { 8, 12, -10 }, { 9, 12, -10 }, { 10, 12, -12 },
{ 10, 12, -12 }, { 11, 12, -12 }, { 13, 14, -12 }
}
- },
- /* 6BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 10,
{ 768, 15, 6144, 7, 17, 15, 15, {
{ 0, 8, 0 }, { 3, 10, -2 }, { 7, 12, -2 }, { 8, 12, -4 },
{ 9, 13, -6 }, { 9, 13, -6 }, { 10, 13, -6 }, { 10, 14, -8 },
@@ -356,8 +348,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 14, 16, -12 }, { 14, 16, -12 }, { 15, 16, -12 },
{ 17, 18, -12 }
}
- },
- /* 6BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 12,
{ 768, 15, 6144, 11, 21, 19, 19, {
{ 0, 12, 0 }, { 5, 14, -2 }, { 11, 16, -2 }, { 12, 16, -4 },
{ 13, 17, -6 }, { 13, 17, -6 }, { 14, 17, -6 }, { 14, 18, -8 },
@@ -365,8 +359,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 18, 20, -12 }, { 18, 20, -12 }, { 19, 20, -12 },
{ 21, 22, -12 }
}
- },
- /* 6BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 14,
{ 768, 15, 6144, 15, 25, 23, 23, {
{ 0, 16, 0 }, { 7, 18, -2 }, { 15, 20, -2 }, { 16, 20, -4 },
{ 17, 21, -6 }, { 17, 21, -6 }, { 18, 21, -6 }, { 18, 22, -8 },
@@ -374,8 +370,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 22, 24, -12 }, { 22, 24, -12 }, { 23, 24, -12 },
{ 25, 26, -12 }
}
- },
- /* 6BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 16,
{ 768, 15, 6144, 19, 29, 27, 27, {
{ 0, 20, 0 }, { 9, 22, -2 }, { 19, 24, -2 }, { 20, 24, -4 },
{ 21, 25, -6 }, { 21, 25, -6 }, { 22, 25, -6 }, { 22, 26, -8 },
@@ -383,18 +381,20 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 26, 28, -12 }, { 26, 28, -12 }, { 27, 28, -12 },
{ 29, 30, -12 }
}
- },
+ }
},
{
- /* 8BPP/8BPC */
+ .bpp = DSC_BPP(8), .bpc = 8,
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
{ 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
}
- },
- /* 8BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
{ 512, 12, 6144, 7, 16, 15, 15, {
/*
* DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
@@ -405,8 +405,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
}
- },
- /* 8BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
{ 512, 12, 6144, 11, 20, 19, 19, {
{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
@@ -414,8 +416,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
{ 21, 23, -12 }
}
- },
- /* 8BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 14,
{ 512, 12, 6144, 15, 24, 23, 23, {
{ 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
@@ -423,8 +427,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
{ 24, 25, -12 }
}
- },
- /* 8BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 16,
{ 512, 12, 6144, 19, 28, 27, 27, {
{ 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
@@ -432,26 +438,30 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
{ 28, 29, -12 }
}
- },
+ }
},
{
- /* 10BPP/8BPC */
+ .bpp = DSC_BPP(10), .bpc = 8,
{ 410, 15, 5632, 3, 12, 11, 11, {
{ 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
{ 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
{ 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
}
- },
- /* 10BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 10,
{ 410, 15, 5632, 7, 16, 15, 15, {
{ 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
{ 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
{ 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
}
- },
- /* 10BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 12,
{ 410, 15, 5632, 11, 20, 19, 19, {
{ 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
@@ -459,8 +469,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
{ 19, 20, -12 }
}
- },
- /* 10BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 14,
{ 410, 15, 5632, 15, 24, 23, 23, {
{ 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
{ 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
@@ -468,8 +480,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
{ 23, 24, -12 }
}
- },
- /* 10BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 16,
{ 410, 15, 5632, 19, 28, 27, 27, {
{ 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
{ 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
@@ -477,26 +491,30 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
{ 27, 28, -12 }
}
- },
+ }
},
{
- /* 12BPP/8BPC */
+ .bpp = DSC_BPP(12), .bpc = 8,
{ 341, 15, 2048, 3, 12, 11, 11, {
{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
{ 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
{ 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
}
- },
- /* 12BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 10,
{ 341, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
{ 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
{ 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
}
- },
- /* 12BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 12,
{ 341, 15, 2048, 11, 20, 19, 19, {
{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
@@ -504,8 +522,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
{ 21, 23, -12 }
}
- },
- /* 12BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 14,
{ 341, 15, 2048, 15, 24, 23, 23, {
{ 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
{ 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
@@ -513,8 +533,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
{ 22, 23, -12 }
}
- },
- /* 12BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 16,
{ 341, 15, 2048, 19, 28, 27, 27, {
{ 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
{ 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
@@ -522,26 +544,30 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
{ 26, 27, -12 }
}
- },
+ }
},
{
- /* 15BPP/8BPC */
+ .bpp = DSC_BPP(15), .bpc = 8,
{ 273, 15, 2048, 3, 12, 11, 11, {
{ 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
{ 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
{ 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
{ 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
}
- },
- /* 15BPP/10BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 10,
{ 273, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
{ 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
{ 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
{ 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
}
- },
- /* 15BPP/12BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 12,
{ 273, 15, 2048, 11, 20, 19, 19, {
{ 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
{ 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
@@ -549,8 +575,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
{ 16, 17, -12 }
}
- },
- /* 15BPP/14BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 14,
{ 273, 15, 2048, 15, 24, 23, 23, {
{ 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
{ 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
@@ -558,8 +586,10 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
{ 20, 21, -12 }
}
- },
- /* 15BPP/16BPC */
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 16,
{ 273, 15, 2048, 19, 28, 27, 27, {
{ 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
{ 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
@@ -568,59 +598,21 @@ static const struct rc_parameters rc_parameters[][MAX_COLUMN_INDEX] = {
{ 24, 25, -12 }
}
}
- }
+ },
+ { /* sentinel */ }
};
-static int get_row_index_for_rc_params(u16 compressed_bpp)
-{
- switch (compressed_bpp) {
- case 6:
- return ROW_INDEX_6BPP;
- case 8:
- return ROW_INDEX_8BPP;
- case 10:
- return ROW_INDEX_10BPP;
- case 12:
- return ROW_INDEX_12BPP;
- case 15:
- return ROW_INDEX_15BPP;
- default:
- return -EINVAL;
- }
-}
-
-static int get_column_index_for_rc_params(u8 bits_per_component)
-{
- switch (bits_per_component) {
- case 8:
- return COLUMN_INDEX_8BPC;
- case 10:
- return COLUMN_INDEX_10BPC;
- case 12:
- return COLUMN_INDEX_12BPC;
- case 14:
- return COLUMN_INDEX_14BPC;
- case 16:
- return COLUMN_INDEX_16BPC;
- default:
- return -EINVAL;
- }
-}
-
-static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
+static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
u8 bits_per_component)
{
- int row_index, column_index;
-
- row_index = get_row_index_for_rc_params(compressed_bpp);
- if (row_index < 0)
- return NULL;
+ int i;
- column_index = get_column_index_for_rc_params(bits_per_component);
- if (column_index < 0)
- return NULL;
+ for (i = 0; rc_parameters[i].bpp; i++)
+ if (rc_parameters[i].bpp == dsc_bpp &&
+ rc_parameters[i].bpc == bits_per_component)
+ return &rc_parameters[i].params;
- return &rc_parameters[row_index][column_index];
+ return NULL;
}
/**
@@ -642,11 +634,7 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
!vdsc_cfg->bits_per_component))
return -EINVAL;
- /* fractional BPP is not supported */
- if (vdsc_cfg->bits_per_pixel & 0xf)
- return -EINVAL;
-
- rc_params = get_rc_params(vdsc_cfg->bits_per_pixel >> 4,
+ rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_component);
if (!rc_params)
return -EINVAL;
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
(?)
@ 2023-03-07 13:48 ` Dmitry Baryshkov
-1 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
The array of rc_parameters contains a mixture of parameters from DSC 1.1
and DSC 1.2 standards. Split these tow configuration arrays in
preparation to adding more configuration data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
include/drm/display/drm_dsc_helper.h | 7 +-
3 files changed, 119 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index acb93d4116e0..35b39f3109c4 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -324,11 +324,81 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
+static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+ {
+ .bpp = DSC_BPP(8), .bpc = 8,
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 8,
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 10,
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 12,
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
+ { /* sentinel */ }
+};
+
/*
* Selected Rate Control Related Parameter Recommended Values
* from DSC_v1.11 spec & C Model release: DSC_model_20161212
*/
-static const struct rc_parameters_data rc_parameters[] = {
+static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{
.bpp = DSC_BPP(6), .bpc = 8,
{ 768, 15, 6144, 3, 13, 11, 11, {
@@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
- { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
}
}
},
{
.bpp = DSC_BPP(8), .bpc = 10,
{ 512, 12, 6144, 7, 16, 15, 15, {
- /*
- * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
- * VESA DSC 1.1 Table E-5 sets it to 4.
- */
- { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
}
}
},
@@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 11, 20, 19, 19, {
{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
}
}
},
@@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 3, 12, 11, 11, {
{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
- { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
}
}
},
@@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
}
}
},
@@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 11, 20, 19, 19, {
{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
}
}
},
@@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ /* sentinel */ }
};
-static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
+static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
+ u16 dsc_bpp,
u8 bits_per_component)
{
int i;
@@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
* function.
*
* @vdsc_cfg: DSC Configuration data partially filled by driver
+ * @kind: operating mode and standard to follow
*
* Return: 0 or -error code in case of an error
*/
-int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
{
+ const struct rc_parameters_data *data;
const struct rc_parameters *rc_params;
int i;
@@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
!vdsc_cfg->bits_per_component))
return -EINVAL;
- rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
+ switch (kind) {
+ case DRM_DSC_1_2_444:
+ data = rc_parameters_1_2_444;
+ break;
+ case DRM_DSC_1_1_PRE_SCR:
+ data = rc_parameters_pre_scr;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ rc_params = get_rc_params(data,
+ vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_component);
if (!rc_params)
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 20a4c2f343fe..a4d1d2ba71bb 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
if (DISPLAY_VER(dev_priv) >= 13) {
calculate_rc_params(vdsc_cfg);
} else {
- ret = drm_dsc_setup_rc_params(vdsc_cfg);
+ if ((compressed_bpp == 8 ||
+ compressed_bpp == 12) &&
+ (vdsc_cfg->bits_per_component == 8 ||
+ vdsc_cfg->bits_per_component == 10 ||
+ vdsc_cfg->bits_per_component == 12))
+ ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
+ else
+ ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
+
if (ret)
return ret;
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 1681791f65a5..c634bb2935d3 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -10,12 +10,17 @@
#include <drm/display/drm_dsc.h>
+enum drm_dsc_params_kind {
+ DRM_DSC_1_2_444,
+ DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
+};
+
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
-int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
The array of rc_parameters contains a mixture of parameters from DSC 1.1
and DSC 1.2 standards. Split these tow configuration arrays in
preparation to adding more configuration data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
include/drm/display/drm_dsc_helper.h | 7 +-
3 files changed, 119 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index acb93d4116e0..35b39f3109c4 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -324,11 +324,81 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
+static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+ {
+ .bpp = DSC_BPP(8), .bpc = 8,
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 8,
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 10,
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 12,
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
+ { /* sentinel */ }
+};
+
/*
* Selected Rate Control Related Parameter Recommended Values
* from DSC_v1.11 spec & C Model release: DSC_model_20161212
*/
-static const struct rc_parameters_data rc_parameters[] = {
+static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{
.bpp = DSC_BPP(6), .bpc = 8,
{ 768, 15, 6144, 3, 13, 11, 11, {
@@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
- { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
}
}
},
{
.bpp = DSC_BPP(8), .bpc = 10,
{ 512, 12, 6144, 7, 16, 15, 15, {
- /*
- * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
- * VESA DSC 1.1 Table E-5 sets it to 4.
- */
- { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
}
}
},
@@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 11, 20, 19, 19, {
{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
}
}
},
@@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 3, 12, 11, 11, {
{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
- { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
}
}
},
@@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
}
}
},
@@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 11, 20, 19, 19, {
{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
}
}
},
@@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ /* sentinel */ }
};
-static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
+static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
+ u16 dsc_bpp,
u8 bits_per_component)
{
int i;
@@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
* function.
*
* @vdsc_cfg: DSC Configuration data partially filled by driver
+ * @kind: operating mode and standard to follow
*
* Return: 0 or -error code in case of an error
*/
-int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
{
+ const struct rc_parameters_data *data;
const struct rc_parameters *rc_params;
int i;
@@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
!vdsc_cfg->bits_per_component))
return -EINVAL;
- rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
+ switch (kind) {
+ case DRM_DSC_1_2_444:
+ data = rc_parameters_1_2_444;
+ break;
+ case DRM_DSC_1_1_PRE_SCR:
+ data = rc_parameters_pre_scr;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ rc_params = get_rc_params(data,
+ vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_component);
if (!rc_params)
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 20a4c2f343fe..a4d1d2ba71bb 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
if (DISPLAY_VER(dev_priv) >= 13) {
calculate_rc_params(vdsc_cfg);
} else {
- ret = drm_dsc_setup_rc_params(vdsc_cfg);
+ if ((compressed_bpp == 8 ||
+ compressed_bpp == 12) &&
+ (vdsc_cfg->bits_per_component == 8 ||
+ vdsc_cfg->bits_per_component == 10 ||
+ vdsc_cfg->bits_per_component == 12))
+ ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
+ else
+ ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
+
if (ret)
return ret;
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 1681791f65a5..c634bb2935d3 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -10,12 +10,17 @@
#include <drm/display/drm_dsc.h>
+enum drm_dsc_params_kind {
+ DRM_DSC_1_2_444,
+ DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
+};
+
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
-int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
The array of rc_parameters contains a mixture of parameters from DSC 1.1
and DSC 1.2 standards. Split these tow configuration arrays in
preparation to adding more configuration data.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
include/drm/display/drm_dsc_helper.h | 7 +-
3 files changed, 119 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index acb93d4116e0..35b39f3109c4 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -324,11 +324,81 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
+static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+ {
+ .bpp = DSC_BPP(8), .bpc = 8,
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
+ { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ /*
+ * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
+ * VESA DSC 1.1 Table E-5 sets it to 4.
+ */
+ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 8,
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 10,
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
+ { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(12), .bpc = 12,
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
+ { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
+ { /* sentinel */ }
+};
+
/*
* Selected Rate Control Related Parameter Recommended Values
* from DSC_v1.11 spec & C Model release: DSC_model_20161212
*/
-static const struct rc_parameters_data rc_parameters[] = {
+static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{
.bpp = DSC_BPP(6), .bpc = 8,
{ 768, 15, 6144, 3, 13, 11, 11, {
@@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 3, 12, 11, 11, {
{ 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
- { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
}
}
},
{
.bpp = DSC_BPP(8), .bpc = 10,
{ 512, 12, 6144, 7, 16, 15, 15, {
- /*
- * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
- * VESA DSC 1.1 Table E-5 sets it to 4.
- */
- { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
{ 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
}
}
},
@@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 512, 12, 6144, 11, 20, 19, 19, {
{ 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
{ 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
}
}
},
@@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 3, 12, 11, 11, {
{ 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
{ 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
- { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
- { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
}
}
},
@@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 7, 16, 15, 15, {
{ 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
{ 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
- { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
- { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
}
}
},
@@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
{ 341, 15, 2048, 11, 20, 19, 19, {
{ 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
{ 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
- { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
- { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
- { 21, 23, -12 }
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
}
}
},
@@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
{ /* sentinel */ }
};
-static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
+static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
+ u16 dsc_bpp,
u8 bits_per_component)
{
int i;
@@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
* function.
*
* @vdsc_cfg: DSC Configuration data partially filled by driver
+ * @kind: operating mode and standard to follow
*
* Return: 0 or -error code in case of an error
*/
-int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
{
+ const struct rc_parameters_data *data;
const struct rc_parameters *rc_params;
int i;
@@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
!vdsc_cfg->bits_per_component))
return -EINVAL;
- rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
+ switch (kind) {
+ case DRM_DSC_1_2_444:
+ data = rc_parameters_1_2_444;
+ break;
+ case DRM_DSC_1_1_PRE_SCR:
+ data = rc_parameters_pre_scr;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ rc_params = get_rc_params(data,
+ vdsc_cfg->bits_per_pixel,
vdsc_cfg->bits_per_component);
if (!rc_params)
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 20a4c2f343fe..a4d1d2ba71bb 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
if (DISPLAY_VER(dev_priv) >= 13) {
calculate_rc_params(vdsc_cfg);
} else {
- ret = drm_dsc_setup_rc_params(vdsc_cfg);
+ if ((compressed_bpp == 8 ||
+ compressed_bpp == 12) &&
+ (vdsc_cfg->bits_per_component == 8 ||
+ vdsc_cfg->bits_per_component == 10 ||
+ vdsc_cfg->bits_per_component == 12))
+ ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
+ else
+ ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
+
if (ret)
return ret;
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 1681791f65a5..c634bb2935d3 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -10,12 +10,17 @@
#include <drm/display/drm_dsc.h>
+enum drm_dsc_params_kind {
+ DRM_DSC_1_2_444,
+ DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
+};
+
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
-int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
+int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
#endif /* _DRM_DSC_HELPER_H_ */
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 07/10] drm/display/dsc: include the rest of pre-SCR parameters
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
(?)
@ 2023-03-07 13:48 ` Dmitry Baryshkov
-1 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
include them here for completeness.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 72 ++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 35b39f3109c4..aec6f8c201af 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -325,6 +325,16 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+ {
+ .bpp = DSC_BPP(6), .bpc = 8,
+ { 683, 15, 6144, 3, 13, 11, 11, {
+ { 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 },
+ { 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 },
+ { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12, -12 },
+ { 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
+ }
+ }
+ },
{
.bpp = DSC_BPP(8), .bpc = 8,
{ 512, 12, 6144, 3, 12, 11, 11, {
@@ -360,6 +370,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
}
}
},
+ {
+ .bpp = DSC_BPP(10), .bpc = 8,
+ { 410, 12, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 10,
+ { 410, 12, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15, -10 },
+ { 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 12,
+ { 410, 12, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
{
.bpp = DSC_BPP(12), .bpc = 8,
{ 341, 15, 2048, 3, 12, 11, 11, {
@@ -391,6 +432,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
}
}
},
+ {
+ .bpp = DSC_BPP(15), .bpc = 8,
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 4, -2 }, { 2, 4, -4 },
+ { 3, 4, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 5, 7, -10 },
+ { 5, 8, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 10,
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 8, -2 }, { 6, 8, -4 },
+ { 7, 8, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 },
+ { 9, 12, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 12,
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 12, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 16, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
{ /* sentinel */ }
};
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v2 07/10] drm/display/dsc: include the rest of pre-SCR parameters
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
include them here for completeness.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 72 ++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 35b39f3109c4..aec6f8c201af 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -325,6 +325,16 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+ {
+ .bpp = DSC_BPP(6), .bpc = 8,
+ { 683, 15, 6144, 3, 13, 11, 11, {
+ { 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 },
+ { 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 },
+ { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12, -12 },
+ { 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
+ }
+ }
+ },
{
.bpp = DSC_BPP(8), .bpc = 8,
{ 512, 12, 6144, 3, 12, 11, 11, {
@@ -360,6 +370,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
}
}
},
+ {
+ .bpp = DSC_BPP(10), .bpc = 8,
+ { 410, 12, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 10,
+ { 410, 12, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15, -10 },
+ { 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 12,
+ { 410, 12, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
{
.bpp = DSC_BPP(12), .bpc = 8,
{ 341, 15, 2048, 3, 12, 11, 11, {
@@ -391,6 +432,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
}
}
},
+ {
+ .bpp = DSC_BPP(15), .bpc = 8,
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 4, -2 }, { 2, 4, -4 },
+ { 3, 4, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 5, 7, -10 },
+ { 5, 8, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 10,
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 8, -2 }, { 6, 8, -4 },
+ { 7, 8, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 },
+ { 9, 12, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 12,
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 12, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 16, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
{ /* sentinel */ }
};
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 07/10] drm/display/dsc: include the rest of pre-SCR parameters
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
DSC model contains pre-SCR RC parameters for other bpp/bpc combinations,
include them here for completeness.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 72 ++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 35b39f3109c4..aec6f8c201af 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -325,6 +325,16 @@ struct rc_parameters_data {
#define DSC_BPP(bpp) ((bpp) << 4)
static const struct rc_parameters_data rc_parameters_pre_scr[] = {
+ {
+ .bpp = DSC_BPP(6), .bpc = 8,
+ { 683, 15, 6144, 3, 13, 11, 11, {
+ { 0, 2, 0 }, { 1, 4, -2 }, { 3, 6, -2 }, { 4, 6, -4 },
+ { 5, 7, -6 }, { 5, 7, -6 }, { 6, 7, -6 }, { 6, 8, -8 },
+ { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 }, { 10, 12, -12 },
+ { 10, 13, -12 }, { 12, 14, -12 }, { 15, 15, -12 }
+ }
+ }
+ },
{
.bpp = DSC_BPP(8), .bpc = 8,
{ 512, 12, 6144, 3, 12, 11, 11, {
@@ -360,6 +370,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
}
}
},
+ {
+ .bpp = DSC_BPP(10), .bpc = 8,
+ { 410, 12, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 11, -10 },
+ { 5, 12, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 10,
+ { 410, 12, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 15, -10 },
+ { 9, 16, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 12,
+ { 410, 12, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 19, -10 }, { 13, 20, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
{
.bpp = DSC_BPP(12), .bpc = 8,
{ 341, 15, 2048, 3, 12, 11, 11, {
@@ -391,6 +432,37 @@ static const struct rc_parameters_data rc_parameters_pre_scr[] = {
}
}
},
+ {
+ .bpp = DSC_BPP(15), .bpc = 8,
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 4, -2 }, { 2, 4, -4 },
+ { 3, 4, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 5, 7, -10 },
+ { 5, 8, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 10,
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 8, -2 }, { 6, 8, -4 },
+ { 7, 8, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 9, 11, -10 },
+ { 9, 12, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(15), .bpc = 12,
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 12, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 16, -12 }, { 15, 21, -12 },
+ { 21, 23, -12 }
+ }
+ }
+ },
{ /* sentinel */ }
};
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 08/10] drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
(?)
@ 2023-03-07 13:48 ` Dmitry Baryshkov
-1 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Include RC parameters for YCbCr 4:2:2 and 4:2:0 configurations.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 438 +++++++++++++++++++++++
include/drm/display/drm_dsc_helper.h | 2 +
2 files changed, 440 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index aec6f8c201af..65e810a54257 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -740,6 +740,438 @@ static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{ /* sentinel */ }
};
+static const struct rc_parameters_data rc_parameters_1_2_422[] = {
+ {
+ .bpp = DSC_BPP(6), .bpc = 8,
+ { 512, 15, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 10,
+ { 512, 15, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 12,
+ { 512, 15, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 14,
+ { 512, 15, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 16,
+ { 512, 15, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 8,
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 10,
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 12,
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 14,
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 16,
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 8,
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 14,
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 16,
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 8,
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 10,
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 12,
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 14,
+ { 273, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 16,
+ { 273, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ { /* sentinel */ }
+};
+
+static const struct rc_parameters_data rc_parameters_1_2_420[] = {
+ {
+ .bpp = DSC_BPP(4), .bpc = 8,
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(4), .bpc = 10,
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(4), .bpc = 12,
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(4), .bpc = 14,
+ { 512, 12, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(4), .bpc = 16,
+ { 512, 12, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 8,
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 10,
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 12,
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 14,
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 16,
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 8,
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 12, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 10,
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 12,
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 14,
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 16,
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 8,
+ { 256, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
+ { 256, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
+ { 256, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 14,
+ { 256, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 16,
+ { 256, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ { /* sentinel */ }
+};
+
static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
u16 dsc_bpp,
u8 bits_per_component)
@@ -782,6 +1214,12 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params
case DRM_DSC_1_1_PRE_SCR:
data = rc_parameters_pre_scr;
break;
+ case DRM_DSC_1_2_422:
+ data = rc_parameters_1_2_422;
+ break;
+ case DRM_DSC_1_2_420:
+ data = rc_parameters_1_2_420;
+ break;
default:
return -EINVAL;
}
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index c634bb2935d3..0bb0c3afd740 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -13,6 +13,8 @@
enum drm_dsc_params_kind {
DRM_DSC_1_2_444,
DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
+ DRM_DSC_1_2_422,
+ DRM_DSC_1_2_420,
};
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v2 08/10] drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Include RC parameters for YCbCr 4:2:2 and 4:2:0 configurations.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 438 +++++++++++++++++++++++
include/drm/display/drm_dsc_helper.h | 2 +
2 files changed, 440 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index aec6f8c201af..65e810a54257 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -740,6 +740,438 @@ static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{ /* sentinel */ }
};
+static const struct rc_parameters_data rc_parameters_1_2_422[] = {
+ {
+ .bpp = DSC_BPP(6), .bpc = 8,
+ { 512, 15, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 10,
+ { 512, 15, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 12,
+ { 512, 15, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 14,
+ { 512, 15, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 16,
+ { 512, 15, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 8,
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 10,
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 12,
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 14,
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 16,
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 8,
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 14,
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 16,
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 8,
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 10,
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 12,
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 14,
+ { 273, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 16,
+ { 273, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ { /* sentinel */ }
+};
+
+static const struct rc_parameters_data rc_parameters_1_2_420[] = {
+ {
+ .bpp = DSC_BPP(4), .bpc = 8,
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(4), .bpc = 10,
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(4), .bpc = 12,
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(4), .bpc = 14,
+ { 512, 12, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(4), .bpc = 16,
+ { 512, 12, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 8,
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 10,
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 12,
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 14,
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 16,
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 8,
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 12, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 10,
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 12,
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 14,
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 16,
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 8,
+ { 256, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
+ { 256, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
+ { 256, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 14,
+ { 256, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 16,
+ { 256, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ { /* sentinel */ }
+};
+
static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
u16 dsc_bpp,
u8 bits_per_component)
@@ -782,6 +1214,12 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params
case DRM_DSC_1_1_PRE_SCR:
data = rc_parameters_pre_scr;
break;
+ case DRM_DSC_1_2_422:
+ data = rc_parameters_1_2_422;
+ break;
+ case DRM_DSC_1_2_420:
+ data = rc_parameters_1_2_420;
+ break;
default:
return -EINVAL;
}
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index c634bb2935d3..0bb0c3afd740 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -13,6 +13,8 @@
enum drm_dsc_params_kind {
DRM_DSC_1_2_444,
DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
+ DRM_DSC_1_2_422,
+ DRM_DSC_1_2_420,
};
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 08/10] drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters
@ 2023-03-07 13:48 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:48 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
Include RC parameters for YCbCr 4:2:2 and 4:2:0 configurations.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 438 +++++++++++++++++++++++
include/drm/display/drm_dsc_helper.h | 2 +
2 files changed, 440 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index aec6f8c201af..65e810a54257 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -740,6 +740,438 @@ static const struct rc_parameters_data rc_parameters_1_2_444[] = {
{ /* sentinel */ }
};
+static const struct rc_parameters_data rc_parameters_1_2_422[] = {
+ {
+ .bpp = DSC_BPP(6), .bpc = 8,
+ { 512, 15, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 10,
+ { 512, 15, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 12,
+ { 512, 15, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 14,
+ { 512, 15, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 16,
+ { 512, 15, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 8,
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 10,
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 12,
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 14,
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(7), .bpc = 16,
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 8,
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 14,
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 16,
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 8,
+ { 273, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 10,
+ { 273, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 12,
+ { 273, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 14,
+ { 273, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(10), .bpc = 16,
+ { 273, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ { /* sentinel */ }
+};
+
+static const struct rc_parameters_data rc_parameters_1_2_420[] = {
+ {
+ .bpp = DSC_BPP(4), .bpc = 8,
+ { 512, 12, 6144, 3, 12, 11, 11, {
+ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
+ { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(4), .bpc = 10,
+ { 512, 12, 6144, 7, 16, 15, 15, {
+ { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
+ { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(4), .bpc = 12,
+ { 512, 12, 6144, 11, 20, 19, 19, {
+ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
+ { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(4), .bpc = 14,
+ { 512, 12, 6144, 15, 24, 23, 23, {
+ { 0, 12, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 12, 17, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 22, -10 }, { 17, 22, -10 },
+ { 17, 23, -12 }, { 17, 23, -12 }, { 21, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(4), .bpc = 16,
+ { 512, 12, 6144, 19, 28, 27, 27, {
+ { 0, 12, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 15, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 26, -10 }, { 21, 26, -10 },
+ { 21, 27, -12 }, { 21, 27, -12 }, { 25, 28, -12 },
+ { 28, 29, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 8,
+ { 410, 15, 5632, 3, 12, 11, 11, {
+ { 0, 3, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 2, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 9, -8 }, { 3, 9, -10 }, { 5, 10, -10 }, { 5, 10, -10 },
+ { 5, 11, -12 }, { 7, 11, -12 }, { 11, 12, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 10,
+ { 410, 15, 5632, 7, 16, 15, 15, {
+ { 0, 7, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 6, 10, -2 },
+ { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 13, -8 }, { 7, 13, -10 }, { 9, 14, -10 }, { 9, 14, -10 },
+ { 9, 15, -12 }, { 11, 15, -12 }, { 15, 16, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 12,
+ { 410, 15, 5632, 11, 20, 19, 19, {
+ { 0, 11, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 10, 14, -2 },
+ { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 17, -8 }, { 11, 17, -10 }, { 13, 18, -10 },
+ { 13, 18, -10 }, { 13, 19, -12 }, { 15, 19, -12 },
+ { 19, 20, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 14,
+ { 410, 15, 5632, 15, 24, 23, 23, {
+ { 0, 11, 2 }, { 5, 13, 0 }, { 11, 15, 0 }, { 13, 18, -2 },
+ { 15, 19, -4 }, { 15, 19, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 21, -8 }, { 15, 21, -10 }, { 17, 22, -10 },
+ { 17, 22, -10 }, { 17, 23, -12 }, { 19, 23, -12 },
+ { 23, 24, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(5), .bpc = 16,
+ { 410, 15, 5632, 19, 28, 27, 27, {
+ { 0, 11, 2 }, { 6, 14, 0 }, { 13, 17, 0 }, { 16, 20, -2 },
+ { 19, 23, -4 }, { 19, 23, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 25, -8 }, { 19, 25, -10 }, { 21, 26, -10 },
+ { 21, 26, -10 }, { 21, 27, -12 }, { 23, 27, -12 },
+ { 27, 28, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 8,
+ { 341, 15, 2048, 3, 12, 11, 11, {
+ { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
+ { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
+ { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
+ { 5, 9, -12 }, { 7, 10, -12 }, { 10, 12, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 10,
+ { 341, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
+ { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
+ { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
+ { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 12,
+ { 341, 15, 2048, 11, 20, 19, 19, {
+ { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
+ { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
+ { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
+ { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
+ { 18, 19, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 14,
+ { 341, 15, 2048, 15, 24, 23, 23, {
+ { 0, 6, 2 }, { 7, 10, 0 }, { 9, 13, 0 }, { 11, 16, -2 },
+ { 14, 17, -4 }, { 15, 18, -6 }, { 15, 19, -8 }, { 15, 20, -8 },
+ { 15, 20, -8 }, { 15, 21, -10 }, { 17, 21, -10 },
+ { 17, 21, -12 }, { 17, 21, -12 }, { 19, 22, -12 },
+ { 22, 23, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(6), .bpc = 16,
+ { 341, 15, 2048, 19, 28, 27, 27, {
+ { 0, 6, 2 }, { 6, 11, 0 }, { 11, 15, 0 }, { 14, 18, -2 },
+ { 18, 21, -4 }, { 19, 22, -6 }, { 19, 23, -8 }, { 19, 24, -8 },
+ { 19, 24, -8 }, { 19, 25, -10 }, { 21, 25, -10 },
+ { 21, 25, -12 }, { 21, 25, -12 }, { 23, 26, -12 },
+ { 26, 27, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 8,
+ { 256, 15, 2048, 3, 12, 11, 11, {
+ { 0, 0, 10 }, { 0, 1, 8 }, { 0, 1, 6 }, { 0, 2, 4 },
+ { 1, 2, 2 }, { 1, 3, 0 }, { 1, 3, -2 }, { 2, 4, -4 },
+ { 2, 5, -6 }, { 3, 5, -8 }, { 4, 6, -10 }, { 4, 7, -10 },
+ { 5, 7, -12 }, { 7, 8, -12 }, { 8, 9, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 10,
+ { 256, 15, 2048, 7, 16, 15, 15, {
+ { 0, 2, 10 }, { 2, 5, 8 }, { 3, 5, 6 }, { 4, 6, 4 },
+ { 5, 6, 2 }, { 5, 7, 0 }, { 5, 7, -2 }, { 6, 8, -4 },
+ { 6, 9, -6 }, { 7, 9, -8 }, { 8, 10, -10 }, { 8, 11, -10 },
+ { 9, 11, -12 }, { 11, 12, -12 }, { 12, 13, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 12,
+ { 256, 15, 2048, 11, 20, 19, 19, {
+ { 0, 4, 10 }, { 2, 7, 8 }, { 4, 9, 6 }, { 6, 11, 4 },
+ { 9, 11, 2 }, { 9, 11, 0 }, { 9, 12, -2 }, { 10, 12, -4 },
+ { 11, 13, -6 }, { 11, 13, -8 }, { 12, 14, -10 },
+ { 13, 15, -10 }, { 13, 15, -12 }, { 15, 16, -12 },
+ { 16, 17, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 14,
+ { 256, 15, 2048, 15, 24, 23, 23, {
+ { 0, 4, 10 }, { 3, 8, 8 }, { 6, 11, 6 }, { 9, 14, 4 },
+ { 13, 15, 2 }, { 13, 15, 0 }, { 13, 16, -2 }, { 14, 16, -4 },
+ { 15, 17, -6 }, { 15, 17, -8 }, { 16, 18, -10 },
+ { 17, 19, -10 }, { 17, 19, -12 }, { 19, 20, -12 },
+ { 20, 21, -12 }
+ }
+ }
+ },
+ {
+ .bpp = DSC_BPP(8), .bpc = 16,
+ { 256, 15, 2048, 19, 28, 27, 27, {
+ { 0, 4, 10 }, { 4, 9, 8 }, { 8, 13, 6 }, { 12, 17, 4 },
+ { 17, 19, 2 }, { 17, 20, 0 }, { 17, 20, -2 }, { 18, 20, -4 },
+ { 19, 21, -6 }, { 19, 21, -8 }, { 20, 22, -10 },
+ { 21, 23, -10 }, { 21, 23, -12 }, { 23, 24, -12 },
+ { 24, 25, -12 }
+ }
+ }
+ },
+ { /* sentinel */ }
+};
+
static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
u16 dsc_bpp,
u8 bits_per_component)
@@ -782,6 +1214,12 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params
case DRM_DSC_1_1_PRE_SCR:
data = rc_parameters_pre_scr;
break;
+ case DRM_DSC_1_2_422:
+ data = rc_parameters_1_2_422;
+ break;
+ case DRM_DSC_1_2_420:
+ data = rc_parameters_1_2_420;
+ break;
default:
return -EINVAL;
}
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index c634bb2935d3..0bb0c3afd740 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -13,6 +13,8 @@
enum drm_dsc_params_kind {
DRM_DSC_1_2_444,
DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
+ DRM_DSC_1_2_422,
+ DRM_DSC_1_2_420,
};
void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 09/10] drm/display/dsc: add helper to set semi-const parameters
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
(?)
@ 2023-03-07 13:49 ` Dmitry Baryshkov
-1 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:49 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Add a helper setting config values which are typically constant across
operating modes (table E-4 of the standard) and mux_word_size (which is
a const according to 3.5.2).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 21 +++++++++++++++++++++
include/drm/display/drm_dsc_helper.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 65e810a54257..10ba413d8bf1 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -270,6 +270,27 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
}
EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+/**
+ * drm_dsc_set_const_params() - Set DSC parameters considered typically
+ * constant across operation modes
+ *
+ * @vdsc_cfg:
+ * DSC Configuration data partially filled by driver
+ */
+void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg)
+{
+ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
+ vdsc_cfg->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
+ vdsc_cfg->rc_tgt_offset_high = DSC_RC_TGT_OFFSET_HI_CONST;
+ vdsc_cfg->rc_tgt_offset_low = DSC_RC_TGT_OFFSET_LO_CONST;
+
+ if (vdsc_cfg->bits_per_component <= 10)
+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
+ else
+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
+}
+EXPORT_SYMBOL(drm_dsc_set_const_params);
+
/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
static const u16 drm_dsc_rc_buf_thresh[] = {
896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 0bb0c3afd740..4448c482b092 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -21,6 +21,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
+void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v2 09/10] drm/display/dsc: add helper to set semi-const parameters
@ 2023-03-07 13:49 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:49 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Add a helper setting config values which are typically constant across
operating modes (table E-4 of the standard) and mux_word_size (which is
a const according to 3.5.2).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 21 +++++++++++++++++++++
include/drm/display/drm_dsc_helper.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 65e810a54257..10ba413d8bf1 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -270,6 +270,27 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
}
EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+/**
+ * drm_dsc_set_const_params() - Set DSC parameters considered typically
+ * constant across operation modes
+ *
+ * @vdsc_cfg:
+ * DSC Configuration data partially filled by driver
+ */
+void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg)
+{
+ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
+ vdsc_cfg->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
+ vdsc_cfg->rc_tgt_offset_high = DSC_RC_TGT_OFFSET_HI_CONST;
+ vdsc_cfg->rc_tgt_offset_low = DSC_RC_TGT_OFFSET_LO_CONST;
+
+ if (vdsc_cfg->bits_per_component <= 10)
+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
+ else
+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
+}
+EXPORT_SYMBOL(drm_dsc_set_const_params);
+
/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
static const u16 drm_dsc_rc_buf_thresh[] = {
896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 0bb0c3afd740..4448c482b092 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -21,6 +21,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
+void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 09/10] drm/display/dsc: add helper to set semi-const parameters
@ 2023-03-07 13:49 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:49 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
Add a helper setting config values which are typically constant across
operating modes (table E-4 of the standard) and mux_word_size (which is
a const according to 3.5.2).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/display/drm_dsc_helper.c | 21 +++++++++++++++++++++
include/drm/display/drm_dsc_helper.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
index 65e810a54257..10ba413d8bf1 100644
--- a/drivers/gpu/drm/display/drm_dsc_helper.c
+++ b/drivers/gpu/drm/display/drm_dsc_helper.c
@@ -270,6 +270,27 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
}
EXPORT_SYMBOL(drm_dsc_pps_payload_pack);
+/**
+ * drm_dsc_set_const_params() - Set DSC parameters considered typically
+ * constant across operation modes
+ *
+ * @vdsc_cfg:
+ * DSC Configuration data partially filled by driver
+ */
+void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg)
+{
+ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
+ vdsc_cfg->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
+ vdsc_cfg->rc_tgt_offset_high = DSC_RC_TGT_OFFSET_HI_CONST;
+ vdsc_cfg->rc_tgt_offset_low = DSC_RC_TGT_OFFSET_LO_CONST;
+
+ if (vdsc_cfg->bits_per_component <= 10)
+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
+ else
+ vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
+}
+EXPORT_SYMBOL(drm_dsc_set_const_params);
+
/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
static const u16 drm_dsc_rc_buf_thresh[] = {
896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
index 0bb0c3afd740..4448c482b092 100644
--- a/include/drm/display/drm_dsc_helper.h
+++ b/include/drm/display/drm_dsc_helper.h
@@ -21,6 +21,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
const struct drm_dsc_config *dsc_cfg);
+void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg);
void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 10/10] drm/msm/dsi: use new helpers for DSC setup
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
(?)
@ 2023-03-07 13:49 ` Dmitry Baryshkov
-1 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:49 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Use new DRM DSC helpers to setup DSI DSC configuration. The
initial_scale_value needs to be adjusted according to the standard, but
this is a separate change.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 61 ++++--------------------------
1 file changed, 8 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 18fa30e1e858..dda989727921 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1735,28 +1735,9 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
return -EINVAL;
}
-static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
- 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
- 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
-};
-
-/* only 8bpc, 8bpp added */
-static char min_qp[DSC_NUM_BUF_RANGES] = {
- 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
-};
-
-static char max_qp[DSC_NUM_BUF_RANGES] = {
- 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
-};
-
-static char bpg_offset[DSC_NUM_BUF_RANGES] = {
- 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
-};
-
static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)
{
- int i;
- u16 bpp = dsc->bits_per_pixel >> 4;
+ int ret;
if (dsc->bits_per_pixel & 0xf) {
DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
@@ -1768,49 +1749,23 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc
return -EOPNOTSUPP;
}
- dsc->rc_model_size = 8192;
- dsc->first_line_bpg_offset = 12;
- dsc->rc_edge_factor = 6;
- dsc->rc_tgt_offset_high = 3;
- dsc->rc_tgt_offset_low = 3;
dsc->simple_422 = 0;
dsc->convert_rgb = 1;
dsc->vbr_enable = 0;
- /* handle only bpp = bpc = 8 */
- for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
- dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
+ drm_dsc_set_const_params(dsc);
+ drm_dsc_set_rc_buf_thresh(dsc);
- for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
- dsc->rc_range_params[i].range_min_qp = min_qp[i];
- dsc->rc_range_params[i].range_max_qp = max_qp[i];
- /*
- * Range BPG Offset contains two's-complement signed values that fill
- * 8 bits, yet the registers and DCS PPS field are only 6 bits wide.
- */
- dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK;
+ /* handle only bpp = bpc = 8, pre-SCR panels */
+ ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR);
+ if (ret) {
+ DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n");
+ return ret;
}
- dsc->initial_offset = 6144; /* Not bpp 12 */
- if (bpp != 8)
- dsc->initial_offset = 2048; /* bpp = 12 */
-
- if (dsc->bits_per_component <= 10)
- dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
- else
- dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
-
- dsc->initial_xmit_delay = 512;
dsc->initial_scale_value = 32;
- dsc->first_line_bpg_offset = 12;
dsc->line_buf_depth = dsc->bits_per_component + 1;
- /* bpc 8 */
- dsc->flatness_min_qp = 3;
- dsc->flatness_max_qp = 12;
- dsc->rc_quant_incr_limit0 = 11;
- dsc->rc_quant_incr_limit1 = 11;
-
return drm_dsc_compute_rc_parameters(dsc);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [Intel-gfx] [PATCH v2 10/10] drm/msm/dsi: use new helpers for DSC setup
@ 2023-03-07 13:49 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:49 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
Use new DRM DSC helpers to setup DSI DSC configuration. The
initial_scale_value needs to be adjusted according to the standard, but
this is a separate change.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 61 ++++--------------------------
1 file changed, 8 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 18fa30e1e858..dda989727921 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1735,28 +1735,9 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
return -EINVAL;
}
-static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
- 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
- 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
-};
-
-/* only 8bpc, 8bpp added */
-static char min_qp[DSC_NUM_BUF_RANGES] = {
- 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
-};
-
-static char max_qp[DSC_NUM_BUF_RANGES] = {
- 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
-};
-
-static char bpg_offset[DSC_NUM_BUF_RANGES] = {
- 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
-};
-
static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)
{
- int i;
- u16 bpp = dsc->bits_per_pixel >> 4;
+ int ret;
if (dsc->bits_per_pixel & 0xf) {
DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
@@ -1768,49 +1749,23 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc
return -EOPNOTSUPP;
}
- dsc->rc_model_size = 8192;
- dsc->first_line_bpg_offset = 12;
- dsc->rc_edge_factor = 6;
- dsc->rc_tgt_offset_high = 3;
- dsc->rc_tgt_offset_low = 3;
dsc->simple_422 = 0;
dsc->convert_rgb = 1;
dsc->vbr_enable = 0;
- /* handle only bpp = bpc = 8 */
- for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
- dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
+ drm_dsc_set_const_params(dsc);
+ drm_dsc_set_rc_buf_thresh(dsc);
- for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
- dsc->rc_range_params[i].range_min_qp = min_qp[i];
- dsc->rc_range_params[i].range_max_qp = max_qp[i];
- /*
- * Range BPG Offset contains two's-complement signed values that fill
- * 8 bits, yet the registers and DCS PPS field are only 6 bits wide.
- */
- dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK;
+ /* handle only bpp = bpc = 8, pre-SCR panels */
+ ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR);
+ if (ret) {
+ DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n");
+ return ret;
}
- dsc->initial_offset = 6144; /* Not bpp 12 */
- if (bpp != 8)
- dsc->initial_offset = 2048; /* bpp = 12 */
-
- if (dsc->bits_per_component <= 10)
- dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
- else
- dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
-
- dsc->initial_xmit_delay = 512;
dsc->initial_scale_value = 32;
- dsc->first_line_bpg_offset = 12;
dsc->line_buf_depth = dsc->bits_per_component + 1;
- /* bpc 8 */
- dsc->flatness_min_qp = 3;
- dsc->flatness_max_qp = 12;
- dsc->rc_quant_incr_limit0 = 11;
- dsc->rc_quant_incr_limit1 = 11;
-
return drm_dsc_compute_rc_parameters(dsc);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 10/10] drm/msm/dsi: use new helpers for DSC setup
@ 2023-03-07 13:49 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-07 13:49 UTC (permalink / raw)
To: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
Use new DRM DSC helpers to setup DSI DSC configuration. The
initial_scale_value needs to be adjusted according to the standard, but
this is a separate change.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 61 ++++--------------------------
1 file changed, 8 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 18fa30e1e858..dda989727921 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1735,28 +1735,9 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
return -EINVAL;
}
-static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
- 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
- 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
-};
-
-/* only 8bpc, 8bpp added */
-static char min_qp[DSC_NUM_BUF_RANGES] = {
- 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
-};
-
-static char max_qp[DSC_NUM_BUF_RANGES] = {
- 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
-};
-
-static char bpg_offset[DSC_NUM_BUF_RANGES] = {
- 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
-};
-
static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)
{
- int i;
- u16 bpp = dsc->bits_per_pixel >> 4;
+ int ret;
if (dsc->bits_per_pixel & 0xf) {
DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
@@ -1768,49 +1749,23 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc
return -EOPNOTSUPP;
}
- dsc->rc_model_size = 8192;
- dsc->first_line_bpg_offset = 12;
- dsc->rc_edge_factor = 6;
- dsc->rc_tgt_offset_high = 3;
- dsc->rc_tgt_offset_low = 3;
dsc->simple_422 = 0;
dsc->convert_rgb = 1;
dsc->vbr_enable = 0;
- /* handle only bpp = bpc = 8 */
- for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
- dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
+ drm_dsc_set_const_params(dsc);
+ drm_dsc_set_rc_buf_thresh(dsc);
- for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
- dsc->rc_range_params[i].range_min_qp = min_qp[i];
- dsc->rc_range_params[i].range_max_qp = max_qp[i];
- /*
- * Range BPG Offset contains two's-complement signed values that fill
- * 8 bits, yet the registers and DCS PPS field are only 6 bits wide.
- */
- dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK;
+ /* handle only bpp = bpc = 8, pre-SCR panels */
+ ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR);
+ if (ret) {
+ DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n");
+ return ret;
}
- dsc->initial_offset = 6144; /* Not bpp 12 */
- if (bpp != 8)
- dsc->initial_offset = 2048; /* bpp = 12 */
-
- if (dsc->bits_per_component <= 10)
- dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
- else
- dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
-
- dsc->initial_xmit_delay = 512;
dsc->initial_scale_value = 32;
- dsc->first_line_bpg_offset = 12;
dsc->line_buf_depth = dsc->bits_per_component + 1;
- /* bpc 8 */
- dsc->flatness_min_qp = 3;
- dsc->flatness_max_qp = 12;
- dsc->rc_quant_incr_limit0 = 11;
- dsc->rc_quant_incr_limit1 = 11;
-
return drm_dsc_compute_rc_parameters(dsc);
}
--
2.39.2
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
2023-03-07 13:48 ` Dmitry Baryshkov
(?)
@ 2023-03-08 10:14 ` Jani Nikula
-1 siblings, 0 replies; 47+ messages in thread
From: Jani Nikula @ 2023-03-08 10:14 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: Ville Syrjälä, dri-devel, intel-gfx, linux-arm-msm, freedreno
On Tue, 07 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in
> preparation to adding more configuration data.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
> drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> include/drm/display/drm_dsc_helper.h | 7 +-
> 3 files changed, 119 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index acb93d4116e0..35b39f3109c4 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -324,11 +324,81 @@ struct rc_parameters_data {
>
> #define DSC_BPP(bpp) ((bpp) << 4)
>
> +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> + {
> + .bpp = DSC_BPP(8), .bpc = 8,
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 10,
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 12,
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 8,
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 10,
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 12,
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + { /* sentinel */ }
> +};
> +
> /*
> * Selected Rate Control Related Parameter Recommended Values
> * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> */
The comment is no longer accurate, is it?
There are various ways to determine the parameters to use. There's even
an application note "VESA DSC v1.2a Guidance on Deriving DSC Rate
Control Parameters" that lists the options. They are all valid and
should "provide visually lossless quality".
Would it be simplest to always use the C model parameters in the tables
here, referencing the zip file name with date above each table? That
could at least be consistent, and drivers could override parameters
using other methods if they desire. And it would be easiest to review.
I'm having a hard time finding time to review all this in a timely
fashion. Would be good to try to get other folks to review the rest,
it's really not very i915 specific anyway. In the mean time I think
patches 1-5 are okay to merge via drm-misc.
BR,
Jani.
> -static const struct rc_parameters_data rc_parameters[] = {
> +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> {
> .bpp = DSC_BPP(6), .bpc = 8,
> { 768, 15, 6144, 3, 13, 11, 11, {
> @@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 512, 12, 6144, 3, 12, 11, 11, {
> { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
> + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
> }
> }
> },
> {
> .bpp = DSC_BPP(8), .bpc = 10,
> { 512, 12, 6144, 7, 16, 15, 15, {
> - /*
> - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> - * VESA DSC 1.1 Table E-5 sets it to 4.
> - */
> - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
> + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
> }
> }
> },
> @@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 512, 12, 6144, 11, 20, 19, 19, {
> { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
> + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
> + { 20, 21, -12 }
> }
> }
> },
> @@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 3, 12, 11, 11, {
> { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
> + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
> }
> }
> },
> @@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 7, 16, 15, 15, {
> { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
> + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
> }
> }
> },
> @@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 11, 20, 19, 19, {
> { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
> + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
> + { 18, 19, -12 }
> }
> }
> },
> @@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { /* sentinel */ }
> };
>
> -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
> + u16 dsc_bpp,
> u8 bits_per_component)
> {
> int i;
> @@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> * function.
> *
> * @vdsc_cfg: DSC Configuration data partially filled by driver
> + * @kind: operating mode and standard to follow
> *
> * Return: 0 or -error code in case of an error
> */
> -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
> {
> + const struct rc_parameters_data *data;
> const struct rc_parameters *rc_params;
> int i;
>
> @@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> !vdsc_cfg->bits_per_component))
> return -EINVAL;
>
> - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> + switch (kind) {
> + case DRM_DSC_1_2_444:
> + data = rc_parameters_1_2_444;
> + break;
> + case DRM_DSC_1_1_PRE_SCR:
> + data = rc_parameters_pre_scr;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + rc_params = get_rc_params(data,
> + vdsc_cfg->bits_per_pixel,
> vdsc_cfg->bits_per_component);
> if (!rc_params)
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 20a4c2f343fe..a4d1d2ba71bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> if (DISPLAY_VER(dev_priv) >= 13) {
> calculate_rc_params(vdsc_cfg);
> } else {
> - ret = drm_dsc_setup_rc_params(vdsc_cfg);
> + if ((compressed_bpp == 8 ||
> + compressed_bpp == 12) &&
> + (vdsc_cfg->bits_per_component == 8 ||
> + vdsc_cfg->bits_per_component == 10 ||
> + vdsc_cfg->bits_per_component == 12))
> + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
> + else
> + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
> +
> if (ret)
> return ret;
>
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 1681791f65a5..c634bb2935d3 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -10,12 +10,17 @@
>
> #include <drm/display/drm_dsc.h>
>
> +enum drm_dsc_params_kind {
> + DRM_DSC_1_2_444,
> + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
> +};
> +
> void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-03-08 10:14 ` Jani Nikula
0 siblings, 0 replies; 47+ messages in thread
From: Jani Nikula @ 2023-03-08 10:14 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 07 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in
> preparation to adding more configuration data.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
> drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> include/drm/display/drm_dsc_helper.h | 7 +-
> 3 files changed, 119 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index acb93d4116e0..35b39f3109c4 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -324,11 +324,81 @@ struct rc_parameters_data {
>
> #define DSC_BPP(bpp) ((bpp) << 4)
>
> +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> + {
> + .bpp = DSC_BPP(8), .bpc = 8,
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 10,
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 12,
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 8,
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 10,
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 12,
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + { /* sentinel */ }
> +};
> +
> /*
> * Selected Rate Control Related Parameter Recommended Values
> * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> */
The comment is no longer accurate, is it?
There are various ways to determine the parameters to use. There's even
an application note "VESA DSC v1.2a Guidance on Deriving DSC Rate
Control Parameters" that lists the options. They are all valid and
should "provide visually lossless quality".
Would it be simplest to always use the C model parameters in the tables
here, referencing the zip file name with date above each table? That
could at least be consistent, and drivers could override parameters
using other methods if they desire. And it would be easiest to review.
I'm having a hard time finding time to review all this in a timely
fashion. Would be good to try to get other folks to review the rest,
it's really not very i915 specific anyway. In the mean time I think
patches 1-5 are okay to merge via drm-misc.
BR,
Jani.
> -static const struct rc_parameters_data rc_parameters[] = {
> +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> {
> .bpp = DSC_BPP(6), .bpc = 8,
> { 768, 15, 6144, 3, 13, 11, 11, {
> @@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 512, 12, 6144, 3, 12, 11, 11, {
> { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
> + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
> }
> }
> },
> {
> .bpp = DSC_BPP(8), .bpc = 10,
> { 512, 12, 6144, 7, 16, 15, 15, {
> - /*
> - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> - * VESA DSC 1.1 Table E-5 sets it to 4.
> - */
> - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
> + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
> }
> }
> },
> @@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 512, 12, 6144, 11, 20, 19, 19, {
> { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
> + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
> + { 20, 21, -12 }
> }
> }
> },
> @@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 3, 12, 11, 11, {
> { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
> + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
> }
> }
> },
> @@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 7, 16, 15, 15, {
> { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
> + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
> }
> }
> },
> @@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 11, 20, 19, 19, {
> { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
> + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
> + { 18, 19, -12 }
> }
> }
> },
> @@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { /* sentinel */ }
> };
>
> -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
> + u16 dsc_bpp,
> u8 bits_per_component)
> {
> int i;
> @@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> * function.
> *
> * @vdsc_cfg: DSC Configuration data partially filled by driver
> + * @kind: operating mode and standard to follow
> *
> * Return: 0 or -error code in case of an error
> */
> -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
> {
> + const struct rc_parameters_data *data;
> const struct rc_parameters *rc_params;
> int i;
>
> @@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> !vdsc_cfg->bits_per_component))
> return -EINVAL;
>
> - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> + switch (kind) {
> + case DRM_DSC_1_2_444:
> + data = rc_parameters_1_2_444;
> + break;
> + case DRM_DSC_1_1_PRE_SCR:
> + data = rc_parameters_pre_scr;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + rc_params = get_rc_params(data,
> + vdsc_cfg->bits_per_pixel,
> vdsc_cfg->bits_per_component);
> if (!rc_params)
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 20a4c2f343fe..a4d1d2ba71bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> if (DISPLAY_VER(dev_priv) >= 13) {
> calculate_rc_params(vdsc_cfg);
> } else {
> - ret = drm_dsc_setup_rc_params(vdsc_cfg);
> + if ((compressed_bpp == 8 ||
> + compressed_bpp == 12) &&
> + (vdsc_cfg->bits_per_component == 8 ||
> + vdsc_cfg->bits_per_component == 10 ||
> + vdsc_cfg->bits_per_component == 12))
> + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
> + else
> + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
> +
> if (ret)
> return ret;
>
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 1681791f65a5..c634bb2935d3 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -10,12 +10,17 @@
>
> #include <drm/display/drm_dsc.h>
>
> +enum drm_dsc_params_kind {
> + DRM_DSC_1_2_444,
> + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
> +};
> +
> void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-03-08 10:14 ` Jani Nikula
0 siblings, 0 replies; 47+ messages in thread
From: Jani Nikula @ 2023-03-08 10:14 UTC (permalink / raw)
To: Dmitry Baryshkov, David Airlie, Daniel Vetter, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, Rob Clark, Abhinav Kumar,
Sean Paul, Marijn Suijten
Cc: linux-arm-msm, intel-gfx, freedreno, dri-devel
On Tue, 07 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> The array of rc_parameters contains a mixture of parameters from DSC 1.1
> and DSC 1.2 standards. Split these tow configuration arrays in
> preparation to adding more configuration data.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
> drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> include/drm/display/drm_dsc_helper.h | 7 +-
> 3 files changed, 119 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> index acb93d4116e0..35b39f3109c4 100644
> --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> @@ -324,11 +324,81 @@ struct rc_parameters_data {
>
> #define DSC_BPP(bpp) ((bpp) << 4)
>
> +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> + {
> + .bpp = DSC_BPP(8), .bpc = 8,
> + { 512, 12, 6144, 3, 12, 11, 11, {
> + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 10,
> + { 512, 12, 6144, 7, 16, 15, 15, {
> + /*
> + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> + * VESA DSC 1.1 Table E-5 sets it to 4.
> + */
> + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(8), .bpc = 12,
> + { 512, 12, 6144, 11, 20, 19, 19, {
> + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 8,
> + { 341, 15, 2048, 3, 12, 11, 11, {
> + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 10,
> + { 341, 15, 2048, 7, 16, 15, 15, {
> + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + }
> + }
> + },
> + {
> + .bpp = DSC_BPP(12), .bpc = 12,
> + { 341, 15, 2048, 11, 20, 19, 19, {
> + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> + { 21, 23, -12 }
> + }
> + }
> + },
> + { /* sentinel */ }
> +};
> +
> /*
> * Selected Rate Control Related Parameter Recommended Values
> * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> */
The comment is no longer accurate, is it?
There are various ways to determine the parameters to use. There's even
an application note "VESA DSC v1.2a Guidance on Deriving DSC Rate
Control Parameters" that lists the options. They are all valid and
should "provide visually lossless quality".
Would it be simplest to always use the C model parameters in the tables
here, referencing the zip file name with date above each table? That
could at least be consistent, and drivers could override parameters
using other methods if they desire. And it would be easiest to review.
I'm having a hard time finding time to review all this in a timely
fashion. Would be good to try to get other folks to review the rest,
it's really not very i915 specific anyway. In the mean time I think
patches 1-5 are okay to merge via drm-misc.
BR,
Jani.
> -static const struct rc_parameters_data rc_parameters[] = {
> +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> {
> .bpp = DSC_BPP(6), .bpc = 8,
> { 768, 15, 6144, 3, 13, 11, 11, {
> @@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 512, 12, 6144, 3, 12, 11, 11, {
> { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
> + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
> }
> }
> },
> {
> .bpp = DSC_BPP(8), .bpc = 10,
> { 512, 12, 6144, 7, 16, 15, 15, {
> - /*
> - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> - * VESA DSC 1.1 Table E-5 sets it to 4.
> - */
> - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
> + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
> }
> }
> },
> @@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 512, 12, 6144, 11, 20, 19, 19, {
> { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
> + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
> + { 20, 21, -12 }
> }
> }
> },
> @@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 3, 12, 11, 11, {
> { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
> + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
> }
> }
> },
> @@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 7, 16, 15, 15, {
> { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
> + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
> }
> }
> },
> @@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> { 341, 15, 2048, 11, 20, 19, 19, {
> { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> - { 21, 23, -12 }
> + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
> + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
> + { 18, 19, -12 }
> }
> }
> },
> @@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> { /* sentinel */ }
> };
>
> -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
> + u16 dsc_bpp,
> u8 bits_per_component)
> {
> int i;
> @@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> * function.
> *
> * @vdsc_cfg: DSC Configuration data partially filled by driver
> + * @kind: operating mode and standard to follow
> *
> * Return: 0 or -error code in case of an error
> */
> -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
> {
> + const struct rc_parameters_data *data;
> const struct rc_parameters *rc_params;
> int i;
>
> @@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> !vdsc_cfg->bits_per_component))
> return -EINVAL;
>
> - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> + switch (kind) {
> + case DRM_DSC_1_2_444:
> + data = rc_parameters_1_2_444;
> + break;
> + case DRM_DSC_1_1_PRE_SCR:
> + data = rc_parameters_pre_scr;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + rc_params = get_rc_params(data,
> + vdsc_cfg->bits_per_pixel,
> vdsc_cfg->bits_per_component);
> if (!rc_params)
> return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 20a4c2f343fe..a4d1d2ba71bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> if (DISPLAY_VER(dev_priv) >= 13) {
> calculate_rc_params(vdsc_cfg);
> } else {
> - ret = drm_dsc_setup_rc_params(vdsc_cfg);
> + if ((compressed_bpp == 8 ||
> + compressed_bpp == 12) &&
> + (vdsc_cfg->bits_per_component == 8 ||
> + vdsc_cfg->bits_per_component == 10 ||
> + vdsc_cfg->bits_per_component == 12))
> + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
> + else
> + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
> +
> if (ret)
> return ret;
>
> diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> index 1681791f65a5..c634bb2935d3 100644
> --- a/include/drm/display/drm_dsc_helper.h
> +++ b/include/drm/display/drm_dsc_helper.h
> @@ -10,12 +10,17 @@
>
> #include <drm/display/drm_dsc.h>
>
> +enum drm_dsc_params_kind {
> + DRM_DSC_1_2_444,
> + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
> +};
> +
> void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> const struct drm_dsc_config *dsc_cfg);
> void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
> int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>
> #endif /* _DRM_DSC_HELPER_H_ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
2023-03-08 10:14 ` Jani Nikula
(?)
@ 2023-03-08 12:59 ` Dmitry Baryshkov
-1 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-08 12:59 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-arm-msm, Tvrtko Ursulin, Sean Paul, intel-gfx,
Abhinav Kumar, dri-devel, Rodrigo Vivi, Marijn Suijten,
freedreno
On Wed, 8 Mar 2023 at 12:14, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Tue, 07 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> > The array of rc_parameters contains a mixture of parameters from DSC 1.1
> > and DSC 1.2 standards. Split these tow configuration arrays in
> > preparation to adding more configuration data.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> > include/drm/display/drm_dsc_helper.h | 7 +-
> > 3 files changed, 119 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> > index acb93d4116e0..35b39f3109c4 100644
> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> > @@ -324,11 +324,81 @@ struct rc_parameters_data {
> >
> > #define DSC_BPP(bpp) ((bpp) << 4)
> >
> > +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> > + {
> > + .bpp = DSC_BPP(8), .bpc = 8,
> > + { 512, 12, 6144, 3, 12, 11, 11, {
> > + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> > + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(8), .bpc = 10,
> > + { 512, 12, 6144, 7, 16, 15, 15, {
> > + /*
> > + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> > + * VESA DSC 1.1 Table E-5 sets it to 4.
> > + */
> > + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(8), .bpc = 12,
> > + { 512, 12, 6144, 11, 20, 19, 19, {
> > + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> > + { 21, 23, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(12), .bpc = 8,
> > + { 341, 15, 2048, 3, 12, 11, 11, {
> > + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> > + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(12), .bpc = 10,
> > + { 341, 15, 2048, 7, 16, 15, 15, {
> > + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> > + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(12), .bpc = 12,
> > + { 341, 15, 2048, 11, 20, 19, 19, {
> > + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> > + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> > + { 21, 23, -12 }
> > + }
> > + }
> > + },
> > + { /* sentinel */ }
> > +};
> > +
> > /*
> > * Selected Rate Control Related Parameter Recommended Values
> > * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> > */
>
> The comment is no longer accurate, is it?
Ugh, yes. it is no longer DSC 1.1. I cross-checked, the rc*cfg files
are the same between 20161212 and 20210623
>
> There are various ways to determine the parameters to use. There's even
> an application note "VESA DSC v1.2a Guidance on Deriving DSC Rate
> Control Parameters" that lists the options. They are all valid and
> should "provide visually lossless quality".
>
> Would it be simplest to always use the C model parameters in the tables
> here, referencing the zip file name with date above each table? That
> could at least be consistent, and drivers could override parameters
> using other methods if they desire. And it would be easiest to review.
Do you mean the calculated RC parameters? As I mentioned in another
email, it is at least worth investigating. I haven't looked into that,
as my primary goal (driven by the forthcoming drm/msm needs) were the
.cfg tables. I targeted cleaning up the simplest path to reduce
duplication (see [1]). Anyway, with the proposed patches we have the
API, which tells nothing about the way it fills out the RC tables.
They can be based on top of the cfg files (method 2) or calculated
(methods 3, 4).
[1] https://patchwork.freedesktop.org/patch/524051/?series=114355&rev=1
>
> I'm having a hard time finding time to review all this in a timely
> fashion. Would be good to try to get other folks to review the rest,
> it's really not very i915 specific anyway. In the mean time I think
> patches 1-5 are okay to merge via drm-misc.
For reference, the tables here are a direct conversion of the rc*cfg
files found in the DSC model. If you wish, I can post the program that
I used to convert these files into C arrays. Will that help the
review?
>
> BR,
> Jani.
>
> > -static const struct rc_parameters_data rc_parameters[] = {
> > +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> > {
> > .bpp = DSC_BPP(6), .bpc = 8,
> > { 768, 15, 6144, 3, 13, 11, 11, {
> > @@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 512, 12, 6144, 3, 12, 11, 11, {
> > { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> > - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
> > + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
> > }
> > }
> > },
> > {
> > .bpp = DSC_BPP(8), .bpc = 10,
> > { 512, 12, 6144, 7, 16, 15, 15, {
> > - /*
> > - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> > - * VESA DSC 1.1 Table E-5 sets it to 4.
> > - */
> > - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> > + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> > { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
> > + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
> > }
> > }
> > },
> > @@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 512, 12, 6144, 11, 20, 19, 19, {
> > { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> > { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> > - { 21, 23, -12 }
> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
> > + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
> > + { 20, 21, -12 }
> > }
> > }
> > },
> > @@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 341, 15, 2048, 3, 12, 11, 11, {
> > { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> > - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> > + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
> > + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
> > }
> > }
> > },
> > @@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 341, 15, 2048, 7, 16, 15, 15, {
> > { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> > { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> > + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
> > + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
> > }
> > }
> > },
> > @@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 341, 15, 2048, 11, 20, 19, 19, {
> > { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> > { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> > - { 21, 23, -12 }
> > + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
> > + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
> > + { 18, 19, -12 }
> > }
> > }
> > },
> > @@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { /* sentinel */ }
> > };
> >
> > -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> > +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
> > + u16 dsc_bpp,
> > u8 bits_per_component)
> > {
> > int i;
> > @@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> > * function.
> > *
> > * @vdsc_cfg: DSC Configuration data partially filled by driver
> > + * @kind: operating mode and standard to follow
> > *
> > * Return: 0 or -error code in case of an error
> > */
> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
> > {
> > + const struct rc_parameters_data *data;
> > const struct rc_parameters *rc_params;
> > int i;
> >
> > @@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> > !vdsc_cfg->bits_per_component))
> > return -EINVAL;
> >
> > - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> > + switch (kind) {
> > + case DRM_DSC_1_2_444:
> > + data = rc_parameters_1_2_444;
> > + break;
> > + case DRM_DSC_1_1_PRE_SCR:
> > + data = rc_parameters_pre_scr;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + rc_params = get_rc_params(data,
> > + vdsc_cfg->bits_per_pixel,
> > vdsc_cfg->bits_per_component);
> > if (!rc_params)
> > return -EINVAL;
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index 20a4c2f343fe..a4d1d2ba71bb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> > if (DISPLAY_VER(dev_priv) >= 13) {
> > calculate_rc_params(vdsc_cfg);
> > } else {
> > - ret = drm_dsc_setup_rc_params(vdsc_cfg);
> > + if ((compressed_bpp == 8 ||
> > + compressed_bpp == 12) &&
> > + (vdsc_cfg->bits_per_component == 8 ||
> > + vdsc_cfg->bits_per_component == 10 ||
> > + vdsc_cfg->bits_per_component == 12))
> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
> > + else
> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
> > +
> > if (ret)
> > return ret;
> >
> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> > index 1681791f65a5..c634bb2935d3 100644
> > --- a/include/drm/display/drm_dsc_helper.h
> > +++ b/include/drm/display/drm_dsc_helper.h
> > @@ -10,12 +10,17 @@
> >
> > #include <drm/display/drm_dsc.h>
> >
> > +enum drm_dsc_params_kind {
> > + DRM_DSC_1_2_444,
> > + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
> > +};
> > +
> > void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> > const struct drm_dsc_config *dsc_cfg);
> > void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
> >
> > #endif /* _DRM_DSC_HELPER_H_ */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-03-08 12:59 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-08 12:59 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-arm-msm, intel-gfx, Abhinav Kumar, dri-devel,
Daniel Vetter, Rodrigo Vivi, Marijn Suijten, freedreno,
David Airlie
On Wed, 8 Mar 2023 at 12:14, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Tue, 07 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> > The array of rc_parameters contains a mixture of parameters from DSC 1.1
> > and DSC 1.2 standards. Split these tow configuration arrays in
> > preparation to adding more configuration data.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> > include/drm/display/drm_dsc_helper.h | 7 +-
> > 3 files changed, 119 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> > index acb93d4116e0..35b39f3109c4 100644
> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> > @@ -324,11 +324,81 @@ struct rc_parameters_data {
> >
> > #define DSC_BPP(bpp) ((bpp) << 4)
> >
> > +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> > + {
> > + .bpp = DSC_BPP(8), .bpc = 8,
> > + { 512, 12, 6144, 3, 12, 11, 11, {
> > + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> > + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(8), .bpc = 10,
> > + { 512, 12, 6144, 7, 16, 15, 15, {
> > + /*
> > + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> > + * VESA DSC 1.1 Table E-5 sets it to 4.
> > + */
> > + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(8), .bpc = 12,
> > + { 512, 12, 6144, 11, 20, 19, 19, {
> > + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> > + { 21, 23, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(12), .bpc = 8,
> > + { 341, 15, 2048, 3, 12, 11, 11, {
> > + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> > + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(12), .bpc = 10,
> > + { 341, 15, 2048, 7, 16, 15, 15, {
> > + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> > + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(12), .bpc = 12,
> > + { 341, 15, 2048, 11, 20, 19, 19, {
> > + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> > + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> > + { 21, 23, -12 }
> > + }
> > + }
> > + },
> > + { /* sentinel */ }
> > +};
> > +
> > /*
> > * Selected Rate Control Related Parameter Recommended Values
> > * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> > */
>
> The comment is no longer accurate, is it?
Ugh, yes. it is no longer DSC 1.1. I cross-checked, the rc*cfg files
are the same between 20161212 and 20210623
>
> There are various ways to determine the parameters to use. There's even
> an application note "VESA DSC v1.2a Guidance on Deriving DSC Rate
> Control Parameters" that lists the options. They are all valid and
> should "provide visually lossless quality".
>
> Would it be simplest to always use the C model parameters in the tables
> here, referencing the zip file name with date above each table? That
> could at least be consistent, and drivers could override parameters
> using other methods if they desire. And it would be easiest to review.
Do you mean the calculated RC parameters? As I mentioned in another
email, it is at least worth investigating. I haven't looked into that,
as my primary goal (driven by the forthcoming drm/msm needs) were the
.cfg tables. I targeted cleaning up the simplest path to reduce
duplication (see [1]). Anyway, with the proposed patches we have the
API, which tells nothing about the way it fills out the RC tables.
They can be based on top of the cfg files (method 2) or calculated
(methods 3, 4).
[1] https://patchwork.freedesktop.org/patch/524051/?series=114355&rev=1
>
> I'm having a hard time finding time to review all this in a timely
> fashion. Would be good to try to get other folks to review the rest,
> it's really not very i915 specific anyway. In the mean time I think
> patches 1-5 are okay to merge via drm-misc.
For reference, the tables here are a direct conversion of the rc*cfg
files found in the DSC model. If you wish, I can post the program that
I used to convert these files into C arrays. Will that help the
review?
>
> BR,
> Jani.
>
> > -static const struct rc_parameters_data rc_parameters[] = {
> > +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> > {
> > .bpp = DSC_BPP(6), .bpc = 8,
> > { 768, 15, 6144, 3, 13, 11, 11, {
> > @@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 512, 12, 6144, 3, 12, 11, 11, {
> > { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> > - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
> > + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
> > }
> > }
> > },
> > {
> > .bpp = DSC_BPP(8), .bpc = 10,
> > { 512, 12, 6144, 7, 16, 15, 15, {
> > - /*
> > - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> > - * VESA DSC 1.1 Table E-5 sets it to 4.
> > - */
> > - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> > + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> > { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
> > + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
> > }
> > }
> > },
> > @@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 512, 12, 6144, 11, 20, 19, 19, {
> > { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> > { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> > - { 21, 23, -12 }
> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
> > + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
> > + { 20, 21, -12 }
> > }
> > }
> > },
> > @@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 341, 15, 2048, 3, 12, 11, 11, {
> > { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> > - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> > + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
> > + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
> > }
> > }
> > },
> > @@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 341, 15, 2048, 7, 16, 15, 15, {
> > { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> > { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> > + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
> > + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
> > }
> > }
> > },
> > @@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 341, 15, 2048, 11, 20, 19, 19, {
> > { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> > { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> > - { 21, 23, -12 }
> > + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
> > + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
> > + { 18, 19, -12 }
> > }
> > }
> > },
> > @@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { /* sentinel */ }
> > };
> >
> > -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> > +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
> > + u16 dsc_bpp,
> > u8 bits_per_component)
> > {
> > int i;
> > @@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> > * function.
> > *
> > * @vdsc_cfg: DSC Configuration data partially filled by driver
> > + * @kind: operating mode and standard to follow
> > *
> > * Return: 0 or -error code in case of an error
> > */
> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
> > {
> > + const struct rc_parameters_data *data;
> > const struct rc_parameters *rc_params;
> > int i;
> >
> > @@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> > !vdsc_cfg->bits_per_component))
> > return -EINVAL;
> >
> > - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> > + switch (kind) {
> > + case DRM_DSC_1_2_444:
> > + data = rc_parameters_1_2_444;
> > + break;
> > + case DRM_DSC_1_1_PRE_SCR:
> > + data = rc_parameters_pre_scr;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + rc_params = get_rc_params(data,
> > + vdsc_cfg->bits_per_pixel,
> > vdsc_cfg->bits_per_component);
> > if (!rc_params)
> > return -EINVAL;
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index 20a4c2f343fe..a4d1d2ba71bb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> > if (DISPLAY_VER(dev_priv) >= 13) {
> > calculate_rc_params(vdsc_cfg);
> > } else {
> > - ret = drm_dsc_setup_rc_params(vdsc_cfg);
> > + if ((compressed_bpp == 8 ||
> > + compressed_bpp == 12) &&
> > + (vdsc_cfg->bits_per_component == 8 ||
> > + vdsc_cfg->bits_per_component == 10 ||
> > + vdsc_cfg->bits_per_component == 12))
> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
> > + else
> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
> > +
> > if (ret)
> > return ret;
> >
> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> > index 1681791f65a5..c634bb2935d3 100644
> > --- a/include/drm/display/drm_dsc_helper.h
> > +++ b/include/drm/display/drm_dsc_helper.h
> > @@ -10,12 +10,17 @@
> >
> > #include <drm/display/drm_dsc.h>
> >
> > +enum drm_dsc_params_kind {
> > + DRM_DSC_1_2_444,
> > + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
> > +};
> > +
> > void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> > const struct drm_dsc_config *dsc_cfg);
> > void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
> >
> > #endif /* _DRM_DSC_HELPER_H_ */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-03-08 12:59 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-08 12:59 UTC (permalink / raw)
To: Jani Nikula
Cc: David Airlie, Daniel Vetter, Joonas Lahtinen, Rodrigo Vivi,
Tvrtko Ursulin, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, Ville Syrjälä,
dri-devel, intel-gfx, linux-arm-msm, freedreno
On Wed, 8 Mar 2023 at 12:14, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Tue, 07 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> > The array of rc_parameters contains a mixture of parameters from DSC 1.1
> > and DSC 1.2 standards. Split these tow configuration arrays in
> > preparation to adding more configuration data.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> > drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> > include/drm/display/drm_dsc_helper.h | 7 +-
> > 3 files changed, 119 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> > index acb93d4116e0..35b39f3109c4 100644
> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> > @@ -324,11 +324,81 @@ struct rc_parameters_data {
> >
> > #define DSC_BPP(bpp) ((bpp) << 4)
> >
> > +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> > + {
> > + .bpp = DSC_BPP(8), .bpc = 8,
> > + { 512, 12, 6144, 3, 12, 11, 11, {
> > + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> > + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(8), .bpc = 10,
> > + { 512, 12, 6144, 7, 16, 15, 15, {
> > + /*
> > + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> > + * VESA DSC 1.1 Table E-5 sets it to 4.
> > + */
> > + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(8), .bpc = 12,
> > + { 512, 12, 6144, 11, 20, 19, 19, {
> > + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> > + { 21, 23, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(12), .bpc = 8,
> > + { 341, 15, 2048, 3, 12, 11, 11, {
> > + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> > + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(12), .bpc = 10,
> > + { 341, 15, 2048, 7, 16, 15, 15, {
> > + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> > + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> > + }
> > + }
> > + },
> > + {
> > + .bpp = DSC_BPP(12), .bpc = 12,
> > + { 341, 15, 2048, 11, 20, 19, 19, {
> > + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> > + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> > + { 21, 23, -12 }
> > + }
> > + }
> > + },
> > + { /* sentinel */ }
> > +};
> > +
> > /*
> > * Selected Rate Control Related Parameter Recommended Values
> > * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> > */
>
> The comment is no longer accurate, is it?
Ugh, yes. it is no longer DSC 1.1. I cross-checked, the rc*cfg files
are the same between 20161212 and 20210623
>
> There are various ways to determine the parameters to use. There's even
> an application note "VESA DSC v1.2a Guidance on Deriving DSC Rate
> Control Parameters" that lists the options. They are all valid and
> should "provide visually lossless quality".
>
> Would it be simplest to always use the C model parameters in the tables
> here, referencing the zip file name with date above each table? That
> could at least be consistent, and drivers could override parameters
> using other methods if they desire. And it would be easiest to review.
Do you mean the calculated RC parameters? As I mentioned in another
email, it is at least worth investigating. I haven't looked into that,
as my primary goal (driven by the forthcoming drm/msm needs) were the
.cfg tables. I targeted cleaning up the simplest path to reduce
duplication (see [1]). Anyway, with the proposed patches we have the
API, which tells nothing about the way it fills out the RC tables.
They can be based on top of the cfg files (method 2) or calculated
(methods 3, 4).
[1] https://patchwork.freedesktop.org/patch/524051/?series=114355&rev=1
>
> I'm having a hard time finding time to review all this in a timely
> fashion. Would be good to try to get other folks to review the rest,
> it's really not very i915 specific anyway. In the mean time I think
> patches 1-5 are okay to merge via drm-misc.
For reference, the tables here are a direct conversion of the rc*cfg
files found in the DSC model. If you wish, I can post the program that
I used to convert these files into C arrays. Will that help the
review?
>
> BR,
> Jani.
>
> > -static const struct rc_parameters_data rc_parameters[] = {
> > +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> > {
> > .bpp = DSC_BPP(6), .bpc = 8,
> > { 768, 15, 6144, 3, 13, 11, 11, {
> > @@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 512, 12, 6144, 3, 12, 11, 11, {
> > { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> > - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
> > + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
> > }
> > }
> > },
> > {
> > .bpp = DSC_BPP(8), .bpc = 10,
> > { 512, 12, 6144, 7, 16, 15, 15, {
> > - /*
> > - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> > - * VESA DSC 1.1 Table E-5 sets it to 4.
> > - */
> > - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> > + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> > { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
> > + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
> > }
> > }
> > },
> > @@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 512, 12, 6144, 11, 20, 19, 19, {
> > { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> > { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> > - { 21, 23, -12 }
> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
> > + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
> > + { 20, 21, -12 }
> > }
> > }
> > },
> > @@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 341, 15, 2048, 3, 12, 11, 11, {
> > { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> > - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> > + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
> > + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
> > }
> > }
> > },
> > @@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 341, 15, 2048, 7, 16, 15, 15, {
> > { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> > { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> > + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
> > + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
> > }
> > }
> > },
> > @@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { 341, 15, 2048, 11, 20, 19, 19, {
> > { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> > { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> > - { 21, 23, -12 }
> > + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
> > + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
> > + { 18, 19, -12 }
> > }
> > }
> > },
> > @@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> > { /* sentinel */ }
> > };
> >
> > -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> > +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
> > + u16 dsc_bpp,
> > u8 bits_per_component)
> > {
> > int i;
> > @@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> > * function.
> > *
> > * @vdsc_cfg: DSC Configuration data partially filled by driver
> > + * @kind: operating mode and standard to follow
> > *
> > * Return: 0 or -error code in case of an error
> > */
> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
> > {
> > + const struct rc_parameters_data *data;
> > const struct rc_parameters *rc_params;
> > int i;
> >
> > @@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> > !vdsc_cfg->bits_per_component))
> > return -EINVAL;
> >
> > - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> > + switch (kind) {
> > + case DRM_DSC_1_2_444:
> > + data = rc_parameters_1_2_444;
> > + break;
> > + case DRM_DSC_1_1_PRE_SCR:
> > + data = rc_parameters_pre_scr;
> > + break;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + rc_params = get_rc_params(data,
> > + vdsc_cfg->bits_per_pixel,
> > vdsc_cfg->bits_per_component);
> > if (!rc_params)
> > return -EINVAL;
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index 20a4c2f343fe..a4d1d2ba71bb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> > if (DISPLAY_VER(dev_priv) >= 13) {
> > calculate_rc_params(vdsc_cfg);
> > } else {
> > - ret = drm_dsc_setup_rc_params(vdsc_cfg);
> > + if ((compressed_bpp == 8 ||
> > + compressed_bpp == 12) &&
> > + (vdsc_cfg->bits_per_component == 8 ||
> > + vdsc_cfg->bits_per_component == 10 ||
> > + vdsc_cfg->bits_per_component == 12))
> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
> > + else
> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
> > +
> > if (ret)
> > return ret;
> >
> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> > index 1681791f65a5..c634bb2935d3 100644
> > --- a/include/drm/display/drm_dsc_helper.h
> > +++ b/include/drm/display/drm_dsc_helper.h
> > @@ -10,12 +10,17 @@
> >
> > #include <drm/display/drm_dsc.h>
> >
> > +enum drm_dsc_params_kind {
> > + DRM_DSC_1_2_444,
> > + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
> > +};
> > +
> > void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> > const struct drm_dsc_config *dsc_cfg);
> > void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
> >
> > #endif /* _DRM_DSC_HELPER_H_ */
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
2023-03-08 12:59 ` [Intel-gfx] " Dmitry Baryshkov
(?)
@ 2023-03-08 13:19 ` Jani Nikula
-1 siblings, 0 replies; 47+ messages in thread
From: Jani Nikula @ 2023-03-08 13:19 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: linux-arm-msm, Tvrtko Ursulin, Sean Paul, intel-gfx,
Abhinav Kumar, dri-devel, Rodrigo Vivi, Marijn Suijten,
freedreno
On Wed, 08 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> On Wed, 8 Mar 2023 at 12:14, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>
>> On Tue, 07 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> > The array of rc_parameters contains a mixture of parameters from DSC 1.1
>> > and DSC 1.2 standards. Split these tow configuration arrays in
>> > preparation to adding more configuration data.
>> >
>> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> > ---
>> > drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
>> > drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
>> > include/drm/display/drm_dsc_helper.h | 7 +-
>> > 3 files changed, 119 insertions(+), 25 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
>> > index acb93d4116e0..35b39f3109c4 100644
>> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
>> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
>> > @@ -324,11 +324,81 @@ struct rc_parameters_data {
>> >
>> > #define DSC_BPP(bpp) ((bpp) << 4)
>> >
>> > +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
>> > + {
>> > + .bpp = DSC_BPP(8), .bpc = 8,
>> > + { 512, 12, 6144, 3, 12, 11, 11, {
>> > + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
>> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
>> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
>> > + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(8), .bpc = 10,
>> > + { 512, 12, 6144, 7, 16, 15, 15, {
>> > + /*
>> > + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
>> > + * VESA DSC 1.1 Table E-5 sets it to 4.
>> > + */
>> > + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
>> > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(8), .bpc = 12,
>> > + { 512, 12, 6144, 11, 20, 19, 19, {
>> > + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
>> > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
>> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
>> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
>> > + { 21, 23, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(12), .bpc = 8,
>> > + { 341, 15, 2048, 3, 12, 11, 11, {
>> > + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
>> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
>> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
>> > + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(12), .bpc = 10,
>> > + { 341, 15, 2048, 7, 16, 15, 15, {
>> > + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
>> > + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(12), .bpc = 12,
>> > + { 341, 15, 2048, 11, 20, 19, 19, {
>> > + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
>> > + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
>> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
>> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
>> > + { 21, 23, -12 }
>> > + }
>> > + }
>> > + },
>> > + { /* sentinel */ }
>> > +};
>> > +
>> > /*
>> > * Selected Rate Control Related Parameter Recommended Values
>> > * from DSC_v1.11 spec & C Model release: DSC_model_20161212
>> > */
>>
>> The comment is no longer accurate, is it?
>
> Ugh, yes. it is no longer DSC 1.1. I cross-checked, the rc*cfg files
> are the same between 20161212 and 20210623
>
>>
>> There are various ways to determine the parameters to use. There's even
>> an application note "VESA DSC v1.2a Guidance on Deriving DSC Rate
>> Control Parameters" that lists the options. They are all valid and
>> should "provide visually lossless quality".
>>
>> Would it be simplest to always use the C model parameters in the tables
>> here, referencing the zip file name with date above each table? That
>> could at least be consistent, and drivers could override parameters
>> using other methods if they desire. And it would be easiest to review.
>
> Do you mean the calculated RC parameters?
No, I simply mean using the values from the .cfg files, and clearly
stating that in the source. Your reply below implies this is exactly
what you're doing. What we currently have in intel_vdsc.c isn't clear by
any means.
Moreover, I started checking some of the values against the *specs* and
those actually differ from the .cfg files. I just want to get rid of the
ambiguity.
> As I mentioned in another
> email, it is at least worth investigating. I haven't looked into that,
> as my primary goal (driven by the forthcoming drm/msm needs) were the
> .cfg tables. I targeted cleaning up the simplest path to reduce
> duplication (see [1]). Anyway, with the proposed patches we have the
> API, which tells nothing about the way it fills out the RC tables.
> They can be based on top of the cfg files (method 2) or calculated
> (methods 3, 4).
>
> [1] https://patchwork.freedesktop.org/patch/524051/?series=114355&rev=1
>
>>
>> I'm having a hard time finding time to review all this in a timely
>> fashion. Would be good to try to get other folks to review the rest,
>> it's really not very i915 specific anyway. In the mean time I think
>> patches 1-5 are okay to merge via drm-misc.
>
> For reference, the tables here are a direct conversion of the rc*cfg
> files found in the DSC model. If you wish, I can post the program that
> I used to convert these files into C arrays. Will that help the
> review?
Probably; it's a bit annoying to cross check as the values aren't in the
same order.
BR,
Jani.
>
>>
>> BR,
>> Jani.
>>
>> > -static const struct rc_parameters_data rc_parameters[] = {
>> > +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
>> > {
>> > .bpp = DSC_BPP(6), .bpc = 8,
>> > { 768, 15, 6144, 3, 13, 11, 11, {
>> > @@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 512, 12, 6144, 3, 12, 11, 11, {
>> > { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
>> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
>> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
>> > - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
>> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
>> > + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
>> > }
>> > }
>> > },
>> > {
>> > .bpp = DSC_BPP(8), .bpc = 10,
>> > { 512, 12, 6144, 7, 16, 15, 15, {
>> > - /*
>> > - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
>> > - * VESA DSC 1.1 Table E-5 sets it to 4.
>> > - */
>> > - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
>> > + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
>> > { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
>> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
>> > + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
>> > }
>> > }
>> > },
>> > @@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 512, 12, 6144, 11, 20, 19, 19, {
>> > { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
>> > { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
>> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
>> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
>> > - { 21, 23, -12 }
>> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
>> > + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
>> > + { 20, 21, -12 }
>> > }
>> > }
>> > },
>> > @@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 341, 15, 2048, 3, 12, 11, 11, {
>> > { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
>> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
>> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
>> > - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
>> > + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
>> > + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
>> > }
>> > }
>> > },
>> > @@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 341, 15, 2048, 7, 16, 15, 15, {
>> > { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
>> > { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
>> > + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
>> > + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
>> > }
>> > }
>> > },
>> > @@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 341, 15, 2048, 11, 20, 19, 19, {
>> > { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
>> > { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
>> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
>> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
>> > - { 21, 23, -12 }
>> > + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
>> > + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
>> > + { 18, 19, -12 }
>> > }
>> > }
>> > },
>> > @@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { /* sentinel */ }
>> > };
>> >
>> > -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
>> > +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
>> > + u16 dsc_bpp,
>> > u8 bits_per_component)
>> > {
>> > int i;
>> > @@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
>> > * function.
>> > *
>> > * @vdsc_cfg: DSC Configuration data partially filled by driver
>> > + * @kind: operating mode and standard to follow
>> > *
>> > * Return: 0 or -error code in case of an error
>> > */
>> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
>> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
>> > {
>> > + const struct rc_parameters_data *data;
>> > const struct rc_parameters *rc_params;
>> > int i;
>> >
>> > @@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
>> > !vdsc_cfg->bits_per_component))
>> > return -EINVAL;
>> >
>> > - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
>> > + switch (kind) {
>> > + case DRM_DSC_1_2_444:
>> > + data = rc_parameters_1_2_444;
>> > + break;
>> > + case DRM_DSC_1_1_PRE_SCR:
>> > + data = rc_parameters_pre_scr;
>> > + break;
>> > + default:
>> > + return -EINVAL;
>> > + }
>> > +
>> > + rc_params = get_rc_params(data,
>> > + vdsc_cfg->bits_per_pixel,
>> > vdsc_cfg->bits_per_component);
>> > if (!rc_params)
>> > return -EINVAL;
>> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > index 20a4c2f343fe..a4d1d2ba71bb 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > @@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>> > if (DISPLAY_VER(dev_priv) >= 13) {
>> > calculate_rc_params(vdsc_cfg);
>> > } else {
>> > - ret = drm_dsc_setup_rc_params(vdsc_cfg);
>> > + if ((compressed_bpp == 8 ||
>> > + compressed_bpp == 12) &&
>> > + (vdsc_cfg->bits_per_component == 8 ||
>> > + vdsc_cfg->bits_per_component == 10 ||
>> > + vdsc_cfg->bits_per_component == 12))
>> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
>> > + else
>> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
>> > +
>> > if (ret)
>> > return ret;
>> >
>> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
>> > index 1681791f65a5..c634bb2935d3 100644
>> > --- a/include/drm/display/drm_dsc_helper.h
>> > +++ b/include/drm/display/drm_dsc_helper.h
>> > @@ -10,12 +10,17 @@
>> >
>> > #include <drm/display/drm_dsc.h>
>> >
>> > +enum drm_dsc_params_kind {
>> > + DRM_DSC_1_2_444,
>> > + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
>> > +};
>> > +
>> > void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
>> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
>> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
>> > const struct drm_dsc_config *dsc_cfg);
>> > void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
>> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
>> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
>> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>> >
>> > #endif /* _DRM_DSC_HELPER_H_ */
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-03-08 13:19 ` Jani Nikula
0 siblings, 0 replies; 47+ messages in thread
From: Jani Nikula @ 2023-03-08 13:19 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: linux-arm-msm, intel-gfx, Abhinav Kumar, dri-devel,
Daniel Vetter, Rodrigo Vivi, Marijn Suijten, freedreno,
David Airlie
On Wed, 08 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> On Wed, 8 Mar 2023 at 12:14, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>
>> On Tue, 07 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> > The array of rc_parameters contains a mixture of parameters from DSC 1.1
>> > and DSC 1.2 standards. Split these tow configuration arrays in
>> > preparation to adding more configuration data.
>> >
>> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> > ---
>> > drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
>> > drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
>> > include/drm/display/drm_dsc_helper.h | 7 +-
>> > 3 files changed, 119 insertions(+), 25 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
>> > index acb93d4116e0..35b39f3109c4 100644
>> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
>> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
>> > @@ -324,11 +324,81 @@ struct rc_parameters_data {
>> >
>> > #define DSC_BPP(bpp) ((bpp) << 4)
>> >
>> > +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
>> > + {
>> > + .bpp = DSC_BPP(8), .bpc = 8,
>> > + { 512, 12, 6144, 3, 12, 11, 11, {
>> > + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
>> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
>> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
>> > + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(8), .bpc = 10,
>> > + { 512, 12, 6144, 7, 16, 15, 15, {
>> > + /*
>> > + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
>> > + * VESA DSC 1.1 Table E-5 sets it to 4.
>> > + */
>> > + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
>> > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(8), .bpc = 12,
>> > + { 512, 12, 6144, 11, 20, 19, 19, {
>> > + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
>> > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
>> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
>> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
>> > + { 21, 23, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(12), .bpc = 8,
>> > + { 341, 15, 2048, 3, 12, 11, 11, {
>> > + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
>> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
>> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
>> > + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(12), .bpc = 10,
>> > + { 341, 15, 2048, 7, 16, 15, 15, {
>> > + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
>> > + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(12), .bpc = 12,
>> > + { 341, 15, 2048, 11, 20, 19, 19, {
>> > + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
>> > + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
>> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
>> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
>> > + { 21, 23, -12 }
>> > + }
>> > + }
>> > + },
>> > + { /* sentinel */ }
>> > +};
>> > +
>> > /*
>> > * Selected Rate Control Related Parameter Recommended Values
>> > * from DSC_v1.11 spec & C Model release: DSC_model_20161212
>> > */
>>
>> The comment is no longer accurate, is it?
>
> Ugh, yes. it is no longer DSC 1.1. I cross-checked, the rc*cfg files
> are the same between 20161212 and 20210623
>
>>
>> There are various ways to determine the parameters to use. There's even
>> an application note "VESA DSC v1.2a Guidance on Deriving DSC Rate
>> Control Parameters" that lists the options. They are all valid and
>> should "provide visually lossless quality".
>>
>> Would it be simplest to always use the C model parameters in the tables
>> here, referencing the zip file name with date above each table? That
>> could at least be consistent, and drivers could override parameters
>> using other methods if they desire. And it would be easiest to review.
>
> Do you mean the calculated RC parameters?
No, I simply mean using the values from the .cfg files, and clearly
stating that in the source. Your reply below implies this is exactly
what you're doing. What we currently have in intel_vdsc.c isn't clear by
any means.
Moreover, I started checking some of the values against the *specs* and
those actually differ from the .cfg files. I just want to get rid of the
ambiguity.
> As I mentioned in another
> email, it is at least worth investigating. I haven't looked into that,
> as my primary goal (driven by the forthcoming drm/msm needs) were the
> .cfg tables. I targeted cleaning up the simplest path to reduce
> duplication (see [1]). Anyway, with the proposed patches we have the
> API, which tells nothing about the way it fills out the RC tables.
> They can be based on top of the cfg files (method 2) or calculated
> (methods 3, 4).
>
> [1] https://patchwork.freedesktop.org/patch/524051/?series=114355&rev=1
>
>>
>> I'm having a hard time finding time to review all this in a timely
>> fashion. Would be good to try to get other folks to review the rest,
>> it's really not very i915 specific anyway. In the mean time I think
>> patches 1-5 are okay to merge via drm-misc.
>
> For reference, the tables here are a direct conversion of the rc*cfg
> files found in the DSC model. If you wish, I can post the program that
> I used to convert these files into C arrays. Will that help the
> review?
Probably; it's a bit annoying to cross check as the values aren't in the
same order.
BR,
Jani.
>
>>
>> BR,
>> Jani.
>>
>> > -static const struct rc_parameters_data rc_parameters[] = {
>> > +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
>> > {
>> > .bpp = DSC_BPP(6), .bpc = 8,
>> > { 768, 15, 6144, 3, 13, 11, 11, {
>> > @@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 512, 12, 6144, 3, 12, 11, 11, {
>> > { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
>> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
>> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
>> > - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
>> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
>> > + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
>> > }
>> > }
>> > },
>> > {
>> > .bpp = DSC_BPP(8), .bpc = 10,
>> > { 512, 12, 6144, 7, 16, 15, 15, {
>> > - /*
>> > - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
>> > - * VESA DSC 1.1 Table E-5 sets it to 4.
>> > - */
>> > - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
>> > + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
>> > { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
>> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
>> > + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
>> > }
>> > }
>> > },
>> > @@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 512, 12, 6144, 11, 20, 19, 19, {
>> > { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
>> > { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
>> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
>> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
>> > - { 21, 23, -12 }
>> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
>> > + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
>> > + { 20, 21, -12 }
>> > }
>> > }
>> > },
>> > @@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 341, 15, 2048, 3, 12, 11, 11, {
>> > { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
>> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
>> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
>> > - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
>> > + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
>> > + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
>> > }
>> > }
>> > },
>> > @@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 341, 15, 2048, 7, 16, 15, 15, {
>> > { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
>> > { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
>> > + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
>> > + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
>> > }
>> > }
>> > },
>> > @@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 341, 15, 2048, 11, 20, 19, 19, {
>> > { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
>> > { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
>> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
>> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
>> > - { 21, 23, -12 }
>> > + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
>> > + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
>> > + { 18, 19, -12 }
>> > }
>> > }
>> > },
>> > @@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { /* sentinel */ }
>> > };
>> >
>> > -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
>> > +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
>> > + u16 dsc_bpp,
>> > u8 bits_per_component)
>> > {
>> > int i;
>> > @@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
>> > * function.
>> > *
>> > * @vdsc_cfg: DSC Configuration data partially filled by driver
>> > + * @kind: operating mode and standard to follow
>> > *
>> > * Return: 0 or -error code in case of an error
>> > */
>> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
>> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
>> > {
>> > + const struct rc_parameters_data *data;
>> > const struct rc_parameters *rc_params;
>> > int i;
>> >
>> > @@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
>> > !vdsc_cfg->bits_per_component))
>> > return -EINVAL;
>> >
>> > - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
>> > + switch (kind) {
>> > + case DRM_DSC_1_2_444:
>> > + data = rc_parameters_1_2_444;
>> > + break;
>> > + case DRM_DSC_1_1_PRE_SCR:
>> > + data = rc_parameters_pre_scr;
>> > + break;
>> > + default:
>> > + return -EINVAL;
>> > + }
>> > +
>> > + rc_params = get_rc_params(data,
>> > + vdsc_cfg->bits_per_pixel,
>> > vdsc_cfg->bits_per_component);
>> > if (!rc_params)
>> > return -EINVAL;
>> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > index 20a4c2f343fe..a4d1d2ba71bb 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > @@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>> > if (DISPLAY_VER(dev_priv) >= 13) {
>> > calculate_rc_params(vdsc_cfg);
>> > } else {
>> > - ret = drm_dsc_setup_rc_params(vdsc_cfg);
>> > + if ((compressed_bpp == 8 ||
>> > + compressed_bpp == 12) &&
>> > + (vdsc_cfg->bits_per_component == 8 ||
>> > + vdsc_cfg->bits_per_component == 10 ||
>> > + vdsc_cfg->bits_per_component == 12))
>> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
>> > + else
>> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
>> > +
>> > if (ret)
>> > return ret;
>> >
>> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
>> > index 1681791f65a5..c634bb2935d3 100644
>> > --- a/include/drm/display/drm_dsc_helper.h
>> > +++ b/include/drm/display/drm_dsc_helper.h
>> > @@ -10,12 +10,17 @@
>> >
>> > #include <drm/display/drm_dsc.h>
>> >
>> > +enum drm_dsc_params_kind {
>> > + DRM_DSC_1_2_444,
>> > + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
>> > +};
>> > +
>> > void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
>> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
>> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
>> > const struct drm_dsc_config *dsc_cfg);
>> > void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
>> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
>> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
>> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>> >
>> > #endif /* _DRM_DSC_HELPER_H_ */
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-03-08 13:19 ` Jani Nikula
0 siblings, 0 replies; 47+ messages in thread
From: Jani Nikula @ 2023-03-08 13:19 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: David Airlie, Daniel Vetter, Joonas Lahtinen, Rodrigo Vivi,
Tvrtko Ursulin, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, Ville Syrjälä,
dri-devel, intel-gfx, linux-arm-msm, freedreno
On Wed, 08 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> On Wed, 8 Mar 2023 at 12:14, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>
>> On Tue, 07 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
>> > The array of rc_parameters contains a mixture of parameters from DSC 1.1
>> > and DSC 1.2 standards. Split these tow configuration arrays in
>> > preparation to adding more configuration data.
>> >
>> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> > ---
>> > drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
>> > drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
>> > include/drm/display/drm_dsc_helper.h | 7 +-
>> > 3 files changed, 119 insertions(+), 25 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
>> > index acb93d4116e0..35b39f3109c4 100644
>> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
>> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
>> > @@ -324,11 +324,81 @@ struct rc_parameters_data {
>> >
>> > #define DSC_BPP(bpp) ((bpp) << 4)
>> >
>> > +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
>> > + {
>> > + .bpp = DSC_BPP(8), .bpc = 8,
>> > + { 512, 12, 6144, 3, 12, 11, 11, {
>> > + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
>> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
>> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
>> > + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(8), .bpc = 10,
>> > + { 512, 12, 6144, 7, 16, 15, 15, {
>> > + /*
>> > + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
>> > + * VESA DSC 1.1 Table E-5 sets it to 4.
>> > + */
>> > + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
>> > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(8), .bpc = 12,
>> > + { 512, 12, 6144, 11, 20, 19, 19, {
>> > + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
>> > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
>> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
>> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
>> > + { 21, 23, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(12), .bpc = 8,
>> > + { 341, 15, 2048, 3, 12, 11, 11, {
>> > + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
>> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
>> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
>> > + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(12), .bpc = 10,
>> > + { 341, 15, 2048, 7, 16, 15, 15, {
>> > + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
>> > + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
>> > + }
>> > + }
>> > + },
>> > + {
>> > + .bpp = DSC_BPP(12), .bpc = 12,
>> > + { 341, 15, 2048, 11, 20, 19, 19, {
>> > + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
>> > + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
>> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
>> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
>> > + { 21, 23, -12 }
>> > + }
>> > + }
>> > + },
>> > + { /* sentinel */ }
>> > +};
>> > +
>> > /*
>> > * Selected Rate Control Related Parameter Recommended Values
>> > * from DSC_v1.11 spec & C Model release: DSC_model_20161212
>> > */
>>
>> The comment is no longer accurate, is it?
>
> Ugh, yes. it is no longer DSC 1.1. I cross-checked, the rc*cfg files
> are the same between 20161212 and 20210623
>
>>
>> There are various ways to determine the parameters to use. There's even
>> an application note "VESA DSC v1.2a Guidance on Deriving DSC Rate
>> Control Parameters" that lists the options. They are all valid and
>> should "provide visually lossless quality".
>>
>> Would it be simplest to always use the C model parameters in the tables
>> here, referencing the zip file name with date above each table? That
>> could at least be consistent, and drivers could override parameters
>> using other methods if they desire. And it would be easiest to review.
>
> Do you mean the calculated RC parameters?
No, I simply mean using the values from the .cfg files, and clearly
stating that in the source. Your reply below implies this is exactly
what you're doing. What we currently have in intel_vdsc.c isn't clear by
any means.
Moreover, I started checking some of the values against the *specs* and
those actually differ from the .cfg files. I just want to get rid of the
ambiguity.
> As I mentioned in another
> email, it is at least worth investigating. I haven't looked into that,
> as my primary goal (driven by the forthcoming drm/msm needs) were the
> .cfg tables. I targeted cleaning up the simplest path to reduce
> duplication (see [1]). Anyway, with the proposed patches we have the
> API, which tells nothing about the way it fills out the RC tables.
> They can be based on top of the cfg files (method 2) or calculated
> (methods 3, 4).
>
> [1] https://patchwork.freedesktop.org/patch/524051/?series=114355&rev=1
>
>>
>> I'm having a hard time finding time to review all this in a timely
>> fashion. Would be good to try to get other folks to review the rest,
>> it's really not very i915 specific anyway. In the mean time I think
>> patches 1-5 are okay to merge via drm-misc.
>
> For reference, the tables here are a direct conversion of the rc*cfg
> files found in the DSC model. If you wish, I can post the program that
> I used to convert these files into C arrays. Will that help the
> review?
Probably; it's a bit annoying to cross check as the values aren't in the
same order.
BR,
Jani.
>
>>
>> BR,
>> Jani.
>>
>> > -static const struct rc_parameters_data rc_parameters[] = {
>> > +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
>> > {
>> > .bpp = DSC_BPP(6), .bpc = 8,
>> > { 768, 15, 6144, 3, 13, 11, 11, {
>> > @@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 512, 12, 6144, 3, 12, 11, 11, {
>> > { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
>> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
>> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
>> > - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
>> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
>> > + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
>> > }
>> > }
>> > },
>> > {
>> > .bpp = DSC_BPP(8), .bpc = 10,
>> > { 512, 12, 6144, 7, 16, 15, 15, {
>> > - /*
>> > - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
>> > - * VESA DSC 1.1 Table E-5 sets it to 4.
>> > - */
>> > - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
>> > + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
>> > { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
>> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
>> > + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
>> > }
>> > }
>> > },
>> > @@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 512, 12, 6144, 11, 20, 19, 19, {
>> > { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
>> > { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
>> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
>> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
>> > - { 21, 23, -12 }
>> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
>> > + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
>> > + { 20, 21, -12 }
>> > }
>> > }
>> > },
>> > @@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 341, 15, 2048, 3, 12, 11, 11, {
>> > { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
>> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
>> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
>> > - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
>> > + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
>> > + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
>> > }
>> > }
>> > },
>> > @@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 341, 15, 2048, 7, 16, 15, 15, {
>> > { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
>> > { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
>> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
>> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
>> > + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
>> > + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
>> > }
>> > }
>> > },
>> > @@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { 341, 15, 2048, 11, 20, 19, 19, {
>> > { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
>> > { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
>> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
>> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
>> > - { 21, 23, -12 }
>> > + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
>> > + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
>> > + { 18, 19, -12 }
>> > }
>> > }
>> > },
>> > @@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
>> > { /* sentinel */ }
>> > };
>> >
>> > -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
>> > +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
>> > + u16 dsc_bpp,
>> > u8 bits_per_component)
>> > {
>> > int i;
>> > @@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
>> > * function.
>> > *
>> > * @vdsc_cfg: DSC Configuration data partially filled by driver
>> > + * @kind: operating mode and standard to follow
>> > *
>> > * Return: 0 or -error code in case of an error
>> > */
>> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
>> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
>> > {
>> > + const struct rc_parameters_data *data;
>> > const struct rc_parameters *rc_params;
>> > int i;
>> >
>> > @@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
>> > !vdsc_cfg->bits_per_component))
>> > return -EINVAL;
>> >
>> > - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
>> > + switch (kind) {
>> > + case DRM_DSC_1_2_444:
>> > + data = rc_parameters_1_2_444;
>> > + break;
>> > + case DRM_DSC_1_1_PRE_SCR:
>> > + data = rc_parameters_pre_scr;
>> > + break;
>> > + default:
>> > + return -EINVAL;
>> > + }
>> > +
>> > + rc_params = get_rc_params(data,
>> > + vdsc_cfg->bits_per_pixel,
>> > vdsc_cfg->bits_per_component);
>> > if (!rc_params)
>> > return -EINVAL;
>> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > index 20a4c2f343fe..a4d1d2ba71bb 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> > @@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
>> > if (DISPLAY_VER(dev_priv) >= 13) {
>> > calculate_rc_params(vdsc_cfg);
>> > } else {
>> > - ret = drm_dsc_setup_rc_params(vdsc_cfg);
>> > + if ((compressed_bpp == 8 ||
>> > + compressed_bpp == 12) &&
>> > + (vdsc_cfg->bits_per_component == 8 ||
>> > + vdsc_cfg->bits_per_component == 10 ||
>> > + vdsc_cfg->bits_per_component == 12))
>> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
>> > + else
>> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
>> > +
>> > if (ret)
>> > return ret;
>> >
>> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
>> > index 1681791f65a5..c634bb2935d3 100644
>> > --- a/include/drm/display/drm_dsc_helper.h
>> > +++ b/include/drm/display/drm_dsc_helper.h
>> > @@ -10,12 +10,17 @@
>> >
>> > #include <drm/display/drm_dsc.h>
>> >
>> > +enum drm_dsc_params_kind {
>> > + DRM_DSC_1_2_444,
>> > + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
>> > +};
>> > +
>> > void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
>> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
>> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
>> > const struct drm_dsc_config *dsc_cfg);
>> > void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
>> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
>> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
>> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
>> >
>> > #endif /* _DRM_DSC_HELPER_H_ */
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
2023-03-08 13:19 ` [Intel-gfx] " Jani Nikula
(?)
@ 2023-03-08 16:50 ` Dmitry Baryshkov
-1 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-08 16:50 UTC (permalink / raw)
To: Jani Nikula
Cc: David Airlie, Daniel Vetter, Joonas Lahtinen, Rodrigo Vivi,
Tvrtko Ursulin, Rob Clark, Abhinav Kumar, Sean Paul,
Marijn Suijten, Ville Syrjälä,
dri-devel, intel-gfx, linux-arm-msm, freedreno
On Wed, 8 Mar 2023 at 15:19, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Wed, 08 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> > On Wed, 8 Mar 2023 at 12:14, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> >>
> >> On Tue, 07 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> >> > The array of rc_parameters contains a mixture of parameters from DSC 1.1
> >> > and DSC 1.2 standards. Split these tow configuration arrays in
> >> > preparation to adding more configuration data.
> >> >
> >> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >> > ---
> >> > drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
> >> > drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> >> > include/drm/display/drm_dsc_helper.h | 7 +-
> >> > 3 files changed, 119 insertions(+), 25 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> >> > index acb93d4116e0..35b39f3109c4 100644
> >> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> >> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> >> > @@ -324,11 +324,81 @@ struct rc_parameters_data {
> >> >
> >> > #define DSC_BPP(bpp) ((bpp) << 4)
> >> >
> >> > +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> >> > + {
> >> > + .bpp = DSC_BPP(8), .bpc = 8,
> >> > + { 512, 12, 6144, 3, 12, 11, 11, {
> >> > + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> >> > + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(8), .bpc = 10,
> >> > + { 512, 12, 6144, 7, 16, 15, 15, {
> >> > + /*
> >> > + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> >> > + * VESA DSC 1.1 Table E-5 sets it to 4.
> >> > + */
> >> > + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> >> > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(8), .bpc = 12,
> >> > + { 512, 12, 6144, 11, 20, 19, 19, {
> >> > + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> >> > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >> > + { 21, 23, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(12), .bpc = 8,
> >> > + { 341, 15, 2048, 3, 12, 11, 11, {
> >> > + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> >> > + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(12), .bpc = 10,
> >> > + { 341, 15, 2048, 7, 16, 15, 15, {
> >> > + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> >> > + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(12), .bpc = 12,
> >> > + { 341, 15, 2048, 11, 20, 19, 19, {
> >> > + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> >> > + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >> > + { 21, 23, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + { /* sentinel */ }
> >> > +};
> >> > +
> >> > /*
> >> > * Selected Rate Control Related Parameter Recommended Values
> >> > * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> >> > */
> >>
> >> The comment is no longer accurate, is it?
> >
> > Ugh, yes. it is no longer DSC 1.1. I cross-checked, the rc*cfg files
> > are the same between 20161212 and 20210623
> >
> >>
> >> There are various ways to determine the parameters to use. There's even
> >> an application note "VESA DSC v1.2a Guidance on Deriving DSC Rate
> >> Control Parameters" that lists the options. They are all valid and
> >> should "provide visually lossless quality".
> >>
> >> Would it be simplest to always use the C model parameters in the tables
> >> here, referencing the zip file name with date above each table? That
> >> could at least be consistent, and drivers could override parameters
> >> using other methods if they desire. And it would be easiest to review.
> >
> > Do you mean the calculated RC parameters?
>
> No, I simply mean using the values from the .cfg files, and clearly
> stating that in the source. Your reply below implies this is exactly
> what you're doing. What we currently have in intel_vdsc.c isn't clear by
> any means.
Yes, it took me a while to narrow down which entries correspond to
'legacy'/pre-SCR configs.
>
> Moreover, I started checking some of the values against the *specs* and
> those actually differ from the .cfg files. I just want to get rid of the
> ambiguity.
Ugh.
>
> > As I mentioned in another
> > email, it is at least worth investigating. I haven't looked into that,
> > as my primary goal (driven by the forthcoming drm/msm needs) were the
> > .cfg tables. I targeted cleaning up the simplest path to reduce
> > duplication (see [1]). Anyway, with the proposed patches we have the
> > API, which tells nothing about the way it fills out the RC tables.
> > They can be based on top of the cfg files (method 2) or calculated
> > (methods 3, 4).
> >
> > [1] https://patchwork.freedesktop.org/patch/524051/?series=114355&rev=1
> >
> >>
> >> I'm having a hard time finding time to review all this in a timely
> >> fashion. Would be good to try to get other folks to review the rest,
> >> it's really not very i915 specific anyway. In the mean time I think
> >> patches 1-5 are okay to merge via drm-misc.
> >
> > For reference, the tables here are a direct conversion of the rc*cfg
> > files found in the DSC model. If you wish, I can post the program that
> > I used to convert these files into C arrays. Will that help the
> > review?
>
> Probably; it's a bit annoying to cross check as the values aren't in the
> same order.
I pushed my code to
https://git.linaro.org/people/dmitry.baryshkov/dsc_model_process.git/
>
> BR,
> Jani.
>
>
> >
> >>
> >> BR,
> >> Jani.
> >>
> >> > -static const struct rc_parameters_data rc_parameters[] = {
> >> > +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> >> > {
> >> > .bpp = DSC_BPP(6), .bpc = 8,
> >> > { 768, 15, 6144, 3, 13, 11, 11, {
> >> > @@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 512, 12, 6144, 3, 12, 11, 11, {
> >> > { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> >> > - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
> >> > + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
> >> > }
> >> > }
> >> > },
> >> > {
> >> > .bpp = DSC_BPP(8), .bpc = 10,
> >> > { 512, 12, 6144, 7, 16, 15, 15, {
> >> > - /*
> >> > - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> >> > - * VESA DSC 1.1 Table E-5 sets it to 4.
> >> > - */
> >> > - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> >> > + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> >> > { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
> >> > + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 512, 12, 6144, 11, 20, 19, 19, {
> >> > { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> >> > { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >> > - { 21, 23, -12 }
> >> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
> >> > + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
> >> > + { 20, 21, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 341, 15, 2048, 3, 12, 11, 11, {
> >> > { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> >> > - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >> > + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
> >> > + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 341, 15, 2048, 7, 16, 15, 15, {
> >> > { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> >> > { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >> > + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
> >> > + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 341, 15, 2048, 11, 20, 19, 19, {
> >> > { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> >> > { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >> > - { 21, 23, -12 }
> >> > + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
> >> > + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
> >> > + { 18, 19, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { /* sentinel */ }
> >> > };
> >> >
> >> > -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> >> > +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
> >> > + u16 dsc_bpp,
> >> > u8 bits_per_component)
> >> > {
> >> > int i;
> >> > @@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> >> > * function.
> >> > *
> >> > * @vdsc_cfg: DSC Configuration data partially filled by driver
> >> > + * @kind: operating mode and standard to follow
> >> > *
> >> > * Return: 0 or -error code in case of an error
> >> > */
> >> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> >> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
> >> > {
> >> > + const struct rc_parameters_data *data;
> >> > const struct rc_parameters *rc_params;
> >> > int i;
> >> >
> >> > @@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> >> > !vdsc_cfg->bits_per_component))
> >> > return -EINVAL;
> >> >
> >> > - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> >> > + switch (kind) {
> >> > + case DRM_DSC_1_2_444:
> >> > + data = rc_parameters_1_2_444;
> >> > + break;
> >> > + case DRM_DSC_1_1_PRE_SCR:
> >> > + data = rc_parameters_pre_scr;
> >> > + break;
> >> > + default:
> >> > + return -EINVAL;
> >> > + }
> >> > +
> >> > + rc_params = get_rc_params(data,
> >> > + vdsc_cfg->bits_per_pixel,
> >> > vdsc_cfg->bits_per_component);
> >> > if (!rc_params)
> >> > return -EINVAL;
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > index 20a4c2f343fe..a4d1d2ba71bb 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > @@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> >> > if (DISPLAY_VER(dev_priv) >= 13) {
> >> > calculate_rc_params(vdsc_cfg);
> >> > } else {
> >> > - ret = drm_dsc_setup_rc_params(vdsc_cfg);
> >> > + if ((compressed_bpp == 8 ||
> >> > + compressed_bpp == 12) &&
> >> > + (vdsc_cfg->bits_per_component == 8 ||
> >> > + vdsc_cfg->bits_per_component == 10 ||
> >> > + vdsc_cfg->bits_per_component == 12))
> >> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
> >> > + else
> >> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
> >> > +
> >> > if (ret)
> >> > return ret;
> >> >
> >> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> >> > index 1681791f65a5..c634bb2935d3 100644
> >> > --- a/include/drm/display/drm_dsc_helper.h
> >> > +++ b/include/drm/display/drm_dsc_helper.h
> >> > @@ -10,12 +10,17 @@
> >> >
> >> > #include <drm/display/drm_dsc.h>
> >> >
> >> > +enum drm_dsc_params_kind {
> >> > + DRM_DSC_1_2_444,
> >> > + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
> >> > +};
> >> > +
> >> > void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> >> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> >> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> >> > const struct drm_dsc_config *dsc_cfg);
> >> > void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> >> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> >> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
> >> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
> >> >
> >> > #endif /* _DRM_DSC_HELPER_H_ */
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-03-08 16:50 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-08 16:50 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-arm-msm, Tvrtko Ursulin, Sean Paul, intel-gfx,
Abhinav Kumar, dri-devel, Rodrigo Vivi, Marijn Suijten,
freedreno
On Wed, 8 Mar 2023 at 15:19, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Wed, 08 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> > On Wed, 8 Mar 2023 at 12:14, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> >>
> >> On Tue, 07 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> >> > The array of rc_parameters contains a mixture of parameters from DSC 1.1
> >> > and DSC 1.2 standards. Split these tow configuration arrays in
> >> > preparation to adding more configuration data.
> >> >
> >> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >> > ---
> >> > drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
> >> > drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> >> > include/drm/display/drm_dsc_helper.h | 7 +-
> >> > 3 files changed, 119 insertions(+), 25 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> >> > index acb93d4116e0..35b39f3109c4 100644
> >> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> >> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> >> > @@ -324,11 +324,81 @@ struct rc_parameters_data {
> >> >
> >> > #define DSC_BPP(bpp) ((bpp) << 4)
> >> >
> >> > +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> >> > + {
> >> > + .bpp = DSC_BPP(8), .bpc = 8,
> >> > + { 512, 12, 6144, 3, 12, 11, 11, {
> >> > + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> >> > + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(8), .bpc = 10,
> >> > + { 512, 12, 6144, 7, 16, 15, 15, {
> >> > + /*
> >> > + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> >> > + * VESA DSC 1.1 Table E-5 sets it to 4.
> >> > + */
> >> > + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> >> > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(8), .bpc = 12,
> >> > + { 512, 12, 6144, 11, 20, 19, 19, {
> >> > + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> >> > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >> > + { 21, 23, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(12), .bpc = 8,
> >> > + { 341, 15, 2048, 3, 12, 11, 11, {
> >> > + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> >> > + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(12), .bpc = 10,
> >> > + { 341, 15, 2048, 7, 16, 15, 15, {
> >> > + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> >> > + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(12), .bpc = 12,
> >> > + { 341, 15, 2048, 11, 20, 19, 19, {
> >> > + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> >> > + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >> > + { 21, 23, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + { /* sentinel */ }
> >> > +};
> >> > +
> >> > /*
> >> > * Selected Rate Control Related Parameter Recommended Values
> >> > * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> >> > */
> >>
> >> The comment is no longer accurate, is it?
> >
> > Ugh, yes. it is no longer DSC 1.1. I cross-checked, the rc*cfg files
> > are the same between 20161212 and 20210623
> >
> >>
> >> There are various ways to determine the parameters to use. There's even
> >> an application note "VESA DSC v1.2a Guidance on Deriving DSC Rate
> >> Control Parameters" that lists the options. They are all valid and
> >> should "provide visually lossless quality".
> >>
> >> Would it be simplest to always use the C model parameters in the tables
> >> here, referencing the zip file name with date above each table? That
> >> could at least be consistent, and drivers could override parameters
> >> using other methods if they desire. And it would be easiest to review.
> >
> > Do you mean the calculated RC parameters?
>
> No, I simply mean using the values from the .cfg files, and clearly
> stating that in the source. Your reply below implies this is exactly
> what you're doing. What we currently have in intel_vdsc.c isn't clear by
> any means.
Yes, it took me a while to narrow down which entries correspond to
'legacy'/pre-SCR configs.
>
> Moreover, I started checking some of the values against the *specs* and
> those actually differ from the .cfg files. I just want to get rid of the
> ambiguity.
Ugh.
>
> > As I mentioned in another
> > email, it is at least worth investigating. I haven't looked into that,
> > as my primary goal (driven by the forthcoming drm/msm needs) were the
> > .cfg tables. I targeted cleaning up the simplest path to reduce
> > duplication (see [1]). Anyway, with the proposed patches we have the
> > API, which tells nothing about the way it fills out the RC tables.
> > They can be based on top of the cfg files (method 2) or calculated
> > (methods 3, 4).
> >
> > [1] https://patchwork.freedesktop.org/patch/524051/?series=114355&rev=1
> >
> >>
> >> I'm having a hard time finding time to review all this in a timely
> >> fashion. Would be good to try to get other folks to review the rest,
> >> it's really not very i915 specific anyway. In the mean time I think
> >> patches 1-5 are okay to merge via drm-misc.
> >
> > For reference, the tables here are a direct conversion of the rc*cfg
> > files found in the DSC model. If you wish, I can post the program that
> > I used to convert these files into C arrays. Will that help the
> > review?
>
> Probably; it's a bit annoying to cross check as the values aren't in the
> same order.
I pushed my code to
https://git.linaro.org/people/dmitry.baryshkov/dsc_model_process.git/
>
> BR,
> Jani.
>
>
> >
> >>
> >> BR,
> >> Jani.
> >>
> >> > -static const struct rc_parameters_data rc_parameters[] = {
> >> > +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> >> > {
> >> > .bpp = DSC_BPP(6), .bpc = 8,
> >> > { 768, 15, 6144, 3, 13, 11, 11, {
> >> > @@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 512, 12, 6144, 3, 12, 11, 11, {
> >> > { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> >> > - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
> >> > + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
> >> > }
> >> > }
> >> > },
> >> > {
> >> > .bpp = DSC_BPP(8), .bpc = 10,
> >> > { 512, 12, 6144, 7, 16, 15, 15, {
> >> > - /*
> >> > - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> >> > - * VESA DSC 1.1 Table E-5 sets it to 4.
> >> > - */
> >> > - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> >> > + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> >> > { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
> >> > + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 512, 12, 6144, 11, 20, 19, 19, {
> >> > { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> >> > { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >> > - { 21, 23, -12 }
> >> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
> >> > + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
> >> > + { 20, 21, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 341, 15, 2048, 3, 12, 11, 11, {
> >> > { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> >> > - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >> > + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
> >> > + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 341, 15, 2048, 7, 16, 15, 15, {
> >> > { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> >> > { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >> > + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
> >> > + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 341, 15, 2048, 11, 20, 19, 19, {
> >> > { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> >> > { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >> > - { 21, 23, -12 }
> >> > + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
> >> > + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
> >> > + { 18, 19, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { /* sentinel */ }
> >> > };
> >> >
> >> > -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> >> > +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
> >> > + u16 dsc_bpp,
> >> > u8 bits_per_component)
> >> > {
> >> > int i;
> >> > @@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> >> > * function.
> >> > *
> >> > * @vdsc_cfg: DSC Configuration data partially filled by driver
> >> > + * @kind: operating mode and standard to follow
> >> > *
> >> > * Return: 0 or -error code in case of an error
> >> > */
> >> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> >> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
> >> > {
> >> > + const struct rc_parameters_data *data;
> >> > const struct rc_parameters *rc_params;
> >> > int i;
> >> >
> >> > @@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> >> > !vdsc_cfg->bits_per_component))
> >> > return -EINVAL;
> >> >
> >> > - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> >> > + switch (kind) {
> >> > + case DRM_DSC_1_2_444:
> >> > + data = rc_parameters_1_2_444;
> >> > + break;
> >> > + case DRM_DSC_1_1_PRE_SCR:
> >> > + data = rc_parameters_pre_scr;
> >> > + break;
> >> > + default:
> >> > + return -EINVAL;
> >> > + }
> >> > +
> >> > + rc_params = get_rc_params(data,
> >> > + vdsc_cfg->bits_per_pixel,
> >> > vdsc_cfg->bits_per_component);
> >> > if (!rc_params)
> >> > return -EINVAL;
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > index 20a4c2f343fe..a4d1d2ba71bb 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > @@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> >> > if (DISPLAY_VER(dev_priv) >= 13) {
> >> > calculate_rc_params(vdsc_cfg);
> >> > } else {
> >> > - ret = drm_dsc_setup_rc_params(vdsc_cfg);
> >> > + if ((compressed_bpp == 8 ||
> >> > + compressed_bpp == 12) &&
> >> > + (vdsc_cfg->bits_per_component == 8 ||
> >> > + vdsc_cfg->bits_per_component == 10 ||
> >> > + vdsc_cfg->bits_per_component == 12))
> >> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
> >> > + else
> >> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
> >> > +
> >> > if (ret)
> >> > return ret;
> >> >
> >> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> >> > index 1681791f65a5..c634bb2935d3 100644
> >> > --- a/include/drm/display/drm_dsc_helper.h
> >> > +++ b/include/drm/display/drm_dsc_helper.h
> >> > @@ -10,12 +10,17 @@
> >> >
> >> > #include <drm/display/drm_dsc.h>
> >> >
> >> > +enum drm_dsc_params_kind {
> >> > + DRM_DSC_1_2_444,
> >> > + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
> >> > +};
> >> > +
> >> > void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> >> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> >> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> >> > const struct drm_dsc_config *dsc_cfg);
> >> > void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> >> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> >> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
> >> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
> >> >
> >> > #endif /* _DRM_DSC_HELPER_H_ */
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [Intel-gfx] [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters
@ 2023-03-08 16:50 ` Dmitry Baryshkov
0 siblings, 0 replies; 47+ messages in thread
From: Dmitry Baryshkov @ 2023-03-08 16:50 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-arm-msm, intel-gfx, Abhinav Kumar, dri-devel,
Daniel Vetter, Rodrigo Vivi, Marijn Suijten, freedreno,
David Airlie
On Wed, 8 Mar 2023 at 15:19, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Wed, 08 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> > On Wed, 8 Mar 2023 at 12:14, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> >>
> >> On Tue, 07 Mar 2023, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> >> > The array of rc_parameters contains a mixture of parameters from DSC 1.1
> >> > and DSC 1.2 standards. Split these tow configuration arrays in
> >> > preparation to adding more configuration data.
> >> >
> >> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >> > ---
> >> > drivers/gpu/drm/display/drm_dsc_helper.c | 127 ++++++++++++++++++----
> >> > drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +-
> >> > include/drm/display/drm_dsc_helper.h | 7 +-
> >> > 3 files changed, 119 insertions(+), 25 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c
> >> > index acb93d4116e0..35b39f3109c4 100644
> >> > --- a/drivers/gpu/drm/display/drm_dsc_helper.c
> >> > +++ b/drivers/gpu/drm/display/drm_dsc_helper.c
> >> > @@ -324,11 +324,81 @@ struct rc_parameters_data {
> >> >
> >> > #define DSC_BPP(bpp) ((bpp) << 4)
> >> >
> >> > +static const struct rc_parameters_data rc_parameters_pre_scr[] = {
> >> > + {
> >> > + .bpp = DSC_BPP(8), .bpc = 8,
> >> > + { 512, 12, 6144, 3, 12, 11, 11, {
> >> > + { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> >> > + { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(8), .bpc = 10,
> >> > + { 512, 12, 6144, 7, 16, 15, 15, {
> >> > + /*
> >> > + * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> >> > + * VESA DSC 1.1 Table E-5 sets it to 4.
> >> > + */
> >> > + { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> >> > + { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(8), .bpc = 12,
> >> > + { 512, 12, 6144, 11, 20, 19, 19, {
> >> > + { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> >> > + { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >> > + { 21, 23, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(12), .bpc = 8,
> >> > + { 341, 15, 2048, 3, 12, 11, 11, {
> >> > + { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >> > + { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> >> > + { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(12), .bpc = 10,
> >> > + { 341, 15, 2048, 7, 16, 15, 15, {
> >> > + { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> >> > + { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >> > + { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + {
> >> > + .bpp = DSC_BPP(12), .bpc = 12,
> >> > + { 341, 15, 2048, 11, 20, 19, 19, {
> >> > + { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> >> > + { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >> > + { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >> > + { 21, 23, -12 }
> >> > + }
> >> > + }
> >> > + },
> >> > + { /* sentinel */ }
> >> > +};
> >> > +
> >> > /*
> >> > * Selected Rate Control Related Parameter Recommended Values
> >> > * from DSC_v1.11 spec & C Model release: DSC_model_20161212
> >> > */
> >>
> >> The comment is no longer accurate, is it?
> >
> > Ugh, yes. it is no longer DSC 1.1. I cross-checked, the rc*cfg files
> > are the same between 20161212 and 20210623
> >
> >>
> >> There are various ways to determine the parameters to use. There's even
> >> an application note "VESA DSC v1.2a Guidance on Deriving DSC Rate
> >> Control Parameters" that lists the options. They are all valid and
> >> should "provide visually lossless quality".
> >>
> >> Would it be simplest to always use the C model parameters in the tables
> >> here, referencing the zip file name with date above each table? That
> >> could at least be consistent, and drivers could override parameters
> >> using other methods if they desire. And it would be easiest to review.
> >
> > Do you mean the calculated RC parameters?
>
> No, I simply mean using the values from the .cfg files, and clearly
> stating that in the source. Your reply below implies this is exactly
> what you're doing. What we currently have in intel_vdsc.c isn't clear by
> any means.
Yes, it took me a while to narrow down which entries correspond to
'legacy'/pre-SCR configs.
>
> Moreover, I started checking some of the values against the *specs* and
> those actually differ from the .cfg files. I just want to get rid of the
> ambiguity.
Ugh.
>
> > As I mentioned in another
> > email, it is at least worth investigating. I haven't looked into that,
> > as my primary goal (driven by the forthcoming drm/msm needs) were the
> > .cfg tables. I targeted cleaning up the simplest path to reduce
> > duplication (see [1]). Anyway, with the proposed patches we have the
> > API, which tells nothing about the way it fills out the RC tables.
> > They can be based on top of the cfg files (method 2) or calculated
> > (methods 3, 4).
> >
> > [1] https://patchwork.freedesktop.org/patch/524051/?series=114355&rev=1
> >
> >>
> >> I'm having a hard time finding time to review all this in a timely
> >> fashion. Would be good to try to get other folks to review the rest,
> >> it's really not very i915 specific anyway. In the mean time I think
> >> patches 1-5 are okay to merge via drm-misc.
> >
> > For reference, the tables here are a direct conversion of the rc*cfg
> > files found in the DSC model. If you wish, I can post the program that
> > I used to convert these files into C arrays. Will that help the
> > review?
>
> Probably; it's a bit annoying to cross check as the values aren't in the
> same order.
I pushed my code to
https://git.linaro.org/people/dmitry.baryshkov/dsc_model_process.git/
>
> BR,
> Jani.
>
>
> >
> >>
> >> BR,
> >> Jani.
> >>
> >> > -static const struct rc_parameters_data rc_parameters[] = {
> >> > +static const struct rc_parameters_data rc_parameters_1_2_444[] = {
> >> > {
> >> > .bpp = DSC_BPP(6), .bpc = 8,
> >> > { 768, 15, 6144, 3, 13, 11, 11, {
> >> > @@ -388,22 +458,18 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 512, 12, 6144, 3, 12, 11, 11, {
> >> > { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 }, { 5, 12, -12 },
> >> > - { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >> > + { 3, 9, -8 }, { 3, 10, -10 }, { 5, 10, -10 }, { 5, 11, -12 },
> >> > + { 5, 11, -12 }, { 9, 12, -12 }, { 12, 13, -12 }
> >> > }
> >> > }
> >> > },
> >> > {
> >> > .bpp = DSC_BPP(8), .bpc = 10,
> >> > { 512, 12, 6144, 7, 16, 15, 15, {
> >> > - /*
> >> > - * DSC model/pre-SCR-cfg has 8 for range_max_qp[0], however
> >> > - * VESA DSC 1.1 Table E-5 sets it to 4.
> >> > - */
> >> > - { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> >> > + { 0, 8, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, -2 },
> >> > { 7, 11, -4 }, { 7, 11, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >> > + { 7, 13, -8 }, { 7, 14, -10 }, { 9, 14, -10 }, { 9, 15, -12 },
> >> > + { 9, 15, -12 }, { 13, 16, -12 }, { 16, 17, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -412,9 +478,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 512, 12, 6144, 11, 20, 19, 19, {
> >> > { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 }, { 9, 14, -2 },
> >> > { 11, 15, -4 }, { 11, 15, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >> > - { 21, 23, -12 }
> >> > + { 11, 17, -8 }, { 11, 18, -10 }, { 13, 18, -10 },
> >> > + { 13, 19, -12 }, { 13, 19, -12 }, { 17, 20, -12 },
> >> > + { 20, 21, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -498,8 +564,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 341, 15, 2048, 3, 12, 11, 11, {
> >> > { 0, 2, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, -2 },
> >> > { 3, 7, -4 }, { 3, 7, -6 }, { 3, 7, -8 }, { 3, 8, -8 },
> >> > - { 3, 9, -8 }, { 3, 10, -10 }, { 5, 11, -10 },
> >> > - { 5, 12, -12 }, { 5, 13, -12 }, { 7, 13, -12 }, { 13, 15, -12 }
> >> > + { 3, 8, -8 }, { 3, 9, -10 }, { 5, 9, -10 }, { 5, 9, -12 },
> >> > + { 5, 9, -12 }, { 7, 10, -12 }, { 10, 11, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -508,8 +574,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 341, 15, 2048, 7, 16, 15, 15, {
> >> > { 0, 2, 2 }, { 2, 5, 0 }, { 3, 7, 0 }, { 4, 8, -2 },
> >> > { 6, 9, -4 }, { 7, 10, -6 }, { 7, 11, -8 }, { 7, 12, -8 },
> >> > - { 7, 13, -8 }, { 7, 14, -10 }, { 9, 15, -10 }, { 9, 16, -12 },
> >> > - { 9, 17, -12 }, { 11, 17, -12 }, { 17, 19, -12 }
> >> > + { 7, 12, -8 }, { 7, 13, -10 }, { 9, 13, -10 }, { 9, 13, -12 },
> >> > + { 9, 13, -12 }, { 11, 14, -12 }, { 14, 15, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -518,9 +584,9 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { 341, 15, 2048, 11, 20, 19, 19, {
> >> > { 0, 6, 2 }, { 4, 9, 0 }, { 7, 11, 0 }, { 8, 12, -2 },
> >> > { 10, 13, -4 }, { 11, 14, -6 }, { 11, 15, -8 }, { 11, 16, -8 },
> >> > - { 11, 17, -8 }, { 11, 18, -10 }, { 13, 19, -10 },
> >> > - { 13, 20, -12 }, { 13, 21, -12 }, { 15, 21, -12 },
> >> > - { 21, 23, -12 }
> >> > + { 11, 16, -8 }, { 11, 17, -10 }, { 13, 17, -10 },
> >> > + { 13, 17, -12 }, { 13, 17, -12 }, { 15, 18, -12 },
> >> > + { 18, 19, -12 }
> >> > }
> >> > }
> >> > },
> >> > @@ -602,7 +668,8 @@ static const struct rc_parameters_data rc_parameters[] = {
> >> > { /* sentinel */ }
> >> > };
> >> >
> >> > -static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> >> > +static const struct rc_parameters *get_rc_params(const struct rc_parameters_data *rc_parameters,
> >> > + u16 dsc_bpp,
> >> > u8 bits_per_component)
> >> > {
> >> > int i;
> >> > @@ -622,11 +689,13 @@ static const struct rc_parameters *get_rc_params(u16 dsc_bpp,
> >> > * function.
> >> > *
> >> > * @vdsc_cfg: DSC Configuration data partially filled by driver
> >> > + * @kind: operating mode and standard to follow
> >> > *
> >> > * Return: 0 or -error code in case of an error
> >> > */
> >> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> >> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind)
> >> > {
> >> > + const struct rc_parameters_data *data;
> >> > const struct rc_parameters *rc_params;
> >> > int i;
> >> >
> >> > @@ -634,7 +703,19 @@ int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg)
> >> > !vdsc_cfg->bits_per_component))
> >> > return -EINVAL;
> >> >
> >> > - rc_params = get_rc_params(vdsc_cfg->bits_per_pixel,
> >> > + switch (kind) {
> >> > + case DRM_DSC_1_2_444:
> >> > + data = rc_parameters_1_2_444;
> >> > + break;
> >> > + case DRM_DSC_1_1_PRE_SCR:
> >> > + data = rc_parameters_pre_scr;
> >> > + break;
> >> > + default:
> >> > + return -EINVAL;
> >> > + }
> >> > +
> >> > + rc_params = get_rc_params(data,
> >> > + vdsc_cfg->bits_per_pixel,
> >> > vdsc_cfg->bits_per_component);
> >> > if (!rc_params)
> >> > return -EINVAL;
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > index 20a4c2f343fe..a4d1d2ba71bb 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> >> > @@ -157,7 +157,15 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
> >> > if (DISPLAY_VER(dev_priv) >= 13) {
> >> > calculate_rc_params(vdsc_cfg);
> >> > } else {
> >> > - ret = drm_dsc_setup_rc_params(vdsc_cfg);
> >> > + if ((compressed_bpp == 8 ||
> >> > + compressed_bpp == 12) &&
> >> > + (vdsc_cfg->bits_per_component == 8 ||
> >> > + vdsc_cfg->bits_per_component == 10 ||
> >> > + vdsc_cfg->bits_per_component == 12))
> >> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
> >> > + else
> >> > + ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
> >> > +
> >> > if (ret)
> >> > return ret;
> >> >
> >> > diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h
> >> > index 1681791f65a5..c634bb2935d3 100644
> >> > --- a/include/drm/display/drm_dsc_helper.h
> >> > +++ b/include/drm/display/drm_dsc_helper.h
> >> > @@ -10,12 +10,17 @@
> >> >
> >> > #include <drm/display/drm_dsc.h>
> >> >
> >> > +enum drm_dsc_params_kind {
> >> > + DRM_DSC_1_2_444,
> >> > + DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
> >> > +};
> >> > +
> >> > void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header);
> >> > int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size);
> >> > void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp,
> >> > const struct drm_dsc_config *dsc_cfg);
> >> > void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg);
> >> > -int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg);
> >> > +int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind);
> >> > int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg);
> >> >
> >> > #endif /* _DRM_DSC_HELPER_H_ */
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: move DSC RC tables to drm_dsc_helper.c (rev2)
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
` (11 preceding siblings ...)
(?)
@ 2023-03-14 8:45 ` Patchwork
-1 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2023-03-14 8:45 UTC (permalink / raw)
To: Dmitry Baryshkov; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: move DSC RC tables to drm_dsc_helper.c (rev2)
URL : https://patchwork.freedesktop.org/series/114473/
State : failure
== Summary ==
Error: patch https://patchwork.freedesktop.org/api/1.0/series/114473/revisions/2/mbox/ not applied
Applying: drm/i915/dsc: change DSC param tables to follow the DSC model
Applying: drm/i915/dsc: move rc_buf_thresh values to common helper
Applying: drm/i915/dsc: move DSC tables to DRM DSC helper
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_vdsc.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0003 drm/i915/dsc: move DSC tables to DRM DSC helper
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
^ permalink raw reply [flat|nested] 47+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: move DSC RC tables to drm_dsc_helper.c (rev3)
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
` (12 preceding siblings ...)
(?)
@ 2023-03-28 23:22 ` Patchwork
-1 siblings, 0 replies; 47+ messages in thread
From: Patchwork @ 2023-03-28 23:22 UTC (permalink / raw)
To: Dmitry Baryshkov; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: move DSC RC tables to drm_dsc_helper.c (rev3)
URL : https://patchwork.freedesktop.org/series/114473/
State : failure
== Summary ==
Error: patch https://patchwork.freedesktop.org/api/1.0/series/114473/revisions/3/mbox/ not applied
Applying: drm/i915/dsc: change DSC param tables to follow the DSC model
Applying: drm/i915/dsc: move rc_buf_thresh values to common helper
Applying: drm/i915/dsc: move DSC tables to DRM DSC helper
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_vdsc.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0003 drm/i915/dsc: move DSC tables to DRM DSC helper
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced
^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2023-03-28 23:22 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-07 13:48 [PATCH v2 00/10] drm/i915: move DSC RC tables to drm_dsc_helper.c Dmitry Baryshkov
2023-03-07 13:48 ` Dmitry Baryshkov
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
2023-03-07 13:48 ` [PATCH v2 01/10] drm/i915/dsc: change DSC param tables to follow the DSC model Dmitry Baryshkov
2023-03-07 13:48 ` Dmitry Baryshkov
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
2023-03-07 13:48 ` [Intel-gfx] [PATCH v2 02/10] drm/i915/dsc: move rc_buf_thresh values to common helper Dmitry Baryshkov
2023-03-07 13:48 ` Dmitry Baryshkov
2023-03-07 13:48 ` Dmitry Baryshkov
2023-03-07 13:48 ` [Intel-gfx] [PATCH v2 03/10] drm/i915/dsc: move DSC tables to DRM DSC helper Dmitry Baryshkov
2023-03-07 13:48 ` Dmitry Baryshkov
2023-03-07 13:48 ` Dmitry Baryshkov
2023-03-07 13:48 ` [PATCH v2 04/10] drm/i915/dsc: stop using interim structure for calculated params Dmitry Baryshkov
2023-03-07 13:48 ` Dmitry Baryshkov
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
2023-03-07 13:48 ` [Intel-gfx] [PATCH v2 05/10] drm/display/dsc: use flat array for rc_parameters lookup Dmitry Baryshkov
2023-03-07 13:48 ` Dmitry Baryshkov
2023-03-07 13:48 ` Dmitry Baryshkov
2023-03-07 13:48 ` [Intel-gfx] [PATCH v2 06/10] drm/display/dsc: split DSC 1.2 and DSC 1.1 (pre-SCR) parameters Dmitry Baryshkov
2023-03-07 13:48 ` Dmitry Baryshkov
2023-03-07 13:48 ` Dmitry Baryshkov
2023-03-08 10:14 ` Jani Nikula
2023-03-08 10:14 ` [Intel-gfx] " Jani Nikula
2023-03-08 10:14 ` Jani Nikula
2023-03-08 12:59 ` Dmitry Baryshkov
2023-03-08 12:59 ` Dmitry Baryshkov
2023-03-08 12:59 ` [Intel-gfx] " Dmitry Baryshkov
2023-03-08 13:19 ` Jani Nikula
2023-03-08 13:19 ` Jani Nikula
2023-03-08 13:19 ` [Intel-gfx] " Jani Nikula
2023-03-08 16:50 ` Dmitry Baryshkov
2023-03-08 16:50 ` [Intel-gfx] " Dmitry Baryshkov
2023-03-08 16:50 ` Dmitry Baryshkov
2023-03-07 13:48 ` [PATCH v2 07/10] drm/display/dsc: include the rest of pre-SCR parameters Dmitry Baryshkov
2023-03-07 13:48 ` Dmitry Baryshkov
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
2023-03-07 13:48 ` [PATCH v2 08/10] drm/display/dsc: add YCbCr 4:2:2 and 4:2:0 RC parameters Dmitry Baryshkov
2023-03-07 13:48 ` Dmitry Baryshkov
2023-03-07 13:48 ` [Intel-gfx] " Dmitry Baryshkov
2023-03-07 13:49 ` [PATCH v2 09/10] drm/display/dsc: add helper to set semi-const parameters Dmitry Baryshkov
2023-03-07 13:49 ` Dmitry Baryshkov
2023-03-07 13:49 ` [Intel-gfx] " Dmitry Baryshkov
2023-03-07 13:49 ` [PATCH v2 10/10] drm/msm/dsi: use new helpers for DSC setup Dmitry Baryshkov
2023-03-07 13:49 ` Dmitry Baryshkov
2023-03-07 13:49 ` [Intel-gfx] " Dmitry Baryshkov
2023-03-14 8:45 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: move DSC RC tables to drm_dsc_helper.c (rev2) Patchwork
2023-03-28 23:22 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: move DSC RC tables to drm_dsc_helper.c (rev3) Patchwork
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