* [PATCH v2 00/25] tcg: Remove tcg_const_*
@ 2023-03-07 18:34 Richard Henderson
2023-03-07 18:34 ` [PATCH v2 01/25] target/arm: Use rmode >= 0 for need_rmode Richard Henderson
` (24 more replies)
0 siblings, 25 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel
Based-on: 20230307175848.2508955-1-richard.henderson@linaro.org
("[PULL 00/67] tcg patch queue")
This completes the transition from tcg_const_* to tcg_constant_* that
started in 2020.
The bulk of the v1 patch set has been reviewed and is queued above.
A few of these patches are reviewed, but have dependencies on
unreviewed patches and so couldn't be queued.
r~
Needs Review:
02-target-arm-Handle-FPROUNDING_ODD-in-arm_rmode_to_.patch
05-target-arm-Create-gen_set_rmode-gen_restore_rmode.patch
06-target-arm-Improve-trans_BFCI.patch
08-target-arm-Avoid-tcg_const_-in-translate-mve.c.patch
09-target-arm-Avoid-tcg_const_ptr-in-disas_simd_zip_.patch
12-target-m68k-Reject-immediate-as-destination-in-ge.patch
14-target-ppc-Avoid-tcg_const_i64-in-do_vcntmb.patch
15-target-ppc-Avoid-tcg_const_-in-vmx-impl.c.inc.patch
16-target-ppc-Avoid-tcg_const_-in-xxeval.patch
17-target-ppc-Avoid-tcg_const_-in-vsx-impl.c.inc.patch
18-target-ppc-Avoid-tcg_const_-in-fp-impl.c.inc.patch
19-target-ppc-Avoid-tcg_const_-in-power8-pmu-regs.c..patch
20-target-ppc-Rewrite-trans_ADDG6S.patch
21-target-ppc-Fix-gen_tlbsx_booke206.patch
22-target-ppc-Avoid-tcg_const_-in-translate.c.patch
23-target-tricore-Use-min-max-for-saturate.patch
Richard Henderson (25):
target/arm: Use rmode >= 0 for need_rmode
target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf
target/arm: Improve arm_rmode_to_sf
target/arm: Consistently use ARMFPRounding during translation
target/arm: Create gen_set_rmode, gen_restore_rmode
target/arm: Improve trans_BFCI
target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
target/arm: Avoid tcg_const_* in translate-mve.c
target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
target/arm: Avoid tcg_const_ptr in handle_rev
target/m68k: Reject immediate as destination in gen_ea_mode
target/m68k: Use tcg_constant_i32 in gen_ea_mode
target/ppc: Avoid tcg_const_i64 in do_vcntmb
target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
target/ppc: Avoid tcg_const_* in xxeval
target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
target/ppc: Avoid tcg_const_* in fp-impl.c.inc
target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
target/ppc: Rewrite trans_ADDG6S
target/ppc: Fix gen_tlbsx_booke206
target/ppc: Avoid tcg_const_* in translate.c
target/tricore: Use min/max for saturate
tcg: Drop tcg_const_*_vec
tcg: Drop tcg_const_*
include/tcg/tcg-op.h | 4 -
include/tcg/tcg.h | 10 --
target/arm/internals.h | 12 +-
target/arm/tcg/translate.h | 17 +++
target/arm/tcg/translate-a64.c | 168 +++++++++------------
target/arm/tcg/translate-mve.c | 56 +++----
target/arm/tcg/translate-sve.c | 28 ++--
target/arm/tcg/translate-vfp.c | 26 ++--
target/arm/tcg/translate.c | 13 +-
target/arm/vfp_helper.c | 35 +----
target/m68k/translate.c | 6 +-
target/ppc/translate.c | 148 +++++++++---------
target/tricore/translate.c | 14 +-
tcg/tcg-op-vec.c | 34 +----
tcg/tcg.c | 16 --
target/ppc/power8-pmu-regs.c.inc | 4 +-
target/ppc/translate/fixedpoint-impl.c.inc | 44 +++---
target/ppc/translate/fp-impl.c.inc | 26 ++--
target/ppc/translate/vmx-impl.c.inc | 31 ++--
target/ppc/translate/vsx-impl.c.inc | 36 ++---
tcg/i386/tcg-target.c.inc | 9 +-
21 files changed, 326 insertions(+), 411 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v2 01/25] target/arm: Use rmode >= 0 for need_rmode
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 18:34 ` [PATCH v2 02/25] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf Richard Henderson
` (23 subsequent siblings)
24 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Initialize rmode to -1 instead of keeping two variables.
This is already used elsewhere in translate-a64.c.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 34 ++++++----------------------------
1 file changed, 6 insertions(+), 28 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 2c2ea45b47..bef66086a2 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -12133,7 +12133,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
bool need_fpstatus = false;
- bool need_rmode = false;
int rmode = -1;
TCGv_i32 tcg_rmode;
TCGv_ptr tcg_fpstatus;
@@ -12283,7 +12282,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x7a: /* FCVTPU */
case 0x7b: /* FCVTZU */
need_fpstatus = true;
- need_rmode = true;
rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
if (size == 3 && !is_q) {
unallocated_encoding(s);
@@ -12293,7 +12291,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x5c: /* FCVTAU */
case 0x1c: /* FCVTAS */
need_fpstatus = true;
- need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
if (size == 3 && !is_q) {
unallocated_encoding(s);
@@ -12352,7 +12349,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x19: /* FRINTM */
case 0x38: /* FRINTP */
case 0x39: /* FRINTZ */
- need_rmode = true;
rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
/* fall through */
case 0x59: /* FRINTX */
@@ -12364,7 +12360,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
break;
case 0x58: /* FRINTA */
- need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
need_fpstatus = true;
if (size == 3 && !is_q) {
@@ -12380,7 +12375,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
break;
case 0x1e: /* FRINT32Z */
case 0x1f: /* FRINT64Z */
- need_rmode = true;
rmode = FPROUNDING_ZERO;
/* fall through */
case 0x5e: /* FRINT32X */
@@ -12406,12 +12400,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
return;
}
- if (need_fpstatus || need_rmode) {
+ if (need_fpstatus || rmode >= 0) {
tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
} else {
tcg_fpstatus = NULL;
}
- if (need_rmode) {
+ if (rmode >= 0) {
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
} else {
@@ -12595,7 +12589,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
clear_vec_high(s, is_q, rd);
- if (need_rmode) {
+ if (tcg_rmode) {
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
}
}
@@ -12625,9 +12619,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
int pass;
TCGv_i32 tcg_rmode = NULL;
TCGv_ptr tcg_fpstatus = NULL;
- bool need_rmode = false;
bool need_fpst = true;
- int rmode;
+ int rmode = -1;
if (!dc_isar_feature(aa64_fp16, s)) {
unallocated_encoding(s);
@@ -12676,27 +12669,22 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x3f: /* FRECPX */
break;
case 0x18: /* FRINTN */
- need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x19: /* FRINTM */
- need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x38: /* FRINTP */
- need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_POSINF;
break;
case 0x39: /* FRINTZ */
- need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_ZERO;
break;
case 0x58: /* FRINTA */
- need_rmode = true;
only_in_vector = true;
rmode = FPROUNDING_TIEAWAY;
break;
@@ -12706,43 +12694,33 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
/* current rounding mode */
break;
case 0x1a: /* FCVTNS */
- need_rmode = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x1b: /* FCVTMS */
- need_rmode = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x1c: /* FCVTAS */
- need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
break;
case 0x3a: /* FCVTPS */
- need_rmode = true;
rmode = FPROUNDING_POSINF;
break;
case 0x3b: /* FCVTZS */
- need_rmode = true;
rmode = FPROUNDING_ZERO;
break;
case 0x5a: /* FCVTNU */
- need_rmode = true;
rmode = FPROUNDING_TIEEVEN;
break;
case 0x5b: /* FCVTMU */
- need_rmode = true;
rmode = FPROUNDING_NEGINF;
break;
case 0x5c: /* FCVTAU */
- need_rmode = true;
rmode = FPROUNDING_TIEAWAY;
break;
case 0x7a: /* FCVTPU */
- need_rmode = true;
rmode = FPROUNDING_POSINF;
break;
case 0x7b: /* FCVTZU */
- need_rmode = true;
rmode = FPROUNDING_ZERO;
break;
case 0x2f: /* FABS */
@@ -12775,11 +12753,11 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
return;
}
- if (need_rmode || need_fpst) {
+ if (rmode >= 0 || need_fpst) {
tcg_fpstatus = fpstatus_ptr(FPST_FPCR_F16);
}
- if (need_rmode) {
+ if (rmode >= 0) {
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 02/25] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
2023-03-07 18:34 ` [PATCH v2 01/25] target/arm: Use rmode >= 0 for need_rmode Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-08 17:25 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 03/25] target/arm: Improve arm_rmode_to_sf Richard Henderson
` (22 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
While this enumerator has been present since the first commit,
it isn't ever used. The first actual use of round-to-odd came
with SVE, which currently uses float_round_to_odd instead of
the arm-specific enumerator.
Amusingly, the comment about unhandled TIEAWAY has been
out of date since the initial commit of translate-a64.c.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: qemu-arm@nongnu.org
---
target/arm/vfp_helper.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 24e3d820a5..90cc324f71 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -1111,10 +1111,8 @@ int arm_rmode_to_sf(int rmode)
rmode = float_round_ties_away;
break;
case FPROUNDING_ODD:
- /* FIXME: add support for TIEAWAY and ODD */
- qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
- rmode);
- /* fall through for now */
+ rmode = float_round_to_odd;
+ break;
case FPROUNDING_TIEEVEN:
default:
rmode = float_round_nearest_even;
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 03/25] target/arm: Improve arm_rmode_to_sf
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
2023-03-07 18:34 ` [PATCH v2 01/25] target/arm: Use rmode >= 0 for need_rmode Richard Henderson
2023-03-07 18:34 ` [PATCH v2 02/25] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 18:34 ` [PATCH v2 04/25] target/arm: Consistently use ARMFPRounding during translation Richard Henderson
` (21 subsequent siblings)
24 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Use proper enumeration types for input and output.
Use a const array to perform the mapping, with an
assert that the input is valid.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/internals.h | 12 +++++++++---
target/arm/tcg/translate-mve.c | 2 +-
target/arm/vfp_helper.c | 33 ++++++++-------------------------
3 files changed, 18 insertions(+), 29 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index b1ef05963f..673519a24a 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -193,16 +193,22 @@ void arm_restore_state_to_opc(CPUState *cs,
void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
#endif /* CONFIG_TCG */
-enum arm_fprounding {
+typedef enum ARMFPRounding {
FPROUNDING_TIEEVEN,
FPROUNDING_POSINF,
FPROUNDING_NEGINF,
FPROUNDING_ZERO,
FPROUNDING_TIEAWAY,
FPROUNDING_ODD
-};
+} ARMFPRounding;
-int arm_rmode_to_sf(int rmode);
+extern const FloatRoundMode arm_rmode_to_sf_map[6];
+
+static inline FloatRoundMode arm_rmode_to_sf(ARMFPRounding rmode)
+{
+ assert((unsigned)rmode < ARRAY_SIZE(arm_rmode_to_sf_map));
+ return arm_rmode_to_sf_map[rmode];
+}
static inline void aarch64_save_sp(CPUARMState *env, int el)
{
diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c
index 798b4fddfe..9744bf3de0 100644
--- a/target/arm/tcg/translate-mve.c
+++ b/target/arm/tcg/translate-mve.c
@@ -588,7 +588,7 @@ DO_VCVT(VCVT_FS, vcvt_hs, vcvt_fs)
DO_VCVT(VCVT_FU, vcvt_hu, vcvt_fu)
static bool do_vcvt_rmode(DisasContext *s, arg_1op *a,
- enum arm_fprounding rmode, bool u)
+ ARMFPRounding rmode, bool u)
{
/*
* Handle VCVT fp to int with specified rounding mode.
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index 90cc324f71..36906db8e0 100644
--- a/target/arm/vfp_helper.c
+++ b/target/arm/vfp_helper.c
@@ -1104,31 +1104,14 @@ float64 HELPER(rintd)(float64 x, void *fp_status)
}
/* Convert ARM rounding mode to softfloat */
-int arm_rmode_to_sf(int rmode)
-{
- switch (rmode) {
- case FPROUNDING_TIEAWAY:
- rmode = float_round_ties_away;
- break;
- case FPROUNDING_ODD:
- rmode = float_round_to_odd;
- break;
- case FPROUNDING_TIEEVEN:
- default:
- rmode = float_round_nearest_even;
- break;
- case FPROUNDING_POSINF:
- rmode = float_round_up;
- break;
- case FPROUNDING_NEGINF:
- rmode = float_round_down;
- break;
- case FPROUNDING_ZERO:
- rmode = float_round_to_zero;
- break;
- }
- return rmode;
-}
+const FloatRoundMode arm_rmode_to_sf_map[] = {
+ [FPROUNDING_TIEEVEN] = float_round_nearest_even,
+ [FPROUNDING_POSINF] = float_round_up,
+ [FPROUNDING_NEGINF] = float_round_down,
+ [FPROUNDING_ZERO] = float_round_to_zero,
+ [FPROUNDING_TIEAWAY] = float_round_ties_away,
+ [FPROUNDING_ODD] = float_round_to_odd,
+};
/*
* Implement float64 to int32_t conversion without saturation;
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 04/25] target/arm: Consistently use ARMFPRounding during translation
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (2 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 03/25] target/arm: Improve arm_rmode_to_sf Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 18:34 ` [PATCH v2 05/25] target/arm: Create gen_set_rmode, gen_restore_rmode Richard Henderson
` (20 subsequent siblings)
24 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
In preparation for extracting new helpers, ensure that
the rounding mode is represented as ARMFPRounding and
not FloatRoundMode.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 16 ++++++++--------
target/arm/tcg/translate-sve.c | 18 +++++++++---------
target/arm/tcg/translate-vfp.c | 6 +++---
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index bef66086a2..210899ff79 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -6202,7 +6202,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
case 0xa: /* FRINTM */
case 0xb: /* FRINTZ */
case 0xc: /* FRINTA */
- rmode = arm_rmode_to_sf(opcode & 7);
+ rmode = opcode & 7;
gen_fpst = gen_helper_rints;
break;
case 0xe: /* FRINTX */
@@ -6212,14 +6212,14 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
gen_fpst = gen_helper_rints;
break;
case 0x10: /* FRINT32Z */
- rmode = float_round_to_zero;
+ rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint32_s;
break;
case 0x11: /* FRINT32X */
gen_fpst = gen_helper_frint32_s;
break;
case 0x12: /* FRINT64Z */
- rmode = float_round_to_zero;
+ rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint64_s;
break;
case 0x13: /* FRINT64X */
@@ -6231,7 +6231,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
- TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
+ TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
@@ -6275,7 +6275,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
case 0xa: /* FRINTM */
case 0xb: /* FRINTZ */
case 0xc: /* FRINTA */
- rmode = arm_rmode_to_sf(opcode & 7);
+ rmode = opcode & 7;
gen_fpst = gen_helper_rintd;
break;
case 0xe: /* FRINTX */
@@ -6285,14 +6285,14 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
gen_fpst = gen_helper_rintd;
break;
case 0x10: /* FRINT32Z */
- rmode = float_round_to_zero;
+ rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint32_d;
break;
case 0x11: /* FRINT32X */
gen_fpst = gen_helper_frint32_d;
break;
case 0x12: /* FRINT64Z */
- rmode = float_round_to_zero;
+ rmode = FPROUNDING_ZERO;
gen_fpst = gen_helper_frint64_d;
break;
case 0x13: /* FRINT64X */
@@ -6304,7 +6304,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
- TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
+ TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 5bf80b22d7..3c65dd1ff2 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4082,7 +4082,7 @@ TRANS_FEAT(FRINTX, aa64_sve, gen_gvec_fpst_arg_zpz, frintx_fns[a->esz],
a, 0, a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
- int mode, gen_helper_gvec_3_ptr *fn)
+ ARMFPRounding mode, gen_helper_gvec_3_ptr *fn)
{
unsigned vsz;
TCGv_i32 tmode;
@@ -4096,7 +4096,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
}
vsz = vec_full_reg_size(s);
- tmode = tcg_const_i32(mode);
+ tmode = tcg_const_i32(arm_rmode_to_sf(mode));
status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
gen_helper_set_rmode(tmode, tmode, status);
@@ -4111,15 +4111,15 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
}
TRANS_FEAT(FRINTN, aa64_sve, do_frint_mode, a,
- float_round_nearest_even, frint_fns[a->esz])
+ FPROUNDING_TIEEVEN, frint_fns[a->esz])
TRANS_FEAT(FRINTP, aa64_sve, do_frint_mode, a,
- float_round_up, frint_fns[a->esz])
+ FPROUNDING_POSINF, frint_fns[a->esz])
TRANS_FEAT(FRINTM, aa64_sve, do_frint_mode, a,
- float_round_down, frint_fns[a->esz])
+ FPROUNDING_NEGINF, frint_fns[a->esz])
TRANS_FEAT(FRINTZ, aa64_sve, do_frint_mode, a,
- float_round_to_zero, frint_fns[a->esz])
+ FPROUNDING_ZERO, frint_fns[a->esz])
TRANS_FEAT(FRINTA, aa64_sve, do_frint_mode, a,
- float_round_ties_away, frint_fns[a->esz])
+ FPROUNDING_TIEAWAY, frint_fns[a->esz])
static gen_helper_gvec_3_ptr * const frecpx_fns[] = {
NULL, gen_helper_sve_frecpx_h,
@@ -7145,9 +7145,9 @@ TRANS_FEAT(FCVTLT_sd, aa64_sve2, gen_gvec_fpst_arg_zpz,
gen_helper_sve2_fcvtlt_sd, a, 0, FPST_FPCR)
TRANS_FEAT(FCVTX_ds, aa64_sve2, do_frint_mode, a,
- float_round_to_odd, gen_helper_sve_fcvt_ds)
+ FPROUNDING_ODD, gen_helper_sve_fcvt_ds)
TRANS_FEAT(FCVTXNT_ds, aa64_sve2, do_frint_mode, a,
- float_round_to_odd, gen_helper_sve2_fcvtnt_ds)
+ FPROUNDING_ODD, gen_helper_sve2_fcvtnt_ds)
static gen_helper_gvec_3_ptr * const flogb_fns[] = {
NULL, gen_helper_flogb_h,
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
index 757a2bf7d9..e7acfb3338 100644
--- a/target/arm/tcg/translate-vfp.c
+++ b/target/arm/tcg/translate-vfp.c
@@ -2783,7 +2783,7 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR_F16);
- tcg_rmode = tcg_const_i32(float_round_to_zero);
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_helper_rinth(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
@@ -2808,7 +2808,7 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
- tcg_rmode = tcg_const_i32(float_round_to_zero);
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_helper_rints(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
@@ -2842,7 +2842,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
- tcg_rmode = tcg_const_i32(float_round_to_zero);
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
gen_helper_rintd(tmp, tmp, fpst);
gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 05/25] target/arm: Create gen_set_rmode, gen_restore_rmode
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (3 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 04/25] target/arm: Consistently use ARMFPRounding during translation Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-09 9:48 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 06/25] target/arm: Improve trans_BFCI Richard Henderson
` (19 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Split out common subroutines for handing rounding mode
changes during translation. Use tcg_constant_i32 and
tcg_temp_new_i32 instead of tcg_const_i32.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: qemu-arm@nongnu.org
---
target/arm/tcg/translate.h | 17 ++++++++++++
target/arm/tcg/translate-a64.c | 47 ++++++++++++++--------------------
target/arm/tcg/translate-sve.c | 6 ++---
target/arm/tcg/translate-vfp.c | 26 ++++++++-----------
4 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 20f3ca7aca..f02d4685b4 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -616,6 +616,23 @@ static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
return ret;
}
+/*
+ * Set and reset rounding mode around another operation.
+ */
+static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst)
+{
+ TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode));
+ TCGv_i32 old = tcg_temp_new_i32();
+
+ gen_helper_set_rmode(old, new, fpst);
+ return old;
+}
+
+static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)
+{
+ gen_helper_set_rmode(old, old, fpst);
+}
+
/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 210899ff79..989c958de6 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -6146,13 +6146,12 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
case 0xb: /* FRINTZ */
case 0xc: /* FRINTA */
{
- TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
+ TCGv_i32 tcg_rmode;
+
fpst = fpstatus_ptr(FPST_FPCR_F16);
-
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(opcode & 7, fpst);
gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
-
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
break;
}
case 0xe: /* FRINTX */
@@ -6231,10 +6230,9 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
- TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
} else {
gen_fpst(tcg_res, tcg_op, fpst);
}
@@ -6304,10 +6302,9 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
fpst = fpstatus_ptr(FPST_FPCR);
if (rmode >= 0) {
- TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ TCGv_i32 tcg_rmode = gen_set_rmode(rmode, fpst);
gen_fpst(tcg_res, tcg_op, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
} else {
gen_fpst(tcg_res, tcg_op, fpst);
}
@@ -6944,9 +6941,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
rmode = FPROUNDING_TIEAWAY;
}
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
-
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
switch (type) {
case 1: /* float64 */
@@ -7023,7 +7018,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
g_assert_not_reached();
}
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@@ -8771,9 +8766,8 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
assert(!(is_scalar && is_q));
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
tcg_fpstatus = fpstatus_ptr(size == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, tcg_fpstatus);
fracbits = (16 << size) - immhb;
tcg_shift = tcg_constant_i32(fracbits);
@@ -8831,7 +8825,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
}
}
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
/* AdvSIMD scalar shift by immediate
@@ -10219,12 +10213,11 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
if (is_fcvt) {
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
} else {
- tcg_rmode = NULL;
tcg_fpstatus = NULL;
+ tcg_rmode = NULL;
}
if (size == 3) {
@@ -10276,7 +10269,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
if (is_fcvt) {
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@@ -12406,8 +12399,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
tcg_fpstatus = NULL;
}
if (rmode >= 0) {
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
} else {
tcg_rmode = NULL;
}
@@ -12590,7 +12582,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
clear_vec_high(s, is_q, rd);
if (tcg_rmode) {
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
@@ -12758,8 +12750,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
}
if (rmode >= 0) {
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
}
if (is_scalar) {
@@ -12859,7 +12850,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
}
if (tcg_rmode) {
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
+ gen_restore_rmode(tcg_rmode, tcg_fpstatus);
}
}
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 3c65dd1ff2..3ca60fb36b 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4096,17 +4096,15 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a,
}
vsz = vec_full_reg_size(s);
- tmode = tcg_const_i32(arm_rmode_to_sf(mode));
status = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
-
- gen_helper_set_rmode(tmode, tmode, status);
+ tmode = gen_set_rmode(mode, status);
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),
vec_full_reg_offset(s, a->rn),
pred_full_reg_offset(s, a->pg),
status, vsz, vsz, 0, fn);
- gen_helper_set_rmode(tmode, tmode, status);
+ gen_restore_rmode(tmode, status);
return true;
}
diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c
index e7acfb3338..dd782aacf4 100644
--- a/target/arm/tcg/translate-vfp.c
+++ b/target/arm/tcg/translate-vfp.c
@@ -464,8 +464,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
fpst = fpstatus_ptr(FPST_FPCR);
}
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(rounding, fpst);
if (sz == 3) {
TCGv_i64 tcg_op;
@@ -489,7 +488,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
vfp_store_reg32(tcg_res, rd);
}
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
return true;
}
@@ -533,9 +532,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
}
tcg_shift = tcg_constant_i32(0);
-
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(rounding, fpst);
if (sz == 3) {
TCGv_i64 tcg_double, tcg_res;
@@ -572,7 +569,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
vfp_store_reg32(tcg_res, rd);
}
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
return true;
}
@@ -2783,10 +2780,9 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR_F16);
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rinth(tmp, tmp, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
}
@@ -2808,10 +2804,9 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VRINTZ_sp *a)
tmp = tcg_temp_new_i32();
vfp_load_reg32(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rints(tmp, tmp, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg32(tmp, a->vd);
return true;
}
@@ -2842,10 +2837,9 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
tmp = tcg_temp_new_i64();
vfp_load_reg64(tmp, a->vm);
fpst = fpstatus_ptr(FPST_FPCR);
- tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ tcg_rmode = gen_set_rmode(FPROUNDING_ZERO, fpst);
gen_helper_rintd(tmp, tmp, fpst);
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
+ gen_restore_rmode(tcg_rmode, fpst);
vfp_store_reg64(tmp, a->vd);
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 06/25] target/arm: Improve trans_BFCI
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (4 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 05/25] target/arm: Create gen_set_rmode, gen_restore_rmode Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 23:05 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 07/25] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr, str} Richard Henderson
` (18 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Reorg temporary usage so that we can use tcg_constant_i32.
tcg_gen_deposit_i32 already has a width == 32 special case,
so remove the check here.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: qemu-arm@nongnu.org
---
target/arm/tcg/translate.c | 13 +++++--------
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index b70b628000..4451aea09c 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -7261,8 +7261,8 @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a)
static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
{
- TCGv_i32 tmp;
int msb = a->msb, lsb = a->lsb;
+ TCGv_i32 t_in, t_rd;
int width;
if (!ENABLE_ARCH_6T2) {
@@ -7277,16 +7277,13 @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
width = msb + 1 - lsb;
if (a->rn == 15) {
/* BFC */
- tmp = tcg_const_i32(0);
+ t_in = tcg_constant_i32(0);
} else {
/* BFI */
- tmp = load_reg(s, a->rn);
+ t_in = load_reg(s, a->rn);
}
- if (width != 32) {
- TCGv_i32 tmp2 = load_reg(s, a->rd);
- tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width);
- }
- store_reg(s, a->rd, tmp);
+ t_rd = load_reg(s, a->rd);
+ tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width);
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 07/25] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr, str}
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (5 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 06/25] target/arm: Improve trans_BFCI Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 18:34 ` [PATCH v2 08/25] target/arm: Avoid tcg_const_* in translate-mve.c Richard Henderson
` (17 subsequent siblings)
24 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
This hides the implicit initialization of a variable.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-sve.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 3ca60fb36b..92ab290106 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -4206,8 +4206,9 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs,
}
} else {
TCGLabel *loop = gen_new_label();
- TCGv_ptr tp, i = tcg_const_ptr(0);
+ TCGv_ptr tp, i = tcg_temp_new_ptr();
+ tcg_gen_movi_ptr(i, 0);
gen_set_label(loop);
t0 = tcg_temp_new_i64();
@@ -4284,8 +4285,9 @@ void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs,
}
} else {
TCGLabel *loop = gen_new_label();
- TCGv_ptr tp, i = tcg_const_ptr(0);
+ TCGv_ptr tp, i = tcg_temp_new_ptr();
+ tcg_gen_movi_ptr(i, 0);
gen_set_label(loop);
t0 = tcg_temp_new_i64();
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 08/25] target/arm: Avoid tcg_const_* in translate-mve.c
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (6 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 07/25] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr, str} Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-09 13:27 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 09/25] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn Richard Henderson
` (16 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
All uses are in the context of an accumulator conditionally
having a zero input. Split the rda variable to rda_{i,o},
and set rda_i to tcg_constant_foo(0) when required.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: qemu-arm@nongnu.org
---
target/arm/tcg/translate-mve.c | 54 ++++++++++++++++++----------------
1 file changed, 29 insertions(+), 25 deletions(-)
diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c
index 9744bf3de0..31fb2110f1 100644
--- a/target/arm/tcg/translate-mve.c
+++ b/target/arm/tcg/translate-mve.c
@@ -1150,7 +1150,7 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
MVEGenLongDualAccOpFn *fn)
{
TCGv_ptr qn, qm;
- TCGv_i64 rda;
+ TCGv_i64 rda_i, rda_o;
TCGv_i32 rdalo, rdahi;
if (!dc_isar_feature(aa32_mve, s) ||
@@ -1177,21 +1177,22 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
* of an A=0 (no-accumulate) insn which does not execute the first
* beat must start with the current rda value, not 0.
*/
+ rda_o = tcg_temp_new_i64();
if (a->a || mve_skip_first_beat(s)) {
- rda = tcg_temp_new_i64();
+ rda_i = rda_o;
rdalo = load_reg(s, a->rdalo);
rdahi = load_reg(s, a->rdahi);
- tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
+ tcg_gen_concat_i32_i64(rda_i, rdalo, rdahi);
} else {
- rda = tcg_const_i64(0);
+ rda_i = tcg_constant_i64(0);
}
- fn(rda, cpu_env, qn, qm, rda);
+ fn(rda_o, cpu_env, qn, qm, rda_i);
rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(rdalo, rda);
- tcg_gen_extrh_i64_i32(rdahi, rda);
+ tcg_gen_extrl_i64_i32(rdalo, rda_o);
+ tcg_gen_extrh_i64_i32(rdahi, rda_o);
store_reg(s, a->rdalo, rdalo);
store_reg(s, a->rdahi, rdahi);
mve_update_eci(s);
@@ -1258,7 +1259,7 @@ static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a)
static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)
{
TCGv_ptr qn, qm;
- TCGv_i32 rda;
+ TCGv_i32 rda_i, rda_o;
if (!dc_isar_feature(aa32_mve, s) ||
!mve_check_qreg_bank(s, a->qn) ||
@@ -1278,13 +1279,14 @@ static bool do_dual_acc(DisasContext *s, arg_vmladav *a, MVEGenDualAccOpFn *fn)
* beat must start with the current rda value, not 0.
*/
if (a->a || mve_skip_first_beat(s)) {
- rda = load_reg(s, a->rda);
+ rda_o = rda_i = load_reg(s, a->rda);
} else {
- rda = tcg_const_i32(0);
+ rda_i = tcg_constant_i32(0);
+ rda_o = tcg_temp_new_i32();
}
- fn(rda, cpu_env, qn, qm, rda);
- store_reg(s, a->rda, rda);
+ fn(rda_o, cpu_env, qn, qm, rda_i);
+ store_reg(s, a->rda, rda_o);
mve_update_eci(s);
return true;
@@ -1396,7 +1398,7 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
{ NULL, NULL }
};
TCGv_ptr qm;
- TCGv_i32 rda;
+ TCGv_i32 rda_i, rda_o;
if (!dc_isar_feature(aa32_mve, s) ||
a->size == 3) {
@@ -1413,15 +1415,16 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a)
*/
if (a->a || mve_skip_first_beat(s)) {
/* Accumulate input from Rda */
- rda = load_reg(s, a->rda);
+ rda_o = rda_i = load_reg(s, a->rda);
} else {
/* Accumulate starting at zero */
- rda = tcg_const_i32(0);
+ rda_i = tcg_constant_i32(0);
+ rda_o = tcg_temp_new_i32();
}
qm = mve_qreg_ptr(a->qm);
- fns[a->size][a->u](rda, cpu_env, qm, rda);
- store_reg(s, a->rda, rda);
+ fns[a->size][a->u](rda_o, cpu_env, qm, rda_i);
+ store_reg(s, a->rda, rda_o);
mve_update_eci(s);
return true;
@@ -1436,7 +1439,7 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
* No need to check Qm's bank: it is only 3 bits in decode.
*/
TCGv_ptr qm;
- TCGv_i64 rda;
+ TCGv_i64 rda_i, rda_o;
TCGv_i32 rdalo, rdahi;
if (!dc_isar_feature(aa32_mve, s)) {
@@ -1458,28 +1461,29 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV *a)
* of an A=0 (no-accumulate) insn which does not execute the first
* beat must start with the current value of RdaHi:RdaLo, not zero.
*/
+ rda_o = tcg_temp_new_i64();
if (a->a || mve_skip_first_beat(s)) {
/* Accumulate input from RdaHi:RdaLo */
- rda = tcg_temp_new_i64();
+ rda_i = rda_o;
rdalo = load_reg(s, a->rdalo);
rdahi = load_reg(s, a->rdahi);
- tcg_gen_concat_i32_i64(rda, rdalo, rdahi);
+ tcg_gen_concat_i32_i64(rda_i, rdalo, rdahi);
} else {
/* Accumulate starting at zero */
- rda = tcg_const_i64(0);
+ rda_i = tcg_constant_i64(0);
}
qm = mve_qreg_ptr(a->qm);
if (a->u) {
- gen_helper_mve_vaddlv_u(rda, cpu_env, qm, rda);
+ gen_helper_mve_vaddlv_u(rda_o, cpu_env, qm, rda_i);
} else {
- gen_helper_mve_vaddlv_s(rda, cpu_env, qm, rda);
+ gen_helper_mve_vaddlv_s(rda_o, cpu_env, qm, rda_i);
}
rdalo = tcg_temp_new_i32();
rdahi = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(rdalo, rda);
- tcg_gen_extrh_i64_i32(rdahi, rda);
+ tcg_gen_extrl_i64_i32(rdalo, rda_o);
+ tcg_gen_extrh_i64_i32(rdahi, rda_o);
store_reg(s, a->rdalo, rdalo);
store_reg(s, a->rdahi, rdahi);
mve_update_eci(s);
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 09/25] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (7 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 08/25] target/arm: Avoid tcg_const_* in translate-mve.c Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 23:02 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 10/25] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn Richard Henderson
` (15 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
It is easy enough to use mov instead of or-with-zero
and relying on the optimizer to fold away the or.
Use an array for the output, rather than separate
tcg_res{l,h} variables.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: qemu-arm@nongnu.org
---
target/arm/tcg/translate-a64.c | 41 +++++++++++++++++-----------------
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 989c958de6..2ad7c48901 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7442,10 +7442,10 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
bool part = extract32(insn, 14, 1);
bool is_q = extract32(insn, 30, 1);
int esize = 8 << size;
- int i, ofs;
+ int i;
int datasize = is_q ? 128 : 64;
int elements = datasize / esize;
- TCGv_i64 tcg_res, tcg_resl, tcg_resh;
+ TCGv_i64 tcg_res[2], tcg_ele;
if (opcode == 0 || (size == 3 && !is_q)) {
unallocated_encoding(s);
@@ -7456,37 +7456,39 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
return;
}
- tcg_resl = tcg_const_i64(0);
- tcg_resh = is_q ? tcg_const_i64(0) : NULL;
- tcg_res = tcg_temp_new_i64();
+ tcg_res[0] = tcg_temp_new_i64();
+ tcg_res[1] = is_q ? tcg_temp_new_i64() : NULL;
+ tcg_ele = tcg_temp_new_i64();
for (i = 0; i < elements; i++) {
+ int o, w;
+
switch (opcode) {
case 1: /* UZP1/2 */
{
int midpoint = elements / 2;
if (i < midpoint) {
- read_vec_element(s, tcg_res, rn, 2 * i + part, size);
+ read_vec_element(s, tcg_ele, rn, 2 * i + part, size);
} else {
- read_vec_element(s, tcg_res, rm,
+ read_vec_element(s, tcg_ele, rm,
2 * (i - midpoint) + part, size);
}
break;
}
case 2: /* TRN1/2 */
if (i & 1) {
- read_vec_element(s, tcg_res, rm, (i & ~1) + part, size);
+ read_vec_element(s, tcg_ele, rm, (i & ~1) + part, size);
} else {
- read_vec_element(s, tcg_res, rn, (i & ~1) + part, size);
+ read_vec_element(s, tcg_ele, rn, (i & ~1) + part, size);
}
break;
case 3: /* ZIP1/2 */
{
int base = part * elements / 2;
if (i & 1) {
- read_vec_element(s, tcg_res, rm, base + (i >> 1), size);
+ read_vec_element(s, tcg_ele, rm, base + (i >> 1), size);
} else {
- read_vec_element(s, tcg_res, rn, base + (i >> 1), size);
+ read_vec_element(s, tcg_ele, rn, base + (i >> 1), size);
}
break;
}
@@ -7494,19 +7496,18 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
g_assert_not_reached();
}
- ofs = i * esize;
- if (ofs < 64) {
- tcg_gen_shli_i64(tcg_res, tcg_res, ofs);
- tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res);
+ w = (i * esize) / 64;
+ o = (i * esize) % 64;
+ if (o == 0) {
+ tcg_gen_mov_i64(tcg_res[w], tcg_ele);
} else {
- tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64);
- tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res);
+ tcg_gen_shli_i64(tcg_ele, tcg_ele, o);
+ tcg_gen_or_i64(tcg_res[w], tcg_res[w], tcg_ele);
}
}
- write_vec_element(s, tcg_resl, rd, 0, MO_64);
- if (is_q) {
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
+ for (i = 0; i <= is_q; ++i) {
+ write_vec_element(s, tcg_res[i], rd, i, MO_64);
}
clear_vec_high(s, is_q, rd);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 10/25] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (8 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 09/25] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 18:34 ` [PATCH v2 11/25] target/arm: Avoid tcg_const_ptr in handle_rev Richard Henderson
` (14 subsequent siblings)
24 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
It is easy enough to use mov instead of or-with-zero
and relying on the optimizer to fold away the or.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 2ad7c48901..082a8b82dd 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -8459,7 +8459,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
tcg_rn = tcg_temp_new_i64();
tcg_rd = tcg_temp_new_i64();
tcg_rd_narrowed = tcg_temp_new_i32();
- tcg_final = tcg_const_i64(0);
+ tcg_final = tcg_temp_new_i64();
if (round) {
tcg_round = tcg_constant_i64(1ULL << (shift - 1));
@@ -8473,7 +8473,11 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
false, is_u_shift, size+1, shift);
narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd);
tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed);
- tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
+ if (i == 0) {
+ tcg_gen_mov_i64(tcg_final, tcg_rd);
+ } else {
+ tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
+ }
}
if (!is_q) {
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 11/25] target/arm: Avoid tcg_const_ptr in handle_rev
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (9 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 10/25] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 18:34 ` [PATCH v2 12/25] target/m68k: Reject immediate as destination in gen_ea_mode Richard Henderson
` (13 subsequent siblings)
24 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Here it is not trivial to notice first initialization, so explicitly
zero the temps. Use an array for the output, rather than separate
tcg_rd/tcg_rd_hi variables.
Fixes a bug by adding a missing clear_vec_high.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-a64.c | 26 +++++++++++++++-----------
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 082a8b82dd..dff391bfe2 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -12003,22 +12003,26 @@ static void handle_rev(DisasContext *s, int opcode, bool u,
int esize = 8 << size;
int elements = dsize / esize;
TCGv_i64 tcg_rn = tcg_temp_new_i64();
- TCGv_i64 tcg_rd = tcg_const_i64(0);
- TCGv_i64 tcg_rd_hi = tcg_const_i64(0);
+ TCGv_i64 tcg_rd[2];
+
+ for (i = 0; i < 2; i++) {
+ tcg_rd[i] = tcg_temp_new_i64();
+ tcg_gen_movi_i64(tcg_rd[i], 0);
+ }
for (i = 0; i < elements; i++) {
int e_rev = (i & 0xf) ^ revmask;
- int off = e_rev * esize;
+ int w = (e_rev * esize) / 64;
+ int o = (e_rev * esize) % 64;
+
read_vec_element(s, tcg_rn, rn, i, size);
- if (off >= 64) {
- tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi,
- tcg_rn, off - 64, esize);
- } else {
- tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize);
- }
+ tcg_gen_deposit_i64(tcg_rd[w], tcg_rd[w], tcg_rn, o, esize);
}
- write_vec_element(s, tcg_rd, rd, 0, MO_64);
- write_vec_element(s, tcg_rd_hi, rd, 1, MO_64);
+
+ for (i = 0; i < 2; i++) {
+ write_vec_element(s, tcg_rd[i], rd, i, MO_64);
+ }
+ clear_vec_high(s, true, rd);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 12/25] target/m68k: Reject immediate as destination in gen_ea_mode
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (10 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 11/25] target/arm: Avoid tcg_const_ptr in handle_rev Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-09 12:32 ` Laurent Vivier
2023-03-07 18:34 ` [PATCH v2 13/25] target/m68k: Use tcg_constant_i32 " Richard Henderson
` (12 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel; +Cc: Laurent Vivier
In theory this should never happen, as all such instructions
are illegal. This is checked in e.g. gen_lea_mode and
gen_ea_mode_fp but not here. In case something higher up
isn't checking modes properly, return NULL_QREG. This will
result in an illegal instruction exception being raised.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Laurent Vivier <laurent@vivier.eu>
---
target/m68k/translate.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 44c3ac0bc3..fc65dad190 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -894,6 +894,10 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
case 3: /* pc index+displacement. */
goto do_indirect;
case 4: /* Immediate. */
+ /* Should never be used for an output or RMW input. */
+ if (what == EA_STORE || addrp) {
+ return NULL_QREG;
+ }
/* Sign extend values for consistency. */
switch (opsize) {
case OS_BYTE:
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 13/25] target/m68k: Use tcg_constant_i32 in gen_ea_mode
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (11 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 12/25] target/m68k: Reject immediate as destination in gen_ea_mode Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 18:34 ` [PATCH v2 14/25] target/ppc: Avoid tcg_const_i64 in do_vcntmb Richard Henderson
` (11 subsequent siblings)
24 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Return a constant for an immediate input.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index fc65dad190..e16c608ef8 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -920,7 +920,7 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
default:
g_assert_not_reached();
}
- return tcg_const_i32(offset);
+ return tcg_constant_i32(offset);
default:
return NULL_QREG;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 14/25] target/ppc: Avoid tcg_const_i64 in do_vcntmb
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (12 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 13/25] target/m68k: Use tcg_constant_i32 " Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 21:42 ` Daniel Henrique Barboza
2023-03-09 10:18 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 15/25] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc Richard Henderson
` (10 subsequent siblings)
24 siblings, 2 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
Compute both partial results separately and accumulate
at the end, instead of accumulating in the middle.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: Cédric Le Goater <clg@kaod.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Greg Kurz <groug@kaod.org>
Cc: qemu-ppc@nongnu.org
---
target/ppc/translate/vmx-impl.c.inc | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 7af6d7217d..ca27c11d87 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -2236,24 +2236,25 @@ static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)
static bool do_vcntmb(DisasContext *ctx, arg_VX_mp *a, int vece)
{
- TCGv_i64 rt, vrb, mask;
- rt = tcg_const_i64(0);
- vrb = tcg_temp_new_i64();
+ TCGv_i64 r[2], mask;
+
+ r[0] = tcg_temp_new_i64();
+ r[1] = tcg_temp_new_i64();
mask = tcg_constant_i64(dup_const(vece, 1ULL << ((8 << vece) - 1)));
for (int i = 0; i < 2; i++) {
- get_avr64(vrb, a->vrb, i);
+ get_avr64(r[i], a->vrb, i);
if (a->mp) {
- tcg_gen_and_i64(vrb, mask, vrb);
+ tcg_gen_and_i64(r[i], mask, r[i]);
} else {
- tcg_gen_andc_i64(vrb, mask, vrb);
+ tcg_gen_andc_i64(r[i], mask, r[i]);
}
- tcg_gen_ctpop_i64(vrb, vrb);
- tcg_gen_add_i64(rt, rt, vrb);
+ tcg_gen_ctpop_i64(r[i], r[i]);
}
- tcg_gen_shli_i64(rt, rt, TARGET_LONG_BITS - 8 + vece);
- tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], rt);
+ tcg_gen_add_i64(r[0], r[0], r[1]);
+ tcg_gen_shli_i64(r[0], r[0], TARGET_LONG_BITS - 8 + vece);
+ tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], r[0]);
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 15/25] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (13 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 14/25] target/ppc: Avoid tcg_const_i64 in do_vcntmb Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 21:42 ` Daniel Henrique Barboza
2023-03-09 9:49 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 16/25] target/ppc: Avoid tcg_const_* in xxeval Richard Henderson
` (9 subsequent siblings)
24 siblings, 2 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
All remaining uses are strictly read-only.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: Cédric Le Goater <clg@kaod.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Greg Kurz <groug@kaod.org>
Cc: qemu-ppc@nongnu.org
---
target/ppc/translate/vmx-impl.c.inc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index ca27c11d87..112233b541 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1624,7 +1624,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VPU); \
return; \
} \
- uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
+ uimm = tcg_constant_i32(UIMM5(ctx->opcode)); \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
gen_helper_##name(cpu_env, rd, rb, uimm); \
@@ -1965,7 +1965,7 @@ static void gen_vsldoi(DisasContext *ctx)
ra = gen_avr_ptr(rA(ctx->opcode));
rb = gen_avr_ptr(rB(ctx->opcode));
rd = gen_avr_ptr(rD(ctx->opcode));
- sh = tcg_const_i32(VSH(ctx->opcode));
+ sh = tcg_constant_i32(VSH(ctx->opcode));
gen_helper_vsldoi(rd, ra, rb, sh);
}
@@ -2575,7 +2575,7 @@ static void gen_##op(DisasContext *ctx) \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
\
- ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
+ ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \
\
gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
}
@@ -2594,7 +2594,7 @@ static void gen_##op(DisasContext *ctx) \
rb = gen_avr_ptr(rB(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
\
- ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
+ ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \
\
gen_helper_##op(cpu_crf[6], rd, rb, ps); \
}
@@ -2726,7 +2726,7 @@ static void gen_##op(DisasContext *ctx) \
} \
ra = gen_avr_ptr(rA(ctx->opcode)); \
rd = gen_avr_ptr(rD(ctx->opcode)); \
- st_six = tcg_const_i32(rB(ctx->opcode)); \
+ st_six = tcg_constant_i32(rB(ctx->opcode)); \
gen_helper_##op(rd, ra, st_six); \
}
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 16/25] target/ppc: Avoid tcg_const_* in xxeval
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (14 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 15/25] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 21:42 ` Daniel Henrique Barboza
2023-03-09 9:51 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 17/25] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Richard Henderson
` (8 subsequent siblings)
24 siblings, 2 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
Initialize a new temp instead of tcg_const_*.
Fix a pasto in a comment.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: Cédric Le Goater <clg@kaod.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Greg Kurz <groug@kaod.org>
Cc: qemu-ppc@nongnu.org
---
target/ppc/translate/vsx-impl.c.inc | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 6e63403727..9916784e64 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2449,7 +2449,8 @@ static void gen_xxeval_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c,
TCGv_i64 conj, disj;
conj = tcg_temp_new_i64();
- disj = tcg_const_i64(0);
+ disj = tcg_temp_new_i64();
+ tcg_gen_movi_i64(disj, 0);
/* Iterate over set bits from the least to the most significant bit */
while (imm) {
@@ -2492,8 +2493,9 @@ static void gen_xxeval_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
int bit;
TCGv_vec disj, conj;
- disj = tcg_const_zeros_vec_matching(t);
conj = tcg_temp_new_vec_matching(t);
+ disj = tcg_temp_new_vec_matching(t);
+ tcg_gen_dupi_vec(vece, disj, 0);
/* Iterate over set bits from the least to the most significant bit */
while (imm) {
@@ -2546,7 +2548,7 @@ static bool trans_XXEVAL(DisasContext *ctx, arg_8RR_XX4_imm *a)
/* Equivalent functions that can be implemented with a single gen_gvec */
switch (a->imm) {
- case 0b00000000: /* true */
+ case 0b00000000: /* false */
set_cpu_vsr(a->xt, tcg_constant_i64(0), true);
set_cpu_vsr(a->xt, tcg_constant_i64(0), false);
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 17/25] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (15 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 16/25] target/ppc: Avoid tcg_const_* in xxeval Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 21:42 ` Daniel Henrique Barboza
2023-03-09 9:52 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 18/25] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Richard Henderson
` (7 subsequent siblings)
24 siblings, 2 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
All remaining uses are strictly read-only.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: Cédric Le Goater <clg@kaod.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Greg Kurz <groug@kaod.org>
Cc: qemu-ppc@nongnu.org
---
target/ppc/translate/vsx-impl.c.inc | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 9916784e64..0f5b0056f1 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -154,7 +154,7 @@ static void gen_lxvdsx(DisasContext *ctx)
static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
TCGv_i64 inh, TCGv_i64 inl)
{
- TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF);
+ TCGv_i64 mask = tcg_constant_i64(0x00FF00FF00FF00FF);
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
@@ -825,7 +825,7 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_VSX(ctx);
- ro = tcg_const_i32(a->rc);
+ ro = tcg_constant_i32(a->rc);
xt = gen_avr_ptr(a->rt);
xb = gen_avr_ptr(a->rb);
@@ -860,7 +860,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
gen_helper_##name(cpu_env, opc); \
}
@@ -900,7 +900,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(xA(ctx->opcode)); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, opc, xa, xb); \
@@ -915,7 +915,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xb = gen_vsr_ptr(xB(ctx->opcode)); \
gen_helper_##name(cpu_env, opc, xb); \
}
@@ -929,7 +929,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
@@ -945,7 +945,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
gen_helper_##name(cpu_env, opc, xt, xb); \
@@ -960,7 +960,7 @@ static void gen_##name(DisasContext *ctx) \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- opc = tcg_const_i32(ctx->opcode); \
+ opc = tcg_constant_i32(ctx->opcode); \
xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
gen_helper_##name(cpu_env, opc, xa, xb); \
@@ -1994,8 +1994,8 @@ static void gen_xsxsigdp(DisasContext *ctx)
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
- zr = tcg_const_i64(0);
- nan = tcg_const_i64(2047);
+ zr = tcg_constant_i64(0);
+ nan = tcg_constant_i64(2047);
get_cpu_vsr(t1, xB(ctx->opcode), true);
tcg_gen_extract_i64(exp, t1, 52, 11);
@@ -2026,8 +2026,8 @@ static void gen_xsxsigqp(DisasContext *ctx)
get_cpu_vsr(xbl, rB(ctx->opcode) + 32, false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
- zr = tcg_const_i64(0);
- nan = tcg_const_i64(32767);
+ zr = tcg_constant_i64(0);
+ nan = tcg_constant_i64(32767);
tcg_gen_extract_i64(exp, xbh, 48, 15);
tcg_gen_movi_i64(t0, 0x0001000000000000);
@@ -2193,8 +2193,8 @@ static void gen_xvxsigdp(DisasContext *ctx)
get_cpu_vsr(xbl, xB(ctx->opcode), false);
exp = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
- zr = tcg_const_i64(0);
- nan = tcg_const_i64(2047);
+ zr = tcg_constant_i64(0);
+ nan = tcg_constant_i64(2047);
tcg_gen_extract_i64(exp, xbh, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 18/25] target/ppc: Avoid tcg_const_* in fp-impl.c.inc
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (16 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 17/25] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 21:43 ` Daniel Henrique Barboza
2023-03-09 9:54 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 19/25] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc Richard Henderson
` (6 subsequent siblings)
24 siblings, 2 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
All uses are strictly read-only.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: Cédric Le Goater <clg@kaod.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Greg Kurz <groug@kaod.org>
Cc: qemu-ppc@nongnu.org
---
target/ppc/translate/fp-impl.c.inc | 26 ++++++++++++--------------
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index d5d88e7d49..57d8437851 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -348,7 +348,7 @@ static void gen_fcmpo(DisasContext *ctx)
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
gen_reset_fpstatus();
- crf = tcg_const_i32(crfD(ctx->opcode));
+ crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode));
gen_helper_fcmpo(cpu_env, t0, t1, crf);
@@ -368,7 +368,7 @@ static void gen_fcmpu(DisasContext *ctx)
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
gen_reset_fpstatus();
- crf = tcg_const_i32(crfD(ctx->opcode));
+ crf = tcg_constant_i32(crfD(ctx->opcode));
get_fpr(t0, rA(ctx->opcode));
get_fpr(t1, rB(ctx->opcode));
gen_helper_fcmpu(cpu_env, t0, t1, crf);
@@ -541,7 +541,7 @@ static void gen_mcrfs(DisasContext *ctx)
tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr,
~((0xF << shift) & FP_EX_CLEAR_BITS));
/* FEX and VX need to be updated, so don't set fpscr directly */
- tmask = tcg_const_i32(1 << nibble);
+ tmask = tcg_constant_i32(1 << nibble);
gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
}
@@ -681,9 +681,7 @@ static void gen_mtfsb0(DisasContext *ctx)
crb = 31 - crbD(ctx->opcode);
gen_reset_fpstatus();
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
- TCGv_i32 t0;
- t0 = tcg_const_i32(crb);
- gen_helper_fpscr_clrbit(cpu_env, t0);
+ gen_helper_fpscr_clrbit(cpu_env, tcg_constant_i32(crb));
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
@@ -703,9 +701,7 @@ static void gen_mtfsb1(DisasContext *ctx)
crb = 31 - crbD(ctx->opcode);
/* XXX: we pretend we can only do IEEE floating-point computations */
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
- TCGv_i32 t0;
- t0 = tcg_const_i32(crb);
- gen_helper_fpscr_setbit(cpu_env, t0);
+ gen_helper_fpscr_setbit(cpu_env, tcg_constant_i32(crb));
}
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
@@ -733,10 +729,12 @@ static void gen_mtfsf(DisasContext *ctx)
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
return;
}
- if (l) {
- t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
+ if (!l) {
+ t0 = tcg_constant_i32(flm << (w * 8));
+ } else if (ctx->insns_flags2 & PPC2_ISA205) {
+ t0 = tcg_constant_i32(0xffff);
} else {
- t0 = tcg_const_i32(flm << (w * 8));
+ t0 = tcg_constant_i32(0xff);
}
t1 = tcg_temp_new_i64();
get_fpr(t1, rB(ctx->opcode));
@@ -767,8 +765,8 @@ static void gen_mtfsfi(DisasContext *ctx)
return;
}
sh = (8 * w) + 7 - bf;
- t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
- t1 = tcg_const_i32(1 << sh);
+ t0 = tcg_constant_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
+ t1 = tcg_constant_i32(1 << sh);
gen_helper_store_fpscr(cpu_env, t0, t1);
if (unlikely(Rc(ctx->opcode) != 0)) {
tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 19/25] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (17 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 18/25] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 21:43 ` Daniel Henrique Barboza
2023-03-09 9:54 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 20/25] target/ppc: Rewrite trans_ADDG6S Richard Henderson
` (5 subsequent siblings)
24 siblings, 2 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
All uses are strictly read-only.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: Cédric Le Goater <clg@kaod.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Greg Kurz <groug@kaod.org>
Cc: qemu-ppc@nongnu.org
---
target/ppc/power8-pmu-regs.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
index 42f2cd04a1..d900e13cad 100644
--- a/target/ppc/power8-pmu-regs.c.inc
+++ b/target/ppc/power8-pmu-regs.c.inc
@@ -177,7 +177,7 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn)
void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)
{
- TCGv_i32 t_sprn = tcg_const_i32(sprn);
+ TCGv_i32 t_sprn = tcg_constant_i32(sprn);
gen_icount_io_start(ctx);
gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn);
@@ -210,7 +210,7 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn)
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t_sprn = tcg_const_i32(sprn);
+ TCGv_i32 t_sprn = tcg_constant_i32(sprn);
gen_icount_io_start(ctx);
gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]);
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 20/25] target/ppc: Rewrite trans_ADDG6S
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (18 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 19/25] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 21:51 ` Daniel Henrique Barboza
2023-03-07 18:34 ` [PATCH v2 21/25] target/ppc: Fix gen_tlbsx_booke206 Richard Henderson
` (4 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
Compute all carry bits in parallel instead of a loop.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: Cédric Le Goater <clg@kaod.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Greg Kurz <groug@kaod.org>
Cc: qemu-ppc@nongnu.org
---
target/ppc/translate/fixedpoint-impl.c.inc | 44 +++++++++++-----------
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 20ea484c3d..02d86b77a8 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -484,33 +484,35 @@ static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
{
- const uint64_t carry_bits = 0x1111111111111111ULL;
- TCGv t0, t1, carry, zero = tcg_constant_tl(0);
+ const target_ulong carry_bits = (target_ulong)-1 / 0xf;
+ TCGv in1, in2, carryl, carryh, tmp;
+ TCGv zero = tcg_constant_tl(0);
REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
- t0 = tcg_temp_new();
- t1 = tcg_const_tl(0);
- carry = tcg_const_tl(0);
+ in1 = cpu_gpr[a->ra];
+ in2 = cpu_gpr[a->rb];
+ tmp = tcg_temp_new();
+ carryl = tcg_temp_new();
+ carryh = tcg_temp_new();
- for (int i = 0; i < 16; i++) {
- tcg_gen_shri_tl(t0, cpu_gpr[a->ra], i * 4);
- tcg_gen_andi_tl(t0, t0, 0xf);
- tcg_gen_add_tl(t1, t1, t0);
+ /* Addition with carry. */
+ tcg_gen_add2_tl(carryl, carryh, in1, zero, in2, zero);
+ /* Addition without carry. */
+ tcg_gen_xor_tl(tmp, in1, in2);
+ /* Difference between the two is carry in to each bit. */
+ tcg_gen_xor_tl(carryl, carryl, tmp);
- tcg_gen_shri_tl(t0, cpu_gpr[a->rb], i * 4);
- tcg_gen_andi_tl(t0, t0, 0xf);
- tcg_gen_add_tl(t1, t1, t0);
+ /*
+ * The carry-out that we're looking for is the carry-in to
+ * the next nibble. Shift the double-word down one nibble,
+ * which puts all of the bits back into one word.
+ */
+ tcg_gen_extract2_tl(carryl, carryl, carryh, 4);
- tcg_gen_andi_tl(t1, t1, 0x10);
- tcg_gen_setcond_tl(TCG_COND_NE, t1, t1, zero);
-
- tcg_gen_shli_tl(t0, t1, i * 4);
- tcg_gen_or_tl(carry, carry, t0);
- }
-
- tcg_gen_xori_tl(carry, carry, (target_long)carry_bits);
- tcg_gen_muli_tl(cpu_gpr[a->rt], carry, 6);
+ /* Invert, isolate the carry bits, and produce 6's. */
+ tcg_gen_andc_tl(carryl, tcg_constant_tl(carry_bits), carryl);
+ tcg_gen_muli_tl(cpu_gpr[a->rt], carryl, 6);
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 21/25] target/ppc: Fix gen_tlbsx_booke206
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (19 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 20/25] target/ppc: Rewrite trans_ADDG6S Richard Henderson
@ 2023-03-07 18:34 ` Richard Henderson
2023-03-07 21:44 ` Daniel Henrique Barboza
2023-03-07 18:35 ` [PATCH v2 22/25] target/ppc: Avoid tcg_const_* in translate.c Richard Henderson
` (3 subsequent siblings)
24 siblings, 1 reply; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:34 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
Fix incorrect read from rD.
Avoid adding 0 when rA == 0.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: Cédric Le Goater <clg@kaod.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Greg Kurz <groug@kaod.org>
Cc: qemu-ppc@nongnu.org
---
target/ppc/translate.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index df324fc7ff..7ec940b7d8 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5875,12 +5875,10 @@ static void gen_tlbsx_booke206(DisasContext *ctx)
CHK_SV(ctx);
if (rA(ctx->opcode)) {
t0 = tcg_temp_new();
- tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
+ tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
} else {
- t0 = tcg_const_tl(0);
+ t0 = cpu_gpr[rB(ctx->opcode)];
}
-
- tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
gen_helper_booke206_tlbsx(cpu_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 22/25] target/ppc: Avoid tcg_const_* in translate.c
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (20 preceding siblings ...)
2023-03-07 18:34 ` [PATCH v2 21/25] target/ppc: Fix gen_tlbsx_booke206 Richard Henderson
@ 2023-03-07 18:35 ` Richard Henderson
2023-03-07 21:44 ` Daniel Henrique Barboza
2023-03-09 10:02 ` Philippe Mathieu-Daudé
2023-03-07 18:35 ` [PATCH v2 23/25] target/tricore: Use min/max for saturate Richard Henderson
` (2 subsequent siblings)
24 siblings, 2 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:35 UTC (permalink / raw)
To: qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
All remaining uses are strictly read-only.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: Cédric Le Goater <clg@kaod.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: Greg Kurz <groug@kaod.org>
Cc: qemu-ppc@nongnu.org
---
target/ppc/translate.c | 142 +++++++++++++++++++++--------------------
1 file changed, 72 insertions(+), 70 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 7ec940b7d8..9d05357d03 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -263,8 +263,8 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
* faulting instruction
*/
gen_update_nip(ctx, ctx->cia);
- t0 = tcg_const_i32(excp);
- t1 = tcg_const_i32(error);
+ t0 = tcg_constant_i32(excp);
+ t1 = tcg_constant_i32(error);
gen_helper_raise_exception_err(cpu_env, t0, t1);
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -278,7 +278,7 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
* faulting instruction
*/
gen_update_nip(ctx, ctx->cia);
- t0 = tcg_const_i32(excp);
+ t0 = tcg_constant_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -289,7 +289,7 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
TCGv_i32 t0;
gen_update_nip(ctx, nip);
- t0 = tcg_const_i32(excp);
+ t0 = tcg_constant_i32(excp);
gen_helper_raise_exception(cpu_env, t0);
ctx->base.is_jmp = DISAS_NORETURN;
}
@@ -386,7 +386,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
static void spr_load_dump_spr(int sprn)
{
#ifdef PPC_DUMP_SPR_ACCESSES
- TCGv_i32 t0 = tcg_const_i32(sprn);
+ TCGv_i32 t0 = tcg_constant_i32(sprn);
gen_helper_load_dump_spr(cpu_env, t0);
#endif
}
@@ -400,7 +400,7 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
static void spr_store_dump_spr(int sprn)
{
#ifdef PPC_DUMP_SPR_ACCESSES
- TCGv_i32 t0 = tcg_const_i32(sprn);
+ TCGv_i32 t0 = tcg_constant_i32(sprn);
gen_helper_store_dump_spr(cpu_env, t0);
#endif
}
@@ -672,25 +672,25 @@ void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
+ TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2);
gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
+ TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4);
gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
+ TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2);
gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
+ TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4);
gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
}
@@ -712,25 +712,25 @@ void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
+ TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2);
gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
+ TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4);
gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
+ TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2);
gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
}
void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
+ TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4);
gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
}
@@ -1040,13 +1040,15 @@ void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
{
- TCGv_i32 t0 = tcg_const_i32(sprn);
+ TCGv_i32 t0 = tcg_constant_i32(sprn);
gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
}
+
void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
}
+
void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
@@ -1080,9 +1082,9 @@ void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
int bit, int sprn, int cause)
{
- TCGv_i32 t1 = tcg_const_i32(bit);
- TCGv_i32 t2 = tcg_const_i32(sprn);
- TCGv_i32 t3 = tcg_const_i32(cause);
+ TCGv_i32 t1 = tcg_constant_i32(bit);
+ TCGv_i32 t2 = tcg_constant_i32(sprn);
+ TCGv_i32 t3 = tcg_constant_i32(cause);
gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
}
@@ -1090,9 +1092,9 @@ static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
int bit, int sprn, int cause)
{
- TCGv_i32 t1 = tcg_const_i32(bit);
- TCGv_i32 t2 = tcg_const_i32(sprn);
- TCGv_i32 t3 = tcg_const_i32(cause);
+ TCGv_i32 t1 = tcg_constant_i32(bit);
+ TCGv_i32 t2 = tcg_constant_i32(sprn);
+ TCGv_i32 t3 = tcg_constant_i32(cause);
gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
}
@@ -1388,7 +1390,7 @@ static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
{
- TCGv t0 = tcg_const_tl(arg1);
+ TCGv t0 = tcg_constant_tl(arg1);
gen_op_cmp(arg0, t0, s, crf);
}
@@ -1409,7 +1411,7 @@ static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
{
- TCGv t0 = tcg_const_tl(arg1);
+ TCGv t0 = tcg_constant_tl(arg1);
gen_op_cmp32(arg0, t0, s, crf);
}
@@ -1476,7 +1478,7 @@ static void gen_isel(DisasContext *ctx)
tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
tcg_gen_andi_tl(t0, t0, mask);
- zr = tcg_const_tl(0);
+ zr = tcg_constant_tl(0);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
cpu_gpr[rB(ctx->opcode)]);
@@ -1568,7 +1570,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_mov_tl(ca32, ca);
}
} else {
- TCGv zero = tcg_const_tl(0);
+ TCGv zero = tcg_constant_tl(0);
if (add_ca) {
tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
@@ -1609,7 +1611,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
add_ca, compute_ca, compute_ov) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
- TCGv t0 = tcg_const_tl(const_val); \
+ TCGv t0 = tcg_constant_tl(const_val); \
gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
cpu_gpr[rA(ctx->opcode)], t0, \
ca, glue(ca, 32), \
@@ -1636,7 +1638,7 @@ GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
/* addic addic.*/
static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
{
- TCGv c = tcg_const_tl(SIMM(ctx->opcode));
+ TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
}
@@ -1709,7 +1711,7 @@ GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
#define GEN_DIVE(name, hlpr, compute_ov) \
static void gen_##name(DisasContext *ctx) \
{ \
- TCGv_i32 t0 = tcg_const_i32(compute_ov); \
+ TCGv_i32 t0 = tcg_constant_i32(compute_ov); \
gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
if (unlikely(Rc(ctx->opcode) != 0)) { \
@@ -1802,8 +1804,8 @@ static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_rem_i32(t3, t0, t1);
tcg_gen_ext_i32_tl(ret, t3);
} else {
- TCGv_i32 t2 = tcg_const_i32(1);
- TCGv_i32 t3 = tcg_const_i32(0);
+ TCGv_i32 t2 = tcg_constant_i32(1);
+ TCGv_i32 t3 = tcg_constant_i32(0);
tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
tcg_gen_remu_i32(t3, t0, t1);
tcg_gen_extu_i32_tl(ret, t3);
@@ -1842,8 +1844,8 @@ static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
tcg_gen_rem_i64(ret, t0, t1);
} else {
- TCGv_i64 t2 = tcg_const_i64(1);
- TCGv_i64 t3 = tcg_const_i64(0);
+ TCGv_i64 t2 = tcg_constant_i64(1);
+ TCGv_i64 t3 = tcg_constant_i64(0);
tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
tcg_gen_remu_i64(ret, t0, t1);
}
@@ -2038,7 +2040,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
} else if (add_ca) {
TCGv zero, inv1 = tcg_temp_new();
tcg_gen_not_tl(inv1, arg1);
- zero = tcg_const_tl(0);
+ zero = tcg_constant_tl(0);
tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
@@ -2083,7 +2085,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
add_ca, compute_ca, compute_ov) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
- TCGv t0 = tcg_const_tl(const_val); \
+ TCGv t0 = tcg_constant_tl(const_val); \
gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
cpu_gpr[rA(ctx->opcode)], t0, \
add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
@@ -2107,7 +2109,7 @@ GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
/* subfic */
static void gen_subfic(DisasContext *ctx)
{
- TCGv c = tcg_const_tl(SIMM(ctx->opcode));
+ TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
c, 0, 1, 0, 0);
}
@@ -2115,7 +2117,7 @@ static void gen_subfic(DisasContext *ctx)
/* neg neg. nego nego. */
static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
{
- TCGv zero = tcg_const_tl(0);
+ TCGv zero = tcg_constant_tl(0);
gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
zero, 0, 0, compute_ov, Rc(ctx->opcode));
}
@@ -2214,7 +2216,7 @@ GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
static void gen_pause(DisasContext *ctx)
{
- TCGv_i32 t0 = tcg_const_i32(0);
+ TCGv_i32 t0 = tcg_constant_i32(0);
tcg_gen_st_i32(t0, cpu_env,
-offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
@@ -3256,7 +3258,7 @@ static void gen_lmw(DisasContext *ctx)
}
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
- t1 = tcg_const_i32(rD(ctx->opcode));
+ t1 = tcg_constant_i32(rD(ctx->opcode));
gen_addr_imm_index(ctx, t0, 0);
gen_helper_lmw(cpu_env, t0, t1);
}
@@ -3273,7 +3275,7 @@ static void gen_stmw(DisasContext *ctx)
}
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
- t1 = tcg_const_i32(rS(ctx->opcode));
+ t1 = tcg_constant_i32(rS(ctx->opcode));
gen_addr_imm_index(ctx, t0, 0);
gen_helper_stmw(cpu_env, t0, t1);
}
@@ -3311,8 +3313,8 @@ static void gen_lswi(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
gen_addr_register(ctx, t0);
- t1 = tcg_const_i32(nb);
- t2 = tcg_const_i32(start);
+ t1 = tcg_constant_i32(nb);
+ t2 = tcg_constant_i32(start);
gen_helper_lsw(cpu_env, t0, t1, t2);
}
@@ -3329,9 +3331,9 @@ static void gen_lswx(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_INT);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- t1 = tcg_const_i32(rD(ctx->opcode));
- t2 = tcg_const_i32(rA(ctx->opcode));
- t3 = tcg_const_i32(rB(ctx->opcode));
+ t1 = tcg_constant_i32(rD(ctx->opcode));
+ t2 = tcg_constant_i32(rA(ctx->opcode));
+ t3 = tcg_constant_i32(rB(ctx->opcode));
gen_helper_lswx(cpu_env, t0, t1, t2, t3);
}
@@ -3352,8 +3354,8 @@ static void gen_stswi(DisasContext *ctx)
if (nb == 0) {
nb = 32;
}
- t1 = tcg_const_i32(nb);
- t2 = tcg_const_i32(rS(ctx->opcode));
+ t1 = tcg_constant_i32(nb);
+ t2 = tcg_constant_i32(rS(ctx->opcode));
gen_helper_stsw(cpu_env, t0, t1, t2);
}
@@ -3373,7 +3375,7 @@ static void gen_stswx(DisasContext *ctx)
t1 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t1, cpu_xer);
tcg_gen_andi_i32(t1, t1, 0x7F);
- t2 = tcg_const_i32(rS(ctx->opcode));
+ t2 = tcg_constant_i32(rS(ctx->opcode));
gen_helper_stsw(cpu_env, t0, t1, t2);
}
@@ -3943,7 +3945,7 @@ static void gen_wait(DisasContext *ctx)
* to occur.
*/
if (wc == 0) {
- TCGv_i32 t0 = tcg_const_i32(1);
+ TCGv_i32 t0 = tcg_constant_i32(1);
tcg_gen_st_i32(t0, cpu_env,
-offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
/* Stop translation, as the CPU is supposed to sleep from now */
@@ -3989,7 +3991,7 @@ static void gen_doze(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
- t = tcg_const_i32(PPC_PM_DOZE);
+ t = tcg_constant_i32(PPC_PM_DOZE);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@@ -4004,7 +4006,7 @@ static void gen_nap(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
- t = tcg_const_i32(PPC_PM_NAP);
+ t = tcg_constant_i32(PPC_PM_NAP);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@@ -4019,7 +4021,7 @@ static void gen_stop(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
- t = tcg_const_i32(PPC_PM_STOP);
+ t = tcg_constant_i32(PPC_PM_STOP);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@@ -4034,7 +4036,7 @@ static void gen_sleep(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
- t = tcg_const_i32(PPC_PM_SLEEP);
+ t = tcg_constant_i32(PPC_PM_SLEEP);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@@ -4049,7 +4051,7 @@ static void gen_rvwinkle(DisasContext *ctx)
TCGv_i32 t;
CHK_HV(ctx);
- t = tcg_const_i32(PPC_PM_RVWINKLE);
+ t = tcg_constant_i32(PPC_PM_RVWINKLE);
gen_helper_pminsn(cpu_env, t);
/* Stop translation, as the CPU is supposed to sleep from now */
gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
@@ -4506,7 +4508,7 @@ static void gen_tw(DisasContext *ctx)
if (check_unconditional_trap(ctx)) {
return;
}
- t0 = tcg_const_i32(TO(ctx->opcode));
+ t0 = tcg_constant_i32(TO(ctx->opcode));
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
}
@@ -4520,8 +4522,8 @@ static void gen_twi(DisasContext *ctx)
if (check_unconditional_trap(ctx)) {
return;
}
- t0 = tcg_const_tl(SIMM(ctx->opcode));
- t1 = tcg_const_i32(TO(ctx->opcode));
+ t0 = tcg_constant_tl(SIMM(ctx->opcode));
+ t1 = tcg_constant_i32(TO(ctx->opcode));
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
}
@@ -4534,7 +4536,7 @@ static void gen_td(DisasContext *ctx)
if (check_unconditional_trap(ctx)) {
return;
}
- t0 = tcg_const_i32(TO(ctx->opcode));
+ t0 = tcg_constant_i32(TO(ctx->opcode));
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
}
@@ -4548,8 +4550,8 @@ static void gen_tdi(DisasContext *ctx)
if (check_unconditional_trap(ctx)) {
return;
}
- t0 = tcg_const_tl(SIMM(ctx->opcode));
- t1 = tcg_const_i32(TO(ctx->opcode));
+ t0 = tcg_constant_tl(SIMM(ctx->opcode));
+ t1 = tcg_constant_i32(TO(ctx->opcode));
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
}
#endif
@@ -5026,7 +5028,7 @@ static void gen_dcbz(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_CACHE);
tcgv_addr = tcg_temp_new();
- tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
+ tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
gen_addr_reg_index(ctx, tcgv_addr);
gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
}
@@ -5039,7 +5041,7 @@ static void gen_dcbzep(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_CACHE);
tcgv_addr = tcg_temp_new();
- tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
+ tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
gen_addr_reg_index(ctx, tcgv_addr);
gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
}
@@ -5114,7 +5116,7 @@ static void gen_mfsr(DisasContext *ctx)
TCGv t0;
CHK_SV(ctx);
- t0 = tcg_const_tl(SR(ctx->opcode));
+ t0 = tcg_constant_tl(SR(ctx->opcode));
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5143,7 +5145,7 @@ static void gen_mtsr(DisasContext *ctx)
TCGv t0;
CHK_SV(ctx);
- t0 = tcg_const_tl(SR(ctx->opcode));
+ t0 = tcg_constant_tl(SR(ctx->opcode));
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5175,7 +5177,7 @@ static void gen_mfsr_64b(DisasContext *ctx)
TCGv t0;
CHK_SV(ctx);
- t0 = tcg_const_tl(SR(ctx->opcode));
+ t0 = tcg_constant_tl(SR(ctx->opcode));
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5204,7 +5206,7 @@ static void gen_mtsr_64b(DisasContext *ctx)
TCGv t0;
CHK_SV(ctx);
- t0 = tcg_const_tl(SR(ctx->opcode));
+ t0 = tcg_constant_tl(SR(ctx->opcode));
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5558,7 +5560,7 @@ static void gen_mfdcr(DisasContext *ctx)
TCGv dcrn;
CHK_SV(ctx);
- dcrn = tcg_const_tl(SPR(ctx->opcode));
+ dcrn = tcg_constant_tl(SPR(ctx->opcode));
gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5572,7 +5574,7 @@ static void gen_mtdcr(DisasContext *ctx)
TCGv dcrn;
CHK_SV(ctx);
- dcrn = tcg_const_tl(SPR(ctx->opcode));
+ dcrn = tcg_constant_tl(SPR(ctx->opcode));
gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5793,7 +5795,7 @@ static void gen_tlbre_440(DisasContext *ctx)
case 1:
case 2:
{
- TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
+ TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
t0, cpu_gpr[rA(ctx->opcode)]);
}
@@ -5839,7 +5841,7 @@ static void gen_tlbwe_440(DisasContext *ctx)
case 1:
case 2:
{
- TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
+ TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)]);
}
@@ -5981,7 +5983,7 @@ static void gen_wrteei(DisasContext *ctx)
/* dlmzb */
static void gen_dlmzb(DisasContext *ctx)
{
- TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
+ TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode));
gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 23/25] target/tricore: Use min/max for saturate
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (21 preceding siblings ...)
2023-03-07 18:35 ` [PATCH v2 22/25] target/ppc: Avoid tcg_const_* in translate.c Richard Henderson
@ 2023-03-07 18:35 ` Richard Henderson
2023-03-09 10:09 ` Philippe Mathieu-Daudé
2023-03-07 18:35 ` [PATCH v2 24/25] tcg: Drop tcg_const_*_vec Richard Henderson
2023-03-07 18:35 ` [PATCH v2 25/25] tcg: Drop tcg_const_* Richard Henderson
24 siblings, 1 reply; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Bastian Koppelmann
Use tcg_constant_i32 for the bounds.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 14 +++-----------
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index a3a5263a5d..2646cb3eb5 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -2443,21 +2443,13 @@ gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
{
- TCGv sat_neg = tcg_const_i32(low);
- TCGv temp = tcg_const_i32(up);
-
- /* sat_neg = (arg < low ) ? low : arg; */
- tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
-
- /* ret = (sat_neg > up ) ? up : sat_neg; */
- tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
+ tcg_gen_smax_tl(ret, arg, tcg_constant_i32(low));
+ tcg_gen_smin_tl(ret, ret, tcg_constant_i32(up));
}
static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
{
- TCGv temp = tcg_const_i32(up);
- /* sat_neg = (arg > up ) ? up : arg; */
- tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
+ tcg_gen_umin_tl(ret, arg, tcg_constant_i32(up));
}
static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 24/25] tcg: Drop tcg_const_*_vec
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (22 preceding siblings ...)
2023-03-07 18:35 ` [PATCH v2 23/25] target/tricore: Use min/max for saturate Richard Henderson
@ 2023-03-07 18:35 ` Richard Henderson
2023-03-07 18:35 ` [PATCH v2 25/25] tcg: Drop tcg_const_* Richard Henderson
24 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Replace with tcg_constant_vec*.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 4 ----
tcg/tcg-op-vec.c | 34 ++--------------------------------
tcg/i386/tcg-target.c.inc | 9 ++++-----
3 files changed, 6 insertions(+), 41 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 00c4fbe613..d620012c48 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -999,10 +999,6 @@ void tcg_optimize(TCGContext *s);
/* Allocate a new temporary and initialize it with a constant. */
TCGv_i32 tcg_const_i32(int32_t val);
TCGv_i64 tcg_const_i64(int64_t val);
-TCGv_vec tcg_const_zeros_vec(TCGType);
-TCGv_vec tcg_const_ones_vec(TCGType);
-TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
-TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
/*
* Locate or create a read-only temporary that is a constant.
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 0f023f42c6..aeeb2435cb 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -229,32 +229,6 @@ void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a)
}
}
-TCGv_vec tcg_const_zeros_vec(TCGType type)
-{
- TCGv_vec ret = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(MO_64, ret, 0);
- return ret;
-}
-
-TCGv_vec tcg_const_ones_vec(TCGType type)
-{
- TCGv_vec ret = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(MO_64, ret, -1);
- return ret;
-}
-
-TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec m)
-{
- TCGTemp *t = tcgv_vec_temp(m);
- return tcg_const_zeros_vec(t->base_type);
-}
-
-TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
-{
- TCGTemp *t = tcgv_vec_temp(m);
- return tcg_const_ones_vec(t->base_type);
-}
-
void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
{
TCGTemp *rt = tcgv_vec_temp(r);
@@ -431,9 +405,7 @@ void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL);
if (!TCG_TARGET_HAS_not_vec || !do_op2(vece, r, a, INDEX_op_not_vec)) {
- TCGv_vec t = tcg_const_ones_vec_matching(r);
- tcg_gen_xor_vec(0, r, a, t);
- tcg_temp_free_vec(t);
+ tcg_gen_xor_vec(0, r, a, tcg_constant_vec_matching(r, 0, -1));
}
tcg_swap_vecop_list(hold_list);
}
@@ -446,9 +418,7 @@ void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
hold_list = tcg_swap_vecop_list(NULL);
if (!TCG_TARGET_HAS_neg_vec || !do_op2(vece, r, a, INDEX_op_neg_vec)) {
- TCGv_vec t = tcg_const_zeros_vec_matching(r);
- tcg_gen_sub_vec(vece, r, t, a);
- tcg_temp_free_vec(t);
+ tcg_gen_sub_vec(vece, r, tcg_constant_vec_matching(r, vece, 0), a);
}
tcg_swap_vecop_list(hold_list);
}
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 4060a35cf6..4444eb9234 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -3651,6 +3651,7 @@ static void expand_vec_sari(TCGType type, unsigned vece,
break;
case MO_64:
+ t1 = tcg_temp_new_vec(type);
if (imm <= 32) {
/*
* We can emulate a small sign extend by performing an arithmetic
@@ -3659,24 +3660,22 @@ static void expand_vec_sari(TCGType type, unsigned vece,
* does not, so we have to bound the smaller shift -- we get the
* same result in the high half either way.
*/
- t1 = tcg_temp_new_vec(type);
tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31));
tcg_gen_shri_vec(MO_64, v0, v1, imm);
vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
tcgv_vec_arg(v0), tcgv_vec_arg(v0),
tcgv_vec_arg(t1), 0xaa);
- tcg_temp_free_vec(t1);
} else {
/* Otherwise we will need to use a compare vs 0 to produce
* the sign-extend, shift and merge.
*/
- t1 = tcg_const_zeros_vec(type);
- tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1, t1, v1);
+ tcg_gen_cmp_vec(TCG_COND_GT, MO_64, t1,
+ tcg_constant_vec(type, MO_64, 0), v1);
tcg_gen_shri_vec(MO_64, v0, v1, imm);
tcg_gen_shli_vec(MO_64, t1, t1, 64 - imm);
tcg_gen_or_vec(MO_64, v0, v0, t1);
- tcg_temp_free_vec(t1);
}
+ tcg_temp_free_vec(t1);
break;
default:
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v2 25/25] tcg: Drop tcg_const_*
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
` (23 preceding siblings ...)
2023-03-07 18:35 ` [PATCH v2 24/25] tcg: Drop tcg_const_*_vec Richard Henderson
@ 2023-03-07 18:35 ` Richard Henderson
24 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 18:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
These functions are no longer used.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op.h | 4 ----
include/tcg/tcg.h | 6 ------
tcg/tcg.c | 16 ----------------
3 files changed, 26 deletions(-)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 70856147c5..dff17c7072 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -1089,9 +1089,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_extract_tl tcg_gen_extract_i64
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
#define tcg_gen_extract2_tl tcg_gen_extract2_i64
-#define tcg_const_tl tcg_const_i64
#define tcg_constant_tl tcg_constant_i64
-#define tcg_const_local_tl tcg_const_local_i64
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
#define tcg_gen_add2_tl tcg_gen_add2_i64
#define tcg_gen_sub2_tl tcg_gen_sub2_i64
@@ -1205,9 +1203,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
#define tcg_gen_extract_tl tcg_gen_extract_i32
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
#define tcg_gen_extract2_tl tcg_gen_extract2_i32
-#define tcg_const_tl tcg_const_i32
#define tcg_constant_tl tcg_constant_i32
-#define tcg_const_local_tl tcg_const_local_i32
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
#define tcg_gen_add2_tl tcg_gen_add2_i32
#define tcg_gen_sub2_tl tcg_gen_sub2_i32
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index d620012c48..5cfaa53938 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -996,10 +996,6 @@ void tcg_remove_ops_after(TCGOp *op);
void tcg_optimize(TCGContext *s);
-/* Allocate a new temporary and initialize it with a constant. */
-TCGv_i32 tcg_const_i32(int32_t val);
-TCGv_i64 tcg_const_i64(int64_t val);
-
/*
* Locate or create a read-only temporary that is a constant.
* This kind of temporary need not be freed, but for convenience
@@ -1021,10 +1017,8 @@ TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val);
TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val);
#if UINTPTR_MAX == UINT32_MAX
-# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x)))
#else
-# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x)))
#endif
diff --git a/tcg/tcg.c b/tcg/tcg.c
index d2993826c8..bb52bc060b 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1445,22 +1445,6 @@ TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val)
return tcg_constant_vec(t->base_type, vece, val);
}
-TCGv_i32 tcg_const_i32(int32_t val)
-{
- TCGv_i32 t0;
- t0 = tcg_temp_new_i32();
- tcg_gen_movi_i32(t0, val);
- return t0;
-}
-
-TCGv_i64 tcg_const_i64(int64_t val)
-{
- TCGv_i64 t0;
- t0 = tcg_temp_new_i64();
- tcg_gen_movi_i64(t0, val);
- return t0;
-}
-
/* Return true if OP may appear in the opcode stream.
Test the runtime variable that controls each opcode. */
bool tcg_op_supported(TCGOpcode op)
--
2.34.1
^ permalink raw reply related [flat|nested] 51+ messages in thread
* Re: [PATCH v2 14/25] target/ppc: Avoid tcg_const_i64 in do_vcntmb
2023-03-07 18:34 ` [PATCH v2 14/25] target/ppc: Avoid tcg_const_i64 in do_vcntmb Richard Henderson
@ 2023-03-07 21:42 ` Daniel Henrique Barboza
2023-03-09 10:18 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Daniel Henrique Barboza @ 2023-03-07 21:42 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Cédric Le Goater, David Gibson, Greg Kurz, qemu-ppc
On 3/7/23 15:34, Richard Henderson wrote:
> Compute both partial results separately and accumulate
> at the end, instead of accumulating in the middle.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate/vmx-impl.c.inc | 21 +++++++++++----------
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
> index 7af6d7217d..ca27c11d87 100644
> --- a/target/ppc/translate/vmx-impl.c.inc
> +++ b/target/ppc/translate/vmx-impl.c.inc
> @@ -2236,24 +2236,25 @@ static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)
>
> static bool do_vcntmb(DisasContext *ctx, arg_VX_mp *a, int vece)
> {
> - TCGv_i64 rt, vrb, mask;
> - rt = tcg_const_i64(0);
> - vrb = tcg_temp_new_i64();
> + TCGv_i64 r[2], mask;
> +
> + r[0] = tcg_temp_new_i64();
> + r[1] = tcg_temp_new_i64();
> mask = tcg_constant_i64(dup_const(vece, 1ULL << ((8 << vece) - 1)));
>
> for (int i = 0; i < 2; i++) {
> - get_avr64(vrb, a->vrb, i);
> + get_avr64(r[i], a->vrb, i);
> if (a->mp) {
> - tcg_gen_and_i64(vrb, mask, vrb);
> + tcg_gen_and_i64(r[i], mask, r[i]);
> } else {
> - tcg_gen_andc_i64(vrb, mask, vrb);
> + tcg_gen_andc_i64(r[i], mask, r[i]);
> }
> - tcg_gen_ctpop_i64(vrb, vrb);
> - tcg_gen_add_i64(rt, rt, vrb);
> + tcg_gen_ctpop_i64(r[i], r[i]);
> }
>
> - tcg_gen_shli_i64(rt, rt, TARGET_LONG_BITS - 8 + vece);
> - tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], rt);
> + tcg_gen_add_i64(r[0], r[0], r[1]);
> + tcg_gen_shli_i64(r[0], r[0], TARGET_LONG_BITS - 8 + vece);
> + tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], r[0]);
> return true;
> }
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 15/25] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
2023-03-07 18:34 ` [PATCH v2 15/25] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc Richard Henderson
@ 2023-03-07 21:42 ` Daniel Henrique Barboza
2023-03-09 9:49 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Daniel Henrique Barboza @ 2023-03-07 21:42 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Cédric Le Goater, David Gibson, Greg Kurz, qemu-ppc
On 3/7/23 15:34, Richard Henderson wrote:
> All remaining uses are strictly read-only.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate/vmx-impl.c.inc | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
> index ca27c11d87..112233b541 100644
> --- a/target/ppc/translate/vmx-impl.c.inc
> +++ b/target/ppc/translate/vmx-impl.c.inc
> @@ -1624,7 +1624,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
> gen_exception(ctx, POWERPC_EXCP_VPU); \
> return; \
> } \
> - uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
> + uimm = tcg_constant_i32(UIMM5(ctx->opcode)); \
> rb = gen_avr_ptr(rB(ctx->opcode)); \
> rd = gen_avr_ptr(rD(ctx->opcode)); \
> gen_helper_##name(cpu_env, rd, rb, uimm); \
> @@ -1965,7 +1965,7 @@ static void gen_vsldoi(DisasContext *ctx)
> ra = gen_avr_ptr(rA(ctx->opcode));
> rb = gen_avr_ptr(rB(ctx->opcode));
> rd = gen_avr_ptr(rD(ctx->opcode));
> - sh = tcg_const_i32(VSH(ctx->opcode));
> + sh = tcg_constant_i32(VSH(ctx->opcode));
> gen_helper_vsldoi(rd, ra, rb, sh);
> }
>
> @@ -2575,7 +2575,7 @@ static void gen_##op(DisasContext *ctx) \
> rb = gen_avr_ptr(rB(ctx->opcode)); \
> rd = gen_avr_ptr(rD(ctx->opcode)); \
> \
> - ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
> + ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \
> \
> gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
> }
> @@ -2594,7 +2594,7 @@ static void gen_##op(DisasContext *ctx) \
> rb = gen_avr_ptr(rB(ctx->opcode)); \
> rd = gen_avr_ptr(rD(ctx->opcode)); \
> \
> - ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
> + ps = tcg_constant_i32((ctx->opcode & 0x200) != 0); \
> \
> gen_helper_##op(cpu_crf[6], rd, rb, ps); \
> }
> @@ -2726,7 +2726,7 @@ static void gen_##op(DisasContext *ctx) \
> } \
> ra = gen_avr_ptr(rA(ctx->opcode)); \
> rd = gen_avr_ptr(rD(ctx->opcode)); \
> - st_six = tcg_const_i32(rB(ctx->opcode)); \
> + st_six = tcg_constant_i32(rB(ctx->opcode)); \
> gen_helper_##op(rd, ra, st_six); \
> }
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 16/25] target/ppc: Avoid tcg_const_* in xxeval
2023-03-07 18:34 ` [PATCH v2 16/25] target/ppc: Avoid tcg_const_* in xxeval Richard Henderson
@ 2023-03-07 21:42 ` Daniel Henrique Barboza
2023-03-09 9:51 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Daniel Henrique Barboza @ 2023-03-07 21:42 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Cédric Le Goater, David Gibson, Greg Kurz, qemu-ppc
On 3/7/23 15:34, Richard Henderson wrote:
> Initialize a new temp instead of tcg_const_*.
> Fix a pasto in a comment.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate/vsx-impl.c.inc | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
> index 6e63403727..9916784e64 100644
> --- a/target/ppc/translate/vsx-impl.c.inc
> +++ b/target/ppc/translate/vsx-impl.c.inc
> @@ -2449,7 +2449,8 @@ static void gen_xxeval_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c,
> TCGv_i64 conj, disj;
>
> conj = tcg_temp_new_i64();
> - disj = tcg_const_i64(0);
> + disj = tcg_temp_new_i64();
> + tcg_gen_movi_i64(disj, 0);
>
> /* Iterate over set bits from the least to the most significant bit */
> while (imm) {
> @@ -2492,8 +2493,9 @@ static void gen_xxeval_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
> int bit;
> TCGv_vec disj, conj;
>
> - disj = tcg_const_zeros_vec_matching(t);
> conj = tcg_temp_new_vec_matching(t);
> + disj = tcg_temp_new_vec_matching(t);
> + tcg_gen_dupi_vec(vece, disj, 0);
>
> /* Iterate over set bits from the least to the most significant bit */
> while (imm) {
> @@ -2546,7 +2548,7 @@ static bool trans_XXEVAL(DisasContext *ctx, arg_8RR_XX4_imm *a)
>
> /* Equivalent functions that can be implemented with a single gen_gvec */
> switch (a->imm) {
> - case 0b00000000: /* true */
> + case 0b00000000: /* false */
> set_cpu_vsr(a->xt, tcg_constant_i64(0), true);
> set_cpu_vsr(a->xt, tcg_constant_i64(0), false);
> break;
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 17/25] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
2023-03-07 18:34 ` [PATCH v2 17/25] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Richard Henderson
@ 2023-03-07 21:42 ` Daniel Henrique Barboza
2023-03-09 9:52 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Daniel Henrique Barboza @ 2023-03-07 21:42 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Cédric Le Goater, David Gibson, Greg Kurz, qemu-ppc
On 3/7/23 15:34, Richard Henderson wrote:
> All remaining uses are strictly read-only.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate/vsx-impl.c.inc | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
> index 9916784e64..0f5b0056f1 100644
> --- a/target/ppc/translate/vsx-impl.c.inc
> +++ b/target/ppc/translate/vsx-impl.c.inc
> @@ -154,7 +154,7 @@ static void gen_lxvdsx(DisasContext *ctx)
> static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
> TCGv_i64 inh, TCGv_i64 inl)
> {
> - TCGv_i64 mask = tcg_const_i64(0x00FF00FF00FF00FF);
> + TCGv_i64 mask = tcg_constant_i64(0x00FF00FF00FF00FF);
> TCGv_i64 t0 = tcg_temp_new_i64();
> TCGv_i64 t1 = tcg_temp_new_i64();
>
> @@ -825,7 +825,7 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
> REQUIRE_INSNS_FLAGS2(ctx, ISA300);
> REQUIRE_VSX(ctx);
>
> - ro = tcg_const_i32(a->rc);
> + ro = tcg_constant_i32(a->rc);
>
> xt = gen_avr_ptr(a->rt);
> xb = gen_avr_ptr(a->rb);
> @@ -860,7 +860,7 @@ static void gen_##name(DisasContext *ctx) \
> gen_exception(ctx, POWERPC_EXCP_VSXU); \
> return; \
> } \
> - opc = tcg_const_i32(ctx->opcode); \
> + opc = tcg_constant_i32(ctx->opcode); \
> gen_helper_##name(cpu_env, opc); \
> }
>
> @@ -900,7 +900,7 @@ static void gen_##name(DisasContext *ctx) \
> gen_exception(ctx, POWERPC_EXCP_VSXU); \
> return; \
> } \
> - opc = tcg_const_i32(ctx->opcode); \
> + opc = tcg_constant_i32(ctx->opcode); \
> xa = gen_vsr_ptr(xA(ctx->opcode)); \
> xb = gen_vsr_ptr(xB(ctx->opcode)); \
> gen_helper_##name(cpu_env, opc, xa, xb); \
> @@ -915,7 +915,7 @@ static void gen_##name(DisasContext *ctx) \
> gen_exception(ctx, POWERPC_EXCP_VSXU); \
> return; \
> } \
> - opc = tcg_const_i32(ctx->opcode); \
> + opc = tcg_constant_i32(ctx->opcode); \
> xb = gen_vsr_ptr(xB(ctx->opcode)); \
> gen_helper_##name(cpu_env, opc, xb); \
> }
> @@ -929,7 +929,7 @@ static void gen_##name(DisasContext *ctx) \
> gen_exception(ctx, POWERPC_EXCP_VSXU); \
> return; \
> } \
> - opc = tcg_const_i32(ctx->opcode); \
> + opc = tcg_constant_i32(ctx->opcode); \
> xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
> xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
> xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
> @@ -945,7 +945,7 @@ static void gen_##name(DisasContext *ctx) \
> gen_exception(ctx, POWERPC_EXCP_VSXU); \
> return; \
> } \
> - opc = tcg_const_i32(ctx->opcode); \
> + opc = tcg_constant_i32(ctx->opcode); \
> xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \
> xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
> gen_helper_##name(cpu_env, opc, xt, xb); \
> @@ -960,7 +960,7 @@ static void gen_##name(DisasContext *ctx) \
> gen_exception(ctx, POWERPC_EXCP_VSXU); \
> return; \
> } \
> - opc = tcg_const_i32(ctx->opcode); \
> + opc = tcg_constant_i32(ctx->opcode); \
> xa = gen_vsr_ptr(rA(ctx->opcode) + 32); \
> xb = gen_vsr_ptr(rB(ctx->opcode) + 32); \
> gen_helper_##name(cpu_env, opc, xa, xb); \
> @@ -1994,8 +1994,8 @@ static void gen_xsxsigdp(DisasContext *ctx)
> exp = tcg_temp_new_i64();
> t0 = tcg_temp_new_i64();
> t1 = tcg_temp_new_i64();
> - zr = tcg_const_i64(0);
> - nan = tcg_const_i64(2047);
> + zr = tcg_constant_i64(0);
> + nan = tcg_constant_i64(2047);
>
> get_cpu_vsr(t1, xB(ctx->opcode), true);
> tcg_gen_extract_i64(exp, t1, 52, 11);
> @@ -2026,8 +2026,8 @@ static void gen_xsxsigqp(DisasContext *ctx)
> get_cpu_vsr(xbl, rB(ctx->opcode) + 32, false);
> exp = tcg_temp_new_i64();
> t0 = tcg_temp_new_i64();
> - zr = tcg_const_i64(0);
> - nan = tcg_const_i64(32767);
> + zr = tcg_constant_i64(0);
> + nan = tcg_constant_i64(32767);
>
> tcg_gen_extract_i64(exp, xbh, 48, 15);
> tcg_gen_movi_i64(t0, 0x0001000000000000);
> @@ -2193,8 +2193,8 @@ static void gen_xvxsigdp(DisasContext *ctx)
> get_cpu_vsr(xbl, xB(ctx->opcode), false);
> exp = tcg_temp_new_i64();
> t0 = tcg_temp_new_i64();
> - zr = tcg_const_i64(0);
> - nan = tcg_const_i64(2047);
> + zr = tcg_constant_i64(0);
> + nan = tcg_constant_i64(2047);
>
> tcg_gen_extract_i64(exp, xbh, 52, 11);
> tcg_gen_movi_i64(t0, 0x0010000000000000);
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 18/25] target/ppc: Avoid tcg_const_* in fp-impl.c.inc
2023-03-07 18:34 ` [PATCH v2 18/25] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Richard Henderson
@ 2023-03-07 21:43 ` Daniel Henrique Barboza
2023-03-09 9:54 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Daniel Henrique Barboza @ 2023-03-07 21:43 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Cédric Le Goater, David Gibson, Greg Kurz, qemu-ppc
On 3/7/23 15:34, Richard Henderson wrote:
> All uses are strictly read-only.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate/fp-impl.c.inc | 26 ++++++++++++--------------
> 1 file changed, 12 insertions(+), 14 deletions(-)
>
> diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
> index d5d88e7d49..57d8437851 100644
> --- a/target/ppc/translate/fp-impl.c.inc
> +++ b/target/ppc/translate/fp-impl.c.inc
> @@ -348,7 +348,7 @@ static void gen_fcmpo(DisasContext *ctx)
> t0 = tcg_temp_new_i64();
> t1 = tcg_temp_new_i64();
> gen_reset_fpstatus();
> - crf = tcg_const_i32(crfD(ctx->opcode));
> + crf = tcg_constant_i32(crfD(ctx->opcode));
> get_fpr(t0, rA(ctx->opcode));
> get_fpr(t1, rB(ctx->opcode));
> gen_helper_fcmpo(cpu_env, t0, t1, crf);
> @@ -368,7 +368,7 @@ static void gen_fcmpu(DisasContext *ctx)
> t0 = tcg_temp_new_i64();
> t1 = tcg_temp_new_i64();
> gen_reset_fpstatus();
> - crf = tcg_const_i32(crfD(ctx->opcode));
> + crf = tcg_constant_i32(crfD(ctx->opcode));
> get_fpr(t0, rA(ctx->opcode));
> get_fpr(t1, rB(ctx->opcode));
> gen_helper_fcmpu(cpu_env, t0, t1, crf);
> @@ -541,7 +541,7 @@ static void gen_mcrfs(DisasContext *ctx)
> tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr,
> ~((0xF << shift) & FP_EX_CLEAR_BITS));
> /* FEX and VX need to be updated, so don't set fpscr directly */
> - tmask = tcg_const_i32(1 << nibble);
> + tmask = tcg_constant_i32(1 << nibble);
> gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
> }
>
> @@ -681,9 +681,7 @@ static void gen_mtfsb0(DisasContext *ctx)
> crb = 31 - crbD(ctx->opcode);
> gen_reset_fpstatus();
> if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
> - TCGv_i32 t0;
> - t0 = tcg_const_i32(crb);
> - gen_helper_fpscr_clrbit(cpu_env, t0);
> + gen_helper_fpscr_clrbit(cpu_env, tcg_constant_i32(crb));
> }
> if (unlikely(Rc(ctx->opcode) != 0)) {
> tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
> @@ -703,9 +701,7 @@ static void gen_mtfsb1(DisasContext *ctx)
> crb = 31 - crbD(ctx->opcode);
> /* XXX: we pretend we can only do IEEE floating-point computations */
> if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
> - TCGv_i32 t0;
> - t0 = tcg_const_i32(crb);
> - gen_helper_fpscr_setbit(cpu_env, t0);
> + gen_helper_fpscr_setbit(cpu_env, tcg_constant_i32(crb));
> }
> if (unlikely(Rc(ctx->opcode) != 0)) {
> tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
> @@ -733,10 +729,12 @@ static void gen_mtfsf(DisasContext *ctx)
> gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
> return;
> }
> - if (l) {
> - t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
> + if (!l) {
> + t0 = tcg_constant_i32(flm << (w * 8));
> + } else if (ctx->insns_flags2 & PPC2_ISA205) {
> + t0 = tcg_constant_i32(0xffff);
> } else {
> - t0 = tcg_const_i32(flm << (w * 8));
> + t0 = tcg_constant_i32(0xff);
> }
> t1 = tcg_temp_new_i64();
> get_fpr(t1, rB(ctx->opcode));
> @@ -767,8 +765,8 @@ static void gen_mtfsfi(DisasContext *ctx)
> return;
> }
> sh = (8 * w) + 7 - bf;
> - t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
> - t1 = tcg_const_i32(1 << sh);
> + t0 = tcg_constant_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
> + t1 = tcg_constant_i32(1 << sh);
> gen_helper_store_fpscr(cpu_env, t0, t1);
> if (unlikely(Rc(ctx->opcode) != 0)) {
> tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 19/25] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
2023-03-07 18:34 ` [PATCH v2 19/25] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc Richard Henderson
@ 2023-03-07 21:43 ` Daniel Henrique Barboza
2023-03-09 9:54 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Daniel Henrique Barboza @ 2023-03-07 21:43 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Cédric Le Goater, David Gibson, Greg Kurz, qemu-ppc
On 3/7/23 15:34, Richard Henderson wrote:
> All uses are strictly read-only.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/power8-pmu-regs.c.inc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
> index 42f2cd04a1..d900e13cad 100644
> --- a/target/ppc/power8-pmu-regs.c.inc
> +++ b/target/ppc/power8-pmu-regs.c.inc
> @@ -177,7 +177,7 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn, int gprn)
>
> void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)
> {
> - TCGv_i32 t_sprn = tcg_const_i32(sprn);
> + TCGv_i32 t_sprn = tcg_constant_i32(sprn);
>
> gen_icount_io_start(ctx);
> gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn);
> @@ -210,7 +210,7 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn)
>
> void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
> {
> - TCGv_i32 t_sprn = tcg_const_i32(sprn);
> + TCGv_i32 t_sprn = tcg_constant_i32(sprn);
>
> gen_icount_io_start(ctx);
> gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]);
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 22/25] target/ppc: Avoid tcg_const_* in translate.c
2023-03-07 18:35 ` [PATCH v2 22/25] target/ppc: Avoid tcg_const_* in translate.c Richard Henderson
@ 2023-03-07 21:44 ` Daniel Henrique Barboza
2023-03-09 10:02 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Daniel Henrique Barboza @ 2023-03-07 21:44 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Cédric Le Goater, David Gibson, Greg Kurz, qemu-ppc
On 3/7/23 15:35, Richard Henderson wrote:
> All remaining uses are strictly read-only.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate.c | 142 +++++++++++++++++++++--------------------
> 1 file changed, 72 insertions(+), 70 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 7ec940b7d8..9d05357d03 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -263,8 +263,8 @@ static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
> * faulting instruction
> */
> gen_update_nip(ctx, ctx->cia);
> - t0 = tcg_const_i32(excp);
> - t1 = tcg_const_i32(error);
> + t0 = tcg_constant_i32(excp);
> + t1 = tcg_constant_i32(error);
> gen_helper_raise_exception_err(cpu_env, t0, t1);
> ctx->base.is_jmp = DISAS_NORETURN;
> }
> @@ -278,7 +278,7 @@ static void gen_exception(DisasContext *ctx, uint32_t excp)
> * faulting instruction
> */
> gen_update_nip(ctx, ctx->cia);
> - t0 = tcg_const_i32(excp);
> + t0 = tcg_constant_i32(excp);
> gen_helper_raise_exception(cpu_env, t0);
> ctx->base.is_jmp = DISAS_NORETURN;
> }
> @@ -289,7 +289,7 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
> TCGv_i32 t0;
>
> gen_update_nip(ctx, nip);
> - t0 = tcg_const_i32(excp);
> + t0 = tcg_constant_i32(excp);
> gen_helper_raise_exception(cpu_env, t0);
> ctx->base.is_jmp = DISAS_NORETURN;
> }
> @@ -386,7 +386,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
> static void spr_load_dump_spr(int sprn)
> {
> #ifdef PPC_DUMP_SPR_ACCESSES
> - TCGv_i32 t0 = tcg_const_i32(sprn);
> + TCGv_i32 t0 = tcg_constant_i32(sprn);
> gen_helper_load_dump_spr(cpu_env, t0);
> #endif
> }
> @@ -400,7 +400,7 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
> static void spr_store_dump_spr(int sprn)
> {
> #ifdef PPC_DUMP_SPR_ACCESSES
> - TCGv_i32 t0 = tcg_const_i32(sprn);
> + TCGv_i32 t0 = tcg_constant_i32(sprn);
> gen_helper_store_dump_spr(cpu_env, t0);
> #endif
> }
> @@ -672,25 +672,25 @@ void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
>
> void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
> {
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
> + TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0U) / 2);
> gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
> }
>
> void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
> {
> - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
> + TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4);
> gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
> }
>
> void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
> {
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
> + TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_IBAT0L) / 2);
> gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
> }
>
> void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
> {
> - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
> + TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4);
> gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
> }
>
> @@ -712,25 +712,25 @@ void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
>
> void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
> {
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
> + TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0U) / 2);
> gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
> }
>
> void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
> {
> - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
> + TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4);
> gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
> }
>
> void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
> {
> - TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
> + TCGv_i32 t0 = tcg_constant_i32((sprn - SPR_DBAT0L) / 2);
> gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
> }
>
> void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
> {
> - TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
> + TCGv_i32 t0 = tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4);
> gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
> }
>
> @@ -1040,13 +1040,15 @@ void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
>
> void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
> {
> - TCGv_i32 t0 = tcg_const_i32(sprn);
> + TCGv_i32 t0 = tcg_constant_i32(sprn);
> gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
> }
> +
> void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
> {
> gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
> }
> +
> void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
> {
> gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
> @@ -1080,9 +1082,9 @@ void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
> static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
> int bit, int sprn, int cause)
> {
> - TCGv_i32 t1 = tcg_const_i32(bit);
> - TCGv_i32 t2 = tcg_const_i32(sprn);
> - TCGv_i32 t3 = tcg_const_i32(cause);
> + TCGv_i32 t1 = tcg_constant_i32(bit);
> + TCGv_i32 t2 = tcg_constant_i32(sprn);
> + TCGv_i32 t3 = tcg_constant_i32(cause);
>
> gen_helper_fscr_facility_check(cpu_env, t1, t2, t3);
> }
> @@ -1090,9 +1092,9 @@ static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
> static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn,
> int bit, int sprn, int cause)
> {
> - TCGv_i32 t1 = tcg_const_i32(bit);
> - TCGv_i32 t2 = tcg_const_i32(sprn);
> - TCGv_i32 t3 = tcg_const_i32(cause);
> + TCGv_i32 t1 = tcg_constant_i32(bit);
> + TCGv_i32 t2 = tcg_constant_i32(sprn);
> + TCGv_i32 t3 = tcg_constant_i32(cause);
>
> gen_helper_msr_facility_check(cpu_env, t1, t2, t3);
> }
> @@ -1388,7 +1390,7 @@ static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
>
> static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
> {
> - TCGv t0 = tcg_const_tl(arg1);
> + TCGv t0 = tcg_constant_tl(arg1);
> gen_op_cmp(arg0, t0, s, crf);
> }
>
> @@ -1409,7 +1411,7 @@ static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
>
> static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
> {
> - TCGv t0 = tcg_const_tl(arg1);
> + TCGv t0 = tcg_constant_tl(arg1);
> gen_op_cmp32(arg0, t0, s, crf);
> }
>
> @@ -1476,7 +1478,7 @@ static void gen_isel(DisasContext *ctx)
> tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
> tcg_gen_andi_tl(t0, t0, mask);
>
> - zr = tcg_const_tl(0);
> + zr = tcg_constant_tl(0);
> tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
> rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
> cpu_gpr[rB(ctx->opcode)]);
> @@ -1568,7 +1570,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
> tcg_gen_mov_tl(ca32, ca);
> }
> } else {
> - TCGv zero = tcg_const_tl(0);
> + TCGv zero = tcg_constant_tl(0);
> if (add_ca) {
> tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
> tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
> @@ -1609,7 +1611,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
> add_ca, compute_ca, compute_ov) \
> static void glue(gen_, name)(DisasContext *ctx) \
> { \
> - TCGv t0 = tcg_const_tl(const_val); \
> + TCGv t0 = tcg_constant_tl(const_val); \
> gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
> cpu_gpr[rA(ctx->opcode)], t0, \
> ca, glue(ca, 32), \
> @@ -1636,7 +1638,7 @@ GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1)
> /* addic addic.*/
> static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
> {
> - TCGv c = tcg_const_tl(SIMM(ctx->opcode));
> + TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
> gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
> c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0);
> }
> @@ -1709,7 +1711,7 @@ GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
> #define GEN_DIVE(name, hlpr, compute_ov) \
> static void gen_##name(DisasContext *ctx) \
> { \
> - TCGv_i32 t0 = tcg_const_i32(compute_ov); \
> + TCGv_i32 t0 = tcg_constant_i32(compute_ov); \
> gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
> cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
> if (unlikely(Rc(ctx->opcode) != 0)) { \
> @@ -1802,8 +1804,8 @@ static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
> tcg_gen_rem_i32(t3, t0, t1);
> tcg_gen_ext_i32_tl(ret, t3);
> } else {
> - TCGv_i32 t2 = tcg_const_i32(1);
> - TCGv_i32 t3 = tcg_const_i32(0);
> + TCGv_i32 t2 = tcg_constant_i32(1);
> + TCGv_i32 t3 = tcg_constant_i32(0);
> tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1);
> tcg_gen_remu_i32(t3, t0, t1);
> tcg_gen_extu_i32_tl(ret, t3);
> @@ -1842,8 +1844,8 @@ static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1,
> tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1);
> tcg_gen_rem_i64(ret, t0, t1);
> } else {
> - TCGv_i64 t2 = tcg_const_i64(1);
> - TCGv_i64 t3 = tcg_const_i64(0);
> + TCGv_i64 t2 = tcg_constant_i64(1);
> + TCGv_i64 t3 = tcg_constant_i64(0);
> tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1);
> tcg_gen_remu_i64(ret, t0, t1);
> }
> @@ -2038,7 +2040,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
> } else if (add_ca) {
> TCGv zero, inv1 = tcg_temp_new();
> tcg_gen_not_tl(inv1, arg1);
> - zero = tcg_const_tl(0);
> + zero = tcg_constant_tl(0);
> tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
> tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
> gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
> @@ -2083,7 +2085,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
> add_ca, compute_ca, compute_ov) \
> static void glue(gen_, name)(DisasContext *ctx) \
> { \
> - TCGv t0 = tcg_const_tl(const_val); \
> + TCGv t0 = tcg_constant_tl(const_val); \
> gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
> cpu_gpr[rA(ctx->opcode)], t0, \
> add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
> @@ -2107,7 +2109,7 @@ GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
> /* subfic */
> static void gen_subfic(DisasContext *ctx)
> {
> - TCGv c = tcg_const_tl(SIMM(ctx->opcode));
> + TCGv c = tcg_constant_tl(SIMM(ctx->opcode));
> gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
> c, 0, 1, 0, 0);
> }
> @@ -2115,7 +2117,7 @@ static void gen_subfic(DisasContext *ctx)
> /* neg neg. nego nego. */
> static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
> {
> - TCGv zero = tcg_const_tl(0);
> + TCGv zero = tcg_constant_tl(0);
> gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
> zero, 0, 0, compute_ov, Rc(ctx->opcode));
> }
> @@ -2214,7 +2216,7 @@ GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
> #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> static void gen_pause(DisasContext *ctx)
> {
> - TCGv_i32 t0 = tcg_const_i32(0);
> + TCGv_i32 t0 = tcg_constant_i32(0);
> tcg_gen_st_i32(t0, cpu_env,
> -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
>
> @@ -3256,7 +3258,7 @@ static void gen_lmw(DisasContext *ctx)
> }
> gen_set_access_type(ctx, ACCESS_INT);
> t0 = tcg_temp_new();
> - t1 = tcg_const_i32(rD(ctx->opcode));
> + t1 = tcg_constant_i32(rD(ctx->opcode));
> gen_addr_imm_index(ctx, t0, 0);
> gen_helper_lmw(cpu_env, t0, t1);
> }
> @@ -3273,7 +3275,7 @@ static void gen_stmw(DisasContext *ctx)
> }
> gen_set_access_type(ctx, ACCESS_INT);
> t0 = tcg_temp_new();
> - t1 = tcg_const_i32(rS(ctx->opcode));
> + t1 = tcg_constant_i32(rS(ctx->opcode));
> gen_addr_imm_index(ctx, t0, 0);
> gen_helper_stmw(cpu_env, t0, t1);
> }
> @@ -3311,8 +3313,8 @@ static void gen_lswi(DisasContext *ctx)
> gen_set_access_type(ctx, ACCESS_INT);
> t0 = tcg_temp_new();
> gen_addr_register(ctx, t0);
> - t1 = tcg_const_i32(nb);
> - t2 = tcg_const_i32(start);
> + t1 = tcg_constant_i32(nb);
> + t2 = tcg_constant_i32(start);
> gen_helper_lsw(cpu_env, t0, t1, t2);
> }
>
> @@ -3329,9 +3331,9 @@ static void gen_lswx(DisasContext *ctx)
> gen_set_access_type(ctx, ACCESS_INT);
> t0 = tcg_temp_new();
> gen_addr_reg_index(ctx, t0);
> - t1 = tcg_const_i32(rD(ctx->opcode));
> - t2 = tcg_const_i32(rA(ctx->opcode));
> - t3 = tcg_const_i32(rB(ctx->opcode));
> + t1 = tcg_constant_i32(rD(ctx->opcode));
> + t2 = tcg_constant_i32(rA(ctx->opcode));
> + t3 = tcg_constant_i32(rB(ctx->opcode));
> gen_helper_lswx(cpu_env, t0, t1, t2, t3);
> }
>
> @@ -3352,8 +3354,8 @@ static void gen_stswi(DisasContext *ctx)
> if (nb == 0) {
> nb = 32;
> }
> - t1 = tcg_const_i32(nb);
> - t2 = tcg_const_i32(rS(ctx->opcode));
> + t1 = tcg_constant_i32(nb);
> + t2 = tcg_constant_i32(rS(ctx->opcode));
> gen_helper_stsw(cpu_env, t0, t1, t2);
> }
>
> @@ -3373,7 +3375,7 @@ static void gen_stswx(DisasContext *ctx)
> t1 = tcg_temp_new_i32();
> tcg_gen_trunc_tl_i32(t1, cpu_xer);
> tcg_gen_andi_i32(t1, t1, 0x7F);
> - t2 = tcg_const_i32(rS(ctx->opcode));
> + t2 = tcg_constant_i32(rS(ctx->opcode));
> gen_helper_stsw(cpu_env, t0, t1, t2);
> }
>
> @@ -3943,7 +3945,7 @@ static void gen_wait(DisasContext *ctx)
> * to occur.
> */
> if (wc == 0) {
> - TCGv_i32 t0 = tcg_const_i32(1);
> + TCGv_i32 t0 = tcg_constant_i32(1);
> tcg_gen_st_i32(t0, cpu_env,
> -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
> /* Stop translation, as the CPU is supposed to sleep from now */
> @@ -3989,7 +3991,7 @@ static void gen_doze(DisasContext *ctx)
> TCGv_i32 t;
>
> CHK_HV(ctx);
> - t = tcg_const_i32(PPC_PM_DOZE);
> + t = tcg_constant_i32(PPC_PM_DOZE);
> gen_helper_pminsn(cpu_env, t);
> /* Stop translation, as the CPU is supposed to sleep from now */
> gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
> @@ -4004,7 +4006,7 @@ static void gen_nap(DisasContext *ctx)
> TCGv_i32 t;
>
> CHK_HV(ctx);
> - t = tcg_const_i32(PPC_PM_NAP);
> + t = tcg_constant_i32(PPC_PM_NAP);
> gen_helper_pminsn(cpu_env, t);
> /* Stop translation, as the CPU is supposed to sleep from now */
> gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
> @@ -4019,7 +4021,7 @@ static void gen_stop(DisasContext *ctx)
> TCGv_i32 t;
>
> CHK_HV(ctx);
> - t = tcg_const_i32(PPC_PM_STOP);
> + t = tcg_constant_i32(PPC_PM_STOP);
> gen_helper_pminsn(cpu_env, t);
> /* Stop translation, as the CPU is supposed to sleep from now */
> gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
> @@ -4034,7 +4036,7 @@ static void gen_sleep(DisasContext *ctx)
> TCGv_i32 t;
>
> CHK_HV(ctx);
> - t = tcg_const_i32(PPC_PM_SLEEP);
> + t = tcg_constant_i32(PPC_PM_SLEEP);
> gen_helper_pminsn(cpu_env, t);
> /* Stop translation, as the CPU is supposed to sleep from now */
> gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
> @@ -4049,7 +4051,7 @@ static void gen_rvwinkle(DisasContext *ctx)
> TCGv_i32 t;
>
> CHK_HV(ctx);
> - t = tcg_const_i32(PPC_PM_RVWINKLE);
> + t = tcg_constant_i32(PPC_PM_RVWINKLE);
> gen_helper_pminsn(cpu_env, t);
> /* Stop translation, as the CPU is supposed to sleep from now */
> gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
> @@ -4506,7 +4508,7 @@ static void gen_tw(DisasContext *ctx)
> if (check_unconditional_trap(ctx)) {
> return;
> }
> - t0 = tcg_const_i32(TO(ctx->opcode));
> + t0 = tcg_constant_i32(TO(ctx->opcode));
> gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
> t0);
> }
> @@ -4520,8 +4522,8 @@ static void gen_twi(DisasContext *ctx)
> if (check_unconditional_trap(ctx)) {
> return;
> }
> - t0 = tcg_const_tl(SIMM(ctx->opcode));
> - t1 = tcg_const_i32(TO(ctx->opcode));
> + t0 = tcg_constant_tl(SIMM(ctx->opcode));
> + t1 = tcg_constant_i32(TO(ctx->opcode));
> gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
> }
>
> @@ -4534,7 +4536,7 @@ static void gen_td(DisasContext *ctx)
> if (check_unconditional_trap(ctx)) {
> return;
> }
> - t0 = tcg_const_i32(TO(ctx->opcode));
> + t0 = tcg_constant_i32(TO(ctx->opcode));
> gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
> t0);
> }
> @@ -4548,8 +4550,8 @@ static void gen_tdi(DisasContext *ctx)
> if (check_unconditional_trap(ctx)) {
> return;
> }
> - t0 = tcg_const_tl(SIMM(ctx->opcode));
> - t1 = tcg_const_i32(TO(ctx->opcode));
> + t0 = tcg_constant_tl(SIMM(ctx->opcode));
> + t1 = tcg_constant_i32(TO(ctx->opcode));
> gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
> }
> #endif
> @@ -5026,7 +5028,7 @@ static void gen_dcbz(DisasContext *ctx)
>
> gen_set_access_type(ctx, ACCESS_CACHE);
> tcgv_addr = tcg_temp_new();
> - tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
> + tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
> gen_addr_reg_index(ctx, tcgv_addr);
> gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op);
> }
> @@ -5039,7 +5041,7 @@ static void gen_dcbzep(DisasContext *ctx)
>
> gen_set_access_type(ctx, ACCESS_CACHE);
> tcgv_addr = tcg_temp_new();
> - tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000);
> + tcgv_op = tcg_constant_i32(ctx->opcode & 0x03FF000);
> gen_addr_reg_index(ctx, tcgv_addr);
> gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op);
> }
> @@ -5114,7 +5116,7 @@ static void gen_mfsr(DisasContext *ctx)
> TCGv t0;
>
> CHK_SV(ctx);
> - t0 = tcg_const_tl(SR(ctx->opcode));
> + t0 = tcg_constant_tl(SR(ctx->opcode));
> gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
> #endif /* defined(CONFIG_USER_ONLY) */
> }
> @@ -5143,7 +5145,7 @@ static void gen_mtsr(DisasContext *ctx)
> TCGv t0;
>
> CHK_SV(ctx);
> - t0 = tcg_const_tl(SR(ctx->opcode));
> + t0 = tcg_constant_tl(SR(ctx->opcode));
> gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
> #endif /* defined(CONFIG_USER_ONLY) */
> }
> @@ -5175,7 +5177,7 @@ static void gen_mfsr_64b(DisasContext *ctx)
> TCGv t0;
>
> CHK_SV(ctx);
> - t0 = tcg_const_tl(SR(ctx->opcode));
> + t0 = tcg_constant_tl(SR(ctx->opcode));
> gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
> #endif /* defined(CONFIG_USER_ONLY) */
> }
> @@ -5204,7 +5206,7 @@ static void gen_mtsr_64b(DisasContext *ctx)
> TCGv t0;
>
> CHK_SV(ctx);
> - t0 = tcg_const_tl(SR(ctx->opcode));
> + t0 = tcg_constant_tl(SR(ctx->opcode));
> gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
> #endif /* defined(CONFIG_USER_ONLY) */
> }
> @@ -5558,7 +5560,7 @@ static void gen_mfdcr(DisasContext *ctx)
> TCGv dcrn;
>
> CHK_SV(ctx);
> - dcrn = tcg_const_tl(SPR(ctx->opcode));
> + dcrn = tcg_constant_tl(SPR(ctx->opcode));
> gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
> #endif /* defined(CONFIG_USER_ONLY) */
> }
> @@ -5572,7 +5574,7 @@ static void gen_mtdcr(DisasContext *ctx)
> TCGv dcrn;
>
> CHK_SV(ctx);
> - dcrn = tcg_const_tl(SPR(ctx->opcode));
> + dcrn = tcg_constant_tl(SPR(ctx->opcode));
> gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
> #endif /* defined(CONFIG_USER_ONLY) */
> }
> @@ -5793,7 +5795,7 @@ static void gen_tlbre_440(DisasContext *ctx)
> case 1:
> case 2:
> {
> - TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
> + TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
> gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
> t0, cpu_gpr[rA(ctx->opcode)]);
> }
> @@ -5839,7 +5841,7 @@ static void gen_tlbwe_440(DisasContext *ctx)
> case 1:
> case 2:
> {
> - TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
> + TCGv_i32 t0 = tcg_constant_i32(rB(ctx->opcode));
> gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
> cpu_gpr[rS(ctx->opcode)]);
> }
> @@ -5981,7 +5983,7 @@ static void gen_wrteei(DisasContext *ctx)
> /* dlmzb */
> static void gen_dlmzb(DisasContext *ctx)
> {
> - TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
> + TCGv_i32 t0 = tcg_constant_i32(Rc(ctx->opcode));
> gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
> cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
> }
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 21/25] target/ppc: Fix gen_tlbsx_booke206
2023-03-07 18:34 ` [PATCH v2 21/25] target/ppc: Fix gen_tlbsx_booke206 Richard Henderson
@ 2023-03-07 21:44 ` Daniel Henrique Barboza
0 siblings, 0 replies; 51+ messages in thread
From: Daniel Henrique Barboza @ 2023-03-07 21:44 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Cédric Le Goater, David Gibson, Greg Kurz, qemu-ppc
On 3/7/23 15:34, Richard Henderson wrote:
> Fix incorrect read from rD.
> Avoid adding 0 when rA == 0.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index df324fc7ff..7ec940b7d8 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -5875,12 +5875,10 @@ static void gen_tlbsx_booke206(DisasContext *ctx)
> CHK_SV(ctx);
> if (rA(ctx->opcode)) {
> t0 = tcg_temp_new();
> - tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
> + tcg_gen_add_tl(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
> } else {
> - t0 = tcg_const_tl(0);
> + t0 = cpu_gpr[rB(ctx->opcode)];
> }
> -
> - tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
> gen_helper_booke206_tlbsx(cpu_env, t0);
> #endif /* defined(CONFIG_USER_ONLY) */
> }
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 20/25] target/ppc: Rewrite trans_ADDG6S
2023-03-07 18:34 ` [PATCH v2 20/25] target/ppc: Rewrite trans_ADDG6S Richard Henderson
@ 2023-03-07 21:51 ` Daniel Henrique Barboza
2023-03-07 22:34 ` Richard Henderson
0 siblings, 1 reply; 51+ messages in thread
From: Daniel Henrique Barboza @ 2023-03-07 21:51 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Cédric Le Goater, David Gibson, Greg Kurz, qemu-ppc
On 3/7/23 15:34, Richard Henderson wrote:
> Compute all carry bits in parallel instead of a loop.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
Hmmmm the function was added by 6addef4d27268 9 months ago. All tcg ops you used
here were available back then.
I guess this existing implementation was an oversight on our end.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate/fixedpoint-impl.c.inc | 44 +++++++++++-----------
> 1 file changed, 23 insertions(+), 21 deletions(-)
>
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
> index 20ea484c3d..02d86b77a8 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -484,33 +484,35 @@ static bool trans_PEXTD(DisasContext *ctx, arg_X *a)
>
> static bool trans_ADDG6S(DisasContext *ctx, arg_X *a)
> {
> - const uint64_t carry_bits = 0x1111111111111111ULL;
> - TCGv t0, t1, carry, zero = tcg_constant_tl(0);
> + const target_ulong carry_bits = (target_ulong)-1 / 0xf;
> + TCGv in1, in2, carryl, carryh, tmp;
> + TCGv zero = tcg_constant_tl(0);
>
> REQUIRE_INSNS_FLAGS2(ctx, BCDA_ISA206);
>
> - t0 = tcg_temp_new();
> - t1 = tcg_const_tl(0);
> - carry = tcg_const_tl(0);
> + in1 = cpu_gpr[a->ra];
> + in2 = cpu_gpr[a->rb];
> + tmp = tcg_temp_new();
> + carryl = tcg_temp_new();
> + carryh = tcg_temp_new();
>
> - for (int i = 0; i < 16; i++) {
> - tcg_gen_shri_tl(t0, cpu_gpr[a->ra], i * 4);
> - tcg_gen_andi_tl(t0, t0, 0xf);
> - tcg_gen_add_tl(t1, t1, t0);
> + /* Addition with carry. */
> + tcg_gen_add2_tl(carryl, carryh, in1, zero, in2, zero);
> + /* Addition without carry. */
> + tcg_gen_xor_tl(tmp, in1, in2);
> + /* Difference between the two is carry in to each bit. */
> + tcg_gen_xor_tl(carryl, carryl, tmp);
>
> - tcg_gen_shri_tl(t0, cpu_gpr[a->rb], i * 4);
> - tcg_gen_andi_tl(t0, t0, 0xf);
> - tcg_gen_add_tl(t1, t1, t0);
> + /*
> + * The carry-out that we're looking for is the carry-in to
> + * the next nibble. Shift the double-word down one nibble,
> + * which puts all of the bits back into one word.
> + */
> + tcg_gen_extract2_tl(carryl, carryl, carryh, 4);
>
> - tcg_gen_andi_tl(t1, t1, 0x10);
> - tcg_gen_setcond_tl(TCG_COND_NE, t1, t1, zero);
> -
> - tcg_gen_shli_tl(t0, t1, i * 4);
> - tcg_gen_or_tl(carry, carry, t0);
> - }
> -
> - tcg_gen_xori_tl(carry, carry, (target_long)carry_bits);
> - tcg_gen_muli_tl(cpu_gpr[a->rt], carry, 6);
> + /* Invert, isolate the carry bits, and produce 6's. */
> + tcg_gen_andc_tl(carryl, tcg_constant_tl(carry_bits), carryl);
> + tcg_gen_muli_tl(cpu_gpr[a->rt], carryl, 6);
> return true;
> }
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 20/25] target/ppc: Rewrite trans_ADDG6S
2023-03-07 21:51 ` Daniel Henrique Barboza
@ 2023-03-07 22:34 ` Richard Henderson
0 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-07 22:34 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: Cédric Le Goater, David Gibson, Greg Kurz, qemu-ppc
On 3/7/23 13:51, Daniel Henrique Barboza wrote:
>
>
> On 3/7/23 15:34, Richard Henderson wrote:
>> Compute all carry bits in parallel instead of a loop.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>
> Hmmmm the function was added by 6addef4d27268 9 months ago. All tcg ops you used
> here were available back then.
>
> I guess this existing implementation was an oversight on our end.
I seem to have missed the whole patch set, which is a shame -- I could have pointed you to
a similar function for hppa.
r~
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 09/25] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
2023-03-07 18:34 ` [PATCH v2 09/25] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn Richard Henderson
@ 2023-03-07 23:02 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-07 23:02 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 7/3/23 19:34, Richard Henderson wrote:
> It is easy enough to use mov instead of or-with-zero
> and relying on the optimizer to fold away the or.
> Use an array for the output, rather than separate
> tcg_res{l,h} variables.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: qemu-arm@nongnu.org
> ---
> target/arm/tcg/translate-a64.c | 41 +++++++++++++++++-----------------
> 1 file changed, 21 insertions(+), 20 deletions(-)
> + for (i = 0; i <= is_q; ++i) {
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> + write_vec_element(s, tcg_res[i], rd, i, MO_64);
> }
> clear_vec_high(s, is_q, rd);
> }
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 06/25] target/arm: Improve trans_BFCI
2023-03-07 18:34 ` [PATCH v2 06/25] target/arm: Improve trans_BFCI Richard Henderson
@ 2023-03-07 23:05 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-07 23:05 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 7/3/23 19:34, Richard Henderson wrote:
> Reorg temporary usage so that we can use tcg_constant_i32.
> tcg_gen_deposit_i32 already has a width == 32 special case,
> so remove the check here.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: qemu-arm@nongnu.org
> ---
> target/arm/tcg/translate.c | 13 +++++--------
> 1 file changed, 5 insertions(+), 8 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 02/25] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf
2023-03-07 18:34 ` [PATCH v2 02/25] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf Richard Henderson
@ 2023-03-08 17:25 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-08 17:25 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 7/3/23 19:34, Richard Henderson wrote:
> While this enumerator has been present since the first commit,
> it isn't ever used. The first actual use of round-to-odd came
> with SVE, which currently uses float_round_to_odd instead of
> the arm-specific enumerator.
>
> Amusingly, the comment about unhandled TIEAWAY has been
> out of date since the initial commit of translate-a64.c.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: qemu-arm@nongnu.org
> ---
> target/arm/vfp_helper.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 05/25] target/arm: Create gen_set_rmode, gen_restore_rmode
2023-03-07 18:34 ` [PATCH v2 05/25] target/arm: Create gen_set_rmode, gen_restore_rmode Richard Henderson
@ 2023-03-09 9:48 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-09 9:48 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 7/3/23 19:34, Richard Henderson wrote:
> Split out common subroutines for handing rounding mode
> changes during translation. Use tcg_constant_i32 and
> tcg_temp_new_i32 instead of tcg_const_i32.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: qemu-arm@nongnu.org
> ---
> target/arm/tcg/translate.h | 17 ++++++++++++
> target/arm/tcg/translate-a64.c | 47 ++++++++++++++--------------------
> target/arm/tcg/translate-sve.c | 6 ++---
> target/arm/tcg/translate-vfp.c | 26 ++++++++-----------
> 4 files changed, 48 insertions(+), 48 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 15/25] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
2023-03-07 18:34 ` [PATCH v2 15/25] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc Richard Henderson
2023-03-07 21:42 ` Daniel Henrique Barboza
@ 2023-03-09 9:49 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-09 9:49 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
On 7/3/23 19:34, Richard Henderson wrote:
> All remaining uses are strictly read-only.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate/vmx-impl.c.inc | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 16/25] target/ppc: Avoid tcg_const_* in xxeval
2023-03-07 18:34 ` [PATCH v2 16/25] target/ppc: Avoid tcg_const_* in xxeval Richard Henderson
2023-03-07 21:42 ` Daniel Henrique Barboza
@ 2023-03-09 9:51 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-09 9:51 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
On 7/3/23 19:34, Richard Henderson wrote:
> Initialize a new temp instead of tcg_const_*.
> Fix a pasto in a comment.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate/vsx-impl.c.inc | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 17/25] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
2023-03-07 18:34 ` [PATCH v2 17/25] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Richard Henderson
2023-03-07 21:42 ` Daniel Henrique Barboza
@ 2023-03-09 9:52 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-09 9:52 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
On 7/3/23 19:34, Richard Henderson wrote:
> All remaining uses are strictly read-only.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate/vsx-impl.c.inc | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 18/25] target/ppc: Avoid tcg_const_* in fp-impl.c.inc
2023-03-07 18:34 ` [PATCH v2 18/25] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Richard Henderson
2023-03-07 21:43 ` Daniel Henrique Barboza
@ 2023-03-09 9:54 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-09 9:54 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
On 7/3/23 19:34, Richard Henderson wrote:
> All uses are strictly read-only.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate/fp-impl.c.inc | 26 ++++++++++++--------------
> 1 file changed, 12 insertions(+), 14 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 19/25] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
2023-03-07 18:34 ` [PATCH v2 19/25] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc Richard Henderson
2023-03-07 21:43 ` Daniel Henrique Barboza
@ 2023-03-09 9:54 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-09 9:54 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
On 7/3/23 19:34, Richard Henderson wrote:
> All uses are strictly read-only.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/power8-pmu-regs.c.inc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 22/25] target/ppc: Avoid tcg_const_* in translate.c
2023-03-07 18:35 ` [PATCH v2 22/25] target/ppc: Avoid tcg_const_* in translate.c Richard Henderson
2023-03-07 21:44 ` Daniel Henrique Barboza
@ 2023-03-09 10:02 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-09 10:02 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
On 7/3/23 19:35, Richard Henderson wrote:
> All remaining uses are strictly read-only.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate.c | 142 +++++++++++++++++++++--------------------
> 1 file changed, 72 insertions(+), 70 deletions(-)
> @@ -386,7 +386,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
> static void spr_load_dump_spr(int sprn)
> {
> #ifdef PPC_DUMP_SPR_ACCESSES
> - TCGv_i32 t0 = tcg_const_i32(sprn);
> + TCGv_i32 t0 = tcg_constant_i32(sprn);
> gen_helper_load_dump_spr(cpu_env, t0);
> #endif
> }
> @@ -400,7 +400,7 @@ void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
> static void spr_store_dump_spr(int sprn)
> {
> #ifdef PPC_DUMP_SPR_ACCESSES
> - TCGv_i32 t0 = tcg_const_i32(sprn);
> + TCGv_i32 t0 = tcg_constant_i32(sprn);
> gen_helper_store_dump_spr(cpu_env, t0);
> #endif
> }
Unrelated, but probably better to convert this PPC_DUMP_SPR_ACCESSES
#ifdef'ry to a boolean in DisasContext.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 23/25] target/tricore: Use min/max for saturate
2023-03-07 18:35 ` [PATCH v2 23/25] target/tricore: Use min/max for saturate Richard Henderson
@ 2023-03-09 10:09 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-09 10:09 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Bastian Koppelmann
On 7/3/23 19:35, Richard Henderson wrote:
> Use tcg_constant_i32 for the bounds.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> target/tricore/translate.c | 14 +++-----------
> 1 file changed, 3 insertions(+), 11 deletions(-)
> static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
> {
> - TCGv sat_neg = tcg_const_i32(low);
> - TCGv temp = tcg_const_i32(up);
> -
> - /* sat_neg = (arg < low ) ? low : arg; */
> - tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
> -
> - /* ret = (sat_neg > up ) ? up : sat_neg; */
> - tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
> + tcg_gen_smax_tl(ret, arg, tcg_constant_i32(low));
This one is trivial when looking at tcg_gen_smax implementation.
> + tcg_gen_smin_tl(ret, ret, tcg_constant_i32(up));
OK, when changing TCG_COND_GT -> TCG_COND_LT and inverting the args,
then this becomes obvious this is tcg_gen_smin.
> }
>
> static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
> {
> - TCGv temp = tcg_const_i32(up);
> - /* sat_neg = (arg > up ) ? up : arg; */
> - tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
> + tcg_gen_umin_tl(ret, arg, tcg_constant_i32(up));
Inverting args for TCG_COND_GTU -> TCG_COND_LTU, this is indeed
tcg_gen_umin.
> }
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 14/25] target/ppc: Avoid tcg_const_i64 in do_vcntmb
2023-03-07 18:34 ` [PATCH v2 14/25] target/ppc: Avoid tcg_const_i64 in do_vcntmb Richard Henderson
2023-03-07 21:42 ` Daniel Henrique Barboza
@ 2023-03-09 10:18 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-09 10:18 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Cc: Daniel Henrique Barboza, Cédric Le Goater, David Gibson,
Greg Kurz, qemu-ppc
On 7/3/23 19:34, Richard Henderson wrote:
> Compute both partial results separately and accumulate
> at the end, instead of accumulating in the middle.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: Daniel Henrique Barboza <danielhb413@gmail.com>
> Cc: Cédric Le Goater <clg@kaod.org>
> Cc: David Gibson <david@gibson.dropbear.id.au>
> Cc: Greg Kurz <groug@kaod.org>
> Cc: qemu-ppc@nongnu.org
> ---
> target/ppc/translate/vmx-impl.c.inc | 21 +++++++++++----------
> 1 file changed, 11 insertions(+), 10 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 12/25] target/m68k: Reject immediate as destination in gen_ea_mode
2023-03-07 18:34 ` [PATCH v2 12/25] target/m68k: Reject immediate as destination in gen_ea_mode Richard Henderson
@ 2023-03-09 12:32 ` Laurent Vivier
2023-03-09 16:27 ` Richard Henderson
0 siblings, 1 reply; 51+ messages in thread
From: Laurent Vivier @ 2023-03-09 12:32 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
Le 07/03/2023 à 19:34, Richard Henderson a écrit :
> In theory this should never happen, as all such instructions
> are illegal. This is checked in e.g. gen_lea_mode and
> gen_ea_mode_fp but not here. In case something higher up
> isn't checking modes properly, return NULL_QREG. This will
> result in an illegal instruction exception being raised.
NULL_QREG generates an address exception, not illegal instruction.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: Laurent Vivier <laurent@vivier.eu>
> ---
> target/m68k/translate.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/m68k/translate.c b/target/m68k/translate.c
> index 44c3ac0bc3..fc65dad190 100644
> --- a/target/m68k/translate.c
> +++ b/target/m68k/translate.c
> @@ -894,6 +894,10 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
> case 3: /* pc index+displacement. */
> goto do_indirect;
> case 4: /* Immediate. */
> + /* Should never be used for an output or RMW input. */
> + if (what == EA_STORE || addrp) {
Why do you check addrp?
What happens for an instruction that provides addrp to SRC_EA() when it is used with immediate mode?
In this case addrp is unused, but it should not trigger an exception.
Thanks,
Laurent
> + return NULL_QREG;
> + }
> /* Sign extend values for consistency. */
> switch (opsize) {
> case OS_BYTE:
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 08/25] target/arm: Avoid tcg_const_* in translate-mve.c
2023-03-07 18:34 ` [PATCH v2 08/25] target/arm: Avoid tcg_const_* in translate-mve.c Richard Henderson
@ 2023-03-09 13:27 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 51+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-03-09 13:27 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: qemu-arm
On 7/3/23 19:34, Richard Henderson wrote:
> All uses are in the context of an accumulator conditionally
> having a zero input. Split the rda variable to rda_{i,o},
> and set rda_i to tcg_constant_foo(0) when required.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> Cc: qemu-arm@nongnu.org
> ---
> target/arm/tcg/translate-mve.c | 54 ++++++++++++++++++----------------
> 1 file changed, 29 insertions(+), 25 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v2 12/25] target/m68k: Reject immediate as destination in gen_ea_mode
2023-03-09 12:32 ` Laurent Vivier
@ 2023-03-09 16:27 ` Richard Henderson
0 siblings, 0 replies; 51+ messages in thread
From: Richard Henderson @ 2023-03-09 16:27 UTC (permalink / raw)
To: Laurent Vivier, qemu-devel
On 3/9/23 04:32, Laurent Vivier wrote:
> Le 07/03/2023 à 19:34, Richard Henderson a écrit :
>> In theory this should never happen, as all such instructions
>> are illegal. This is checked in e.g. gen_lea_mode and
>> gen_ea_mode_fp but not here. In case something higher up
>> isn't checking modes properly, return NULL_QREG. This will
>> result in an illegal instruction exception being raised.
>
> NULL_QREG generates an address exception, not illegal instruction.
>
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>> Cc: Laurent Vivier <laurent@vivier.eu>
>> ---
>> target/m68k/translate.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/target/m68k/translate.c b/target/m68k/translate.c
>> index 44c3ac0bc3..fc65dad190 100644
>> --- a/target/m68k/translate.c
>> +++ b/target/m68k/translate.c
>> @@ -894,6 +894,10 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int
>> mode, int reg0,
>> case 3: /* pc index+displacement. */
>> goto do_indirect;
>> case 4: /* Immediate. */
>> + /* Should never be used for an output or RMW input. */
>> + if (what == EA_STORE || addrp) {
>
> Why do you check addrp?
>
> What happens for an instruction that provides addrp to SRC_EA() when it is used with
> immediate mode?
> In this case addrp is unused, but it should not trigger an exception.
Because addrp is *not* unused with SRC_EA. It is a signal for a read-modify-write operand
and addrp will be passed to DEST_EA.
r~
^ permalink raw reply [flat|nested] 51+ messages in thread
end of thread, other threads:[~2023-03-09 16:28 UTC | newest]
Thread overview: 51+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-07 18:34 [PATCH v2 00/25] tcg: Remove tcg_const_* Richard Henderson
2023-03-07 18:34 ` [PATCH v2 01/25] target/arm: Use rmode >= 0 for need_rmode Richard Henderson
2023-03-07 18:34 ` [PATCH v2 02/25] target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf Richard Henderson
2023-03-08 17:25 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 03/25] target/arm: Improve arm_rmode_to_sf Richard Henderson
2023-03-07 18:34 ` [PATCH v2 04/25] target/arm: Consistently use ARMFPRounding during translation Richard Henderson
2023-03-07 18:34 ` [PATCH v2 05/25] target/arm: Create gen_set_rmode, gen_restore_rmode Richard Henderson
2023-03-09 9:48 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 06/25] target/arm: Improve trans_BFCI Richard Henderson
2023-03-07 23:05 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 07/25] target/arm: Avoid tcg_const_ptr in gen_sve_{ldr, str} Richard Henderson
2023-03-07 18:34 ` [PATCH v2 08/25] target/arm: Avoid tcg_const_* in translate-mve.c Richard Henderson
2023-03-09 13:27 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 09/25] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn Richard Henderson
2023-03-07 23:02 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 10/25] target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn Richard Henderson
2023-03-07 18:34 ` [PATCH v2 11/25] target/arm: Avoid tcg_const_ptr in handle_rev Richard Henderson
2023-03-07 18:34 ` [PATCH v2 12/25] target/m68k: Reject immediate as destination in gen_ea_mode Richard Henderson
2023-03-09 12:32 ` Laurent Vivier
2023-03-09 16:27 ` Richard Henderson
2023-03-07 18:34 ` [PATCH v2 13/25] target/m68k: Use tcg_constant_i32 " Richard Henderson
2023-03-07 18:34 ` [PATCH v2 14/25] target/ppc: Avoid tcg_const_i64 in do_vcntmb Richard Henderson
2023-03-07 21:42 ` Daniel Henrique Barboza
2023-03-09 10:18 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 15/25] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc Richard Henderson
2023-03-07 21:42 ` Daniel Henrique Barboza
2023-03-09 9:49 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 16/25] target/ppc: Avoid tcg_const_* in xxeval Richard Henderson
2023-03-07 21:42 ` Daniel Henrique Barboza
2023-03-09 9:51 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 17/25] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Richard Henderson
2023-03-07 21:42 ` Daniel Henrique Barboza
2023-03-09 9:52 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 18/25] target/ppc: Avoid tcg_const_* in fp-impl.c.inc Richard Henderson
2023-03-07 21:43 ` Daniel Henrique Barboza
2023-03-09 9:54 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 19/25] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc Richard Henderson
2023-03-07 21:43 ` Daniel Henrique Barboza
2023-03-09 9:54 ` Philippe Mathieu-Daudé
2023-03-07 18:34 ` [PATCH v2 20/25] target/ppc: Rewrite trans_ADDG6S Richard Henderson
2023-03-07 21:51 ` Daniel Henrique Barboza
2023-03-07 22:34 ` Richard Henderson
2023-03-07 18:34 ` [PATCH v2 21/25] target/ppc: Fix gen_tlbsx_booke206 Richard Henderson
2023-03-07 21:44 ` Daniel Henrique Barboza
2023-03-07 18:35 ` [PATCH v2 22/25] target/ppc: Avoid tcg_const_* in translate.c Richard Henderson
2023-03-07 21:44 ` Daniel Henrique Barboza
2023-03-09 10:02 ` Philippe Mathieu-Daudé
2023-03-07 18:35 ` [PATCH v2 23/25] target/tricore: Use min/max for saturate Richard Henderson
2023-03-09 10:09 ` Philippe Mathieu-Daudé
2023-03-07 18:35 ` [PATCH v2 24/25] tcg: Drop tcg_const_*_vec Richard Henderson
2023-03-07 18:35 ` [PATCH v2 25/25] tcg: Drop tcg_const_* Richard Henderson
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