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* ZICBOM and SVPBMT in same system
@ 2023-03-07 20:58 Ben Dooks
  2023-03-07 20:58 ` [PATCH 1/2] riscv: alternatives: add 3-config alternative set Ben Dooks
  2023-03-07 20:58 ` [PATCH 2/2] riscv: mm: add pgprot_dmacoherent for zicbom Ben Dooks
  0 siblings, 2 replies; 10+ messages in thread
From: Ben Dooks @ 2023-03-07 20:58 UTC (permalink / raw)
  To: linux-riscv; +Cc: palmer, aou, heiko.stuebner, conor.dooley, ajones

It is possible to have a system with both of these in the risc,isa
string and if so they do not work well with the dma memory allocator.

Fix this up by adding a new pgprog_dmacoherent which returns either
non-cached if SVPBMT only, or cached iff there is ZICBOM and thus
cache management operations.



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^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 1/2] riscv: alternatives: add 3-config alternative set
  2023-03-07 20:58 ZICBOM and SVPBMT in same system Ben Dooks
@ 2023-03-07 20:58 ` Ben Dooks
  2023-03-07 21:31   ` Conor Dooley
  2023-03-07 20:58 ` [PATCH 2/2] riscv: mm: add pgprot_dmacoherent for zicbom Ben Dooks
  1 sibling, 1 reply; 10+ messages in thread
From: Ben Dooks @ 2023-03-07 20:58 UTC (permalink / raw)
  To: linux-riscv; +Cc: palmer, aou, heiko.stuebner, conor.dooley, ajones, Ben Dooks

Add a 3-config alternative macro set for cases where there are
three different choices for a given erratum. This will be used
when we come to patch the issues with SVPBMT and ZICBOM.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/riscv/include/asm/alternative-macros.h | 38 +++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
index 51c6867e02f3..8c74b00d707c 100644
--- a/arch/riscv/include/asm/alternative-macros.h
+++ b/arch/riscv/include/asm/alternative-macros.h
@@ -50,8 +50,18 @@
 	ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
 .endm
 
+.macro ALTERNATIVE_CFG_3 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1,	\
+				new_c_2, vendor_id_2, errata_id_2, enable_2,	\
+				new_c_3, vendor_id_3, errata_id_3, enable_3
+	ALTERNATIVE_CFG "\old_c", "\new_c_1", \vendor_id_1, \errata_id_1, \enable_1
+	ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
+	ALT_NEW_CONTENT \vendor_id_3, \errata_id_3, \enable_3, \new_c_3
+.endm
+
+
 #define __ALTERNATIVE_CFG(...)		ALTERNATIVE_CFG __VA_ARGS__
 #define __ALTERNATIVE_CFG_2(...)	ALTERNATIVE_CFG_2 __VA_ARGS__
+#define __ALTERNATIVE_CFG_3(...)	ALTERNATIVE_CFG_3 __VA_ARGS__
 
 #else /* !__ASSEMBLY__ */
 
@@ -98,6 +108,13 @@
 	__ALTERNATIVE_CFG(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1)	\
 	ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
 
+#define __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1,	\
+				   new_c_2, vendor_id_2, errata_id_2, enable_2, \
+				   new_c_3, vendor_id_3, errata_id_3, enable_3)	\
+	__ALTERNATIVE_CFG(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1)	\
+	ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)		\
+	ALT_NEW_CONTENT(vendor_id_3, errata_id_3, enable_3, new_c_3)
+	
 #endif /* __ASSEMBLY__ */
 
 #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k)	\
@@ -108,6 +125,13 @@
 	__ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1),	\
 				   new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2))
 
+#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1,		\
+				  new_c_2, vendor_id_2, errata_id_2, CONFIG_k_2,		\
+				  new_c_3, vendor_id_3, errata_id_3, CONFIG_k_3)		\
+	__ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1),	\
+				   new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2),   \
+				   new_c_3, vendor_id_3, errata_id_3, IS_ENABLED(CONFIG_k_3))
+	
 #else /* CONFIG_RISCV_ALTERNATIVE */
 #ifdef __ASSEMBLY__
 
@@ -121,6 +145,9 @@
 #define _ALTERNATIVE_CFG_2(old_c, ...)	\
 	ALTERNATIVE_CFG old_c
 
+#define _ALTERNATIVE_CFG_3(old_c, ...)	\
+	ALTERNATIVE_CFG old_c
+
 #else /* !__ASSEMBLY__ */
 
 #define __ALTERNATIVE_CFG(old_c)	\
@@ -132,6 +159,9 @@
 #define _ALTERNATIVE_CFG_2(old_c, ...)	\
 	__ALTERNATIVE_CFG(old_c)
 
+#define _ALTERNATIVE_CFG_3(old_c, ...)	\
+	__ALTERNATIVE_CFG(old_c)
+
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_RISCV_ALTERNATIVE */
 
@@ -163,4 +193,12 @@
 	_ALTERNATIVE_CFG_2(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1,	\
 					new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2)
 
+#define ALTERNATIVE_3(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1,		\
+				   new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2,		\
+				   new_content_3, vendor_id_3, errata_id_3, CONFIG_k_3)		\
+	_ALTERNATIVE_CFG_3(old_content, new_content_1, vendor_id_1, errata_id_1, CONFIG_k_1,	\
+					new_content_2, vendor_id_2, errata_id_2, CONFIG_k_2,	\
+					new_content_3, vendor_id_3, errata_id_3, CONFIG_k_3)
+
+
 #endif
-- 
2.39.2


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^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [PATCH 2/2] riscv: mm: add pgprot_dmacoherent for zicbom
  2023-03-07 20:58 ZICBOM and SVPBMT in same system Ben Dooks
  2023-03-07 20:58 ` [PATCH 1/2] riscv: alternatives: add 3-config alternative set Ben Dooks
@ 2023-03-07 20:58 ` Ben Dooks
  2023-03-08  9:35   ` Ben Dooks
  1 sibling, 1 reply; 10+ messages in thread
From: Ben Dooks @ 2023-03-07 20:58 UTC (permalink / raw)
  To: linux-riscv; +Cc: palmer, aou, heiko.stuebner, conor.dooley, ajones, Ben Dooks

If the system uses both ZICBOM and SVPBMT then currently SVPBMT will be
used for DMA allocated memory even though ZICBOM gives us the cache ops
to use cached memory and clean/flush them as needed by the DMA code.

Fix this by adding pgprot_dmacoherent() which is used by the allocator
code to map the dma memory, thus allowing the return of suitably mapped
memory for any use of dma_alloc_attrs() code. This s uses the added
riscv_page_dmacoherent() which will work out the correct page flags to
return using ALT_SVPBMT_ZICBOM() to runtime patch the right result.

Note, we can't just disable SVPBMT as it will be neede for things like
ioremap() which don't have assoicated cache management operations.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 arch/riscv/include/asm/errata_list.h | 16 ++++++++++++++++
 arch/riscv/include/asm/pgtable-64.h  | 10 ++++++++++
 2 files changed, 26 insertions(+)

diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index fb1a810f3d8c..49ed2e7984a7 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -62,6 +62,22 @@ asm(ALTERNATIVE_2("li %0, 0\t\nnop",					\
 		  "I"(ALT_SVPBMT_SHIFT),				\
 		  "I"(ALT_THEAD_PBMT_SHIFT))
 
+#define ALT_SVPBMT_ZICBOM(_val, prot)					\
+asm(ALTERNATIVE_3("li %0, 0\t\nnop",					\
+		  "li %0, %1\t\nslli %0,%0,%3", 0,			\
+			RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,	\
+		  "li %0, 0\t\nnop", 0,					\
+			RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM,	\
+		  "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID,	\
+			ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)	\
+		: "=r"(_val)						\
+		: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),		\
+		  "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
+		  "I"(ALT_SVPBMT_SHIFT),				\
+		  "I"(ALT_THEAD_PBMT_SHIFT))
+
+
+
 #ifdef CONFIG_ERRATA_THEAD_PBMT
 /*
  * IO/NOCACHE memory types are handled together with svpbmt,
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 42a042c0e13e..e0d2e5fda5a4 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -126,10 +126,20 @@ static inline u64 riscv_page_io(void)
 	return val;
 }
 
+static inline u64 riscv_page_dmacoherent(void)
+{
+	u64 val;
+
+	ALT_SVPBMT_ZICBOM(val, _PAGE_IO);
+	return val;
+}
+
 #define _PAGE_NOCACHE		riscv_page_nocache()
 #define _PAGE_IO		riscv_page_io()
 #define _PAGE_MTMASK		riscv_page_mtmask()
 
+#define pgprot_dmacoherent(__prot) __pgprot(pgprot_val(__prot) | riscv_page_dmacoherent())
+
 /* Set of bits to preserve across pte_modify() */
 #define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
 					  _PAGE_WRITE | _PAGE_EXEC |	\
-- 
2.39.2


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^ permalink raw reply related	[flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] riscv: alternatives: add 3-config alternative set
  2023-03-07 20:58 ` [PATCH 1/2] riscv: alternatives: add 3-config alternative set Ben Dooks
@ 2023-03-07 21:31   ` Conor Dooley
  2023-03-08  9:34     ` Ben Dooks
  0 siblings, 1 reply; 10+ messages in thread
From: Conor Dooley @ 2023-03-07 21:31 UTC (permalink / raw)
  To: Ben Dooks; +Cc: linux-riscv, palmer, aou, heiko.stuebner, conor.dooley, ajones


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Hey Ben,

On Tue, Mar 07, 2023 at 08:58:33PM +0000, Ben Dooks wrote:
> Add a 3-config alternative macro set for cases where there are
> three different choices for a given erratum. This will be used
> when we come to patch the issues with SVPBMT and ZICBOM.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
>  arch/riscv/include/asm/alternative-macros.h | 38 +++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
> index 51c6867e02f3..8c74b00d707c 100644
> --- a/arch/riscv/include/asm/alternative-macros.h
> +++ b/arch/riscv/include/asm/alternative-macros.h
> @@ -50,8 +50,18 @@
>  	ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
>  .endm
>  
> +.macro ALTERNATIVE_CFG_3 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1,	\
> +				new_c_2, vendor_id_2, errata_id_2, enable_2,	\
> +				new_c_3, vendor_id_3, errata_id_3, enable_3
> +	ALTERNATIVE_CFG "\old_c", "\new_c_1", \vendor_id_1, \errata_id_1, \enable_1
> +	ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
> +	ALT_NEW_CONTENT \vendor_id_3, \errata_id_3, \enable_3, \new_c_3

A matter of opinion maybe, but there was a previous ALTERNATIVE_CFG_3
posting that was implemented using ALTERNATIVE_CFG_2 that, to me, is
easier to grok:
https://lore.kernel.org/linux-riscv/20221212115505.36770-2-prabhakar.mahadev-lad.rj@bp.renesas.com/
It's certainly an easier pattern to replicate for the inevitable
ALTERNATIVE_CFG_4,5,6,7 etc.

I'm not super bothered either way, but worth considering I think.

Cheers,
Conor.

> +.endm
> +
> +

btw, here & further down in the patch there's some instances of double
newlines that automation is gonna whinge about.

>  #define __ALTERNATIVE_CFG(...)		ALTERNATIVE_CFG __VA_ARGS__
>  #define __ALTERNATIVE_CFG_2(...)	ALTERNATIVE_CFG_2 __VA_ARGS__
> +#define __ALTERNATIVE_CFG_3(...)	ALTERNATIVE_CFG_3 __VA_ARGS__
>  
>  #else /* !__ASSEMBLY__ */
>  
> @@ -98,6 +108,13 @@
>  	__ALTERNATIVE_CFG(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1)	\
>  	ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
>  
> +#define __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1,	\
> +				   new_c_2, vendor_id_2, errata_id_2, enable_2, \
> +				   new_c_3, vendor_id_3, errata_id_3, enable_3)	\
> +	__ALTERNATIVE_CFG(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1)	\
> +	ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)		\
> +	ALT_NEW_CONTENT(vendor_id_3, errata_id_3, enable_3, new_c_3)
> +	
>  #endif /* __ASSEMBLY__ */
>  
>  #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k)	\
> @@ -108,6 +125,13 @@
>  	__ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1),	\
>  				   new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2))
>  
  ^ there's also trailing whitespace here that git am complains about.

> +#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1,		\
> +				  new_c_2, vendor_id_2, errata_id_2, CONFIG_k_2,		\
> +				  new_c_3, vendor_id_3, errata_id_3, CONFIG_k_3)		\
> +	__ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1),	\
> +				   new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2),   \
> +				   new_c_3, vendor_id_3, errata_id_3, IS_ENABLED(CONFIG_k_3))
> +	
>  #else /* CONFIG_RISCV_ALTERNATIVE */
>  #ifdef __ASSEMBLY__
>  
> @@ -121,6 +145,9 @@
>  #define _ALTERNATIVE_CFG_2(old_c, ...)	\
>  	ALTERNATIVE_CFG old_c
>  
  ^ and here too.

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^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] riscv: alternatives: add 3-config alternative set
  2023-03-07 21:31   ` Conor Dooley
@ 2023-03-08  9:34     ` Ben Dooks
  0 siblings, 0 replies; 10+ messages in thread
From: Ben Dooks @ 2023-03-08  9:34 UTC (permalink / raw)
  To: Conor Dooley
  Cc: linux-riscv, palmer, aou, heiko.stuebner, conor.dooley, ajones

On 07/03/2023 21:31, Conor Dooley wrote:
> Hey Ben,
> 
> On Tue, Mar 07, 2023 at 08:58:33PM +0000, Ben Dooks wrote:
>> Add a 3-config alternative macro set for cases where there are
>> three different choices for a given erratum. This will be used
>> when we come to patch the issues with SVPBMT and ZICBOM.
>>
>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>> ---
>>   arch/riscv/include/asm/alternative-macros.h | 38 +++++++++++++++++++++
>>   1 file changed, 38 insertions(+)
>>
>> diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
>> index 51c6867e02f3..8c74b00d707c 100644
>> --- a/arch/riscv/include/asm/alternative-macros.h
>> +++ b/arch/riscv/include/asm/alternative-macros.h
>> @@ -50,8 +50,18 @@
>>   	ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
>>   .endm
>>   
>> +.macro ALTERNATIVE_CFG_3 old_c, new_c_1, vendor_id_1, errata_id_1, enable_1,	\
>> +				new_c_2, vendor_id_2, errata_id_2, enable_2,	\
>> +				new_c_3, vendor_id_3, errata_id_3, enable_3
>> +	ALTERNATIVE_CFG "\old_c", "\new_c_1", \vendor_id_1, \errata_id_1, \enable_1
>> +	ALT_NEW_CONTENT \vendor_id_2, \errata_id_2, \enable_2, \new_c_2
>> +	ALT_NEW_CONTENT \vendor_id_3, \errata_id_3, \enable_3, \new_c_3
> 
> A matter of opinion maybe, but there was a previous ALTERNATIVE_CFG_3
> posting that was implemented using ALTERNATIVE_CFG_2 that, to me, is
> easier to grok:
> https://lore.kernel.org/linux-riscv/20221212115505.36770-2-prabhakar.mahadev-lad.rj@bp.renesas.com/
> It's certainly an easier pattern to replicate for the inevitable
> ALTERNATIVE_CFG_4,5,6,7 etc.
> 
> I'm not super bothered either way, but worth considering I think.
> 
> Cheers,
> Conor.

I'll have a look, whatever way we need to have this support before
we can add the fixes for zibom fixes in.

>> +.endm
>> +
>> +
> 
> btw, here & further down in the patch there's some instances of double
> newlines that automation is gonna whinge about.
> 
>>   #define __ALTERNATIVE_CFG(...)		ALTERNATIVE_CFG __VA_ARGS__
>>   #define __ALTERNATIVE_CFG_2(...)	ALTERNATIVE_CFG_2 __VA_ARGS__
>> +#define __ALTERNATIVE_CFG_3(...)	ALTERNATIVE_CFG_3 __VA_ARGS__
>>   
>>   #else /* !__ASSEMBLY__ */
>>   
>> @@ -98,6 +108,13 @@
>>   	__ALTERNATIVE_CFG(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1)	\
>>   	ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)
>>   
>> +#define __ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1,	\
>> +				   new_c_2, vendor_id_2, errata_id_2, enable_2, \
>> +				   new_c_3, vendor_id_3, errata_id_3, enable_3)	\
>> +	__ALTERNATIVE_CFG(old_c, new_c_1, vendor_id_1, errata_id_1, enable_1)	\
>> +	ALT_NEW_CONTENT(vendor_id_2, errata_id_2, enable_2, new_c_2)		\
>> +	ALT_NEW_CONTENT(vendor_id_3, errata_id_3, enable_3, new_c_3)
>> +	
>>   #endif /* __ASSEMBLY__ */
>>   
>>   #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k)	\
>> @@ -108,6 +125,13 @@
>>   	__ALTERNATIVE_CFG_2(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1),	\
>>   				   new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2))
>>   
>    ^ there's also trailing whitespace here that git am complains about.
> 
>> +#define _ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, CONFIG_k_1,		\
>> +				  new_c_2, vendor_id_2, errata_id_2, CONFIG_k_2,		\
>> +				  new_c_3, vendor_id_3, errata_id_3, CONFIG_k_3)		\
>> +	__ALTERNATIVE_CFG_3(old_c, new_c_1, vendor_id_1, errata_id_1, IS_ENABLED(CONFIG_k_1),	\
>> +				   new_c_2, vendor_id_2, errata_id_2, IS_ENABLED(CONFIG_k_2),   \
>> +				   new_c_3, vendor_id_3, errata_id_3, IS_ENABLED(CONFIG_k_3))
>> +	
>>   #else /* CONFIG_RISCV_ALTERNATIVE */
>>   #ifdef __ASSEMBLY__
>>   
>> @@ -121,6 +145,9 @@
>>   #define _ALTERNATIVE_CFG_2(old_c, ...)	\
>>   	ALTERNATIVE_CFG old_c
>>   
>    ^ and here too.
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html


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^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] riscv: mm: add pgprot_dmacoherent for zicbom
  2023-03-07 20:58 ` [PATCH 2/2] riscv: mm: add pgprot_dmacoherent for zicbom Ben Dooks
@ 2023-03-08  9:35   ` Ben Dooks
  2023-03-08 10:13     ` Conor Dooley
  2023-03-08 13:19     ` heiko
  0 siblings, 2 replies; 10+ messages in thread
From: Ben Dooks @ 2023-03-08  9:35 UTC (permalink / raw)
  To: linux-riscv; +Cc: palmer, aou, heiko.stuebner, conor.dooley, ajones

On 07/03/2023 20:58, Ben Dooks wrote:
> If the system uses both ZICBOM and SVPBMT then currently SVPBMT will be
> used for DMA allocated memory even though ZICBOM gives us the cache ops
> to use cached memory and clean/flush them as needed by the DMA code.
> 
> Fix this by adding pgprot_dmacoherent() which is used by the allocator
> code to map the dma memory, thus allowing the return of suitably mapped
> memory for any use of dma_alloc_attrs() code. This s uses the added
> riscv_page_dmacoherent() which will work out the correct page flags to
> return using ALT_SVPBMT_ZICBOM() to runtime patch the right result.
> 
> Note, we can't just disable SVPBMT as it will be neede for things like
> ioremap() which don't have assoicated cache management operations.
> 
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
>   arch/riscv/include/asm/errata_list.h | 16 ++++++++++++++++
>   arch/riscv/include/asm/pgtable-64.h  | 10 ++++++++++
>   2 files changed, 26 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index fb1a810f3d8c..49ed2e7984a7 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -62,6 +62,22 @@ asm(ALTERNATIVE_2("li %0, 0\t\nnop",					\
>   		  "I"(ALT_SVPBMT_SHIFT),				\
>   		  "I"(ALT_THEAD_PBMT_SHIFT))
>   
> +#define ALT_SVPBMT_ZICBOM(_val, prot)					\
> +asm(ALTERNATIVE_3("li %0, 0\t\nnop",					\
> +		  "li %0, %1\t\nslli %0,%0,%3", 0,			\
> +			RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,	\
> +		  "li %0, 0\t\nnop", 0,					\
> +			RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM,	\

so, I tink this needs to be selected on CONFIG_RISCV_DMA_NONCOHERENT
as just having ZICBOM in the ISA isn't enough to actually use it, you'll
need the dma-noncoherent.o being built to do the cache management.

> +		  "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID,	\
> +			ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)	\
> +		: "=r"(_val)						\
> +		: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),		\
> +		  "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
> +		  "I"(ALT_SVPBMT_SHIFT),				\
> +		  "I"(ALT_THEAD_PBMT_SHIFT))
> +
> +
> +
>   #ifdef CONFIG_ERRATA_THEAD_PBMT
>   /*
>    * IO/NOCACHE memory types are handled together with svpbmt,
> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> index 42a042c0e13e..e0d2e5fda5a4 100644
> --- a/arch/riscv/include/asm/pgtable-64.h
> +++ b/arch/riscv/include/asm/pgtable-64.h
> @@ -126,10 +126,20 @@ static inline u64 riscv_page_io(void)
>   	return val;
>   }
>   
> +static inline u64 riscv_page_dmacoherent(void)
> +{
> +	u64 val;
> +
> +	ALT_SVPBMT_ZICBOM(val, _PAGE_IO);
> +	return val;
> +}
> +
>   #define _PAGE_NOCACHE		riscv_page_nocache()
>   #define _PAGE_IO		riscv_page_io()
>   #define _PAGE_MTMASK		riscv_page_mtmask()
>   
> +#define pgprot_dmacoherent(__prot) __pgprot(pgprot_val(__prot) | riscv_page_dmacoherent())
> +
>   /* Set of bits to preserve across pte_modify() */
>   #define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
>   					  _PAGE_WRITE | _PAGE_EXEC |	\

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html


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^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] riscv: mm: add pgprot_dmacoherent for zicbom
  2023-03-08  9:35   ` Ben Dooks
@ 2023-03-08 10:13     ` Conor Dooley
  2023-03-08 13:19     ` heiko
  1 sibling, 0 replies; 10+ messages in thread
From: Conor Dooley @ 2023-03-08 10:13 UTC (permalink / raw)
  To: Ben Dooks; +Cc: linux-riscv, palmer, aou, heiko.stuebner, conor.dooley, ajones


[-- Attachment #1.1: Type: text/plain, Size: 4184 bytes --]

On Wed, Mar 08, 2023 at 09:35:14AM +0000, Ben Dooks wrote:
> On 07/03/2023 20:58, Ben Dooks wrote:
> > If the system uses both ZICBOM and SVPBMT then currently SVPBMT will be
> > used for DMA allocated memory even though ZICBOM gives us the cache ops
> > to use cached memory and clean/flush them as needed by the DMA code.
> > 
> > Fix this by adding pgprot_dmacoherent() which is used by the allocator
> > code to map the dma memory, thus allowing the return of suitably mapped
> > memory for any use of dma_alloc_attrs() code. This s uses the added
> > riscv_page_dmacoherent() which will work out the correct page flags to
> > return using ALT_SVPBMT_ZICBOM() to runtime patch the right result.
> > 
> > Note, we can't just disable SVPBMT as it will be neede for things like
> > ioremap() which don't have assoicated cache management operations.
> > 
> > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> > ---
> >   arch/riscv/include/asm/errata_list.h | 16 ++++++++++++++++
> >   arch/riscv/include/asm/pgtable-64.h  | 10 ++++++++++
> >   2 files changed, 26 insertions(+)
> > 
> > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > index fb1a810f3d8c..49ed2e7984a7 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -62,6 +62,22 @@ asm(ALTERNATIVE_2("li %0, 0\t\nnop",					\
> >   		  "I"(ALT_SVPBMT_SHIFT),				\
> >   		  "I"(ALT_THEAD_PBMT_SHIFT))
> > +#define ALT_SVPBMT_ZICBOM(_val, prot)					\
> > +asm(ALTERNATIVE_3("li %0, 0\t\nnop",					\
> > +		  "li %0, %1\t\nslli %0,%0,%3", 0,			\
> > +			RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,	\
> > +		  "li %0, 0\t\nnop", 0,					\
> > +			RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM,	\
> 
> so, I tink this needs to be selected on CONFIG_RISCV_DMA_NONCOHERENT
> as just having ZICBOM in the ISA isn't enough to actually use it, you'll
> need the dma-noncoherent.o being built to do the cache management.

I think we are okay here w/ ZICBOM, as it selects RISCV_DMA_NONCOHERENT:
config RISCV_ISA_ZICBOM
	bool "Zicbom extension support for non-coherent DMA operation"
	depends on !XIP_KERNEL && MMU
	default y
	select RISCV_ALTERNATIVE
	select RISCV_DMA_NONCOHERENT

In fact, I think that RISCV_DMA_NONCOHERENT would not be correct here,
as the THEAD CMO erratum selects RISCV_DMA_NONCOHERENT, so its presence
doesn't mean that the kernel supports Zicbom.

> > +		  "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID,	\
> > +			ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)	\
> > +		: "=r"(_val)						\
> > +		: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),		\
> > +		  "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
> > +		  "I"(ALT_SVPBMT_SHIFT),				\
> > +		  "I"(ALT_THEAD_PBMT_SHIFT))
> > +
> > +
> > +
> >   #ifdef CONFIG_ERRATA_THEAD_PBMT
> >   /*
> >    * IO/NOCACHE memory types are handled together with svpbmt,
> > diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> > index 42a042c0e13e..e0d2e5fda5a4 100644
> > --- a/arch/riscv/include/asm/pgtable-64.h
> > +++ b/arch/riscv/include/asm/pgtable-64.h
> > @@ -126,10 +126,20 @@ static inline u64 riscv_page_io(void)
> >   	return val;
> >   }
> > +static inline u64 riscv_page_dmacoherent(void)
> > +{
> > +	u64 val;
> > +
> > +	ALT_SVPBMT_ZICBOM(val, _PAGE_IO);
> > +	return val;
> > +}
> > +
> >   #define _PAGE_NOCACHE		riscv_page_nocache()
> >   #define _PAGE_IO		riscv_page_io()
> >   #define _PAGE_MTMASK		riscv_page_mtmask()
> > +#define pgprot_dmacoherent(__prot) __pgprot(pgprot_val(__prot) | riscv_page_dmacoherent())
> > +
> >   /* Set of bits to preserve across pte_modify() */
> >   #define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
> >   					  _PAGE_WRITE | _PAGE_EXEC |	\
> 
> -- 
> Ben Dooks				http://www.codethink.co.uk/
> Senior Engineer				Codethink - Providing Genius
> 
> https://www.codethink.co.uk/privacy.html
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

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^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] riscv: mm: add pgprot_dmacoherent for zicbom
  2023-03-08  9:35   ` Ben Dooks
  2023-03-08 10:13     ` Conor Dooley
@ 2023-03-08 13:19     ` heiko
  2023-03-08 14:48       ` Ben Dooks
  1 sibling, 1 reply; 10+ messages in thread
From: heiko @ 2023-03-08 13:19 UTC (permalink / raw)
  To: linux-riscv; +Cc: palmer, aou, conor.dooley, ajones, Ben Dooks

Am Mittwoch, 8. März 2023, 10:35:14 CET schrieb Ben Dooks:
> On 07/03/2023 20:58, Ben Dooks wrote:
> > If the system uses both ZICBOM and SVPBMT then currently SVPBMT will be
> > used for DMA allocated memory even though ZICBOM gives us the cache ops
> > to use cached memory and clean/flush them as needed by the DMA code.
> > 
> > Fix this by adding pgprot_dmacoherent() which is used by the allocator
> > code to map the dma memory, thus allowing the return of suitably mapped
> > memory for any use of dma_alloc_attrs() code. This s uses the added
> > riscv_page_dmacoherent() which will work out the correct page flags to
> > return using ALT_SVPBMT_ZICBOM() to runtime patch the right result.
> > 
> > Note, we can't just disable SVPBMT as it will be neede for things like
> > ioremap() which don't have assoicated cache management operations.
> > 
> > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> > ---
> >   arch/riscv/include/asm/errata_list.h | 16 ++++++++++++++++
> >   arch/riscv/include/asm/pgtable-64.h  | 10 ++++++++++
> >   2 files changed, 26 insertions(+)
> > 
> > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> > index fb1a810f3d8c..49ed2e7984a7 100644
> > --- a/arch/riscv/include/asm/errata_list.h
> > +++ b/arch/riscv/include/asm/errata_list.h
> > @@ -62,6 +62,22 @@ asm(ALTERNATIVE_2("li %0, 0\t\nnop",					\
> >   		  "I"(ALT_SVPBMT_SHIFT),				\
> >   		  "I"(ALT_THEAD_PBMT_SHIFT))
> >   
> > +#define ALT_SVPBMT_ZICBOM(_val, prot)					\
> > +asm(ALTERNATIVE_3("li %0, 0\t\nnop",					\
> > +		  "li %0, %1\t\nslli %0,%0,%3", 0,			\
> > +			RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,	\
> > +		  "li %0, 0\t\nnop", 0,					\
> > +			RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM,	\
> 
> so, I tink this needs to be selected on CONFIG_RISCV_DMA_NONCOHERENT
> as just having ZICBOM in the ISA isn't enough to actually use it, you'll
> need the dma-noncoherent.o being built to do the cache management.

CONFIG_RISCV_ISA_ZICBOM does a
	select RISCV_DMA_NONCOHERENT
same as CONFIG_ERRATA_THEAD_CMO

So dma-noncoherent gets build if you enable at least one of them.
What am I missing?


> > +		  "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID,	\
> > +			ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT)	\
> > +		: "=r"(_val)						\
> > +		: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT),		\
> > +		  "I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT),		\
> > +		  "I"(ALT_SVPBMT_SHIFT),				\
> > +		  "I"(ALT_THEAD_PBMT_SHIFT))
> > +
> > +
> > +
> >   #ifdef CONFIG_ERRATA_THEAD_PBMT
> >   /*
> >    * IO/NOCACHE memory types are handled together with svpbmt,
> > diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> > index 42a042c0e13e..e0d2e5fda5a4 100644
> > --- a/arch/riscv/include/asm/pgtable-64.h
> > +++ b/arch/riscv/include/asm/pgtable-64.h
> > @@ -126,10 +126,20 @@ static inline u64 riscv_page_io(void)
> >   	return val;
> >   }
> >   
> > +static inline u64 riscv_page_dmacoherent(void)
> > +{
> > +	u64 val;
> > +
> > +	ALT_SVPBMT_ZICBOM(val, _PAGE_IO);
> > +	return val;
> > +}
> > +
> >   #define _PAGE_NOCACHE		riscv_page_nocache()
> >   #define _PAGE_IO		riscv_page_io()
> >   #define _PAGE_MTMASK		riscv_page_mtmask()
> >   
> > +#define pgprot_dmacoherent(__prot) __pgprot(pgprot_val(__prot) | riscv_page_dmacoherent())
> > +
> >   /* Set of bits to preserve across pte_modify() */
> >   #define _PAGE_CHG_MASK  (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ |	\
> >   					  _PAGE_WRITE | _PAGE_EXEC |	\
> 
> 





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^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] riscv: mm: add pgprot_dmacoherent for zicbom
  2023-03-08 13:19     ` heiko
@ 2023-03-08 14:48       ` Ben Dooks
  2023-03-24 17:30         ` Ben Dooks
  0 siblings, 1 reply; 10+ messages in thread
From: Ben Dooks @ 2023-03-08 14:48 UTC (permalink / raw)
  To: heiko, linux-riscv; +Cc: palmer, aou, conor.dooley, ajones

On 08/03/2023 13:19, heiko@sntech.de wrote:
> Am Mittwoch, 8. März 2023, 10:35:14 CET schrieb Ben Dooks:
>> On 07/03/2023 20:58, Ben Dooks wrote:
>>> If the system uses both ZICBOM and SVPBMT then currently SVPBMT will be
>>> used for DMA allocated memory even though ZICBOM gives us the cache ops
>>> to use cached memory and clean/flush them as needed by the DMA code.
>>>
>>> Fix this by adding pgprot_dmacoherent() which is used by the allocator
>>> code to map the dma memory, thus allowing the return of suitably mapped
>>> memory for any use of dma_alloc_attrs() code. This s uses the added
>>> riscv_page_dmacoherent() which will work out the correct page flags to
>>> return using ALT_SVPBMT_ZICBOM() to runtime patch the right result.
>>>
>>> Note, we can't just disable SVPBMT as it will be neede for things like
>>> ioremap() which don't have assoicated cache management operations.
>>>
>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>> ---
>>>    arch/riscv/include/asm/errata_list.h | 16 ++++++++++++++++
>>>    arch/riscv/include/asm/pgtable-64.h  | 10 ++++++++++
>>>    2 files changed, 26 insertions(+)
>>>
>>> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
>>> index fb1a810f3d8c..49ed2e7984a7 100644
>>> --- a/arch/riscv/include/asm/errata_list.h
>>> +++ b/arch/riscv/include/asm/errata_list.h
>>> @@ -62,6 +62,22 @@ asm(ALTERNATIVE_2("li %0, 0\t\nnop",					\
>>>    		  "I"(ALT_SVPBMT_SHIFT),				\
>>>    		  "I"(ALT_THEAD_PBMT_SHIFT))
>>>    
>>> +#define ALT_SVPBMT_ZICBOM(_val, prot)					\
>>> +asm(ALTERNATIVE_3("li %0, 0\t\nnop",					\
>>> +		  "li %0, %1\t\nslli %0,%0,%3", 0,			\
>>> +			RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,	\
>>> +		  "li %0, 0\t\nnop", 0,					\
>>> +			RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM,	\
>>
>> so, I tink this needs to be selected on CONFIG_RISCV_DMA_NONCOHERENT
>> as just having ZICBOM in the ISA isn't enough to actually use it, you'll
>> need the dma-noncoherent.o being built to do the cache management.
> 
> CONFIG_RISCV_ISA_ZICBOM does a
> 	select RISCV_DMA_NONCOHERENT
> same as CONFIG_ERRATA_THEAD_CMO
> 
> So dma-noncoherent gets build if you enable at least one of them.
> What am I missing?

Ah, I think (and Connor also pointed out) that currently the config
is selceted from either user of the dma-noncoherent.c code. I think
thereore we can probably keep this as is.

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html


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^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] riscv: mm: add pgprot_dmacoherent for zicbom
  2023-03-08 14:48       ` Ben Dooks
@ 2023-03-24 17:30         ` Ben Dooks
  0 siblings, 0 replies; 10+ messages in thread
From: Ben Dooks @ 2023-03-24 17:30 UTC (permalink / raw)
  To: heiko, linux-riscv; +Cc: palmer, aou, conor.dooley, ajones

On 08/03/2023 14:48, Ben Dooks wrote:
> On 08/03/2023 13:19, heiko@sntech.de wrote:
>> Am Mittwoch, 8. März 2023, 10:35:14 CET schrieb Ben Dooks:
>>> On 07/03/2023 20:58, Ben Dooks wrote:
>>>> If the system uses both ZICBOM and SVPBMT then currently SVPBMT will be
>>>> used for DMA allocated memory even though ZICBOM gives us the cache ops
>>>> to use cached memory and clean/flush them as needed by the DMA code.
>>>>
>>>> Fix this by adding pgprot_dmacoherent() which is used by the allocator
>>>> code to map the dma memory, thus allowing the return of suitably mapped
>>>> memory for any use of dma_alloc_attrs() code. This s uses the added
>>>> riscv_page_dmacoherent() which will work out the correct page flags to
>>>> return using ALT_SVPBMT_ZICBOM() to runtime patch the right result.
>>>>
>>>> Note, we can't just disable SVPBMT as it will be neede for things like
>>>> ioremap() which don't have assoicated cache management operations.
>>>>
>>>> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
>>>> ---
>>>>    arch/riscv/include/asm/errata_list.h | 16 ++++++++++++++++
>>>>    arch/riscv/include/asm/pgtable-64.h  | 10 ++++++++++
>>>>    2 files changed, 26 insertions(+)
>>>>
>>>> diff --git a/arch/riscv/include/asm/errata_list.h 
>>>> b/arch/riscv/include/asm/errata_list.h
>>>> index fb1a810f3d8c..49ed2e7984a7 100644
>>>> --- a/arch/riscv/include/asm/errata_list.h
>>>> +++ b/arch/riscv/include/asm/errata_list.h
>>>> @@ -62,6 +62,22 @@ asm(ALTERNATIVE_2("li %0, 
>>>> 0\t\nnop",                    \
>>>>              "I"(ALT_SVPBMT_SHIFT),                \
>>>>              "I"(ALT_THEAD_PBMT_SHIFT))
>>>> +#define ALT_SVPBMT_ZICBOM(_val, prot)                    \
>>>> +asm(ALTERNATIVE_3("li %0, 0\t\nnop",                    \
>>>> +          "li %0, %1\t\nslli %0,%0,%3", 0,            \
>>>> +            RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT,    \
>>>> +          "li %0, 0\t\nnop", 0,                    \
>>>> +            RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM,    \
>>>
>>> so, I tink this needs to be selected on CONFIG_RISCV_DMA_NONCOHERENT
>>> as just having ZICBOM in the ISA isn't enough to actually use it, you'll
>>> need the dma-noncoherent.o being built to do the cache management.
>>
>> CONFIG_RISCV_ISA_ZICBOM does a
>>     select RISCV_DMA_NONCOHERENT
>> same as CONFIG_ERRATA_THEAD_CMO
>>
>> So dma-noncoherent gets build if you enable at least one of them.
>> What am I missing?
> 
> Ah, I think (and Connor also pointed out) that currently the config
> is selceted from either user of the dma-noncoherent.c code. I think
> thereore we can probably keep this as is

After a discussion with Arnd it looks like I was using the DMA api
wrong and was after dma_alloc_noncoherent or similar.

These patches can be dropped

-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html


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^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-03-24 17:30 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-07 20:58 ZICBOM and SVPBMT in same system Ben Dooks
2023-03-07 20:58 ` [PATCH 1/2] riscv: alternatives: add 3-config alternative set Ben Dooks
2023-03-07 21:31   ` Conor Dooley
2023-03-08  9:34     ` Ben Dooks
2023-03-07 20:58 ` [PATCH 2/2] riscv: mm: add pgprot_dmacoherent for zicbom Ben Dooks
2023-03-08  9:35   ` Ben Dooks
2023-03-08 10:13     ` Conor Dooley
2023-03-08 13:19     ` heiko
2023-03-08 14:48       ` Ben Dooks
2023-03-24 17:30         ` Ben Dooks

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