[PATCH v1 00/18] Permission Indirection Extension

[PATCH v1 00/18] Permission Indirection Extension

[Joey Gouly]

Hi all,

This series implements the Permission Indirection Extension introduced in 2022
VMSA enhancements [1].

The Permission Indirection Extension is a new way to set memory permissions.
Instead of directly encoding the permission in the Page Table Entry (PTE),
fields in the PTEs are used to index into an array of permissions specified in
a register. This indirection provides greater flexibility, greater encoding
density and enables the representation of new permissions.

The PTEs bit that are repurposed for use with permission indirection are:
	54 PTE_UXN
	53 PTE_PXN
	51 PTE_DBM
	6 PTE_USER

The way that PIE is implemented in this patchset is that the encodings are
picked such that they match how Linux currently sets the bits in the PTEs, so
none of the page table handling has changed. This means this patchset keeps the
same functionality as currently implemented, but allows for future expansion.

Enabling PIE is also a prerequisite for implementing the Guarded Control Stack
Extension (GCS).

Another related extension is the Permission Overlay Extension, which is not
covered by this patch set, but is mentioned in patch 5 as half of PIE encoding
values apply an overlay. However, since overlays are not currently enabled, they
act as all the other permissions do.

This first few patches are adding the new system registers, and cpufeature
capabilities. Then KVM support for save/restore of the new registers is added.
Finally the new Permission Indirection registers are set and the new feature is
enabled.

There's two series on the ML that conflict-ish, but I don't think either will
tough to rework against:
  Kristina's series which changes how HCRX_EL2 works [2]
  Mark's commit to switch HFGxTR to automatic generation [3]

Thanks,
Joey

[1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022
[2] https://lore.kernel.org/linux-arm-kernel/20230216160012.272345-1-kristina.martsenko@arm.com/
[3] https://lore.kernel.org/linux-arm-kernel/20230306-arm64-fgt-reg-gen-v1-1-95bc0c97cfed@kernel.org/

Joey Gouly (18):
  arm64/sysreg: Add ID register ID_AA64MMFR3
  arm64/sysreg: add system registers TCR2_ELx
  arm64/sysreg: add TCR2En to HCRX_EL2
  arm64/sysreg: add HFGxTR_EL2 bits for Permission Indirection Extension
  arm64/sysreg: add PIR*_ELx registers
  arm64: cpufeature: add system register ID_AA64MMFR3
  arm64: cpufeature: add TCR2 cpucap
  arm64: cpufeature: add Permission Indirection Extension cpucap
  KVM: arm64: Save/restore TCR2_EL1
  KVM: arm64: Save/restore PIE registers
  KVM: arm64: expose ID_AA64MMFR3_EL1 to guests
  arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS
  arm64: add PTE_WRITE to PROT_SECT_NORMAL
  arm64: reorganise PAGE_/PROT_ macros
  arm64: disable EL2 traps for PIE
  arm64: add encodings of PIRx_ELx registers
  arm64: enable Permission Indirection Extension (PIE)
  arm64: transfer permission indirection settings to EL2

 arch/arm64/include/asm/cpu.h               |   1 +
 arch/arm64/include/asm/el2_setup.h         |  27 ++++-
 arch/arm64/include/asm/kernel-pgtable.h    |   4 +-
 arch/arm64/include/asm/kvm_host.h          |   5 +
 arch/arm64/include/asm/pgtable-hwdef.h     |   8 ++
 arch/arm64/include/asm/pgtable-prot.h      |  90 ++++++++++-----
 arch/arm64/include/asm/pgtable.h           |   6 +
 arch/arm64/include/asm/sysreg.h            |  23 ++++
 arch/arm64/kernel/cpufeature.c             |  32 ++++++
 arch/arm64/kernel/cpuinfo.c                |   1 +
 arch/arm64/kernel/head.S                   |   8 +-
 arch/arm64/kernel/hyp-stub.S               |  18 +++
 arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h |  12 ++
 arch/arm64/kvm/sys_regs.c                  |   2 +-
 arch/arm64/mm/proc.S                       |  17 ++-
 arch/arm64/tools/cpucaps                   |   2 +
 arch/arm64/tools/sysreg                    | 127 ++++++++++++++++++++-
 17 files changed, 345 insertions(+), 38 deletions(-)

-- 
2.17.1


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[PATCH v1 01/18] arm64/sysreg: Add ID register ID_AA64MMFR3

[Joey Gouly]

Add the new ID register ID_AA64MMFR3.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
---
 arch/arm64/tools/sysreg | 64 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index dd5a9c7e310f..a444579a8d2f 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1515,6 +1515,70 @@ UnsignedEnum	3:0	CnP
 EndEnum
 EndSysreg
 
+Sysreg	ID_AA64MMFR3_EL1	3	0	0	7	3
+Enum	63:60	Spec_FPACC
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	59:56	ADERR
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	55:52	SDERR
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Res0	51:48
+Enum	47:44	ANERR
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	43:40	SNERR
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	39:36	D128_2
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	35:32	D128
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	31:28	MEC
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	27:24	AIE
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	23:20	S2POE
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	19:16	S1POE
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	15:12	S2PIE
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	11:8	S1PIE
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	7:4	SCTLRX
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	3:0	TCRX
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+EndSysreg
+
 Sysreg	SCTLR_EL1	3	0	1	0	0
 Field	63	TIDCP
 Field	62	SPINTMASK
-- 
2.17.1


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[PATCH v1 02/18] arm64/sysreg: add system registers TCR2_ELx

[Joey Gouly]

Add definitions of TCR2_EL1 and TCR2_EL12 registers.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
---
 arch/arm64/tools/sysreg | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index a444579a8d2f..0c3a6790842a 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2050,6 +2050,30 @@ Sysreg	TTBR1_EL1	3	0	2	0	1
 Fields	TTBRx_EL1
 EndSysreg
 
+SysregFields	TCR2_ELx
+Res0	63:16
+Field	15	DisCH1
+Field	14	DisCH0
+Res0	13:12
+Field	11	HAFT
+Field	10	PTTWI
+Res0	9:6
+Field	5	D128
+Field	4	AIE
+Field	3	POE
+Field	2	E0POE
+Field	1	PIE
+Field	0	PnCH
+EndSysregFields
+
+Sysreg	TCR2_EL1	3	0	2	0	3
+Fields	TCR2_ELx
+EndSysreg
+
+Sysreg	TCR2_EL12	3	5	2	0	3
+Fields	TCR2_ELx
+EndSysreg
+
 Sysreg	LORSA_EL1	3	0	10	4	0
 Res0	63:52
 Field	51:16	SA
-- 
2.17.1


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[PATCH v1 03/18] arm64/sysreg: add TCR2En to HCRX_EL2

[Joey Gouly]

This bit controls the trapping of TCR2_EL1 to EL2.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
---
 arch/arm64/tools/sysreg | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 0c3a6790842a..1d9805239a73 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1935,7 +1935,9 @@ Fields	ZCR_ELx
 EndSysreg
 
 Sysreg	HCRX_EL2	3	4	1	2	2
-Res0	63:12
+Res0	63:15
+Field	14	TCR2En
+Res0	13:12
 Field	11	MSCEn
 Field	10	MCE2
 Field	9	CMOW
-- 
2.17.1


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[PATCH v1 04/18] arm64/sysreg: add HFGxTR_EL2 bits for Permission Indirection Extension

[Joey Gouly]

Add the trap bit definitions for nPIR_EL1 and nPIRE0_EL1.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 9e3ecba3c4e6..cb9e387e39e0 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -759,6 +759,10 @@
 #define ICH_VTR_TDS_MASK	(1 << ICH_VTR_TDS_SHIFT)
 
 /* HFG[WR]TR_EL2 bit definitions */
+#define HFGxTR_EL2_nPIR_EL0_SHIFT	58
+#define HFGxTR_EL2_nPIR_EL0_MASK	BIT_MASK(HFGxTR_EL2_nPIR_EL0_SHIFT)
+#define HFGxTR_EL2_nPIREO_EL0_SHIFT	57
+#define HFGxTR_EL2_nPIREO_EL0_MASK	BIT_MASK(HFGxTR_EL2_nPIREO_EL0_SHIFT)
 #define HFGxTR_EL2_nTPIDR2_EL0_SHIFT	55
 #define HFGxTR_EL2_nTPIDR2_EL0_MASK	BIT_MASK(HFGxTR_EL2_nTPIDR2_EL0_SHIFT)
 #define HFGxTR_EL2_nSMPRI_EL1_SHIFT	54
-- 
2.17.1


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[PATCH v1 05/18] arm64/sysreg: add PIR*_ELx registers

[Joey Gouly]

Add definitions of PIR_EL1, PIR_EL12, PIRE0_EL1, PIRE0_EL12 registers.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 19 ++++++++++++++++++
 arch/arm64/tools/sysreg         | 35 +++++++++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index cb9e387e39e0..538b2368e3bc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -768,6 +768,25 @@
 #define HFGxTR_EL2_nSMPRI_EL1_SHIFT	54
 #define HFGxTR_EL2_nSMPRI_EL1_MASK	BIT_MASK(HFGxTR_EL2_nSMPRI_EL1_SHIFT)
 
+/*
+ * Permission Indirection Extension (PIE) permission encodings.
+ * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension).
+ */
+#define PIE_NONE_O	0x0
+#define PIE_R_O		0x1
+#define PIE_X_O		0x2
+#define PIE_RX_O	0x3
+#define PIE_RW_O	0x5
+#define PIE_RWnX_O	0x6
+#define PIE_RWX_O	0x7
+#define PIE_R		0x8
+#define PIE_GCS		0x9
+#define PIE_RX		0xa
+#define PIE_RW		0xc
+#define PIE_RWX		0xe
+
+#define PIRx_ELx_PERMIDX(perm, idx)	((perm) << ((idx) * 4))
+
 #define ARM64_FEATURE_FIELD_BITS	4
 
 /* Defined for compatibility only, do not add new users. */
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 1d9805239a73..446cc52d7317 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2076,6 +2076,41 @@ Sysreg	TCR2_EL12	3	5	2	0	3
 Fields	TCR2_ELx
 EndSysreg
 
+SysregFields PIRx_ELx
+Field	63:60	Perm15
+Field	59:56	Perm14
+Field	55:52	Perm13
+Field	51:48	Perm12
+Field	47:44	Perm11
+Field	43:40	Perm10
+Field	39:36	Perm9
+Field	35:32	Perm8
+Field	31:28	Perm7
+Field	27:24	Perm6
+Field	23:20	Perm5
+Field	19:16	Perm4
+Field	15:12	Perm3
+Field	11:8	Perm2
+Field	7:4	Perm1
+Field	3:0	Perm0
+EndSysregFields
+
+Sysreg	PIRE0_EL1	3	0	10	2	2
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	PIRE0_EL12	3	5	10	2	2
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	PIR_EL1		3	0	10	2	3
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	PIR_EL12	3	5	10	2	3
+Fields	PIRx_ELx
+EndSysreg
+
 Sysreg	LORSA_EL1	3	0	10	4	0
 Res0	63:52
 Field	51:16	SA
-- 
2.17.1


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[PATCH v1 06/18] arm64: cpufeature: add system register ID_AA64MMFR3

[Joey Gouly]

Add new system register ID_AA64MMFR3 to the cpufeature infrastructure.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
 arch/arm64/include/asm/cpu.h   |  1 +
 arch/arm64/kernel/cpufeature.c | 11 +++++++++++
 arch/arm64/kernel/cpuinfo.c    |  1 +
 3 files changed, 13 insertions(+)

diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
index fd7a92219eea..e749838b9c5d 100644
--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
@@ -56,6 +56,7 @@ struct cpuinfo_arm64 {
 	u64		reg_id_aa64mmfr0;
 	u64		reg_id_aa64mmfr1;
 	u64		reg_id_aa64mmfr2;
+	u64		reg_id_aa64mmfr3;
 	u64		reg_id_aa64pfr0;
 	u64		reg_id_aa64pfr1;
 	u64		reg_id_aa64zfr0;
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 2e3e55139777..9590335b2ce0 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -389,6 +389,12 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 	ARM64_FTR_END,
 };
 
+static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0),
+	ARM64_FTR_END,
+};
+
 static const struct arm64_ftr_bits ftr_ctr[] = {
 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1),
@@ -715,6 +721,7 @@ static const struct __ftr_reg_entry {
 	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
 			       &id_aa64mmfr1_override),
 	ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
+	ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3),
 
 	/* Op1 = 0, CRn = 1, CRm = 2 */
 	ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
@@ -1010,6 +1017,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
 	init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 	init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 	init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
+	init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3);
 	init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 	init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 	init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
@@ -1255,6 +1263,8 @@ void update_cpu_features(int cpu,
 				      info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 				      info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
+	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu,
+				      info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3);
 
 	taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 				      info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
@@ -1384,6 +1394,7 @@ u64 __read_sysreg_by_encoding(u32 sys_id)
 	read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 	read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 	read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
+	read_sysreg_case(SYS_ID_AA64MMFR3_EL1);
 	read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 	read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 	read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index eb4378c23b3c..9937614c3deb 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -446,6 +446,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
 	info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
 	info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
 	info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
+	info->reg_id_aa64mmfr3 = read_cpuid(ID_AA64MMFR3_EL1);
 	info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
 	info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
 	info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1);
-- 
2.17.1


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[PATCH v1 07/18] arm64: cpufeature: add TCR2 cpucap

[Joey Gouly]

This capability indicates if the system supports the TCR2_ELx system register.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
 arch/arm64/kernel/cpufeature.c | 10 ++++++++++
 arch/arm64/tools/cpucaps       |  1 +
 2 files changed, 11 insertions(+)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9590335b2ce0..6944d8bbb17c 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2783,6 +2783,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.matches = has_cpuid_feature,
 		.cpu_enable = cpu_enable_dit,
 	},
+	{
+		.capability = ARM64_HAS_TCR2,
+		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
+		.sys_reg = SYS_ID_AA64MMFR3_EL1,
+		.sign = FTR_UNSIGNED,
+		.field_pos = ID_AA64MMFR3_EL1_TCRX_SHIFT,
+		.field_width = 4,
+		.min_field_value = ID_AA64MMFR3_EL1_TCRX_IMP,
+		.matches = has_cpuid_feature,
+	},
 	{},
 };
 
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 37b1340e9646..5859b9ee7444 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -41,6 +41,7 @@ HAS_RAS_EXTN
 HAS_RNG
 HAS_SB
 HAS_STAGE2_FWB
+HAS_TCR2
 HAS_TIDCP1
 HAS_TLB_RANGE
 HAS_VIRT_HOST_EXTN
-- 
2.17.1


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[PATCH v1 08/18] arm64: cpufeature: add Permission Indirection Extension cpucap

[Joey Gouly]

This indicates if the system supports PIE. This is a CPUCAP_BOOT_CPU_FEATURE
as the boot CPU will enable PIE if it has it, so secondary CPUs must also
have this feature.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
 arch/arm64/kernel/cpufeature.c | 11 +++++++++++
 arch/arm64/tools/cpucaps       |  1 +
 2 files changed, 12 insertions(+)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 6944d8bbb17c..acbc21963128 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2793,6 +2793,17 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.min_field_value = ID_AA64MMFR3_EL1_TCRX_IMP,
 		.matches = has_cpuid_feature,
 	},
+	{
+		.desc = "Permission Indirection Extension (PIE)",
+		.capability = ARM64_HAS_PIE,
+		.type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
+		.sys_reg = SYS_ID_AA64MMFR3_EL1,
+		.sign = FTR_UNSIGNED,
+		.field_pos = ID_AA64MMFR3_EL1_S1PIE_SHIFT,
+		.field_width = 4,
+		.min_field_value = ID_AA64MMFR3_EL1_S1PIE_IMP,
+		.matches = has_cpuid_feature,
+	},
 	{},
 };
 
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 5859b9ee7444..c4c4c59882b8 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -37,6 +37,7 @@ HAS_NESTED_VIRT
 HAS_NO_FPSIMD
 HAS_NO_HW_PREFETCH
 HAS_PAN
+HAS_PIE
 HAS_RAS_EXTN
 HAS_RNG
 HAS_SB
-- 
2.17.1


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[PATCH v1 09/18] KVM: arm64: Save/restore TCR2_EL1

[Joey Gouly]

Define the new system register TCR2_EL1 and context switch it.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Zenghui Yu <yuzenghui@huawei.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
 arch/arm64/include/asm/kvm_host.h          | 1 +
 arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 4 ++++
 2 files changed, 5 insertions(+)

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index a1892a8f6032..799857ba281d 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -266,6 +266,7 @@ enum vcpu_sysreg {
 	TTBR0_EL1,	/* Translation Table Base Register 0 */
 	TTBR1_EL1,	/* Translation Table Base Register 1 */
 	TCR_EL1,	/* Translation Control Register */
+	TCR2_EL1,	/* Extended Translation Control Register */
 	ESR_EL1,	/* Exception Syndrome Register */
 	AFSR0_EL1,	/* Auxiliary Fault Status Register 0 */
 	AFSR1_EL1,	/* Auxiliary Fault Status Register 1 */
diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
index 699ea1f8d409..16199a107a47 100644
--- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
+++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
@@ -44,6 +44,8 @@ static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
 	ctxt_sys_reg(ctxt, TTBR0_EL1)	= read_sysreg_el1(SYS_TTBR0);
 	ctxt_sys_reg(ctxt, TTBR1_EL1)	= read_sysreg_el1(SYS_TTBR1);
 	ctxt_sys_reg(ctxt, TCR_EL1)	= read_sysreg_el1(SYS_TCR);
+	if (cpus_have_final_cap(ARM64_HAS_TCR2))
+		ctxt_sys_reg(ctxt, TCR2_EL1)	= read_sysreg_el1(SYS_TCR2);
 	ctxt_sys_reg(ctxt, ESR_EL1)	= read_sysreg_el1(SYS_ESR);
 	ctxt_sys_reg(ctxt, AFSR0_EL1)	= read_sysreg_el1(SYS_AFSR0);
 	ctxt_sys_reg(ctxt, AFSR1_EL1)	= read_sysreg_el1(SYS_AFSR1);
@@ -114,6 +116,8 @@ static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
 	write_sysreg_el1(ctxt_sys_reg(ctxt, CPACR_EL1),	SYS_CPACR);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR0_EL1),	SYS_TTBR0);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, TTBR1_EL1),	SYS_TTBR1);
+	if (cpus_have_final_cap(ARM64_HAS_TCR2))
+		write_sysreg_el1(ctxt_sys_reg(ctxt, TCR2_EL1),	SYS_TCR2);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, ESR_EL1),	SYS_ESR);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR0_EL1),	SYS_AFSR0);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, AFSR1_EL1),	SYS_AFSR1);
-- 
2.17.1


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[PATCH v1 10/18] KVM: arm64: Save/restore PIE registers

[Joey Gouly]

Define the new system registers that PIE introduces and context switch them.
The PIE feature is still hidden from the ID register, and not exposed to a VM.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Zenghui Yu <yuzenghui@huawei.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
 arch/arm64/include/asm/kvm_host.h          | 4 ++++
 arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 8 ++++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 799857ba281d..4b8229942bc5 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -364,6 +364,10 @@ enum vcpu_sysreg {
 	CNTHCTL_EL2,	/* Counter-timer Hypervisor Control register */
 	SP_EL2,		/* EL2 Stack Pointer */
 
+	/* Permission Indirection Extension registers */
+	PIR_EL1,       /* Permission Indirection Register 1 (EL1) */
+	PIRE0_EL1,     /*  Permission Indirection Register 0 (EL1) */
+
 	NR_SYS_REGS	/* Nothing after this line! */
 };
 
diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
index 16199a107a47..99566bca19a9 100644
--- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
+++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
@@ -55,6 +55,10 @@ static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
 	ctxt_sys_reg(ctxt, CONTEXTIDR_EL1) = read_sysreg_el1(SYS_CONTEXTIDR);
 	ctxt_sys_reg(ctxt, AMAIR_EL1)	= read_sysreg_el1(SYS_AMAIR);
 	ctxt_sys_reg(ctxt, CNTKCTL_EL1)	= read_sysreg_el1(SYS_CNTKCTL);
+	if (cpus_have_final_cap(ARM64_HAS_PIE)) {
+		ctxt_sys_reg(ctxt, PIR_EL1)	= read_sysreg_el1(SYS_PIR);
+		ctxt_sys_reg(ctxt, PIRE0_EL1)	= read_sysreg_el1(SYS_PIRE0);
+	}
 	ctxt_sys_reg(ctxt, PAR_EL1)	= read_sysreg_par();
 	ctxt_sys_reg(ctxt, TPIDR_EL1)	= read_sysreg(tpidr_el1);
 
@@ -127,6 +131,10 @@ static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
 	write_sysreg_el1(ctxt_sys_reg(ctxt, CONTEXTIDR_EL1), SYS_CONTEXTIDR);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, AMAIR_EL1),	SYS_AMAIR);
 	write_sysreg_el1(ctxt_sys_reg(ctxt, CNTKCTL_EL1), SYS_CNTKCTL);
+	if (cpus_have_final_cap(ARM64_HAS_PIE)) {
+		write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1),	SYS_PIR);
+		write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1),	SYS_PIRE0);
+	}
 	write_sysreg(ctxt_sys_reg(ctxt, PAR_EL1),	par_el1);
 	write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL1),	tpidr_el1);
 
-- 
2.17.1


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[PATCH v1 11/18] KVM: arm64: expose ID_AA64MMFR3_EL1 to guests

[Joey Gouly]

Now that KVM context switches the appropriate registers, expose ID_AA64MMFR3_EL1
to guests to allow them to use the new features.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Zenghui Yu <yuzenghui@huawei.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
 arch/arm64/kvm/sys_regs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 53749d3a0996..db68841f3441 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1851,7 +1851,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 	ID_SANITISED(ID_AA64MMFR0_EL1),
 	ID_SANITISED(ID_AA64MMFR1_EL1),
 	ID_SANITISED(ID_AA64MMFR2_EL1),
-	ID_UNALLOCATED(7,3),
+	ID_SANITISED(ID_AA64MMFR3_EL1),
 	ID_UNALLOCATED(7,4),
 	ID_UNALLOCATED(7,5),
 	ID_UNALLOCATED(7,6),
-- 
2.17.1


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[PATCH v1 12/18] arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS

[Joey Gouly]

With PIE enabled, the swapper PTEs would have a Permission Indirection Index (PIIndex)
of 0. A PIIndex of 0 is not currently used by any other PTEs.

To avoid using index 0 specifically for the swapper PTEs, mark them as PTE_UXN
and PTE_WRITE, so that they map to a PAGE_KERNEL_EXEC equivalent.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
---
 arch/arm64/include/asm/kernel-pgtable.h | 4 ++--
 arch/arm64/kernel/head.S                | 8 ++++----
 arch/arm64/mm/proc.S                    | 2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h
index fcd14197756f..daf1909116f6 100644
--- a/arch/arm64/include/asm/kernel-pgtable.h
+++ b/arch/arm64/include/asm/kernel-pgtable.h
@@ -104,8 +104,8 @@
 /*
  * Initial memory map attributes.
  */
-#define SWAPPER_PTE_FLAGS	(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
-#define SWAPPER_PMD_FLAGS	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
+#define SWAPPER_PTE_FLAGS	(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED | PTE_UXN | PTE_WRITE)
+#define SWAPPER_PMD_FLAGS	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S | PTE_UXN | PTE_WRITE)
 
 #ifdef CONFIG_ARM64_4K_PAGES
 #define SWAPPER_RW_MMUFLAGS	(PMD_ATTRINDX(MT_NORMAL) | SWAPPER_PMD_FLAGS)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index b98970907226..989e2132af14 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -382,7 +382,7 @@ SYM_FUNC_START_LOCAL(create_idmap)
 	adrp	x0, init_idmap_pg_dir
 	adrp	x3, _text
 	adrp	x6, _end + MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE
-	mov	x7, SWAPPER_RX_MMUFLAGS
+	mov_q	x7, SWAPPER_RX_MMUFLAGS
 
 	map_memory x0, x1, x3, x6, x7, x3, IDMAP_PGD_ORDER, x10, x11, x12, x13, x14, EXTRA_SHIFT
 
@@ -391,7 +391,7 @@ SYM_FUNC_START_LOCAL(create_idmap)
 	adrp	x2, init_pg_dir
 	adrp	x3, init_pg_end
 	bic	x4, x2, #SWAPPER_BLOCK_SIZE - 1
-	mov	x5, SWAPPER_RW_MMUFLAGS
+	mov_q	x5, SWAPPER_RW_MMUFLAGS
 	mov	x6, #SWAPPER_BLOCK_SHIFT
 	bl	remap_region
 
@@ -402,7 +402,7 @@ SYM_FUNC_START_LOCAL(create_idmap)
 	bfi	x22, x21, #0, #SWAPPER_BLOCK_SHIFT		// remapped FDT address
 	add	x3, x2, #MAX_FDT_SIZE + SWAPPER_BLOCK_SIZE
 	bic	x4, x21, #SWAPPER_BLOCK_SIZE - 1
-	mov	x5, SWAPPER_RW_MMUFLAGS
+	mov_q	x5, SWAPPER_RW_MMUFLAGS
 	mov	x6, #SWAPPER_BLOCK_SHIFT
 	bl	remap_region
 
@@ -430,7 +430,7 @@ SYM_FUNC_START_LOCAL(create_kernel_mapping)
 	adrp	x3, _text			// runtime __pa(_text)
 	sub	x6, x6, x3			// _end - _text
 	add	x6, x6, x5			// runtime __va(_end)
-	mov	x7, SWAPPER_RW_MMUFLAGS
+	mov_q	x7, SWAPPER_RW_MMUFLAGS
 
 	map_memory x0, x1, x5, x6, x7, x3, (VA_BITS - PGDIR_SHIFT), x10, x11, x12, x13, x14
 
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 91410f488090..644e8daa25df 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -290,7 +290,7 @@ SYM_TYPED_FUNC_START(idmap_kpti_install_ng_mappings)
 	isb
 
 	mov	temp_pte, x5
-	mov	pte_flags, #KPTI_NG_PTE_FLAGS
+	mov_q	pte_flags, KPTI_NG_PTE_FLAGS
 
 	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
 	/* PGD */
-- 
2.17.1


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[PATCH v1 13/18] arm64: add PTE_WRITE to PROT_SECT_NORMAL

[Joey Gouly]

With PIE enabled, PROT_SECT_NORMAL would map onto PAGE_KERNEL_RO.
Add PTE_WRITE so that this maps onto PAGE_KERNEL, so that it is writable.

Without PIE, this should enable DBM for PROT_SECT_NORMAL, which should be
functionally equivalent.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
---
 arch/arm64/include/asm/pgtable-prot.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
index 9b165117a454..d26d0b427c0a 100644
--- a/arch/arm64/include/asm/pgtable-prot.h
+++ b/arch/arm64/include/asm/pgtable-prot.h
@@ -60,7 +60,7 @@ extern bool arm64_use_ng_mappings;
 #define PROT_NORMAL_TAGGED	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED))
 
 #define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
-#define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
+#define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PTE_WRITE | PMD_ATTRINDX(MT_NORMAL))
 #define PROT_SECT_NORMAL_EXEC	(PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
 
 #define _PAGE_DEFAULT		(_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
-- 
2.17.1


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[PATCH v1 14/18] arm64: reorganise PAGE_/PROT_ macros

[Joey Gouly]

Make these macros available to assembly code, so they can be re-used by the PIE
initialisation code.

This involves adding some extra macros, prepended with _ that are the raw values
not `pgprot` values.

A dummy value for PTE_MAYBE_NG is also provided, for use in assembly.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
---
 arch/arm64/include/asm/pgtable-prot.h | 72 ++++++++++++++++-----------
 1 file changed, 44 insertions(+), 28 deletions(-)

diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
index d26d0b427c0a..a45af0a22b25 100644
--- a/arch/arm64/include/asm/pgtable-prot.h
+++ b/arch/arm64/include/asm/pgtable-prot.h
@@ -27,6 +27,40 @@
  */
 #define PMD_PRESENT_INVALID	(_AT(pteval_t, 1) << 59) /* only when !PMD_SECT_VALID */
 
+#define _PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
+#define _PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
+
+#define PROT_DEFAULT		(_PROT_DEFAULT | PTE_MAYBE_NG)
+#define PROT_SECT_DEFAULT	(_PROT_SECT_DEFAULT | PMD_MAYBE_NG)
+
+#define PROT_DEVICE_nGnRnE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
+#define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
+#define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
+#define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
+#define PROT_NORMAL_TAGGED	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED))
+
+#define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
+#define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PTE_WRITE | PMD_ATTRINDX(MT_NORMAL))
+#define PROT_SECT_NORMAL_EXEC	(PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
+
+#define _PAGE_DEFAULT		(_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
+
+#define _PAGE_KERNEL		(PROT_NORMAL)
+#define _PAGE_KERNEL_RO		((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY)
+#define _PAGE_KERNEL_ROX	((PROT_NORMAL & ~(PTE_WRITE | PTE_PXN)) | PTE_RDONLY)
+#define _PAGE_KERNEL_EXEC	(PROT_NORMAL & ~PTE_PXN)
+#define _PAGE_KERNEL_EXEC_CONT	((PROT_NORMAL & ~PTE_PXN) | PTE_CONT)
+
+#define _PAGE_SHARED		(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
+#define _PAGE_SHARED_EXEC	(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
+#define _PAGE_READONLY		(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
+#define _PAGE_READONLY_EXEC	(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
+#define _PAGE_EXECONLY		(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
+
+#ifdef __ASSEMBLY__
+#define PTE_MAYBE_NG	0
+#endif
+
 #ifndef __ASSEMBLY__
 
 #include <asm/cpufeature.h>
@@ -34,9 +68,6 @@
 
 extern bool arm64_use_ng_mappings;
 
-#define _PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
-#define _PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
-
 #define PTE_MAYBE_NG		(arm64_use_ng_mappings ? PTE_NG : 0)
 #define PMD_MAYBE_NG		(arm64_use_ng_mappings ? PMD_SECT_NG : 0)
 
@@ -50,26 +81,11 @@ extern bool arm64_use_ng_mappings;
 #define PTE_MAYBE_GP		0
 #endif
 
-#define PROT_DEFAULT		(_PROT_DEFAULT | PTE_MAYBE_NG)
-#define PROT_SECT_DEFAULT	(_PROT_SECT_DEFAULT | PMD_MAYBE_NG)
-
-#define PROT_DEVICE_nGnRnE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
-#define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
-#define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
-#define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
-#define PROT_NORMAL_TAGGED	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED))
-
-#define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
-#define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PTE_WRITE | PMD_ATTRINDX(MT_NORMAL))
-#define PROT_SECT_NORMAL_EXEC	(PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
-
-#define _PAGE_DEFAULT		(_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
-
-#define PAGE_KERNEL		__pgprot(PROT_NORMAL)
-#define PAGE_KERNEL_RO		__pgprot((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY)
-#define PAGE_KERNEL_ROX		__pgprot((PROT_NORMAL & ~(PTE_WRITE | PTE_PXN)) | PTE_RDONLY)
-#define PAGE_KERNEL_EXEC	__pgprot(PROT_NORMAL & ~PTE_PXN)
-#define PAGE_KERNEL_EXEC_CONT	__pgprot((PROT_NORMAL & ~PTE_PXN) | PTE_CONT)
+#define PAGE_KERNEL		__pgprot(_PAGE_KERNEL)
+#define PAGE_KERNEL_RO		__pgprot(_PAGE_KERNEL_RO)
+#define PAGE_KERNEL_ROX		__pgprot(_PAGE_KERNEL_ROX)
+#define PAGE_KERNEL_EXEC	__pgprot(_PAGE_KERNEL_EXEC)
+#define PAGE_KERNEL_EXEC_CONT	__pgprot(_PAGE_KERNEL_EXEC_CONT)
 
 #define PAGE_S2_MEMATTR(attr, has_fwb)					\
 	({								\
@@ -83,11 +99,11 @@ extern bool arm64_use_ng_mappings;
 
 #define PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
 /* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */
-#define PAGE_SHARED		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
-#define PAGE_SHARED_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_WRITE)
-#define PAGE_READONLY		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
-#define PAGE_READONLY_EXEC	__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN)
-#define PAGE_EXECONLY		__pgprot(_PAGE_DEFAULT | PTE_RDONLY | PTE_NG | PTE_PXN)
+#define PAGE_SHARED		__pgprot(_PAGE_SHARED)
+#define PAGE_SHARED_EXEC	__pgprot(_PAGE_SHARED_EXEC)
+#define PAGE_READONLY		__pgprot(_PAGE_READONLY)
+#define PAGE_READONLY_EXEC	__pgprot(_PAGE_READONLY_EXEC)
+#define PAGE_EXECONLY		__pgprot(_PAGE_EXECONLY)
 
 #endif /* __ASSEMBLY__ */
 
-- 
2.17.1


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[PATCH v1 15/18] arm64: disable EL2 traps for PIE

[Joey Gouly]

Disable trapping of TCR2_EL1 and PIRx_EL1 registers, so they can be
accessed from by EL1.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
 arch/arm64/include/asm/el2_setup.h | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 037724b19c5c..6e6675fae194 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -22,6 +22,21 @@
 	isb
 .endm
 
+.macro __init_el2_hcrx
+	mrs	x1, id_aa64mmfr1_el1
+	ubfx	x0, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, 4
+	cbz	x0, .Lskip_hcrx_\@
+
+	mrs_s	x1, SYS_ID_AA64MMFR2_EL1
+	ubfx	x0, x1, #ID_AA64MMFR3_EL1_TCRX_SHIFT, 4
+	cbz	x0, .Lskip_hcrx_\@
+
+	mrs_s	x0, SYS_HCRX_EL2
+	orr	x0, x0, #HCRX_EL2_TCR2En
+	msr_s	SYS_HCRX_EL2, x0
+.Lskip_hcrx_\@:
+.endm
+
 /*
  * Allow Non-secure EL1 and EL0 to access physical timer and counter.
  * This is not necessary for VHE, since the host kernel runs in EL2,
@@ -150,12 +165,21 @@
 	mov	x0, xzr
 	mrs	x1, id_aa64pfr1_el1
 	ubfx	x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4
-	cbz	x1, .Lset_fgt_\@
+	cbz	x1, .Lset_pie_fgt_\@
 
 	/* Disable nVHE traps of TPIDR2 and SMPRI */
 	orr	x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK
 	orr	x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK
 
+.Lset_pie_fgt_\@:
+	mrs_s	x1, SYS_ID_AA64MMFR3_EL1
+	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
+	cbz	x1, .Lset_fgt_\@
+
+	/* Disable trapping of PIR_EL1 / PIRE0_EL1 */
+	orr	x0, x0, #HFGxTR_EL2_nPIR_EL0_MASK
+	orr	x0, x0, #HFGxTR_EL2_nPIREO_EL0_MASK
+
 .Lset_fgt_\@:
 	msr_s	SYS_HFGRTR_EL2, x0
 	msr_s	SYS_HFGWTR_EL2, x0
@@ -184,6 +208,7 @@
  */
 .macro init_el2_state
 	__init_el2_sctlr
+	__init_el2_hcrx
 	__init_el2_timers
 	__init_el2_debug
 	__init_el2_lor
-- 
2.17.1


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[PATCH v1 16/18] arm64: add encodings of PIRx_ELx registers

[Joey Gouly]

The encodings used in the permission indirection registers means that the
values that Linux puts in the PTEs do not need to be changed.

The E0 values are replicated in E1, with the execute permissions removed.
This is needed as the futex operations access user mappings with privileged
loads/stores.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
 arch/arm64/include/asm/pgtable-hwdef.h |  8 ++++++++
 arch/arm64/include/asm/pgtable-prot.h  | 18 ++++++++++++++++++
 arch/arm64/include/asm/pgtable.h       |  6 ++++++
 3 files changed, 32 insertions(+)

diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index f658aafc47df..11c81e700335 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -170,6 +170,14 @@
 #define PTE_ATTRINDX(t)		(_AT(pteval_t, (t)) << 2)
 #define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)
 
+/*
+ * PIIndex[3:0] encoding (Permission Indirection Extension)
+ */
+#define PTE_PI_IDX_0	6
+#define PTE_PI_IDX_1	51
+#define PTE_PI_IDX_2	53
+#define PTE_PI_IDX_3	54
+
 /*
  * Memory Attribute override for Stage-2 (MemAttr[3:0])
  */
diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
index a45af0a22b25..2b192da1ef9d 100644
--- a/arch/arm64/include/asm/pgtable-prot.h
+++ b/arch/arm64/include/asm/pgtable-prot.h
@@ -107,4 +107,22 @@ extern bool arm64_use_ng_mappings;
 
 #endif /* __ASSEMBLY__ */
 
+#define PIE_E0	( \
+	PIRx_ELx_PERMIDX(PIE_X_O, pte_pi_index(_PAGE_EXECONLY))      | \
+	PIRx_ELx_PERMIDX(PIE_RX,  pte_pi_index(_PAGE_READONLY_EXEC)) | \
+	PIRx_ELx_PERMIDX(PIE_RWX, pte_pi_index(_PAGE_SHARED_EXEC))   | \
+	PIRx_ELx_PERMIDX(PIE_R,   pte_pi_index(_PAGE_READONLY))      | \
+	PIRx_ELx_PERMIDX(PIE_RW,  pte_pi_index(_PAGE_SHARED)))
+
+#define PIE_E1	( \
+	PIRx_ELx_PERMIDX(PIE_NONE_O, pte_pi_index(_PAGE_EXECONLY))      | \
+	PIRx_ELx_PERMIDX(PIE_R,      pte_pi_index(_PAGE_READONLY_EXEC)) | \
+	PIRx_ELx_PERMIDX(PIE_RW,     pte_pi_index(_PAGE_SHARED_EXEC))   | \
+	PIRx_ELx_PERMIDX(PIE_R,      pte_pi_index(_PAGE_READONLY))      | \
+	PIRx_ELx_PERMIDX(PIE_RW,     pte_pi_index(_PAGE_SHARED))        | \
+	PIRx_ELx_PERMIDX(PIE_RX,     pte_pi_index(_PAGE_KERNEL_ROX))    | \
+	PIRx_ELx_PERMIDX(PIE_RWX,    pte_pi_index(_PAGE_KERNEL_EXEC))   | \
+	PIRx_ELx_PERMIDX(PIE_R,      pte_pi_index(_PAGE_KERNEL_RO))     | \
+	PIRx_ELx_PERMIDX(PIE_RW,     pte_pi_index(_PAGE_KERNEL)))
+
 #endif /* __ASM_PGTABLE_PROT_H */
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index b6ba466e2e8a..b31d39f22803 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -26,6 +26,12 @@
 
 #define vmemmap			((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
 
+#define pte_pi_index(pte) ( \
+	((pte & BIT(PTE_PI_IDX_3)) >> (PTE_PI_IDX_3 - 3)) | \
+	((pte & BIT(PTE_PI_IDX_2)) >> (PTE_PI_IDX_2 - 2)) | \
+	((pte & BIT(PTE_PI_IDX_1)) >> (PTE_PI_IDX_1 - 1)) | \
+	((pte & BIT(PTE_PI_IDX_0)) >> (PTE_PI_IDX_0 - 0)))
+
 #ifndef __ASSEMBLY__
 
 #include <asm/cmpxchg.h>
-- 
2.17.1


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[PATCH v1 17/18] arm64: enable Permission Indirection Extension (PIE)

[Joey Gouly]

Now that the necessary changes have been made, set the Permission Indirection
registers and enable the Permission Indirection Extension.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
---
 arch/arm64/mm/proc.S | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 644e8daa25df..5734f077dd46 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -454,6 +454,21 @@ SYM_FUNC_START(__cpu_setup)
 #endif	/* CONFIG_ARM64_HW_AFDBM */
 	msr	mair_el1, mair
 	msr	tcr_el1, tcr
+
+	mrs_s	x1, SYS_ID_AA64MMFR3_EL1
+	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
+	cbz	x1, .Lskip_indirection
+
+	mov_q	x0, PIE_E0
+	msr	REG_PIRE0_EL1, x0
+	mov_q	x0, PIE_E1
+	msr	REG_PIR_EL1, x0
+
+	mov	x0, TCR2_ELx_PIE
+	msr	REG_TCR2_EL1, x0
+
+.Lskip_indirection:
+
 	/*
 	 * Prepare SCTLR
 	 */
-- 
2.17.1


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[PATCH v1 18/18] arm64: transfer permission indirection settings to EL2

[Joey Gouly]

Copy the EL1 registers: TCR2_EL1, PIR_EL1, PIRE0_EL1, such that PIE
is also enabled for EL2.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
---
 arch/arm64/kernel/hyp-stub.S | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S
index 9439240c3fcf..d63de1973ddb 100644
--- a/arch/arm64/kernel/hyp-stub.S
+++ b/arch/arm64/kernel/hyp-stub.S
@@ -119,6 +119,24 @@ SYM_CODE_START_LOCAL(__finalise_el2)
 	msr	ttbr1_el1, x0
 	mrs_s	x0, SYS_MAIR_EL12
 	msr	mair_el1, x0
+	mrs	x1, REG_ID_AA64MMFR3_EL1
+	ubfx	x1, x1, #ID_AA64MMFR3_EL1_TCRX_SHIFT, #4
+	cbz	x1, .Lskip_tcr2
+	mrs	x0, REG_TCR2_EL12
+	msr	REG_TCR2_EL1, x0
+
+	// Transfer permission indirection state
+	mrs	x1, REG_ID_AA64MMFR3_EL1
+	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
+	cbz	x1, .Lskip_indirection
+	mrs	x0, REG_PIRE0_EL12
+	msr	REG_PIRE0_EL1, x0
+	mrs	x0, REG_PIR_EL12
+	msr	REG_PIR_EL1, x0
+
+.Lskip_indirection:
+.Lskip_tcr2:
+
 	isb
 
 	// Hack the exception return to stay at EL2
-- 
2.17.1


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Re: [PATCH v1 01/18] arm64/sysreg: Add ID register ID_AA64MMFR3

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 558 bytes --]

On Thu, Mar 09, 2023 at 02:52:29PM +0000, Joey Gouly wrote:

> Add the new ID register ID_AA64MMFR3.

Checking against DDI0601 2022-12.

> +Enum	59:56	ADERR
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum

There is also a 0b0010 which implements FEAT_ADERR.  This probably
suggests that 0b0001 is misnamed - perhaps DEV_ASYNC or something?

> +Enum	55:52	SDERR
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum

Similar comments here.

> +Enum	47:44	ANERR
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	43:40	SNERR
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum

and for these two.

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Re: [PATCH v1 02/18] arm64/sysreg: add system registers TCR2_ELx

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 323 bytes --]

On Thu, Mar 09, 2023 at 02:52:30PM +0000, Joey Gouly wrote:

> Add definitions of TCR2_EL1 and TCR2_EL12 registers.

Checking against DDI0601 2022-12.

> +SysregFields	TCR2_ELx

Note that TCR2_EL2 has some additional fields, might be worth a comment
but otherwise 

Reviewed-by: Mark Brown <broonie@kernel.org>

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Re: [PATCH v1 03/18] arm64/sysreg: add TCR2En to HCRX_EL2

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 462 bytes --]

On Thu, Mar 09, 2023 at 02:52:31PM +0000, Joey Gouly wrote:

> This bit controls the trapping of TCR2_EL1 to EL2.

>  Sysreg	HCRX_EL2	3	4	1	2	2
> -Res0	63:12
> +Res0	63:15
> +Field	14	TCR2En
> +Res0	13:12

This is correct but it would be much better to sync with the latest XML
release (DDI 0601 2022-12), there's a bunch of other fields defined.
That way different serieses can share the patch without conflicts, and
it makes life a bit easier with the review.

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Re: [PATCH v1 04/18] arm64/sysreg: add HFGxTR_EL2 bits for Permission Indirection Extension

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 528 bytes --]

On Thu, Mar 09, 2023 at 02:52:32PM +0000, Joey Gouly wrote:

> Add the trap bit definitions for nPIR_EL1 and nPIRE0_EL1.

>  /* HFG[WR]TR_EL2 bit definitions */
> +#define HFGxTR_EL2_nPIR_EL0_SHIFT	58
> +#define HFGxTR_EL2_nPIR_EL0_MASK	BIT_MASK(HFGxTR_EL2_nPIR_EL0_SHIFT)
> +#define HFGxTR_EL2_nPIREO_EL0_SHIFT	57
> +#define HFGxTR_EL2_nPIREO_EL0_MASK	BIT_MASK(HFGxTR_EL2_nPIREO_EL0_SHIFT)

Similarly please add new bits by syncing with the latest XML, in this
case you could pick up the patch I posted the other day for this.

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Re: [PATCH v1 05/18] arm64/sysreg: add PIR*_ELx registers

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 470 bytes --]

On Thu, Mar 09, 2023 at 02:52:33PM +0000, Joey Gouly wrote:

> Add definitions of PIR_EL1, PIR_EL12, PIRE0_EL1, PIRE0_EL12 registers.

Would be nice to also include PIR_EL2 while we're at it.  Otherwise
this looks good according to DDI0601 2022-12.  We *could* define the
bitmasks for the fields in sysreg but that doesn't really scale and I'm
not sure this is going to happen often enough to be worth extending the
script.

Reviewed-by: Mark Brown <broonie@kernel.org>

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Re: [PATCH v1 15/18] arm64: disable EL2 traps for PIE

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 323 bytes --]

On Thu, Mar 09, 2023 at 02:52:43PM +0000, Joey Gouly wrote:

> Disable trapping of TCR2_EL1 and PIRx_EL1 registers, so they can be
> accessed from by EL1.

There should be an update to booting.rst documenting what's needed here,
and also what we need EL3 to do for use at EL2.

Reviewed-by: Mark Brown <broonie@kernel.org>

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Re: [PATCH v1 11/18] KVM: arm64: expose ID_AA64MMFR3_EL1 to guests

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 283 bytes --]

On Thu, Mar 09, 2023 at 02:52:39PM +0000, Joey Gouly wrote:

> Now that KVM context switches the appropriate registers, expose ID_AA64MMFR3_EL1
> to guests to allow them to use the new features.

Should we be adding new vCPU features given that there's new
architectural state here?

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Re: [PATCH v1 11/18] KVM: arm64: expose ID_AA64MMFR3_EL1 to guests

[Marc Zyngier]

On Thu, 09 Mar 2023 16:07:42 +0000,
Mark Brown <broonie@kernel.org> wrote:
> 
> [1  <text/plain; us-ascii (7bit)>]
> On Thu, Mar 09, 2023 at 02:52:39PM +0000, Joey Gouly wrote:
> 
> > Now that KVM context switches the appropriate registers, expose
> > ID_AA64MMFR3_EL1 to guests to allow them to use the new features.
> 
> Should we be adding new vCPU features given that there's new
> architectural state here?

What do we gain by that? AFAICT, it only makes the UAPI more complex.
And to be honest, *any* new feature added to KVM results in new
architectural state. Are we going to add more and more of these ad
nauseam? It doesn't scale. All we need to ensure at this stage is that
you cannot migrate a VM that has seen this to a host that doesn't have
the feature.

And if anything, this sort of selection should be defined by writing
to the ID_AA64MMFR3_EL1 register from userspace and let the whole
thing be driven by it. See Jing's current effort at [1].

Thanks,

	M.

[1] https://lore.kernel.org/r/20230228062246.1222387-1-jingzhangos@google.com

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Re: [PATCH v1 15/18] arm64: disable EL2 traps for PIE

[Suzuki K Poulose]

On 09/03/2023 14:52, Joey Gouly wrote:
> Disable trapping of TCR2_EL1 and PIRx_EL1 registers, so they can be
> accessed from by EL1.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> ---
>   arch/arm64/include/asm/el2_setup.h | 27 ++++++++++++++++++++++++++-
>   1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index 037724b19c5c..6e6675fae194 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -22,6 +22,21 @@
>   	isb
>   .endm
>   
> +.macro __init_el2_hcrx
> +	mrs	x1, id_aa64mmfr1_el1
> +	ubfx	x0, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, 4
> +	cbz	x0, .Lskip_hcrx_\@

If TCR2 is available, HCX must also be supported ?

> +
> +	mrs_s	x1, SYS_ID_AA64MMFR2_EL1


MMFR3 ?

> +	ubfx	x0, x1, #ID_AA64MMFR3_EL1_TCRX_SHIFT, 4
> +	cbz	x0, .Lskip_hcrx_\@

Suzuki


> +
> +	mrs_s	x0, SYS_HCRX_EL2
> +	orr	x0, x0, #HCRX_EL2_TCR2En
> +	msr_s	SYS_HCRX_EL2, x0
> +.Lskip_hcrx_\@:
> +.endm
> +
>   /*
>    * Allow Non-secure EL1 and EL0 to access physical timer and counter.
>    * This is not necessary for VHE, since the host kernel runs in EL2,
> @@ -150,12 +165,21 @@
>   	mov	x0, xzr
>   	mrs	x1, id_aa64pfr1_el1
>   	ubfx	x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4
> -	cbz	x1, .Lset_fgt_\@
> +	cbz	x1, .Lset_pie_fgt_\@
>   
>   	/* Disable nVHE traps of TPIDR2 and SMPRI */
>   	orr	x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK
>   	orr	x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK
>   
> +.Lset_pie_fgt_\@:
> +	mrs_s	x1, SYS_ID_AA64MMFR3_EL1
> +	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
> +	cbz	x1, .Lset_fgt_\@
> +
> +	/* Disable trapping of PIR_EL1 / PIRE0_EL1 */
> +	orr	x0, x0, #HFGxTR_EL2_nPIR_EL0_MASK
> +	orr	x0, x0, #HFGxTR_EL2_nPIREO_EL0_MASK
> +
>   .Lset_fgt_\@:
>   	msr_s	SYS_HFGRTR_EL2, x0
>   	msr_s	SYS_HFGWTR_EL2, x0
> @@ -184,6 +208,7 @@
>    */
>   .macro init_el2_state
>   	__init_el2_sctlr
> +	__init_el2_hcrx
>   	__init_el2_timers
>   	__init_el2_debug
>   	__init_el2_lor


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Re: [PATCH v1 11/18] KVM: arm64: expose ID_AA64MMFR3_EL1 to guests

[Mark Brown]

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On Thu, Mar 09, 2023 at 04:07:48PM +0000, Mark Brown wrote:
> On Thu, Mar 09, 2023 at 02:52:39PM +0000, Joey Gouly wrote:
> 
> > Now that KVM context switches the appropriate registers, expose ID_AA64MMFR3_EL1
> > to guests to allow them to use the new features.
> 
> Should we be adding new vCPU features given that there's new
> architectural state here?

I'd also expect an update to the get-reg-list test for the new registers
BTW.

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Re: [PATCH v1 15/18] arm64: disable EL2 traps for PIE

[Mark Brown]

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On Thu, Mar 09, 2023 at 04:27:39PM +0000, Suzuki K Poulose wrote:
> On 09/03/2023 14:52, Joey Gouly wrote:

> > Disable trapping of TCR2_EL1 and PIRx_EL1 registers, so they can be
> > accessed from by EL1.

> > +.macro __init_el2_hcrx
> > +	mrs	x1, id_aa64mmfr1_el1
> > +	ubfx	x0, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, 4
> > +	cbz	x0, .Lskip_hcrx_\@

> If TCR2 is available, HCX must also be supported ?

OTOH given that an error here means that we'll die with no output and we
*have* had issues with virtual implementations not implementing all the
features they were supposed to (plus I guess some will allow user error
in configuration) a bit of defensiveness doesn't hurt.

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Re: [PATCH v1 11/18] KVM: arm64: expose ID_AA64MMFR3_EL1 to guests

[Mark Brown]

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On Thu, Mar 09, 2023 at 04:24:56PM +0000, Marc Zyngier wrote:
> Mark Brown <broonie@kernel.org> wrote:
> > On Thu, Mar 09, 2023 at 02:52:39PM +0000, Joey Gouly wrote:

> > > Now that KVM context switches the appropriate registers, expose
> > > ID_AA64MMFR3_EL1 to guests to allow them to use the new features.
> > 
> > Should we be adding new vCPU features given that there's new
> > architectural state here?

> What do we gain by that? AFAICT, it only makes the UAPI more complex.
> And to be honest, *any* new feature added to KVM results in new
> architectural state. Are we going to add more and more of these ad
> nauseam? It doesn't scale. All we need to ensure at this stage is that
> you cannot migrate a VM that has seen this to a host that doesn't have
> the feature.

That was a genuine question prompted by how we handle pointer auth -
that seemed to be in a similar situation but has a flag.  With something
like SVE which causes the V registers to be replaced by the Z registers
in the view offered to VMMs it's more obvious.

> And if anything, this sort of selection should be defined by writing
> to the ID_AA64MMFR3_EL1 register from userspace and let the whole
> thing be driven by it. See Jing's current effort at [1].

Yes, I've seen that and it does seem a lot more logical - I was always
confused by why we couldn't do that normally.

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Re: [PATCH v1 11/18] KVM: arm64: expose ID_AA64MMFR3_EL1 to guests

[Marc Zyngier]

On Thu, 09 Mar 2023 17:04:20 +0000,
Mark Brown <broonie@kernel.org> wrote:
> 
> On Thu, Mar 09, 2023 at 04:24:56PM +0000, Marc Zyngier wrote:
> > Mark Brown <broonie@kernel.org> wrote:
> > > On Thu, Mar 09, 2023 at 02:52:39PM +0000, Joey Gouly wrote:
> 
> > > > Now that KVM context switches the appropriate registers, expose
> > > > ID_AA64MMFR3_EL1 to guests to allow them to use the new features.
> > > 
> > > Should we be adding new vCPU features given that there's new
> > > architectural state here?
> 
> > What do we gain by that? AFAICT, it only makes the UAPI more complex.
> > And to be honest, *any* new feature added to KVM results in new
> > architectural state. Are we going to add more and more of these ad
> > nauseam? It doesn't scale. All we need to ensure at this stage is that
> > you cannot migrate a VM that has seen this to a host that doesn't have
> > the feature.
> 
> That was a genuine question prompted by how we handle pointer auth -
> that seemed to be in a similar situation but has a flag.  With something
> like SVE which causes the V registers to be replaced by the Z registers
> in the view offered to VMMs it's more obvious.
>
> > And if anything, this sort of selection should be defined by writing
> > to the ID_AA64MMFR3_EL1 register from userspace and let the whole
> > thing be driven by it. See Jing's current effort at [1].
> 
> Yes, I've seen that and it does seem a lot more logical - I was always
> confused by why we couldn't do that normally.

Because we made the mistake initially and nobody cared enough to fix
it until now? The KVM UAPI is a never ending train wreck...

	M.

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Re: [PATCH v1 05/18] arm64/sysreg: add PIR*_ELx registers

[Mark Brown]

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On Thu, Mar 09, 2023 at 02:52:33PM +0000, Joey Gouly wrote:

> +#define PIE_NONE_O	0x0
> +#define PIE_R_O		0x1
> +#define PIE_X_O		0x2
> +#define PIE_RX_O	0x3
> +#define PIE_RW_O	0x5
> +#define PIE_RWnX_O	0x6
> +#define PIE_RWX_O	0x7
> +#define PIE_R		0x8
> +#define PIE_GCS		0x9
> +#define PIE_RX		0xa
> +#define PIE_RW		0xc
> +#define PIE_RWX		0xe

> +#define PIRx_ELx_PERMIDX(perm, idx)	((perm) << ((idx) * 4))

This is bikeshedding but every time I look at the uses of this macro I
find myself trying to read it as index, permission rather than the way
it is - that's the order for both assignment statements and #defines in
headers so it's what my brain is reaching for.

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Re: [PATCH v1 00/18] Permission Indirection Extension

[Mark Brown]

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On Thu, Mar 09, 2023 at 02:52:28PM +0000, Joey Gouly wrote:

> The PTEs bit that are repurposed for use with permission indirection are:
> 	54 PTE_UXN
> 	53 PTE_PXN
> 	51 PTE_DBM
> 	6 PTE_USER

> The way that PIE is implemented in this patchset is that the encodings are
> picked such that they match how Linux currently sets the bits in the PTEs, so
> none of the page table handling has changed. This means this patchset keeps the
> same functionality as currently implemented, but allows for future expansion.

While it's not strictly needed as a result of this patch set since it
aims to implement the same encodings as currently used as soon as we
use any of the new functionality that the extension makes available
we'll need updates to the page table dumping in ptdump.c and task_mmu.c
to decode the indirect encodings natively rather than just relying on
the overlap with the direct encodings.

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Re: [PATCH v1 05/18] arm64/sysreg: add PIR*_ELx registers

[Catalin Marinas]

On Thu, Mar 16, 2023 at 05:23:48PM +0000, Mark Brown wrote:
> On Thu, Mar 09, 2023 at 02:52:33PM +0000, Joey Gouly wrote:
> 
> > +#define PIE_NONE_O	0x0
> > +#define PIE_R_O		0x1
> > +#define PIE_X_O		0x2
> > +#define PIE_RX_O	0x3
> > +#define PIE_RW_O	0x5
> > +#define PIE_RWnX_O	0x6
> > +#define PIE_RWX_O	0x7
> > +#define PIE_R		0x8
> > +#define PIE_GCS		0x9
> > +#define PIE_RX		0xa
> > +#define PIE_RW		0xc
> > +#define PIE_RWX		0xe
> 
> > +#define PIRx_ELx_PERMIDX(perm, idx)	((perm) << ((idx) * 4))
> 
> This is bikeshedding but every time I look at the uses of this macro I
> find myself trying to read it as index, permission rather than the way
> it is - that's the order for both assignment statements and #defines in
> headers so it's what my brain is reaching for.

You are right, we should probably drop the IDX suffix (or maybe you have
better suggestion for naming it). It refers to the permission field in
the PIR* registers.

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Re: [PATCH v1 06/18] arm64: cpufeature: add system register ID_AA64MMFR3

[Catalin Marinas]

On Thu, Mar 09, 2023 at 02:52:34PM +0000, Joey Gouly wrote:
> Add new system register ID_AA64MMFR3 to the cpufeature infrastructure.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

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Re: [PATCH v1 07/18] arm64: cpufeature: add TCR2 cpucap

[Catalin Marinas]

On Thu, Mar 09, 2023 at 02:52:35PM +0000, Joey Gouly wrote:
> This capability indicates if the system supports the TCR2_ELx system register.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

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Re: [PATCH v1 08/18] arm64: cpufeature: add Permission Indirection Extension cpucap

[Catalin Marinas]

On Thu, Mar 09, 2023 at 02:52:36PM +0000, Joey Gouly wrote:
> This indicates if the system supports PIE. This is a CPUCAP_BOOT_CPU_FEATURE
> as the boot CPU will enable PIE if it has it, so secondary CPUs must also
> have this feature.

In theory I think we could combine them CPUs with and without PIE
(possibly a slight issue with DBM) but it's not worth the effort.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

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Re: [PATCH v1 09/18] KVM: arm64: Save/restore TCR2_EL1

[Catalin Marinas]

On Thu, Mar 09, 2023 at 02:52:37PM +0000, Joey Gouly wrote:
> Define the new system register TCR2_EL1 and context switch it.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Oliver Upton <oliver.upton@linux.dev>
> Cc: James Morse <james.morse@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Zenghui Yu <yuzenghui@huawei.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

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Re: [PATCH v1 10/18] KVM: arm64: Save/restore PIE registers

[Catalin Marinas]

On Thu, Mar 09, 2023 at 02:52:38PM +0000, Joey Gouly wrote:
> Define the new system registers that PIE introduces and context switch them.
> The PIE feature is still hidden from the ID register, and not exposed to a VM.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Oliver Upton <oliver.upton@linux.dev>
> Cc: James Morse <james.morse@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: Zenghui Yu <yuzenghui@huawei.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

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Re: [PATCH v1 12/18] arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS

[Catalin Marinas]

On Thu, Mar 09, 2023 at 02:52:40PM +0000, Joey Gouly wrote:
> With PIE enabled, the swapper PTEs would have a Permission Indirection Index (PIIndex)
> of 0. A PIIndex of 0 is not currently used by any other PTEs.
> 
> To avoid using index 0 specifically for the swapper PTEs, mark them as PTE_UXN
> and PTE_WRITE, so that they map to a PAGE_KERNEL_EXEC equivalent.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> ---
>  arch/arm64/include/asm/kernel-pgtable.h | 4 ++--
>  arch/arm64/kernel/head.S                | 8 ++++----
>  arch/arm64/mm/proc.S                    | 2 +-
>  3 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h
> index fcd14197756f..daf1909116f6 100644
> --- a/arch/arm64/include/asm/kernel-pgtable.h
> +++ b/arch/arm64/include/asm/kernel-pgtable.h
> @@ -104,8 +104,8 @@
>  /*
>   * Initial memory map attributes.
>   */
> -#define SWAPPER_PTE_FLAGS	(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
> -#define SWAPPER_PMD_FLAGS	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
> +#define SWAPPER_PTE_FLAGS	(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED | PTE_UXN | PTE_WRITE)
> +#define SWAPPER_PMD_FLAGS	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S | PTE_UXN | PTE_WRITE)

Adding PTE_UXN is fine but we have SWAPPER_RX_MMUFLAGS which is no
longer read-only after this change. I don't think this matters much as
IIUC we only use init_pg_dir briefly before creating the proper
swapper_pg_dir.

-- 
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Re: [PATCH v1 13/18] arm64: add PTE_WRITE to PROT_SECT_NORMAL

[Catalin Marinas]

On Thu, Mar 09, 2023 at 02:52:41PM +0000, Joey Gouly wrote:
> With PIE enabled, PROT_SECT_NORMAL would map onto PAGE_KERNEL_RO.
> Add PTE_WRITE so that this maps onto PAGE_KERNEL, so that it is writable.
> 
> Without PIE, this should enable DBM for PROT_SECT_NORMAL, which should be
> functionally equivalent.

It's worth mentioning that since PTE_RDONLY (a.k.a. PTE_NDIRTY with PIE)
is already cleared, we don't even rely on the DBM mechanism to make it
writable.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

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Re: [PATCH v1 14/18] arm64: reorganise PAGE_/PROT_ macros

[Catalin Marinas]

On Thu, Mar 09, 2023 at 02:52:42PM +0000, Joey Gouly wrote:
> Make these macros available to assembly code, so they can be re-used by the PIE
> initialisation code.
> 
> This involves adding some extra macros, prepended with _ that are the raw values
> not `pgprot` values.
> 
> A dummy value for PTE_MAYBE_NG is also provided, for use in assembly.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

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Re: [PATCH v1 15/18] arm64: disable EL2 traps for PIE

[Catalin Marinas]

On Thu, Mar 09, 2023 at 02:52:43PM +0000, Joey Gouly wrote:
> Disable trapping of TCR2_EL1 and PIRx_EL1 registers, so they can be
> accessed from by EL1.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> ---
>  arch/arm64/include/asm/el2_setup.h | 27 ++++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index 037724b19c5c..6e6675fae194 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -22,6 +22,21 @@
>  	isb
>  .endm
>  
> +.macro __init_el2_hcrx
> +	mrs	x1, id_aa64mmfr1_el1
> +	ubfx	x0, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, 4
> +	cbz	x0, .Lskip_hcrx_\@
> +
> +	mrs_s	x1, SYS_ID_AA64MMFR2_EL1
> +	ubfx	x0, x1, #ID_AA64MMFR3_EL1_TCRX_SHIFT, 4
> +	cbz	x0, .Lskip_hcrx_\@
> +
> +	mrs_s	x0, SYS_HCRX_EL2
> +	orr	x0, x0, #HCRX_EL2_TCR2En
> +	msr_s	SYS_HCRX_EL2, x0
> +.Lskip_hcrx_\@:
> +.endm

Can we not just set HCRX_EL2_TCR2En without probing for TCRX?

BTW, Kristina's doing some initialisation of HCRX_EL2 as well here, not
sure whether they conflict:

https://lore.kernel.org/all/20230216160012.272345-2-kristina.martsenko@arm.com/

-- 
Catalin

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Re: [PATCH v1 16/18] arm64: add encodings of PIRx_ELx registers

[Catalin Marinas]

On Thu, Mar 09, 2023 at 02:52:44PM +0000, Joey Gouly wrote:
> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
> index f658aafc47df..11c81e700335 100644
> --- a/arch/arm64/include/asm/pgtable-hwdef.h
> +++ b/arch/arm64/include/asm/pgtable-hwdef.h
> @@ -170,6 +170,14 @@
>  #define PTE_ATTRINDX(t)		(_AT(pteval_t, (t)) << 2)
>  #define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)
>  
> +/*
> + * PIIndex[3:0] encoding (Permission Indirection Extension)
> + */
> +#define PTE_PI_IDX_0	6
> +#define PTE_PI_IDX_1	51
> +#define PTE_PI_IDX_2	53
> +#define PTE_PI_IDX_3	54
> +
>  /*
>   * Memory Attribute override for Stage-2 (MemAttr[3:0])
>   */
> diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
> index a45af0a22b25..2b192da1ef9d 100644
> --- a/arch/arm64/include/asm/pgtable-prot.h
> +++ b/arch/arm64/include/asm/pgtable-prot.h
> @@ -107,4 +107,22 @@ extern bool arm64_use_ng_mappings;
>  
>  #endif /* __ASSEMBLY__ */
>  
> +#define PIE_E0	( \
> +	PIRx_ELx_PERMIDX(PIE_X_O, pte_pi_index(_PAGE_EXECONLY))      | \
> +	PIRx_ELx_PERMIDX(PIE_RX,  pte_pi_index(_PAGE_READONLY_EXEC)) | \
> +	PIRx_ELx_PERMIDX(PIE_RWX, pte_pi_index(_PAGE_SHARED_EXEC))   | \
> +	PIRx_ELx_PERMIDX(PIE_R,   pte_pi_index(_PAGE_READONLY))      | \
> +	PIRx_ELx_PERMIDX(PIE_RW,  pte_pi_index(_PAGE_SHARED)))
> +
> +#define PIE_E1	( \
> +	PIRx_ELx_PERMIDX(PIE_NONE_O, pte_pi_index(_PAGE_EXECONLY))      | \
> +	PIRx_ELx_PERMIDX(PIE_R,      pte_pi_index(_PAGE_READONLY_EXEC)) | \
> +	PIRx_ELx_PERMIDX(PIE_RW,     pte_pi_index(_PAGE_SHARED_EXEC))   | \
> +	PIRx_ELx_PERMIDX(PIE_R,      pte_pi_index(_PAGE_READONLY))      | \
> +	PIRx_ELx_PERMIDX(PIE_RW,     pte_pi_index(_PAGE_SHARED))        | \
> +	PIRx_ELx_PERMIDX(PIE_RX,     pte_pi_index(_PAGE_KERNEL_ROX))    | \
> +	PIRx_ELx_PERMIDX(PIE_RWX,    pte_pi_index(_PAGE_KERNEL_EXEC))   | \
> +	PIRx_ELx_PERMIDX(PIE_R,      pte_pi_index(_PAGE_KERNEL_RO))     | \
> +	PIRx_ELx_PERMIDX(PIE_RW,     pte_pi_index(_PAGE_KERNEL)))
> +
>  #endif /* __ASM_PGTABLE_PROT_H */
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index b6ba466e2e8a..b31d39f22803 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -26,6 +26,12 @@
>  
>  #define vmemmap			((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT))
>  
> +#define pte_pi_index(pte) ( \
> +	((pte & BIT(PTE_PI_IDX_3)) >> (PTE_PI_IDX_3 - 3)) | \
> +	((pte & BIT(PTE_PI_IDX_2)) >> (PTE_PI_IDX_2 - 2)) | \
> +	((pte & BIT(PTE_PI_IDX_1)) >> (PTE_PI_IDX_1 - 1)) | \
> +	((pte & BIT(PTE_PI_IDX_0)) >> (PTE_PI_IDX_0 - 0)))

You might as well keep this macro with the PIE_E0/E1 definitions above.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

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Re: [PATCH v1 17/18] arm64: enable Permission Indirection Extension (PIE)

[Catalin Marinas]

On Thu, Mar 09, 2023 at 02:52:45PM +0000, Joey Gouly wrote:
> Now that the necessary changes have been made, set the Permission Indirection
> registers and enable the Permission Indirection Extension.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

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Re: [PATCH v1 18/18] arm64: transfer permission indirection settings to EL2

[Catalin Marinas]

On Thu, Mar 09, 2023 at 02:52:46PM +0000, Joey Gouly wrote:
> Copy the EL1 registers: TCR2_EL1, PIR_EL1, PIRE0_EL1, such that PIE
> is also enabled for EL2.
> 
> Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Oliver Upton <oliver.upton@linux.dev>

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

(to the best of my knowledge; KVM experts should review this)

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Re: [PATCH v1 15/18] arm64: disable EL2 traps for PIE

[Joey Gouly]

Hi Catalin,

On Mon, Mar 27, 2023 at 05:59:23PM +0100, Catalin Marinas wrote:
> On Thu, Mar 09, 2023 at 02:52:43PM +0000, Joey Gouly wrote:
> > Disable trapping of TCR2_EL1 and PIRx_EL1 registers, so they can be
> > accessed from by EL1.
> > 
> > Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Will Deacon <will@kernel.org>
> > ---
> >  arch/arm64/include/asm/el2_setup.h | 27 ++++++++++++++++++++++++++-
> >  1 file changed, 26 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> > index 037724b19c5c..6e6675fae194 100644
> > --- a/arch/arm64/include/asm/el2_setup.h
> > +++ b/arch/arm64/include/asm/el2_setup.h
> > @@ -22,6 +22,21 @@
> >  	isb
> >  .endm
> >  
> > +.macro __init_el2_hcrx
> > +	mrs	x1, id_aa64mmfr1_el1
> > +	ubfx	x0, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, 4
> > +	cbz	x0, .Lskip_hcrx_\@
> > +
> > +	mrs_s	x1, SYS_ID_AA64MMFR2_EL1
> > +	ubfx	x0, x1, #ID_AA64MMFR3_EL1_TCRX_SHIFT, 4
> > +	cbz	x0, .Lskip_hcrx_\@
> > +
> > +	mrs_s	x0, SYS_HCRX_EL2
> > +	orr	x0, x0, #HCRX_EL2_TCR2En
> > +	msr_s	SYS_HCRX_EL2, x0
> > +.Lskip_hcrx_\@:
> > +.endm
> 
> Can we not just set HCRX_EL2_TCR2En without probing for TCRX?

It's RES0, so I avoided it, but if it's fine I can drop the check.

> 
> BTW, Kristina's doing some initialisation of HCRX_EL2 as well here, not
> sure whether they conflict:
> 
> https://lore.kernel.org/all/20230216160012.272345-2-kristina.martsenko@arm.com/

I don't think they will conflict in the git sense. I think it should be pretty
easy to deal with, this code can be dropped, and HCRX_{HOST, GUEST}_FLAGS will
need to be modified to include HCRX_EL2_TCR2En.

Thanks,
Joey

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Re: [PATCH v1 15/18] arm64: disable EL2 traps for PIE

[Catalin Marinas]

On Tue, Mar 28, 2023 at 11:34:27AM +0100, Joey Gouly wrote:
> On Mon, Mar 27, 2023 at 05:59:23PM +0100, Catalin Marinas wrote:
> > On Thu, Mar 09, 2023 at 02:52:43PM +0000, Joey Gouly wrote:
> > > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> > > index 037724b19c5c..6e6675fae194 100644
> > > --- a/arch/arm64/include/asm/el2_setup.h
> > > +++ b/arch/arm64/include/asm/el2_setup.h
> > > @@ -22,6 +22,21 @@
> > >  	isb
> > >  .endm
> > >  
> > > +.macro __init_el2_hcrx
> > > +	mrs	x1, id_aa64mmfr1_el1
> > > +	ubfx	x0, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, 4
> > > +	cbz	x0, .Lskip_hcrx_\@
> > > +
> > > +	mrs_s	x1, SYS_ID_AA64MMFR2_EL1
> > > +	ubfx	x0, x1, #ID_AA64MMFR3_EL1_TCRX_SHIFT, 4
> > > +	cbz	x0, .Lskip_hcrx_\@
> > > +
> > > +	mrs_s	x0, SYS_HCRX_EL2
> > > +	orr	x0, x0, #HCRX_EL2_TCR2En
> > > +	msr_s	SYS_HCRX_EL2, x0
> > > +.Lskip_hcrx_\@:
> > > +.endm
> > 
> > Can we not just set HCRX_EL2_TCR2En without probing for TCRX?
> 
> It's RES0, so I avoided it, but if it's fine I can drop the check.

We do this in a few other places (SCTLR_ELx etc). When it's RES0, we
only write 0 as we can't tell what it will do in a future architecture
version. But now that it has a defined meaning, just set it and it
has no effect on earlier CPUs (there is a definition of RES0 on page
11943 in the Arm ARM).

-- 
Catalin

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Re: [PATCH v1 05/18] arm64/sysreg: add PIR*_ELx registers

[Mark Brown]

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On Mon, Mar 27, 2023 at 01:22:12PM +0100, Catalin Marinas wrote:
> On Thu, Mar 16, 2023 at 05:23:48PM +0000, Mark Brown wrote:
> > On Thu, Mar 09, 2023 at 02:52:33PM +0000, Joey Gouly wrote:

> > > +#define PIRx_ELx_PERMIDX(perm, idx)	((perm) << ((idx) * 4))

> > This is bikeshedding but every time I look at the uses of this macro I
> > find myself trying to read it as index, permission rather than the way
> > it is - that's the order for both assignment statements and #defines in
> > headers so it's what my brain is reaching for.

> You are right, we should probably drop the IDX suffix (or maybe you have
> better suggestion for naming it). It refers to the permission field in
> the PIR* registers.

I'd suggest dropping the IDX and reversing the arguments.

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