* [PULL v3 00/91] tcg patch queue
@ 2023-03-13 18:59 Richard Henderson
2023-03-13 18:59 ` [PULL v3 73/91] target/arm: Improve trans_BFCI Richard Henderson
2023-03-14 14:28 ` [PULL v3 00/91] tcg patch queue Peter Maydell
0 siblings, 2 replies; 3+ messages in thread
From: Richard Henderson @ 2023-03-13 18:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Version 3 fixes a rebase error from v2 affecting ARM BFC insn.
r~
The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
Merge tag 'linux-user-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2023-03-12 10:57:00 +0000)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230313
for you to fetch changes up to 0c8b6b9a6383e2e37ff3d1d12b40c58b7ed36c1c:
tcg: Drop tcg_const_* (2023-03-13 07:03:39 -0700)
----------------------------------------------------------------
accel/tcg: Fix NB_MMU_MODES to 16
Balance of the target/ patchset which eliminates tcg_temp_free
Balance of the target/ patchset which eliminates tcg_const
----------------------------------------------------------------
Anton Johansson (23):
include/exec: Set default `NB_MMU_MODES` to 16
target/alpha: Remove `NB_MMU_MODES` define
target/arm: Remove `NB_MMU_MODES` define
target/avr: Remove `NB_MMU_MODES` define
target/cris: Remove `NB_MMU_MODES` define
target/hexagon: Remove `NB_MMU_MODES` define
target/hppa: Remove `NB_MMU_MODES` define
target/i386: Remove `NB_MMU_MODES` define
target/loongarch: Remove `NB_MMU_MODES` define
target/m68k: Remove `NB_MMU_MODES` define
target/microblaze: Remove `NB_MMU_MODES` define
target/mips: Remove `NB_MMU_MODES` define
target/nios2: Remove `NB_MMU_MODES` define
target/openrisc: Remove `NB_MMU_MODES` define
target/ppc: Remove `NB_MMU_MODES` define
target/riscv: Remove `NB_MMU_MODES` define
target/rx: Remove `NB_MMU_MODES` define
target/s390x: Remove `NB_MMU_MODES` define
target/sh4: Remove `NB_MMU_MODES` define
target/sparc: Remove `NB_MMU_MODES` define
target/tricore: Remove `NB_MMU_MODES` define
target/xtensa: Remove `NB_MMU_MODES` define
include/exec: Remove guards around `NB_MMU_MODES`
Richard Henderson (68):
target/mips: Drop tcg_temp_free from micromips_translate.c.inc
target/mips: Drop tcg_temp_free from msa_translate.c
target/mips: Drop tcg_temp_free from mxu_translate.c
target/mips: Drop tcg_temp_free from nanomips_translate.c.inc
target/mips: Drop tcg_temp_free from octeon_translate.c
target/mips: Drop tcg_temp_free from translate_addr_const.c
target/mips: Drop tcg_temp_free from tx79_translate.c
target/mips: Drop tcg_temp_free from vr54xx_translate.c
target/mips: Drop tcg_temp_free from translate.c
target/s390x: Drop free_compare
target/s390x: Drop tcg_temp_free from translate_vx.c.inc
target/s390x: Drop tcg_temp_free from translate.c
target/s390x: Remove assert vs g_in2
target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext
tcg: Create tcg/tcg-temp-internal.h
target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS
target/avr: Avoid use of tcg_const_i32 throughout
target/cris: Avoid use of tcg_const_i32 throughout
target/hppa: Avoid tcg_const_i64 in trans_fid_f
target/hppa: Avoid use of tcg_const_i32 throughout
target/i386: Avoid use of tcg_const_* throughout
target/m68k: Avoid tcg_const_i32 when modified
target/m68k: Avoid tcg_const_i32 in bfop_reg
target/m68k: Avoid tcg_const_* throughout
target/mips: Split out gen_lxl
target/mips: Split out gen_lxr
target/mips: Avoid tcg_const_tl in gen_r6_ld
target/mips: Avoid tcg_const_* throughout
target/ppc: Split out gen_vx_vmul10
target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad
target/rx: Use tcg_gen_abs_i32
target/rx: Use cpu_psw_z as temp in flags computation
target/rx: Avoid tcg_const_i32 when new temp needed
target/rx: Avoid tcg_const_i32
target/s390x: Avoid tcg_const_i64
target/sh4: Avoid tcg_const_i32 for TAS.B
target/sh4: Avoid tcg_const_i32
tcg/sparc: Avoid tcg_const_tl in gen_edge
target/tricore: Split t_n as constant from temp as variable
target/tricore: Rename t_off10 and use tcg_constant_i32
target/tricore: Use setcondi instead of explicit allocation
target/tricore: Drop some temp initialization
target/tricore: Avoid tcg_const_i32
tcg: Replace tcg_const_i64 in tcg-op.c
target/arm: Use rmode >= 0 for need_rmode
target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sf
target/arm: Improve arm_rmode_to_sf
target/arm: Consistently use ARMFPRounding during translation
target/arm: Create gen_set_rmode, gen_restore_rmode
target/arm: Improve trans_BFCI
target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}
target/arm: Avoid tcg_const_* in translate-mve.c
target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn
target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn
target/arm: Avoid tcg_const_ptr in handle_rev
target/m68k: Use tcg_constant_i32 in gen_ea_mode
target/ppc: Avoid tcg_const_i64 in do_vcntmb
target/ppc: Avoid tcg_const_* in vmx-impl.c.inc
target/ppc: Avoid tcg_const_* in xxeval
target/ppc: Avoid tcg_const_* in vsx-impl.c.inc
target/ppc: Avoid tcg_const_* in fp-impl.c.inc
target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc
target/ppc: Rewrite trans_ADDG6S
target/ppc: Fix gen_tlbsx_booke206
target/ppc: Avoid tcg_const_* in translate.c
target/tricore: Use min/max for saturate
tcg: Drop tcg_const_*_vec
tcg: Drop tcg_const_*
include/exec/cpu-defs.h | 9 +-
include/tcg/tcg-op.h | 4 -
include/tcg/tcg-temp-internal.h | 83 +++
include/tcg/tcg.h | 64 ---
target/alpha/cpu-param.h | 2 -
target/arm/cpu-param.h | 2 -
target/arm/internals.h | 12 +-
target/arm/tcg/translate.h | 17 +
target/avr/cpu-param.h | 1 -
target/cris/cpu-param.h | 1 -
target/hexagon/cpu-param.h | 2 -
target/hppa/cpu-param.h | 1 -
target/i386/cpu-param.h | 1 -
target/loongarch/cpu-param.h | 1 -
target/m68k/cpu-param.h | 1 -
target/microblaze/cpu-param.h | 1 -
target/microblaze/cpu.h | 2 +-
target/mips/cpu-param.h | 1 -
target/nios2/cpu-param.h | 1 -
target/openrisc/cpu-param.h | 1 -
target/ppc/cpu-param.h | 1 -
target/riscv/cpu-param.h | 1 -
target/rx/cpu-param.h | 2 -
target/s390x/cpu-param.h | 1 -
target/sh4/cpu-param.h | 1 -
target/sparc/cpu-param.h | 2 -
target/tricore/cpu-param.h | 1 -
target/xtensa/cpu-param.h | 1 -
accel/tcg/plugin-gen.c | 1 +
target/arm/tcg/translate-a64.c | 168 +++---
target/arm/tcg/translate-mve.c | 56 +-
target/arm/tcg/translate-sve.c | 28 +-
target/arm/tcg/translate-vfp.c | 26 +-
target/arm/tcg/translate.c | 14 +-
target/arm/vfp_helper.c | 35 +-
target/avr/translate.c | 48 +-
target/cris/translate.c | 46 +-
target/hppa/translate.c | 35 +-
target/i386/tcg/translate.c | 83 +--
target/m68k/translate.c | 231 ++++----
target/mips/tcg/msa_translate.c | 9 -
target/mips/tcg/mxu_translate.c | 55 +-
target/mips/tcg/octeon_translate.c | 23 -
target/mips/tcg/translate.c | 819 +++++------------------------
target/mips/tcg/translate_addr_const.c | 7 -
target/mips/tcg/tx79_translate.c | 45 +-
target/mips/tcg/vr54xx_translate.c | 4 -
target/ppc/translate.c | 148 +++---
target/rx/translate.c | 84 ++-
target/s390x/tcg/translate.c | 208 +-------
target/sh4/translate.c | 35 +-
target/sparc/translate.c | 14 +-
target/tricore/translate.c | 476 ++++++++---------
tcg/tcg-op-gvec.c | 1 +
tcg/tcg-op-vec.c | 35 +-
tcg/tcg-op.c | 13 +-
tcg/tcg.c | 17 +-
target/cris/translate_v10.c.inc | 26 +-
target/mips/tcg/micromips_translate.c.inc | 12 +-
target/mips/tcg/nanomips_translate.c.inc | 143 +----
target/ppc/power8-pmu-regs.c.inc | 4 +-
target/ppc/translate/fixedpoint-impl.c.inc | 44 +-
target/ppc/translate/fp-impl.c.inc | 26 +-
target/ppc/translate/vmx-impl.c.inc | 130 ++---
target/ppc/translate/vsx-impl.c.inc | 36 +-
target/s390x/tcg/translate_vx.c.inc | 143 -----
tcg/i386/tcg-target.c.inc | 9 +-
67 files changed, 1166 insertions(+), 2388 deletions(-)
create mode 100644 include/tcg/tcg-temp-internal.h
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PULL v3 73/91] target/arm: Improve trans_BFCI
2023-03-13 18:59 [PULL v3 00/91] tcg patch queue Richard Henderson
@ 2023-03-13 18:59 ` Richard Henderson
2023-03-14 14:28 ` [PULL v3 00/91] tcg patch queue Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2023-03-13 18:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
Reorg temporary usage so that we can use tcg_constant_i32.
tcg_gen_deposit_i32 already has a width == 32 special case,
so remove the check here.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index b70b628000..2cb9368b1b 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -7261,8 +7261,8 @@ static bool trans_UBFX(DisasContext *s, arg_UBFX *a)
static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
{
- TCGv_i32 tmp;
int msb = a->msb, lsb = a->lsb;
+ TCGv_i32 t_in, t_rd;
int width;
if (!ENABLE_ARCH_6T2) {
@@ -7277,16 +7277,14 @@ static bool trans_BFCI(DisasContext *s, arg_BFCI *a)
width = msb + 1 - lsb;
if (a->rn == 15) {
/* BFC */
- tmp = tcg_const_i32(0);
+ t_in = tcg_constant_i32(0);
} else {
/* BFI */
- tmp = load_reg(s, a->rn);
+ t_in = load_reg(s, a->rn);
}
- if (width != 32) {
- TCGv_i32 tmp2 = load_reg(s, a->rd);
- tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width);
- }
- store_reg(s, a->rd, tmp);
+ t_rd = load_reg(s, a->rd);
+ tcg_gen_deposit_i32(t_rd, t_rd, t_in, lsb, width);
+ store_reg(s, a->rd, t_rd);
return true;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PULL v3 00/91] tcg patch queue
2023-03-13 18:59 [PULL v3 00/91] tcg patch queue Richard Henderson
2023-03-13 18:59 ` [PULL v3 73/91] target/arm: Improve trans_BFCI Richard Henderson
@ 2023-03-14 14:28 ` Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2023-03-14 14:28 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Mon, 13 Mar 2023 at 18:59, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Version 3 fixes a rebase error from v2 affecting ARM BFC insn.
>
>
> r~
>
>
> The following changes since commit 29c8a9e31a982874ce4e2c15f2bf82d5f8dc3517:
>
> Merge tag 'linux-user-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2023-03-12 10:57:00 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230313
>
> for you to fetch changes up to 0c8b6b9a6383e2e37ff3d1d12b40c58b7ed36c1c:
>
> tcg: Drop tcg_const_* (2023-03-13 07:03:39 -0700)
>
> ----------------------------------------------------------------
> accel/tcg: Fix NB_MMU_MODES to 16
> Balance of the target/ patchset which eliminates tcg_temp_free
> Balance of the target/ patchset which eliminates tcg_const
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-03-14 14:45 UTC | newest]
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2023-03-13 18:59 [PULL v3 00/91] tcg patch queue Richard Henderson
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2023-03-14 14:28 ` [PULL v3 00/91] tcg patch queue Peter Maydell
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