* [PULL 0/2] riscv-to-apply queue
@ 2023-03-14 6:38 Alistair Francis
2023-03-14 6:38 ` [PULL 1/2] disas/riscv: Fix slli_uw decoding Alistair Francis
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Alistair Francis @ 2023-03-14 6:38 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Alistair Francis
From: Alistair Francis <alistair.francis@wdc.com>
The following changes since commit 284c52eec2d0a1b9c47f06c3eee46762c5fc0915:
Merge tag 'win-socket-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2023-03-13 13:44:17 +0000)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230314
for you to fetch changes up to 0d581506de803204c5a321100afa270573382932:
Fix incorrect register name in disassembler for fmv,fabs,fneg instructions (2023-03-14 16:36:43 +1000)
----------------------------------------------------------------
Seventh RISC-V PR for 8.0
* Fix slli_uw decoding
* Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
----------------------------------------------------------------
Ivan Klokov (1):
disas/riscv: Fix slli_uw decoding
Mikhail Tyutin (1):
Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
disas/riscv.c | 27 ++++++++++++++-------------
1 file changed, 14 insertions(+), 13 deletions(-)
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PULL 1/2] disas/riscv: Fix slli_uw decoding
2023-03-14 6:38 [PULL 0/2] riscv-to-apply queue Alistair Francis
@ 2023-03-14 6:38 ` Alistair Francis
2023-03-14 6:38 ` [PULL 2/2] Fix incorrect register name in disassembler for fmv, fabs, fneg instructions Alistair Francis via
2023-03-14 19:21 ` [PULL 0/2] riscv-to-apply queue Peter Maydell
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2023-03-14 6:38 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Ivan Klokov, Philipp Tomsich, Alistair Francis
From: Ivan Klokov <ivan.klokov@syntacore.com>
The decoding of the slli_uw currently contains decoding
error: shamt part of opcode has six bits, not five.
Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw")
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230227090228.17117-1-ivan.klokov@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 54455aaaa8..2aca11b90e 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1647,7 +1647,7 @@ const rv_opcode_data opcode_data[] = {
{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
+ { "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
{ "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
@@ -2617,10 +2617,10 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_addiw; break;
case 1:
- switch (((inst >> 25) & 0b1111111)) {
+ switch (((inst >> 26) & 0b111111)) {
case 0: op = rv_op_slliw; break;
- case 4: op = rv_op_slli_uw; break;
- case 48:
+ case 2: op = rv_op_slli_uw; break;
+ case 24:
switch ((inst >> 20) & 0b11111) {
case 0b00000: op = rv_op_clzw; break;
case 0b00001: op = rv_op_ctzw; break;
--
2.39.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PULL 2/2] Fix incorrect register name in disassembler for fmv, fabs, fneg instructions
2023-03-14 6:38 [PULL 0/2] riscv-to-apply queue Alistair Francis
2023-03-14 6:38 ` [PULL 1/2] disas/riscv: Fix slli_uw decoding Alistair Francis
@ 2023-03-14 6:38 ` Alistair Francis via
2023-03-14 19:21 ` [PULL 0/2] riscv-to-apply queue Peter Maydell
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis via @ 2023-03-14 6:38 UTC (permalink / raw)
To: qemu-devel; +Cc: alistair23, Mikhail Tyutin, Alistair Francis
From: Mikhail Tyutin <m.tyutin@yadro.com>
Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg instructions
Signed-off-by: Mikhail Tyutin <m.tyutin@yadro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <3454991f-7f64-24c3-9a36-f5fa2cc389e1@yadro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
disas/riscv.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 2aca11b90e..d6b0fbe5e8 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1014,6 +1014,7 @@ static const char rv_vreg_name_sym[32][4] = {
#define rv_fmt_rd_offset "O\t0,o"
#define rv_fmt_rd_rs1_rs2 "O\t0,1,2"
#define rv_fmt_frd_rs1 "O\t3,1"
+#define rv_fmt_frd_frs1 "O\t3,4"
#define rv_fmt_rd_frs1 "O\t0,4"
#define rv_fmt_rd_frs1_frs2 "O\t0,4,5"
#define rv_fmt_frd_frs1_frs2 "O\t3,4,5"
@@ -1580,15 +1581,15 @@ const rv_opcode_data opcode_data[] = {
{ "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
{ "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
{ "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
- { "fmv.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fabs.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fneg.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fmv.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fabs.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fneg.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fmv.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fabs.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
- { "fneg.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
+ { "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
+ { "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
{ "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
{ "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
{ "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
--
2.39.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PULL 0/2] riscv-to-apply queue
2023-03-14 6:38 [PULL 0/2] riscv-to-apply queue Alistair Francis
2023-03-14 6:38 ` [PULL 1/2] disas/riscv: Fix slli_uw decoding Alistair Francis
2023-03-14 6:38 ` [PULL 2/2] Fix incorrect register name in disassembler for fmv, fabs, fneg instructions Alistair Francis via
@ 2023-03-14 19:21 ` Peter Maydell
2 siblings, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2023-03-14 19:21 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel, alistair23, Alistair Francis
On Tue, 14 Mar 2023 at 06:39, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit 284c52eec2d0a1b9c47f06c3eee46762c5fc0915:
>
> Merge tag 'win-socket-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2023-03-13 13:44:17 +0000)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230314
>
> for you to fetch changes up to 0d581506de803204c5a321100afa270573382932:
>
> Fix incorrect register name in disassembler for fmv,fabs,fneg instructions (2023-03-14 16:36:43 +1000)
>
> ----------------------------------------------------------------
> Seventh RISC-V PR for 8.0
>
> * Fix slli_uw decoding
> * Fix incorrect register name in disassembler for fmv,fabs,fneg instructions
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 4+ messages in thread
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