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* [PATCH v2] arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G
@ 2023-03-15  4:25 ` Siddharth Vadapalli
  0 siblings, 0 replies; 6+ messages in thread
From: Siddharth Vadapalli @ 2023-03-15  4:25 UTC (permalink / raw)
  To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski,
	krzysztof.kozlowski+dt, afd
  Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli

Add device tree support to enable MCU CPSW with J784S4 EVM.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Hello,

Please do not merge this patch until the following have been merged:
1. https://lore.kernel.org/r/20230314085500.10597-1-j-choudhary@ti.com/
2. https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com/
3. https://lore.kernel.org/r/20230308201513.116638-1-j-choudhary@ti.com/

Changes from v1:
1. Drop patch for adding device id property for mcu_navss. This patch is
   now a part of another series at:
   https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com/
2. Move "mcu_mdio_pins_default" pinctrl to the "davinci_mdio" node.

v1:
https://lore.kernel.org/r/20230314104055.1475054-1-s-vadapalli@ti.com/

 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 50 ++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 8cd4a7ecc121..476ad8915c5b 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -140,6 +140,32 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
 	};
 };
 
+&wkup_pmx0 {
+	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+		pinctrl-single,pins = <
+			J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
+			J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
+			J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
+			J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
+			J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
+			J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
+			J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
+			J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
+			J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
+			J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
+			J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
+			J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
+		>;
+	};
+
+	mcu_mdio_pins_default: mcu-mdio-pins-default {
+		pinctrl-single,pins = <
+			J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
+			J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
+		>;
+	};
+};
+
 &main_uart8 {
 	status = "okay";
 	pinctrl-names = "default";
@@ -194,3 +220,27 @@ &main_sdhci1 {
 &main_gpio0 {
 	status = "okay";
 };
+
+&mcu_cpsw {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_cpsw_pins_default>;
+};
+
+&davinci_mdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_mdio_pins_default>;
+
+	mcu_phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+	};
+};
+
+&mcu_cpsw_port1 {
+	status = "okay";
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&mcu_phy0>;
+};
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH v2] arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G
@ 2023-03-15  4:25 ` Siddharth Vadapalli
  0 siblings, 0 replies; 6+ messages in thread
From: Siddharth Vadapalli @ 2023-03-15  4:25 UTC (permalink / raw)
  To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski,
	krzysztof.kozlowski+dt, afd
  Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli

Add device tree support to enable MCU CPSW with J784S4 EVM.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Hello,

Please do not merge this patch until the following have been merged:
1. https://lore.kernel.org/r/20230314085500.10597-1-j-choudhary@ti.com/
2. https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com/
3. https://lore.kernel.org/r/20230308201513.116638-1-j-choudhary@ti.com/

Changes from v1:
1. Drop patch for adding device id property for mcu_navss. This patch is
   now a part of another series at:
   https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com/
2. Move "mcu_mdio_pins_default" pinctrl to the "davinci_mdio" node.

v1:
https://lore.kernel.org/r/20230314104055.1475054-1-s-vadapalli@ti.com/

 arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 50 ++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 8cd4a7ecc121..476ad8915c5b 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -140,6 +140,32 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
 	};
 };
 
+&wkup_pmx0 {
+	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
+		pinctrl-single,pins = <
+			J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
+			J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
+			J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
+			J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
+			J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
+			J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
+			J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
+			J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
+			J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
+			J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
+			J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
+			J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
+		>;
+	};
+
+	mcu_mdio_pins_default: mcu-mdio-pins-default {
+		pinctrl-single,pins = <
+			J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
+			J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
+		>;
+	};
+};
+
 &main_uart8 {
 	status = "okay";
 	pinctrl-names = "default";
@@ -194,3 +220,27 @@ &main_sdhci1 {
 &main_gpio0 {
 	status = "okay";
 };
+
+&mcu_cpsw {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_cpsw_pins_default>;
+};
+
+&davinci_mdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_mdio_pins_default>;
+
+	mcu_phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+		ti,min-output-impedance;
+	};
+};
+
+&mcu_cpsw_port1 {
+	status = "okay";
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&mcu_phy0>;
+};
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G
  2023-03-15  4:25 ` Siddharth Vadapalli
@ 2023-03-15 14:42   ` Andrew Davis
  -1 siblings, 0 replies; 6+ messages in thread
From: Andrew Davis @ 2023-03-15 14:42 UTC (permalink / raw)
  To: Siddharth Vadapalli, nm, vigneshr, kristo, robh+dt,
	krzysztof.kozlowski, krzysztof.kozlowski+dt
  Cc: devicetree, linux-kernel, linux-arm-kernel, srk

On 3/14/23 11:25 PM, Siddharth Vadapalli wrote:
> Add device tree support to enable MCU CPSW with J784S4 EVM.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> Hello,
> 
> Please do not merge this patch until the following have been merged:
> 1. https://lore.kernel.org/r/20230314085500.10597-1-j-choudhary@ti.com/
> 2. https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com/
> 3. https://lore.kernel.org/r/20230308201513.116638-1-j-choudhary@ti.com/
> 
> Changes from v1:
> 1. Drop patch for adding device id property for mcu_navss. This patch is
>     now a part of another series at:
>     https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com/
> 2. Move "mcu_mdio_pins_default" pinctrl to the "davinci_mdio" node.
> 

LGTM,

Reviewed-by: Andrew Davis <afd@ti.com>

> v1:
> https://lore.kernel.org/r/20230314104055.1475054-1-s-vadapalli@ti.com/
> 
>   arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 50 ++++++++++++++++++++++++
>   1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> index 8cd4a7ecc121..476ad8915c5b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> @@ -140,6 +140,32 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
>   	};
>   };
>   
> +&wkup_pmx0 {
> +	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
> +		pinctrl-single,pins = <
> +			J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
> +			J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
> +			J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
> +			J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
> +			J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
> +			J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
> +			J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
> +			J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
> +			J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
> +			J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
> +			J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
> +			J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
> +		>;
> +	};
> +
> +	mcu_mdio_pins_default: mcu-mdio-pins-default {
> +		pinctrl-single,pins = <
> +			J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
> +			J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
> +		>;
> +	};
> +};
> +
>   &main_uart8 {
>   	status = "okay";
>   	pinctrl-names = "default";
> @@ -194,3 +220,27 @@ &main_sdhci1 {
>   &main_gpio0 {
>   	status = "okay";
>   };
> +
> +&mcu_cpsw {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mcu_cpsw_pins_default>;
> +};
> +
> +&davinci_mdio {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mcu_mdio_pins_default>;
> +
> +	mcu_phy0: ethernet-phy@0 {
> +		reg = <0>;
> +		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> +		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> +		ti,min-output-impedance;
> +	};
> +};
> +
> +&mcu_cpsw_port1 {
> +	status = "okay";
> +	phy-mode = "rgmii-rxid";
> +	phy-handle = <&mcu_phy0>;
> +};

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G
@ 2023-03-15 14:42   ` Andrew Davis
  0 siblings, 0 replies; 6+ messages in thread
From: Andrew Davis @ 2023-03-15 14:42 UTC (permalink / raw)
  To: Siddharth Vadapalli, nm, vigneshr, kristo, robh+dt,
	krzysztof.kozlowski, krzysztof.kozlowski+dt
  Cc: devicetree, linux-kernel, linux-arm-kernel, srk

On 3/14/23 11:25 PM, Siddharth Vadapalli wrote:
> Add device tree support to enable MCU CPSW with J784S4 EVM.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> Hello,
> 
> Please do not merge this patch until the following have been merged:
> 1. https://lore.kernel.org/r/20230314085500.10597-1-j-choudhary@ti.com/
> 2. https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com/
> 3. https://lore.kernel.org/r/20230308201513.116638-1-j-choudhary@ti.com/
> 
> Changes from v1:
> 1. Drop patch for adding device id property for mcu_navss. This patch is
>     now a part of another series at:
>     https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com/
> 2. Move "mcu_mdio_pins_default" pinctrl to the "davinci_mdio" node.
> 

LGTM,

Reviewed-by: Andrew Davis <afd@ti.com>

> v1:
> https://lore.kernel.org/r/20230314104055.1475054-1-s-vadapalli@ti.com/
> 
>   arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 50 ++++++++++++++++++++++++
>   1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> index 8cd4a7ecc121..476ad8915c5b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> @@ -140,6 +140,32 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
>   	};
>   };
>   
> +&wkup_pmx0 {
> +	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
> +		pinctrl-single,pins = <
> +			J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */
> +			J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */
> +			J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */
> +			J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */
> +			J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */
> +			J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */
> +			J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */
> +			J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */
> +			J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */
> +			J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */
> +			J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */
> +			J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */
> +		>;
> +	};
> +
> +	mcu_mdio_pins_default: mcu-mdio-pins-default {
> +		pinctrl-single,pins = <
> +			J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */
> +			J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */
> +		>;
> +	};
> +};
> +
>   &main_uart8 {
>   	status = "okay";
>   	pinctrl-names = "default";
> @@ -194,3 +220,27 @@ &main_sdhci1 {
>   &main_gpio0 {
>   	status = "okay";
>   };
> +
> +&mcu_cpsw {
> +	status = "okay";
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mcu_cpsw_pins_default>;
> +};
> +
> +&davinci_mdio {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&mcu_mdio_pins_default>;
> +
> +	mcu_phy0: ethernet-phy@0 {
> +		reg = <0>;
> +		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
> +		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> +		ti,min-output-impedance;
> +	};
> +};
> +
> +&mcu_cpsw_port1 {
> +	status = "okay";
> +	phy-mode = "rgmii-rxid";
> +	phy-handle = <&mcu_phy0>;
> +};

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G
  2023-03-15  4:25 ` Siddharth Vadapalli
@ 2023-03-20 22:59   ` Nishanth Menon
  -1 siblings, 0 replies; 6+ messages in thread
From: Nishanth Menon @ 2023-03-20 22:59 UTC (permalink / raw)
  To: vigneshr, kristo, robh+dt, krzysztof.kozlowski,
	krzysztof.kozlowski+dt, afd, Siddharth Vadapalli
  Cc: Nishanth Menon, devicetree, linux-kernel, linux-arm-kernel, srk

Hi Siddharth Vadapalli,

On Wed, 15 Mar 2023 09:55:48 +0530, Siddharth Vadapalli wrote:
> Add device tree support to enable MCU CPSW with J784S4 EVM.
> 
> 

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/1] arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G
      commit: 6cd4b7cfbcca4a45f06a8031f299c4019221a4ce

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G
@ 2023-03-20 22:59   ` Nishanth Menon
  0 siblings, 0 replies; 6+ messages in thread
From: Nishanth Menon @ 2023-03-20 22:59 UTC (permalink / raw)
  To: vigneshr, kristo, robh+dt, krzysztof.kozlowski,
	krzysztof.kozlowski+dt, afd, Siddharth Vadapalli
  Cc: Nishanth Menon, devicetree, linux-kernel, linux-arm-kernel, srk

Hi Siddharth Vadapalli,

On Wed, 15 Mar 2023 09:55:48 +0530, Siddharth Vadapalli wrote:
> Add device tree support to enable MCU CPSW with J784S4 EVM.
> 
> 

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/1] arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G
      commit: 6cd4b7cfbcca4a45f06a8031f299c4019221a4ce

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D


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^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-03-20 23:01 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-15  4:25 [PATCH v2] arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G Siddharth Vadapalli
2023-03-15  4:25 ` Siddharth Vadapalli
2023-03-15 14:42 ` Andrew Davis
2023-03-15 14:42   ` Andrew Davis
2023-03-20 22:59 ` Nishanth Menon
2023-03-20 22:59   ` Nishanth Menon

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