* [PATCH v2 0/3] Add timer driver for StarFive JH7110 RISC-V SoC
@ 2023-03-20 13:54 ` Xingyu Wu
0 siblings, 0 replies; 20+ messages in thread
From: Xingyu Wu @ 2023-03-20 13:54 UTC (permalink / raw)
To: linux-riscv, devicetree, Daniel Lezcano, Thomas Gleixner,
Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Xingyu Wu, Samin Guo, linux-kernel, Conor Dooley
This patch serises are to add timer driver for the StarFive JH7110
RISC-V SoC. The first patch adds documentation to describe device
tree bindings. The subsequent patch adds timer driver and support
JH7110 SoC. The last patch adds device node about timer to JH7110
dts.
This timer has four free-running 32 bit counters in StarFive JH7110
SoC. And each channel(counter) triggers an interrupt when timeout.
They support one-shot mode and continuous-run mode.
The last patch should be applied after the patchset [1]:
[1] https://lore.kernel.org/all/20230311090733.56918-1-hal.feng@starfivetech.com/
Changes since v1:
- Added description about timer and modified properties' description
in dt-bindings.
- Dropped the 'interrupt-names' and 'clock-frequency' in dt-bindings.
- Renamed the functions and added 'starfive_'
- Modified that the driver probe by platform bus.
v1 https://lore.kernel.org/all/20221223094801.181315-1-xingyu.wu@starfivetech.com/
Xingyu Wu (3):
dt-bindings: timer: Add timer for StarFive JH7110 SoC
clocksource: Add StarFive timer driver
riscv: dts: jh7110: starfive: Add timer node
.../bindings/timer/starfive,jh7110-timer.yaml | 95 +++++
MAINTAINERS | 7 +
arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 +
drivers/clocksource/Kconfig | 12 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-starfive.c | 390 ++++++++++++++++++
drivers/clocksource/timer-starfive.h | 96 +++++
7 files changed, 621 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
create mode 100644 drivers/clocksource/timer-starfive.c
create mode 100644 drivers/clocksource/timer-starfive.h
base-commit: 8ca09d5fa3549d142c2080a72a4c70ce389163cd
prerequisite-patch-id: ebaead89601acf604e83224f4df8d57a7f4331b8
prerequisite-patch-id: 609d5d7c55b0b8e2967966673dab8f62a6fceab9
prerequisite-patch-id: ac150a8c622e858e088df8121093d448df49c245
prerequisite-patch-id: a4255724d4698f1238663443024de56de38d717b
prerequisite-patch-id: 89f049f951e5acf75aab92541992f816fd0acc0d
prerequisite-patch-id: dfb8d5a1fb262127d7a8e1ef3e97f455aaa19509
prerequisite-patch-id: 11b0f5746bbfbf8aa5c5746dcd7b0dce62e7f922
prerequisite-patch-id: 315303931e4b6499de7127a88113763f86e97e16
prerequisite-patch-id: 40cb8212ddb024c20593f73d8b87d9894877e172
prerequisite-patch-id: a1673a9e9f19d6fab5a51abb721e54e36636f067
prerequisite-patch-id: 189a0f41ba4eecd4f3f35c503baac8aed8ccd7de
prerequisite-patch-id: 1117ecaa40a353c667b71802ab34ecf9568d8bb2
prerequisite-patch-id: 25923a0c77e92631ed3cd8a163d789daad35f0f8
prerequisite-patch-id: 6a6f6215f09932e68fdfd294df2e813ec9d2481f
prerequisite-patch-id: 2cc95b47cad25fd9b875d27f4e8e3d84eb70274b
prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f
prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9
prerequisite-patch-id: dbb0c0151b8bdf093e6ce79fd2fe3f60791a6e0b
prerequisite-patch-id: e7773c977a7b37692e9792b21cc4f17fa58f9215
prerequisite-patch-id: d57e95d31686772abc4c4d5aa1cadc344dc293cd
prerequisite-patch-id: 0a0ac5a8a90655b415f6b62e324f3db083cdaaee
--
2.25.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/3] Add timer driver for StarFive JH7110 RISC-V SoC
@ 2023-03-20 13:54 ` Xingyu Wu
0 siblings, 0 replies; 20+ messages in thread
From: Xingyu Wu @ 2023-03-20 13:54 UTC (permalink / raw)
To: linux-riscv, devicetree, Daniel Lezcano, Thomas Gleixner,
Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Xingyu Wu, Samin Guo, linux-kernel, Conor Dooley
This patch serises are to add timer driver for the StarFive JH7110
RISC-V SoC. The first patch adds documentation to describe device
tree bindings. The subsequent patch adds timer driver and support
JH7110 SoC. The last patch adds device node about timer to JH7110
dts.
This timer has four free-running 32 bit counters in StarFive JH7110
SoC. And each channel(counter) triggers an interrupt when timeout.
They support one-shot mode and continuous-run mode.
The last patch should be applied after the patchset [1]:
[1] https://lore.kernel.org/all/20230311090733.56918-1-hal.feng@starfivetech.com/
Changes since v1:
- Added description about timer and modified properties' description
in dt-bindings.
- Dropped the 'interrupt-names' and 'clock-frequency' in dt-bindings.
- Renamed the functions and added 'starfive_'
- Modified that the driver probe by platform bus.
v1 https://lore.kernel.org/all/20221223094801.181315-1-xingyu.wu@starfivetech.com/
Xingyu Wu (3):
dt-bindings: timer: Add timer for StarFive JH7110 SoC
clocksource: Add StarFive timer driver
riscv: dts: jh7110: starfive: Add timer node
.../bindings/timer/starfive,jh7110-timer.yaml | 95 +++++
MAINTAINERS | 7 +
arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 +
drivers/clocksource/Kconfig | 12 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-starfive.c | 390 ++++++++++++++++++
drivers/clocksource/timer-starfive.h | 96 +++++
7 files changed, 621 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
create mode 100644 drivers/clocksource/timer-starfive.c
create mode 100644 drivers/clocksource/timer-starfive.h
base-commit: 8ca09d5fa3549d142c2080a72a4c70ce389163cd
prerequisite-patch-id: ebaead89601acf604e83224f4df8d57a7f4331b8
prerequisite-patch-id: 609d5d7c55b0b8e2967966673dab8f62a6fceab9
prerequisite-patch-id: ac150a8c622e858e088df8121093d448df49c245
prerequisite-patch-id: a4255724d4698f1238663443024de56de38d717b
prerequisite-patch-id: 89f049f951e5acf75aab92541992f816fd0acc0d
prerequisite-patch-id: dfb8d5a1fb262127d7a8e1ef3e97f455aaa19509
prerequisite-patch-id: 11b0f5746bbfbf8aa5c5746dcd7b0dce62e7f922
prerequisite-patch-id: 315303931e4b6499de7127a88113763f86e97e16
prerequisite-patch-id: 40cb8212ddb024c20593f73d8b87d9894877e172
prerequisite-patch-id: a1673a9e9f19d6fab5a51abb721e54e36636f067
prerequisite-patch-id: 189a0f41ba4eecd4f3f35c503baac8aed8ccd7de
prerequisite-patch-id: 1117ecaa40a353c667b71802ab34ecf9568d8bb2
prerequisite-patch-id: 25923a0c77e92631ed3cd8a163d789daad35f0f8
prerequisite-patch-id: 6a6f6215f09932e68fdfd294df2e813ec9d2481f
prerequisite-patch-id: 2cc95b47cad25fd9b875d27f4e8e3d84eb70274b
prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f
prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9
prerequisite-patch-id: dbb0c0151b8bdf093e6ce79fd2fe3f60791a6e0b
prerequisite-patch-id: e7773c977a7b37692e9792b21cc4f17fa58f9215
prerequisite-patch-id: d57e95d31686772abc4c4d5aa1cadc344dc293cd
prerequisite-patch-id: 0a0ac5a8a90655b415f6b62e324f3db083cdaaee
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/3] dt-bindings: timer: Add timer for StarFive JH7110 SoC
2023-03-20 13:54 ` Xingyu Wu
@ 2023-03-20 13:54 ` Xingyu Wu
-1 siblings, 0 replies; 20+ messages in thread
From: Xingyu Wu @ 2023-03-20 13:54 UTC (permalink / raw)
To: linux-riscv, devicetree, Daniel Lezcano, Thomas Gleixner,
Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Xingyu Wu, Samin Guo, linux-kernel, Conor Dooley
Add bindings for the timer on the JH7110 RISC-V SoC
by StarFive Technology Ltd.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
.../bindings/timer/starfive,jh7110-timer.yaml | 95 +++++++++++++++++++
1 file changed, 95 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
new file mode 100644
index 000000000000..24b34618f2c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/starfive,jh7110-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Timer
+maintainers:
+ - Xingyu Wu <xingyu.wu@starfivetech.com>
+ - Samin Guo <samin.guo@starfivetech.com>
+
+description:
+ This timer has four free-running 32 bit counters in StarFive JH7110 SoC.
+ And each channel(counter) triggers an interrupt when timeout. They support
+ one-shot mode and continuous-run mode.
+
+properties:
+ compatible:
+ const: starfive,jh7110-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: channel 0
+ - description: channel 1
+ - description: channel 2
+ - description: channel 3
+
+ clocks:
+ items:
+ - description: timer APB
+ - description: channel 0
+ - description: channel 1
+ - description: channel 2
+ - description: channel 3
+
+ clock-names:
+ items:
+ - const: apb
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+
+ resets:
+ items:
+ - description: timer APB
+ - description: channel 0
+ - description: channel 1
+ - description: channel 2
+ - description: channel 3
+
+ reset-names:
+ items:
+ - const: apb
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ timer@13050000 {
+ compatible = "starfive,jh7110-timer";
+ reg = <0x13050000 0x10000>;
+ interrupts = <69>, <70>, <71> ,<72>;
+ clocks = <&clk 124>,
+ <&clk 125>,
+ <&clk 126>,
+ <&clk 127>,
+ <&clk 128>;
+ clock-names = "apb", "ch0", "ch1",
+ "ch2", "ch3";
+ resets = <&rst 117>,
+ <&rst 118>,
+ <&rst 119>,
+ <&rst 120>,
+ <&rst 121>;
+ reset-names = "apb", "ch0", "ch1",
+ "ch2", "ch3";
+ };
+
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 1/3] dt-bindings: timer: Add timer for StarFive JH7110 SoC
@ 2023-03-20 13:54 ` Xingyu Wu
0 siblings, 0 replies; 20+ messages in thread
From: Xingyu Wu @ 2023-03-20 13:54 UTC (permalink / raw)
To: linux-riscv, devicetree, Daniel Lezcano, Thomas Gleixner,
Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Xingyu Wu, Samin Guo, linux-kernel, Conor Dooley
Add bindings for the timer on the JH7110 RISC-V SoC
by StarFive Technology Ltd.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
.../bindings/timer/starfive,jh7110-timer.yaml | 95 +++++++++++++++++++
1 file changed, 95 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
new file mode 100644
index 000000000000..24b34618f2c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
@@ -0,0 +1,95 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/starfive,jh7110-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Timer
+maintainers:
+ - Xingyu Wu <xingyu.wu@starfivetech.com>
+ - Samin Guo <samin.guo@starfivetech.com>
+
+description:
+ This timer has four free-running 32 bit counters in StarFive JH7110 SoC.
+ And each channel(counter) triggers an interrupt when timeout. They support
+ one-shot mode and continuous-run mode.
+
+properties:
+ compatible:
+ const: starfive,jh7110-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: channel 0
+ - description: channel 1
+ - description: channel 2
+ - description: channel 3
+
+ clocks:
+ items:
+ - description: timer APB
+ - description: channel 0
+ - description: channel 1
+ - description: channel 2
+ - description: channel 3
+
+ clock-names:
+ items:
+ - const: apb
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+
+ resets:
+ items:
+ - description: timer APB
+ - description: channel 0
+ - description: channel 1
+ - description: channel 2
+ - description: channel 3
+
+ reset-names:
+ items:
+ - const: apb
+ - const: ch0
+ - const: ch1
+ - const: ch2
+ - const: ch3
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ timer@13050000 {
+ compatible = "starfive,jh7110-timer";
+ reg = <0x13050000 0x10000>;
+ interrupts = <69>, <70>, <71> ,<72>;
+ clocks = <&clk 124>,
+ <&clk 125>,
+ <&clk 126>,
+ <&clk 127>,
+ <&clk 128>;
+ clock-names = "apb", "ch0", "ch1",
+ "ch2", "ch3";
+ resets = <&rst 117>,
+ <&rst 118>,
+ <&rst 119>,
+ <&rst 120>,
+ <&rst 121>;
+ reset-names = "apb", "ch0", "ch1",
+ "ch2", "ch3";
+ };
+
--
2.25.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/3] clocksource: Add StarFive timer driver
2023-03-20 13:54 ` Xingyu Wu
@ 2023-03-20 13:54 ` Xingyu Wu
-1 siblings, 0 replies; 20+ messages in thread
From: Xingyu Wu @ 2023-03-20 13:54 UTC (permalink / raw)
To: linux-riscv, devicetree, Daniel Lezcano, Thomas Gleixner,
Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Xingyu Wu, Samin Guo, linux-kernel, Conor Dooley
Add timer driver for the StarFive JH7110 SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
MAINTAINERS | 7 +
drivers/clocksource/Kconfig | 12 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-starfive.c | 390 +++++++++++++++++++++++++++
drivers/clocksource/timer-starfive.h | 96 +++++++
5 files changed, 506 insertions(+)
create mode 100644 drivers/clocksource/timer-starfive.c
create mode 100644 drivers/clocksource/timer-starfive.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 958b7ec118b4..dac6298d8f6e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19958,6 +19958,13 @@ S: Maintained
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
F: drivers/soc/starfive/
+STARFIVE TIMER DRIVER
+M: Samin Guo <samin.guo@starfivetech.com>
+M: Xingyu Wu <xingyu.wu@starfivetech.com>
+S: Supported
+F: Documentation/devicetree/bindings/timer/starfive*
+F: drivers/clocksource/timer-starfive*
+
STARFIVE TRNG DRIVER
M: Jia Jie Ho <jiajie.ho@starfivetech.com>
S: Supported
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 5fc8f0e7fb38..35daf07d4db7 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -630,6 +630,18 @@ config RISCV_TIMER
is accessed via both the SBI and the rdcycle instruction. This is
required for all RISC-V systems.
+config STARFIVE_TIMER
+ bool "Timer for the STARFIVE SoCs"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select TIMER_OF
+ select CLKSRC_MMIO
+ default ARCH_STARFIVE
+ help
+ This enables the timer for StarFive SoCs. On RISC-V platform,
+ the system has started RISCV_TIMER. But you can also use this timer
+ to do a lot more on StarFive SoCs. This timer can provide high
+ precision and four channels to use in JH7110 SoC.
+
config CLINT_TIMER
bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
depends on GENERIC_SCHED_CLOCK && RISCV
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 64ab547de97b..276695d95cdc 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -80,6 +80,7 @@ obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o
obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
obj-$(CONFIG_X86_NUMACHIP) += numachip.o
obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o
+obj-$(CONFIG_STARFIVE_TIMER) += timer-starfive.o
obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
diff --git a/drivers/clocksource/timer-starfive.c b/drivers/clocksource/timer-starfive.c
new file mode 100644
index 000000000000..53163948ed86
--- /dev/null
+++ b/drivers/clocksource/timer-starfive.c
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Starfive Timer driver
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *
+ * Author:
+ * Xingyu Wu <xingyu.wu@starfivetech.com>
+ * Samin Guo <samin.guo@starfivetech.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/sched_clock.h>
+
+#include "timer-starfive.h"
+
+static const struct starfive_timer_chan_base starfive_timer_jh7110_base = {
+ .ctrl = STARFIVE_TIMER_JH7110_CTL,
+ .load = STARFIVE_TIMER_JH7110_LOAD,
+ .enable = STARFIVE_TIMER_JH7110_ENABLE,
+ .reload = STARFIVE_TIMER_JH7110_RELOAD,
+ .value = STARFIVE_TIMER_JH7110_VALUE,
+ .intclr = STARFIVE_TIMER_JH7110_INT_CLR,
+ .intmask = STARFIVE_TIMER_JH7110_INT_MASK,
+ .channel_num = STARFIVE_TIMER_CH_4,
+ .channel_base = {STARFIVE_TIMER_CH_BASE(0), STARFIVE_TIMER_CH_BASE(1),
+ STARFIVE_TIMER_CH_BASE(2), STARFIVE_TIMER_CH_BASE(3)},
+};
+
+static inline struct starfive_clkevt *to_starfive_clkevt(struct clock_event_device *evt)
+{
+ return container_of(evt, struct starfive_clkevt, evt);
+}
+
+/* 0:continuous-run mode, 1:single-run mode */
+static inline void starfive_timer_set_mod(struct starfive_clkevt *clkevt, int mod)
+{
+ writel(mod, clkevt->ctrl);
+}
+
+/* Interrupt Mask Register, 0:Unmask, 1:Mask */
+static inline void starfive_timer_int_enable(struct starfive_clkevt *clkevt)
+{
+ writel(STARFIVE_TIMER_INTMASK_DIS, clkevt->intmask);
+}
+
+static inline void starfive_timer_int_disable(struct starfive_clkevt *clkevt)
+{
+ writel(STARFIVE_TIMER_INTMASK_ENA, clkevt->intmask);
+}
+
+/*
+ * BIT(0): Read value represent channel intr status.
+ * Write 1 to this bit to clear interrupt. Write 0 has no effects.
+ * BIT(1): "1" means that it is clearing interrupt. BIT(0) can not be written.
+ */
+static inline int starfive_timer_int_clear(struct starfive_clkevt *clkevt)
+{
+ u32 value;
+ int ret;
+
+ /* waiting interrupt can be to clearing */
+ ret = readl_poll_timeout_atomic(clkevt->intclr, value,
+ !(value & STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK),
+ STARFIVE_DELAY_US, STARFIVE_TIMEOUT_US);
+ if (!ret)
+ writel(0x1, clkevt->intclr);
+
+ return ret;
+}
+
+/*
+ * The initial value to be loaded into the
+ * counter and is also used as the reload value.
+ * val = clock rate --> 1s
+ */
+static inline void starfive_timer_set_load(struct starfive_clkevt *clkevt, u32 val)
+{
+ writel(val, clkevt->load);
+}
+
+static inline u32 starfive_timer_get_val(struct starfive_clkevt *clkevt)
+{
+ return readl(clkevt->value);
+}
+
+/*
+ * Write RELOAD register to reload preset value to counter.
+ * (Write 0 and write 1 are both ok)
+ */
+static inline void starfive_timer_set_reload(struct starfive_clkevt *clkevt)
+{
+ writel(0, clkevt->reload);
+}
+
+static inline void starfive_timer_enable(struct starfive_clkevt *clkevt)
+{
+ writel(STARFIVE_TIMER_ENA, clkevt->enable);
+}
+
+static inline void starfive_timer_disable(struct starfive_clkevt *clkevt)
+{
+ writel(STARFIVE_TIMER_DIS, clkevt->enable);
+}
+
+static int starfive_timer_int_init_enable(struct starfive_clkevt *clkevt)
+{
+ int ret;
+
+ starfive_timer_int_disable(clkevt);
+ ret = starfive_timer_int_clear(clkevt);
+ if (ret)
+ return ret;
+
+ starfive_timer_int_enable(clkevt);
+ starfive_timer_enable(clkevt);
+
+ return 0;
+}
+
+static int starfive_timer_shutdown(struct clock_event_device *evt)
+{
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ starfive_timer_disable(clkevt);
+ return starfive_timer_int_clear(clkevt);
+}
+
+static void starfive_timer_suspend(struct clock_event_device *evt)
+{
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ clkevt->reload_val = starfive_timer_get_val(clkevt);
+ starfive_timer_shutdown(evt);
+}
+
+static void starfive_timer_resume(struct clock_event_device *evt)
+{
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ starfive_timer_set_load(clkevt, clkevt->reload_val);
+ starfive_timer_set_reload(clkevt);
+ starfive_timer_int_enable(clkevt);
+ starfive_timer_enable(clkevt);
+}
+
+static int starfive_timer_tick_resume(struct clock_event_device *evt)
+{
+ starfive_timer_resume(evt);
+
+ return 0;
+}
+
+static int starfive_clocksource_init(struct starfive_clkevt *clkevt)
+{
+ int ret;
+
+ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
+ starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
+ ret = starfive_timer_int_init_enable(clkevt);
+ if (ret)
+ return ret;
+
+ return clocksource_mmio_init(clkevt->value, clkevt->name, clkevt->rate,
+ STARFIVE_CLOCK_SOURCE_RATING, STARFIVE_VALID_BITS,
+ clocksource_mmio_readl_down);
+}
+
+/* IRQ handler for the timer */
+static irqreturn_t starfive_timer_interrupt(int irq, void *priv)
+{
+ struct clock_event_device *evt = (struct clock_event_device *)priv;
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ if (starfive_timer_int_clear(clkevt))
+ return IRQ_NONE;
+
+ if (evt->event_handler)
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static int starfive_timer_set_periodic(struct clock_event_device *evt)
+{
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ starfive_timer_disable(clkevt);
+ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
+ starfive_timer_set_load(clkevt, clkevt->periodic);
+
+ return starfive_timer_int_init_enable(clkevt);
+}
+
+static int starfive_timer_set_oneshot(struct clock_event_device *evt)
+{
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ starfive_timer_disable(clkevt);
+ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
+ starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
+
+ return starfive_timer_int_init_enable(clkevt);
+}
+
+static int starfive_timer_set_next_event(unsigned long next,
+ struct clock_event_device *evt)
+{
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ starfive_timer_disable(clkevt);
+ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
+ starfive_timer_set_load(clkevt, next);
+ starfive_timer_enable(clkevt);
+
+ return 0;
+}
+
+static void starfive_set_clockevent(struct clock_event_device *evt)
+{
+ evt->features = CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_DYNIRQ;
+ evt->set_state_shutdown = starfive_timer_shutdown;
+ evt->set_state_periodic = starfive_timer_set_periodic;
+ evt->set_state_oneshot = starfive_timer_set_oneshot;
+ evt->set_state_oneshot_stopped = starfive_timer_shutdown;
+ evt->tick_resume = starfive_timer_tick_resume;
+ evt->set_next_event = starfive_timer_set_next_event;
+ evt->suspend = starfive_timer_suspend;
+ evt->resume = starfive_timer_resume;
+ evt->rating = STARFIVE_CLOCKEVENT_RATING;
+}
+
+static void starfive_clockevents_register(struct starfive_clkevt *clkevt)
+{
+ clkevt->rate = clk_get_rate(clkevt->clk);
+ clkevt->periodic = DIV_ROUND_CLOSEST(clkevt->rate, HZ);
+
+ starfive_set_clockevent(&clkevt->evt);
+ clkevt->evt.name = clkevt->name;
+ clkevt->evt.irq = clkevt->irq;
+ clkevt->evt.cpumask = cpu_possible_mask;
+
+ clockevents_config_and_register(&clkevt->evt, clkevt->rate,
+ STARFIVE_TIMER_MIN_TICKS, STARFIVE_TIMER_MAX_TICKS);
+}
+
+static void __init starfive_clkevt_base_init(const struct starfive_timer_chan_base *timer,
+ struct starfive_clkevt *clkevt,
+ void __iomem *base, int ch)
+{
+ void __iomem *channel_base;
+
+ channel_base = base + timer->channel_base[ch];
+ clkevt->base = channel_base;
+ clkevt->ctrl = channel_base + timer->ctrl;
+ clkevt->load = channel_base + timer->load;
+ clkevt->enable = channel_base + timer->enable;
+ clkevt->reload = channel_base + timer->reload;
+ clkevt->value = channel_base + timer->value;
+ clkevt->intclr = channel_base + timer->intclr;
+ clkevt->intmask = channel_base + timer->intmask;
+}
+
+static int __init starfive_timer_probe(struct platform_device *pdev)
+{
+ const struct starfive_timer_chan_base *timer_base = of_device_get_match_data(&pdev->dev);
+ char name[10];
+ struct starfive_timer_priv *priv;
+ struct starfive_clkevt *clkevt;
+ struct clk *pclk;
+ struct reset_control *rst;
+ int ch;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, struct_size(priv, clkevt, timer_base->channel_num),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->base),
+ "failed to map registers\n");
+
+ rst = devm_reset_control_get_exclusive(&pdev->dev, "apb");
+ if (IS_ERR(rst))
+ return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get apb reset\n");
+
+ pclk = devm_clk_get_enabled(&pdev->dev, "apb");
+ if (IS_ERR(pclk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pclk),
+ "failed to get & enable apb clock\n");
+
+ ret = reset_control_deassert(rst);
+ if (ret)
+ goto err;
+
+ priv->dev = &pdev->dev;
+ platform_set_drvdata(pdev, priv);
+
+ for (ch = 0; ch < timer_base->channel_num; ch++) {
+ clkevt = &priv->clkevt[ch];
+ snprintf(name, sizeof(name), "ch%d", ch);
+
+ starfive_clkevt_base_init(timer_base, clkevt, priv->base, ch);
+ /* Ensure timers are disabled */
+ starfive_timer_disable(clkevt);
+
+ rst = devm_reset_control_get_exclusive(&pdev->dev, name);
+ if (IS_ERR(rst)) {
+ ret = PTR_ERR(rst);
+ goto err;
+ }
+
+ clkevt->clk = devm_clk_get_enabled(&pdev->dev, name);
+ if (IS_ERR(clkevt->clk)) {
+ ret = PTR_ERR(clkevt->clk);
+ goto err;
+ }
+
+ ret = reset_control_deassert(rst);
+ if (ret)
+ goto ch_err;
+
+ clkevt->irq = platform_get_irq(pdev, ch);
+ if (clkevt->irq < 0) {
+ ret = clkevt->irq;
+ goto ch_err;
+ }
+
+ snprintf(clkevt->name, sizeof(clkevt->name), "%s.ch%d", pdev->name, ch);
+ starfive_clockevents_register(clkevt);
+
+ ret = devm_request_irq(&pdev->dev, clkevt->irq, starfive_timer_interrupt,
+ IRQF_TIMER | IRQF_IRQPOLL,
+ clkevt->name, &clkevt->evt);
+ if (ret)
+ goto ch_err;
+
+ ret = starfive_clocksource_init(clkevt);
+ if (ret)
+ goto ch_err;
+ }
+
+ return 0;
+
+ch_err:
+ /* Only unregister the failed channel and the rest timer channels continue to work. */
+ clk_disable_unprepare(clkevt->clk);
+err:
+ /* If no other channel successfully registers, pclk should be disabled. */
+ if (!ch)
+ clk_disable_unprepare(pclk);
+
+ return ret;
+}
+
+static const struct of_device_id starfive_timer_match[] = {
+ { .compatible = "starfive,jh7110-timer", .data = &starfive_timer_jh7110_base },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, starfive_timer_match);
+
+static struct platform_driver starfive_timer_driver = {
+ .probe = starfive_timer_probe,
+ .driver = {
+ .name = "starfive-timer",
+ .of_match_table = starfive_timer_match,
+ },
+};
+module_platform_driver(starfive_timer_driver);
+
+MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive timer driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clocksource/timer-starfive.h b/drivers/clocksource/timer-starfive.h
new file mode 100644
index 000000000000..62eb630cc98d
--- /dev/null
+++ b/drivers/clocksource/timer-starfive.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __STARFIVE_TIMER_H__
+#define __STARFIVE_TIMER_H__
+
+/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */
+#define STARFIVE_TIMER_CH_LEN 0x40
+#define STARFIVE_TIMER_CH_BASE(x) ((STARFIVE_TIMER_CH_##x) * STARFIVE_TIMER_CH_LEN)
+
+#define STARFIVE_CLOCK_SOURCE_RATING 200
+#define STARFIVE_VALID_BITS 32
+#define STARFIVE_DELAY_US 0
+#define STARFIVE_TIMEOUT_US 10000
+#define STARFIVE_CLOCKEVENT_RATING 300
+#define STARFIVE_TIMER_MAX_TICKS 0xffffffff
+#define STARFIVE_TIMER_MIN_TICKS 0xf
+
+#define STARFIVE_TIMER_JH7110_INT_STATUS 0x00 /* RO[0:4]: Interrupt Status for channel0~4 */
+#define STARFIVE_TIMER_JH7110_CTL 0x04 /* RW[0]: 0-continuous run, 1-single run */
+#define STARFIVE_TIMER_JH7110_LOAD 0x08 /* RW: load value to counter */
+#define STARFIVE_TIMER_JH7110_ENABLE 0x10 /* RW[0]: timer enable register */
+#define STARFIVE_TIMER_JH7110_RELOAD 0x14 /* RW: write 1 or 0 both reload counter */
+#define STARFIVE_TIMER_JH7110_VALUE 0x18 /* RO: timer value register */
+#define STARFIVE_TIMER_JH7110_INT_CLR 0x20 /* RW: timer interrupt clear register */
+#define STARFIVE_TIMER_JH7110_INT_MASK 0x24 /* RW[0]: timer interrupt mask register */
+#define STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK BIT(1)
+
+enum STARFIVE_TIMER_CH {
+ STARFIVE_TIMER_CH_0 = 0,
+ STARFIVE_TIMER_CH_1,
+ STARFIVE_TIMER_CH_2,
+ STARFIVE_TIMER_CH_3,
+ STARFIVE_TIMER_CH_4,
+ STARFIVE_TIMER_CH_5,
+ STARFIVE_TIMER_CH_6,
+ STARFIVE_TIMER_CH_7,
+ STARFIVE_TIMER_CH_MAX
+};
+
+enum STARFIVE_TIMER_INTMASK {
+ STARFIVE_TIMER_INTMASK_DIS = 0,
+ STARFIVE_TIMER_INTMASK_ENA = 1
+};
+
+enum STARFIVE_TIMER_MOD {
+ STARFIVE_TIMER_MOD_CONTIN = 0,
+ STARFIVE_TIMER_MOD_SINGLE = 1
+};
+
+enum STARFIVE_TIMER_CTL_EN {
+ STARFIVE_TIMER_DIS = 0,
+ STARFIVE_TIMER_ENA = 1
+};
+
+struct starfive_timer_chan_base {
+ /* Resgister */
+ unsigned int ctrl;
+ unsigned int load;
+ unsigned int enable;
+ unsigned int reload;
+ unsigned int value;
+ unsigned int intclr;
+ unsigned int intmask;
+
+ unsigned int channel_num; /* timer channel numbers */
+ unsigned int channel_base[];
+};
+
+struct starfive_clkevt {
+ struct clock_event_device evt;
+ struct clk *clk;
+ char name[20];
+ int irq;
+ u32 periodic;
+ u32 rate;
+ u32 reload_val;
+ void __iomem *base;
+ void __iomem *ctrl;
+ void __iomem *load;
+ void __iomem *enable;
+ void __iomem *reload;
+ void __iomem *value;
+ void __iomem *intclr;
+ void __iomem *intmask;
+};
+
+struct starfive_timer_priv {
+ struct device *dev;
+ void __iomem *base;
+ struct starfive_clkevt clkevt[];
+};
+
+#endif /* __STARFIVE_TIMER_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/3] clocksource: Add StarFive timer driver
@ 2023-03-20 13:54 ` Xingyu Wu
0 siblings, 0 replies; 20+ messages in thread
From: Xingyu Wu @ 2023-03-20 13:54 UTC (permalink / raw)
To: linux-riscv, devicetree, Daniel Lezcano, Thomas Gleixner,
Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Xingyu Wu, Samin Guo, linux-kernel, Conor Dooley
Add timer driver for the StarFive JH7110 SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
MAINTAINERS | 7 +
drivers/clocksource/Kconfig | 12 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-starfive.c | 390 +++++++++++++++++++++++++++
drivers/clocksource/timer-starfive.h | 96 +++++++
5 files changed, 506 insertions(+)
create mode 100644 drivers/clocksource/timer-starfive.c
create mode 100644 drivers/clocksource/timer-starfive.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 958b7ec118b4..dac6298d8f6e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19958,6 +19958,13 @@ S: Maintained
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
F: drivers/soc/starfive/
+STARFIVE TIMER DRIVER
+M: Samin Guo <samin.guo@starfivetech.com>
+M: Xingyu Wu <xingyu.wu@starfivetech.com>
+S: Supported
+F: Documentation/devicetree/bindings/timer/starfive*
+F: drivers/clocksource/timer-starfive*
+
STARFIVE TRNG DRIVER
M: Jia Jie Ho <jiajie.ho@starfivetech.com>
S: Supported
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 5fc8f0e7fb38..35daf07d4db7 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -630,6 +630,18 @@ config RISCV_TIMER
is accessed via both the SBI and the rdcycle instruction. This is
required for all RISC-V systems.
+config STARFIVE_TIMER
+ bool "Timer for the STARFIVE SoCs"
+ depends on ARCH_STARFIVE || COMPILE_TEST
+ select TIMER_OF
+ select CLKSRC_MMIO
+ default ARCH_STARFIVE
+ help
+ This enables the timer for StarFive SoCs. On RISC-V platform,
+ the system has started RISCV_TIMER. But you can also use this timer
+ to do a lot more on StarFive SoCs. This timer can provide high
+ precision and four channels to use in JH7110 SoC.
+
config CLINT_TIMER
bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
depends on GENERIC_SCHED_CLOCK && RISCV
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 64ab547de97b..276695d95cdc 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -80,6 +80,7 @@ obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o
obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
obj-$(CONFIG_X86_NUMACHIP) += numachip.o
obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o
+obj-$(CONFIG_STARFIVE_TIMER) += timer-starfive.o
obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
diff --git a/drivers/clocksource/timer-starfive.c b/drivers/clocksource/timer-starfive.c
new file mode 100644
index 000000000000..53163948ed86
--- /dev/null
+++ b/drivers/clocksource/timer-starfive.c
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Starfive Timer driver
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ *
+ * Author:
+ * Xingyu Wu <xingyu.wu@starfivetech.com>
+ * Samin Guo <samin.guo@starfivetech.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/sched_clock.h>
+
+#include "timer-starfive.h"
+
+static const struct starfive_timer_chan_base starfive_timer_jh7110_base = {
+ .ctrl = STARFIVE_TIMER_JH7110_CTL,
+ .load = STARFIVE_TIMER_JH7110_LOAD,
+ .enable = STARFIVE_TIMER_JH7110_ENABLE,
+ .reload = STARFIVE_TIMER_JH7110_RELOAD,
+ .value = STARFIVE_TIMER_JH7110_VALUE,
+ .intclr = STARFIVE_TIMER_JH7110_INT_CLR,
+ .intmask = STARFIVE_TIMER_JH7110_INT_MASK,
+ .channel_num = STARFIVE_TIMER_CH_4,
+ .channel_base = {STARFIVE_TIMER_CH_BASE(0), STARFIVE_TIMER_CH_BASE(1),
+ STARFIVE_TIMER_CH_BASE(2), STARFIVE_TIMER_CH_BASE(3)},
+};
+
+static inline struct starfive_clkevt *to_starfive_clkevt(struct clock_event_device *evt)
+{
+ return container_of(evt, struct starfive_clkevt, evt);
+}
+
+/* 0:continuous-run mode, 1:single-run mode */
+static inline void starfive_timer_set_mod(struct starfive_clkevt *clkevt, int mod)
+{
+ writel(mod, clkevt->ctrl);
+}
+
+/* Interrupt Mask Register, 0:Unmask, 1:Mask */
+static inline void starfive_timer_int_enable(struct starfive_clkevt *clkevt)
+{
+ writel(STARFIVE_TIMER_INTMASK_DIS, clkevt->intmask);
+}
+
+static inline void starfive_timer_int_disable(struct starfive_clkevt *clkevt)
+{
+ writel(STARFIVE_TIMER_INTMASK_ENA, clkevt->intmask);
+}
+
+/*
+ * BIT(0): Read value represent channel intr status.
+ * Write 1 to this bit to clear interrupt. Write 0 has no effects.
+ * BIT(1): "1" means that it is clearing interrupt. BIT(0) can not be written.
+ */
+static inline int starfive_timer_int_clear(struct starfive_clkevt *clkevt)
+{
+ u32 value;
+ int ret;
+
+ /* waiting interrupt can be to clearing */
+ ret = readl_poll_timeout_atomic(clkevt->intclr, value,
+ !(value & STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK),
+ STARFIVE_DELAY_US, STARFIVE_TIMEOUT_US);
+ if (!ret)
+ writel(0x1, clkevt->intclr);
+
+ return ret;
+}
+
+/*
+ * The initial value to be loaded into the
+ * counter and is also used as the reload value.
+ * val = clock rate --> 1s
+ */
+static inline void starfive_timer_set_load(struct starfive_clkevt *clkevt, u32 val)
+{
+ writel(val, clkevt->load);
+}
+
+static inline u32 starfive_timer_get_val(struct starfive_clkevt *clkevt)
+{
+ return readl(clkevt->value);
+}
+
+/*
+ * Write RELOAD register to reload preset value to counter.
+ * (Write 0 and write 1 are both ok)
+ */
+static inline void starfive_timer_set_reload(struct starfive_clkevt *clkevt)
+{
+ writel(0, clkevt->reload);
+}
+
+static inline void starfive_timer_enable(struct starfive_clkevt *clkevt)
+{
+ writel(STARFIVE_TIMER_ENA, clkevt->enable);
+}
+
+static inline void starfive_timer_disable(struct starfive_clkevt *clkevt)
+{
+ writel(STARFIVE_TIMER_DIS, clkevt->enable);
+}
+
+static int starfive_timer_int_init_enable(struct starfive_clkevt *clkevt)
+{
+ int ret;
+
+ starfive_timer_int_disable(clkevt);
+ ret = starfive_timer_int_clear(clkevt);
+ if (ret)
+ return ret;
+
+ starfive_timer_int_enable(clkevt);
+ starfive_timer_enable(clkevt);
+
+ return 0;
+}
+
+static int starfive_timer_shutdown(struct clock_event_device *evt)
+{
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ starfive_timer_disable(clkevt);
+ return starfive_timer_int_clear(clkevt);
+}
+
+static void starfive_timer_suspend(struct clock_event_device *evt)
+{
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ clkevt->reload_val = starfive_timer_get_val(clkevt);
+ starfive_timer_shutdown(evt);
+}
+
+static void starfive_timer_resume(struct clock_event_device *evt)
+{
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ starfive_timer_set_load(clkevt, clkevt->reload_val);
+ starfive_timer_set_reload(clkevt);
+ starfive_timer_int_enable(clkevt);
+ starfive_timer_enable(clkevt);
+}
+
+static int starfive_timer_tick_resume(struct clock_event_device *evt)
+{
+ starfive_timer_resume(evt);
+
+ return 0;
+}
+
+static int starfive_clocksource_init(struct starfive_clkevt *clkevt)
+{
+ int ret;
+
+ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
+ starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
+ ret = starfive_timer_int_init_enable(clkevt);
+ if (ret)
+ return ret;
+
+ return clocksource_mmio_init(clkevt->value, clkevt->name, clkevt->rate,
+ STARFIVE_CLOCK_SOURCE_RATING, STARFIVE_VALID_BITS,
+ clocksource_mmio_readl_down);
+}
+
+/* IRQ handler for the timer */
+static irqreturn_t starfive_timer_interrupt(int irq, void *priv)
+{
+ struct clock_event_device *evt = (struct clock_event_device *)priv;
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ if (starfive_timer_int_clear(clkevt))
+ return IRQ_NONE;
+
+ if (evt->event_handler)
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static int starfive_timer_set_periodic(struct clock_event_device *evt)
+{
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ starfive_timer_disable(clkevt);
+ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
+ starfive_timer_set_load(clkevt, clkevt->periodic);
+
+ return starfive_timer_int_init_enable(clkevt);
+}
+
+static int starfive_timer_set_oneshot(struct clock_event_device *evt)
+{
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ starfive_timer_disable(clkevt);
+ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
+ starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
+
+ return starfive_timer_int_init_enable(clkevt);
+}
+
+static int starfive_timer_set_next_event(unsigned long next,
+ struct clock_event_device *evt)
+{
+ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
+
+ starfive_timer_disable(clkevt);
+ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
+ starfive_timer_set_load(clkevt, next);
+ starfive_timer_enable(clkevt);
+
+ return 0;
+}
+
+static void starfive_set_clockevent(struct clock_event_device *evt)
+{
+ evt->features = CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_DYNIRQ;
+ evt->set_state_shutdown = starfive_timer_shutdown;
+ evt->set_state_periodic = starfive_timer_set_periodic;
+ evt->set_state_oneshot = starfive_timer_set_oneshot;
+ evt->set_state_oneshot_stopped = starfive_timer_shutdown;
+ evt->tick_resume = starfive_timer_tick_resume;
+ evt->set_next_event = starfive_timer_set_next_event;
+ evt->suspend = starfive_timer_suspend;
+ evt->resume = starfive_timer_resume;
+ evt->rating = STARFIVE_CLOCKEVENT_RATING;
+}
+
+static void starfive_clockevents_register(struct starfive_clkevt *clkevt)
+{
+ clkevt->rate = clk_get_rate(clkevt->clk);
+ clkevt->periodic = DIV_ROUND_CLOSEST(clkevt->rate, HZ);
+
+ starfive_set_clockevent(&clkevt->evt);
+ clkevt->evt.name = clkevt->name;
+ clkevt->evt.irq = clkevt->irq;
+ clkevt->evt.cpumask = cpu_possible_mask;
+
+ clockevents_config_and_register(&clkevt->evt, clkevt->rate,
+ STARFIVE_TIMER_MIN_TICKS, STARFIVE_TIMER_MAX_TICKS);
+}
+
+static void __init starfive_clkevt_base_init(const struct starfive_timer_chan_base *timer,
+ struct starfive_clkevt *clkevt,
+ void __iomem *base, int ch)
+{
+ void __iomem *channel_base;
+
+ channel_base = base + timer->channel_base[ch];
+ clkevt->base = channel_base;
+ clkevt->ctrl = channel_base + timer->ctrl;
+ clkevt->load = channel_base + timer->load;
+ clkevt->enable = channel_base + timer->enable;
+ clkevt->reload = channel_base + timer->reload;
+ clkevt->value = channel_base + timer->value;
+ clkevt->intclr = channel_base + timer->intclr;
+ clkevt->intmask = channel_base + timer->intmask;
+}
+
+static int __init starfive_timer_probe(struct platform_device *pdev)
+{
+ const struct starfive_timer_chan_base *timer_base = of_device_get_match_data(&pdev->dev);
+ char name[10];
+ struct starfive_timer_priv *priv;
+ struct starfive_clkevt *clkevt;
+ struct clk *pclk;
+ struct reset_control *rst;
+ int ch;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, struct_size(priv, clkevt, timer_base->channel_num),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->base),
+ "failed to map registers\n");
+
+ rst = devm_reset_control_get_exclusive(&pdev->dev, "apb");
+ if (IS_ERR(rst))
+ return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get apb reset\n");
+
+ pclk = devm_clk_get_enabled(&pdev->dev, "apb");
+ if (IS_ERR(pclk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pclk),
+ "failed to get & enable apb clock\n");
+
+ ret = reset_control_deassert(rst);
+ if (ret)
+ goto err;
+
+ priv->dev = &pdev->dev;
+ platform_set_drvdata(pdev, priv);
+
+ for (ch = 0; ch < timer_base->channel_num; ch++) {
+ clkevt = &priv->clkevt[ch];
+ snprintf(name, sizeof(name), "ch%d", ch);
+
+ starfive_clkevt_base_init(timer_base, clkevt, priv->base, ch);
+ /* Ensure timers are disabled */
+ starfive_timer_disable(clkevt);
+
+ rst = devm_reset_control_get_exclusive(&pdev->dev, name);
+ if (IS_ERR(rst)) {
+ ret = PTR_ERR(rst);
+ goto err;
+ }
+
+ clkevt->clk = devm_clk_get_enabled(&pdev->dev, name);
+ if (IS_ERR(clkevt->clk)) {
+ ret = PTR_ERR(clkevt->clk);
+ goto err;
+ }
+
+ ret = reset_control_deassert(rst);
+ if (ret)
+ goto ch_err;
+
+ clkevt->irq = platform_get_irq(pdev, ch);
+ if (clkevt->irq < 0) {
+ ret = clkevt->irq;
+ goto ch_err;
+ }
+
+ snprintf(clkevt->name, sizeof(clkevt->name), "%s.ch%d", pdev->name, ch);
+ starfive_clockevents_register(clkevt);
+
+ ret = devm_request_irq(&pdev->dev, clkevt->irq, starfive_timer_interrupt,
+ IRQF_TIMER | IRQF_IRQPOLL,
+ clkevt->name, &clkevt->evt);
+ if (ret)
+ goto ch_err;
+
+ ret = starfive_clocksource_init(clkevt);
+ if (ret)
+ goto ch_err;
+ }
+
+ return 0;
+
+ch_err:
+ /* Only unregister the failed channel and the rest timer channels continue to work. */
+ clk_disable_unprepare(clkevt->clk);
+err:
+ /* If no other channel successfully registers, pclk should be disabled. */
+ if (!ch)
+ clk_disable_unprepare(pclk);
+
+ return ret;
+}
+
+static const struct of_device_id starfive_timer_match[] = {
+ { .compatible = "starfive,jh7110-timer", .data = &starfive_timer_jh7110_base },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, starfive_timer_match);
+
+static struct platform_driver starfive_timer_driver = {
+ .probe = starfive_timer_probe,
+ .driver = {
+ .name = "starfive-timer",
+ .of_match_table = starfive_timer_match,
+ },
+};
+module_platform_driver(starfive_timer_driver);
+
+MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive timer driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clocksource/timer-starfive.h b/drivers/clocksource/timer-starfive.h
new file mode 100644
index 000000000000..62eb630cc98d
--- /dev/null
+++ b/drivers/clocksource/timer-starfive.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __STARFIVE_TIMER_H__
+#define __STARFIVE_TIMER_H__
+
+/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */
+#define STARFIVE_TIMER_CH_LEN 0x40
+#define STARFIVE_TIMER_CH_BASE(x) ((STARFIVE_TIMER_CH_##x) * STARFIVE_TIMER_CH_LEN)
+
+#define STARFIVE_CLOCK_SOURCE_RATING 200
+#define STARFIVE_VALID_BITS 32
+#define STARFIVE_DELAY_US 0
+#define STARFIVE_TIMEOUT_US 10000
+#define STARFIVE_CLOCKEVENT_RATING 300
+#define STARFIVE_TIMER_MAX_TICKS 0xffffffff
+#define STARFIVE_TIMER_MIN_TICKS 0xf
+
+#define STARFIVE_TIMER_JH7110_INT_STATUS 0x00 /* RO[0:4]: Interrupt Status for channel0~4 */
+#define STARFIVE_TIMER_JH7110_CTL 0x04 /* RW[0]: 0-continuous run, 1-single run */
+#define STARFIVE_TIMER_JH7110_LOAD 0x08 /* RW: load value to counter */
+#define STARFIVE_TIMER_JH7110_ENABLE 0x10 /* RW[0]: timer enable register */
+#define STARFIVE_TIMER_JH7110_RELOAD 0x14 /* RW: write 1 or 0 both reload counter */
+#define STARFIVE_TIMER_JH7110_VALUE 0x18 /* RO: timer value register */
+#define STARFIVE_TIMER_JH7110_INT_CLR 0x20 /* RW: timer interrupt clear register */
+#define STARFIVE_TIMER_JH7110_INT_MASK 0x24 /* RW[0]: timer interrupt mask register */
+#define STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK BIT(1)
+
+enum STARFIVE_TIMER_CH {
+ STARFIVE_TIMER_CH_0 = 0,
+ STARFIVE_TIMER_CH_1,
+ STARFIVE_TIMER_CH_2,
+ STARFIVE_TIMER_CH_3,
+ STARFIVE_TIMER_CH_4,
+ STARFIVE_TIMER_CH_5,
+ STARFIVE_TIMER_CH_6,
+ STARFIVE_TIMER_CH_7,
+ STARFIVE_TIMER_CH_MAX
+};
+
+enum STARFIVE_TIMER_INTMASK {
+ STARFIVE_TIMER_INTMASK_DIS = 0,
+ STARFIVE_TIMER_INTMASK_ENA = 1
+};
+
+enum STARFIVE_TIMER_MOD {
+ STARFIVE_TIMER_MOD_CONTIN = 0,
+ STARFIVE_TIMER_MOD_SINGLE = 1
+};
+
+enum STARFIVE_TIMER_CTL_EN {
+ STARFIVE_TIMER_DIS = 0,
+ STARFIVE_TIMER_ENA = 1
+};
+
+struct starfive_timer_chan_base {
+ /* Resgister */
+ unsigned int ctrl;
+ unsigned int load;
+ unsigned int enable;
+ unsigned int reload;
+ unsigned int value;
+ unsigned int intclr;
+ unsigned int intmask;
+
+ unsigned int channel_num; /* timer channel numbers */
+ unsigned int channel_base[];
+};
+
+struct starfive_clkevt {
+ struct clock_event_device evt;
+ struct clk *clk;
+ char name[20];
+ int irq;
+ u32 periodic;
+ u32 rate;
+ u32 reload_val;
+ void __iomem *base;
+ void __iomem *ctrl;
+ void __iomem *load;
+ void __iomem *enable;
+ void __iomem *reload;
+ void __iomem *value;
+ void __iomem *intclr;
+ void __iomem *intmask;
+};
+
+struct starfive_timer_priv {
+ struct device *dev;
+ void __iomem *base;
+ struct starfive_clkevt clkevt[];
+};
+
+#endif /* __STARFIVE_TIMER_H__ */
--
2.25.1
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^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 3/3] riscv: dts: jh7110: starfive: Add timer node
2023-03-20 13:54 ` Xingyu Wu
@ 2023-03-20 13:54 ` Xingyu Wu
-1 siblings, 0 replies; 20+ messages in thread
From: Xingyu Wu @ 2023-03-20 13:54 UTC (permalink / raw)
To: linux-riscv, devicetree, Daniel Lezcano, Thomas Gleixner,
Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Xingyu Wu, Samin Guo, linux-kernel, Conor Dooley
Add the timer node for the Starfive JH7110 SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index d484ecdf93f7..fbd0a510ca1b 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -478,6 +478,26 @@ sysgpio: pinctrl@13040000 {
#gpio-cells = <2>;
};
+ timer@13050000 {
+ compatible = "starfive,jh7110-timer";
+ reg = <0x0 0x13050000 0x0 0x10000>;
+ interrupts = <69>, <70>, <71> ,<72>;
+ clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
+ <&syscrg JH7110_SYSCLK_TIMER0>,
+ <&syscrg JH7110_SYSCLK_TIMER1>,
+ <&syscrg JH7110_SYSCLK_TIMER2>,
+ <&syscrg JH7110_SYSCLK_TIMER3>;
+ clock-names = "apb", "ch0", "ch1",
+ "ch2", "ch3";
+ resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
+ <&syscrg JH7110_SYSRST_TIMER0>,
+ <&syscrg JH7110_SYSRST_TIMER1>,
+ <&syscrg JH7110_SYSRST_TIMER2>,
+ <&syscrg JH7110_SYSRST_TIMER3>;
+ reset-names = "apb", "ch0", "ch1",
+ "ch2", "ch3";
+ };
+
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 3/3] riscv: dts: jh7110: starfive: Add timer node
@ 2023-03-20 13:54 ` Xingyu Wu
0 siblings, 0 replies; 20+ messages in thread
From: Xingyu Wu @ 2023-03-20 13:54 UTC (permalink / raw)
To: linux-riscv, devicetree, Daniel Lezcano, Thomas Gleixner,
Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Xingyu Wu, Samin Guo, linux-kernel, Conor Dooley
Add the timer node for the Starfive JH7110 SoC.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index d484ecdf93f7..fbd0a510ca1b 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -478,6 +478,26 @@ sysgpio: pinctrl@13040000 {
#gpio-cells = <2>;
};
+ timer@13050000 {
+ compatible = "starfive,jh7110-timer";
+ reg = <0x0 0x13050000 0x0 0x10000>;
+ interrupts = <69>, <70>, <71> ,<72>;
+ clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
+ <&syscrg JH7110_SYSCLK_TIMER0>,
+ <&syscrg JH7110_SYSCLK_TIMER1>,
+ <&syscrg JH7110_SYSCLK_TIMER2>,
+ <&syscrg JH7110_SYSCLK_TIMER3>;
+ clock-names = "apb", "ch0", "ch1",
+ "ch2", "ch3";
+ resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
+ <&syscrg JH7110_SYSRST_TIMER0>,
+ <&syscrg JH7110_SYSRST_TIMER1>,
+ <&syscrg JH7110_SYSRST_TIMER2>,
+ <&syscrg JH7110_SYSRST_TIMER3>;
+ reset-names = "apb", "ch0", "ch1",
+ "ch2", "ch3";
+ };
+
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;
--
2.25.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: timer: Add timer for StarFive JH7110 SoC
2023-03-20 13:54 ` Xingyu Wu
@ 2023-03-21 7:12 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-21 7:12 UTC (permalink / raw)
To: Xingyu Wu, linux-riscv, devicetree, Daniel Lezcano,
Thomas Gleixner, Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Samin Guo, linux-kernel, Conor Dooley
On 20/03/2023 14:54, Xingyu Wu wrote:
> Add bindings for the timer on the JH7110 RISC-V SoC
> by StarFive Technology Ltd.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: timer: Add timer for StarFive JH7110 SoC
@ 2023-03-21 7:12 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-21 7:12 UTC (permalink / raw)
To: Xingyu Wu, linux-riscv, devicetree, Daniel Lezcano,
Thomas Gleixner, Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Samin Guo, linux-kernel, Conor Dooley
On 20/03/2023 14:54, Xingyu Wu wrote:
> Add bindings for the timer on the JH7110 RISC-V SoC
> by StarFive Technology Ltd.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: timer: Add timer for StarFive JH7110 SoC
2023-03-20 13:54 ` Xingyu Wu
@ 2023-03-21 7:14 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-21 7:14 UTC (permalink / raw)
To: Xingyu Wu, linux-riscv, devicetree, Daniel Lezcano,
Thomas Gleixner, Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Samin Guo, linux-kernel, Conor Dooley
On 20/03/2023 14:54, Xingyu Wu wrote:
> Add bindings for the timer on the JH7110 RISC-V SoC
> by StarFive Technology Ltd.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
> .../bindings/timer/starfive,jh7110-timer.yaml | 95 +++++++++++++++++++
> 1 file changed, 95 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
> new file mode 100644
> index 000000000000..24b34618f2c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
> @@ -0,0 +1,95 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/starfive,jh7110-timer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Timer
Actually one change is needed - missing blank line.
> +maintainers:
> + - Xingyu Wu <xingyu.wu@starfivetech.com>
> + - Samin Guo <samin.guo@starfivetech.com>
> +
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: timer: Add timer for StarFive JH7110 SoC
@ 2023-03-21 7:14 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-21 7:14 UTC (permalink / raw)
To: Xingyu Wu, linux-riscv, devicetree, Daniel Lezcano,
Thomas Gleixner, Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Samin Guo, linux-kernel, Conor Dooley
On 20/03/2023 14:54, Xingyu Wu wrote:
> Add bindings for the timer on the JH7110 RISC-V SoC
> by StarFive Technology Ltd.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
> .../bindings/timer/starfive,jh7110-timer.yaml | 95 +++++++++++++++++++
> 1 file changed, 95 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
> new file mode 100644
> index 000000000000..24b34618f2c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
> @@ -0,0 +1,95 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/starfive,jh7110-timer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Timer
Actually one change is needed - missing blank line.
> +maintainers:
> + - Xingyu Wu <xingyu.wu@starfivetech.com>
> + - Samin Guo <samin.guo@starfivetech.com>
> +
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: timer: Add timer for StarFive JH7110 SoC
2023-03-21 7:14 ` Krzysztof Kozlowski
@ 2023-03-21 7:17 ` Xingyu Wu
-1 siblings, 0 replies; 20+ messages in thread
From: Xingyu Wu @ 2023-03-21 7:17 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-riscv, devicetree, Daniel Lezcano,
Thomas Gleixner, Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Samin Guo, linux-kernel, Conor Dooley
On 2023/3/21 15:14, Krzysztof Kozlowski wrote:
> On 20/03/2023 14:54, Xingyu Wu wrote:
>> Add bindings for the timer on the JH7110 RISC-V SoC
>> by StarFive Technology Ltd.
>>
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> ---
>> .../bindings/timer/starfive,jh7110-timer.yaml | 95 +++++++++++++++++++
>> 1 file changed, 95 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
>> new file mode 100644
>> index 000000000000..24b34618f2c8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
>> @@ -0,0 +1,95 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/timer/starfive,jh7110-timer.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 Timer
>
> Actually one change is needed - missing blank line.
>
Will fix. Thanks.
Best regards,
Xingyu Wu
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: timer: Add timer for StarFive JH7110 SoC
@ 2023-03-21 7:17 ` Xingyu Wu
0 siblings, 0 replies; 20+ messages in thread
From: Xingyu Wu @ 2023-03-21 7:17 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-riscv, devicetree, Daniel Lezcano,
Thomas Gleixner, Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Philipp Zabel, Samin Guo, linux-kernel, Conor Dooley
On 2023/3/21 15:14, Krzysztof Kozlowski wrote:
> On 20/03/2023 14:54, Xingyu Wu wrote:
>> Add bindings for the timer on the JH7110 RISC-V SoC
>> by StarFive Technology Ltd.
>>
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> ---
>> .../bindings/timer/starfive,jh7110-timer.yaml | 95 +++++++++++++++++++
>> 1 file changed, 95 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
>> new file mode 100644
>> index 000000000000..24b34618f2c8
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml
>> @@ -0,0 +1,95 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/timer/starfive,jh7110-timer.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 Timer
>
> Actually one change is needed - missing blank line.
>
Will fix. Thanks.
Best regards,
Xingyu Wu
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/3] clocksource: Add StarFive timer driver
2023-03-20 13:54 ` Xingyu Wu
@ 2023-06-02 9:45 ` Xingyu Wu
-1 siblings, 0 replies; 20+ messages in thread
From: Xingyu Wu @ 2023-06-02 9:45 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner
Cc: devicetree, linux-riscv, Krzysztof Kozlowski, Rob Herring,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Philipp Zabel,
Samin Guo, linux-kernel, Conor Dooley
On 2023/3/20 21:54, Xingyu Wu wrote:
> Add timer driver for the StarFive JH7110 SoC.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
> MAINTAINERS | 7 +
> drivers/clocksource/Kconfig | 12 +
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/timer-starfive.c | 390 +++++++++++++++++++++++++++
> drivers/clocksource/timer-starfive.h | 96 +++++++
> 5 files changed, 506 insertions(+)
> create mode 100644 drivers/clocksource/timer-starfive.c
> create mode 100644 drivers/clocksource/timer-starfive.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 958b7ec118b4..dac6298d8f6e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19958,6 +19958,13 @@ S: Maintained
> T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
> F: drivers/soc/starfive/
>
> +STARFIVE TIMER DRIVER
> +M: Samin Guo <samin.guo@starfivetech.com>
> +M: Xingyu Wu <xingyu.wu@starfivetech.com>
> +S: Supported
> +F: Documentation/devicetree/bindings/timer/starfive*
> +F: drivers/clocksource/timer-starfive*
> +
> STARFIVE TRNG DRIVER
> M: Jia Jie Ho <jiajie.ho@starfivetech.com>
> S: Supported
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 5fc8f0e7fb38..35daf07d4db7 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -630,6 +630,18 @@ config RISCV_TIMER
> is accessed via both the SBI and the rdcycle instruction. This is
> required for all RISC-V systems.
>
> +config STARFIVE_TIMER
> + bool "Timer for the STARFIVE SoCs"
> + depends on ARCH_STARFIVE || COMPILE_TEST
> + select TIMER_OF
> + select CLKSRC_MMIO
> + default ARCH_STARFIVE
> + help
> + This enables the timer for StarFive SoCs. On RISC-V platform,
> + the system has started RISCV_TIMER. But you can also use this timer
> + to do a lot more on StarFive SoCs. This timer can provide high
> + precision and four channels to use in JH7110 SoC.
> +
> config CLINT_TIMER
> bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
> depends on GENERIC_SCHED_CLOCK && RISCV
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 64ab547de97b..276695d95cdc 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -80,6 +80,7 @@ obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o
> obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
> obj-$(CONFIG_X86_NUMACHIP) += numachip.o
> obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o
> +obj-$(CONFIG_STARFIVE_TIMER) += timer-starfive.o
> obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
> obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
> obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
> diff --git a/drivers/clocksource/timer-starfive.c b/drivers/clocksource/timer-starfive.c
> new file mode 100644
> index 000000000000..53163948ed86
> --- /dev/null
> +++ b/drivers/clocksource/timer-starfive.c
> @@ -0,0 +1,390 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Starfive Timer driver
> + *
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + *
> + * Author:
> + * Xingyu Wu <xingyu.wu@starfivetech.com>
> + * Samin Guo <samin.guo@starfivetech.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clockchips.h>
> +#include <linux/clocksource.h>
> +#include <linux/err.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/irq.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include <linux/sched_clock.h>
> +
> +#include "timer-starfive.h"
> +
> +static const struct starfive_timer_chan_base starfive_timer_jh7110_base = {
> + .ctrl = STARFIVE_TIMER_JH7110_CTL,
> + .load = STARFIVE_TIMER_JH7110_LOAD,
> + .enable = STARFIVE_TIMER_JH7110_ENABLE,
> + .reload = STARFIVE_TIMER_JH7110_RELOAD,
> + .value = STARFIVE_TIMER_JH7110_VALUE,
> + .intclr = STARFIVE_TIMER_JH7110_INT_CLR,
> + .intmask = STARFIVE_TIMER_JH7110_INT_MASK,
> + .channel_num = STARFIVE_TIMER_CH_4,
> + .channel_base = {STARFIVE_TIMER_CH_BASE(0), STARFIVE_TIMER_CH_BASE(1),
> + STARFIVE_TIMER_CH_BASE(2), STARFIVE_TIMER_CH_BASE(3)},
> +};
> +
> +static inline struct starfive_clkevt *to_starfive_clkevt(struct clock_event_device *evt)
> +{
> + return container_of(evt, struct starfive_clkevt, evt);
> +}
> +
> +/* 0:continuous-run mode, 1:single-run mode */
> +static inline void starfive_timer_set_mod(struct starfive_clkevt *clkevt, int mod)
> +{
> + writel(mod, clkevt->ctrl);
> +}
> +
> +/* Interrupt Mask Register, 0:Unmask, 1:Mask */
> +static inline void starfive_timer_int_enable(struct starfive_clkevt *clkevt)
> +{
> + writel(STARFIVE_TIMER_INTMASK_DIS, clkevt->intmask);
> +}
> +
> +static inline void starfive_timer_int_disable(struct starfive_clkevt *clkevt)
> +{
> + writel(STARFIVE_TIMER_INTMASK_ENA, clkevt->intmask);
> +}
> +
> +/*
> + * BIT(0): Read value represent channel intr status.
> + * Write 1 to this bit to clear interrupt. Write 0 has no effects.
> + * BIT(1): "1" means that it is clearing interrupt. BIT(0) can not be written.
> + */
> +static inline int starfive_timer_int_clear(struct starfive_clkevt *clkevt)
> +{
> + u32 value;
> + int ret;
> +
> + /* waiting interrupt can be to clearing */
> + ret = readl_poll_timeout_atomic(clkevt->intclr, value,
> + !(value & STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK),
> + STARFIVE_DELAY_US, STARFIVE_TIMEOUT_US);
> + if (!ret)
> + writel(0x1, clkevt->intclr);
> +
> + return ret;
> +}
> +
> +/*
> + * The initial value to be loaded into the
> + * counter and is also used as the reload value.
> + * val = clock rate --> 1s
> + */
> +static inline void starfive_timer_set_load(struct starfive_clkevt *clkevt, u32 val)
> +{
> + writel(val, clkevt->load);
> +}
> +
> +static inline u32 starfive_timer_get_val(struct starfive_clkevt *clkevt)
> +{
> + return readl(clkevt->value);
> +}
> +
> +/*
> + * Write RELOAD register to reload preset value to counter.
> + * (Write 0 and write 1 are both ok)
> + */
> +static inline void starfive_timer_set_reload(struct starfive_clkevt *clkevt)
> +{
> + writel(0, clkevt->reload);
> +}
> +
> +static inline void starfive_timer_enable(struct starfive_clkevt *clkevt)
> +{
> + writel(STARFIVE_TIMER_ENA, clkevt->enable);
> +}
> +
> +static inline void starfive_timer_disable(struct starfive_clkevt *clkevt)
> +{
> + writel(STARFIVE_TIMER_DIS, clkevt->enable);
> +}
> +
> +static int starfive_timer_int_init_enable(struct starfive_clkevt *clkevt)
> +{
> + int ret;
> +
> + starfive_timer_int_disable(clkevt);
> + ret = starfive_timer_int_clear(clkevt);
> + if (ret)
> + return ret;
> +
> + starfive_timer_int_enable(clkevt);
> + starfive_timer_enable(clkevt);
> +
> + return 0;
> +}
> +
> +static int starfive_timer_shutdown(struct clock_event_device *evt)
> +{
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + starfive_timer_disable(clkevt);
> + return starfive_timer_int_clear(clkevt);
> +}
> +
> +static void starfive_timer_suspend(struct clock_event_device *evt)
> +{
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + clkevt->reload_val = starfive_timer_get_val(clkevt);
> + starfive_timer_shutdown(evt);
> +}
> +
> +static void starfive_timer_resume(struct clock_event_device *evt)
> +{
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + starfive_timer_set_load(clkevt, clkevt->reload_val);
> + starfive_timer_set_reload(clkevt);
> + starfive_timer_int_enable(clkevt);
> + starfive_timer_enable(clkevt);
> +}
> +
> +static int starfive_timer_tick_resume(struct clock_event_device *evt)
> +{
> + starfive_timer_resume(evt);
> +
> + return 0;
> +}
> +
> +static int starfive_clocksource_init(struct starfive_clkevt *clkevt)
> +{
> + int ret;
> +
> + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
> + starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
> + ret = starfive_timer_int_init_enable(clkevt);
> + if (ret)
> + return ret;
> +
> + return clocksource_mmio_init(clkevt->value, clkevt->name, clkevt->rate,
> + STARFIVE_CLOCK_SOURCE_RATING, STARFIVE_VALID_BITS,
> + clocksource_mmio_readl_down);
> +}
> +
> +/* IRQ handler for the timer */
> +static irqreturn_t starfive_timer_interrupt(int irq, void *priv)
> +{
> + struct clock_event_device *evt = (struct clock_event_device *)priv;
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + if (starfive_timer_int_clear(clkevt))
> + return IRQ_NONE;
> +
> + if (evt->event_handler)
> + evt->event_handler(evt);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int starfive_timer_set_periodic(struct clock_event_device *evt)
> +{
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + starfive_timer_disable(clkevt);
> + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
> + starfive_timer_set_load(clkevt, clkevt->periodic);
> +
> + return starfive_timer_int_init_enable(clkevt);
> +}
> +
> +static int starfive_timer_set_oneshot(struct clock_event_device *evt)
> +{
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + starfive_timer_disable(clkevt);
> + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
> + starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
> +
> + return starfive_timer_int_init_enable(clkevt);
> +}
> +
> +static int starfive_timer_set_next_event(unsigned long next,
> + struct clock_event_device *evt)
> +{
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + starfive_timer_disable(clkevt);
> + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
> + starfive_timer_set_load(clkevt, next);
> + starfive_timer_enable(clkevt);
> +
> + return 0;
> +}
> +
> +static void starfive_set_clockevent(struct clock_event_device *evt)
> +{
> + evt->features = CLOCK_EVT_FEAT_PERIODIC |
> + CLOCK_EVT_FEAT_ONESHOT |
> + CLOCK_EVT_FEAT_DYNIRQ;
> + evt->set_state_shutdown = starfive_timer_shutdown;
> + evt->set_state_periodic = starfive_timer_set_periodic;
> + evt->set_state_oneshot = starfive_timer_set_oneshot;
> + evt->set_state_oneshot_stopped = starfive_timer_shutdown;
> + evt->tick_resume = starfive_timer_tick_resume;
> + evt->set_next_event = starfive_timer_set_next_event;
> + evt->suspend = starfive_timer_suspend;
> + evt->resume = starfive_timer_resume;
> + evt->rating = STARFIVE_CLOCKEVENT_RATING;
> +}
> +
> +static void starfive_clockevents_register(struct starfive_clkevt *clkevt)
> +{
> + clkevt->rate = clk_get_rate(clkevt->clk);
> + clkevt->periodic = DIV_ROUND_CLOSEST(clkevt->rate, HZ);
> +
> + starfive_set_clockevent(&clkevt->evt);
> + clkevt->evt.name = clkevt->name;
> + clkevt->evt.irq = clkevt->irq;
> + clkevt->evt.cpumask = cpu_possible_mask;
> +
> + clockevents_config_and_register(&clkevt->evt, clkevt->rate,
> + STARFIVE_TIMER_MIN_TICKS, STARFIVE_TIMER_MAX_TICKS);
> +}
> +
> +static void __init starfive_clkevt_base_init(const struct starfive_timer_chan_base *timer,
> + struct starfive_clkevt *clkevt,
> + void __iomem *base, int ch)
> +{
> + void __iomem *channel_base;
> +
> + channel_base = base + timer->channel_base[ch];
> + clkevt->base = channel_base;
> + clkevt->ctrl = channel_base + timer->ctrl;
> + clkevt->load = channel_base + timer->load;
> + clkevt->enable = channel_base + timer->enable;
> + clkevt->reload = channel_base + timer->reload;
> + clkevt->value = channel_base + timer->value;
> + clkevt->intclr = channel_base + timer->intclr;
> + clkevt->intmask = channel_base + timer->intmask;
> +}
> +
> +static int __init starfive_timer_probe(struct platform_device *pdev)
> +{
> + const struct starfive_timer_chan_base *timer_base = of_device_get_match_data(&pdev->dev);
> + char name[10];
> + struct starfive_timer_priv *priv;
> + struct starfive_clkevt *clkevt;
> + struct clk *pclk;
> + struct reset_control *rst;
> + int ch;
> + int ret;
> +
> + priv = devm_kzalloc(&pdev->dev, struct_size(priv, clkevt, timer_base->channel_num),
> + GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(priv->base))
> + return dev_err_probe(&pdev->dev, PTR_ERR(priv->base),
> + "failed to map registers\n");
> +
> + rst = devm_reset_control_get_exclusive(&pdev->dev, "apb");
> + if (IS_ERR(rst))
> + return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get apb reset\n");
> +
> + pclk = devm_clk_get_enabled(&pdev->dev, "apb");
> + if (IS_ERR(pclk))
> + return dev_err_probe(&pdev->dev, PTR_ERR(pclk),
> + "failed to get & enable apb clock\n");
> +
> + ret = reset_control_deassert(rst);
> + if (ret)
> + goto err;
> +
> + priv->dev = &pdev->dev;
> + platform_set_drvdata(pdev, priv);
> +
> + for (ch = 0; ch < timer_base->channel_num; ch++) {
> + clkevt = &priv->clkevt[ch];
> + snprintf(name, sizeof(name), "ch%d", ch);
> +
> + starfive_clkevt_base_init(timer_base, clkevt, priv->base, ch);
> + /* Ensure timers are disabled */
> + starfive_timer_disable(clkevt);
> +
> + rst = devm_reset_control_get_exclusive(&pdev->dev, name);
> + if (IS_ERR(rst)) {
> + ret = PTR_ERR(rst);
> + goto err;
> + }
> +
> + clkevt->clk = devm_clk_get_enabled(&pdev->dev, name);
> + if (IS_ERR(clkevt->clk)) {
> + ret = PTR_ERR(clkevt->clk);
> + goto err;
> + }
> +
> + ret = reset_control_deassert(rst);
> + if (ret)
> + goto ch_err;
> +
> + clkevt->irq = platform_get_irq(pdev, ch);
> + if (clkevt->irq < 0) {
> + ret = clkevt->irq;
> + goto ch_err;
> + }
> +
> + snprintf(clkevt->name, sizeof(clkevt->name), "%s.ch%d", pdev->name, ch);
> + starfive_clockevents_register(clkevt);
> +
> + ret = devm_request_irq(&pdev->dev, clkevt->irq, starfive_timer_interrupt,
> + IRQF_TIMER | IRQF_IRQPOLL,
> + clkevt->name, &clkevt->evt);
> + if (ret)
> + goto ch_err;
> +
> + ret = starfive_clocksource_init(clkevt);
> + if (ret)
> + goto ch_err;
> + }
> +
> + return 0;
> +
> +ch_err:
> + /* Only unregister the failed channel and the rest timer channels continue to work. */
> + clk_disable_unprepare(clkevt->clk);
> +err:
> + /* If no other channel successfully registers, pclk should be disabled. */
> + if (!ch)
> + clk_disable_unprepare(pclk);
> +
> + return ret;
> +}
> +
> +static const struct of_device_id starfive_timer_match[] = {
> + { .compatible = "starfive,jh7110-timer", .data = &starfive_timer_jh7110_base },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, starfive_timer_match);
> +
> +static struct platform_driver starfive_timer_driver = {
> + .probe = starfive_timer_probe,
> + .driver = {
> + .name = "starfive-timer",
> + .of_match_table = starfive_timer_match,
> + },
> +};
> +module_platform_driver(starfive_timer_driver);
> +
> +MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
> +MODULE_DESCRIPTION("StarFive timer driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clocksource/timer-starfive.h b/drivers/clocksource/timer-starfive.h
> new file mode 100644
> index 000000000000..62eb630cc98d
> --- /dev/null
> +++ b/drivers/clocksource/timer-starfive.h
> @@ -0,0 +1,96 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +#ifndef __STARFIVE_TIMER_H__
> +#define __STARFIVE_TIMER_H__
> +
> +/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */
> +#define STARFIVE_TIMER_CH_LEN 0x40
> +#define STARFIVE_TIMER_CH_BASE(x) ((STARFIVE_TIMER_CH_##x) * STARFIVE_TIMER_CH_LEN)
> +
> +#define STARFIVE_CLOCK_SOURCE_RATING 200
> +#define STARFIVE_VALID_BITS 32
> +#define STARFIVE_DELAY_US 0
> +#define STARFIVE_TIMEOUT_US 10000
> +#define STARFIVE_CLOCKEVENT_RATING 300
> +#define STARFIVE_TIMER_MAX_TICKS 0xffffffff
> +#define STARFIVE_TIMER_MIN_TICKS 0xf
> +
> +#define STARFIVE_TIMER_JH7110_INT_STATUS 0x00 /* RO[0:4]: Interrupt Status for channel0~4 */
> +#define STARFIVE_TIMER_JH7110_CTL 0x04 /* RW[0]: 0-continuous run, 1-single run */
> +#define STARFIVE_TIMER_JH7110_LOAD 0x08 /* RW: load value to counter */
> +#define STARFIVE_TIMER_JH7110_ENABLE 0x10 /* RW[0]: timer enable register */
> +#define STARFIVE_TIMER_JH7110_RELOAD 0x14 /* RW: write 1 or 0 both reload counter */
> +#define STARFIVE_TIMER_JH7110_VALUE 0x18 /* RO: timer value register */
> +#define STARFIVE_TIMER_JH7110_INT_CLR 0x20 /* RW: timer interrupt clear register */
> +#define STARFIVE_TIMER_JH7110_INT_MASK 0x24 /* RW[0]: timer interrupt mask register */
> +#define STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK BIT(1)
> +
> +enum STARFIVE_TIMER_CH {
> + STARFIVE_TIMER_CH_0 = 0,
> + STARFIVE_TIMER_CH_1,
> + STARFIVE_TIMER_CH_2,
> + STARFIVE_TIMER_CH_3,
> + STARFIVE_TIMER_CH_4,
> + STARFIVE_TIMER_CH_5,
> + STARFIVE_TIMER_CH_6,
> + STARFIVE_TIMER_CH_7,
> + STARFIVE_TIMER_CH_MAX
> +};
> +
> +enum STARFIVE_TIMER_INTMASK {
> + STARFIVE_TIMER_INTMASK_DIS = 0,
> + STARFIVE_TIMER_INTMASK_ENA = 1
> +};
> +
> +enum STARFIVE_TIMER_MOD {
> + STARFIVE_TIMER_MOD_CONTIN = 0,
> + STARFIVE_TIMER_MOD_SINGLE = 1
> +};
> +
> +enum STARFIVE_TIMER_CTL_EN {
> + STARFIVE_TIMER_DIS = 0,
> + STARFIVE_TIMER_ENA = 1
> +};
> +
> +struct starfive_timer_chan_base {
> + /* Resgister */
> + unsigned int ctrl;
> + unsigned int load;
> + unsigned int enable;
> + unsigned int reload;
> + unsigned int value;
> + unsigned int intclr;
> + unsigned int intmask;
> +
> + unsigned int channel_num; /* timer channel numbers */
> + unsigned int channel_base[];
> +};
> +
> +struct starfive_clkevt {
> + struct clock_event_device evt;
> + struct clk *clk;
> + char name[20];
> + int irq;
> + u32 periodic;
> + u32 rate;
> + u32 reload_val;
> + void __iomem *base;
> + void __iomem *ctrl;
> + void __iomem *load;
> + void __iomem *enable;
> + void __iomem *reload;
> + void __iomem *value;
> + void __iomem *intclr;
> + void __iomem *intmask;
> +};
> +
> +struct starfive_timer_priv {
> + struct device *dev;
> + void __iomem *base;
> + struct starfive_clkevt clkevt[];
> +};
> +
> +#endif /* __STARFIVE_TIMER_H__ */
Hi Daniel and Thomas,
I have submitted patches for Timer driver. Could you please help to review and give your comments?
Thanks.
Best regards,
Xingyu Wu
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/3] clocksource: Add StarFive timer driver
@ 2023-06-02 9:45 ` Xingyu Wu
0 siblings, 0 replies; 20+ messages in thread
From: Xingyu Wu @ 2023-06-02 9:45 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner
Cc: devicetree, linux-riscv, Krzysztof Kozlowski, Rob Herring,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Philipp Zabel,
Samin Guo, linux-kernel, Conor Dooley
On 2023/3/20 21:54, Xingyu Wu wrote:
> Add timer driver for the StarFive JH7110 SoC.
>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
> MAINTAINERS | 7 +
> drivers/clocksource/Kconfig | 12 +
> drivers/clocksource/Makefile | 1 +
> drivers/clocksource/timer-starfive.c | 390 +++++++++++++++++++++++++++
> drivers/clocksource/timer-starfive.h | 96 +++++++
> 5 files changed, 506 insertions(+)
> create mode 100644 drivers/clocksource/timer-starfive.c
> create mode 100644 drivers/clocksource/timer-starfive.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 958b7ec118b4..dac6298d8f6e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19958,6 +19958,13 @@ S: Maintained
> T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
> F: drivers/soc/starfive/
>
> +STARFIVE TIMER DRIVER
> +M: Samin Guo <samin.guo@starfivetech.com>
> +M: Xingyu Wu <xingyu.wu@starfivetech.com>
> +S: Supported
> +F: Documentation/devicetree/bindings/timer/starfive*
> +F: drivers/clocksource/timer-starfive*
> +
> STARFIVE TRNG DRIVER
> M: Jia Jie Ho <jiajie.ho@starfivetech.com>
> S: Supported
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 5fc8f0e7fb38..35daf07d4db7 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -630,6 +630,18 @@ config RISCV_TIMER
> is accessed via both the SBI and the rdcycle instruction. This is
> required for all RISC-V systems.
>
> +config STARFIVE_TIMER
> + bool "Timer for the STARFIVE SoCs"
> + depends on ARCH_STARFIVE || COMPILE_TEST
> + select TIMER_OF
> + select CLKSRC_MMIO
> + default ARCH_STARFIVE
> + help
> + This enables the timer for StarFive SoCs. On RISC-V platform,
> + the system has started RISCV_TIMER. But you can also use this timer
> + to do a lot more on StarFive SoCs. This timer can provide high
> + precision and four channels to use in JH7110 SoC.
> +
> config CLINT_TIMER
> bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
> depends on GENERIC_SCHED_CLOCK && RISCV
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 64ab547de97b..276695d95cdc 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -80,6 +80,7 @@ obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o
> obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
> obj-$(CONFIG_X86_NUMACHIP) += numachip.o
> obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o
> +obj-$(CONFIG_STARFIVE_TIMER) += timer-starfive.o
> obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
> obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
> obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
> diff --git a/drivers/clocksource/timer-starfive.c b/drivers/clocksource/timer-starfive.c
> new file mode 100644
> index 000000000000..53163948ed86
> --- /dev/null
> +++ b/drivers/clocksource/timer-starfive.c
> @@ -0,0 +1,390 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Starfive Timer driver
> + *
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + *
> + * Author:
> + * Xingyu Wu <xingyu.wu@starfivetech.com>
> + * Samin Guo <samin.guo@starfivetech.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clockchips.h>
> +#include <linux/clocksource.h>
> +#include <linux/err.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/irq.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +#include <linux/sched_clock.h>
> +
> +#include "timer-starfive.h"
> +
> +static const struct starfive_timer_chan_base starfive_timer_jh7110_base = {
> + .ctrl = STARFIVE_TIMER_JH7110_CTL,
> + .load = STARFIVE_TIMER_JH7110_LOAD,
> + .enable = STARFIVE_TIMER_JH7110_ENABLE,
> + .reload = STARFIVE_TIMER_JH7110_RELOAD,
> + .value = STARFIVE_TIMER_JH7110_VALUE,
> + .intclr = STARFIVE_TIMER_JH7110_INT_CLR,
> + .intmask = STARFIVE_TIMER_JH7110_INT_MASK,
> + .channel_num = STARFIVE_TIMER_CH_4,
> + .channel_base = {STARFIVE_TIMER_CH_BASE(0), STARFIVE_TIMER_CH_BASE(1),
> + STARFIVE_TIMER_CH_BASE(2), STARFIVE_TIMER_CH_BASE(3)},
> +};
> +
> +static inline struct starfive_clkevt *to_starfive_clkevt(struct clock_event_device *evt)
> +{
> + return container_of(evt, struct starfive_clkevt, evt);
> +}
> +
> +/* 0:continuous-run mode, 1:single-run mode */
> +static inline void starfive_timer_set_mod(struct starfive_clkevt *clkevt, int mod)
> +{
> + writel(mod, clkevt->ctrl);
> +}
> +
> +/* Interrupt Mask Register, 0:Unmask, 1:Mask */
> +static inline void starfive_timer_int_enable(struct starfive_clkevt *clkevt)
> +{
> + writel(STARFIVE_TIMER_INTMASK_DIS, clkevt->intmask);
> +}
> +
> +static inline void starfive_timer_int_disable(struct starfive_clkevt *clkevt)
> +{
> + writel(STARFIVE_TIMER_INTMASK_ENA, clkevt->intmask);
> +}
> +
> +/*
> + * BIT(0): Read value represent channel intr status.
> + * Write 1 to this bit to clear interrupt. Write 0 has no effects.
> + * BIT(1): "1" means that it is clearing interrupt. BIT(0) can not be written.
> + */
> +static inline int starfive_timer_int_clear(struct starfive_clkevt *clkevt)
> +{
> + u32 value;
> + int ret;
> +
> + /* waiting interrupt can be to clearing */
> + ret = readl_poll_timeout_atomic(clkevt->intclr, value,
> + !(value & STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK),
> + STARFIVE_DELAY_US, STARFIVE_TIMEOUT_US);
> + if (!ret)
> + writel(0x1, clkevt->intclr);
> +
> + return ret;
> +}
> +
> +/*
> + * The initial value to be loaded into the
> + * counter and is also used as the reload value.
> + * val = clock rate --> 1s
> + */
> +static inline void starfive_timer_set_load(struct starfive_clkevt *clkevt, u32 val)
> +{
> + writel(val, clkevt->load);
> +}
> +
> +static inline u32 starfive_timer_get_val(struct starfive_clkevt *clkevt)
> +{
> + return readl(clkevt->value);
> +}
> +
> +/*
> + * Write RELOAD register to reload preset value to counter.
> + * (Write 0 and write 1 are both ok)
> + */
> +static inline void starfive_timer_set_reload(struct starfive_clkevt *clkevt)
> +{
> + writel(0, clkevt->reload);
> +}
> +
> +static inline void starfive_timer_enable(struct starfive_clkevt *clkevt)
> +{
> + writel(STARFIVE_TIMER_ENA, clkevt->enable);
> +}
> +
> +static inline void starfive_timer_disable(struct starfive_clkevt *clkevt)
> +{
> + writel(STARFIVE_TIMER_DIS, clkevt->enable);
> +}
> +
> +static int starfive_timer_int_init_enable(struct starfive_clkevt *clkevt)
> +{
> + int ret;
> +
> + starfive_timer_int_disable(clkevt);
> + ret = starfive_timer_int_clear(clkevt);
> + if (ret)
> + return ret;
> +
> + starfive_timer_int_enable(clkevt);
> + starfive_timer_enable(clkevt);
> +
> + return 0;
> +}
> +
> +static int starfive_timer_shutdown(struct clock_event_device *evt)
> +{
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + starfive_timer_disable(clkevt);
> + return starfive_timer_int_clear(clkevt);
> +}
> +
> +static void starfive_timer_suspend(struct clock_event_device *evt)
> +{
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + clkevt->reload_val = starfive_timer_get_val(clkevt);
> + starfive_timer_shutdown(evt);
> +}
> +
> +static void starfive_timer_resume(struct clock_event_device *evt)
> +{
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + starfive_timer_set_load(clkevt, clkevt->reload_val);
> + starfive_timer_set_reload(clkevt);
> + starfive_timer_int_enable(clkevt);
> + starfive_timer_enable(clkevt);
> +}
> +
> +static int starfive_timer_tick_resume(struct clock_event_device *evt)
> +{
> + starfive_timer_resume(evt);
> +
> + return 0;
> +}
> +
> +static int starfive_clocksource_init(struct starfive_clkevt *clkevt)
> +{
> + int ret;
> +
> + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
> + starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
> + ret = starfive_timer_int_init_enable(clkevt);
> + if (ret)
> + return ret;
> +
> + return clocksource_mmio_init(clkevt->value, clkevt->name, clkevt->rate,
> + STARFIVE_CLOCK_SOURCE_RATING, STARFIVE_VALID_BITS,
> + clocksource_mmio_readl_down);
> +}
> +
> +/* IRQ handler for the timer */
> +static irqreturn_t starfive_timer_interrupt(int irq, void *priv)
> +{
> + struct clock_event_device *evt = (struct clock_event_device *)priv;
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + if (starfive_timer_int_clear(clkevt))
> + return IRQ_NONE;
> +
> + if (evt->event_handler)
> + evt->event_handler(evt);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int starfive_timer_set_periodic(struct clock_event_device *evt)
> +{
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + starfive_timer_disable(clkevt);
> + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
> + starfive_timer_set_load(clkevt, clkevt->periodic);
> +
> + return starfive_timer_int_init_enable(clkevt);
> +}
> +
> +static int starfive_timer_set_oneshot(struct clock_event_device *evt)
> +{
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + starfive_timer_disable(clkevt);
> + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
> + starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
> +
> + return starfive_timer_int_init_enable(clkevt);
> +}
> +
> +static int starfive_timer_set_next_event(unsigned long next,
> + struct clock_event_device *evt)
> +{
> + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> +
> + starfive_timer_disable(clkevt);
> + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
> + starfive_timer_set_load(clkevt, next);
> + starfive_timer_enable(clkevt);
> +
> + return 0;
> +}
> +
> +static void starfive_set_clockevent(struct clock_event_device *evt)
> +{
> + evt->features = CLOCK_EVT_FEAT_PERIODIC |
> + CLOCK_EVT_FEAT_ONESHOT |
> + CLOCK_EVT_FEAT_DYNIRQ;
> + evt->set_state_shutdown = starfive_timer_shutdown;
> + evt->set_state_periodic = starfive_timer_set_periodic;
> + evt->set_state_oneshot = starfive_timer_set_oneshot;
> + evt->set_state_oneshot_stopped = starfive_timer_shutdown;
> + evt->tick_resume = starfive_timer_tick_resume;
> + evt->set_next_event = starfive_timer_set_next_event;
> + evt->suspend = starfive_timer_suspend;
> + evt->resume = starfive_timer_resume;
> + evt->rating = STARFIVE_CLOCKEVENT_RATING;
> +}
> +
> +static void starfive_clockevents_register(struct starfive_clkevt *clkevt)
> +{
> + clkevt->rate = clk_get_rate(clkevt->clk);
> + clkevt->periodic = DIV_ROUND_CLOSEST(clkevt->rate, HZ);
> +
> + starfive_set_clockevent(&clkevt->evt);
> + clkevt->evt.name = clkevt->name;
> + clkevt->evt.irq = clkevt->irq;
> + clkevt->evt.cpumask = cpu_possible_mask;
> +
> + clockevents_config_and_register(&clkevt->evt, clkevt->rate,
> + STARFIVE_TIMER_MIN_TICKS, STARFIVE_TIMER_MAX_TICKS);
> +}
> +
> +static void __init starfive_clkevt_base_init(const struct starfive_timer_chan_base *timer,
> + struct starfive_clkevt *clkevt,
> + void __iomem *base, int ch)
> +{
> + void __iomem *channel_base;
> +
> + channel_base = base + timer->channel_base[ch];
> + clkevt->base = channel_base;
> + clkevt->ctrl = channel_base + timer->ctrl;
> + clkevt->load = channel_base + timer->load;
> + clkevt->enable = channel_base + timer->enable;
> + clkevt->reload = channel_base + timer->reload;
> + clkevt->value = channel_base + timer->value;
> + clkevt->intclr = channel_base + timer->intclr;
> + clkevt->intmask = channel_base + timer->intmask;
> +}
> +
> +static int __init starfive_timer_probe(struct platform_device *pdev)
> +{
> + const struct starfive_timer_chan_base *timer_base = of_device_get_match_data(&pdev->dev);
> + char name[10];
> + struct starfive_timer_priv *priv;
> + struct starfive_clkevt *clkevt;
> + struct clk *pclk;
> + struct reset_control *rst;
> + int ch;
> + int ret;
> +
> + priv = devm_kzalloc(&pdev->dev, struct_size(priv, clkevt, timer_base->channel_num),
> + GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(priv->base))
> + return dev_err_probe(&pdev->dev, PTR_ERR(priv->base),
> + "failed to map registers\n");
> +
> + rst = devm_reset_control_get_exclusive(&pdev->dev, "apb");
> + if (IS_ERR(rst))
> + return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get apb reset\n");
> +
> + pclk = devm_clk_get_enabled(&pdev->dev, "apb");
> + if (IS_ERR(pclk))
> + return dev_err_probe(&pdev->dev, PTR_ERR(pclk),
> + "failed to get & enable apb clock\n");
> +
> + ret = reset_control_deassert(rst);
> + if (ret)
> + goto err;
> +
> + priv->dev = &pdev->dev;
> + platform_set_drvdata(pdev, priv);
> +
> + for (ch = 0; ch < timer_base->channel_num; ch++) {
> + clkevt = &priv->clkevt[ch];
> + snprintf(name, sizeof(name), "ch%d", ch);
> +
> + starfive_clkevt_base_init(timer_base, clkevt, priv->base, ch);
> + /* Ensure timers are disabled */
> + starfive_timer_disable(clkevt);
> +
> + rst = devm_reset_control_get_exclusive(&pdev->dev, name);
> + if (IS_ERR(rst)) {
> + ret = PTR_ERR(rst);
> + goto err;
> + }
> +
> + clkevt->clk = devm_clk_get_enabled(&pdev->dev, name);
> + if (IS_ERR(clkevt->clk)) {
> + ret = PTR_ERR(clkevt->clk);
> + goto err;
> + }
> +
> + ret = reset_control_deassert(rst);
> + if (ret)
> + goto ch_err;
> +
> + clkevt->irq = platform_get_irq(pdev, ch);
> + if (clkevt->irq < 0) {
> + ret = clkevt->irq;
> + goto ch_err;
> + }
> +
> + snprintf(clkevt->name, sizeof(clkevt->name), "%s.ch%d", pdev->name, ch);
> + starfive_clockevents_register(clkevt);
> +
> + ret = devm_request_irq(&pdev->dev, clkevt->irq, starfive_timer_interrupt,
> + IRQF_TIMER | IRQF_IRQPOLL,
> + clkevt->name, &clkevt->evt);
> + if (ret)
> + goto ch_err;
> +
> + ret = starfive_clocksource_init(clkevt);
> + if (ret)
> + goto ch_err;
> + }
> +
> + return 0;
> +
> +ch_err:
> + /* Only unregister the failed channel and the rest timer channels continue to work. */
> + clk_disable_unprepare(clkevt->clk);
> +err:
> + /* If no other channel successfully registers, pclk should be disabled. */
> + if (!ch)
> + clk_disable_unprepare(pclk);
> +
> + return ret;
> +}
> +
> +static const struct of_device_id starfive_timer_match[] = {
> + { .compatible = "starfive,jh7110-timer", .data = &starfive_timer_jh7110_base },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, starfive_timer_match);
> +
> +static struct platform_driver starfive_timer_driver = {
> + .probe = starfive_timer_probe,
> + .driver = {
> + .name = "starfive-timer",
> + .of_match_table = starfive_timer_match,
> + },
> +};
> +module_platform_driver(starfive_timer_driver);
> +
> +MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
> +MODULE_DESCRIPTION("StarFive timer driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clocksource/timer-starfive.h b/drivers/clocksource/timer-starfive.h
> new file mode 100644
> index 000000000000..62eb630cc98d
> --- /dev/null
> +++ b/drivers/clocksource/timer-starfive.h
> @@ -0,0 +1,96 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +#ifndef __STARFIVE_TIMER_H__
> +#define __STARFIVE_TIMER_H__
> +
> +/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */
> +#define STARFIVE_TIMER_CH_LEN 0x40
> +#define STARFIVE_TIMER_CH_BASE(x) ((STARFIVE_TIMER_CH_##x) * STARFIVE_TIMER_CH_LEN)
> +
> +#define STARFIVE_CLOCK_SOURCE_RATING 200
> +#define STARFIVE_VALID_BITS 32
> +#define STARFIVE_DELAY_US 0
> +#define STARFIVE_TIMEOUT_US 10000
> +#define STARFIVE_CLOCKEVENT_RATING 300
> +#define STARFIVE_TIMER_MAX_TICKS 0xffffffff
> +#define STARFIVE_TIMER_MIN_TICKS 0xf
> +
> +#define STARFIVE_TIMER_JH7110_INT_STATUS 0x00 /* RO[0:4]: Interrupt Status for channel0~4 */
> +#define STARFIVE_TIMER_JH7110_CTL 0x04 /* RW[0]: 0-continuous run, 1-single run */
> +#define STARFIVE_TIMER_JH7110_LOAD 0x08 /* RW: load value to counter */
> +#define STARFIVE_TIMER_JH7110_ENABLE 0x10 /* RW[0]: timer enable register */
> +#define STARFIVE_TIMER_JH7110_RELOAD 0x14 /* RW: write 1 or 0 both reload counter */
> +#define STARFIVE_TIMER_JH7110_VALUE 0x18 /* RO: timer value register */
> +#define STARFIVE_TIMER_JH7110_INT_CLR 0x20 /* RW: timer interrupt clear register */
> +#define STARFIVE_TIMER_JH7110_INT_MASK 0x24 /* RW[0]: timer interrupt mask register */
> +#define STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK BIT(1)
> +
> +enum STARFIVE_TIMER_CH {
> + STARFIVE_TIMER_CH_0 = 0,
> + STARFIVE_TIMER_CH_1,
> + STARFIVE_TIMER_CH_2,
> + STARFIVE_TIMER_CH_3,
> + STARFIVE_TIMER_CH_4,
> + STARFIVE_TIMER_CH_5,
> + STARFIVE_TIMER_CH_6,
> + STARFIVE_TIMER_CH_7,
> + STARFIVE_TIMER_CH_MAX
> +};
> +
> +enum STARFIVE_TIMER_INTMASK {
> + STARFIVE_TIMER_INTMASK_DIS = 0,
> + STARFIVE_TIMER_INTMASK_ENA = 1
> +};
> +
> +enum STARFIVE_TIMER_MOD {
> + STARFIVE_TIMER_MOD_CONTIN = 0,
> + STARFIVE_TIMER_MOD_SINGLE = 1
> +};
> +
> +enum STARFIVE_TIMER_CTL_EN {
> + STARFIVE_TIMER_DIS = 0,
> + STARFIVE_TIMER_ENA = 1
> +};
> +
> +struct starfive_timer_chan_base {
> + /* Resgister */
> + unsigned int ctrl;
> + unsigned int load;
> + unsigned int enable;
> + unsigned int reload;
> + unsigned int value;
> + unsigned int intclr;
> + unsigned int intmask;
> +
> + unsigned int channel_num; /* timer channel numbers */
> + unsigned int channel_base[];
> +};
> +
> +struct starfive_clkevt {
> + struct clock_event_device evt;
> + struct clk *clk;
> + char name[20];
> + int irq;
> + u32 periodic;
> + u32 rate;
> + u32 reload_val;
> + void __iomem *base;
> + void __iomem *ctrl;
> + void __iomem *load;
> + void __iomem *enable;
> + void __iomem *reload;
> + void __iomem *value;
> + void __iomem *intclr;
> + void __iomem *intmask;
> +};
> +
> +struct starfive_timer_priv {
> + struct device *dev;
> + void __iomem *base;
> + struct starfive_clkevt clkevt[];
> +};
> +
> +#endif /* __STARFIVE_TIMER_H__ */
Hi Daniel and Thomas,
I have submitted patches for Timer driver. Could you please help to review and give your comments?
Thanks.
Best regards,
Xingyu Wu
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/3] clocksource: Add StarFive timer driver
2023-06-02 9:45 ` Xingyu Wu
@ 2023-06-02 10:51 ` Emil Renner Berthing
-1 siblings, 0 replies; 20+ messages in thread
From: Emil Renner Berthing @ 2023-06-02 10:51 UTC (permalink / raw)
To: Xingyu Wu
Cc: Daniel Lezcano, Thomas Gleixner, devicetree, linux-riscv,
Krzysztof Kozlowski, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Philipp Zabel, Samin Guo, linux-kernel, Conor Dooley
On Fri, 2 Jun 2023 at 11:48, Xingyu Wu <xingyu.wu@starfivetech.com> wrote:
>
> On 2023/3/20 21:54, Xingyu Wu wrote:
> > Add timer driver for the StarFive JH7110 SoC.
> >
> > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> > ---
> > MAINTAINERS | 7 +
> > drivers/clocksource/Kconfig | 12 +
> > drivers/clocksource/Makefile | 1 +
> > drivers/clocksource/timer-starfive.c | 390 +++++++++++++++++++++++++++
> > drivers/clocksource/timer-starfive.h | 96 +++++++
> > 5 files changed, 506 insertions(+)
> > create mode 100644 drivers/clocksource/timer-starfive.c
> > create mode 100644 drivers/clocksource/timer-starfive.h
Hi Xingyu,
Just by a quick glance you're again adding a header that is only used
in one file. I don't see any other driver in drivers/clocksource doing
that, so I don't understand why you need that.
/Emil
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 958b7ec118b4..dac6298d8f6e 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -19958,6 +19958,13 @@ S: Maintained
> > T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
> > F: drivers/soc/starfive/
> >
> > +STARFIVE TIMER DRIVER
> > +M: Samin Guo <samin.guo@starfivetech.com>
> > +M: Xingyu Wu <xingyu.wu@starfivetech.com>
> > +S: Supported
> > +F: Documentation/devicetree/bindings/timer/starfive*
> > +F: drivers/clocksource/timer-starfive*
> > +
> > STARFIVE TRNG DRIVER
> > M: Jia Jie Ho <jiajie.ho@starfivetech.com>
> > S: Supported
> > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> > index 5fc8f0e7fb38..35daf07d4db7 100644
> > --- a/drivers/clocksource/Kconfig
> > +++ b/drivers/clocksource/Kconfig
> > @@ -630,6 +630,18 @@ config RISCV_TIMER
> > is accessed via both the SBI and the rdcycle instruction. This is
> > required for all RISC-V systems.
> >
> > +config STARFIVE_TIMER
> > + bool "Timer for the STARFIVE SoCs"
> > + depends on ARCH_STARFIVE || COMPILE_TEST
> > + select TIMER_OF
> > + select CLKSRC_MMIO
> > + default ARCH_STARFIVE
> > + help
> > + This enables the timer for StarFive SoCs. On RISC-V platform,
> > + the system has started RISCV_TIMER. But you can also use this timer
> > + to do a lot more on StarFive SoCs. This timer can provide high
> > + precision and four channels to use in JH7110 SoC.
> > +
> > config CLINT_TIMER
> > bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
> > depends on GENERIC_SCHED_CLOCK && RISCV
> > diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> > index 64ab547de97b..276695d95cdc 100644
> > --- a/drivers/clocksource/Makefile
> > +++ b/drivers/clocksource/Makefile
> > @@ -80,6 +80,7 @@ obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o
> > obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
> > obj-$(CONFIG_X86_NUMACHIP) += numachip.o
> > obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o
> > +obj-$(CONFIG_STARFIVE_TIMER) += timer-starfive.o
> > obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
> > obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
> > obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
> > diff --git a/drivers/clocksource/timer-starfive.c b/drivers/clocksource/timer-starfive.c
> > new file mode 100644
> > index 000000000000..53163948ed86
> > --- /dev/null
> > +++ b/drivers/clocksource/timer-starfive.c
> > @@ -0,0 +1,390 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Starfive Timer driver
> > + *
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + *
> > + * Author:
> > + * Xingyu Wu <xingyu.wu@starfivetech.com>
> > + * Samin Guo <samin.guo@starfivetech.com>
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/clockchips.h>
> > +#include <linux/clocksource.h>
> > +#include <linux/err.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/irq.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/reset.h>
> > +#include <linux/sched_clock.h>
> > +
> > +#include "timer-starfive.h"
> > +
> > +static const struct starfive_timer_chan_base starfive_timer_jh7110_base = {
> > + .ctrl = STARFIVE_TIMER_JH7110_CTL,
> > + .load = STARFIVE_TIMER_JH7110_LOAD,
> > + .enable = STARFIVE_TIMER_JH7110_ENABLE,
> > + .reload = STARFIVE_TIMER_JH7110_RELOAD,
> > + .value = STARFIVE_TIMER_JH7110_VALUE,
> > + .intclr = STARFIVE_TIMER_JH7110_INT_CLR,
> > + .intmask = STARFIVE_TIMER_JH7110_INT_MASK,
> > + .channel_num = STARFIVE_TIMER_CH_4,
> > + .channel_base = {STARFIVE_TIMER_CH_BASE(0), STARFIVE_TIMER_CH_BASE(1),
> > + STARFIVE_TIMER_CH_BASE(2), STARFIVE_TIMER_CH_BASE(3)},
> > +};
> > +
> > +static inline struct starfive_clkevt *to_starfive_clkevt(struct clock_event_device *evt)
> > +{
> > + return container_of(evt, struct starfive_clkevt, evt);
> > +}
> > +
> > +/* 0:continuous-run mode, 1:single-run mode */
> > +static inline void starfive_timer_set_mod(struct starfive_clkevt *clkevt, int mod)
> > +{
> > + writel(mod, clkevt->ctrl);
> > +}
> > +
> > +/* Interrupt Mask Register, 0:Unmask, 1:Mask */
> > +static inline void starfive_timer_int_enable(struct starfive_clkevt *clkevt)
> > +{
> > + writel(STARFIVE_TIMER_INTMASK_DIS, clkevt->intmask);
> > +}
> > +
> > +static inline void starfive_timer_int_disable(struct starfive_clkevt *clkevt)
> > +{
> > + writel(STARFIVE_TIMER_INTMASK_ENA, clkevt->intmask);
> > +}
> > +
> > +/*
> > + * BIT(0): Read value represent channel intr status.
> > + * Write 1 to this bit to clear interrupt. Write 0 has no effects.
> > + * BIT(1): "1" means that it is clearing interrupt. BIT(0) can not be written.
> > + */
> > +static inline int starfive_timer_int_clear(struct starfive_clkevt *clkevt)
> > +{
> > + u32 value;
> > + int ret;
> > +
> > + /* waiting interrupt can be to clearing */
> > + ret = readl_poll_timeout_atomic(clkevt->intclr, value,
> > + !(value & STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK),
> > + STARFIVE_DELAY_US, STARFIVE_TIMEOUT_US);
> > + if (!ret)
> > + writel(0x1, clkevt->intclr);
> > +
> > + return ret;
> > +}
> > +
> > +/*
> > + * The initial value to be loaded into the
> > + * counter and is also used as the reload value.
> > + * val = clock rate --> 1s
> > + */
> > +static inline void starfive_timer_set_load(struct starfive_clkevt *clkevt, u32 val)
> > +{
> > + writel(val, clkevt->load);
> > +}
> > +
> > +static inline u32 starfive_timer_get_val(struct starfive_clkevt *clkevt)
> > +{
> > + return readl(clkevt->value);
> > +}
> > +
> > +/*
> > + * Write RELOAD register to reload preset value to counter.
> > + * (Write 0 and write 1 are both ok)
> > + */
> > +static inline void starfive_timer_set_reload(struct starfive_clkevt *clkevt)
> > +{
> > + writel(0, clkevt->reload);
> > +}
> > +
> > +static inline void starfive_timer_enable(struct starfive_clkevt *clkevt)
> > +{
> > + writel(STARFIVE_TIMER_ENA, clkevt->enable);
> > +}
> > +
> > +static inline void starfive_timer_disable(struct starfive_clkevt *clkevt)
> > +{
> > + writel(STARFIVE_TIMER_DIS, clkevt->enable);
> > +}
> > +
> > +static int starfive_timer_int_init_enable(struct starfive_clkevt *clkevt)
> > +{
> > + int ret;
> > +
> > + starfive_timer_int_disable(clkevt);
> > + ret = starfive_timer_int_clear(clkevt);
> > + if (ret)
> > + return ret;
> > +
> > + starfive_timer_int_enable(clkevt);
> > + starfive_timer_enable(clkevt);
> > +
> > + return 0;
> > +}
> > +
> > +static int starfive_timer_shutdown(struct clock_event_device *evt)
> > +{
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + starfive_timer_disable(clkevt);
> > + return starfive_timer_int_clear(clkevt);
> > +}
> > +
> > +static void starfive_timer_suspend(struct clock_event_device *evt)
> > +{
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + clkevt->reload_val = starfive_timer_get_val(clkevt);
> > + starfive_timer_shutdown(evt);
> > +}
> > +
> > +static void starfive_timer_resume(struct clock_event_device *evt)
> > +{
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + starfive_timer_set_load(clkevt, clkevt->reload_val);
> > + starfive_timer_set_reload(clkevt);
> > + starfive_timer_int_enable(clkevt);
> > + starfive_timer_enable(clkevt);
> > +}
> > +
> > +static int starfive_timer_tick_resume(struct clock_event_device *evt)
> > +{
> > + starfive_timer_resume(evt);
> > +
> > + return 0;
> > +}
> > +
> > +static int starfive_clocksource_init(struct starfive_clkevt *clkevt)
> > +{
> > + int ret;
> > +
> > + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
> > + starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
> > + ret = starfive_timer_int_init_enable(clkevt);
> > + if (ret)
> > + return ret;
> > +
> > + return clocksource_mmio_init(clkevt->value, clkevt->name, clkevt->rate,
> > + STARFIVE_CLOCK_SOURCE_RATING, STARFIVE_VALID_BITS,
> > + clocksource_mmio_readl_down);
> > +}
> > +
> > +/* IRQ handler for the timer */
> > +static irqreturn_t starfive_timer_interrupt(int irq, void *priv)
> > +{
> > + struct clock_event_device *evt = (struct clock_event_device *)priv;
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + if (starfive_timer_int_clear(clkevt))
> > + return IRQ_NONE;
> > +
> > + if (evt->event_handler)
> > + evt->event_handler(evt);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static int starfive_timer_set_periodic(struct clock_event_device *evt)
> > +{
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + starfive_timer_disable(clkevt);
> > + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
> > + starfive_timer_set_load(clkevt, clkevt->periodic);
> > +
> > + return starfive_timer_int_init_enable(clkevt);
> > +}
> > +
> > +static int starfive_timer_set_oneshot(struct clock_event_device *evt)
> > +{
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + starfive_timer_disable(clkevt);
> > + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
> > + starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
> > +
> > + return starfive_timer_int_init_enable(clkevt);
> > +}
> > +
> > +static int starfive_timer_set_next_event(unsigned long next,
> > + struct clock_event_device *evt)
> > +{
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + starfive_timer_disable(clkevt);
> > + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
> > + starfive_timer_set_load(clkevt, next);
> > + starfive_timer_enable(clkevt);
> > +
> > + return 0;
> > +}
> > +
> > +static void starfive_set_clockevent(struct clock_event_device *evt)
> > +{
> > + evt->features = CLOCK_EVT_FEAT_PERIODIC |
> > + CLOCK_EVT_FEAT_ONESHOT |
> > + CLOCK_EVT_FEAT_DYNIRQ;
> > + evt->set_state_shutdown = starfive_timer_shutdown;
> > + evt->set_state_periodic = starfive_timer_set_periodic;
> > + evt->set_state_oneshot = starfive_timer_set_oneshot;
> > + evt->set_state_oneshot_stopped = starfive_timer_shutdown;
> > + evt->tick_resume = starfive_timer_tick_resume;
> > + evt->set_next_event = starfive_timer_set_next_event;
> > + evt->suspend = starfive_timer_suspend;
> > + evt->resume = starfive_timer_resume;
> > + evt->rating = STARFIVE_CLOCKEVENT_RATING;
> > +}
> > +
> > +static void starfive_clockevents_register(struct starfive_clkevt *clkevt)
> > +{
> > + clkevt->rate = clk_get_rate(clkevt->clk);
> > + clkevt->periodic = DIV_ROUND_CLOSEST(clkevt->rate, HZ);
> > +
> > + starfive_set_clockevent(&clkevt->evt);
> > + clkevt->evt.name = clkevt->name;
> > + clkevt->evt.irq = clkevt->irq;
> > + clkevt->evt.cpumask = cpu_possible_mask;
> > +
> > + clockevents_config_and_register(&clkevt->evt, clkevt->rate,
> > + STARFIVE_TIMER_MIN_TICKS, STARFIVE_TIMER_MAX_TICKS);
> > +}
> > +
> > +static void __init starfive_clkevt_base_init(const struct starfive_timer_chan_base *timer,
> > + struct starfive_clkevt *clkevt,
> > + void __iomem *base, int ch)
> > +{
> > + void __iomem *channel_base;
> > +
> > + channel_base = base + timer->channel_base[ch];
> > + clkevt->base = channel_base;
> > + clkevt->ctrl = channel_base + timer->ctrl;
> > + clkevt->load = channel_base + timer->load;
> > + clkevt->enable = channel_base + timer->enable;
> > + clkevt->reload = channel_base + timer->reload;
> > + clkevt->value = channel_base + timer->value;
> > + clkevt->intclr = channel_base + timer->intclr;
> > + clkevt->intmask = channel_base + timer->intmask;
> > +}
> > +
> > +static int __init starfive_timer_probe(struct platform_device *pdev)
> > +{
> > + const struct starfive_timer_chan_base *timer_base = of_device_get_match_data(&pdev->dev);
> > + char name[10];
> > + struct starfive_timer_priv *priv;
> > + struct starfive_clkevt *clkevt;
> > + struct clk *pclk;
> > + struct reset_control *rst;
> > + int ch;
> > + int ret;
> > +
> > + priv = devm_kzalloc(&pdev->dev, struct_size(priv, clkevt, timer_base->channel_num),
> > + GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(priv->base))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(priv->base),
> > + "failed to map registers\n");
> > +
> > + rst = devm_reset_control_get_exclusive(&pdev->dev, "apb");
> > + if (IS_ERR(rst))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get apb reset\n");
> > +
> > + pclk = devm_clk_get_enabled(&pdev->dev, "apb");
> > + if (IS_ERR(pclk))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(pclk),
> > + "failed to get & enable apb clock\n");
> > +
> > + ret = reset_control_deassert(rst);
> > + if (ret)
> > + goto err;
> > +
> > + priv->dev = &pdev->dev;
> > + platform_set_drvdata(pdev, priv);
> > +
> > + for (ch = 0; ch < timer_base->channel_num; ch++) {
> > + clkevt = &priv->clkevt[ch];
> > + snprintf(name, sizeof(name), "ch%d", ch);
> > +
> > + starfive_clkevt_base_init(timer_base, clkevt, priv->base, ch);
> > + /* Ensure timers are disabled */
> > + starfive_timer_disable(clkevt);
> > +
> > + rst = devm_reset_control_get_exclusive(&pdev->dev, name);
> > + if (IS_ERR(rst)) {
> > + ret = PTR_ERR(rst);
> > + goto err;
> > + }
> > +
> > + clkevt->clk = devm_clk_get_enabled(&pdev->dev, name);
> > + if (IS_ERR(clkevt->clk)) {
> > + ret = PTR_ERR(clkevt->clk);
> > + goto err;
> > + }
> > +
> > + ret = reset_control_deassert(rst);
> > + if (ret)
> > + goto ch_err;
> > +
> > + clkevt->irq = platform_get_irq(pdev, ch);
> > + if (clkevt->irq < 0) {
> > + ret = clkevt->irq;
> > + goto ch_err;
> > + }
> > +
> > + snprintf(clkevt->name, sizeof(clkevt->name), "%s.ch%d", pdev->name, ch);
> > + starfive_clockevents_register(clkevt);
> > +
> > + ret = devm_request_irq(&pdev->dev, clkevt->irq, starfive_timer_interrupt,
> > + IRQF_TIMER | IRQF_IRQPOLL,
> > + clkevt->name, &clkevt->evt);
> > + if (ret)
> > + goto ch_err;
> > +
> > + ret = starfive_clocksource_init(clkevt);
> > + if (ret)
> > + goto ch_err;
> > + }
> > +
> > + return 0;
> > +
> > +ch_err:
> > + /* Only unregister the failed channel and the rest timer channels continue to work. */
> > + clk_disable_unprepare(clkevt->clk);
> > +err:
> > + /* If no other channel successfully registers, pclk should be disabled. */
> > + if (!ch)
> > + clk_disable_unprepare(pclk);
> > +
> > + return ret;
> > +}
> > +
> > +static const struct of_device_id starfive_timer_match[] = {
> > + { .compatible = "starfive,jh7110-timer", .data = &starfive_timer_jh7110_base },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, starfive_timer_match);
> > +
> > +static struct platform_driver starfive_timer_driver = {
> > + .probe = starfive_timer_probe,
> > + .driver = {
> > + .name = "starfive-timer",
> > + .of_match_table = starfive_timer_match,
> > + },
> > +};
> > +module_platform_driver(starfive_timer_driver);
> > +
> > +MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
> > +MODULE_DESCRIPTION("StarFive timer driver");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/clocksource/timer-starfive.h b/drivers/clocksource/timer-starfive.h
> > new file mode 100644
> > index 000000000000..62eb630cc98d
> > --- /dev/null
> > +++ b/drivers/clocksource/timer-starfive.h
> > @@ -0,0 +1,96 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + */
> > +
> > +#ifndef __STARFIVE_TIMER_H__
> > +#define __STARFIVE_TIMER_H__
> > +
> > +/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */
> > +#define STARFIVE_TIMER_CH_LEN 0x40
> > +#define STARFIVE_TIMER_CH_BASE(x) ((STARFIVE_TIMER_CH_##x) * STARFIVE_TIMER_CH_LEN)
> > +
> > +#define STARFIVE_CLOCK_SOURCE_RATING 200
> > +#define STARFIVE_VALID_BITS 32
> > +#define STARFIVE_DELAY_US 0
> > +#define STARFIVE_TIMEOUT_US 10000
> > +#define STARFIVE_CLOCKEVENT_RATING 300
> > +#define STARFIVE_TIMER_MAX_TICKS 0xffffffff
> > +#define STARFIVE_TIMER_MIN_TICKS 0xf
> > +
> > +#define STARFIVE_TIMER_JH7110_INT_STATUS 0x00 /* RO[0:4]: Interrupt Status for channel0~4 */
> > +#define STARFIVE_TIMER_JH7110_CTL 0x04 /* RW[0]: 0-continuous run, 1-single run */
> > +#define STARFIVE_TIMER_JH7110_LOAD 0x08 /* RW: load value to counter */
> > +#define STARFIVE_TIMER_JH7110_ENABLE 0x10 /* RW[0]: timer enable register */
> > +#define STARFIVE_TIMER_JH7110_RELOAD 0x14 /* RW: write 1 or 0 both reload counter */
> > +#define STARFIVE_TIMER_JH7110_VALUE 0x18 /* RO: timer value register */
> > +#define STARFIVE_TIMER_JH7110_INT_CLR 0x20 /* RW: timer interrupt clear register */
> > +#define STARFIVE_TIMER_JH7110_INT_MASK 0x24 /* RW[0]: timer interrupt mask register */
> > +#define STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK BIT(1)
> > +
> > +enum STARFIVE_TIMER_CH {
> > + STARFIVE_TIMER_CH_0 = 0,
> > + STARFIVE_TIMER_CH_1,
> > + STARFIVE_TIMER_CH_2,
> > + STARFIVE_TIMER_CH_3,
> > + STARFIVE_TIMER_CH_4,
> > + STARFIVE_TIMER_CH_5,
> > + STARFIVE_TIMER_CH_6,
> > + STARFIVE_TIMER_CH_7,
> > + STARFIVE_TIMER_CH_MAX
> > +};
> > +
> > +enum STARFIVE_TIMER_INTMASK {
> > + STARFIVE_TIMER_INTMASK_DIS = 0,
> > + STARFIVE_TIMER_INTMASK_ENA = 1
> > +};
> > +
> > +enum STARFIVE_TIMER_MOD {
> > + STARFIVE_TIMER_MOD_CONTIN = 0,
> > + STARFIVE_TIMER_MOD_SINGLE = 1
> > +};
> > +
> > +enum STARFIVE_TIMER_CTL_EN {
> > + STARFIVE_TIMER_DIS = 0,
> > + STARFIVE_TIMER_ENA = 1
> > +};
> > +
> > +struct starfive_timer_chan_base {
> > + /* Resgister */
> > + unsigned int ctrl;
> > + unsigned int load;
> > + unsigned int enable;
> > + unsigned int reload;
> > + unsigned int value;
> > + unsigned int intclr;
> > + unsigned int intmask;
> > +
> > + unsigned int channel_num; /* timer channel numbers */
> > + unsigned int channel_base[];
> > +};
> > +
> > +struct starfive_clkevt {
> > + struct clock_event_device evt;
> > + struct clk *clk;
> > + char name[20];
> > + int irq;
> > + u32 periodic;
> > + u32 rate;
> > + u32 reload_val;
> > + void __iomem *base;
> > + void __iomem *ctrl;
> > + void __iomem *load;
> > + void __iomem *enable;
> > + void __iomem *reload;
> > + void __iomem *value;
> > + void __iomem *intclr;
> > + void __iomem *intmask;
> > +};
> > +
> > +struct starfive_timer_priv {
> > + struct device *dev;
> > + void __iomem *base;
> > + struct starfive_clkevt clkevt[];
> > +};
> > +
> > +#endif /* __STARFIVE_TIMER_H__ */
>
> Hi Daniel and Thomas,
>
> I have submitted patches for Timer driver. Could you please help to review and give your comments?
> Thanks.
>
> Best regards,
> Xingyu Wu
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/3] clocksource: Add StarFive timer driver
@ 2023-06-02 10:51 ` Emil Renner Berthing
0 siblings, 0 replies; 20+ messages in thread
From: Emil Renner Berthing @ 2023-06-02 10:51 UTC (permalink / raw)
To: Xingyu Wu
Cc: Daniel Lezcano, Thomas Gleixner, devicetree, linux-riscv,
Krzysztof Kozlowski, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Philipp Zabel, Samin Guo, linux-kernel, Conor Dooley
On Fri, 2 Jun 2023 at 11:48, Xingyu Wu <xingyu.wu@starfivetech.com> wrote:
>
> On 2023/3/20 21:54, Xingyu Wu wrote:
> > Add timer driver for the StarFive JH7110 SoC.
> >
> > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> > ---
> > MAINTAINERS | 7 +
> > drivers/clocksource/Kconfig | 12 +
> > drivers/clocksource/Makefile | 1 +
> > drivers/clocksource/timer-starfive.c | 390 +++++++++++++++++++++++++++
> > drivers/clocksource/timer-starfive.h | 96 +++++++
> > 5 files changed, 506 insertions(+)
> > create mode 100644 drivers/clocksource/timer-starfive.c
> > create mode 100644 drivers/clocksource/timer-starfive.h
Hi Xingyu,
Just by a quick glance you're again adding a header that is only used
in one file. I don't see any other driver in drivers/clocksource doing
that, so I don't understand why you need that.
/Emil
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 958b7ec118b4..dac6298d8f6e 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -19958,6 +19958,13 @@ S: Maintained
> > T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
> > F: drivers/soc/starfive/
> >
> > +STARFIVE TIMER DRIVER
> > +M: Samin Guo <samin.guo@starfivetech.com>
> > +M: Xingyu Wu <xingyu.wu@starfivetech.com>
> > +S: Supported
> > +F: Documentation/devicetree/bindings/timer/starfive*
> > +F: drivers/clocksource/timer-starfive*
> > +
> > STARFIVE TRNG DRIVER
> > M: Jia Jie Ho <jiajie.ho@starfivetech.com>
> > S: Supported
> > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> > index 5fc8f0e7fb38..35daf07d4db7 100644
> > --- a/drivers/clocksource/Kconfig
> > +++ b/drivers/clocksource/Kconfig
> > @@ -630,6 +630,18 @@ config RISCV_TIMER
> > is accessed via both the SBI and the rdcycle instruction. This is
> > required for all RISC-V systems.
> >
> > +config STARFIVE_TIMER
> > + bool "Timer for the STARFIVE SoCs"
> > + depends on ARCH_STARFIVE || COMPILE_TEST
> > + select TIMER_OF
> > + select CLKSRC_MMIO
> > + default ARCH_STARFIVE
> > + help
> > + This enables the timer for StarFive SoCs. On RISC-V platform,
> > + the system has started RISCV_TIMER. But you can also use this timer
> > + to do a lot more on StarFive SoCs. This timer can provide high
> > + precision and four channels to use in JH7110 SoC.
> > +
> > config CLINT_TIMER
> > bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
> > depends on GENERIC_SCHED_CLOCK && RISCV
> > diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> > index 64ab547de97b..276695d95cdc 100644
> > --- a/drivers/clocksource/Makefile
> > +++ b/drivers/clocksource/Makefile
> > @@ -80,6 +80,7 @@ obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o
> > obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o
> > obj-$(CONFIG_X86_NUMACHIP) += numachip.o
> > obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o
> > +obj-$(CONFIG_STARFIVE_TIMER) += timer-starfive.o
> > obj-$(CONFIG_CLINT_TIMER) += timer-clint.o
> > obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o
> > obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
> > diff --git a/drivers/clocksource/timer-starfive.c b/drivers/clocksource/timer-starfive.c
> > new file mode 100644
> > index 000000000000..53163948ed86
> > --- /dev/null
> > +++ b/drivers/clocksource/timer-starfive.c
> > @@ -0,0 +1,390 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Starfive Timer driver
> > + *
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + *
> > + * Author:
> > + * Xingyu Wu <xingyu.wu@starfivetech.com>
> > + * Samin Guo <samin.guo@starfivetech.com>
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/clockchips.h>
> > +#include <linux/clocksource.h>
> > +#include <linux/err.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/irq.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/reset.h>
> > +#include <linux/sched_clock.h>
> > +
> > +#include "timer-starfive.h"
> > +
> > +static const struct starfive_timer_chan_base starfive_timer_jh7110_base = {
> > + .ctrl = STARFIVE_TIMER_JH7110_CTL,
> > + .load = STARFIVE_TIMER_JH7110_LOAD,
> > + .enable = STARFIVE_TIMER_JH7110_ENABLE,
> > + .reload = STARFIVE_TIMER_JH7110_RELOAD,
> > + .value = STARFIVE_TIMER_JH7110_VALUE,
> > + .intclr = STARFIVE_TIMER_JH7110_INT_CLR,
> > + .intmask = STARFIVE_TIMER_JH7110_INT_MASK,
> > + .channel_num = STARFIVE_TIMER_CH_4,
> > + .channel_base = {STARFIVE_TIMER_CH_BASE(0), STARFIVE_TIMER_CH_BASE(1),
> > + STARFIVE_TIMER_CH_BASE(2), STARFIVE_TIMER_CH_BASE(3)},
> > +};
> > +
> > +static inline struct starfive_clkevt *to_starfive_clkevt(struct clock_event_device *evt)
> > +{
> > + return container_of(evt, struct starfive_clkevt, evt);
> > +}
> > +
> > +/* 0:continuous-run mode, 1:single-run mode */
> > +static inline void starfive_timer_set_mod(struct starfive_clkevt *clkevt, int mod)
> > +{
> > + writel(mod, clkevt->ctrl);
> > +}
> > +
> > +/* Interrupt Mask Register, 0:Unmask, 1:Mask */
> > +static inline void starfive_timer_int_enable(struct starfive_clkevt *clkevt)
> > +{
> > + writel(STARFIVE_TIMER_INTMASK_DIS, clkevt->intmask);
> > +}
> > +
> > +static inline void starfive_timer_int_disable(struct starfive_clkevt *clkevt)
> > +{
> > + writel(STARFIVE_TIMER_INTMASK_ENA, clkevt->intmask);
> > +}
> > +
> > +/*
> > + * BIT(0): Read value represent channel intr status.
> > + * Write 1 to this bit to clear interrupt. Write 0 has no effects.
> > + * BIT(1): "1" means that it is clearing interrupt. BIT(0) can not be written.
> > + */
> > +static inline int starfive_timer_int_clear(struct starfive_clkevt *clkevt)
> > +{
> > + u32 value;
> > + int ret;
> > +
> > + /* waiting interrupt can be to clearing */
> > + ret = readl_poll_timeout_atomic(clkevt->intclr, value,
> > + !(value & STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK),
> > + STARFIVE_DELAY_US, STARFIVE_TIMEOUT_US);
> > + if (!ret)
> > + writel(0x1, clkevt->intclr);
> > +
> > + return ret;
> > +}
> > +
> > +/*
> > + * The initial value to be loaded into the
> > + * counter and is also used as the reload value.
> > + * val = clock rate --> 1s
> > + */
> > +static inline void starfive_timer_set_load(struct starfive_clkevt *clkevt, u32 val)
> > +{
> > + writel(val, clkevt->load);
> > +}
> > +
> > +static inline u32 starfive_timer_get_val(struct starfive_clkevt *clkevt)
> > +{
> > + return readl(clkevt->value);
> > +}
> > +
> > +/*
> > + * Write RELOAD register to reload preset value to counter.
> > + * (Write 0 and write 1 are both ok)
> > + */
> > +static inline void starfive_timer_set_reload(struct starfive_clkevt *clkevt)
> > +{
> > + writel(0, clkevt->reload);
> > +}
> > +
> > +static inline void starfive_timer_enable(struct starfive_clkevt *clkevt)
> > +{
> > + writel(STARFIVE_TIMER_ENA, clkevt->enable);
> > +}
> > +
> > +static inline void starfive_timer_disable(struct starfive_clkevt *clkevt)
> > +{
> > + writel(STARFIVE_TIMER_DIS, clkevt->enable);
> > +}
> > +
> > +static int starfive_timer_int_init_enable(struct starfive_clkevt *clkevt)
> > +{
> > + int ret;
> > +
> > + starfive_timer_int_disable(clkevt);
> > + ret = starfive_timer_int_clear(clkevt);
> > + if (ret)
> > + return ret;
> > +
> > + starfive_timer_int_enable(clkevt);
> > + starfive_timer_enable(clkevt);
> > +
> > + return 0;
> > +}
> > +
> > +static int starfive_timer_shutdown(struct clock_event_device *evt)
> > +{
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + starfive_timer_disable(clkevt);
> > + return starfive_timer_int_clear(clkevt);
> > +}
> > +
> > +static void starfive_timer_suspend(struct clock_event_device *evt)
> > +{
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + clkevt->reload_val = starfive_timer_get_val(clkevt);
> > + starfive_timer_shutdown(evt);
> > +}
> > +
> > +static void starfive_timer_resume(struct clock_event_device *evt)
> > +{
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + starfive_timer_set_load(clkevt, clkevt->reload_val);
> > + starfive_timer_set_reload(clkevt);
> > + starfive_timer_int_enable(clkevt);
> > + starfive_timer_enable(clkevt);
> > +}
> > +
> > +static int starfive_timer_tick_resume(struct clock_event_device *evt)
> > +{
> > + starfive_timer_resume(evt);
> > +
> > + return 0;
> > +}
> > +
> > +static int starfive_clocksource_init(struct starfive_clkevt *clkevt)
> > +{
> > + int ret;
> > +
> > + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
> > + starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
> > + ret = starfive_timer_int_init_enable(clkevt);
> > + if (ret)
> > + return ret;
> > +
> > + return clocksource_mmio_init(clkevt->value, clkevt->name, clkevt->rate,
> > + STARFIVE_CLOCK_SOURCE_RATING, STARFIVE_VALID_BITS,
> > + clocksource_mmio_readl_down);
> > +}
> > +
> > +/* IRQ handler for the timer */
> > +static irqreturn_t starfive_timer_interrupt(int irq, void *priv)
> > +{
> > + struct clock_event_device *evt = (struct clock_event_device *)priv;
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + if (starfive_timer_int_clear(clkevt))
> > + return IRQ_NONE;
> > +
> > + if (evt->event_handler)
> > + evt->event_handler(evt);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static int starfive_timer_set_periodic(struct clock_event_device *evt)
> > +{
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + starfive_timer_disable(clkevt);
> > + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
> > + starfive_timer_set_load(clkevt, clkevt->periodic);
> > +
> > + return starfive_timer_int_init_enable(clkevt);
> > +}
> > +
> > +static int starfive_timer_set_oneshot(struct clock_event_device *evt)
> > +{
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + starfive_timer_disable(clkevt);
> > + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
> > + starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
> > +
> > + return starfive_timer_int_init_enable(clkevt);
> > +}
> > +
> > +static int starfive_timer_set_next_event(unsigned long next,
> > + struct clock_event_device *evt)
> > +{
> > + struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
> > +
> > + starfive_timer_disable(clkevt);
> > + starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
> > + starfive_timer_set_load(clkevt, next);
> > + starfive_timer_enable(clkevt);
> > +
> > + return 0;
> > +}
> > +
> > +static void starfive_set_clockevent(struct clock_event_device *evt)
> > +{
> > + evt->features = CLOCK_EVT_FEAT_PERIODIC |
> > + CLOCK_EVT_FEAT_ONESHOT |
> > + CLOCK_EVT_FEAT_DYNIRQ;
> > + evt->set_state_shutdown = starfive_timer_shutdown;
> > + evt->set_state_periodic = starfive_timer_set_periodic;
> > + evt->set_state_oneshot = starfive_timer_set_oneshot;
> > + evt->set_state_oneshot_stopped = starfive_timer_shutdown;
> > + evt->tick_resume = starfive_timer_tick_resume;
> > + evt->set_next_event = starfive_timer_set_next_event;
> > + evt->suspend = starfive_timer_suspend;
> > + evt->resume = starfive_timer_resume;
> > + evt->rating = STARFIVE_CLOCKEVENT_RATING;
> > +}
> > +
> > +static void starfive_clockevents_register(struct starfive_clkevt *clkevt)
> > +{
> > + clkevt->rate = clk_get_rate(clkevt->clk);
> > + clkevt->periodic = DIV_ROUND_CLOSEST(clkevt->rate, HZ);
> > +
> > + starfive_set_clockevent(&clkevt->evt);
> > + clkevt->evt.name = clkevt->name;
> > + clkevt->evt.irq = clkevt->irq;
> > + clkevt->evt.cpumask = cpu_possible_mask;
> > +
> > + clockevents_config_and_register(&clkevt->evt, clkevt->rate,
> > + STARFIVE_TIMER_MIN_TICKS, STARFIVE_TIMER_MAX_TICKS);
> > +}
> > +
> > +static void __init starfive_clkevt_base_init(const struct starfive_timer_chan_base *timer,
> > + struct starfive_clkevt *clkevt,
> > + void __iomem *base, int ch)
> > +{
> > + void __iomem *channel_base;
> > +
> > + channel_base = base + timer->channel_base[ch];
> > + clkevt->base = channel_base;
> > + clkevt->ctrl = channel_base + timer->ctrl;
> > + clkevt->load = channel_base + timer->load;
> > + clkevt->enable = channel_base + timer->enable;
> > + clkevt->reload = channel_base + timer->reload;
> > + clkevt->value = channel_base + timer->value;
> > + clkevt->intclr = channel_base + timer->intclr;
> > + clkevt->intmask = channel_base + timer->intmask;
> > +}
> > +
> > +static int __init starfive_timer_probe(struct platform_device *pdev)
> > +{
> > + const struct starfive_timer_chan_base *timer_base = of_device_get_match_data(&pdev->dev);
> > + char name[10];
> > + struct starfive_timer_priv *priv;
> > + struct starfive_clkevt *clkevt;
> > + struct clk *pclk;
> > + struct reset_control *rst;
> > + int ch;
> > + int ret;
> > +
> > + priv = devm_kzalloc(&pdev->dev, struct_size(priv, clkevt, timer_base->channel_num),
> > + GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(priv->base))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(priv->base),
> > + "failed to map registers\n");
> > +
> > + rst = devm_reset_control_get_exclusive(&pdev->dev, "apb");
> > + if (IS_ERR(rst))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get apb reset\n");
> > +
> > + pclk = devm_clk_get_enabled(&pdev->dev, "apb");
> > + if (IS_ERR(pclk))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(pclk),
> > + "failed to get & enable apb clock\n");
> > +
> > + ret = reset_control_deassert(rst);
> > + if (ret)
> > + goto err;
> > +
> > + priv->dev = &pdev->dev;
> > + platform_set_drvdata(pdev, priv);
> > +
> > + for (ch = 0; ch < timer_base->channel_num; ch++) {
> > + clkevt = &priv->clkevt[ch];
> > + snprintf(name, sizeof(name), "ch%d", ch);
> > +
> > + starfive_clkevt_base_init(timer_base, clkevt, priv->base, ch);
> > + /* Ensure timers are disabled */
> > + starfive_timer_disable(clkevt);
> > +
> > + rst = devm_reset_control_get_exclusive(&pdev->dev, name);
> > + if (IS_ERR(rst)) {
> > + ret = PTR_ERR(rst);
> > + goto err;
> > + }
> > +
> > + clkevt->clk = devm_clk_get_enabled(&pdev->dev, name);
> > + if (IS_ERR(clkevt->clk)) {
> > + ret = PTR_ERR(clkevt->clk);
> > + goto err;
> > + }
> > +
> > + ret = reset_control_deassert(rst);
> > + if (ret)
> > + goto ch_err;
> > +
> > + clkevt->irq = platform_get_irq(pdev, ch);
> > + if (clkevt->irq < 0) {
> > + ret = clkevt->irq;
> > + goto ch_err;
> > + }
> > +
> > + snprintf(clkevt->name, sizeof(clkevt->name), "%s.ch%d", pdev->name, ch);
> > + starfive_clockevents_register(clkevt);
> > +
> > + ret = devm_request_irq(&pdev->dev, clkevt->irq, starfive_timer_interrupt,
> > + IRQF_TIMER | IRQF_IRQPOLL,
> > + clkevt->name, &clkevt->evt);
> > + if (ret)
> > + goto ch_err;
> > +
> > + ret = starfive_clocksource_init(clkevt);
> > + if (ret)
> > + goto ch_err;
> > + }
> > +
> > + return 0;
> > +
> > +ch_err:
> > + /* Only unregister the failed channel and the rest timer channels continue to work. */
> > + clk_disable_unprepare(clkevt->clk);
> > +err:
> > + /* If no other channel successfully registers, pclk should be disabled. */
> > + if (!ch)
> > + clk_disable_unprepare(pclk);
> > +
> > + return ret;
> > +}
> > +
> > +static const struct of_device_id starfive_timer_match[] = {
> > + { .compatible = "starfive,jh7110-timer", .data = &starfive_timer_jh7110_base },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, starfive_timer_match);
> > +
> > +static struct platform_driver starfive_timer_driver = {
> > + .probe = starfive_timer_probe,
> > + .driver = {
> > + .name = "starfive-timer",
> > + .of_match_table = starfive_timer_match,
> > + },
> > +};
> > +module_platform_driver(starfive_timer_driver);
> > +
> > +MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
> > +MODULE_DESCRIPTION("StarFive timer driver");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/clocksource/timer-starfive.h b/drivers/clocksource/timer-starfive.h
> > new file mode 100644
> > index 000000000000..62eb630cc98d
> > --- /dev/null
> > +++ b/drivers/clocksource/timer-starfive.h
> > @@ -0,0 +1,96 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> > + */
> > +
> > +#ifndef __STARFIVE_TIMER_H__
> > +#define __STARFIVE_TIMER_H__
> > +
> > +/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */
> > +#define STARFIVE_TIMER_CH_LEN 0x40
> > +#define STARFIVE_TIMER_CH_BASE(x) ((STARFIVE_TIMER_CH_##x) * STARFIVE_TIMER_CH_LEN)
> > +
> > +#define STARFIVE_CLOCK_SOURCE_RATING 200
> > +#define STARFIVE_VALID_BITS 32
> > +#define STARFIVE_DELAY_US 0
> > +#define STARFIVE_TIMEOUT_US 10000
> > +#define STARFIVE_CLOCKEVENT_RATING 300
> > +#define STARFIVE_TIMER_MAX_TICKS 0xffffffff
> > +#define STARFIVE_TIMER_MIN_TICKS 0xf
> > +
> > +#define STARFIVE_TIMER_JH7110_INT_STATUS 0x00 /* RO[0:4]: Interrupt Status for channel0~4 */
> > +#define STARFIVE_TIMER_JH7110_CTL 0x04 /* RW[0]: 0-continuous run, 1-single run */
> > +#define STARFIVE_TIMER_JH7110_LOAD 0x08 /* RW: load value to counter */
> > +#define STARFIVE_TIMER_JH7110_ENABLE 0x10 /* RW[0]: timer enable register */
> > +#define STARFIVE_TIMER_JH7110_RELOAD 0x14 /* RW: write 1 or 0 both reload counter */
> > +#define STARFIVE_TIMER_JH7110_VALUE 0x18 /* RO: timer value register */
> > +#define STARFIVE_TIMER_JH7110_INT_CLR 0x20 /* RW: timer interrupt clear register */
> > +#define STARFIVE_TIMER_JH7110_INT_MASK 0x24 /* RW[0]: timer interrupt mask register */
> > +#define STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK BIT(1)
> > +
> > +enum STARFIVE_TIMER_CH {
> > + STARFIVE_TIMER_CH_0 = 0,
> > + STARFIVE_TIMER_CH_1,
> > + STARFIVE_TIMER_CH_2,
> > + STARFIVE_TIMER_CH_3,
> > + STARFIVE_TIMER_CH_4,
> > + STARFIVE_TIMER_CH_5,
> > + STARFIVE_TIMER_CH_6,
> > + STARFIVE_TIMER_CH_7,
> > + STARFIVE_TIMER_CH_MAX
> > +};
> > +
> > +enum STARFIVE_TIMER_INTMASK {
> > + STARFIVE_TIMER_INTMASK_DIS = 0,
> > + STARFIVE_TIMER_INTMASK_ENA = 1
> > +};
> > +
> > +enum STARFIVE_TIMER_MOD {
> > + STARFIVE_TIMER_MOD_CONTIN = 0,
> > + STARFIVE_TIMER_MOD_SINGLE = 1
> > +};
> > +
> > +enum STARFIVE_TIMER_CTL_EN {
> > + STARFIVE_TIMER_DIS = 0,
> > + STARFIVE_TIMER_ENA = 1
> > +};
> > +
> > +struct starfive_timer_chan_base {
> > + /* Resgister */
> > + unsigned int ctrl;
> > + unsigned int load;
> > + unsigned int enable;
> > + unsigned int reload;
> > + unsigned int value;
> > + unsigned int intclr;
> > + unsigned int intmask;
> > +
> > + unsigned int channel_num; /* timer channel numbers */
> > + unsigned int channel_base[];
> > +};
> > +
> > +struct starfive_clkevt {
> > + struct clock_event_device evt;
> > + struct clk *clk;
> > + char name[20];
> > + int irq;
> > + u32 periodic;
> > + u32 rate;
> > + u32 reload_val;
> > + void __iomem *base;
> > + void __iomem *ctrl;
> > + void __iomem *load;
> > + void __iomem *enable;
> > + void __iomem *reload;
> > + void __iomem *value;
> > + void __iomem *intclr;
> > + void __iomem *intmask;
> > +};
> > +
> > +struct starfive_timer_priv {
> > + struct device *dev;
> > + void __iomem *base;
> > + struct starfive_clkevt clkevt[];
> > +};
> > +
> > +#endif /* __STARFIVE_TIMER_H__ */
>
> Hi Daniel and Thomas,
>
> I have submitted patches for Timer driver. Could you please help to review and give your comments?
> Thanks.
>
> Best regards,
> Xingyu Wu
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/3] clocksource: Add StarFive timer driver
2023-06-02 9:45 ` Xingyu Wu
@ 2023-06-19 16:12 ` Daniel Lezcano
-1 siblings, 0 replies; 20+ messages in thread
From: Daniel Lezcano @ 2023-06-19 16:12 UTC (permalink / raw)
To: Xingyu Wu, Thomas Gleixner
Cc: devicetree, linux-riscv, Krzysztof Kozlowski, Rob Herring,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Philipp Zabel,
Samin Guo, linux-kernel, Conor Dooley
On 02/06/2023 11:45, Xingyu Wu wrote:
> On 2023/3/20 21:54, Xingyu Wu wrote:
>> Add timer driver for the StarFive JH7110 SoC.
>>
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> ---
[ ... ]
> Hi Daniel and Thomas,
>
> I have submitted patches for Timer driver. Could you please help to review and give your comments?
You told in the series you will send a new version
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 2/3] clocksource: Add StarFive timer driver
@ 2023-06-19 16:12 ` Daniel Lezcano
0 siblings, 0 replies; 20+ messages in thread
From: Daniel Lezcano @ 2023-06-19 16:12 UTC (permalink / raw)
To: Xingyu Wu, Thomas Gleixner
Cc: devicetree, linux-riscv, Krzysztof Kozlowski, Rob Herring,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Philipp Zabel,
Samin Guo, linux-kernel, Conor Dooley
On 02/06/2023 11:45, Xingyu Wu wrote:
> On 2023/3/20 21:54, Xingyu Wu wrote:
>> Add timer driver for the StarFive JH7110 SoC.
>>
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> ---
[ ... ]
> Hi Daniel and Thomas,
>
> I have submitted patches for Timer driver. Could you please help to review and give your comments?
You told in the series you will send a new version
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2023-06-19 16:12 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-20 13:54 [PATCH v2 0/3] Add timer driver for StarFive JH7110 RISC-V SoC Xingyu Wu
2023-03-20 13:54 ` Xingyu Wu
2023-03-20 13:54 ` [PATCH v2 1/3] dt-bindings: timer: Add timer for StarFive JH7110 SoC Xingyu Wu
2023-03-20 13:54 ` Xingyu Wu
2023-03-21 7:12 ` Krzysztof Kozlowski
2023-03-21 7:12 ` Krzysztof Kozlowski
2023-03-21 7:14 ` Krzysztof Kozlowski
2023-03-21 7:14 ` Krzysztof Kozlowski
2023-03-21 7:17 ` Xingyu Wu
2023-03-21 7:17 ` Xingyu Wu
2023-03-20 13:54 ` [PATCH v2 2/3] clocksource: Add StarFive timer driver Xingyu Wu
2023-03-20 13:54 ` Xingyu Wu
2023-06-02 9:45 ` Xingyu Wu
2023-06-02 9:45 ` Xingyu Wu
2023-06-02 10:51 ` Emil Renner Berthing
2023-06-02 10:51 ` Emil Renner Berthing
2023-06-19 16:12 ` Daniel Lezcano
2023-06-19 16:12 ` Daniel Lezcano
2023-03-20 13:54 ` [PATCH v2 3/3] riscv: dts: jh7110: starfive: Add timer node Xingyu Wu
2023-03-20 13:54 ` Xingyu Wu
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