From: Harsha Harsha <harsha.harsha@amd.com> To: <herbert@gondor.apana.org.au>, <davem@davemloft.net>, <linux-crypto@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <michals@xilinx.com> Cc: <saratcha@xilinx.com>, <git@amd.com>, Harsha Harsha <harsha.harsha@amd.com>, Dhaval Shah <dhaval.r.shah@amd.com> Subject: [PATCH V2 2/4] firmware: xilinx: Add ZynqMP RSA API for RSA encrypt/decrypt operation Date: Tue, 21 Mar 2023 11:04:44 +0530 [thread overview] Message-ID: <20230321053446.4303-3-harsha.harsha@amd.com> (raw) In-Reply-To: <20230321053446.4303-1-harsha.harsha@amd.com> Add zynqmp_pm_rsa API in the ZynqMP firmware to encrypt and decrypt the datai using RSA hardware engine for ZynqMP. Signed-off-by: Harsha Harsha <harsha.harsha@amd.com> Co-developed-by: Dhaval Shah <dhaval.r.shah@amd.com> Signed-off-by: Dhaval Shah <dhaval.r.shah@amd.com> --- drivers/firmware/xilinx/zynqmp.c | 21 +++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 10ae42a2ae22..d6f73823bab4 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -1426,6 +1426,27 @@ int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags) } EXPORT_SYMBOL_GPL(zynqmp_pm_sha_hash); +/** + * zynqmp_pm_rsa - Access RSA hardware to encrypt/decrypt the data with RSA. + * @address: Address of the data + * @size: Size of the data. + * @flags: + * BIT(0) - Encryption/Decryption + * 0 - RSA decryption with private key + * 1 - RSA encryption with public key. + * + * Return: Returns status, either success or error code. + */ +int zynqmp_pm_rsa(const u64 address, const u32 size, const u32 flags) +{ + u32 lower_32_bits = lower_32_bits(address); + u32 upper_32_bits = upper_32_bits(address); + + return zynqmp_pm_invoke_fn(PM_SECURE_RSA, upper_32_bits, lower_32_bits, + size, flags, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_rsa); + /** * zynqmp_pm_register_notifier() - PM API for register a subsystem * to be notified about specific diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index cd5acfa29cbc..8666b0c3cd66 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -117,6 +117,7 @@ enum pm_api_id { PM_FPGA_GET_STATUS = 23, PM_GET_CHIPID = 24, PM_SECURE_SHA = 26, + PM_SECURE_RSA = 27, PM_PINCTRL_REQUEST = 28, PM_PINCTRL_RELEASE = 29, PM_PINCTRL_GET_FUNCTION = 30, @@ -542,6 +543,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, const enum zynqmp_pm_request_ack ack); int zynqmp_pm_aes_engine(const u64 address, u32 *out); int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); +int zynqmp_pm_rsa(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_get_status(u32 *value); int zynqmp_pm_write_ggs(u32 index, u32 value); @@ -744,6 +746,12 @@ static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size, return -ENODEV; } +static inline int zynqmp_pm_rsa(const u64 address, const u32 size, + const u32 flags) +{ + return -ENODEV; +} + static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags) { -- 2.36.1
WARNING: multiple messages have this Message-ID (diff)
From: Harsha Harsha <harsha.harsha@amd.com> To: <herbert@gondor.apana.org.au>, <davem@davemloft.net>, <linux-crypto@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <michals@xilinx.com> Cc: <saratcha@xilinx.com>, <git@amd.com>, Harsha Harsha <harsha.harsha@amd.com>, Dhaval Shah <dhaval.r.shah@amd.com> Subject: [PATCH V2 2/4] firmware: xilinx: Add ZynqMP RSA API for RSA encrypt/decrypt operation Date: Tue, 21 Mar 2023 11:04:44 +0530 [thread overview] Message-ID: <20230321053446.4303-3-harsha.harsha@amd.com> (raw) In-Reply-To: <20230321053446.4303-1-harsha.harsha@amd.com> Add zynqmp_pm_rsa API in the ZynqMP firmware to encrypt and decrypt the datai using RSA hardware engine for ZynqMP. Signed-off-by: Harsha Harsha <harsha.harsha@amd.com> Co-developed-by: Dhaval Shah <dhaval.r.shah@amd.com> Signed-off-by: Dhaval Shah <dhaval.r.shah@amd.com> --- drivers/firmware/xilinx/zynqmp.c | 21 +++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 10ae42a2ae22..d6f73823bab4 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -1426,6 +1426,27 @@ int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags) } EXPORT_SYMBOL_GPL(zynqmp_pm_sha_hash); +/** + * zynqmp_pm_rsa - Access RSA hardware to encrypt/decrypt the data with RSA. + * @address: Address of the data + * @size: Size of the data. + * @flags: + * BIT(0) - Encryption/Decryption + * 0 - RSA decryption with private key + * 1 - RSA encryption with public key. + * + * Return: Returns status, either success or error code. + */ +int zynqmp_pm_rsa(const u64 address, const u32 size, const u32 flags) +{ + u32 lower_32_bits = lower_32_bits(address); + u32 upper_32_bits = upper_32_bits(address); + + return zynqmp_pm_invoke_fn(PM_SECURE_RSA, upper_32_bits, lower_32_bits, + size, flags, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_rsa); + /** * zynqmp_pm_register_notifier() - PM API for register a subsystem * to be notified about specific diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index cd5acfa29cbc..8666b0c3cd66 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -117,6 +117,7 @@ enum pm_api_id { PM_FPGA_GET_STATUS = 23, PM_GET_CHIPID = 24, PM_SECURE_SHA = 26, + PM_SECURE_RSA = 27, PM_PINCTRL_REQUEST = 28, PM_PINCTRL_RELEASE = 29, PM_PINCTRL_GET_FUNCTION = 30, @@ -542,6 +543,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, const enum zynqmp_pm_request_ack ack); int zynqmp_pm_aes_engine(const u64 address, u32 *out); int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); +int zynqmp_pm_rsa(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_get_status(u32 *value); int zynqmp_pm_write_ggs(u32 index, u32 value); @@ -744,6 +746,12 @@ static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size, return -ENODEV; } +static inline int zynqmp_pm_rsa(const u64 address, const u32 size, + const u32 flags) +{ + return -ENODEV; +} + static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags) { -- 2.36.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-03-21 5:35 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-21 5:34 [PATCH V2 0/4] crypto: Add Xilinx ZynqMP RSA driver support Harsha Harsha 2023-03-21 5:34 ` Harsha Harsha 2023-03-21 5:34 ` [PATCH V2 1/4] firmware: xilinx: Get the SoC family specific data for crypto operation Harsha Harsha 2023-03-21 5:34 ` Harsha Harsha 2023-03-21 5:34 ` Harsha Harsha [this message] 2023-03-21 5:34 ` [PATCH V2 2/4] firmware: xilinx: Add ZynqMP RSA API for RSA encrypt/decrypt operation Harsha Harsha 2023-03-21 5:34 ` [PATCH V2 3/4] crypto: xilinx: Add ZynqMP RSA driver Harsha Harsha 2023-03-21 5:34 ` Harsha Harsha 2023-03-23 8:36 ` kernel test robot 2023-03-23 8:36 ` kernel test robot 2023-03-31 9:03 ` Herbert Xu 2023-03-31 9:03 ` Herbert Xu 2023-04-03 9:47 ` Harsha, Harsha 2023-04-03 9:47 ` Harsha, Harsha 2023-03-21 5:34 ` [PATCH V2 4/4] MAINTAINERS: Add maintainer for Xilinx " Harsha Harsha 2023-03-21 5:34 ` Harsha Harsha
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