* [PATCH v2 00/10] Introduce initial TI's J784S4 support
@ 2023-03-21 14:10 Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 01/10] arm: dts: introduce j784s4 dtbs from linux kernel Hari Nagalla
` (10 more replies)
0 siblings, 11 replies; 22+ messages in thread
From: Hari Nagalla @ 2023-03-21 14:10 UTC (permalink / raw)
To: trini; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
Hello Everyone!
This series will introduce basic support (SD and UART) support for Texas
Instruments J784S4 EVM.
The J784S4 SoC device tree patches are taken from kernel patch submissions
and will be updated as they are accepted and merged to the kernel tree.
All other patches are specific to SPL and u-boot and do not have
dependency on other trees. Appreciate a review for acceptance to u-boot
tree.
Here are some of the salient features of the J784S4 automotive grade
application processor:
The J784S4 SoC belongs to the K3 Multicore SoC architecture
platform, providing advanced system integration in automotive,
ADAS and industrial applications requiring AI at the network edge.
This SoC extends the K3 Jacinto 7 family of SoCs with focus on
raising performance and integration while providing interfaces,
memory architecture and compute performance for multi-sensor, high
concurrency applications.
Some highlights of this SoC are:
* Up to 8 Cortex-A72s, four clusters of lockstep capable dual Cortex-R5F MCUs,
4 C7x floating point vector DSPs with Matrix Multiply Accelerator(MMA) for
deep learning and CNN.
* 3D GPU: Automotive grade IMG BXS-4-64
* Vision Processing Accelerator (VPAC) with image signal processor and Depth
and Motion Processing Accelerator (DMPAC)
* Three CSI2.0 4L RX plus two CSI2.0 4L TX, two DSI Tx, one eDP/DP and one
DPI interface.
* Integrated gigabit ethernet switch, up to 8 ports (TDA4VH), two ports
support 10Gb USXGMII; Two 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role
device subsystems, Up to 20 MCANs, among other peripherals.
See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022)
for further details: http://www.ti.com/lit/zip/spruj52
In addtion, the J784S4 EVM board is designed for TI J784S4 SoC. It
supports the following interfaces:
* 32 GB DDR4 RAM
* x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode
* x1 Input Audio Jack, x1 Output Audio Jack
* x1 USB2.0 Hub with two Type A host and x1 USB 3.1 Type-C Port
* x2 4L PCIe connector
* x1 UHS-1 capable micro-SD card slot
* 512 Mbit OSPI flash, 1 Gbit Octal NAND flash, 512 Mbit QSPI flash,
UFS flash.
* x6 UART through UART-USB bridge
* XDS110 for onboard JTAG debug using USB
* Temperature sensors, user push buttons and LEDs
* 40-pin User Expansion Connector
* x2 ENET Expansion Connector, x1 GESI expander, x2 Display connector
* x1 15-pin CSI header
* x6 MCAN instances
Schematics: https://www.ti.com/lit/zip/sprr458
bootlog: https://paste.sr.ht/~hnagalla/f14840abc854519f912923662f1fdc8075d92107
Changes in v2:
- Refactored environement scripts to 'j784s4.env' and removed scripts not
needed for basic board bootup.
- Imported the J7874S4 basic device tree files from v6.2 linux kernel.
- Moved j784s4 clock definitions and clock data into one patch/commit.
- coalesce board commits into one commit.
Hari Nagalla (10):
arm: dts: introduce j784s4 dtbs from linux kernel
arm: dts: introduce j784s4 u-boot dtbs
arm: K3: Add basic support for J784S4 SoC definition
drivers: dma: Add support for J784S4
clk: clk-k3: Add support for J784S4 SoC
power: domain: ti: Add support for J784S4 SoC
ram: k3-ddrss: Add support for J784S4 SoC
soc: ti: k3-socinfo: Add entry for J784S4 SoC
board: ti: j784s4: Add board support for J784S4 SoC
dt-bindings: ti-serdes-mux: Add defines for J784S4 SoC
arch/arm/dts/Makefile | 2 +
arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi | 8757 ++++++++++++++++
arch/arm/dts/k3-j784s4-ddr.dtsi | 8858 +++++++++++++++++
arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 135 +
arch/arm/dts/k3-j784s4-evm.dts | 196 +
arch/arm/dts/k3-j784s4-main.dtsi | 1007 ++
arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi | 311 +
arch/arm/dts/k3-j784s4-r5-evm.dts | 209 +
arch/arm/dts/k3-j784s4.dtsi | 287 +
arch/arm/mach-k3/Kconfig | 16 +-
arch/arm/mach-k3/Makefile | 2 +
arch/arm/mach-k3/arm64-mmu.c | 41 +
arch/arm/mach-k3/include/mach/hardware.h | 4 +
.../mach-k3/include/mach/j784s4_hardware.h | 41 +
arch/arm/mach-k3/include/mach/j784s4_spl.h | 46 +
arch/arm/mach-k3/include/mach/spl.h | 6 +-
arch/arm/mach-k3/j784s4/Makefile | 5 +
arch/arm/mach-k3/j784s4/clk-data.c | 428 +
arch/arm/mach-k3/j784s4/dev-data.c | 97 +
arch/arm/mach-k3/j784s4_init.c | 319 +
board/ti/j784s4/Kconfig | 61 +
board/ti/j784s4/MAINTAINERS | 7 +
board/ti/j784s4/Makefile | 8 +
board/ti/j784s4/evm.c | 105 +
board/ti/j784s4/j784s4.env | 108 +
configs/j784s4_evm_a72_defconfig | 213 +
configs/j784s4_evm_r5_defconfig | 179 +
drivers/clk/ti/clk-k3.c | 6 +
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-psil-j784s4.c | 166 +
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 2 +
drivers/firmware/ti_sci_static_data.h | 35 +
drivers/power/domain/ti-power-domain.c | 6 +
drivers/ram/Kconfig | 2 +-
drivers/soc/soc_ti_k3.c | 6 +
include/configs/j784s4_evm.h | 49 +
include/dt-bindings/mux/ti-serdes.h | 62 +
include/dt-bindings/pinctrl/k3.h | 3 +
include/k3-clk.h | 1 +
include/k3-dev.h | 1 +
41 files changed, 21781 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-ddr.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-evm.dts
create mode 100644 arch/arm/dts/k3-j784s4-main.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-r5-evm.dts
create mode 100644 arch/arm/dts/k3-j784s4.dtsi
create mode 100644 arch/arm/mach-k3/include/mach/j784s4_hardware.h
create mode 100644 arch/arm/mach-k3/include/mach/j784s4_spl.h
create mode 100644 arch/arm/mach-k3/j784s4/Makefile
create mode 100644 arch/arm/mach-k3/j784s4/clk-data.c
create mode 100644 arch/arm/mach-k3/j784s4/dev-data.c
create mode 100644 arch/arm/mach-k3/j784s4_init.c
create mode 100644 board/ti/j784s4/Kconfig
create mode 100644 board/ti/j784s4/MAINTAINERS
create mode 100644 board/ti/j784s4/Makefile
create mode 100644 board/ti/j784s4/evm.c
create mode 100644 board/ti/j784s4/j784s4.env
create mode 100644 configs/j784s4_evm_a72_defconfig
create mode 100644 configs/j784s4_evm_r5_defconfig
create mode 100644 drivers/dma/ti/k3-psil-j784s4.c
create mode 100644 include/configs/j784s4_evm.h
--
2.17.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v2 01/10] arm: dts: introduce j784s4 dtbs from linux kernel
2023-03-21 14:10 [PATCH v2 00/10] Introduce initial TI's J784S4 support Hari Nagalla
@ 2023-03-21 14:10 ` Hari Nagalla
2023-03-21 15:57 ` Bryan Brattlof
2023-04-14 5:46 ` Siddharth Vadapalli
2023-03-21 14:10 ` [PATCH v2 02/10] arm: dts: introduce j784s4 u-boot dtbs Hari Nagalla
` (9 subsequent siblings)
10 siblings, 2 replies; 22+ messages in thread
From: Hari Nagalla @ 2023-03-21 14:10 UTC (permalink / raw)
To: trini; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
Introduce the basic j784s4 SoC dtbs from the linux kernel along with
the new j784s4 specific pinmux definitions that we will use to generate
the dtbs for the u-boot-spl and u-boot binaries.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
---
arch/arm/dts/k3-j784s4-evm.dts | 196 +++++
arch/arm/dts/k3-j784s4-main.dtsi | 1007 ++++++++++++++++++++++++
arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi | 311 ++++++++
arch/arm/dts/k3-j784s4.dtsi | 287 +++++++
include/dt-bindings/pinctrl/k3.h | 3 +
5 files changed, 1804 insertions(+)
create mode 100644 arch/arm/dts/k3-j784s4-evm.dts
create mode 100644 arch/arm/dts/k3-j784s4-main.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
create mode 100644 arch/arm/dts/k3-j784s4.dtsi
diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts
new file mode 100644
index 0000000000..8cd4a7ecc1
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-evm.dts
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "k3-j784s4.dtsi"
+
+/ {
+ compatible = "ti,j784s4-evm", "ti,j784s4";
+ model = "Texas Instruments J784S4 EVM";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ aliases {
+ serial2 = &main_uart8;
+ mmc1 = &main_sdhci1;
+ i2c0 = &main_i2c0;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 32G RAM */
+ reg = <0x00 0x80000000 0x00 0x80000000>,
+ <0x08 0x80000000 0x07 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ no-map;
+ };
+ };
+
+ evm_12v0: regulator-evm12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: regulator-vsys3v3 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: regulator-vsys5v0 {
+ /* Output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: regulator-sd {
+ /* Output of TPS22918 */
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv: regulator-TLV71033 {
+ /* Output of TLV71033 */
+ compatible = "regulator-gpio";
+ regulator-name = "tlv71033";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_pins_default>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ vin-supply = <&vsys_5v0>;
+ gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
+ };
+};
+
+&main_pmx0 {
+ main_uart8_pins_default: main-uart8-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */
+ J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */
+ J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
+ J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
+ >;
+ };
+
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
+ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
+ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
+ J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */
+ J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
+ J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
+ J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
+ J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
+ J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
+ >;
+ };
+
+ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
+ >;
+ };
+};
+
+&main_uart8 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart8_pins_default>;
+};
+
+&main_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+
+ clock-frequency = <400000>;
+
+ exp1: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ",
+ "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ",
+ "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#",
+ "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3",
+ "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ";
+ };
+
+ exp2: gpio@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN",
+ "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0",
+ "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#",
+ "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ",
+ "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1",
+ "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ",
+ "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ",
+ "USER_INPUT1", "USER_LED1", "USER_LED2";
+ };
+};
+
+&main_sdhci1 {
+ /* SD card */
+ status = "okay";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ pinctrl-names = "default";
+ disable-wp;
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv>;
+};
+
+&main_gpio0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/k3-j784s4-main.dtsi b/arch/arm/dts/k3-j784s4-main.dtsi
new file mode 100644
index 0000000000..7edf324ac1
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-main.dtsi
@@ -0,0 +1,1007 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J784S4 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+ msmc_ram: sram@70000000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x70000000 0x00 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x70000000 0x800000>;
+
+ atf-sram@0 {
+ reg = <0x00 0x20000>;
+ };
+
+ tifs-sram@1f0000 {
+ reg = <0x1f0000 0x10000>;
+ };
+
+ l3cache-sram@200000 {
+ reg = <0x200000 0x200000>;
+ };
+ };
+
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
+ <0x00 0x01900000 0x00 0x100000>, /* GICR */
+ <0x00 0x6f000000 0x00 0x2000>, /* GICC */
+ <0x00 0x6f010000 0x00 0x1000>, /* GICH */
+ <0x00 0x6f020000 0x00 0x2000>; /* GICV */
+
+ /* vcpumntirq: virtual CPU interface maintenance interrupt */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: msi-controller@1820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ main_gpio_intr: interrupt-controller@a00000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x00a00000 0x00 0x800>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <10>;
+ ti,interrupt-ranges = <8 360 56>;
+ };
+
+ main_pmx0: pinctrl@11c000 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x11c000 0x00 0x120>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ main_uart0: serial@2800000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x200>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 146 0>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x200>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 388 0>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_uart2: serial@2820000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x200>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 389 0>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_uart3: serial@2830000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02830000 0x00 0x200>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 390 0>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_uart4: serial@2840000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02840000 0x00 0x200>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 391 0>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_uart5: serial@2850000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02850000 0x00 0x200>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 392 0>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_uart6: serial@2860000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02860000 0x00 0x200>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 393 0>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_uart7: serial@2870000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02870000 0x00 0x200>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 394 0>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_uart8: serial@2880000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02880000 0x00 0x200>;
+ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 395 0>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_uart9: serial@2890000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02890000 0x00 0x200>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 396 0>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_gpio0: gpio@600000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00600000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <145>, <146>, <147>, <148>, <149>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <66>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 163 0>;
+ clock-names = "gpio";
+ status = "disabled";
+ };
+
+ main_gpio2: gpio@610000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00610000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <154>, <155>, <156>, <157>, <158>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <66>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 164 0>;
+ clock-names = "gpio";
+ status = "disabled";
+ };
+
+ main_gpio4: gpio@620000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00620000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <163>, <164>, <165>, <166>, <167>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <66>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 165 0>;
+ clock-names = "gpio";
+ status = "disabled";
+ };
+
+ main_gpio6: gpio@630000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00630000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <172>, <173>, <174>, <175>, <176>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <66>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 166 0>;
+ clock-names = "gpio";
+ status = "disabled";
+ };
+
+ main_i2c0: i2c@2000000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02000000 0x00 0x100>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 270 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_i2c1: i2c@2010000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02010000 0x00 0x100>;
+ interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 271 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_i2c2: i2c@2020000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02020000 0x00 0x100>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 272 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_i2c3: i2c@2030000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02030000 0x00 0x100>;
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 273 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_i2c4: i2c@2040000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02040000 0x00 0x100>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 274 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_i2c5: i2c@2050000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02050000 0x00 0x100>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 275 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_i2c6: i2c@2060000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x02060000 0x00 0x100>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 276 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ main_sdhci0: mmc@4f80000 {
+ compatible = "ti,j721e-sdhci-8bit";
+ reg = <0x00 0x04f80000 0x00 0x1000>,
+ <0x00 0x04f88000 0x00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 140 1>, <&k3_clks 140 2>;
+ clock-names = "clk_ahb", "clk_xin";
+ assigned-clocks = <&k3_clks 140 2>;
+ assigned-clock-parents = <&k3_clks 140 3>;
+ bus-width = <8>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-ddr52 = <0x6>;
+ ti,otap-del-sel-hs200 = <0x8>;
+ ti,otap-del-sel-hs400 = <0x5>;
+ ti,itap-del-sel-legacy = <0x10>;
+ ti,itap-del-sel-mmc-hs = <0xa>;
+ ti,strobe-sel = <0x77>;
+ ti,clkbuf-sel = <0x7>;
+ ti,trm-icp = <0x8>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ dma-coherent;
+ no-1-8-v;
+ status = "disabled";
+ };
+
+ main_sdhci1: mmc@4fb0000 {
+ compatible = "ti,j721e-sdhci-4bit";
+ reg = <0x00 0x04fb0000 0x00 0x1000>,
+ <0x00 0x04fb8000 0x00 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 141 3>, <&k3_clks 141 4>;
+ clock-names = "clk_ahb", "clk_xin";
+ assigned-clocks = <&k3_clks 141 4>;
+ assigned-clock-parents = <&k3_clks 141 5>;
+ bus-width = <4>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x5>;
+ ti,otap-del-sel-ddr50 = <0xc>;
+ ti,itap-del-sel-legacy = <0x0>;
+ ti,itap-del-sel-sd-hs = <0x0>;
+ ti,itap-del-sel-sdr12 = <0x0>;
+ ti,itap-del-sel-sdr25 = <0x0>;
+ ti,clkbuf-sel = <0x7>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
+ sdhci-caps-mask = <0x00000003 0x00000000>;
+ no-1-8-v;
+ status = "disabled";
+ };
+
+ main_navss: bus@30000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+ dma-coherent;
+ dma-ranges;
+
+ main_navss_intr: interrupt-controller@310e0000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x310e0000 0x00 0x4000>;
+ ti,intr-trigger-type = <4>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <283>;
+ ti,interrupt-ranges = <0 64 64>,
+ <64 448 64>,
+ <128 672 64>;
+ };
+
+ main_udmass_inta: msi-controller@33d00000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x33d00000 0x00 0x100000>;
+ interrupt-controller;
+ #interrupt-cells = <0>;
+ interrupt-parent = <&main_navss_intr>;
+ msi-controller;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <321>;
+ ti,interrupt-ranges = <0 0 256>;
+ };
+
+ secure_proxy_main: mailbox@32c00000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x32c00000 0x00 0x100000>,
+ <0x00 0x32400000 0x00 0x100000>,
+ <0x00 0x32800000 0x00 0x100000>;
+ interrupt-names = "rx_011";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ hwspinlock: hwlock@30e00000 {
+ compatible = "ti,am654-hwspinlock";
+ reg = <0x00 0x30e00000 0x00 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ mailbox0_cluster0: mailbox@31f80000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f80000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster1: mailbox@31f81000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f81000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster2: mailbox@31f82000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f82000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster3: mailbox@31f83000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f83000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster4: mailbox@31f84000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f84000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster5: mailbox@31f85000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f85000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster6: mailbox@31f86000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f86000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster7: mailbox@31f87000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f87000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster8: mailbox@31f88000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f88000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster9: mailbox@31f89000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f89000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster10: mailbox@31f8a000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8a000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster11: mailbox@31f8b000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8b000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox1_cluster0: mailbox@31f90000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f90000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox1_cluster1: mailbox@31f91000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f91000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox1_cluster2: mailbox@31f92000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f92000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox1_cluster3: mailbox@31f93000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f93000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox1_cluster4: mailbox@31f94000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f94000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox1_cluster5: mailbox@31f95000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f95000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox1_cluster6: mailbox@31f96000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f96000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox1_cluster7: mailbox@31f97000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f97000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox1_cluster8: mailbox@31f98000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f98000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox1_cluster9: mailbox@31f99000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f99000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox1_cluster10: mailbox@31f9a000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f9a000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ mailbox1_cluster11: mailbox@31f9b000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f9b000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&main_navss_intr>;
+ status = "disabled";
+ };
+
+ main_ringacc: ringacc@3c000000 {
+ compatible = "ti,am654-navss-ringacc";
+ reg = <0x00 0x3c000000 0x00 0x400000>,
+ <0x00 0x38000000 0x00 0x400000>,
+ <0x00 0x31120000 0x00 0x100>,
+ <0x00 0x33000000 0x00 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ ti,num-rings = <1024>;
+ ti,sci-rm-range-gp-rings = <0x1>;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <315>;
+ msi-parent = <&main_udmass_inta>;
+ };
+
+ main_udmap: dma-controller@31150000 {
+ compatible = "ti,j721e-navss-main-udmap";
+ reg = <0x00 0x31150000 0x00 0x100>,
+ <0x00 0x34000000 0x00 0x80000>,
+ <0x00 0x35000000 0x00 0x200000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt";
+ msi-parent = <&main_udmass_inta>;
+ #dma-cells = <1>;
+
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <319>;
+ ti,ringacc = <&main_ringacc>;
+
+ ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+ <0x0f>, /* TX_HCHAN */
+ <0x10>; /* TX_UHCHAN */
+ ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+ <0x0b>, /* RX_HCHAN */
+ <0x0c>; /* RX_UHCHAN */
+ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+ };
+
+ cpts@310d0000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x00 0x310d0000 0x00 0x400>;
+ reg-names = "cpts";
+ clocks = <&k3_clks 282 0>;
+ clock-names = "cpts";
+ assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */
+ assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */
+ interrupts-extended = <&main_navss_intr 391>;
+ interrupt-names = "cpts";
+ ti,cpts-periodic-outputs = <6>;
+ ti,cpts-ext-ts-inputs = <8>;
+ };
+ };
+
+ main_mcan0: can@2701000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02701000 0x00 0x200>,
+ <0x00 0x02708000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 245 6>, <&k3_clks 245 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan1: can@2711000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02711000 0x00 0x200>,
+ <0x00 0x02718000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 246 6>, <&k3_clks 246 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan2: can@2721000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02721000 0x00 0x200>,
+ <0x00 0x02728000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 247 6>, <&k3_clks 247 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan3: can@2731000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02731000 0x00 0x200>,
+ <0x00 0x02738000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 248 6>, <&k3_clks 248 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan4: can@2741000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02741000 0x00 0x200>,
+ <0x00 0x02748000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 249 6>, <&k3_clks 249 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan5: can@2751000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02751000 0x00 0x200>,
+ <0x00 0x02758000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 250 6>, <&k3_clks 250 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan6: can@2761000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02761000 0x00 0x200>,
+ <0x00 0x02768000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 251 6>, <&k3_clks 251 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan7: can@2771000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02771000 0x00 0x200>,
+ <0x00 0x02778000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 252 6>, <&k3_clks 252 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan8: can@2781000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02781000 0x00 0x200>,
+ <0x00 0x02788000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 253 6>, <&k3_clks 253 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan9: can@2791000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02791000 0x00 0x200>,
+ <0x00 0x02798000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 254 6>, <&k3_clks 254 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan10: can@27a1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027a1000 0x00 0x200>,
+ <0x00 0x027a8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 255 6>, <&k3_clks 255 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan11: can@27b1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027b1000 0x00 0x200>,
+ <0x00 0x027b8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 256 6>, <&k3_clks 256 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan12: can@27c1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027c1000 0x00 0x200>,
+ <0x00 0x027c8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 257 6>, <&k3_clks 257 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan13: can@27d1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x027d1000 0x00 0x200>,
+ <0x00 0x027d8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 258 6>, <&k3_clks 258 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan14: can@2681000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02681000 0x00 0x200>,
+ <0x00 0x02688000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 259 6>, <&k3_clks 259 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan15: can@2691000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x02691000 0x00 0x200>,
+ <0x00 0x02698000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 260 6>, <&k3_clks 260 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan16: can@26a1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x026a1000 0x00 0x200>,
+ <0x00 0x026a8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 261 6>, <&k3_clks 261 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ main_mcan17: can@26b1000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x026b1000 0x00 0x200>,
+ <0x00 0x026b8000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 262 6>, <&k3_clks 262 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
new file mode 100644
index 0000000000..93952af618
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu_wakeup {
+ sms: system-controller@44083000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+
+ mbox-names = "rx", "tx";
+
+ mboxes = <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
+
+ reg-names = "debug_messages";
+ reg = <0x00 0x44083000 0x00 0x1000>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clock-controller {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ chipid@43000014 {
+ compatible = "ti,am654-chipid";
+ reg = <0x00 0x43000014 0x00 0x4>;
+ };
+
+ mcu_ram: sram@41c00000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x41c00000 0x00 0x100000>;
+ ranges = <0x00 0x00 0x41c00000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ wkup_pmx0: pinctrl@4301c000 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c000 0x00 0x178>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ wkup_gpio_intr: interrupt-controller@42200000 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x42200000 0x00 0x400>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ #interrupt-cells = <1>;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <177>;
+ ti,interrupt-ranges = <16 928 16>;
+ };
+
+ mcu_conf: syscon@40f00000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00 0x40f00000 0x00 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x40f00000 0x20000>;
+
+ phy_gmii_sel: phy@4040 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4040 0x4>;
+ #phy-cells = <1>;
+ };
+ };
+
+ wkup_uart0: serial@42300000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x42300000 0x00 0x200>;
+ interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 397 0>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcu_uart0: serial@40a00000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x40a00000 0x00 0x200>;
+ interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ clocks = <&k3_clks 149 0>;
+ clock-names = "fclk";
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ wkup_gpio0: gpio@42110000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x42110000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&wkup_gpio_intr>;
+ interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <89>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 167 0>;
+ clock-names = "gpio";
+ status = "disabled";
+ };
+
+ wkup_gpio1: gpio@42100000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x42100000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&wkup_gpio_intr>;
+ interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <89>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 168 0>;
+ clock-names = "gpio";
+ status = "disabled";
+ };
+
+ wkup_i2c0: i2c@42120000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x42120000 0x00 0x100>;
+ interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 279 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcu_i2c0: i2c@40b00000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x40b00000 0x00 0x100>;
+ interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 277 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcu_i2c1: i2c@40b10000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x40b10000 0x00 0x100>;
+ interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 278 2>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
+ };
+
+ mcu_mcan0: can@40528000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x40528000 0x00 0x200>,
+ <0x00 0x40500000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 263 6>, <&k3_clks 263 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ mcu_mcan1: can@40568000 {
+ compatible = "bosch,m_can";
+ reg = <0x00 0x40568000 0x00 0x200>,
+ <0x00 0x40540000 0x00 0x8000>;
+ reg-names = "m_can", "message_ram";
+ power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 264 6>, <&k3_clks 264 1>;
+ clock-names = "hclk", "cclk";
+ interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ mcu_navss: bus@28380000{
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
+ dma-coherent;
+ dma-ranges;
+
+ mcu_ringacc: ringacc@2b800000 {
+ compatible = "ti,am654-navss-ringacc";
+ reg = <0x00 0x2b800000 0x00 0x400000>,
+ <0x00 0x2b000000 0x00 0x400000>,
+ <0x00 0x28590000 0x00 0x100>,
+ <0x00 0x2a500000 0x00 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ ti,num-rings = <286>;
+ ti,sci-rm-range-gp-rings = <0x1>;
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <328>;
+ msi-parent = <&main_udmass_inta>;
+ };
+
+ mcu_udmap: dma-controller@285c0000 {
+ compatible = "ti,j721e-navss-mcu-udmap";
+ reg = <0x00 0x285c0000 0x00 0x100>,
+ <0x00 0x2a800000 0x00 0x40000>,
+ <0x00 0x2aa00000 0x00 0x40000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt";
+ msi-parent = <&main_udmass_inta>;
+ #dma-cells = <1>;
+
+ ti,sci = <&sms>;
+ ti,sci-dev-id = <329>;
+ ti,ringacc = <&mcu_ringacc>;
+ ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+ <0x0f>; /* TX_HCHAN */
+ ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+ <0x0b>; /* RX_HCHAN */
+ ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+ };
+ };
+
+ mcu_cpsw: ethernet@46000000 {
+ compatible = "ti,j721e-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x00 0x46000000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
+ dma-coherent;
+ clocks = <&k3_clks 63 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&mcu_udmap 0xf000>,
+ <&mcu_udmap 0xf001>,
+ <&mcu_udmap 0xf002>,
+ <&mcu_udmap 0xf003>,
+ <&mcu_udmap 0xf004>,
+ <&mcu_udmap 0xf005>,
+ <&mcu_udmap 0xf006>,
+ <&mcu_udmap 0xf007>,
+ <&mcu_udmap 0x7000>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mcu_cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ ti,syscon-efuse = <&mcu_conf 0x200>;
+ phys = <&phy_gmii_sel 1>;
+ };
+ };
+
+ davinci_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 63 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+
+ cpts@3d000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
+ clocks = <&k3_clks 63 3>;
+ clock-names = "cpts";
+ assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */
+ assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */
+ interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j784s4.dtsi b/arch/arm/dts/k3-j784s4.dtsi
new file mode 100644
index 0000000000..3eb0d05689
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4.dtsi
@@ -0,0 +1,287 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J784S4 SoC Family
+ *
+ * TRM (SPRUJ43 JULY 2022) : http://www.ti.com/lit/zip/spruj52
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+/ {
+ model = "Texas Instruments K3 J784S4 SoC";
+ compatible = "ti,j784s4";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1: cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+
+ core1 {
+ cpu = <&cpu5>;
+ };
+
+ core2 {
+ cpu = <&cpu6>;
+ };
+
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a72";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a72";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a72";
+ reg = <0x002>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a72";
+ reg = <0x003>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu4: cpu@100 {
+ compatible = "arm,cortex-a72";
+ reg = <0x100>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_1>;
+ };
+
+ cpu5: cpu@101 {
+ compatible = "arm,cortex-a72";
+ reg = <0x101>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_1>;
+ };
+
+ cpu6: cpu@102 {
+ compatible = "arm,cortex-a72";
+ reg = <0x102>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_1>;
+ };
+
+ cpu7: cpu@103 {
+ compatible = "arm,cortex-a72";
+ reg = <0x103>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&L2_1>;
+ };
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ next-level-cache = <&msmc_l3>;
+ };
+
+ L2_1: l2-cache1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x200000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ next-level-cache = <&msmc_l3>;
+ };
+
+ msmc_l3: l3-cache0 {
+ compatible = "cache";
+ cache-level = <3>;
+ cache-unified;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ a72_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a72-pmu";
+ /* Recommendation from GIC500 TRM Table A.3 */
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cbass_main: bus@100000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
+ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
+ <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
+ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
+ <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
+ <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
+ <0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */
+ <0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */
+ <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
+ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
+ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
+ <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
+
+ /* MCUSS_WKUP Range */
+ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
+ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
+
+ cbass_mcu_wakeup: bus@28380000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
+ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
+ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
+ };
+ };
+};
+
+/* Now include peripherals from each bus segment */
+#include "k3-j784s4-main.dtsi"
+#include "k3-j784s4-mcu-wakeup.dtsi"
diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h
index e8418318eb..49321c94d7 100644
--- a/include/dt-bindings/pinctrl/k3.h
+++ b/include/dt-bindings/pinctrl/k3.h
@@ -47,4 +47,7 @@
#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 02/10] arm: dts: introduce j784s4 u-boot dtbs
2023-03-21 14:10 [PATCH v2 00/10] Introduce initial TI's J784S4 support Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 01/10] arm: dts: introduce j784s4 dtbs from linux kernel Hari Nagalla
@ 2023-03-21 14:10 ` Hari Nagalla
2023-03-21 15:52 ` Tom Rini
2023-04-14 8:32 ` Siddharth Vadapalli
2023-03-21 14:10 ` [PATCH v2 03/10] arm: K3: Add basic support for J784S4 SoC definition Hari Nagalla
` (8 subsequent siblings)
10 siblings, 2 replies; 22+ messages in thread
From: Hari Nagalla @ 2023-03-21 14:10 UTC (permalink / raw)
To: trini; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
Introduce the base dts files needed for u-boot or to augment the linux
dtbs for use in the u-boot-spl and u-boot binaries.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi | 8757 +++++++++++++++++
arch/arm/dts/k3-j784s4-ddr.dtsi | 8858 ++++++++++++++++++
arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 135 +
arch/arm/dts/k3-j784s4-r5-evm.dts | 209 +
5 files changed, 17961 insertions(+)
create mode 100644 arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-ddr.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
create mode 100644 arch/arm/dts/k3-j784s4-r5-evm.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7a577deb50..7690fd21db 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1264,6 +1264,8 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
k3-am68-sk-r5-base-board.dtb\
k3-j721s2-common-proc-board.dtb\
k3-j721s2-r5-common-proc-board.dtb
+dtb-$(CONFIG_SOC_K3_J784S4) += k3-j784s4-evm.dtb\
+ k3-j784s4-r5-evm.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
k3-am642-sk.dtb \
diff --git a/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
new file mode 100644
index 0000000000..31429e31d1
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
@@ -0,0 +1,8757 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.0
+ * This file was generated on 05/23/2022
+*/
+
+#define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FREQUENCY_0 27500000
+#define DDRSS_PLL_FREQUENCY_1 1066500000
+#define DDRSS_PLL_FREQUENCY_2 1066500000
+
+#define MULTI_DDR_CFG_INTRLV_GRAN 0
+#define MULTI_DDR_CFG_INTRLV_SIZE 12
+#define MULTI_DDR_CFG_ECC_ENABLE 0
+#define MULTI_DDR_CFG_HYBRID_SELECT 24
+#define MULTI_DDR_CFG_EMIFS_ACTIVE 15
+
+#define DDRSS0_CTL_00_DATA 0x00000B00
+#define DDRSS0_CTL_01_DATA 0x00000000
+#define DDRSS0_CTL_02_DATA 0x00000000
+#define DDRSS0_CTL_03_DATA 0x00000000
+#define DDRSS0_CTL_04_DATA 0x00000000
+#define DDRSS0_CTL_05_DATA 0x00000000
+#define DDRSS0_CTL_06_DATA 0x00000000
+#define DDRSS0_CTL_07_DATA 0x00002AF8
+#define DDRSS0_CTL_08_DATA 0x0001ADAF
+#define DDRSS0_CTL_09_DATA 0x00000005
+#define DDRSS0_CTL_10_DATA 0x0000006E
+#define DDRSS0_CTL_11_DATA 0x000681C8
+#define DDRSS0_CTL_12_DATA 0x004111C9
+#define DDRSS0_CTL_13_DATA 0x00000005
+#define DDRSS0_CTL_14_DATA 0x000010A9
+#define DDRSS0_CTL_15_DATA 0x000681C8
+#define DDRSS0_CTL_16_DATA 0x004111C9
+#define DDRSS0_CTL_17_DATA 0x00000005
+#define DDRSS0_CTL_18_DATA 0x000010A9
+#define DDRSS0_CTL_19_DATA 0x01010000
+#define DDRSS0_CTL_20_DATA 0x02011001
+#define DDRSS0_CTL_21_DATA 0x02010000
+#define DDRSS0_CTL_22_DATA 0x00020100
+#define DDRSS0_CTL_23_DATA 0x0000000B
+#define DDRSS0_CTL_24_DATA 0x0000001C
+#define DDRSS0_CTL_25_DATA 0x00000000
+#define DDRSS0_CTL_26_DATA 0x00000000
+#define DDRSS0_CTL_27_DATA 0x03020200
+#define DDRSS0_CTL_28_DATA 0x00005656
+#define DDRSS0_CTL_29_DATA 0x00100000
+#define DDRSS0_CTL_30_DATA 0x00000000
+#define DDRSS0_CTL_31_DATA 0x00000000
+#define DDRSS0_CTL_32_DATA 0x00000000
+#define DDRSS0_CTL_33_DATA 0x00000000
+#define DDRSS0_CTL_34_DATA 0x040C0000
+#define DDRSS0_CTL_35_DATA 0x12481248
+#define DDRSS0_CTL_36_DATA 0x00050804
+#define DDRSS0_CTL_37_DATA 0x09040008
+#define DDRSS0_CTL_38_DATA 0x15000204
+#define DDRSS0_CTL_39_DATA 0x1760008B
+#define DDRSS0_CTL_40_DATA 0x1500422B
+#define DDRSS0_CTL_41_DATA 0x1760008B
+#define DDRSS0_CTL_42_DATA 0x2000422B
+#define DDRSS0_CTL_43_DATA 0x000A0A09
+#define DDRSS0_CTL_44_DATA 0x0400078A
+#define DDRSS0_CTL_45_DATA 0x1E161104
+#define DDRSS0_CTL_46_DATA 0x10012458
+#define DDRSS0_CTL_47_DATA 0x1E161110
+#define DDRSS0_CTL_48_DATA 0x10012458
+#define DDRSS0_CTL_49_DATA 0x02030410
+#define DDRSS0_CTL_50_DATA 0x2C040500
+#define DDRSS0_CTL_51_DATA 0x08292C29
+#define DDRSS0_CTL_52_DATA 0x14000E0A
+#define DDRSS0_CTL_53_DATA 0x04010A0A
+#define DDRSS0_CTL_54_DATA 0x01010004
+#define DDRSS0_CTL_55_DATA 0x04545408
+#define DDRSS0_CTL_56_DATA 0x04313104
+#define DDRSS0_CTL_57_DATA 0x00003131
+#define DDRSS0_CTL_58_DATA 0x00010100
+#define DDRSS0_CTL_59_DATA 0x03010000
+#define DDRSS0_CTL_60_DATA 0x00001508
+#define DDRSS0_CTL_61_DATA 0x000000CE
+#define DDRSS0_CTL_62_DATA 0x0000032B
+#define DDRSS0_CTL_63_DATA 0x00002073
+#define DDRSS0_CTL_64_DATA 0x0000032B
+#define DDRSS0_CTL_65_DATA 0x00002073
+#define DDRSS0_CTL_66_DATA 0x00000005
+#define DDRSS0_CTL_67_DATA 0x00050000
+#define DDRSS0_CTL_68_DATA 0x00CB0012
+#define DDRSS0_CTL_69_DATA 0x00CB0408
+#define DDRSS0_CTL_70_DATA 0x00400408
+#define DDRSS0_CTL_71_DATA 0x00120103
+#define DDRSS0_CTL_72_DATA 0x00100005
+#define DDRSS0_CTL_73_DATA 0x2F080010
+#define DDRSS0_CTL_74_DATA 0x0505012F
+#define DDRSS0_CTL_75_DATA 0x0401030A
+#define DDRSS0_CTL_76_DATA 0x041E100B
+#define DDRSS0_CTL_77_DATA 0x100B0401
+#define DDRSS0_CTL_78_DATA 0x0001041E
+#define DDRSS0_CTL_79_DATA 0x00160016
+#define DDRSS0_CTL_80_DATA 0x033B033B
+#define DDRSS0_CTL_81_DATA 0x033B033B
+#define DDRSS0_CTL_82_DATA 0x03050505
+#define DDRSS0_CTL_83_DATA 0x03010303
+#define DDRSS0_CTL_84_DATA 0x200B100B
+#define DDRSS0_CTL_85_DATA 0x04041004
+#define DDRSS0_CTL_86_DATA 0x200B100B
+#define DDRSS0_CTL_87_DATA 0x04041004
+#define DDRSS0_CTL_88_DATA 0x03010000
+#define DDRSS0_CTL_89_DATA 0x00010000
+#define DDRSS0_CTL_90_DATA 0x00000000
+#define DDRSS0_CTL_91_DATA 0x00000000
+#define DDRSS0_CTL_92_DATA 0x01000000
+#define DDRSS0_CTL_93_DATA 0x80104002
+#define DDRSS0_CTL_94_DATA 0x00000000
+#define DDRSS0_CTL_95_DATA 0x00040005
+#define DDRSS0_CTL_96_DATA 0x00000000
+#define DDRSS0_CTL_97_DATA 0x00050000
+#define DDRSS0_CTL_98_DATA 0x00000004
+#define DDRSS0_CTL_99_DATA 0x00000000
+#define DDRSS0_CTL_100_DATA 0x00040005
+#define DDRSS0_CTL_101_DATA 0x00000000
+#define DDRSS0_CTL_102_DATA 0x00003380
+#define DDRSS0_CTL_103_DATA 0x00003380
+#define DDRSS0_CTL_104_DATA 0x00003380
+#define DDRSS0_CTL_105_DATA 0x00003380
+#define DDRSS0_CTL_106_DATA 0x00003380
+#define DDRSS0_CTL_107_DATA 0x00000000
+#define DDRSS0_CTL_108_DATA 0x000005A2
+#define DDRSS0_CTL_109_DATA 0x00081CC0
+#define DDRSS0_CTL_110_DATA 0x00081CC0
+#define DDRSS0_CTL_111_DATA 0x00081CC0
+#define DDRSS0_CTL_112_DATA 0x00081CC0
+#define DDRSS0_CTL_113_DATA 0x00081CC0
+#define DDRSS0_CTL_114_DATA 0x00000000
+#define DDRSS0_CTL_115_DATA 0x0000E325
+#define DDRSS0_CTL_116_DATA 0x00081CC0
+#define DDRSS0_CTL_117_DATA 0x00081CC0
+#define DDRSS0_CTL_118_DATA 0x00081CC0
+#define DDRSS0_CTL_119_DATA 0x00081CC0
+#define DDRSS0_CTL_120_DATA 0x00081CC0
+#define DDRSS0_CTL_121_DATA 0x00000000
+#define DDRSS0_CTL_122_DATA 0x0000E325
+#define DDRSS0_CTL_123_DATA 0x00000000
+#define DDRSS0_CTL_124_DATA 0x00000000
+#define DDRSS0_CTL_125_DATA 0x00000000
+#define DDRSS0_CTL_126_DATA 0x00000000
+#define DDRSS0_CTL_127_DATA 0x00000000
+#define DDRSS0_CTL_128_DATA 0x00000000
+#define DDRSS0_CTL_129_DATA 0x00000000
+#define DDRSS0_CTL_130_DATA 0x00000000
+#define DDRSS0_CTL_131_DATA 0x0B030500
+#define DDRSS0_CTL_132_DATA 0x00040B04
+#define DDRSS0_CTL_133_DATA 0x0A090000
+#define DDRSS0_CTL_134_DATA 0x0A090701
+#define DDRSS0_CTL_135_DATA 0x0900000E
+#define DDRSS0_CTL_136_DATA 0x0907010A
+#define DDRSS0_CTL_137_DATA 0x00000E0A
+#define DDRSS0_CTL_138_DATA 0x07010A09
+#define DDRSS0_CTL_139_DATA 0x000E0A09
+#define DDRSS0_CTL_140_DATA 0x07000401
+#define DDRSS0_CTL_141_DATA 0x00000000
+#define DDRSS0_CTL_142_DATA 0x00000000
+#define DDRSS0_CTL_143_DATA 0x00000000
+#define DDRSS0_CTL_144_DATA 0x00000000
+#define DDRSS0_CTL_145_DATA 0x00000000
+#define DDRSS0_CTL_146_DATA 0x00000000
+#define DDRSS0_CTL_147_DATA 0x00000000
+#define DDRSS0_CTL_148_DATA 0x08080000
+#define DDRSS0_CTL_149_DATA 0x01000000
+#define DDRSS0_CTL_150_DATA 0x800000C0
+#define DDRSS0_CTL_151_DATA 0x800000C0
+#define DDRSS0_CTL_152_DATA 0x800000C0
+#define DDRSS0_CTL_153_DATA 0x00000000
+#define DDRSS0_CTL_154_DATA 0x00001500
+#define DDRSS0_CTL_155_DATA 0x00000000
+#define DDRSS0_CTL_156_DATA 0x00000001
+#define DDRSS0_CTL_157_DATA 0x00000002
+#define DDRSS0_CTL_158_DATA 0x0000100E
+#define DDRSS0_CTL_159_DATA 0x00000000
+#define DDRSS0_CTL_160_DATA 0x00000000
+#define DDRSS0_CTL_161_DATA 0x00000000
+#define DDRSS0_CTL_162_DATA 0x00000000
+#define DDRSS0_CTL_163_DATA 0x00000000
+#define DDRSS0_CTL_164_DATA 0x000B0000
+#define DDRSS0_CTL_165_DATA 0x000E0006
+#define DDRSS0_CTL_166_DATA 0x000E0404
+#define DDRSS0_CTL_167_DATA 0x00D601AB
+#define DDRSS0_CTL_168_DATA 0x10100216
+#define DDRSS0_CTL_169_DATA 0x01AB0216
+#define DDRSS0_CTL_170_DATA 0x021600D6
+#define DDRSS0_CTL_171_DATA 0x02161010
+#define DDRSS0_CTL_172_DATA 0x00000000
+#define DDRSS0_CTL_173_DATA 0x00000000
+#define DDRSS0_CTL_174_DATA 0x00000000
+#define DDRSS0_CTL_175_DATA 0x3FF40084
+#define DDRSS0_CTL_176_DATA 0x33003FF4
+#define DDRSS0_CTL_177_DATA 0x00003333
+#define DDRSS0_CTL_178_DATA 0x35000000
+#define DDRSS0_CTL_179_DATA 0x27270035
+#define DDRSS0_CTL_180_DATA 0x0F0F0000
+#define DDRSS0_CTL_181_DATA 0x16000000
+#define DDRSS0_CTL_182_DATA 0x00841616
+#define DDRSS0_CTL_183_DATA 0x3FF43FF4
+#define DDRSS0_CTL_184_DATA 0x33333300
+#define DDRSS0_CTL_185_DATA 0x00000000
+#define DDRSS0_CTL_186_DATA 0x00353500
+#define DDRSS0_CTL_187_DATA 0x00002727
+#define DDRSS0_CTL_188_DATA 0x00000F0F
+#define DDRSS0_CTL_189_DATA 0x16161600
+#define DDRSS0_CTL_190_DATA 0x00000020
+#define DDRSS0_CTL_191_DATA 0x00000000
+#define DDRSS0_CTL_192_DATA 0x00000001
+#define DDRSS0_CTL_193_DATA 0x00000000
+#define DDRSS0_CTL_194_DATA 0x01000000
+#define DDRSS0_CTL_195_DATA 0x00000001
+#define DDRSS0_CTL_196_DATA 0x00000000
+#define DDRSS0_CTL_197_DATA 0x00000000
+#define DDRSS0_CTL_198_DATA 0x00000000
+#define DDRSS0_CTL_199_DATA 0x00000000
+#define DDRSS0_CTL_200_DATA 0x00000000
+#define DDRSS0_CTL_201_DATA 0x00000000
+#define DDRSS0_CTL_202_DATA 0x00000000
+#define DDRSS0_CTL_203_DATA 0x00000000
+#define DDRSS0_CTL_204_DATA 0x00000000
+#define DDRSS0_CTL_205_DATA 0x00000000
+#define DDRSS0_CTL_206_DATA 0x02000000
+#define DDRSS0_CTL_207_DATA 0x01080101
+#define DDRSS0_CTL_208_DATA 0x00000000
+#define DDRSS0_CTL_209_DATA 0x00000000
+#define DDRSS0_CTL_210_DATA 0x00000000
+#define DDRSS0_CTL_211_DATA 0x00000000
+#define DDRSS0_CTL_212_DATA 0x00000000
+#define DDRSS0_CTL_213_DATA 0x00000000
+#define DDRSS0_CTL_214_DATA 0x00000000
+#define DDRSS0_CTL_215_DATA 0x00000000
+#define DDRSS0_CTL_216_DATA 0x00000000
+#define DDRSS0_CTL_217_DATA 0x00000000
+#define DDRSS0_CTL_218_DATA 0x00000000
+#define DDRSS0_CTL_219_DATA 0x00000000
+#define DDRSS0_CTL_220_DATA 0x00000000
+#define DDRSS0_CTL_221_DATA 0x00000000
+#define DDRSS0_CTL_222_DATA 0x00001000
+#define DDRSS0_CTL_223_DATA 0x006403E8
+#define DDRSS0_CTL_224_DATA 0x00000000
+#define DDRSS0_CTL_225_DATA 0x00000000
+#define DDRSS0_CTL_226_DATA 0x00000000
+#define DDRSS0_CTL_227_DATA 0x15110000
+#define DDRSS0_CTL_228_DATA 0x00040C18
+#define DDRSS0_CTL_229_DATA 0xF000C000
+#define DDRSS0_CTL_230_DATA 0x0000F000
+#define DDRSS0_CTL_231_DATA 0x00000000
+#define DDRSS0_CTL_232_DATA 0x00000000
+#define DDRSS0_CTL_233_DATA 0xC0000000
+#define DDRSS0_CTL_234_DATA 0xF000F000
+#define DDRSS0_CTL_235_DATA 0x00000000
+#define DDRSS0_CTL_236_DATA 0x00000000
+#define DDRSS0_CTL_237_DATA 0x00000000
+#define DDRSS0_CTL_238_DATA 0xF000C000
+#define DDRSS0_CTL_239_DATA 0x0000F000
+#define DDRSS0_CTL_240_DATA 0x00000000
+#define DDRSS0_CTL_241_DATA 0x00000000
+#define DDRSS0_CTL_242_DATA 0x00030000
+#define DDRSS0_CTL_243_DATA 0x00000000
+#define DDRSS0_CTL_244_DATA 0x00000000
+#define DDRSS0_CTL_245_DATA 0x00000000
+#define DDRSS0_CTL_246_DATA 0x00000000
+#define DDRSS0_CTL_247_DATA 0x00000000
+#define DDRSS0_CTL_248_DATA 0x00000000
+#define DDRSS0_CTL_249_DATA 0x00000000
+#define DDRSS0_CTL_250_DATA 0x00000000
+#define DDRSS0_CTL_251_DATA 0x00000000
+#define DDRSS0_CTL_252_DATA 0x00000000
+#define DDRSS0_CTL_253_DATA 0x00000000
+#define DDRSS0_CTL_254_DATA 0x00000000
+#define DDRSS0_CTL_255_DATA 0x00000000
+#define DDRSS0_CTL_256_DATA 0x00000000
+#define DDRSS0_CTL_257_DATA 0x01000200
+#define DDRSS0_CTL_258_DATA 0x00370040
+#define DDRSS0_CTL_259_DATA 0x00020008
+#define DDRSS0_CTL_260_DATA 0x00400100
+#define DDRSS0_CTL_261_DATA 0x00400855
+#define DDRSS0_CTL_262_DATA 0x01000200
+#define DDRSS0_CTL_263_DATA 0x08550040
+#define DDRSS0_CTL_264_DATA 0x00000040
+#define DDRSS0_CTL_265_DATA 0x006B0003
+#define DDRSS0_CTL_266_DATA 0x0100006B
+#define DDRSS0_CTL_267_DATA 0x03030303
+#define DDRSS0_CTL_268_DATA 0x00000000
+#define DDRSS0_CTL_269_DATA 0x00000202
+#define DDRSS0_CTL_270_DATA 0x00001FFF
+#define DDRSS0_CTL_271_DATA 0x3FFF2000
+#define DDRSS0_CTL_272_DATA 0x03FF0000
+#define DDRSS0_CTL_273_DATA 0x000103FF
+#define DDRSS0_CTL_274_DATA 0x0FFF0B00
+#define DDRSS0_CTL_275_DATA 0x01010001
+#define DDRSS0_CTL_276_DATA 0x01010101
+#define DDRSS0_CTL_277_DATA 0x01180101
+#define DDRSS0_CTL_278_DATA 0x00030000
+#define DDRSS0_CTL_279_DATA 0x00000000
+#define DDRSS0_CTL_280_DATA 0x00000000
+#define DDRSS0_CTL_281_DATA 0x00000000
+#define DDRSS0_CTL_282_DATA 0x00000000
+#define DDRSS0_CTL_283_DATA 0x00000000
+#define DDRSS0_CTL_284_DATA 0x00000000
+#define DDRSS0_CTL_285_DATA 0x00000000
+#define DDRSS0_CTL_286_DATA 0x00040101
+#define DDRSS0_CTL_287_DATA 0x04010100
+#define DDRSS0_CTL_288_DATA 0x00000000
+#define DDRSS0_CTL_289_DATA 0x00000000
+#define DDRSS0_CTL_290_DATA 0x03030300
+#define DDRSS0_CTL_291_DATA 0x00000001
+#define DDRSS0_CTL_292_DATA 0x00000000
+#define DDRSS0_CTL_293_DATA 0x00000000
+#define DDRSS0_CTL_294_DATA 0x00000000
+#define DDRSS0_CTL_295_DATA 0x00000000
+#define DDRSS0_CTL_296_DATA 0x00000000
+#define DDRSS0_CTL_297_DATA 0x00000000
+#define DDRSS0_CTL_298_DATA 0x00000000
+#define DDRSS0_CTL_299_DATA 0x00000000
+#define DDRSS0_CTL_300_DATA 0x00000000
+#define DDRSS0_CTL_301_DATA 0x00000000
+#define DDRSS0_CTL_302_DATA 0x00000000
+#define DDRSS0_CTL_303_DATA 0x00000000
+#define DDRSS0_CTL_304_DATA 0x00000000
+#define DDRSS0_CTL_305_DATA 0x00000000
+#define DDRSS0_CTL_306_DATA 0x00000000
+#define DDRSS0_CTL_307_DATA 0x00000000
+#define DDRSS0_CTL_308_DATA 0x00000000
+#define DDRSS0_CTL_309_DATA 0x00000000
+#define DDRSS0_CTL_310_DATA 0x00000000
+#define DDRSS0_CTL_311_DATA 0x00000000
+#define DDRSS0_CTL_312_DATA 0x00000000
+#define DDRSS0_CTL_313_DATA 0x01000000
+#define DDRSS0_CTL_314_DATA 0x00020201
+#define DDRSS0_CTL_315_DATA 0x01000101
+#define DDRSS0_CTL_316_DATA 0x01010001
+#define DDRSS0_CTL_317_DATA 0x00010101
+#define DDRSS0_CTL_318_DATA 0x050A0A03
+#define DDRSS0_CTL_319_DATA 0x10081F1F
+#define DDRSS0_CTL_320_DATA 0x00090310
+#define DDRSS0_CTL_321_DATA 0x0B0C030F
+#define DDRSS0_CTL_322_DATA 0x0B0C0306
+#define DDRSS0_CTL_323_DATA 0x0C090006
+#define DDRSS0_CTL_324_DATA 0x0100000C
+#define DDRSS0_CTL_325_DATA 0x08040801
+#define DDRSS0_CTL_326_DATA 0x00000004
+#define DDRSS0_CTL_327_DATA 0x00000000
+#define DDRSS0_CTL_328_DATA 0x00010000
+#define DDRSS0_CTL_329_DATA 0x00280D00
+#define DDRSS0_CTL_330_DATA 0x00000001
+#define DDRSS0_CTL_331_DATA 0x00030001
+#define DDRSS0_CTL_332_DATA 0x00000000
+#define DDRSS0_CTL_333_DATA 0x00000000
+#define DDRSS0_CTL_334_DATA 0x00000000
+#define DDRSS0_CTL_335_DATA 0x00000000
+#define DDRSS0_CTL_336_DATA 0x00000000
+#define DDRSS0_CTL_337_DATA 0x00000000
+#define DDRSS0_CTL_338_DATA 0x00000000
+#define DDRSS0_CTL_339_DATA 0x00000000
+#define DDRSS0_CTL_340_DATA 0x01000000
+#define DDRSS0_CTL_341_DATA 0x00000001
+#define DDRSS0_CTL_342_DATA 0x00010100
+#define DDRSS0_CTL_343_DATA 0x03030000
+#define DDRSS0_CTL_344_DATA 0x00000000
+#define DDRSS0_CTL_345_DATA 0x00000000
+#define DDRSS0_CTL_346_DATA 0x00000000
+#define DDRSS0_CTL_347_DATA 0x00000000
+#define DDRSS0_CTL_348_DATA 0x00000000
+#define DDRSS0_CTL_349_DATA 0x00000000
+#define DDRSS0_CTL_350_DATA 0x00000000
+#define DDRSS0_CTL_351_DATA 0x00000000
+#define DDRSS0_CTL_352_DATA 0x00000000
+#define DDRSS0_CTL_353_DATA 0x00000000
+#define DDRSS0_CTL_354_DATA 0x00000000
+#define DDRSS0_CTL_355_DATA 0x00000000
+#define DDRSS0_CTL_356_DATA 0x00000000
+#define DDRSS0_CTL_357_DATA 0x00000000
+#define DDRSS0_CTL_358_DATA 0x00000000
+#define DDRSS0_CTL_359_DATA 0x00000000
+#define DDRSS0_CTL_360_DATA 0x000556AA
+#define DDRSS0_CTL_361_DATA 0x000AAAAA
+#define DDRSS0_CTL_362_DATA 0x000AA955
+#define DDRSS0_CTL_363_DATA 0x00055555
+#define DDRSS0_CTL_364_DATA 0x000B3133
+#define DDRSS0_CTL_365_DATA 0x0004CD33
+#define DDRSS0_CTL_366_DATA 0x0004CECC
+#define DDRSS0_CTL_367_DATA 0x000B32CC
+#define DDRSS0_CTL_368_DATA 0x00010300
+#define DDRSS0_CTL_369_DATA 0x03000100
+#define DDRSS0_CTL_370_DATA 0x00000000
+#define DDRSS0_CTL_371_DATA 0x00000000
+#define DDRSS0_CTL_372_DATA 0x00000000
+#define DDRSS0_CTL_373_DATA 0x00000000
+#define DDRSS0_CTL_374_DATA 0x00000000
+#define DDRSS0_CTL_375_DATA 0x00000000
+#define DDRSS0_CTL_376_DATA 0x00000000
+#define DDRSS0_CTL_377_DATA 0x00010000
+#define DDRSS0_CTL_378_DATA 0x00000404
+#define DDRSS0_CTL_379_DATA 0x00000000
+#define DDRSS0_CTL_380_DATA 0x00000000
+#define DDRSS0_CTL_381_DATA 0x00000000
+#define DDRSS0_CTL_382_DATA 0x00000000
+#define DDRSS0_CTL_383_DATA 0x00000000
+#define DDRSS0_CTL_384_DATA 0x00000000
+#define DDRSS0_CTL_385_DATA 0x00000000
+#define DDRSS0_CTL_386_DATA 0x00000000
+#define DDRSS0_CTL_387_DATA 0x3A3A1B00
+#define DDRSS0_CTL_388_DATA 0x000A0000
+#define DDRSS0_CTL_389_DATA 0x0000019C
+#define DDRSS0_CTL_390_DATA 0x00000200
+#define DDRSS0_CTL_391_DATA 0x00000200
+#define DDRSS0_CTL_392_DATA 0x00000200
+#define DDRSS0_CTL_393_DATA 0x00000200
+#define DDRSS0_CTL_394_DATA 0x000004D4
+#define DDRSS0_CTL_395_DATA 0x00001018
+#define DDRSS0_CTL_396_DATA 0x00000204
+#define DDRSS0_CTL_397_DATA 0x000040E6
+#define DDRSS0_CTL_398_DATA 0x00000200
+#define DDRSS0_CTL_399_DATA 0x00000200
+#define DDRSS0_CTL_400_DATA 0x00000200
+#define DDRSS0_CTL_401_DATA 0x00000200
+#define DDRSS0_CTL_402_DATA 0x0000C2B2
+#define DDRSS0_CTL_403_DATA 0x000288FC
+#define DDRSS0_CTL_404_DATA 0x00000E15
+#define DDRSS0_CTL_405_DATA 0x000040E6
+#define DDRSS0_CTL_406_DATA 0x00000200
+#define DDRSS0_CTL_407_DATA 0x00000200
+#define DDRSS0_CTL_408_DATA 0x00000200
+#define DDRSS0_CTL_409_DATA 0x00000200
+#define DDRSS0_CTL_410_DATA 0x0000C2B2
+#define DDRSS0_CTL_411_DATA 0x000288FC
+#define DDRSS0_CTL_412_DATA 0x02020E15
+#define DDRSS0_CTL_413_DATA 0x03030202
+#define DDRSS0_CTL_414_DATA 0x00000022
+#define DDRSS0_CTL_415_DATA 0x00000000
+#define DDRSS0_CTL_416_DATA 0x00000000
+#define DDRSS0_CTL_417_DATA 0x00001403
+#define DDRSS0_CTL_418_DATA 0x000007D0
+#define DDRSS0_CTL_419_DATA 0x00000000
+#define DDRSS0_CTL_420_DATA 0x00000000
+#define DDRSS0_CTL_421_DATA 0x00030000
+#define DDRSS0_CTL_422_DATA 0x0007001F
+#define DDRSS0_CTL_423_DATA 0x001B0033
+#define DDRSS0_CTL_424_DATA 0x001B0033
+#define DDRSS0_CTL_425_DATA 0x00000000
+#define DDRSS0_CTL_426_DATA 0x00000000
+#define DDRSS0_CTL_427_DATA 0x02000000
+#define DDRSS0_CTL_428_DATA 0x01000404
+#define DDRSS0_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS0_CTL_430_DATA 0x00000105
+#define DDRSS0_CTL_431_DATA 0x00010101
+#define DDRSS0_CTL_432_DATA 0x00010101
+#define DDRSS0_CTL_433_DATA 0x00010001
+#define DDRSS0_CTL_434_DATA 0x00000101
+#define DDRSS0_CTL_435_DATA 0x02000201
+#define DDRSS0_CTL_436_DATA 0x02010000
+#define DDRSS0_CTL_437_DATA 0x00000200
+#define DDRSS0_CTL_438_DATA 0x28060000
+#define DDRSS0_CTL_439_DATA 0x00000128
+#define DDRSS0_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS0_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS0_CTL_442_DATA 0x00000000
+#define DDRSS0_CTL_443_DATA 0x00000000
+#define DDRSS0_CTL_444_DATA 0x00000000
+#define DDRSS0_CTL_445_DATA 0x00000000
+#define DDRSS0_CTL_446_DATA 0x00000000
+#define DDRSS0_CTL_447_DATA 0x00000000
+#define DDRSS0_CTL_448_DATA 0x00000000
+#define DDRSS0_CTL_449_DATA 0x00000000
+#define DDRSS0_CTL_450_DATA 0x00000000
+#define DDRSS0_CTL_451_DATA 0x00000000
+#define DDRSS0_CTL_452_DATA 0x00000000
+#define DDRSS0_CTL_453_DATA 0x00000000
+#define DDRSS0_CTL_454_DATA 0x00000000
+#define DDRSS0_CTL_455_DATA 0x00000000
+#define DDRSS0_CTL_456_DATA 0x00000000
+#define DDRSS0_CTL_457_DATA 0x00000000
+#define DDRSS0_CTL_458_DATA 0x00000000
+
+#define DDRSS0_PI_00_DATA 0x00000B00
+#define DDRSS0_PI_01_DATA 0x00000000
+#define DDRSS0_PI_02_DATA 0x00000000
+#define DDRSS0_PI_03_DATA 0x00000000
+#define DDRSS0_PI_04_DATA 0x00000000
+#define DDRSS0_PI_05_DATA 0x00000101
+#define DDRSS0_PI_06_DATA 0x00640000
+#define DDRSS0_PI_07_DATA 0x00000001
+#define DDRSS0_PI_08_DATA 0x00000000
+#define DDRSS0_PI_09_DATA 0x00000000
+#define DDRSS0_PI_10_DATA 0x00000000
+#define DDRSS0_PI_11_DATA 0x00000000
+#define DDRSS0_PI_12_DATA 0x00000007
+#define DDRSS0_PI_13_DATA 0x00010002
+#define DDRSS0_PI_14_DATA 0x0800000F
+#define DDRSS0_PI_15_DATA 0x00000103
+#define DDRSS0_PI_16_DATA 0x00000005
+#define DDRSS0_PI_17_DATA 0x00000000
+#define DDRSS0_PI_18_DATA 0x00000000
+#define DDRSS0_PI_19_DATA 0x00000000
+#define DDRSS0_PI_20_DATA 0x00000000
+#define DDRSS0_PI_21_DATA 0x00000000
+#define DDRSS0_PI_22_DATA 0x00000000
+#define DDRSS0_PI_23_DATA 0x00000000
+#define DDRSS0_PI_24_DATA 0x00000000
+#define DDRSS0_PI_25_DATA 0x00000000
+#define DDRSS0_PI_26_DATA 0x00010100
+#define DDRSS0_PI_27_DATA 0x00280A00
+#define DDRSS0_PI_28_DATA 0x00000000
+#define DDRSS0_PI_29_DATA 0x0F000000
+#define DDRSS0_PI_30_DATA 0x00003200
+#define DDRSS0_PI_31_DATA 0x00000000
+#define DDRSS0_PI_32_DATA 0x00000000
+#define DDRSS0_PI_33_DATA 0x01010102
+#define DDRSS0_PI_34_DATA 0x00000000
+#define DDRSS0_PI_35_DATA 0x000000AA
+#define DDRSS0_PI_36_DATA 0x00000055
+#define DDRSS0_PI_37_DATA 0x000000B5
+#define DDRSS0_PI_38_DATA 0x0000004A
+#define DDRSS0_PI_39_DATA 0x00000056
+#define DDRSS0_PI_40_DATA 0x000000A9
+#define DDRSS0_PI_41_DATA 0x000000A9
+#define DDRSS0_PI_42_DATA 0x000000B5
+#define DDRSS0_PI_43_DATA 0x00000000
+#define DDRSS0_PI_44_DATA 0x00000000
+#define DDRSS0_PI_45_DATA 0x000F0F00
+#define DDRSS0_PI_46_DATA 0x0000001B
+#define DDRSS0_PI_47_DATA 0x000007D0
+#define DDRSS0_PI_48_DATA 0x00000300
+#define DDRSS0_PI_49_DATA 0x00000000
+#define DDRSS0_PI_50_DATA 0x00000000
+#define DDRSS0_PI_51_DATA 0x01000000
+#define DDRSS0_PI_52_DATA 0x00010101
+#define DDRSS0_PI_53_DATA 0x00000000
+#define DDRSS0_PI_54_DATA 0x00030000
+#define DDRSS0_PI_55_DATA 0x0F000000
+#define DDRSS0_PI_56_DATA 0x00000017
+#define DDRSS0_PI_57_DATA 0x00000000
+#define DDRSS0_PI_58_DATA 0x00000000
+#define DDRSS0_PI_59_DATA 0x00000000
+#define DDRSS0_PI_60_DATA 0x0A0A140A
+#define DDRSS0_PI_61_DATA 0x10020101
+#define DDRSS0_PI_62_DATA 0x00020805
+#define DDRSS0_PI_63_DATA 0x01000404
+#define DDRSS0_PI_64_DATA 0x00000000
+#define DDRSS0_PI_65_DATA 0x00000000
+#define DDRSS0_PI_66_DATA 0x00000100
+#define DDRSS0_PI_67_DATA 0x0001010F
+#define DDRSS0_PI_68_DATA 0x00340000
+#define DDRSS0_PI_69_DATA 0x00000000
+#define DDRSS0_PI_70_DATA 0x00000000
+#define DDRSS0_PI_71_DATA 0x0000FFFF
+#define DDRSS0_PI_72_DATA 0x00000000
+#define DDRSS0_PI_73_DATA 0x00080000
+#define DDRSS0_PI_74_DATA 0x02000200
+#define DDRSS0_PI_75_DATA 0x01000100
+#define DDRSS0_PI_76_DATA 0x01000000
+#define DDRSS0_PI_77_DATA 0x02000200
+#define DDRSS0_PI_78_DATA 0x00000200
+#define DDRSS0_PI_79_DATA 0x00000000
+#define DDRSS0_PI_80_DATA 0x00000000
+#define DDRSS0_PI_81_DATA 0x00000000
+#define DDRSS0_PI_82_DATA 0x00000000
+#define DDRSS0_PI_83_DATA 0x00000000
+#define DDRSS0_PI_84_DATA 0x00000000
+#define DDRSS0_PI_85_DATA 0x00000000
+#define DDRSS0_PI_86_DATA 0x00000000
+#define DDRSS0_PI_87_DATA 0x00000000
+#define DDRSS0_PI_88_DATA 0x00000000
+#define DDRSS0_PI_89_DATA 0x00000000
+#define DDRSS0_PI_90_DATA 0x00000000
+#define DDRSS0_PI_91_DATA 0x00000400
+#define DDRSS0_PI_92_DATA 0x02010000
+#define DDRSS0_PI_93_DATA 0x00080003
+#define DDRSS0_PI_94_DATA 0x00080000
+#define DDRSS0_PI_95_DATA 0x00000001
+#define DDRSS0_PI_96_DATA 0x00000000
+#define DDRSS0_PI_97_DATA 0x0000AA00
+#define DDRSS0_PI_98_DATA 0x00000000
+#define DDRSS0_PI_99_DATA 0x00000000
+#define DDRSS0_PI_100_DATA 0x00010000
+#define DDRSS0_PI_101_DATA 0x00000000
+#define DDRSS0_PI_102_DATA 0x00000000
+#define DDRSS0_PI_103_DATA 0x00000000
+#define DDRSS0_PI_104_DATA 0x00000000
+#define DDRSS0_PI_105_DATA 0x00000000
+#define DDRSS0_PI_106_DATA 0x00000000
+#define DDRSS0_PI_107_DATA 0x00000000
+#define DDRSS0_PI_108_DATA 0x00000000
+#define DDRSS0_PI_109_DATA 0x00000000
+#define DDRSS0_PI_110_DATA 0x00000000
+#define DDRSS0_PI_111_DATA 0x00000000
+#define DDRSS0_PI_112_DATA 0x00000000
+#define DDRSS0_PI_113_DATA 0x00000000
+#define DDRSS0_PI_114_DATA 0x00000000
+#define DDRSS0_PI_115_DATA 0x00000000
+#define DDRSS0_PI_116_DATA 0x00000000
+#define DDRSS0_PI_117_DATA 0x00000000
+#define DDRSS0_PI_118_DATA 0x00000000
+#define DDRSS0_PI_119_DATA 0x00000000
+#define DDRSS0_PI_120_DATA 0x00000000
+#define DDRSS0_PI_121_DATA 0x00000000
+#define DDRSS0_PI_122_DATA 0x00000000
+#define DDRSS0_PI_123_DATA 0x00000000
+#define DDRSS0_PI_124_DATA 0x00000000
+#define DDRSS0_PI_125_DATA 0x00000008
+#define DDRSS0_PI_126_DATA 0x00000000
+#define DDRSS0_PI_127_DATA 0x00000000
+#define DDRSS0_PI_128_DATA 0x00000000
+#define DDRSS0_PI_129_DATA 0x00000000
+#define DDRSS0_PI_130_DATA 0x00000000
+#define DDRSS0_PI_131_DATA 0x00000000
+#define DDRSS0_PI_132_DATA 0x00000000
+#define DDRSS0_PI_133_DATA 0x00000000
+#define DDRSS0_PI_134_DATA 0x00000002
+#define DDRSS0_PI_135_DATA 0x00000000
+#define DDRSS0_PI_136_DATA 0x00000000
+#define DDRSS0_PI_137_DATA 0x0000000A
+#define DDRSS0_PI_138_DATA 0x00000019
+#define DDRSS0_PI_139_DATA 0x00000100
+#define DDRSS0_PI_140_DATA 0x00000000
+#define DDRSS0_PI_141_DATA 0x00000000
+#define DDRSS0_PI_142_DATA 0x00000000
+#define DDRSS0_PI_143_DATA 0x00000000
+#define DDRSS0_PI_144_DATA 0x01000000
+#define DDRSS0_PI_145_DATA 0x00010003
+#define DDRSS0_PI_146_DATA 0x02000101
+#define DDRSS0_PI_147_DATA 0x01030001
+#define DDRSS0_PI_148_DATA 0x00010400
+#define DDRSS0_PI_149_DATA 0x06000105
+#define DDRSS0_PI_150_DATA 0x01070001
+#define DDRSS0_PI_151_DATA 0x00000000
+#define DDRSS0_PI_152_DATA 0x00000000
+#define DDRSS0_PI_153_DATA 0x00000000
+#define DDRSS0_PI_154_DATA 0x00010001
+#define DDRSS0_PI_155_DATA 0x00000000
+#define DDRSS0_PI_156_DATA 0x00000000
+#define DDRSS0_PI_157_DATA 0x00000000
+#define DDRSS0_PI_158_DATA 0x00000000
+#define DDRSS0_PI_159_DATA 0x00000401
+#define DDRSS0_PI_160_DATA 0x00000000
+#define DDRSS0_PI_161_DATA 0x00010000
+#define DDRSS0_PI_162_DATA 0x00000000
+#define DDRSS0_PI_163_DATA 0x2B2B0200
+#define DDRSS0_PI_164_DATA 0x00000034
+#define DDRSS0_PI_165_DATA 0x00000064
+#define DDRSS0_PI_166_DATA 0x00020064
+#define DDRSS0_PI_167_DATA 0x02000200
+#define DDRSS0_PI_168_DATA 0x48120C04
+#define DDRSS0_PI_169_DATA 0x00154812
+#define DDRSS0_PI_170_DATA 0x000000CE
+#define DDRSS0_PI_171_DATA 0x0000032B
+#define DDRSS0_PI_172_DATA 0x00002073
+#define DDRSS0_PI_173_DATA 0x0000032B
+#define DDRSS0_PI_174_DATA 0x04002073
+#define DDRSS0_PI_175_DATA 0x01010404
+#define DDRSS0_PI_176_DATA 0x00001501
+#define DDRSS0_PI_177_DATA 0x00150015
+#define DDRSS0_PI_178_DATA 0x01000100
+#define DDRSS0_PI_179_DATA 0x00000100
+#define DDRSS0_PI_180_DATA 0x00000000
+#define DDRSS0_PI_181_DATA 0x01010101
+#define DDRSS0_PI_182_DATA 0x00000101
+#define DDRSS0_PI_183_DATA 0x00000000
+#define DDRSS0_PI_184_DATA 0x00000000
+#define DDRSS0_PI_185_DATA 0x15040000
+#define DDRSS0_PI_186_DATA 0x0E0E0215
+#define DDRSS0_PI_187_DATA 0x00040402
+#define DDRSS0_PI_188_DATA 0x000D0035
+#define DDRSS0_PI_189_DATA 0x00218049
+#define DDRSS0_PI_190_DATA 0x00218049
+#define DDRSS0_PI_191_DATA 0x01010101
+#define DDRSS0_PI_192_DATA 0x0004000E
+#define DDRSS0_PI_193_DATA 0x00040216
+#define DDRSS0_PI_194_DATA 0x01000216
+#define DDRSS0_PI_195_DATA 0x000F000F
+#define DDRSS0_PI_196_DATA 0x02170100
+#define DDRSS0_PI_197_DATA 0x01000217
+#define DDRSS0_PI_198_DATA 0x02170217
+#define DDRSS0_PI_199_DATA 0x32103200
+#define DDRSS0_PI_200_DATA 0x01013210
+#define DDRSS0_PI_201_DATA 0x0A070601
+#define DDRSS0_PI_202_DATA 0x1F130A0D
+#define DDRSS0_PI_203_DATA 0x1F130A14
+#define DDRSS0_PI_204_DATA 0x0000C014
+#define DDRSS0_PI_205_DATA 0x00C01000
+#define DDRSS0_PI_206_DATA 0x00C01000
+#define DDRSS0_PI_207_DATA 0x00021000
+#define DDRSS0_PI_208_DATA 0x0024000E
+#define DDRSS0_PI_209_DATA 0x00240216
+#define DDRSS0_PI_210_DATA 0x00110216
+#define DDRSS0_PI_211_DATA 0x32000056
+#define DDRSS0_PI_212_DATA 0x00000301
+#define DDRSS0_PI_213_DATA 0x005B0036
+#define DDRSS0_PI_214_DATA 0x03013212
+#define DDRSS0_PI_215_DATA 0x00003600
+#define DDRSS0_PI_216_DATA 0x3212005B
+#define DDRSS0_PI_217_DATA 0x09000301
+#define DDRSS0_PI_218_DATA 0x04010504
+#define DDRSS0_PI_219_DATA 0x040006C9
+#define DDRSS0_PI_220_DATA 0x0A032001
+#define DDRSS0_PI_221_DATA 0x2C31110A
+#define DDRSS0_PI_222_DATA 0x00002918
+#define DDRSS0_PI_223_DATA 0x6001071C
+#define DDRSS0_PI_224_DATA 0x1E202008
+#define DDRSS0_PI_225_DATA 0x2C311116
+#define DDRSS0_PI_226_DATA 0x00002918
+#define DDRSS0_PI_227_DATA 0x6001071C
+#define DDRSS0_PI_228_DATA 0x1E202008
+#define DDRSS0_PI_229_DATA 0x00019C16
+#define DDRSS0_PI_230_DATA 0x00001018
+#define DDRSS0_PI_231_DATA 0x000040E6
+#define DDRSS0_PI_232_DATA 0x000288FC
+#define DDRSS0_PI_233_DATA 0x000040E6
+#define DDRSS0_PI_234_DATA 0x000288FC
+#define DDRSS0_PI_235_DATA 0x033B0016
+#define DDRSS0_PI_236_DATA 0x0303033B
+#define DDRSS0_PI_237_DATA 0x002AF803
+#define DDRSS0_PI_238_DATA 0x0001ADAF
+#define DDRSS0_PI_239_DATA 0x00000005
+#define DDRSS0_PI_240_DATA 0x0000006E
+#define DDRSS0_PI_241_DATA 0x00000016
+#define DDRSS0_PI_242_DATA 0x000681C8
+#define DDRSS0_PI_243_DATA 0x0001ADAF
+#define DDRSS0_PI_244_DATA 0x00000005
+#define DDRSS0_PI_245_DATA 0x000010A9
+#define DDRSS0_PI_246_DATA 0x0000033B
+#define DDRSS0_PI_247_DATA 0x000681C8
+#define DDRSS0_PI_248_DATA 0x0001ADAF
+#define DDRSS0_PI_249_DATA 0x00000005
+#define DDRSS0_PI_250_DATA 0x000010A9
+#define DDRSS0_PI_251_DATA 0x0100033B
+#define DDRSS0_PI_252_DATA 0x00370040
+#define DDRSS0_PI_253_DATA 0x00010008
+#define DDRSS0_PI_254_DATA 0x08550040
+#define DDRSS0_PI_255_DATA 0x00010040
+#define DDRSS0_PI_256_DATA 0x08550040
+#define DDRSS0_PI_257_DATA 0x00000340
+#define DDRSS0_PI_258_DATA 0x006B006B
+#define DDRSS0_PI_259_DATA 0x08040404
+#define DDRSS0_PI_260_DATA 0x00000055
+#define DDRSS0_PI_261_DATA 0x55083C5A
+#define DDRSS0_PI_262_DATA 0x5A000000
+#define DDRSS0_PI_263_DATA 0x0055083C
+#define DDRSS0_PI_264_DATA 0x3C5A0000
+#define DDRSS0_PI_265_DATA 0x00005508
+#define DDRSS0_PI_266_DATA 0x0C3C5A00
+#define DDRSS0_PI_267_DATA 0x080F0E0D
+#define DDRSS0_PI_268_DATA 0x000B0A09
+#define DDRSS0_PI_269_DATA 0x00030201
+#define DDRSS0_PI_270_DATA 0x01000000
+#define DDRSS0_PI_271_DATA 0x04020201
+#define DDRSS0_PI_272_DATA 0x00080804
+#define DDRSS0_PI_273_DATA 0x00000000
+#define DDRSS0_PI_274_DATA 0x00000000
+#define DDRSS0_PI_275_DATA 0x00330084
+#define DDRSS0_PI_276_DATA 0x00160000
+#define DDRSS0_PI_277_DATA 0x35333FF4
+#define DDRSS0_PI_278_DATA 0x00160F27
+#define DDRSS0_PI_279_DATA 0x35333FF4
+#define DDRSS0_PI_280_DATA 0x00160F27
+#define DDRSS0_PI_281_DATA 0x00330084
+#define DDRSS0_PI_282_DATA 0x00160000
+#define DDRSS0_PI_283_DATA 0x35333FF4
+#define DDRSS0_PI_284_DATA 0x00160F27
+#define DDRSS0_PI_285_DATA 0x35333FF4
+#define DDRSS0_PI_286_DATA 0x00160F27
+#define DDRSS0_PI_287_DATA 0x00330084
+#define DDRSS0_PI_288_DATA 0x00160000
+#define DDRSS0_PI_289_DATA 0x35333FF4
+#define DDRSS0_PI_290_DATA 0x00160F27
+#define DDRSS0_PI_291_DATA 0x35333FF4
+#define DDRSS0_PI_292_DATA 0x00160F27
+#define DDRSS0_PI_293_DATA 0x00330084
+#define DDRSS0_PI_294_DATA 0x00160000
+#define DDRSS0_PI_295_DATA 0x35333FF4
+#define DDRSS0_PI_296_DATA 0x00160F27
+#define DDRSS0_PI_297_DATA 0x35333FF4
+#define DDRSS0_PI_298_DATA 0x00160F27
+#define DDRSS0_PI_299_DATA 0x00000000
+
+#define DDRSS0_PHY_00_DATA 0x000004F0
+#define DDRSS0_PHY_01_DATA 0x00000000
+#define DDRSS0_PHY_02_DATA 0x00030200
+#define DDRSS0_PHY_03_DATA 0x00000000
+#define DDRSS0_PHY_04_DATA 0x00000000
+#define DDRSS0_PHY_05_DATA 0x01030000
+#define DDRSS0_PHY_06_DATA 0x00010000
+#define DDRSS0_PHY_07_DATA 0x01030004
+#define DDRSS0_PHY_08_DATA 0x01000000
+#define DDRSS0_PHY_09_DATA 0x00000000
+#define DDRSS0_PHY_10_DATA 0x00000000
+#define DDRSS0_PHY_11_DATA 0x01000001
+#define DDRSS0_PHY_12_DATA 0x00000100
+#define DDRSS0_PHY_13_DATA 0x000800C0
+#define DDRSS0_PHY_14_DATA 0x060100CC
+#define DDRSS0_PHY_15_DATA 0x00030066
+#define DDRSS0_PHY_16_DATA 0x00000000
+#define DDRSS0_PHY_17_DATA 0x00000301
+#define DDRSS0_PHY_18_DATA 0x0000AAAA
+#define DDRSS0_PHY_19_DATA 0x00005555
+#define DDRSS0_PHY_20_DATA 0x0000B5B5
+#define DDRSS0_PHY_21_DATA 0x00004A4A
+#define DDRSS0_PHY_22_DATA 0x00005656
+#define DDRSS0_PHY_23_DATA 0x0000A9A9
+#define DDRSS0_PHY_24_DATA 0x0000A9A9
+#define DDRSS0_PHY_25_DATA 0x0000B5B5
+#define DDRSS0_PHY_26_DATA 0x00000000
+#define DDRSS0_PHY_27_DATA 0x00000000
+#define DDRSS0_PHY_28_DATA 0x2A000000
+#define DDRSS0_PHY_29_DATA 0x00000808
+#define DDRSS0_PHY_30_DATA 0x0F000000
+#define DDRSS0_PHY_31_DATA 0x00000F0F
+#define DDRSS0_PHY_32_DATA 0x10400000
+#define DDRSS0_PHY_33_DATA 0x0C002006
+#define DDRSS0_PHY_34_DATA 0x00000000
+#define DDRSS0_PHY_35_DATA 0x00000000
+#define DDRSS0_PHY_36_DATA 0x55555555
+#define DDRSS0_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_38_DATA 0x55555555
+#define DDRSS0_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_40_DATA 0x00005555
+#define DDRSS0_PHY_41_DATA 0x01000100
+#define DDRSS0_PHY_42_DATA 0x00800180
+#define DDRSS0_PHY_43_DATA 0x00000001
+#define DDRSS0_PHY_44_DATA 0x00000000
+#define DDRSS0_PHY_45_DATA 0x00000000
+#define DDRSS0_PHY_46_DATA 0x00000000
+#define DDRSS0_PHY_47_DATA 0x00000000
+#define DDRSS0_PHY_48_DATA 0x00000000
+#define DDRSS0_PHY_49_DATA 0x00000000
+#define DDRSS0_PHY_50_DATA 0x00000000
+#define DDRSS0_PHY_51_DATA 0x00000000
+#define DDRSS0_PHY_52_DATA 0x00000000
+#define DDRSS0_PHY_53_DATA 0x00000000
+#define DDRSS0_PHY_54_DATA 0x00000000
+#define DDRSS0_PHY_55_DATA 0x00000000
+#define DDRSS0_PHY_56_DATA 0x00000000
+#define DDRSS0_PHY_57_DATA 0x00000000
+#define DDRSS0_PHY_58_DATA 0x00000000
+#define DDRSS0_PHY_59_DATA 0x00000000
+#define DDRSS0_PHY_60_DATA 0x00000000
+#define DDRSS0_PHY_61_DATA 0x00000000
+#define DDRSS0_PHY_62_DATA 0x00000000
+#define DDRSS0_PHY_63_DATA 0x00000000
+#define DDRSS0_PHY_64_DATA 0x00000000
+#define DDRSS0_PHY_65_DATA 0x00000000
+#define DDRSS0_PHY_66_DATA 0x00000104
+#define DDRSS0_PHY_67_DATA 0x00000120
+#define DDRSS0_PHY_68_DATA 0x00000000
+#define DDRSS0_PHY_69_DATA 0x00000000
+#define DDRSS0_PHY_70_DATA 0x00000000
+#define DDRSS0_PHY_71_DATA 0x00000000
+#define DDRSS0_PHY_72_DATA 0x00000000
+#define DDRSS0_PHY_73_DATA 0x00000000
+#define DDRSS0_PHY_74_DATA 0x00000000
+#define DDRSS0_PHY_75_DATA 0x00000001
+#define DDRSS0_PHY_76_DATA 0x07FF0000
+#define DDRSS0_PHY_77_DATA 0x0080081F
+#define DDRSS0_PHY_78_DATA 0x00081020
+#define DDRSS0_PHY_79_DATA 0x04010000
+#define DDRSS0_PHY_80_DATA 0x00000000
+#define DDRSS0_PHY_81_DATA 0x00000000
+#define DDRSS0_PHY_82_DATA 0x00000000
+#define DDRSS0_PHY_83_DATA 0x00000100
+#define DDRSS0_PHY_84_DATA 0x01CC0C01
+#define DDRSS0_PHY_85_DATA 0x1003CC0C
+#define DDRSS0_PHY_86_DATA 0x20000140
+#define DDRSS0_PHY_87_DATA 0x07FF0200
+#define DDRSS0_PHY_88_DATA 0x0000DD01
+#define DDRSS0_PHY_89_DATA 0x10100303
+#define DDRSS0_PHY_90_DATA 0x10101010
+#define DDRSS0_PHY_91_DATA 0x10101010
+#define DDRSS0_PHY_92_DATA 0x00021010
+#define DDRSS0_PHY_93_DATA 0x00100010
+#define DDRSS0_PHY_94_DATA 0x00100010
+#define DDRSS0_PHY_95_DATA 0x00100010
+#define DDRSS0_PHY_96_DATA 0x00100010
+#define DDRSS0_PHY_97_DATA 0x00050010
+#define DDRSS0_PHY_98_DATA 0x51517041
+#define DDRSS0_PHY_99_DATA 0x31C06001
+#define DDRSS0_PHY_100_DATA 0x07AB0340
+#define DDRSS0_PHY_101_DATA 0x00C0C001
+#define DDRSS0_PHY_102_DATA 0x0E0D0001
+#define DDRSS0_PHY_103_DATA 0x10001000
+#define DDRSS0_PHY_104_DATA 0x0C083E42
+#define DDRSS0_PHY_105_DATA 0x0F0C3701
+#define DDRSS0_PHY_106_DATA 0x01000140
+#define DDRSS0_PHY_107_DATA 0x0C000420
+#define DDRSS0_PHY_108_DATA 0x00000198
+#define DDRSS0_PHY_109_DATA 0x0A0000D0
+#define DDRSS0_PHY_110_DATA 0x00030200
+#define DDRSS0_PHY_111_DATA 0x02800000
+#define DDRSS0_PHY_112_DATA 0x80800000
+#define DDRSS0_PHY_113_DATA 0x000E2010
+#define DDRSS0_PHY_114_DATA 0x76543210
+#define DDRSS0_PHY_115_DATA 0x00000008
+#define DDRSS0_PHY_116_DATA 0x02800280
+#define DDRSS0_PHY_117_DATA 0x02800280
+#define DDRSS0_PHY_118_DATA 0x02800280
+#define DDRSS0_PHY_119_DATA 0x02800280
+#define DDRSS0_PHY_120_DATA 0x00000280
+#define DDRSS0_PHY_121_DATA 0x0000A000
+#define DDRSS0_PHY_122_DATA 0x00A000A0
+#define DDRSS0_PHY_123_DATA 0x00A000A0
+#define DDRSS0_PHY_124_DATA 0x00A000A0
+#define DDRSS0_PHY_125_DATA 0x00A000A0
+#define DDRSS0_PHY_126_DATA 0x00A000A0
+#define DDRSS0_PHY_127_DATA 0x00A000A0
+#define DDRSS0_PHY_128_DATA 0x00A000A0
+#define DDRSS0_PHY_129_DATA 0x00A000A0
+#define DDRSS0_PHY_130_DATA 0x01C200A0
+#define DDRSS0_PHY_131_DATA 0x01A00005
+#define DDRSS0_PHY_132_DATA 0x00000000
+#define DDRSS0_PHY_133_DATA 0x00000000
+#define DDRSS0_PHY_134_DATA 0x00080200
+#define DDRSS0_PHY_135_DATA 0x00000000
+#define DDRSS0_PHY_136_DATA 0x20202000
+#define DDRSS0_PHY_137_DATA 0x20202020
+#define DDRSS0_PHY_138_DATA 0xF0F02020
+#define DDRSS0_PHY_139_DATA 0x00000000
+#define DDRSS0_PHY_140_DATA 0x00000000
+#define DDRSS0_PHY_141_DATA 0x00000000
+#define DDRSS0_PHY_142_DATA 0x00000000
+#define DDRSS0_PHY_143_DATA 0x00000000
+#define DDRSS0_PHY_144_DATA 0x00000000
+#define DDRSS0_PHY_145_DATA 0x00000000
+#define DDRSS0_PHY_146_DATA 0x00000000
+#define DDRSS0_PHY_147_DATA 0x00000000
+#define DDRSS0_PHY_148_DATA 0x00000000
+#define DDRSS0_PHY_149_DATA 0x00000000
+#define DDRSS0_PHY_150_DATA 0x00000000
+#define DDRSS0_PHY_151_DATA 0x00000000
+#define DDRSS0_PHY_152_DATA 0x00000000
+#define DDRSS0_PHY_153_DATA 0x00000000
+#define DDRSS0_PHY_154_DATA 0x00000000
+#define DDRSS0_PHY_155_DATA 0x00000000
+#define DDRSS0_PHY_156_DATA 0x00000000
+#define DDRSS0_PHY_157_DATA 0x00000000
+#define DDRSS0_PHY_158_DATA 0x00000000
+#define DDRSS0_PHY_159_DATA 0x00000000
+#define DDRSS0_PHY_160_DATA 0x00000000
+#define DDRSS0_PHY_161_DATA 0x00000000
+#define DDRSS0_PHY_162_DATA 0x00000000
+#define DDRSS0_PHY_163_DATA 0x00000000
+#define DDRSS0_PHY_164_DATA 0x00000000
+#define DDRSS0_PHY_165_DATA 0x00000000
+#define DDRSS0_PHY_166_DATA 0x00000000
+#define DDRSS0_PHY_167_DATA 0x00000000
+#define DDRSS0_PHY_168_DATA 0x00000000
+#define DDRSS0_PHY_169_DATA 0x00000000
+#define DDRSS0_PHY_170_DATA 0x00000000
+#define DDRSS0_PHY_171_DATA 0x00000000
+#define DDRSS0_PHY_172_DATA 0x00000000
+#define DDRSS0_PHY_173_DATA 0x00000000
+#define DDRSS0_PHY_174_DATA 0x00000000
+#define DDRSS0_PHY_175_DATA 0x00000000
+#define DDRSS0_PHY_176_DATA 0x00000000
+#define DDRSS0_PHY_177_DATA 0x00000000
+#define DDRSS0_PHY_178_DATA 0x00000000
+#define DDRSS0_PHY_179_DATA 0x00000000
+#define DDRSS0_PHY_180_DATA 0x00000000
+#define DDRSS0_PHY_181_DATA 0x00000000
+#define DDRSS0_PHY_182_DATA 0x00000000
+#define DDRSS0_PHY_183_DATA 0x00000000
+#define DDRSS0_PHY_184_DATA 0x00000000
+#define DDRSS0_PHY_185_DATA 0x00000000
+#define DDRSS0_PHY_186_DATA 0x00000000
+#define DDRSS0_PHY_187_DATA 0x00000000
+#define DDRSS0_PHY_188_DATA 0x00000000
+#define DDRSS0_PHY_189_DATA 0x00000000
+#define DDRSS0_PHY_190_DATA 0x00000000
+#define DDRSS0_PHY_191_DATA 0x00000000
+#define DDRSS0_PHY_192_DATA 0x00000000
+#define DDRSS0_PHY_193_DATA 0x00000000
+#define DDRSS0_PHY_194_DATA 0x00000000
+#define DDRSS0_PHY_195_DATA 0x00000000
+#define DDRSS0_PHY_196_DATA 0x00000000
+#define DDRSS0_PHY_197_DATA 0x00000000
+#define DDRSS0_PHY_198_DATA 0x00000000
+#define DDRSS0_PHY_199_DATA 0x00000000
+#define DDRSS0_PHY_200_DATA 0x00000000
+#define DDRSS0_PHY_201_DATA 0x00000000
+#define DDRSS0_PHY_202_DATA 0x00000000
+#define DDRSS0_PHY_203_DATA 0x00000000
+#define DDRSS0_PHY_204_DATA 0x00000000
+#define DDRSS0_PHY_205_DATA 0x00000000
+#define DDRSS0_PHY_206_DATA 0x00000000
+#define DDRSS0_PHY_207_DATA 0x00000000
+#define DDRSS0_PHY_208_DATA 0x00000000
+#define DDRSS0_PHY_209_DATA 0x00000000
+#define DDRSS0_PHY_210_DATA 0x00000000
+#define DDRSS0_PHY_211_DATA 0x00000000
+#define DDRSS0_PHY_212_DATA 0x00000000
+#define DDRSS0_PHY_213_DATA 0x00000000
+#define DDRSS0_PHY_214_DATA 0x00000000
+#define DDRSS0_PHY_215_DATA 0x00000000
+#define DDRSS0_PHY_216_DATA 0x00000000
+#define DDRSS0_PHY_217_DATA 0x00000000
+#define DDRSS0_PHY_218_DATA 0x00000000
+#define DDRSS0_PHY_219_DATA 0x00000000
+#define DDRSS0_PHY_220_DATA 0x00000000
+#define DDRSS0_PHY_221_DATA 0x00000000
+#define DDRSS0_PHY_222_DATA 0x00000000
+#define DDRSS0_PHY_223_DATA 0x00000000
+#define DDRSS0_PHY_224_DATA 0x00000000
+#define DDRSS0_PHY_225_DATA 0x00000000
+#define DDRSS0_PHY_226_DATA 0x00000000
+#define DDRSS0_PHY_227_DATA 0x00000000
+#define DDRSS0_PHY_228_DATA 0x00000000
+#define DDRSS0_PHY_229_DATA 0x00000000
+#define DDRSS0_PHY_230_DATA 0x00000000
+#define DDRSS0_PHY_231_DATA 0x00000000
+#define DDRSS0_PHY_232_DATA 0x00000000
+#define DDRSS0_PHY_233_DATA 0x00000000
+#define DDRSS0_PHY_234_DATA 0x00000000
+#define DDRSS0_PHY_235_DATA 0x00000000
+#define DDRSS0_PHY_236_DATA 0x00000000
+#define DDRSS0_PHY_237_DATA 0x00000000
+#define DDRSS0_PHY_238_DATA 0x00000000
+#define DDRSS0_PHY_239_DATA 0x00000000
+#define DDRSS0_PHY_240_DATA 0x00000000
+#define DDRSS0_PHY_241_DATA 0x00000000
+#define DDRSS0_PHY_242_DATA 0x00000000
+#define DDRSS0_PHY_243_DATA 0x00000000
+#define DDRSS0_PHY_244_DATA 0x00000000
+#define DDRSS0_PHY_245_DATA 0x00000000
+#define DDRSS0_PHY_246_DATA 0x00000000
+#define DDRSS0_PHY_247_DATA 0x00000000
+#define DDRSS0_PHY_248_DATA 0x00000000
+#define DDRSS0_PHY_249_DATA 0x00000000
+#define DDRSS0_PHY_250_DATA 0x00000000
+#define DDRSS0_PHY_251_DATA 0x00000000
+#define DDRSS0_PHY_252_DATA 0x00000000
+#define DDRSS0_PHY_253_DATA 0x00000000
+#define DDRSS0_PHY_254_DATA 0x00000000
+#define DDRSS0_PHY_255_DATA 0x00000000
+#define DDRSS0_PHY_256_DATA 0x000004F0
+#define DDRSS0_PHY_257_DATA 0x00000000
+#define DDRSS0_PHY_258_DATA 0x00030200
+#define DDRSS0_PHY_259_DATA 0x00000000
+#define DDRSS0_PHY_260_DATA 0x00000000
+#define DDRSS0_PHY_261_DATA 0x01030000
+#define DDRSS0_PHY_262_DATA 0x00010000
+#define DDRSS0_PHY_263_DATA 0x01030004
+#define DDRSS0_PHY_264_DATA 0x01000000
+#define DDRSS0_PHY_265_DATA 0x00000000
+#define DDRSS0_PHY_266_DATA 0x00000000
+#define DDRSS0_PHY_267_DATA 0x01000001
+#define DDRSS0_PHY_268_DATA 0x00000100
+#define DDRSS0_PHY_269_DATA 0x000800C0
+#define DDRSS0_PHY_270_DATA 0x060100CC
+#define DDRSS0_PHY_271_DATA 0x00030066
+#define DDRSS0_PHY_272_DATA 0x00000000
+#define DDRSS0_PHY_273_DATA 0x00000301
+#define DDRSS0_PHY_274_DATA 0x0000AAAA
+#define DDRSS0_PHY_275_DATA 0x00005555
+#define DDRSS0_PHY_276_DATA 0x0000B5B5
+#define DDRSS0_PHY_277_DATA 0x00004A4A
+#define DDRSS0_PHY_278_DATA 0x00005656
+#define DDRSS0_PHY_279_DATA 0x0000A9A9
+#define DDRSS0_PHY_280_DATA 0x0000A9A9
+#define DDRSS0_PHY_281_DATA 0x0000B5B5
+#define DDRSS0_PHY_282_DATA 0x00000000
+#define DDRSS0_PHY_283_DATA 0x00000000
+#define DDRSS0_PHY_284_DATA 0x2A000000
+#define DDRSS0_PHY_285_DATA 0x00000808
+#define DDRSS0_PHY_286_DATA 0x0F000000
+#define DDRSS0_PHY_287_DATA 0x00000F0F
+#define DDRSS0_PHY_288_DATA 0x10400000
+#define DDRSS0_PHY_289_DATA 0x0C002006
+#define DDRSS0_PHY_290_DATA 0x00000000
+#define DDRSS0_PHY_291_DATA 0x00000000
+#define DDRSS0_PHY_292_DATA 0x55555555
+#define DDRSS0_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_294_DATA 0x55555555
+#define DDRSS0_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_296_DATA 0x00005555
+#define DDRSS0_PHY_297_DATA 0x01000100
+#define DDRSS0_PHY_298_DATA 0x00800180
+#define DDRSS0_PHY_299_DATA 0x00000000
+#define DDRSS0_PHY_300_DATA 0x00000000
+#define DDRSS0_PHY_301_DATA 0x00000000
+#define DDRSS0_PHY_302_DATA 0x00000000
+#define DDRSS0_PHY_303_DATA 0x00000000
+#define DDRSS0_PHY_304_DATA 0x00000000
+#define DDRSS0_PHY_305_DATA 0x00000000
+#define DDRSS0_PHY_306_DATA 0x00000000
+#define DDRSS0_PHY_307_DATA 0x00000000
+#define DDRSS0_PHY_308_DATA 0x00000000
+#define DDRSS0_PHY_309_DATA 0x00000000
+#define DDRSS0_PHY_310_DATA 0x00000000
+#define DDRSS0_PHY_311_DATA 0x00000000
+#define DDRSS0_PHY_312_DATA 0x00000000
+#define DDRSS0_PHY_313_DATA 0x00000000
+#define DDRSS0_PHY_314_DATA 0x00000000
+#define DDRSS0_PHY_315_DATA 0x00000000
+#define DDRSS0_PHY_316_DATA 0x00000000
+#define DDRSS0_PHY_317_DATA 0x00000000
+#define DDRSS0_PHY_318_DATA 0x00000000
+#define DDRSS0_PHY_319_DATA 0x00000000
+#define DDRSS0_PHY_320_DATA 0x00000000
+#define DDRSS0_PHY_321_DATA 0x00000000
+#define DDRSS0_PHY_322_DATA 0x00000104
+#define DDRSS0_PHY_323_DATA 0x00000120
+#define DDRSS0_PHY_324_DATA 0x00000000
+#define DDRSS0_PHY_325_DATA 0x00000000
+#define DDRSS0_PHY_326_DATA 0x00000000
+#define DDRSS0_PHY_327_DATA 0x00000000
+#define DDRSS0_PHY_328_DATA 0x00000000
+#define DDRSS0_PHY_329_DATA 0x00000000
+#define DDRSS0_PHY_330_DATA 0x00000000
+#define DDRSS0_PHY_331_DATA 0x00000001
+#define DDRSS0_PHY_332_DATA 0x07FF0000
+#define DDRSS0_PHY_333_DATA 0x0080081F
+#define DDRSS0_PHY_334_DATA 0x00081020
+#define DDRSS0_PHY_335_DATA 0x04010000
+#define DDRSS0_PHY_336_DATA 0x00000000
+#define DDRSS0_PHY_337_DATA 0x00000000
+#define DDRSS0_PHY_338_DATA 0x00000000
+#define DDRSS0_PHY_339_DATA 0x00000100
+#define DDRSS0_PHY_340_DATA 0x01CC0C01
+#define DDRSS0_PHY_341_DATA 0x1003CC0C
+#define DDRSS0_PHY_342_DATA 0x20000140
+#define DDRSS0_PHY_343_DATA 0x07FF0200
+#define DDRSS0_PHY_344_DATA 0x0000DD01
+#define DDRSS0_PHY_345_DATA 0x10100303
+#define DDRSS0_PHY_346_DATA 0x10101010
+#define DDRSS0_PHY_347_DATA 0x10101010
+#define DDRSS0_PHY_348_DATA 0x00021010
+#define DDRSS0_PHY_349_DATA 0x00100010
+#define DDRSS0_PHY_350_DATA 0x00100010
+#define DDRSS0_PHY_351_DATA 0x00100010
+#define DDRSS0_PHY_352_DATA 0x00100010
+#define DDRSS0_PHY_353_DATA 0x00050010
+#define DDRSS0_PHY_354_DATA 0x51517041
+#define DDRSS0_PHY_355_DATA 0x31C06001
+#define DDRSS0_PHY_356_DATA 0x07AB0340
+#define DDRSS0_PHY_357_DATA 0x00C0C001
+#define DDRSS0_PHY_358_DATA 0x0E0D0001
+#define DDRSS0_PHY_359_DATA 0x10001000
+#define DDRSS0_PHY_360_DATA 0x0C083E42
+#define DDRSS0_PHY_361_DATA 0x0F0C3701
+#define DDRSS0_PHY_362_DATA 0x01000140
+#define DDRSS0_PHY_363_DATA 0x0C000420
+#define DDRSS0_PHY_364_DATA 0x00000198
+#define DDRSS0_PHY_365_DATA 0x0A0000D0
+#define DDRSS0_PHY_366_DATA 0x00030200
+#define DDRSS0_PHY_367_DATA 0x02800000
+#define DDRSS0_PHY_368_DATA 0x80800000
+#define DDRSS0_PHY_369_DATA 0x000E2010
+#define DDRSS0_PHY_370_DATA 0x76543210
+#define DDRSS0_PHY_371_DATA 0x00000008
+#define DDRSS0_PHY_372_DATA 0x02800280
+#define DDRSS0_PHY_373_DATA 0x02800280
+#define DDRSS0_PHY_374_DATA 0x02800280
+#define DDRSS0_PHY_375_DATA 0x02800280
+#define DDRSS0_PHY_376_DATA 0x00000280
+#define DDRSS0_PHY_377_DATA 0x0000A000
+#define DDRSS0_PHY_378_DATA 0x00A000A0
+#define DDRSS0_PHY_379_DATA 0x00A000A0
+#define DDRSS0_PHY_380_DATA 0x00A000A0
+#define DDRSS0_PHY_381_DATA 0x00A000A0
+#define DDRSS0_PHY_382_DATA 0x00A000A0
+#define DDRSS0_PHY_383_DATA 0x00A000A0
+#define DDRSS0_PHY_384_DATA 0x00A000A0
+#define DDRSS0_PHY_385_DATA 0x00A000A0
+#define DDRSS0_PHY_386_DATA 0x01C200A0
+#define DDRSS0_PHY_387_DATA 0x01A00005
+#define DDRSS0_PHY_388_DATA 0x00000000
+#define DDRSS0_PHY_389_DATA 0x00000000
+#define DDRSS0_PHY_390_DATA 0x00080200
+#define DDRSS0_PHY_391_DATA 0x00000000
+#define DDRSS0_PHY_392_DATA 0x20202000
+#define DDRSS0_PHY_393_DATA 0x20202020
+#define DDRSS0_PHY_394_DATA 0xF0F02020
+#define DDRSS0_PHY_395_DATA 0x00000000
+#define DDRSS0_PHY_396_DATA 0x00000000
+#define DDRSS0_PHY_397_DATA 0x00000000
+#define DDRSS0_PHY_398_DATA 0x00000000
+#define DDRSS0_PHY_399_DATA 0x00000000
+#define DDRSS0_PHY_400_DATA 0x00000000
+#define DDRSS0_PHY_401_DATA 0x00000000
+#define DDRSS0_PHY_402_DATA 0x00000000
+#define DDRSS0_PHY_403_DATA 0x00000000
+#define DDRSS0_PHY_404_DATA 0x00000000
+#define DDRSS0_PHY_405_DATA 0x00000000
+#define DDRSS0_PHY_406_DATA 0x00000000
+#define DDRSS0_PHY_407_DATA 0x00000000
+#define DDRSS0_PHY_408_DATA 0x00000000
+#define DDRSS0_PHY_409_DATA 0x00000000
+#define DDRSS0_PHY_410_DATA 0x00000000
+#define DDRSS0_PHY_411_DATA 0x00000000
+#define DDRSS0_PHY_412_DATA 0x00000000
+#define DDRSS0_PHY_413_DATA 0x00000000
+#define DDRSS0_PHY_414_DATA 0x00000000
+#define DDRSS0_PHY_415_DATA 0x00000000
+#define DDRSS0_PHY_416_DATA 0x00000000
+#define DDRSS0_PHY_417_DATA 0x00000000
+#define DDRSS0_PHY_418_DATA 0x00000000
+#define DDRSS0_PHY_419_DATA 0x00000000
+#define DDRSS0_PHY_420_DATA 0x00000000
+#define DDRSS0_PHY_421_DATA 0x00000000
+#define DDRSS0_PHY_422_DATA 0x00000000
+#define DDRSS0_PHY_423_DATA 0x00000000
+#define DDRSS0_PHY_424_DATA 0x00000000
+#define DDRSS0_PHY_425_DATA 0x00000000
+#define DDRSS0_PHY_426_DATA 0x00000000
+#define DDRSS0_PHY_427_DATA 0x00000000
+#define DDRSS0_PHY_428_DATA 0x00000000
+#define DDRSS0_PHY_429_DATA 0x00000000
+#define DDRSS0_PHY_430_DATA 0x00000000
+#define DDRSS0_PHY_431_DATA 0x00000000
+#define DDRSS0_PHY_432_DATA 0x00000000
+#define DDRSS0_PHY_433_DATA 0x00000000
+#define DDRSS0_PHY_434_DATA 0x00000000
+#define DDRSS0_PHY_435_DATA 0x00000000
+#define DDRSS0_PHY_436_DATA 0x00000000
+#define DDRSS0_PHY_437_DATA 0x00000000
+#define DDRSS0_PHY_438_DATA 0x00000000
+#define DDRSS0_PHY_439_DATA 0x00000000
+#define DDRSS0_PHY_440_DATA 0x00000000
+#define DDRSS0_PHY_441_DATA 0x00000000
+#define DDRSS0_PHY_442_DATA 0x00000000
+#define DDRSS0_PHY_443_DATA 0x00000000
+#define DDRSS0_PHY_444_DATA 0x00000000
+#define DDRSS0_PHY_445_DATA 0x00000000
+#define DDRSS0_PHY_446_DATA 0x00000000
+#define DDRSS0_PHY_447_DATA 0x00000000
+#define DDRSS0_PHY_448_DATA 0x00000000
+#define DDRSS0_PHY_449_DATA 0x00000000
+#define DDRSS0_PHY_450_DATA 0x00000000
+#define DDRSS0_PHY_451_DATA 0x00000000
+#define DDRSS0_PHY_452_DATA 0x00000000
+#define DDRSS0_PHY_453_DATA 0x00000000
+#define DDRSS0_PHY_454_DATA 0x00000000
+#define DDRSS0_PHY_455_DATA 0x00000000
+#define DDRSS0_PHY_456_DATA 0x00000000
+#define DDRSS0_PHY_457_DATA 0x00000000
+#define DDRSS0_PHY_458_DATA 0x00000000
+#define DDRSS0_PHY_459_DATA 0x00000000
+#define DDRSS0_PHY_460_DATA 0x00000000
+#define DDRSS0_PHY_461_DATA 0x00000000
+#define DDRSS0_PHY_462_DATA 0x00000000
+#define DDRSS0_PHY_463_DATA 0x00000000
+#define DDRSS0_PHY_464_DATA 0x00000000
+#define DDRSS0_PHY_465_DATA 0x00000000
+#define DDRSS0_PHY_466_DATA 0x00000000
+#define DDRSS0_PHY_467_DATA 0x00000000
+#define DDRSS0_PHY_468_DATA 0x00000000
+#define DDRSS0_PHY_469_DATA 0x00000000
+#define DDRSS0_PHY_470_DATA 0x00000000
+#define DDRSS0_PHY_471_DATA 0x00000000
+#define DDRSS0_PHY_472_DATA 0x00000000
+#define DDRSS0_PHY_473_DATA 0x00000000
+#define DDRSS0_PHY_474_DATA 0x00000000
+#define DDRSS0_PHY_475_DATA 0x00000000
+#define DDRSS0_PHY_476_DATA 0x00000000
+#define DDRSS0_PHY_477_DATA 0x00000000
+#define DDRSS0_PHY_478_DATA 0x00000000
+#define DDRSS0_PHY_479_DATA 0x00000000
+#define DDRSS0_PHY_480_DATA 0x00000000
+#define DDRSS0_PHY_481_DATA 0x00000000
+#define DDRSS0_PHY_482_DATA 0x00000000
+#define DDRSS0_PHY_483_DATA 0x00000000
+#define DDRSS0_PHY_484_DATA 0x00000000
+#define DDRSS0_PHY_485_DATA 0x00000000
+#define DDRSS0_PHY_486_DATA 0x00000000
+#define DDRSS0_PHY_487_DATA 0x00000000
+#define DDRSS0_PHY_488_DATA 0x00000000
+#define DDRSS0_PHY_489_DATA 0x00000000
+#define DDRSS0_PHY_490_DATA 0x00000000
+#define DDRSS0_PHY_491_DATA 0x00000000
+#define DDRSS0_PHY_492_DATA 0x00000000
+#define DDRSS0_PHY_493_DATA 0x00000000
+#define DDRSS0_PHY_494_DATA 0x00000000
+#define DDRSS0_PHY_495_DATA 0x00000000
+#define DDRSS0_PHY_496_DATA 0x00000000
+#define DDRSS0_PHY_497_DATA 0x00000000
+#define DDRSS0_PHY_498_DATA 0x00000000
+#define DDRSS0_PHY_499_DATA 0x00000000
+#define DDRSS0_PHY_500_DATA 0x00000000
+#define DDRSS0_PHY_501_DATA 0x00000000
+#define DDRSS0_PHY_502_DATA 0x00000000
+#define DDRSS0_PHY_503_DATA 0x00000000
+#define DDRSS0_PHY_504_DATA 0x00000000
+#define DDRSS0_PHY_505_DATA 0x00000000
+#define DDRSS0_PHY_506_DATA 0x00000000
+#define DDRSS0_PHY_507_DATA 0x00000000
+#define DDRSS0_PHY_508_DATA 0x00000000
+#define DDRSS0_PHY_509_DATA 0x00000000
+#define DDRSS0_PHY_510_DATA 0x00000000
+#define DDRSS0_PHY_511_DATA 0x00000000
+#define DDRSS0_PHY_512_DATA 0x000004F0
+#define DDRSS0_PHY_513_DATA 0x00000000
+#define DDRSS0_PHY_514_DATA 0x00030200
+#define DDRSS0_PHY_515_DATA 0x00000000
+#define DDRSS0_PHY_516_DATA 0x00000000
+#define DDRSS0_PHY_517_DATA 0x01030000
+#define DDRSS0_PHY_518_DATA 0x00010000
+#define DDRSS0_PHY_519_DATA 0x01030004
+#define DDRSS0_PHY_520_DATA 0x01000000
+#define DDRSS0_PHY_521_DATA 0x00000000
+#define DDRSS0_PHY_522_DATA 0x00000000
+#define DDRSS0_PHY_523_DATA 0x01000001
+#define DDRSS0_PHY_524_DATA 0x00000100
+#define DDRSS0_PHY_525_DATA 0x000800C0
+#define DDRSS0_PHY_526_DATA 0x060100CC
+#define DDRSS0_PHY_527_DATA 0x00030066
+#define DDRSS0_PHY_528_DATA 0x00000000
+#define DDRSS0_PHY_529_DATA 0x00000301
+#define DDRSS0_PHY_530_DATA 0x0000AAAA
+#define DDRSS0_PHY_531_DATA 0x00005555
+#define DDRSS0_PHY_532_DATA 0x0000B5B5
+#define DDRSS0_PHY_533_DATA 0x00004A4A
+#define DDRSS0_PHY_534_DATA 0x00005656
+#define DDRSS0_PHY_535_DATA 0x0000A9A9
+#define DDRSS0_PHY_536_DATA 0x0000A9A9
+#define DDRSS0_PHY_537_DATA 0x0000B5B5
+#define DDRSS0_PHY_538_DATA 0x00000000
+#define DDRSS0_PHY_539_DATA 0x00000000
+#define DDRSS0_PHY_540_DATA 0x2A000000
+#define DDRSS0_PHY_541_DATA 0x00000808
+#define DDRSS0_PHY_542_DATA 0x0F000000
+#define DDRSS0_PHY_543_DATA 0x00000F0F
+#define DDRSS0_PHY_544_DATA 0x10400000
+#define DDRSS0_PHY_545_DATA 0x0C002006
+#define DDRSS0_PHY_546_DATA 0x00000000
+#define DDRSS0_PHY_547_DATA 0x00000000
+#define DDRSS0_PHY_548_DATA 0x55555555
+#define DDRSS0_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_550_DATA 0x55555555
+#define DDRSS0_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_552_DATA 0x00005555
+#define DDRSS0_PHY_553_DATA 0x01000100
+#define DDRSS0_PHY_554_DATA 0x00800180
+#define DDRSS0_PHY_555_DATA 0x00000001
+#define DDRSS0_PHY_556_DATA 0x00000000
+#define DDRSS0_PHY_557_DATA 0x00000000
+#define DDRSS0_PHY_558_DATA 0x00000000
+#define DDRSS0_PHY_559_DATA 0x00000000
+#define DDRSS0_PHY_560_DATA 0x00000000
+#define DDRSS0_PHY_561_DATA 0x00000000
+#define DDRSS0_PHY_562_DATA 0x00000000
+#define DDRSS0_PHY_563_DATA 0x00000000
+#define DDRSS0_PHY_564_DATA 0x00000000
+#define DDRSS0_PHY_565_DATA 0x00000000
+#define DDRSS0_PHY_566_DATA 0x00000000
+#define DDRSS0_PHY_567_DATA 0x00000000
+#define DDRSS0_PHY_568_DATA 0x00000000
+#define DDRSS0_PHY_569_DATA 0x00000000
+#define DDRSS0_PHY_570_DATA 0x00000000
+#define DDRSS0_PHY_571_DATA 0x00000000
+#define DDRSS0_PHY_572_DATA 0x00000000
+#define DDRSS0_PHY_573_DATA 0x00000000
+#define DDRSS0_PHY_574_DATA 0x00000000
+#define DDRSS0_PHY_575_DATA 0x00000000
+#define DDRSS0_PHY_576_DATA 0x00000000
+#define DDRSS0_PHY_577_DATA 0x00000000
+#define DDRSS0_PHY_578_DATA 0x00000104
+#define DDRSS0_PHY_579_DATA 0x00000120
+#define DDRSS0_PHY_580_DATA 0x00000000
+#define DDRSS0_PHY_581_DATA 0x00000000
+#define DDRSS0_PHY_582_DATA 0x00000000
+#define DDRSS0_PHY_583_DATA 0x00000000
+#define DDRSS0_PHY_584_DATA 0x00000000
+#define DDRSS0_PHY_585_DATA 0x00000000
+#define DDRSS0_PHY_586_DATA 0x00000000
+#define DDRSS0_PHY_587_DATA 0x00000001
+#define DDRSS0_PHY_588_DATA 0x07FF0000
+#define DDRSS0_PHY_589_DATA 0x0080081F
+#define DDRSS0_PHY_590_DATA 0x00081020
+#define DDRSS0_PHY_591_DATA 0x04010000
+#define DDRSS0_PHY_592_DATA 0x00000000
+#define DDRSS0_PHY_593_DATA 0x00000000
+#define DDRSS0_PHY_594_DATA 0x00000000
+#define DDRSS0_PHY_595_DATA 0x00000100
+#define DDRSS0_PHY_596_DATA 0x01CC0C01
+#define DDRSS0_PHY_597_DATA 0x1003CC0C
+#define DDRSS0_PHY_598_DATA 0x20000140
+#define DDRSS0_PHY_599_DATA 0x07FF0200
+#define DDRSS0_PHY_600_DATA 0x0000DD01
+#define DDRSS0_PHY_601_DATA 0x10100303
+#define DDRSS0_PHY_602_DATA 0x10101010
+#define DDRSS0_PHY_603_DATA 0x10101010
+#define DDRSS0_PHY_604_DATA 0x00021010
+#define DDRSS0_PHY_605_DATA 0x00100010
+#define DDRSS0_PHY_606_DATA 0x00100010
+#define DDRSS0_PHY_607_DATA 0x00100010
+#define DDRSS0_PHY_608_DATA 0x00100010
+#define DDRSS0_PHY_609_DATA 0x00050010
+#define DDRSS0_PHY_610_DATA 0x51517041
+#define DDRSS0_PHY_611_DATA 0x31C06001
+#define DDRSS0_PHY_612_DATA 0x07AB0340
+#define DDRSS0_PHY_613_DATA 0x00C0C001
+#define DDRSS0_PHY_614_DATA 0x0E0D0001
+#define DDRSS0_PHY_615_DATA 0x10001000
+#define DDRSS0_PHY_616_DATA 0x0C083E42
+#define DDRSS0_PHY_617_DATA 0x0F0C3701
+#define DDRSS0_PHY_618_DATA 0x01000140
+#define DDRSS0_PHY_619_DATA 0x0C000420
+#define DDRSS0_PHY_620_DATA 0x00000198
+#define DDRSS0_PHY_621_DATA 0x0A0000D0
+#define DDRSS0_PHY_622_DATA 0x00030200
+#define DDRSS0_PHY_623_DATA 0x02800000
+#define DDRSS0_PHY_624_DATA 0x80800000
+#define DDRSS0_PHY_625_DATA 0x000E2010
+#define DDRSS0_PHY_626_DATA 0x76543210
+#define DDRSS0_PHY_627_DATA 0x00000008
+#define DDRSS0_PHY_628_DATA 0x02800280
+#define DDRSS0_PHY_629_DATA 0x02800280
+#define DDRSS0_PHY_630_DATA 0x02800280
+#define DDRSS0_PHY_631_DATA 0x02800280
+#define DDRSS0_PHY_632_DATA 0x00000280
+#define DDRSS0_PHY_633_DATA 0x0000A000
+#define DDRSS0_PHY_634_DATA 0x00A000A0
+#define DDRSS0_PHY_635_DATA 0x00A000A0
+#define DDRSS0_PHY_636_DATA 0x00A000A0
+#define DDRSS0_PHY_637_DATA 0x00A000A0
+#define DDRSS0_PHY_638_DATA 0x00A000A0
+#define DDRSS0_PHY_639_DATA 0x00A000A0
+#define DDRSS0_PHY_640_DATA 0x00A000A0
+#define DDRSS0_PHY_641_DATA 0x00A000A0
+#define DDRSS0_PHY_642_DATA 0x01C200A0
+#define DDRSS0_PHY_643_DATA 0x01A00005
+#define DDRSS0_PHY_644_DATA 0x00000000
+#define DDRSS0_PHY_645_DATA 0x00000000
+#define DDRSS0_PHY_646_DATA 0x00080200
+#define DDRSS0_PHY_647_DATA 0x00000000
+#define DDRSS0_PHY_648_DATA 0x20202000
+#define DDRSS0_PHY_649_DATA 0x20202020
+#define DDRSS0_PHY_650_DATA 0xF0F02020
+#define DDRSS0_PHY_651_DATA 0x00000000
+#define DDRSS0_PHY_652_DATA 0x00000000
+#define DDRSS0_PHY_653_DATA 0x00000000
+#define DDRSS0_PHY_654_DATA 0x00000000
+#define DDRSS0_PHY_655_DATA 0x00000000
+#define DDRSS0_PHY_656_DATA 0x00000000
+#define DDRSS0_PHY_657_DATA 0x00000000
+#define DDRSS0_PHY_658_DATA 0x00000000
+#define DDRSS0_PHY_659_DATA 0x00000000
+#define DDRSS0_PHY_660_DATA 0x00000000
+#define DDRSS0_PHY_661_DATA 0x00000000
+#define DDRSS0_PHY_662_DATA 0x00000000
+#define DDRSS0_PHY_663_DATA 0x00000000
+#define DDRSS0_PHY_664_DATA 0x00000000
+#define DDRSS0_PHY_665_DATA 0x00000000
+#define DDRSS0_PHY_666_DATA 0x00000000
+#define DDRSS0_PHY_667_DATA 0x00000000
+#define DDRSS0_PHY_668_DATA 0x00000000
+#define DDRSS0_PHY_669_DATA 0x00000000
+#define DDRSS0_PHY_670_DATA 0x00000000
+#define DDRSS0_PHY_671_DATA 0x00000000
+#define DDRSS0_PHY_672_DATA 0x00000000
+#define DDRSS0_PHY_673_DATA 0x00000000
+#define DDRSS0_PHY_674_DATA 0x00000000
+#define DDRSS0_PHY_675_DATA 0x00000000
+#define DDRSS0_PHY_676_DATA 0x00000000
+#define DDRSS0_PHY_677_DATA 0x00000000
+#define DDRSS0_PHY_678_DATA 0x00000000
+#define DDRSS0_PHY_679_DATA 0x00000000
+#define DDRSS0_PHY_680_DATA 0x00000000
+#define DDRSS0_PHY_681_DATA 0x00000000
+#define DDRSS0_PHY_682_DATA 0x00000000
+#define DDRSS0_PHY_683_DATA 0x00000000
+#define DDRSS0_PHY_684_DATA 0x00000000
+#define DDRSS0_PHY_685_DATA 0x00000000
+#define DDRSS0_PHY_686_DATA 0x00000000
+#define DDRSS0_PHY_687_DATA 0x00000000
+#define DDRSS0_PHY_688_DATA 0x00000000
+#define DDRSS0_PHY_689_DATA 0x00000000
+#define DDRSS0_PHY_690_DATA 0x00000000
+#define DDRSS0_PHY_691_DATA 0x00000000
+#define DDRSS0_PHY_692_DATA 0x00000000
+#define DDRSS0_PHY_693_DATA 0x00000000
+#define DDRSS0_PHY_694_DATA 0x00000000
+#define DDRSS0_PHY_695_DATA 0x00000000
+#define DDRSS0_PHY_696_DATA 0x00000000
+#define DDRSS0_PHY_697_DATA 0x00000000
+#define DDRSS0_PHY_698_DATA 0x00000000
+#define DDRSS0_PHY_699_DATA 0x00000000
+#define DDRSS0_PHY_700_DATA 0x00000000
+#define DDRSS0_PHY_701_DATA 0x00000000
+#define DDRSS0_PHY_702_DATA 0x00000000
+#define DDRSS0_PHY_703_DATA 0x00000000
+#define DDRSS0_PHY_704_DATA 0x00000000
+#define DDRSS0_PHY_705_DATA 0x00000000
+#define DDRSS0_PHY_706_DATA 0x00000000
+#define DDRSS0_PHY_707_DATA 0x00000000
+#define DDRSS0_PHY_708_DATA 0x00000000
+#define DDRSS0_PHY_709_DATA 0x00000000
+#define DDRSS0_PHY_710_DATA 0x00000000
+#define DDRSS0_PHY_711_DATA 0x00000000
+#define DDRSS0_PHY_712_DATA 0x00000000
+#define DDRSS0_PHY_713_DATA 0x00000000
+#define DDRSS0_PHY_714_DATA 0x00000000
+#define DDRSS0_PHY_715_DATA 0x00000000
+#define DDRSS0_PHY_716_DATA 0x00000000
+#define DDRSS0_PHY_717_DATA 0x00000000
+#define DDRSS0_PHY_718_DATA 0x00000000
+#define DDRSS0_PHY_719_DATA 0x00000000
+#define DDRSS0_PHY_720_DATA 0x00000000
+#define DDRSS0_PHY_721_DATA 0x00000000
+#define DDRSS0_PHY_722_DATA 0x00000000
+#define DDRSS0_PHY_723_DATA 0x00000000
+#define DDRSS0_PHY_724_DATA 0x00000000
+#define DDRSS0_PHY_725_DATA 0x00000000
+#define DDRSS0_PHY_726_DATA 0x00000000
+#define DDRSS0_PHY_727_DATA 0x00000000
+#define DDRSS0_PHY_728_DATA 0x00000000
+#define DDRSS0_PHY_729_DATA 0x00000000
+#define DDRSS0_PHY_730_DATA 0x00000000
+#define DDRSS0_PHY_731_DATA 0x00000000
+#define DDRSS0_PHY_732_DATA 0x00000000
+#define DDRSS0_PHY_733_DATA 0x00000000
+#define DDRSS0_PHY_734_DATA 0x00000000
+#define DDRSS0_PHY_735_DATA 0x00000000
+#define DDRSS0_PHY_736_DATA 0x00000000
+#define DDRSS0_PHY_737_DATA 0x00000000
+#define DDRSS0_PHY_738_DATA 0x00000000
+#define DDRSS0_PHY_739_DATA 0x00000000
+#define DDRSS0_PHY_740_DATA 0x00000000
+#define DDRSS0_PHY_741_DATA 0x00000000
+#define DDRSS0_PHY_742_DATA 0x00000000
+#define DDRSS0_PHY_743_DATA 0x00000000
+#define DDRSS0_PHY_744_DATA 0x00000000
+#define DDRSS0_PHY_745_DATA 0x00000000
+#define DDRSS0_PHY_746_DATA 0x00000000
+#define DDRSS0_PHY_747_DATA 0x00000000
+#define DDRSS0_PHY_748_DATA 0x00000000
+#define DDRSS0_PHY_749_DATA 0x00000000
+#define DDRSS0_PHY_750_DATA 0x00000000
+#define DDRSS0_PHY_751_DATA 0x00000000
+#define DDRSS0_PHY_752_DATA 0x00000000
+#define DDRSS0_PHY_753_DATA 0x00000000
+#define DDRSS0_PHY_754_DATA 0x00000000
+#define DDRSS0_PHY_755_DATA 0x00000000
+#define DDRSS0_PHY_756_DATA 0x00000000
+#define DDRSS0_PHY_757_DATA 0x00000000
+#define DDRSS0_PHY_758_DATA 0x00000000
+#define DDRSS0_PHY_759_DATA 0x00000000
+#define DDRSS0_PHY_760_DATA 0x00000000
+#define DDRSS0_PHY_761_DATA 0x00000000
+#define DDRSS0_PHY_762_DATA 0x00000000
+#define DDRSS0_PHY_763_DATA 0x00000000
+#define DDRSS0_PHY_764_DATA 0x00000000
+#define DDRSS0_PHY_765_DATA 0x00000000
+#define DDRSS0_PHY_766_DATA 0x00000000
+#define DDRSS0_PHY_767_DATA 0x00000000
+#define DDRSS0_PHY_768_DATA 0x000004F0
+#define DDRSS0_PHY_769_DATA 0x00000000
+#define DDRSS0_PHY_770_DATA 0x00030200
+#define DDRSS0_PHY_771_DATA 0x00000000
+#define DDRSS0_PHY_772_DATA 0x00000000
+#define DDRSS0_PHY_773_DATA 0x01030000
+#define DDRSS0_PHY_774_DATA 0x00010000
+#define DDRSS0_PHY_775_DATA 0x01030004
+#define DDRSS0_PHY_776_DATA 0x01000000
+#define DDRSS0_PHY_777_DATA 0x00000000
+#define DDRSS0_PHY_778_DATA 0x00000000
+#define DDRSS0_PHY_779_DATA 0x01000001
+#define DDRSS0_PHY_780_DATA 0x00000100
+#define DDRSS0_PHY_781_DATA 0x000800C0
+#define DDRSS0_PHY_782_DATA 0x060100CC
+#define DDRSS0_PHY_783_DATA 0x00030066
+#define DDRSS0_PHY_784_DATA 0x00000000
+#define DDRSS0_PHY_785_DATA 0x00000301
+#define DDRSS0_PHY_786_DATA 0x0000AAAA
+#define DDRSS0_PHY_787_DATA 0x00005555
+#define DDRSS0_PHY_788_DATA 0x0000B5B5
+#define DDRSS0_PHY_789_DATA 0x00004A4A
+#define DDRSS0_PHY_790_DATA 0x00005656
+#define DDRSS0_PHY_791_DATA 0x0000A9A9
+#define DDRSS0_PHY_792_DATA 0x0000A9A9
+#define DDRSS0_PHY_793_DATA 0x0000B5B5
+#define DDRSS0_PHY_794_DATA 0x00000000
+#define DDRSS0_PHY_795_DATA 0x00000000
+#define DDRSS0_PHY_796_DATA 0x2A000000
+#define DDRSS0_PHY_797_DATA 0x00000808
+#define DDRSS0_PHY_798_DATA 0x0F000000
+#define DDRSS0_PHY_799_DATA 0x00000F0F
+#define DDRSS0_PHY_800_DATA 0x10400000
+#define DDRSS0_PHY_801_DATA 0x0C002006
+#define DDRSS0_PHY_802_DATA 0x00000000
+#define DDRSS0_PHY_803_DATA 0x00000000
+#define DDRSS0_PHY_804_DATA 0x55555555
+#define DDRSS0_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_806_DATA 0x55555555
+#define DDRSS0_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS0_PHY_808_DATA 0x00005555
+#define DDRSS0_PHY_809_DATA 0x01000100
+#define DDRSS0_PHY_810_DATA 0x00800180
+#define DDRSS0_PHY_811_DATA 0x00000000
+#define DDRSS0_PHY_812_DATA 0x00000000
+#define DDRSS0_PHY_813_DATA 0x00000000
+#define DDRSS0_PHY_814_DATA 0x00000000
+#define DDRSS0_PHY_815_DATA 0x00000000
+#define DDRSS0_PHY_816_DATA 0x00000000
+#define DDRSS0_PHY_817_DATA 0x00000000
+#define DDRSS0_PHY_818_DATA 0x00000000
+#define DDRSS0_PHY_819_DATA 0x00000000
+#define DDRSS0_PHY_820_DATA 0x00000000
+#define DDRSS0_PHY_821_DATA 0x00000000
+#define DDRSS0_PHY_822_DATA 0x00000000
+#define DDRSS0_PHY_823_DATA 0x00000000
+#define DDRSS0_PHY_824_DATA 0x00000000
+#define DDRSS0_PHY_825_DATA 0x00000000
+#define DDRSS0_PHY_826_DATA 0x00000000
+#define DDRSS0_PHY_827_DATA 0x00000000
+#define DDRSS0_PHY_828_DATA 0x00000000
+#define DDRSS0_PHY_829_DATA 0x00000000
+#define DDRSS0_PHY_830_DATA 0x00000000
+#define DDRSS0_PHY_831_DATA 0x00000000
+#define DDRSS0_PHY_832_DATA 0x00000000
+#define DDRSS0_PHY_833_DATA 0x00000000
+#define DDRSS0_PHY_834_DATA 0x00000104
+#define DDRSS0_PHY_835_DATA 0x00000120
+#define DDRSS0_PHY_836_DATA 0x00000000
+#define DDRSS0_PHY_837_DATA 0x00000000
+#define DDRSS0_PHY_838_DATA 0x00000000
+#define DDRSS0_PHY_839_DATA 0x00000000
+#define DDRSS0_PHY_840_DATA 0x00000000
+#define DDRSS0_PHY_841_DATA 0x00000000
+#define DDRSS0_PHY_842_DATA 0x00000000
+#define DDRSS0_PHY_843_DATA 0x00000001
+#define DDRSS0_PHY_844_DATA 0x07FF0000
+#define DDRSS0_PHY_845_DATA 0x0080081F
+#define DDRSS0_PHY_846_DATA 0x00081020
+#define DDRSS0_PHY_847_DATA 0x04010000
+#define DDRSS0_PHY_848_DATA 0x00000000
+#define DDRSS0_PHY_849_DATA 0x00000000
+#define DDRSS0_PHY_850_DATA 0x00000000
+#define DDRSS0_PHY_851_DATA 0x00000100
+#define DDRSS0_PHY_852_DATA 0x01CC0C01
+#define DDRSS0_PHY_853_DATA 0x1003CC0C
+#define DDRSS0_PHY_854_DATA 0x20000140
+#define DDRSS0_PHY_855_DATA 0x07FF0200
+#define DDRSS0_PHY_856_DATA 0x0000DD01
+#define DDRSS0_PHY_857_DATA 0x10100303
+#define DDRSS0_PHY_858_DATA 0x10101010
+#define DDRSS0_PHY_859_DATA 0x10101010
+#define DDRSS0_PHY_860_DATA 0x00021010
+#define DDRSS0_PHY_861_DATA 0x00100010
+#define DDRSS0_PHY_862_DATA 0x00100010
+#define DDRSS0_PHY_863_DATA 0x00100010
+#define DDRSS0_PHY_864_DATA 0x00100010
+#define DDRSS0_PHY_865_DATA 0x00050010
+#define DDRSS0_PHY_866_DATA 0x51517041
+#define DDRSS0_PHY_867_DATA 0x31C06001
+#define DDRSS0_PHY_868_DATA 0x07AB0340
+#define DDRSS0_PHY_869_DATA 0x00C0C001
+#define DDRSS0_PHY_870_DATA 0x0E0D0001
+#define DDRSS0_PHY_871_DATA 0x10001000
+#define DDRSS0_PHY_872_DATA 0x0C083E42
+#define DDRSS0_PHY_873_DATA 0x0F0C3701
+#define DDRSS0_PHY_874_DATA 0x01000140
+#define DDRSS0_PHY_875_DATA 0x0C000420
+#define DDRSS0_PHY_876_DATA 0x00000198
+#define DDRSS0_PHY_877_DATA 0x0A0000D0
+#define DDRSS0_PHY_878_DATA 0x00030200
+#define DDRSS0_PHY_879_DATA 0x02800000
+#define DDRSS0_PHY_880_DATA 0x80800000
+#define DDRSS0_PHY_881_DATA 0x000E2010
+#define DDRSS0_PHY_882_DATA 0x76543210
+#define DDRSS0_PHY_883_DATA 0x00000008
+#define DDRSS0_PHY_884_DATA 0x02800280
+#define DDRSS0_PHY_885_DATA 0x02800280
+#define DDRSS0_PHY_886_DATA 0x02800280
+#define DDRSS0_PHY_887_DATA 0x02800280
+#define DDRSS0_PHY_888_DATA 0x00000280
+#define DDRSS0_PHY_889_DATA 0x0000A000
+#define DDRSS0_PHY_890_DATA 0x00A000A0
+#define DDRSS0_PHY_891_DATA 0x00A000A0
+#define DDRSS0_PHY_892_DATA 0x00A000A0
+#define DDRSS0_PHY_893_DATA 0x00A000A0
+#define DDRSS0_PHY_894_DATA 0x00A000A0
+#define DDRSS0_PHY_895_DATA 0x00A000A0
+#define DDRSS0_PHY_896_DATA 0x00A000A0
+#define DDRSS0_PHY_897_DATA 0x00A000A0
+#define DDRSS0_PHY_898_DATA 0x01C200A0
+#define DDRSS0_PHY_899_DATA 0x01A00005
+#define DDRSS0_PHY_900_DATA 0x00000000
+#define DDRSS0_PHY_901_DATA 0x00000000
+#define DDRSS0_PHY_902_DATA 0x00080200
+#define DDRSS0_PHY_903_DATA 0x00000000
+#define DDRSS0_PHY_904_DATA 0x20202000
+#define DDRSS0_PHY_905_DATA 0x20202020
+#define DDRSS0_PHY_906_DATA 0xF0F02020
+#define DDRSS0_PHY_907_DATA 0x00000000
+#define DDRSS0_PHY_908_DATA 0x00000000
+#define DDRSS0_PHY_909_DATA 0x00000000
+#define DDRSS0_PHY_910_DATA 0x00000000
+#define DDRSS0_PHY_911_DATA 0x00000000
+#define DDRSS0_PHY_912_DATA 0x00000000
+#define DDRSS0_PHY_913_DATA 0x00000000
+#define DDRSS0_PHY_914_DATA 0x00000000
+#define DDRSS0_PHY_915_DATA 0x00000000
+#define DDRSS0_PHY_916_DATA 0x00000000
+#define DDRSS0_PHY_917_DATA 0x00000000
+#define DDRSS0_PHY_918_DATA 0x00000000
+#define DDRSS0_PHY_919_DATA 0x00000000
+#define DDRSS0_PHY_920_DATA 0x00000000
+#define DDRSS0_PHY_921_DATA 0x00000000
+#define DDRSS0_PHY_922_DATA 0x00000000
+#define DDRSS0_PHY_923_DATA 0x00000000
+#define DDRSS0_PHY_924_DATA 0x00000000
+#define DDRSS0_PHY_925_DATA 0x00000000
+#define DDRSS0_PHY_926_DATA 0x00000000
+#define DDRSS0_PHY_927_DATA 0x00000000
+#define DDRSS0_PHY_928_DATA 0x00000000
+#define DDRSS0_PHY_929_DATA 0x00000000
+#define DDRSS0_PHY_930_DATA 0x00000000
+#define DDRSS0_PHY_931_DATA 0x00000000
+#define DDRSS0_PHY_932_DATA 0x00000000
+#define DDRSS0_PHY_933_DATA 0x00000000
+#define DDRSS0_PHY_934_DATA 0x00000000
+#define DDRSS0_PHY_935_DATA 0x00000000
+#define DDRSS0_PHY_936_DATA 0x00000000
+#define DDRSS0_PHY_937_DATA 0x00000000
+#define DDRSS0_PHY_938_DATA 0x00000000
+#define DDRSS0_PHY_939_DATA 0x00000000
+#define DDRSS0_PHY_940_DATA 0x00000000
+#define DDRSS0_PHY_941_DATA 0x00000000
+#define DDRSS0_PHY_942_DATA 0x00000000
+#define DDRSS0_PHY_943_DATA 0x00000000
+#define DDRSS0_PHY_944_DATA 0x00000000
+#define DDRSS0_PHY_945_DATA 0x00000000
+#define DDRSS0_PHY_946_DATA 0x00000000
+#define DDRSS0_PHY_947_DATA 0x00000000
+#define DDRSS0_PHY_948_DATA 0x00000000
+#define DDRSS0_PHY_949_DATA 0x00000000
+#define DDRSS0_PHY_950_DATA 0x00000000
+#define DDRSS0_PHY_951_DATA 0x00000000
+#define DDRSS0_PHY_952_DATA 0x00000000
+#define DDRSS0_PHY_953_DATA 0x00000000
+#define DDRSS0_PHY_954_DATA 0x00000000
+#define DDRSS0_PHY_955_DATA 0x00000000
+#define DDRSS0_PHY_956_DATA 0x00000000
+#define DDRSS0_PHY_957_DATA 0x00000000
+#define DDRSS0_PHY_958_DATA 0x00000000
+#define DDRSS0_PHY_959_DATA 0x00000000
+#define DDRSS0_PHY_960_DATA 0x00000000
+#define DDRSS0_PHY_961_DATA 0x00000000
+#define DDRSS0_PHY_962_DATA 0x00000000
+#define DDRSS0_PHY_963_DATA 0x00000000
+#define DDRSS0_PHY_964_DATA 0x00000000
+#define DDRSS0_PHY_965_DATA 0x00000000
+#define DDRSS0_PHY_966_DATA 0x00000000
+#define DDRSS0_PHY_967_DATA 0x00000000
+#define DDRSS0_PHY_968_DATA 0x00000000
+#define DDRSS0_PHY_969_DATA 0x00000000
+#define DDRSS0_PHY_970_DATA 0x00000000
+#define DDRSS0_PHY_971_DATA 0x00000000
+#define DDRSS0_PHY_972_DATA 0x00000000
+#define DDRSS0_PHY_973_DATA 0x00000000
+#define DDRSS0_PHY_974_DATA 0x00000000
+#define DDRSS0_PHY_975_DATA 0x00000000
+#define DDRSS0_PHY_976_DATA 0x00000000
+#define DDRSS0_PHY_977_DATA 0x00000000
+#define DDRSS0_PHY_978_DATA 0x00000000
+#define DDRSS0_PHY_979_DATA 0x00000000
+#define DDRSS0_PHY_980_DATA 0x00000000
+#define DDRSS0_PHY_981_DATA 0x00000000
+#define DDRSS0_PHY_982_DATA 0x00000000
+#define DDRSS0_PHY_983_DATA 0x00000000
+#define DDRSS0_PHY_984_DATA 0x00000000
+#define DDRSS0_PHY_985_DATA 0x00000000
+#define DDRSS0_PHY_986_DATA 0x00000000
+#define DDRSS0_PHY_987_DATA 0x00000000
+#define DDRSS0_PHY_988_DATA 0x00000000
+#define DDRSS0_PHY_989_DATA 0x00000000
+#define DDRSS0_PHY_990_DATA 0x00000000
+#define DDRSS0_PHY_991_DATA 0x00000000
+#define DDRSS0_PHY_992_DATA 0x00000000
+#define DDRSS0_PHY_993_DATA 0x00000000
+#define DDRSS0_PHY_994_DATA 0x00000000
+#define DDRSS0_PHY_995_DATA 0x00000000
+#define DDRSS0_PHY_996_DATA 0x00000000
+#define DDRSS0_PHY_997_DATA 0x00000000
+#define DDRSS0_PHY_998_DATA 0x00000000
+#define DDRSS0_PHY_999_DATA 0x00000000
+#define DDRSS0_PHY_1000_DATA 0x00000000
+#define DDRSS0_PHY_1001_DATA 0x00000000
+#define DDRSS0_PHY_1002_DATA 0x00000000
+#define DDRSS0_PHY_1003_DATA 0x00000000
+#define DDRSS0_PHY_1004_DATA 0x00000000
+#define DDRSS0_PHY_1005_DATA 0x00000000
+#define DDRSS0_PHY_1006_DATA 0x00000000
+#define DDRSS0_PHY_1007_DATA 0x00000000
+#define DDRSS0_PHY_1008_DATA 0x00000000
+#define DDRSS0_PHY_1009_DATA 0x00000000
+#define DDRSS0_PHY_1010_DATA 0x00000000
+#define DDRSS0_PHY_1011_DATA 0x00000000
+#define DDRSS0_PHY_1012_DATA 0x00000000
+#define DDRSS0_PHY_1013_DATA 0x00000000
+#define DDRSS0_PHY_1014_DATA 0x00000000
+#define DDRSS0_PHY_1015_DATA 0x00000000
+#define DDRSS0_PHY_1016_DATA 0x00000000
+#define DDRSS0_PHY_1017_DATA 0x00000000
+#define DDRSS0_PHY_1018_DATA 0x00000000
+#define DDRSS0_PHY_1019_DATA 0x00000000
+#define DDRSS0_PHY_1020_DATA 0x00000000
+#define DDRSS0_PHY_1021_DATA 0x00000000
+#define DDRSS0_PHY_1022_DATA 0x00000000
+#define DDRSS0_PHY_1023_DATA 0x00000000
+#define DDRSS0_PHY_1024_DATA 0x00000000
+#define DDRSS0_PHY_1025_DATA 0x00000000
+#define DDRSS0_PHY_1026_DATA 0x00000000
+#define DDRSS0_PHY_1027_DATA 0x00000000
+#define DDRSS0_PHY_1028_DATA 0x00000000
+#define DDRSS0_PHY_1029_DATA 0x00000100
+#define DDRSS0_PHY_1030_DATA 0x00000200
+#define DDRSS0_PHY_1031_DATA 0x00000000
+#define DDRSS0_PHY_1032_DATA 0x00000000
+#define DDRSS0_PHY_1033_DATA 0x00000000
+#define DDRSS0_PHY_1034_DATA 0x00000000
+#define DDRSS0_PHY_1035_DATA 0x00400000
+#define DDRSS0_PHY_1036_DATA 0x00000080
+#define DDRSS0_PHY_1037_DATA 0x00DCBA98
+#define DDRSS0_PHY_1038_DATA 0x03000000
+#define DDRSS0_PHY_1039_DATA 0x00200000
+#define DDRSS0_PHY_1040_DATA 0x00000000
+#define DDRSS0_PHY_1041_DATA 0x00000000
+#define DDRSS0_PHY_1042_DATA 0x00000000
+#define DDRSS0_PHY_1043_DATA 0x00000000
+#define DDRSS0_PHY_1044_DATA 0x00000000
+#define DDRSS0_PHY_1045_DATA 0x0000002A
+#define DDRSS0_PHY_1046_DATA 0x00000015
+#define DDRSS0_PHY_1047_DATA 0x00000015
+#define DDRSS0_PHY_1048_DATA 0x0000002A
+#define DDRSS0_PHY_1049_DATA 0x00000033
+#define DDRSS0_PHY_1050_DATA 0x0000000C
+#define DDRSS0_PHY_1051_DATA 0x0000000C
+#define DDRSS0_PHY_1052_DATA 0x00000033
+#define DDRSS0_PHY_1053_DATA 0x00543210
+#define DDRSS0_PHY_1054_DATA 0x003F0000
+#define DDRSS0_PHY_1055_DATA 0x000F013F
+#define DDRSS0_PHY_1056_DATA 0x20202003
+#define DDRSS0_PHY_1057_DATA 0x00202020
+#define DDRSS0_PHY_1058_DATA 0x20008008
+#define DDRSS0_PHY_1059_DATA 0x00000810
+#define DDRSS0_PHY_1060_DATA 0x00000F00
+#define DDRSS0_PHY_1061_DATA 0x00000000
+#define DDRSS0_PHY_1062_DATA 0x00000000
+#define DDRSS0_PHY_1063_DATA 0x00000000
+#define DDRSS0_PHY_1064_DATA 0x000305CC
+#define DDRSS0_PHY_1065_DATA 0x00030000
+#define DDRSS0_PHY_1066_DATA 0x00000300
+#define DDRSS0_PHY_1067_DATA 0x00000300
+#define DDRSS0_PHY_1068_DATA 0x00000300
+#define DDRSS0_PHY_1069_DATA 0x00000300
+#define DDRSS0_PHY_1070_DATA 0x00000300
+#define DDRSS0_PHY_1071_DATA 0x42080010
+#define DDRSS0_PHY_1072_DATA 0x0000803E
+#define DDRSS0_PHY_1073_DATA 0x00000001
+#define DDRSS0_PHY_1074_DATA 0x01000102
+#define DDRSS0_PHY_1075_DATA 0x00008000
+#define DDRSS0_PHY_1076_DATA 0x00000000
+#define DDRSS0_PHY_1077_DATA 0x00000000
+#define DDRSS0_PHY_1078_DATA 0x00000000
+#define DDRSS0_PHY_1079_DATA 0x00000000
+#define DDRSS0_PHY_1080_DATA 0x00000000
+#define DDRSS0_PHY_1081_DATA 0x00000000
+#define DDRSS0_PHY_1082_DATA 0x00000000
+#define DDRSS0_PHY_1083_DATA 0x00000000
+#define DDRSS0_PHY_1084_DATA 0x00000000
+#define DDRSS0_PHY_1085_DATA 0x00000000
+#define DDRSS0_PHY_1086_DATA 0x00000000
+#define DDRSS0_PHY_1087_DATA 0x00000000
+#define DDRSS0_PHY_1088_DATA 0x00000000
+#define DDRSS0_PHY_1089_DATA 0x00000000
+#define DDRSS0_PHY_1090_DATA 0x00000000
+#define DDRSS0_PHY_1091_DATA 0x00000000
+#define DDRSS0_PHY_1092_DATA 0x00000000
+#define DDRSS0_PHY_1093_DATA 0x00000000
+#define DDRSS0_PHY_1094_DATA 0x00000000
+#define DDRSS0_PHY_1095_DATA 0x00000000
+#define DDRSS0_PHY_1096_DATA 0x00000000
+#define DDRSS0_PHY_1097_DATA 0x00000000
+#define DDRSS0_PHY_1098_DATA 0x00000000
+#define DDRSS0_PHY_1099_DATA 0x00000000
+#define DDRSS0_PHY_1100_DATA 0x00000000
+#define DDRSS0_PHY_1101_DATA 0x00000000
+#define DDRSS0_PHY_1102_DATA 0x00000000
+#define DDRSS0_PHY_1103_DATA 0x00000000
+#define DDRSS0_PHY_1104_DATA 0x00000000
+#define DDRSS0_PHY_1105_DATA 0x00000000
+#define DDRSS0_PHY_1106_DATA 0x00000000
+#define DDRSS0_PHY_1107_DATA 0x00000000
+#define DDRSS0_PHY_1108_DATA 0x00000000
+#define DDRSS0_PHY_1109_DATA 0x00000000
+#define DDRSS0_PHY_1110_DATA 0x00000000
+#define DDRSS0_PHY_1111_DATA 0x00000000
+#define DDRSS0_PHY_1112_DATA 0x00000000
+#define DDRSS0_PHY_1113_DATA 0x00000000
+#define DDRSS0_PHY_1114_DATA 0x00000000
+#define DDRSS0_PHY_1115_DATA 0x00000000
+#define DDRSS0_PHY_1116_DATA 0x00000000
+#define DDRSS0_PHY_1117_DATA 0x00000000
+#define DDRSS0_PHY_1118_DATA 0x00000000
+#define DDRSS0_PHY_1119_DATA 0x00000000
+#define DDRSS0_PHY_1120_DATA 0x00000000
+#define DDRSS0_PHY_1121_DATA 0x00000000
+#define DDRSS0_PHY_1122_DATA 0x00000000
+#define DDRSS0_PHY_1123_DATA 0x00000000
+#define DDRSS0_PHY_1124_DATA 0x00000000
+#define DDRSS0_PHY_1125_DATA 0x00000000
+#define DDRSS0_PHY_1126_DATA 0x00000000
+#define DDRSS0_PHY_1127_DATA 0x00000000
+#define DDRSS0_PHY_1128_DATA 0x00000000
+#define DDRSS0_PHY_1129_DATA 0x00000000
+#define DDRSS0_PHY_1130_DATA 0x00000000
+#define DDRSS0_PHY_1131_DATA 0x00000000
+#define DDRSS0_PHY_1132_DATA 0x00000000
+#define DDRSS0_PHY_1133_DATA 0x00000000
+#define DDRSS0_PHY_1134_DATA 0x00000000
+#define DDRSS0_PHY_1135_DATA 0x00000000
+#define DDRSS0_PHY_1136_DATA 0x00000000
+#define DDRSS0_PHY_1137_DATA 0x00000000
+#define DDRSS0_PHY_1138_DATA 0x00000000
+#define DDRSS0_PHY_1139_DATA 0x00000000
+#define DDRSS0_PHY_1140_DATA 0x00000000
+#define DDRSS0_PHY_1141_DATA 0x00000000
+#define DDRSS0_PHY_1142_DATA 0x00000000
+#define DDRSS0_PHY_1143_DATA 0x00000000
+#define DDRSS0_PHY_1144_DATA 0x00000000
+#define DDRSS0_PHY_1145_DATA 0x00000000
+#define DDRSS0_PHY_1146_DATA 0x00000000
+#define DDRSS0_PHY_1147_DATA 0x00000000
+#define DDRSS0_PHY_1148_DATA 0x00000000
+#define DDRSS0_PHY_1149_DATA 0x00000000
+#define DDRSS0_PHY_1150_DATA 0x00000000
+#define DDRSS0_PHY_1151_DATA 0x00000000
+#define DDRSS0_PHY_1152_DATA 0x00000000
+#define DDRSS0_PHY_1153_DATA 0x00000000
+#define DDRSS0_PHY_1154_DATA 0x00000000
+#define DDRSS0_PHY_1155_DATA 0x00000000
+#define DDRSS0_PHY_1156_DATA 0x00000000
+#define DDRSS0_PHY_1157_DATA 0x00000000
+#define DDRSS0_PHY_1158_DATA 0x00000000
+#define DDRSS0_PHY_1159_DATA 0x00000000
+#define DDRSS0_PHY_1160_DATA 0x00000000
+#define DDRSS0_PHY_1161_DATA 0x00000000
+#define DDRSS0_PHY_1162_DATA 0x00000000
+#define DDRSS0_PHY_1163_DATA 0x00000000
+#define DDRSS0_PHY_1164_DATA 0x00000000
+#define DDRSS0_PHY_1165_DATA 0x00000000
+#define DDRSS0_PHY_1166_DATA 0x00000000
+#define DDRSS0_PHY_1167_DATA 0x00000000
+#define DDRSS0_PHY_1168_DATA 0x00000000
+#define DDRSS0_PHY_1169_DATA 0x00000000
+#define DDRSS0_PHY_1170_DATA 0x00000000
+#define DDRSS0_PHY_1171_DATA 0x00000000
+#define DDRSS0_PHY_1172_DATA 0x00000000
+#define DDRSS0_PHY_1173_DATA 0x00000000
+#define DDRSS0_PHY_1174_DATA 0x00000000
+#define DDRSS0_PHY_1175_DATA 0x00000000
+#define DDRSS0_PHY_1176_DATA 0x00000000
+#define DDRSS0_PHY_1177_DATA 0x00000000
+#define DDRSS0_PHY_1178_DATA 0x00000000
+#define DDRSS0_PHY_1179_DATA 0x00000000
+#define DDRSS0_PHY_1180_DATA 0x00000000
+#define DDRSS0_PHY_1181_DATA 0x00000000
+#define DDRSS0_PHY_1182_DATA 0x00000000
+#define DDRSS0_PHY_1183_DATA 0x00000000
+#define DDRSS0_PHY_1184_DATA 0x00000000
+#define DDRSS0_PHY_1185_DATA 0x00000000
+#define DDRSS0_PHY_1186_DATA 0x00000000
+#define DDRSS0_PHY_1187_DATA 0x00000000
+#define DDRSS0_PHY_1188_DATA 0x00000000
+#define DDRSS0_PHY_1189_DATA 0x00000000
+#define DDRSS0_PHY_1190_DATA 0x00000000
+#define DDRSS0_PHY_1191_DATA 0x00000000
+#define DDRSS0_PHY_1192_DATA 0x00000000
+#define DDRSS0_PHY_1193_DATA 0x00000000
+#define DDRSS0_PHY_1194_DATA 0x00000000
+#define DDRSS0_PHY_1195_DATA 0x00000000
+#define DDRSS0_PHY_1196_DATA 0x00000000
+#define DDRSS0_PHY_1197_DATA 0x00000000
+#define DDRSS0_PHY_1198_DATA 0x00000000
+#define DDRSS0_PHY_1199_DATA 0x00000000
+#define DDRSS0_PHY_1200_DATA 0x00000000
+#define DDRSS0_PHY_1201_DATA 0x00000000
+#define DDRSS0_PHY_1202_DATA 0x00000000
+#define DDRSS0_PHY_1203_DATA 0x00000000
+#define DDRSS0_PHY_1204_DATA 0x00000000
+#define DDRSS0_PHY_1205_DATA 0x00000000
+#define DDRSS0_PHY_1206_DATA 0x00000000
+#define DDRSS0_PHY_1207_DATA 0x00000000
+#define DDRSS0_PHY_1208_DATA 0x00000000
+#define DDRSS0_PHY_1209_DATA 0x00000000
+#define DDRSS0_PHY_1210_DATA 0x00000000
+#define DDRSS0_PHY_1211_DATA 0x00000000
+#define DDRSS0_PHY_1212_DATA 0x00000000
+#define DDRSS0_PHY_1213_DATA 0x00000000
+#define DDRSS0_PHY_1214_DATA 0x00000000
+#define DDRSS0_PHY_1215_DATA 0x00000000
+#define DDRSS0_PHY_1216_DATA 0x00000000
+#define DDRSS0_PHY_1217_DATA 0x00000000
+#define DDRSS0_PHY_1218_DATA 0x00000000
+#define DDRSS0_PHY_1219_DATA 0x00000000
+#define DDRSS0_PHY_1220_DATA 0x00000000
+#define DDRSS0_PHY_1221_DATA 0x00000000
+#define DDRSS0_PHY_1222_DATA 0x00000000
+#define DDRSS0_PHY_1223_DATA 0x00000000
+#define DDRSS0_PHY_1224_DATA 0x00000000
+#define DDRSS0_PHY_1225_DATA 0x00000000
+#define DDRSS0_PHY_1226_DATA 0x00000000
+#define DDRSS0_PHY_1227_DATA 0x00000000
+#define DDRSS0_PHY_1228_DATA 0x00000000
+#define DDRSS0_PHY_1229_DATA 0x00000000
+#define DDRSS0_PHY_1230_DATA 0x00000000
+#define DDRSS0_PHY_1231_DATA 0x00000000
+#define DDRSS0_PHY_1232_DATA 0x00000000
+#define DDRSS0_PHY_1233_DATA 0x00000000
+#define DDRSS0_PHY_1234_DATA 0x00000000
+#define DDRSS0_PHY_1235_DATA 0x00000000
+#define DDRSS0_PHY_1236_DATA 0x00000000
+#define DDRSS0_PHY_1237_DATA 0x00000000
+#define DDRSS0_PHY_1238_DATA 0x00000000
+#define DDRSS0_PHY_1239_DATA 0x00000000
+#define DDRSS0_PHY_1240_DATA 0x00000000
+#define DDRSS0_PHY_1241_DATA 0x00000000
+#define DDRSS0_PHY_1242_DATA 0x00000000
+#define DDRSS0_PHY_1243_DATA 0x00000000
+#define DDRSS0_PHY_1244_DATA 0x00000000
+#define DDRSS0_PHY_1245_DATA 0x00000000
+#define DDRSS0_PHY_1246_DATA 0x00000000
+#define DDRSS0_PHY_1247_DATA 0x00000000
+#define DDRSS0_PHY_1248_DATA 0x00000000
+#define DDRSS0_PHY_1249_DATA 0x00000000
+#define DDRSS0_PHY_1250_DATA 0x00000000
+#define DDRSS0_PHY_1251_DATA 0x00000000
+#define DDRSS0_PHY_1252_DATA 0x00000000
+#define DDRSS0_PHY_1253_DATA 0x00000000
+#define DDRSS0_PHY_1254_DATA 0x00000000
+#define DDRSS0_PHY_1255_DATA 0x00000000
+#define DDRSS0_PHY_1256_DATA 0x00000000
+#define DDRSS0_PHY_1257_DATA 0x00000000
+#define DDRSS0_PHY_1258_DATA 0x00000000
+#define DDRSS0_PHY_1259_DATA 0x00000000
+#define DDRSS0_PHY_1260_DATA 0x00000000
+#define DDRSS0_PHY_1261_DATA 0x00000000
+#define DDRSS0_PHY_1262_DATA 0x00000000
+#define DDRSS0_PHY_1263_DATA 0x00000000
+#define DDRSS0_PHY_1264_DATA 0x00000000
+#define DDRSS0_PHY_1265_DATA 0x00000000
+#define DDRSS0_PHY_1266_DATA 0x00000000
+#define DDRSS0_PHY_1267_DATA 0x00000000
+#define DDRSS0_PHY_1268_DATA 0x00000000
+#define DDRSS0_PHY_1269_DATA 0x00000000
+#define DDRSS0_PHY_1270_DATA 0x00000000
+#define DDRSS0_PHY_1271_DATA 0x00000000
+#define DDRSS0_PHY_1272_DATA 0x00000000
+#define DDRSS0_PHY_1273_DATA 0x00000000
+#define DDRSS0_PHY_1274_DATA 0x00000000
+#define DDRSS0_PHY_1275_DATA 0x00000000
+#define DDRSS0_PHY_1276_DATA 0x00000000
+#define DDRSS0_PHY_1277_DATA 0x00000000
+#define DDRSS0_PHY_1278_DATA 0x00000000
+#define DDRSS0_PHY_1279_DATA 0x00000000
+#define DDRSS0_PHY_1280_DATA 0x00000000
+#define DDRSS0_PHY_1281_DATA 0x00010100
+#define DDRSS0_PHY_1282_DATA 0x00000000
+#define DDRSS0_PHY_1283_DATA 0x00000000
+#define DDRSS0_PHY_1284_DATA 0x00050000
+#define DDRSS0_PHY_1285_DATA 0x04000000
+#define DDRSS0_PHY_1286_DATA 0x00000055
+#define DDRSS0_PHY_1287_DATA 0x00000000
+#define DDRSS0_PHY_1288_DATA 0x00000000
+#define DDRSS0_PHY_1289_DATA 0x00000000
+#define DDRSS0_PHY_1290_DATA 0x00000000
+#define DDRSS0_PHY_1291_DATA 0x00002001
+#define DDRSS0_PHY_1292_DATA 0x0000400F
+#define DDRSS0_PHY_1293_DATA 0x50020028
+#define DDRSS0_PHY_1294_DATA 0x01010000
+#define DDRSS0_PHY_1295_DATA 0x80080001
+#define DDRSS0_PHY_1296_DATA 0x10200000
+#define DDRSS0_PHY_1297_DATA 0x00000008
+#define DDRSS0_PHY_1298_DATA 0x00000000
+#define DDRSS0_PHY_1299_DATA 0x01090E00
+#define DDRSS0_PHY_1300_DATA 0x00040101
+#define DDRSS0_PHY_1301_DATA 0x0000010F
+#define DDRSS0_PHY_1302_DATA 0x00000000
+#define DDRSS0_PHY_1303_DATA 0x0000FFFF
+#define DDRSS0_PHY_1304_DATA 0x00000000
+#define DDRSS0_PHY_1305_DATA 0x01010000
+#define DDRSS0_PHY_1306_DATA 0x01080402
+#define DDRSS0_PHY_1307_DATA 0x01200F02
+#define DDRSS0_PHY_1308_DATA 0x00194280
+#define DDRSS0_PHY_1309_DATA 0x00000004
+#define DDRSS0_PHY_1310_DATA 0x00042000
+#define DDRSS0_PHY_1311_DATA 0x00000000
+#define DDRSS0_PHY_1312_DATA 0x00000000
+#define DDRSS0_PHY_1313_DATA 0x00000000
+#define DDRSS0_PHY_1314_DATA 0x00000000
+#define DDRSS0_PHY_1315_DATA 0x00000000
+#define DDRSS0_PHY_1316_DATA 0x00000000
+#define DDRSS0_PHY_1317_DATA 0x01000000
+#define DDRSS0_PHY_1318_DATA 0x00000705
+#define DDRSS0_PHY_1319_DATA 0x00000054
+#define DDRSS0_PHY_1320_DATA 0x00030820
+#define DDRSS0_PHY_1321_DATA 0x00010820
+#define DDRSS0_PHY_1322_DATA 0x00010820
+#define DDRSS0_PHY_1323_DATA 0x00010820
+#define DDRSS0_PHY_1324_DATA 0x00010820
+#define DDRSS0_PHY_1325_DATA 0x00010820
+#define DDRSS0_PHY_1326_DATA 0x00010820
+#define DDRSS0_PHY_1327_DATA 0x00010820
+#define DDRSS0_PHY_1328_DATA 0x00010820
+#define DDRSS0_PHY_1329_DATA 0x00000000
+#define DDRSS0_PHY_1330_DATA 0x00000074
+#define DDRSS0_PHY_1331_DATA 0x00000400
+#define DDRSS0_PHY_1332_DATA 0x00000108
+#define DDRSS0_PHY_1333_DATA 0x00000000
+#define DDRSS0_PHY_1334_DATA 0x00000000
+#define DDRSS0_PHY_1335_DATA 0x00000000
+#define DDRSS0_PHY_1336_DATA 0x00000000
+#define DDRSS0_PHY_1337_DATA 0x00000000
+#define DDRSS0_PHY_1338_DATA 0x03000000
+#define DDRSS0_PHY_1339_DATA 0x00000000
+#define DDRSS0_PHY_1340_DATA 0x00000000
+#define DDRSS0_PHY_1341_DATA 0x00000000
+#define DDRSS0_PHY_1342_DATA 0x04102006
+#define DDRSS0_PHY_1343_DATA 0x00041020
+#define DDRSS0_PHY_1344_DATA 0x01C98C98
+#define DDRSS0_PHY_1345_DATA 0x3F400000
+#define DDRSS0_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS0_PHY_1347_DATA 0x0000001F
+#define DDRSS0_PHY_1348_DATA 0x00000000
+#define DDRSS0_PHY_1349_DATA 0x00000000
+#define DDRSS0_PHY_1350_DATA 0x00000000
+#define DDRSS0_PHY_1351_DATA 0x00010000
+#define DDRSS0_PHY_1352_DATA 0x00000000
+#define DDRSS0_PHY_1353_DATA 0x00000000
+#define DDRSS0_PHY_1354_DATA 0x00000000
+#define DDRSS0_PHY_1355_DATA 0x00000000
+#define DDRSS0_PHY_1356_DATA 0x76543210
+#define DDRSS0_PHY_1357_DATA 0x00010198
+#define DDRSS0_PHY_1358_DATA 0x00000000
+#define DDRSS0_PHY_1359_DATA 0x00000000
+#define DDRSS0_PHY_1360_DATA 0x00000000
+#define DDRSS0_PHY_1361_DATA 0x00040700
+#define DDRSS0_PHY_1362_DATA 0x00000000
+#define DDRSS0_PHY_1363_DATA 0x00000000
+#define DDRSS0_PHY_1364_DATA 0x00000000
+#define DDRSS0_PHY_1365_DATA 0x00000000
+#define DDRSS0_PHY_1366_DATA 0x00000000
+#define DDRSS0_PHY_1367_DATA 0x00000002
+#define DDRSS0_PHY_1368_DATA 0x00000000
+#define DDRSS0_PHY_1369_DATA 0x00000000
+#define DDRSS0_PHY_1370_DATA 0x00000000
+#define DDRSS0_PHY_1371_DATA 0x00000000
+#define DDRSS0_PHY_1372_DATA 0x00000000
+#define DDRSS0_PHY_1373_DATA 0x00000000
+#define DDRSS0_PHY_1374_DATA 0x00080000
+#define DDRSS0_PHY_1375_DATA 0x000007FF
+#define DDRSS0_PHY_1376_DATA 0x00000000
+#define DDRSS0_PHY_1377_DATA 0x00000000
+#define DDRSS0_PHY_1378_DATA 0x00000000
+#define DDRSS0_PHY_1379_DATA 0x00000000
+#define DDRSS0_PHY_1380_DATA 0x00000000
+#define DDRSS0_PHY_1381_DATA 0x00000000
+#define DDRSS0_PHY_1382_DATA 0x000FFFFF
+#define DDRSS0_PHY_1383_DATA 0x000FFFFF
+#define DDRSS0_PHY_1384_DATA 0x0000FFFF
+#define DDRSS0_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS0_PHY_1386_DATA 0x030FFFFF
+#define DDRSS0_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS0_PHY_1388_DATA 0x0000FFFF
+#define DDRSS0_PHY_1389_DATA 0x00000000
+#define DDRSS0_PHY_1390_DATA 0x00000000
+#define DDRSS0_PHY_1391_DATA 0x00000000
+#define DDRSS0_PHY_1392_DATA 0x00000000
+#define DDRSS0_PHY_1393_DATA 0x0001F7C0
+#define DDRSS0_PHY_1394_DATA 0x00000003
+#define DDRSS0_PHY_1395_DATA 0x00000000
+#define DDRSS0_PHY_1396_DATA 0x00001142
+#define DDRSS0_PHY_1397_DATA 0x010207AB
+#define DDRSS0_PHY_1398_DATA 0x01000080
+#define DDRSS0_PHY_1399_DATA 0x03900390
+#define DDRSS0_PHY_1400_DATA 0x03900390
+#define DDRSS0_PHY_1401_DATA 0x00000390
+#define DDRSS0_PHY_1402_DATA 0x00000390
+#define DDRSS0_PHY_1403_DATA 0x00000390
+#define DDRSS0_PHY_1404_DATA 0x00000390
+#define DDRSS0_PHY_1405_DATA 0x00000005
+#define DDRSS0_PHY_1406_DATA 0x01813FCC
+#define DDRSS0_PHY_1407_DATA 0x000000CC
+#define DDRSS0_PHY_1408_DATA 0x0C000DFF
+#define DDRSS0_PHY_1409_DATA 0x30000DFF
+#define DDRSS0_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1411_DATA 0x000100F0
+#define DDRSS0_PHY_1412_DATA 0x780DFFCC
+#define DDRSS0_PHY_1413_DATA 0x00007E31
+#define DDRSS0_PHY_1414_DATA 0x000CBF11
+#define DDRSS0_PHY_1415_DATA 0x01990010
+#define DDRSS0_PHY_1416_DATA 0x000CBF11
+#define DDRSS0_PHY_1417_DATA 0x01990010
+#define DDRSS0_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1419_DATA 0x00EF00F0
+#define DDRSS0_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS0_PHY_1421_DATA 0x01FF00F0
+#define DDRSS0_PHY_1422_DATA 0x20040006
+
+#define DDRSS1_CTL_00_DATA 0x00000B00
+#define DDRSS1_CTL_01_DATA 0x00000000
+#define DDRSS1_CTL_02_DATA 0x00000000
+#define DDRSS1_CTL_03_DATA 0x00000000
+#define DDRSS1_CTL_04_DATA 0x00000000
+#define DDRSS1_CTL_05_DATA 0x00000000
+#define DDRSS1_CTL_06_DATA 0x00000000
+#define DDRSS1_CTL_07_DATA 0x00002AF8
+#define DDRSS1_CTL_08_DATA 0x0001ADAF
+#define DDRSS1_CTL_09_DATA 0x00000005
+#define DDRSS1_CTL_10_DATA 0x0000006E
+#define DDRSS1_CTL_11_DATA 0x000681C8
+#define DDRSS1_CTL_12_DATA 0x004111C9
+#define DDRSS1_CTL_13_DATA 0x00000005
+#define DDRSS1_CTL_14_DATA 0x000010A9
+#define DDRSS1_CTL_15_DATA 0x000681C8
+#define DDRSS1_CTL_16_DATA 0x004111C9
+#define DDRSS1_CTL_17_DATA 0x00000005
+#define DDRSS1_CTL_18_DATA 0x000010A9
+#define DDRSS1_CTL_19_DATA 0x01010000
+#define DDRSS1_CTL_20_DATA 0x02011001
+#define DDRSS1_CTL_21_DATA 0x02010000
+#define DDRSS1_CTL_22_DATA 0x00020100
+#define DDRSS1_CTL_23_DATA 0x0000000B
+#define DDRSS1_CTL_24_DATA 0x0000001C
+#define DDRSS1_CTL_25_DATA 0x00000000
+#define DDRSS1_CTL_26_DATA 0x00000000
+#define DDRSS1_CTL_27_DATA 0x03020200
+#define DDRSS1_CTL_28_DATA 0x00005656
+#define DDRSS1_CTL_29_DATA 0x00100000
+#define DDRSS1_CTL_30_DATA 0x00000000
+#define DDRSS1_CTL_31_DATA 0x00000000
+#define DDRSS1_CTL_32_DATA 0x00000000
+#define DDRSS1_CTL_33_DATA 0x00000000
+#define DDRSS1_CTL_34_DATA 0x040C0000
+#define DDRSS1_CTL_35_DATA 0x12481248
+#define DDRSS1_CTL_36_DATA 0x00050804
+#define DDRSS1_CTL_37_DATA 0x09040008
+#define DDRSS1_CTL_38_DATA 0x15000204
+#define DDRSS1_CTL_39_DATA 0x1760008B
+#define DDRSS1_CTL_40_DATA 0x1500422B
+#define DDRSS1_CTL_41_DATA 0x1760008B
+#define DDRSS1_CTL_42_DATA 0x2000422B
+#define DDRSS1_CTL_43_DATA 0x000A0A09
+#define DDRSS1_CTL_44_DATA 0x0400078A
+#define DDRSS1_CTL_45_DATA 0x1E161104
+#define DDRSS1_CTL_46_DATA 0x10012458
+#define DDRSS1_CTL_47_DATA 0x1E161110
+#define DDRSS1_CTL_48_DATA 0x10012458
+#define DDRSS1_CTL_49_DATA 0x02030410
+#define DDRSS1_CTL_50_DATA 0x2C040500
+#define DDRSS1_CTL_51_DATA 0x08292C29
+#define DDRSS1_CTL_52_DATA 0x14000E0A
+#define DDRSS1_CTL_53_DATA 0x04010A0A
+#define DDRSS1_CTL_54_DATA 0x01010004
+#define DDRSS1_CTL_55_DATA 0x04545408
+#define DDRSS1_CTL_56_DATA 0x04313104
+#define DDRSS1_CTL_57_DATA 0x00003131
+#define DDRSS1_CTL_58_DATA 0x00010100
+#define DDRSS1_CTL_59_DATA 0x03010000
+#define DDRSS1_CTL_60_DATA 0x00001508
+#define DDRSS1_CTL_61_DATA 0x000000CE
+#define DDRSS1_CTL_62_DATA 0x0000032B
+#define DDRSS1_CTL_63_DATA 0x00002073
+#define DDRSS1_CTL_64_DATA 0x0000032B
+#define DDRSS1_CTL_65_DATA 0x00002073
+#define DDRSS1_CTL_66_DATA 0x00000005
+#define DDRSS1_CTL_67_DATA 0x00050000
+#define DDRSS1_CTL_68_DATA 0x00CB0012
+#define DDRSS1_CTL_69_DATA 0x00CB0408
+#define DDRSS1_CTL_70_DATA 0x00400408
+#define DDRSS1_CTL_71_DATA 0x00120103
+#define DDRSS1_CTL_72_DATA 0x00100005
+#define DDRSS1_CTL_73_DATA 0x2F080010
+#define DDRSS1_CTL_74_DATA 0x0505012F
+#define DDRSS1_CTL_75_DATA 0x0401030A
+#define DDRSS1_CTL_76_DATA 0x041E100B
+#define DDRSS1_CTL_77_DATA 0x100B0401
+#define DDRSS1_CTL_78_DATA 0x0001041E
+#define DDRSS1_CTL_79_DATA 0x00160016
+#define DDRSS1_CTL_80_DATA 0x033B033B
+#define DDRSS1_CTL_81_DATA 0x033B033B
+#define DDRSS1_CTL_82_DATA 0x03050505
+#define DDRSS1_CTL_83_DATA 0x03010303
+#define DDRSS1_CTL_84_DATA 0x200B100B
+#define DDRSS1_CTL_85_DATA 0x04041004
+#define DDRSS1_CTL_86_DATA 0x200B100B
+#define DDRSS1_CTL_87_DATA 0x04041004
+#define DDRSS1_CTL_88_DATA 0x03010000
+#define DDRSS1_CTL_89_DATA 0x00010000
+#define DDRSS1_CTL_90_DATA 0x00000000
+#define DDRSS1_CTL_91_DATA 0x00000000
+#define DDRSS1_CTL_92_DATA 0x01000000
+#define DDRSS1_CTL_93_DATA 0x80104002
+#define DDRSS1_CTL_94_DATA 0x00000000
+#define DDRSS1_CTL_95_DATA 0x00040005
+#define DDRSS1_CTL_96_DATA 0x00000000
+#define DDRSS1_CTL_97_DATA 0x00050000
+#define DDRSS1_CTL_98_DATA 0x00000004
+#define DDRSS1_CTL_99_DATA 0x00000000
+#define DDRSS1_CTL_100_DATA 0x00040005
+#define DDRSS1_CTL_101_DATA 0x00000000
+#define DDRSS1_CTL_102_DATA 0x00003380
+#define DDRSS1_CTL_103_DATA 0x00003380
+#define DDRSS1_CTL_104_DATA 0x00003380
+#define DDRSS1_CTL_105_DATA 0x00003380
+#define DDRSS1_CTL_106_DATA 0x00003380
+#define DDRSS1_CTL_107_DATA 0x00000000
+#define DDRSS1_CTL_108_DATA 0x000005A2
+#define DDRSS1_CTL_109_DATA 0x00081CC0
+#define DDRSS1_CTL_110_DATA 0x00081CC0
+#define DDRSS1_CTL_111_DATA 0x00081CC0
+#define DDRSS1_CTL_112_DATA 0x00081CC0
+#define DDRSS1_CTL_113_DATA 0x00081CC0
+#define DDRSS1_CTL_114_DATA 0x00000000
+#define DDRSS1_CTL_115_DATA 0x0000E325
+#define DDRSS1_CTL_116_DATA 0x00081CC0
+#define DDRSS1_CTL_117_DATA 0x00081CC0
+#define DDRSS1_CTL_118_DATA 0x00081CC0
+#define DDRSS1_CTL_119_DATA 0x00081CC0
+#define DDRSS1_CTL_120_DATA 0x00081CC0
+#define DDRSS1_CTL_121_DATA 0x00000000
+#define DDRSS1_CTL_122_DATA 0x0000E325
+#define DDRSS1_CTL_123_DATA 0x00000000
+#define DDRSS1_CTL_124_DATA 0x00000000
+#define DDRSS1_CTL_125_DATA 0x00000000
+#define DDRSS1_CTL_126_DATA 0x00000000
+#define DDRSS1_CTL_127_DATA 0x00000000
+#define DDRSS1_CTL_128_DATA 0x00000000
+#define DDRSS1_CTL_129_DATA 0x00000000
+#define DDRSS1_CTL_130_DATA 0x00000000
+#define DDRSS1_CTL_131_DATA 0x0B030500
+#define DDRSS1_CTL_132_DATA 0x00040B04
+#define DDRSS1_CTL_133_DATA 0x0A090000
+#define DDRSS1_CTL_134_DATA 0x0A090701
+#define DDRSS1_CTL_135_DATA 0x0900000E
+#define DDRSS1_CTL_136_DATA 0x0907010A
+#define DDRSS1_CTL_137_DATA 0x00000E0A
+#define DDRSS1_CTL_138_DATA 0x07010A09
+#define DDRSS1_CTL_139_DATA 0x000E0A09
+#define DDRSS1_CTL_140_DATA 0x07000401
+#define DDRSS1_CTL_141_DATA 0x00000000
+#define DDRSS1_CTL_142_DATA 0x00000000
+#define DDRSS1_CTL_143_DATA 0x00000000
+#define DDRSS1_CTL_144_DATA 0x00000000
+#define DDRSS1_CTL_145_DATA 0x00000000
+#define DDRSS1_CTL_146_DATA 0x00000000
+#define DDRSS1_CTL_147_DATA 0x00000000
+#define DDRSS1_CTL_148_DATA 0x08080000
+#define DDRSS1_CTL_149_DATA 0x01000000
+#define DDRSS1_CTL_150_DATA 0x800000C0
+#define DDRSS1_CTL_151_DATA 0x800000C0
+#define DDRSS1_CTL_152_DATA 0x800000C0
+#define DDRSS1_CTL_153_DATA 0x00000000
+#define DDRSS1_CTL_154_DATA 0x00001500
+#define DDRSS1_CTL_155_DATA 0x00000000
+#define DDRSS1_CTL_156_DATA 0x00000001
+#define DDRSS1_CTL_157_DATA 0x00000002
+#define DDRSS1_CTL_158_DATA 0x0000100E
+#define DDRSS1_CTL_159_DATA 0x00000000
+#define DDRSS1_CTL_160_DATA 0x00000000
+#define DDRSS1_CTL_161_DATA 0x00000000
+#define DDRSS1_CTL_162_DATA 0x00000000
+#define DDRSS1_CTL_163_DATA 0x00000000
+#define DDRSS1_CTL_164_DATA 0x000B0000
+#define DDRSS1_CTL_165_DATA 0x000E0006
+#define DDRSS1_CTL_166_DATA 0x000E0404
+#define DDRSS1_CTL_167_DATA 0x00D601AB
+#define DDRSS1_CTL_168_DATA 0x10100216
+#define DDRSS1_CTL_169_DATA 0x01AB0216
+#define DDRSS1_CTL_170_DATA 0x021600D6
+#define DDRSS1_CTL_171_DATA 0x02161010
+#define DDRSS1_CTL_172_DATA 0x00000000
+#define DDRSS1_CTL_173_DATA 0x00000000
+#define DDRSS1_CTL_174_DATA 0x00000000
+#define DDRSS1_CTL_175_DATA 0x3FF40084
+#define DDRSS1_CTL_176_DATA 0x33003FF4
+#define DDRSS1_CTL_177_DATA 0x00003333
+#define DDRSS1_CTL_178_DATA 0x35000000
+#define DDRSS1_CTL_179_DATA 0x27270035
+#define DDRSS1_CTL_180_DATA 0x0F0F0000
+#define DDRSS1_CTL_181_DATA 0x16000000
+#define DDRSS1_CTL_182_DATA 0x00841616
+#define DDRSS1_CTL_183_DATA 0x3FF43FF4
+#define DDRSS1_CTL_184_DATA 0x33333300
+#define DDRSS1_CTL_185_DATA 0x00000000
+#define DDRSS1_CTL_186_DATA 0x00353500
+#define DDRSS1_CTL_187_DATA 0x00002727
+#define DDRSS1_CTL_188_DATA 0x00000F0F
+#define DDRSS1_CTL_189_DATA 0x16161600
+#define DDRSS1_CTL_190_DATA 0x00000020
+#define DDRSS1_CTL_191_DATA 0x00000000
+#define DDRSS1_CTL_192_DATA 0x00000001
+#define DDRSS1_CTL_193_DATA 0x00000000
+#define DDRSS1_CTL_194_DATA 0x01000000
+#define DDRSS1_CTL_195_DATA 0x00000001
+#define DDRSS1_CTL_196_DATA 0x00000000
+#define DDRSS1_CTL_197_DATA 0x00000000
+#define DDRSS1_CTL_198_DATA 0x00000000
+#define DDRSS1_CTL_199_DATA 0x00000000
+#define DDRSS1_CTL_200_DATA 0x00000000
+#define DDRSS1_CTL_201_DATA 0x00000000
+#define DDRSS1_CTL_202_DATA 0x00000000
+#define DDRSS1_CTL_203_DATA 0x00000000
+#define DDRSS1_CTL_204_DATA 0x00000000
+#define DDRSS1_CTL_205_DATA 0x00000000
+#define DDRSS1_CTL_206_DATA 0x02000000
+#define DDRSS1_CTL_207_DATA 0x01080101
+#define DDRSS1_CTL_208_DATA 0x00000000
+#define DDRSS1_CTL_209_DATA 0x00000000
+#define DDRSS1_CTL_210_DATA 0x00000000
+#define DDRSS1_CTL_211_DATA 0x00000000
+#define DDRSS1_CTL_212_DATA 0x00000000
+#define DDRSS1_CTL_213_DATA 0x00000000
+#define DDRSS1_CTL_214_DATA 0x00000000
+#define DDRSS1_CTL_215_DATA 0x00000000
+#define DDRSS1_CTL_216_DATA 0x00000000
+#define DDRSS1_CTL_217_DATA 0x00000000
+#define DDRSS1_CTL_218_DATA 0x00000000
+#define DDRSS1_CTL_219_DATA 0x00000000
+#define DDRSS1_CTL_220_DATA 0x00000000
+#define DDRSS1_CTL_221_DATA 0x00000000
+#define DDRSS1_CTL_222_DATA 0x00001000
+#define DDRSS1_CTL_223_DATA 0x006403E8
+#define DDRSS1_CTL_224_DATA 0x00000000
+#define DDRSS1_CTL_225_DATA 0x00000000
+#define DDRSS1_CTL_226_DATA 0x00000000
+#define DDRSS1_CTL_227_DATA 0x15110000
+#define DDRSS1_CTL_228_DATA 0x00040C18
+#define DDRSS1_CTL_229_DATA 0xF000C000
+#define DDRSS1_CTL_230_DATA 0x0000F000
+#define DDRSS1_CTL_231_DATA 0x00000000
+#define DDRSS1_CTL_232_DATA 0x00000000
+#define DDRSS1_CTL_233_DATA 0xC0000000
+#define DDRSS1_CTL_234_DATA 0xF000F000
+#define DDRSS1_CTL_235_DATA 0x00000000
+#define DDRSS1_CTL_236_DATA 0x00000000
+#define DDRSS1_CTL_237_DATA 0x00000000
+#define DDRSS1_CTL_238_DATA 0xF000C000
+#define DDRSS1_CTL_239_DATA 0x0000F000
+#define DDRSS1_CTL_240_DATA 0x00000000
+#define DDRSS1_CTL_241_DATA 0x00000000
+#define DDRSS1_CTL_242_DATA 0x00030000
+#define DDRSS1_CTL_243_DATA 0x00000000
+#define DDRSS1_CTL_244_DATA 0x00000000
+#define DDRSS1_CTL_245_DATA 0x00000000
+#define DDRSS1_CTL_246_DATA 0x00000000
+#define DDRSS1_CTL_247_DATA 0x00000000
+#define DDRSS1_CTL_248_DATA 0x00000000
+#define DDRSS1_CTL_249_DATA 0x00000000
+#define DDRSS1_CTL_250_DATA 0x00000000
+#define DDRSS1_CTL_251_DATA 0x00000000
+#define DDRSS1_CTL_252_DATA 0x00000000
+#define DDRSS1_CTL_253_DATA 0x00000000
+#define DDRSS1_CTL_254_DATA 0x00000000
+#define DDRSS1_CTL_255_DATA 0x00000000
+#define DDRSS1_CTL_256_DATA 0x00000000
+#define DDRSS1_CTL_257_DATA 0x01000200
+#define DDRSS1_CTL_258_DATA 0x00370040
+#define DDRSS1_CTL_259_DATA 0x00020008
+#define DDRSS1_CTL_260_DATA 0x00400100
+#define DDRSS1_CTL_261_DATA 0x00400855
+#define DDRSS1_CTL_262_DATA 0x01000200
+#define DDRSS1_CTL_263_DATA 0x08550040
+#define DDRSS1_CTL_264_DATA 0x00000040
+#define DDRSS1_CTL_265_DATA 0x006B0003
+#define DDRSS1_CTL_266_DATA 0x0100006B
+#define DDRSS1_CTL_267_DATA 0x03030303
+#define DDRSS1_CTL_268_DATA 0x00000000
+#define DDRSS1_CTL_269_DATA 0x00000202
+#define DDRSS1_CTL_270_DATA 0x00001FFF
+#define DDRSS1_CTL_271_DATA 0x3FFF2000
+#define DDRSS1_CTL_272_DATA 0x03FF0000
+#define DDRSS1_CTL_273_DATA 0x000103FF
+#define DDRSS1_CTL_274_DATA 0x0FFF0B00
+#define DDRSS1_CTL_275_DATA 0x01010001
+#define DDRSS1_CTL_276_DATA 0x01010101
+#define DDRSS1_CTL_277_DATA 0x01180101
+#define DDRSS1_CTL_278_DATA 0x00030000
+#define DDRSS1_CTL_279_DATA 0x00000000
+#define DDRSS1_CTL_280_DATA 0x00000000
+#define DDRSS1_CTL_281_DATA 0x00000000
+#define DDRSS1_CTL_282_DATA 0x00000000
+#define DDRSS1_CTL_283_DATA 0x00000000
+#define DDRSS1_CTL_284_DATA 0x00000000
+#define DDRSS1_CTL_285_DATA 0x00000000
+#define DDRSS1_CTL_286_DATA 0x00040101
+#define DDRSS1_CTL_287_DATA 0x04010100
+#define DDRSS1_CTL_288_DATA 0x00000000
+#define DDRSS1_CTL_289_DATA 0x00000000
+#define DDRSS1_CTL_290_DATA 0x03030300
+#define DDRSS1_CTL_291_DATA 0x00000001
+#define DDRSS1_CTL_292_DATA 0x00000000
+#define DDRSS1_CTL_293_DATA 0x00000000
+#define DDRSS1_CTL_294_DATA 0x00000000
+#define DDRSS1_CTL_295_DATA 0x00000000
+#define DDRSS1_CTL_296_DATA 0x00000000
+#define DDRSS1_CTL_297_DATA 0x00000000
+#define DDRSS1_CTL_298_DATA 0x00000000
+#define DDRSS1_CTL_299_DATA 0x00000000
+#define DDRSS1_CTL_300_DATA 0x00000000
+#define DDRSS1_CTL_301_DATA 0x00000000
+#define DDRSS1_CTL_302_DATA 0x00000000
+#define DDRSS1_CTL_303_DATA 0x00000000
+#define DDRSS1_CTL_304_DATA 0x00000000
+#define DDRSS1_CTL_305_DATA 0x00000000
+#define DDRSS1_CTL_306_DATA 0x00000000
+#define DDRSS1_CTL_307_DATA 0x00000000
+#define DDRSS1_CTL_308_DATA 0x00000000
+#define DDRSS1_CTL_309_DATA 0x00000000
+#define DDRSS1_CTL_310_DATA 0x00000000
+#define DDRSS1_CTL_311_DATA 0x00000000
+#define DDRSS1_CTL_312_DATA 0x00000000
+#define DDRSS1_CTL_313_DATA 0x01000000
+#define DDRSS1_CTL_314_DATA 0x00020201
+#define DDRSS1_CTL_315_DATA 0x01000101
+#define DDRSS1_CTL_316_DATA 0x01010001
+#define DDRSS1_CTL_317_DATA 0x00010101
+#define DDRSS1_CTL_318_DATA 0x050A0A03
+#define DDRSS1_CTL_319_DATA 0x10081F1F
+#define DDRSS1_CTL_320_DATA 0x00090310
+#define DDRSS1_CTL_321_DATA 0x0B0C030F
+#define DDRSS1_CTL_322_DATA 0x0B0C0306
+#define DDRSS1_CTL_323_DATA 0x0C090006
+#define DDRSS1_CTL_324_DATA 0x0100000C
+#define DDRSS1_CTL_325_DATA 0x08040801
+#define DDRSS1_CTL_326_DATA 0x00000004
+#define DDRSS1_CTL_327_DATA 0x00000000
+#define DDRSS1_CTL_328_DATA 0x00010000
+#define DDRSS1_CTL_329_DATA 0x00280D00
+#define DDRSS1_CTL_330_DATA 0x00000001
+#define DDRSS1_CTL_331_DATA 0x00030001
+#define DDRSS1_CTL_332_DATA 0x00000000
+#define DDRSS1_CTL_333_DATA 0x00000000
+#define DDRSS1_CTL_334_DATA 0x00000000
+#define DDRSS1_CTL_335_DATA 0x00000000
+#define DDRSS1_CTL_336_DATA 0x00000000
+#define DDRSS1_CTL_337_DATA 0x00000000
+#define DDRSS1_CTL_338_DATA 0x00000000
+#define DDRSS1_CTL_339_DATA 0x00000000
+#define DDRSS1_CTL_340_DATA 0x01000000
+#define DDRSS1_CTL_341_DATA 0x00000001
+#define DDRSS1_CTL_342_DATA 0x00010100
+#define DDRSS1_CTL_343_DATA 0x03030000
+#define DDRSS1_CTL_344_DATA 0x00000000
+#define DDRSS1_CTL_345_DATA 0x00000000
+#define DDRSS1_CTL_346_DATA 0x00000000
+#define DDRSS1_CTL_347_DATA 0x00000000
+#define DDRSS1_CTL_348_DATA 0x00000000
+#define DDRSS1_CTL_349_DATA 0x00000000
+#define DDRSS1_CTL_350_DATA 0x00000000
+#define DDRSS1_CTL_351_DATA 0x00000000
+#define DDRSS1_CTL_352_DATA 0x00000000
+#define DDRSS1_CTL_353_DATA 0x00000000
+#define DDRSS1_CTL_354_DATA 0x00000000
+#define DDRSS1_CTL_355_DATA 0x00000000
+#define DDRSS1_CTL_356_DATA 0x00000000
+#define DDRSS1_CTL_357_DATA 0x00000000
+#define DDRSS1_CTL_358_DATA 0x00000000
+#define DDRSS1_CTL_359_DATA 0x00000000
+#define DDRSS1_CTL_360_DATA 0x000556AA
+#define DDRSS1_CTL_361_DATA 0x000AAAAA
+#define DDRSS1_CTL_362_DATA 0x000AA955
+#define DDRSS1_CTL_363_DATA 0x00055555
+#define DDRSS1_CTL_364_DATA 0x000B3133
+#define DDRSS1_CTL_365_DATA 0x0004CD33
+#define DDRSS1_CTL_366_DATA 0x0004CECC
+#define DDRSS1_CTL_367_DATA 0x000B32CC
+#define DDRSS1_CTL_368_DATA 0x00010300
+#define DDRSS1_CTL_369_DATA 0x03000100
+#define DDRSS1_CTL_370_DATA 0x00000000
+#define DDRSS1_CTL_371_DATA 0x00000000
+#define DDRSS1_CTL_372_DATA 0x00000000
+#define DDRSS1_CTL_373_DATA 0x00000000
+#define DDRSS1_CTL_374_DATA 0x00000000
+#define DDRSS1_CTL_375_DATA 0x00000000
+#define DDRSS1_CTL_376_DATA 0x00000000
+#define DDRSS1_CTL_377_DATA 0x00010000
+#define DDRSS1_CTL_378_DATA 0x00000404
+#define DDRSS1_CTL_379_DATA 0x00000000
+#define DDRSS1_CTL_380_DATA 0x00000000
+#define DDRSS1_CTL_381_DATA 0x00000000
+#define DDRSS1_CTL_382_DATA 0x00000000
+#define DDRSS1_CTL_383_DATA 0x00000000
+#define DDRSS1_CTL_384_DATA 0x00000000
+#define DDRSS1_CTL_385_DATA 0x00000000
+#define DDRSS1_CTL_386_DATA 0x00000000
+#define DDRSS1_CTL_387_DATA 0x3A3A1B00
+#define DDRSS1_CTL_388_DATA 0x000A0000
+#define DDRSS1_CTL_389_DATA 0x0000019C
+#define DDRSS1_CTL_390_DATA 0x00000200
+#define DDRSS1_CTL_391_DATA 0x00000200
+#define DDRSS1_CTL_392_DATA 0x00000200
+#define DDRSS1_CTL_393_DATA 0x00000200
+#define DDRSS1_CTL_394_DATA 0x000004D4
+#define DDRSS1_CTL_395_DATA 0x00001018
+#define DDRSS1_CTL_396_DATA 0x00000204
+#define DDRSS1_CTL_397_DATA 0x000040E6
+#define DDRSS1_CTL_398_DATA 0x00000200
+#define DDRSS1_CTL_399_DATA 0x00000200
+#define DDRSS1_CTL_400_DATA 0x00000200
+#define DDRSS1_CTL_401_DATA 0x00000200
+#define DDRSS1_CTL_402_DATA 0x0000C2B2
+#define DDRSS1_CTL_403_DATA 0x000288FC
+#define DDRSS1_CTL_404_DATA 0x00000E15
+#define DDRSS1_CTL_405_DATA 0x000040E6
+#define DDRSS1_CTL_406_DATA 0x00000200
+#define DDRSS1_CTL_407_DATA 0x00000200
+#define DDRSS1_CTL_408_DATA 0x00000200
+#define DDRSS1_CTL_409_DATA 0x00000200
+#define DDRSS1_CTL_410_DATA 0x0000C2B2
+#define DDRSS1_CTL_411_DATA 0x000288FC
+#define DDRSS1_CTL_412_DATA 0x02020E15
+#define DDRSS1_CTL_413_DATA 0x03030202
+#define DDRSS1_CTL_414_DATA 0x00000022
+#define DDRSS1_CTL_415_DATA 0x00000000
+#define DDRSS1_CTL_416_DATA 0x00000000
+#define DDRSS1_CTL_417_DATA 0x00001403
+#define DDRSS1_CTL_418_DATA 0x000007D0
+#define DDRSS1_CTL_419_DATA 0x00000000
+#define DDRSS1_CTL_420_DATA 0x00000000
+#define DDRSS1_CTL_421_DATA 0x00030000
+#define DDRSS1_CTL_422_DATA 0x0007001F
+#define DDRSS1_CTL_423_DATA 0x001B0033
+#define DDRSS1_CTL_424_DATA 0x001B0033
+#define DDRSS1_CTL_425_DATA 0x00000000
+#define DDRSS1_CTL_426_DATA 0x00000000
+#define DDRSS1_CTL_427_DATA 0x02000000
+#define DDRSS1_CTL_428_DATA 0x01000404
+#define DDRSS1_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS1_CTL_430_DATA 0x00000105
+#define DDRSS1_CTL_431_DATA 0x00010101
+#define DDRSS1_CTL_432_DATA 0x00010101
+#define DDRSS1_CTL_433_DATA 0x00010001
+#define DDRSS1_CTL_434_DATA 0x00000101
+#define DDRSS1_CTL_435_DATA 0x02000201
+#define DDRSS1_CTL_436_DATA 0x02010000
+#define DDRSS1_CTL_437_DATA 0x00000200
+#define DDRSS1_CTL_438_DATA 0x28060000
+#define DDRSS1_CTL_439_DATA 0x00000128
+#define DDRSS1_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS1_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS1_CTL_442_DATA 0x00000000
+#define DDRSS1_CTL_443_DATA 0x00000000
+#define DDRSS1_CTL_444_DATA 0x00000000
+#define DDRSS1_CTL_445_DATA 0x00000000
+#define DDRSS1_CTL_446_DATA 0x00000000
+#define DDRSS1_CTL_447_DATA 0x00000000
+#define DDRSS1_CTL_448_DATA 0x00000000
+#define DDRSS1_CTL_449_DATA 0x00000000
+#define DDRSS1_CTL_450_DATA 0x00000000
+#define DDRSS1_CTL_451_DATA 0x00000000
+#define DDRSS1_CTL_452_DATA 0x00000000
+#define DDRSS1_CTL_453_DATA 0x00000000
+#define DDRSS1_CTL_454_DATA 0x00000000
+#define DDRSS1_CTL_455_DATA 0x00000000
+#define DDRSS1_CTL_456_DATA 0x00000000
+#define DDRSS1_CTL_457_DATA 0x00000000
+#define DDRSS1_CTL_458_DATA 0x00000000
+
+#define DDRSS1_PI_00_DATA 0x00000B00
+#define DDRSS1_PI_01_DATA 0x00000000
+#define DDRSS1_PI_02_DATA 0x00000000
+#define DDRSS1_PI_03_DATA 0x00000000
+#define DDRSS1_PI_04_DATA 0x00000000
+#define DDRSS1_PI_05_DATA 0x00000101
+#define DDRSS1_PI_06_DATA 0x00640000
+#define DDRSS1_PI_07_DATA 0x00000001
+#define DDRSS1_PI_08_DATA 0x00000000
+#define DDRSS1_PI_09_DATA 0x00000000
+#define DDRSS1_PI_10_DATA 0x00000000
+#define DDRSS1_PI_11_DATA 0x00000000
+#define DDRSS1_PI_12_DATA 0x00000007
+#define DDRSS1_PI_13_DATA 0x00010002
+#define DDRSS1_PI_14_DATA 0x0800000F
+#define DDRSS1_PI_15_DATA 0x00000103
+#define DDRSS1_PI_16_DATA 0x00000005
+#define DDRSS1_PI_17_DATA 0x00000000
+#define DDRSS1_PI_18_DATA 0x00000000
+#define DDRSS1_PI_19_DATA 0x00000000
+#define DDRSS1_PI_20_DATA 0x00000000
+#define DDRSS1_PI_21_DATA 0x00000000
+#define DDRSS1_PI_22_DATA 0x00000000
+#define DDRSS1_PI_23_DATA 0x00000000
+#define DDRSS1_PI_24_DATA 0x00000000
+#define DDRSS1_PI_25_DATA 0x00000000
+#define DDRSS1_PI_26_DATA 0x00010100
+#define DDRSS1_PI_27_DATA 0x00280A00
+#define DDRSS1_PI_28_DATA 0x00000000
+#define DDRSS1_PI_29_DATA 0x0F000000
+#define DDRSS1_PI_30_DATA 0x00003200
+#define DDRSS1_PI_31_DATA 0x00000000
+#define DDRSS1_PI_32_DATA 0x00000000
+#define DDRSS1_PI_33_DATA 0x01010102
+#define DDRSS1_PI_34_DATA 0x00000000
+#define DDRSS1_PI_35_DATA 0x000000AA
+#define DDRSS1_PI_36_DATA 0x00000055
+#define DDRSS1_PI_37_DATA 0x000000B5
+#define DDRSS1_PI_38_DATA 0x0000004A
+#define DDRSS1_PI_39_DATA 0x00000056
+#define DDRSS1_PI_40_DATA 0x000000A9
+#define DDRSS1_PI_41_DATA 0x000000A9
+#define DDRSS1_PI_42_DATA 0x000000B5
+#define DDRSS1_PI_43_DATA 0x00000000
+#define DDRSS1_PI_44_DATA 0x00000000
+#define DDRSS1_PI_45_DATA 0x000F0F00
+#define DDRSS1_PI_46_DATA 0x0000001B
+#define DDRSS1_PI_47_DATA 0x000007D0
+#define DDRSS1_PI_48_DATA 0x00000300
+#define DDRSS1_PI_49_DATA 0x00000000
+#define DDRSS1_PI_50_DATA 0x00000000
+#define DDRSS1_PI_51_DATA 0x01000000
+#define DDRSS1_PI_52_DATA 0x00010101
+#define DDRSS1_PI_53_DATA 0x00000000
+#define DDRSS1_PI_54_DATA 0x00030000
+#define DDRSS1_PI_55_DATA 0x0F000000
+#define DDRSS1_PI_56_DATA 0x00000017
+#define DDRSS1_PI_57_DATA 0x00000000
+#define DDRSS1_PI_58_DATA 0x00000000
+#define DDRSS1_PI_59_DATA 0x00000000
+#define DDRSS1_PI_60_DATA 0x0A0A140A
+#define DDRSS1_PI_61_DATA 0x10020101
+#define DDRSS1_PI_62_DATA 0x00020805
+#define DDRSS1_PI_63_DATA 0x01000404
+#define DDRSS1_PI_64_DATA 0x00000000
+#define DDRSS1_PI_65_DATA 0x00000000
+#define DDRSS1_PI_66_DATA 0x00000100
+#define DDRSS1_PI_67_DATA 0x0001010F
+#define DDRSS1_PI_68_DATA 0x00340000
+#define DDRSS1_PI_69_DATA 0x00000000
+#define DDRSS1_PI_70_DATA 0x00000000
+#define DDRSS1_PI_71_DATA 0x0000FFFF
+#define DDRSS1_PI_72_DATA 0x00000000
+#define DDRSS1_PI_73_DATA 0x00080000
+#define DDRSS1_PI_74_DATA 0x02000200
+#define DDRSS1_PI_75_DATA 0x01000100
+#define DDRSS1_PI_76_DATA 0x01000000
+#define DDRSS1_PI_77_DATA 0x02000200
+#define DDRSS1_PI_78_DATA 0x00000200
+#define DDRSS1_PI_79_DATA 0x00000000
+#define DDRSS1_PI_80_DATA 0x00000000
+#define DDRSS1_PI_81_DATA 0x00000000
+#define DDRSS1_PI_82_DATA 0x00000000
+#define DDRSS1_PI_83_DATA 0x00000000
+#define DDRSS1_PI_84_DATA 0x00000000
+#define DDRSS1_PI_85_DATA 0x00000000
+#define DDRSS1_PI_86_DATA 0x00000000
+#define DDRSS1_PI_87_DATA 0x00000000
+#define DDRSS1_PI_88_DATA 0x00000000
+#define DDRSS1_PI_89_DATA 0x00000000
+#define DDRSS1_PI_90_DATA 0x00000000
+#define DDRSS1_PI_91_DATA 0x00000400
+#define DDRSS1_PI_92_DATA 0x02010000
+#define DDRSS1_PI_93_DATA 0x00080003
+#define DDRSS1_PI_94_DATA 0x00080000
+#define DDRSS1_PI_95_DATA 0x00000001
+#define DDRSS1_PI_96_DATA 0x00000000
+#define DDRSS1_PI_97_DATA 0x0000AA00
+#define DDRSS1_PI_98_DATA 0x00000000
+#define DDRSS1_PI_99_DATA 0x00000000
+#define DDRSS1_PI_100_DATA 0x00010000
+#define DDRSS1_PI_101_DATA 0x00000000
+#define DDRSS1_PI_102_DATA 0x00000000
+#define DDRSS1_PI_103_DATA 0x00000000
+#define DDRSS1_PI_104_DATA 0x00000000
+#define DDRSS1_PI_105_DATA 0x00000000
+#define DDRSS1_PI_106_DATA 0x00000000
+#define DDRSS1_PI_107_DATA 0x00000000
+#define DDRSS1_PI_108_DATA 0x00000000
+#define DDRSS1_PI_109_DATA 0x00000000
+#define DDRSS1_PI_110_DATA 0x00000000
+#define DDRSS1_PI_111_DATA 0x00000000
+#define DDRSS1_PI_112_DATA 0x00000000
+#define DDRSS1_PI_113_DATA 0x00000000
+#define DDRSS1_PI_114_DATA 0x00000000
+#define DDRSS1_PI_115_DATA 0x00000000
+#define DDRSS1_PI_116_DATA 0x00000000
+#define DDRSS1_PI_117_DATA 0x00000000
+#define DDRSS1_PI_118_DATA 0x00000000
+#define DDRSS1_PI_119_DATA 0x00000000
+#define DDRSS1_PI_120_DATA 0x00000000
+#define DDRSS1_PI_121_DATA 0x00000000
+#define DDRSS1_PI_122_DATA 0x00000000
+#define DDRSS1_PI_123_DATA 0x00000000
+#define DDRSS1_PI_124_DATA 0x00000000
+#define DDRSS1_PI_125_DATA 0x00000008
+#define DDRSS1_PI_126_DATA 0x00000000
+#define DDRSS1_PI_127_DATA 0x00000000
+#define DDRSS1_PI_128_DATA 0x00000000
+#define DDRSS1_PI_129_DATA 0x00000000
+#define DDRSS1_PI_130_DATA 0x00000000
+#define DDRSS1_PI_131_DATA 0x00000000
+#define DDRSS1_PI_132_DATA 0x00000000
+#define DDRSS1_PI_133_DATA 0x00000000
+#define DDRSS1_PI_134_DATA 0x00000002
+#define DDRSS1_PI_135_DATA 0x00000000
+#define DDRSS1_PI_136_DATA 0x00000000
+#define DDRSS1_PI_137_DATA 0x0000000A
+#define DDRSS1_PI_138_DATA 0x00000019
+#define DDRSS1_PI_139_DATA 0x00000100
+#define DDRSS1_PI_140_DATA 0x00000000
+#define DDRSS1_PI_141_DATA 0x00000000
+#define DDRSS1_PI_142_DATA 0x00000000
+#define DDRSS1_PI_143_DATA 0x00000000
+#define DDRSS1_PI_144_DATA 0x01000000
+#define DDRSS1_PI_145_DATA 0x00010003
+#define DDRSS1_PI_146_DATA 0x02000101
+#define DDRSS1_PI_147_DATA 0x01030001
+#define DDRSS1_PI_148_DATA 0x00010400
+#define DDRSS1_PI_149_DATA 0x06000105
+#define DDRSS1_PI_150_DATA 0x01070001
+#define DDRSS1_PI_151_DATA 0x00000000
+#define DDRSS1_PI_152_DATA 0x00000000
+#define DDRSS1_PI_153_DATA 0x00000000
+#define DDRSS1_PI_154_DATA 0x00010001
+#define DDRSS1_PI_155_DATA 0x00000000
+#define DDRSS1_PI_156_DATA 0x00000000
+#define DDRSS1_PI_157_DATA 0x00000000
+#define DDRSS1_PI_158_DATA 0x00000000
+#define DDRSS1_PI_159_DATA 0x00000401
+#define DDRSS1_PI_160_DATA 0x00000000
+#define DDRSS1_PI_161_DATA 0x00010000
+#define DDRSS1_PI_162_DATA 0x00000000
+#define DDRSS1_PI_163_DATA 0x2B2B0200
+#define DDRSS1_PI_164_DATA 0x00000034
+#define DDRSS1_PI_165_DATA 0x00000064
+#define DDRSS1_PI_166_DATA 0x00020064
+#define DDRSS1_PI_167_DATA 0x02000200
+#define DDRSS1_PI_168_DATA 0x48120C04
+#define DDRSS1_PI_169_DATA 0x00154812
+#define DDRSS1_PI_170_DATA 0x000000CE
+#define DDRSS1_PI_171_DATA 0x0000032B
+#define DDRSS1_PI_172_DATA 0x00002073
+#define DDRSS1_PI_173_DATA 0x0000032B
+#define DDRSS1_PI_174_DATA 0x04002073
+#define DDRSS1_PI_175_DATA 0x01010404
+#define DDRSS1_PI_176_DATA 0x00001501
+#define DDRSS1_PI_177_DATA 0x00150015
+#define DDRSS1_PI_178_DATA 0x01000100
+#define DDRSS1_PI_179_DATA 0x00000100
+#define DDRSS1_PI_180_DATA 0x00000000
+#define DDRSS1_PI_181_DATA 0x01010101
+#define DDRSS1_PI_182_DATA 0x00000101
+#define DDRSS1_PI_183_DATA 0x00000000
+#define DDRSS1_PI_184_DATA 0x00000000
+#define DDRSS1_PI_185_DATA 0x15040000
+#define DDRSS1_PI_186_DATA 0x0E0E0215
+#define DDRSS1_PI_187_DATA 0x00040402
+#define DDRSS1_PI_188_DATA 0x000D0035
+#define DDRSS1_PI_189_DATA 0x00218049
+#define DDRSS1_PI_190_DATA 0x00218049
+#define DDRSS1_PI_191_DATA 0x01010101
+#define DDRSS1_PI_192_DATA 0x0004000E
+#define DDRSS1_PI_193_DATA 0x00040216
+#define DDRSS1_PI_194_DATA 0x01000216
+#define DDRSS1_PI_195_DATA 0x000F000F
+#define DDRSS1_PI_196_DATA 0x02170100
+#define DDRSS1_PI_197_DATA 0x01000217
+#define DDRSS1_PI_198_DATA 0x02170217
+#define DDRSS1_PI_199_DATA 0x32103200
+#define DDRSS1_PI_200_DATA 0x01013210
+#define DDRSS1_PI_201_DATA 0x0A070601
+#define DDRSS1_PI_202_DATA 0x1F130A0D
+#define DDRSS1_PI_203_DATA 0x1F130A14
+#define DDRSS1_PI_204_DATA 0x0000C014
+#define DDRSS1_PI_205_DATA 0x00C01000
+#define DDRSS1_PI_206_DATA 0x00C01000
+#define DDRSS1_PI_207_DATA 0x00021000
+#define DDRSS1_PI_208_DATA 0x0024000E
+#define DDRSS1_PI_209_DATA 0x00240216
+#define DDRSS1_PI_210_DATA 0x00110216
+#define DDRSS1_PI_211_DATA 0x32000056
+#define DDRSS1_PI_212_DATA 0x00000301
+#define DDRSS1_PI_213_DATA 0x005B0036
+#define DDRSS1_PI_214_DATA 0x03013212
+#define DDRSS1_PI_215_DATA 0x00003600
+#define DDRSS1_PI_216_DATA 0x3212005B
+#define DDRSS1_PI_217_DATA 0x09000301
+#define DDRSS1_PI_218_DATA 0x04010504
+#define DDRSS1_PI_219_DATA 0x040006C9
+#define DDRSS1_PI_220_DATA 0x0A032001
+#define DDRSS1_PI_221_DATA 0x2C31110A
+#define DDRSS1_PI_222_DATA 0x00002918
+#define DDRSS1_PI_223_DATA 0x6001071C
+#define DDRSS1_PI_224_DATA 0x1E202008
+#define DDRSS1_PI_225_DATA 0x2C311116
+#define DDRSS1_PI_226_DATA 0x00002918
+#define DDRSS1_PI_227_DATA 0x6001071C
+#define DDRSS1_PI_228_DATA 0x1E202008
+#define DDRSS1_PI_229_DATA 0x00019C16
+#define DDRSS1_PI_230_DATA 0x00001018
+#define DDRSS1_PI_231_DATA 0x000040E6
+#define DDRSS1_PI_232_DATA 0x000288FC
+#define DDRSS1_PI_233_DATA 0x000040E6
+#define DDRSS1_PI_234_DATA 0x000288FC
+#define DDRSS1_PI_235_DATA 0x033B0016
+#define DDRSS1_PI_236_DATA 0x0303033B
+#define DDRSS1_PI_237_DATA 0x002AF803
+#define DDRSS1_PI_238_DATA 0x0001ADAF
+#define DDRSS1_PI_239_DATA 0x00000005
+#define DDRSS1_PI_240_DATA 0x0000006E
+#define DDRSS1_PI_241_DATA 0x00000016
+#define DDRSS1_PI_242_DATA 0x000681C8
+#define DDRSS1_PI_243_DATA 0x0001ADAF
+#define DDRSS1_PI_244_DATA 0x00000005
+#define DDRSS1_PI_245_DATA 0x000010A9
+#define DDRSS1_PI_246_DATA 0x0000033B
+#define DDRSS1_PI_247_DATA 0x000681C8
+#define DDRSS1_PI_248_DATA 0x0001ADAF
+#define DDRSS1_PI_249_DATA 0x00000005
+#define DDRSS1_PI_250_DATA 0x000010A9
+#define DDRSS1_PI_251_DATA 0x0100033B
+#define DDRSS1_PI_252_DATA 0x00370040
+#define DDRSS1_PI_253_DATA 0x00010008
+#define DDRSS1_PI_254_DATA 0x08550040
+#define DDRSS1_PI_255_DATA 0x00010040
+#define DDRSS1_PI_256_DATA 0x08550040
+#define DDRSS1_PI_257_DATA 0x00000340
+#define DDRSS1_PI_258_DATA 0x006B006B
+#define DDRSS1_PI_259_DATA 0x08040404
+#define DDRSS1_PI_260_DATA 0x00000055
+#define DDRSS1_PI_261_DATA 0x55083C5A
+#define DDRSS1_PI_262_DATA 0x5A000000
+#define DDRSS1_PI_263_DATA 0x0055083C
+#define DDRSS1_PI_264_DATA 0x3C5A0000
+#define DDRSS1_PI_265_DATA 0x00005508
+#define DDRSS1_PI_266_DATA 0x0C3C5A00
+#define DDRSS1_PI_267_DATA 0x080F0E0D
+#define DDRSS1_PI_268_DATA 0x000B0A09
+#define DDRSS1_PI_269_DATA 0x00030201
+#define DDRSS1_PI_270_DATA 0x01000000
+#define DDRSS1_PI_271_DATA 0x04020201
+#define DDRSS1_PI_272_DATA 0x00080804
+#define DDRSS1_PI_273_DATA 0x00000000
+#define DDRSS1_PI_274_DATA 0x00000000
+#define DDRSS1_PI_275_DATA 0x00330084
+#define DDRSS1_PI_276_DATA 0x00160000
+#define DDRSS1_PI_277_DATA 0x35333FF4
+#define DDRSS1_PI_278_DATA 0x00160F27
+#define DDRSS1_PI_279_DATA 0x35333FF4
+#define DDRSS1_PI_280_DATA 0x00160F27
+#define DDRSS1_PI_281_DATA 0x00330084
+#define DDRSS1_PI_282_DATA 0x00160000
+#define DDRSS1_PI_283_DATA 0x35333FF4
+#define DDRSS1_PI_284_DATA 0x00160F27
+#define DDRSS1_PI_285_DATA 0x35333FF4
+#define DDRSS1_PI_286_DATA 0x00160F27
+#define DDRSS1_PI_287_DATA 0x00330084
+#define DDRSS1_PI_288_DATA 0x00160000
+#define DDRSS1_PI_289_DATA 0x35333FF4
+#define DDRSS1_PI_290_DATA 0x00160F27
+#define DDRSS1_PI_291_DATA 0x35333FF4
+#define DDRSS1_PI_292_DATA 0x00160F27
+#define DDRSS1_PI_293_DATA 0x00330084
+#define DDRSS1_PI_294_DATA 0x00160000
+#define DDRSS1_PI_295_DATA 0x35333FF4
+#define DDRSS1_PI_296_DATA 0x00160F27
+#define DDRSS1_PI_297_DATA 0x35333FF4
+#define DDRSS1_PI_298_DATA 0x00160F27
+#define DDRSS1_PI_299_DATA 0x00000000
+
+#define DDRSS1_PHY_00_DATA 0x000004F0
+#define DDRSS1_PHY_01_DATA 0x00000000
+#define DDRSS1_PHY_02_DATA 0x00030200
+#define DDRSS1_PHY_03_DATA 0x00000000
+#define DDRSS1_PHY_04_DATA 0x00000000
+#define DDRSS1_PHY_05_DATA 0x01030000
+#define DDRSS1_PHY_06_DATA 0x00010000
+#define DDRSS1_PHY_07_DATA 0x01030004
+#define DDRSS1_PHY_08_DATA 0x01000000
+#define DDRSS1_PHY_09_DATA 0x00000000
+#define DDRSS1_PHY_10_DATA 0x00000000
+#define DDRSS1_PHY_11_DATA 0x01000001
+#define DDRSS1_PHY_12_DATA 0x00000100
+#define DDRSS1_PHY_13_DATA 0x000800C0
+#define DDRSS1_PHY_14_DATA 0x060100CC
+#define DDRSS1_PHY_15_DATA 0x00030066
+#define DDRSS1_PHY_16_DATA 0x00000000
+#define DDRSS1_PHY_17_DATA 0x00000301
+#define DDRSS1_PHY_18_DATA 0x0000AAAA
+#define DDRSS1_PHY_19_DATA 0x00005555
+#define DDRSS1_PHY_20_DATA 0x0000B5B5
+#define DDRSS1_PHY_21_DATA 0x00004A4A
+#define DDRSS1_PHY_22_DATA 0x00005656
+#define DDRSS1_PHY_23_DATA 0x0000A9A9
+#define DDRSS1_PHY_24_DATA 0x0000A9A9
+#define DDRSS1_PHY_25_DATA 0x0000B5B5
+#define DDRSS1_PHY_26_DATA 0x00000000
+#define DDRSS1_PHY_27_DATA 0x00000000
+#define DDRSS1_PHY_28_DATA 0x2A000000
+#define DDRSS1_PHY_29_DATA 0x00000808
+#define DDRSS1_PHY_30_DATA 0x0F000000
+#define DDRSS1_PHY_31_DATA 0x00000F0F
+#define DDRSS1_PHY_32_DATA 0x10400000
+#define DDRSS1_PHY_33_DATA 0x0C002006
+#define DDRSS1_PHY_34_DATA 0x00000000
+#define DDRSS1_PHY_35_DATA 0x00000000
+#define DDRSS1_PHY_36_DATA 0x55555555
+#define DDRSS1_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_38_DATA 0x55555555
+#define DDRSS1_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_40_DATA 0x00005555
+#define DDRSS1_PHY_41_DATA 0x01000100
+#define DDRSS1_PHY_42_DATA 0x00800180
+#define DDRSS1_PHY_43_DATA 0x00000001
+#define DDRSS1_PHY_44_DATA 0x00000000
+#define DDRSS1_PHY_45_DATA 0x00000000
+#define DDRSS1_PHY_46_DATA 0x00000000
+#define DDRSS1_PHY_47_DATA 0x00000000
+#define DDRSS1_PHY_48_DATA 0x00000000
+#define DDRSS1_PHY_49_DATA 0x00000000
+#define DDRSS1_PHY_50_DATA 0x00000000
+#define DDRSS1_PHY_51_DATA 0x00000000
+#define DDRSS1_PHY_52_DATA 0x00000000
+#define DDRSS1_PHY_53_DATA 0x00000000
+#define DDRSS1_PHY_54_DATA 0x00000000
+#define DDRSS1_PHY_55_DATA 0x00000000
+#define DDRSS1_PHY_56_DATA 0x00000000
+#define DDRSS1_PHY_57_DATA 0x00000000
+#define DDRSS1_PHY_58_DATA 0x00000000
+#define DDRSS1_PHY_59_DATA 0x00000000
+#define DDRSS1_PHY_60_DATA 0x00000000
+#define DDRSS1_PHY_61_DATA 0x00000000
+#define DDRSS1_PHY_62_DATA 0x00000000
+#define DDRSS1_PHY_63_DATA 0x00000000
+#define DDRSS1_PHY_64_DATA 0x00000000
+#define DDRSS1_PHY_65_DATA 0x00000000
+#define DDRSS1_PHY_66_DATA 0x00000104
+#define DDRSS1_PHY_67_DATA 0x00000120
+#define DDRSS1_PHY_68_DATA 0x00000000
+#define DDRSS1_PHY_69_DATA 0x00000000
+#define DDRSS1_PHY_70_DATA 0x00000000
+#define DDRSS1_PHY_71_DATA 0x00000000
+#define DDRSS1_PHY_72_DATA 0x00000000
+#define DDRSS1_PHY_73_DATA 0x00000000
+#define DDRSS1_PHY_74_DATA 0x00000000
+#define DDRSS1_PHY_75_DATA 0x00000001
+#define DDRSS1_PHY_76_DATA 0x07FF0000
+#define DDRSS1_PHY_77_DATA 0x0080081F
+#define DDRSS1_PHY_78_DATA 0x00081020
+#define DDRSS1_PHY_79_DATA 0x04010000
+#define DDRSS1_PHY_80_DATA 0x00000000
+#define DDRSS1_PHY_81_DATA 0x00000000
+#define DDRSS1_PHY_82_DATA 0x00000000
+#define DDRSS1_PHY_83_DATA 0x00000100
+#define DDRSS1_PHY_84_DATA 0x01CC0C01
+#define DDRSS1_PHY_85_DATA 0x1003CC0C
+#define DDRSS1_PHY_86_DATA 0x20000140
+#define DDRSS1_PHY_87_DATA 0x07FF0200
+#define DDRSS1_PHY_88_DATA 0x0000DD01
+#define DDRSS1_PHY_89_DATA 0x10100303
+#define DDRSS1_PHY_90_DATA 0x10101010
+#define DDRSS1_PHY_91_DATA 0x10101010
+#define DDRSS1_PHY_92_DATA 0x00021010
+#define DDRSS1_PHY_93_DATA 0x00100010
+#define DDRSS1_PHY_94_DATA 0x00100010
+#define DDRSS1_PHY_95_DATA 0x00100010
+#define DDRSS1_PHY_96_DATA 0x00100010
+#define DDRSS1_PHY_97_DATA 0x00050010
+#define DDRSS1_PHY_98_DATA 0x51517041
+#define DDRSS1_PHY_99_DATA 0x31C06001
+#define DDRSS1_PHY_100_DATA 0x07AB0340
+#define DDRSS1_PHY_101_DATA 0x00C0C001
+#define DDRSS1_PHY_102_DATA 0x0E0D0001
+#define DDRSS1_PHY_103_DATA 0x10001000
+#define DDRSS1_PHY_104_DATA 0x0C083E42
+#define DDRSS1_PHY_105_DATA 0x0F0C3701
+#define DDRSS1_PHY_106_DATA 0x01000140
+#define DDRSS1_PHY_107_DATA 0x0C000420
+#define DDRSS1_PHY_108_DATA 0x00000198
+#define DDRSS1_PHY_109_DATA 0x0A0000D0
+#define DDRSS1_PHY_110_DATA 0x00030200
+#define DDRSS1_PHY_111_DATA 0x02800000
+#define DDRSS1_PHY_112_DATA 0x80800000
+#define DDRSS1_PHY_113_DATA 0x000E2010
+#define DDRSS1_PHY_114_DATA 0x76543210
+#define DDRSS1_PHY_115_DATA 0x00000008
+#define DDRSS1_PHY_116_DATA 0x02800280
+#define DDRSS1_PHY_117_DATA 0x02800280
+#define DDRSS1_PHY_118_DATA 0x02800280
+#define DDRSS1_PHY_119_DATA 0x02800280
+#define DDRSS1_PHY_120_DATA 0x00000280
+#define DDRSS1_PHY_121_DATA 0x0000A000
+#define DDRSS1_PHY_122_DATA 0x00A000A0
+#define DDRSS1_PHY_123_DATA 0x00A000A0
+#define DDRSS1_PHY_124_DATA 0x00A000A0
+#define DDRSS1_PHY_125_DATA 0x00A000A0
+#define DDRSS1_PHY_126_DATA 0x00A000A0
+#define DDRSS1_PHY_127_DATA 0x00A000A0
+#define DDRSS1_PHY_128_DATA 0x00A000A0
+#define DDRSS1_PHY_129_DATA 0x00A000A0
+#define DDRSS1_PHY_130_DATA 0x01C200A0
+#define DDRSS1_PHY_131_DATA 0x01A00005
+#define DDRSS1_PHY_132_DATA 0x00000000
+#define DDRSS1_PHY_133_DATA 0x00000000
+#define DDRSS1_PHY_134_DATA 0x00080200
+#define DDRSS1_PHY_135_DATA 0x00000000
+#define DDRSS1_PHY_136_DATA 0x20202000
+#define DDRSS1_PHY_137_DATA 0x20202020
+#define DDRSS1_PHY_138_DATA 0xF0F02020
+#define DDRSS1_PHY_139_DATA 0x00000000
+#define DDRSS1_PHY_140_DATA 0x00000000
+#define DDRSS1_PHY_141_DATA 0x00000000
+#define DDRSS1_PHY_142_DATA 0x00000000
+#define DDRSS1_PHY_143_DATA 0x00000000
+#define DDRSS1_PHY_144_DATA 0x00000000
+#define DDRSS1_PHY_145_DATA 0x00000000
+#define DDRSS1_PHY_146_DATA 0x00000000
+#define DDRSS1_PHY_147_DATA 0x00000000
+#define DDRSS1_PHY_148_DATA 0x00000000
+#define DDRSS1_PHY_149_DATA 0x00000000
+#define DDRSS1_PHY_150_DATA 0x00000000
+#define DDRSS1_PHY_151_DATA 0x00000000
+#define DDRSS1_PHY_152_DATA 0x00000000
+#define DDRSS1_PHY_153_DATA 0x00000000
+#define DDRSS1_PHY_154_DATA 0x00000000
+#define DDRSS1_PHY_155_DATA 0x00000000
+#define DDRSS1_PHY_156_DATA 0x00000000
+#define DDRSS1_PHY_157_DATA 0x00000000
+#define DDRSS1_PHY_158_DATA 0x00000000
+#define DDRSS1_PHY_159_DATA 0x00000000
+#define DDRSS1_PHY_160_DATA 0x00000000
+#define DDRSS1_PHY_161_DATA 0x00000000
+#define DDRSS1_PHY_162_DATA 0x00000000
+#define DDRSS1_PHY_163_DATA 0x00000000
+#define DDRSS1_PHY_164_DATA 0x00000000
+#define DDRSS1_PHY_165_DATA 0x00000000
+#define DDRSS1_PHY_166_DATA 0x00000000
+#define DDRSS1_PHY_167_DATA 0x00000000
+#define DDRSS1_PHY_168_DATA 0x00000000
+#define DDRSS1_PHY_169_DATA 0x00000000
+#define DDRSS1_PHY_170_DATA 0x00000000
+#define DDRSS1_PHY_171_DATA 0x00000000
+#define DDRSS1_PHY_172_DATA 0x00000000
+#define DDRSS1_PHY_173_DATA 0x00000000
+#define DDRSS1_PHY_174_DATA 0x00000000
+#define DDRSS1_PHY_175_DATA 0x00000000
+#define DDRSS1_PHY_176_DATA 0x00000000
+#define DDRSS1_PHY_177_DATA 0x00000000
+#define DDRSS1_PHY_178_DATA 0x00000000
+#define DDRSS1_PHY_179_DATA 0x00000000
+#define DDRSS1_PHY_180_DATA 0x00000000
+#define DDRSS1_PHY_181_DATA 0x00000000
+#define DDRSS1_PHY_182_DATA 0x00000000
+#define DDRSS1_PHY_183_DATA 0x00000000
+#define DDRSS1_PHY_184_DATA 0x00000000
+#define DDRSS1_PHY_185_DATA 0x00000000
+#define DDRSS1_PHY_186_DATA 0x00000000
+#define DDRSS1_PHY_187_DATA 0x00000000
+#define DDRSS1_PHY_188_DATA 0x00000000
+#define DDRSS1_PHY_189_DATA 0x00000000
+#define DDRSS1_PHY_190_DATA 0x00000000
+#define DDRSS1_PHY_191_DATA 0x00000000
+#define DDRSS1_PHY_192_DATA 0x00000000
+#define DDRSS1_PHY_193_DATA 0x00000000
+#define DDRSS1_PHY_194_DATA 0x00000000
+#define DDRSS1_PHY_195_DATA 0x00000000
+#define DDRSS1_PHY_196_DATA 0x00000000
+#define DDRSS1_PHY_197_DATA 0x00000000
+#define DDRSS1_PHY_198_DATA 0x00000000
+#define DDRSS1_PHY_199_DATA 0x00000000
+#define DDRSS1_PHY_200_DATA 0x00000000
+#define DDRSS1_PHY_201_DATA 0x00000000
+#define DDRSS1_PHY_202_DATA 0x00000000
+#define DDRSS1_PHY_203_DATA 0x00000000
+#define DDRSS1_PHY_204_DATA 0x00000000
+#define DDRSS1_PHY_205_DATA 0x00000000
+#define DDRSS1_PHY_206_DATA 0x00000000
+#define DDRSS1_PHY_207_DATA 0x00000000
+#define DDRSS1_PHY_208_DATA 0x00000000
+#define DDRSS1_PHY_209_DATA 0x00000000
+#define DDRSS1_PHY_210_DATA 0x00000000
+#define DDRSS1_PHY_211_DATA 0x00000000
+#define DDRSS1_PHY_212_DATA 0x00000000
+#define DDRSS1_PHY_213_DATA 0x00000000
+#define DDRSS1_PHY_214_DATA 0x00000000
+#define DDRSS1_PHY_215_DATA 0x00000000
+#define DDRSS1_PHY_216_DATA 0x00000000
+#define DDRSS1_PHY_217_DATA 0x00000000
+#define DDRSS1_PHY_218_DATA 0x00000000
+#define DDRSS1_PHY_219_DATA 0x00000000
+#define DDRSS1_PHY_220_DATA 0x00000000
+#define DDRSS1_PHY_221_DATA 0x00000000
+#define DDRSS1_PHY_222_DATA 0x00000000
+#define DDRSS1_PHY_223_DATA 0x00000000
+#define DDRSS1_PHY_224_DATA 0x00000000
+#define DDRSS1_PHY_225_DATA 0x00000000
+#define DDRSS1_PHY_226_DATA 0x00000000
+#define DDRSS1_PHY_227_DATA 0x00000000
+#define DDRSS1_PHY_228_DATA 0x00000000
+#define DDRSS1_PHY_229_DATA 0x00000000
+#define DDRSS1_PHY_230_DATA 0x00000000
+#define DDRSS1_PHY_231_DATA 0x00000000
+#define DDRSS1_PHY_232_DATA 0x00000000
+#define DDRSS1_PHY_233_DATA 0x00000000
+#define DDRSS1_PHY_234_DATA 0x00000000
+#define DDRSS1_PHY_235_DATA 0x00000000
+#define DDRSS1_PHY_236_DATA 0x00000000
+#define DDRSS1_PHY_237_DATA 0x00000000
+#define DDRSS1_PHY_238_DATA 0x00000000
+#define DDRSS1_PHY_239_DATA 0x00000000
+#define DDRSS1_PHY_240_DATA 0x00000000
+#define DDRSS1_PHY_241_DATA 0x00000000
+#define DDRSS1_PHY_242_DATA 0x00000000
+#define DDRSS1_PHY_243_DATA 0x00000000
+#define DDRSS1_PHY_244_DATA 0x00000000
+#define DDRSS1_PHY_245_DATA 0x00000000
+#define DDRSS1_PHY_246_DATA 0x00000000
+#define DDRSS1_PHY_247_DATA 0x00000000
+#define DDRSS1_PHY_248_DATA 0x00000000
+#define DDRSS1_PHY_249_DATA 0x00000000
+#define DDRSS1_PHY_250_DATA 0x00000000
+#define DDRSS1_PHY_251_DATA 0x00000000
+#define DDRSS1_PHY_252_DATA 0x00000000
+#define DDRSS1_PHY_253_DATA 0x00000000
+#define DDRSS1_PHY_254_DATA 0x00000000
+#define DDRSS1_PHY_255_DATA 0x00000000
+#define DDRSS1_PHY_256_DATA 0x000004F0
+#define DDRSS1_PHY_257_DATA 0x00000000
+#define DDRSS1_PHY_258_DATA 0x00030200
+#define DDRSS1_PHY_259_DATA 0x00000000
+#define DDRSS1_PHY_260_DATA 0x00000000
+#define DDRSS1_PHY_261_DATA 0x01030000
+#define DDRSS1_PHY_262_DATA 0x00010000
+#define DDRSS1_PHY_263_DATA 0x01030004
+#define DDRSS1_PHY_264_DATA 0x01000000
+#define DDRSS1_PHY_265_DATA 0x00000000
+#define DDRSS1_PHY_266_DATA 0x00000000
+#define DDRSS1_PHY_267_DATA 0x01000001
+#define DDRSS1_PHY_268_DATA 0x00000100
+#define DDRSS1_PHY_269_DATA 0x000800C0
+#define DDRSS1_PHY_270_DATA 0x060100CC
+#define DDRSS1_PHY_271_DATA 0x00030066
+#define DDRSS1_PHY_272_DATA 0x00000000
+#define DDRSS1_PHY_273_DATA 0x00000301
+#define DDRSS1_PHY_274_DATA 0x0000AAAA
+#define DDRSS1_PHY_275_DATA 0x00005555
+#define DDRSS1_PHY_276_DATA 0x0000B5B5
+#define DDRSS1_PHY_277_DATA 0x00004A4A
+#define DDRSS1_PHY_278_DATA 0x00005656
+#define DDRSS1_PHY_279_DATA 0x0000A9A9
+#define DDRSS1_PHY_280_DATA 0x0000A9A9
+#define DDRSS1_PHY_281_DATA 0x0000B5B5
+#define DDRSS1_PHY_282_DATA 0x00000000
+#define DDRSS1_PHY_283_DATA 0x00000000
+#define DDRSS1_PHY_284_DATA 0x2A000000
+#define DDRSS1_PHY_285_DATA 0x00000808
+#define DDRSS1_PHY_286_DATA 0x0F000000
+#define DDRSS1_PHY_287_DATA 0x00000F0F
+#define DDRSS1_PHY_288_DATA 0x10400000
+#define DDRSS1_PHY_289_DATA 0x0C002006
+#define DDRSS1_PHY_290_DATA 0x00000000
+#define DDRSS1_PHY_291_DATA 0x00000000
+#define DDRSS1_PHY_292_DATA 0x55555555
+#define DDRSS1_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_294_DATA 0x55555555
+#define DDRSS1_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_296_DATA 0x00005555
+#define DDRSS1_PHY_297_DATA 0x01000100
+#define DDRSS1_PHY_298_DATA 0x00800180
+#define DDRSS1_PHY_299_DATA 0x00000000
+#define DDRSS1_PHY_300_DATA 0x00000000
+#define DDRSS1_PHY_301_DATA 0x00000000
+#define DDRSS1_PHY_302_DATA 0x00000000
+#define DDRSS1_PHY_303_DATA 0x00000000
+#define DDRSS1_PHY_304_DATA 0x00000000
+#define DDRSS1_PHY_305_DATA 0x00000000
+#define DDRSS1_PHY_306_DATA 0x00000000
+#define DDRSS1_PHY_307_DATA 0x00000000
+#define DDRSS1_PHY_308_DATA 0x00000000
+#define DDRSS1_PHY_309_DATA 0x00000000
+#define DDRSS1_PHY_310_DATA 0x00000000
+#define DDRSS1_PHY_311_DATA 0x00000000
+#define DDRSS1_PHY_312_DATA 0x00000000
+#define DDRSS1_PHY_313_DATA 0x00000000
+#define DDRSS1_PHY_314_DATA 0x00000000
+#define DDRSS1_PHY_315_DATA 0x00000000
+#define DDRSS1_PHY_316_DATA 0x00000000
+#define DDRSS1_PHY_317_DATA 0x00000000
+#define DDRSS1_PHY_318_DATA 0x00000000
+#define DDRSS1_PHY_319_DATA 0x00000000
+#define DDRSS1_PHY_320_DATA 0x00000000
+#define DDRSS1_PHY_321_DATA 0x00000000
+#define DDRSS1_PHY_322_DATA 0x00000104
+#define DDRSS1_PHY_323_DATA 0x00000120
+#define DDRSS1_PHY_324_DATA 0x00000000
+#define DDRSS1_PHY_325_DATA 0x00000000
+#define DDRSS1_PHY_326_DATA 0x00000000
+#define DDRSS1_PHY_327_DATA 0x00000000
+#define DDRSS1_PHY_328_DATA 0x00000000
+#define DDRSS1_PHY_329_DATA 0x00000000
+#define DDRSS1_PHY_330_DATA 0x00000000
+#define DDRSS1_PHY_331_DATA 0x00000001
+#define DDRSS1_PHY_332_DATA 0x07FF0000
+#define DDRSS1_PHY_333_DATA 0x0080081F
+#define DDRSS1_PHY_334_DATA 0x00081020
+#define DDRSS1_PHY_335_DATA 0x04010000
+#define DDRSS1_PHY_336_DATA 0x00000000
+#define DDRSS1_PHY_337_DATA 0x00000000
+#define DDRSS1_PHY_338_DATA 0x00000000
+#define DDRSS1_PHY_339_DATA 0x00000100
+#define DDRSS1_PHY_340_DATA 0x01CC0C01
+#define DDRSS1_PHY_341_DATA 0x1003CC0C
+#define DDRSS1_PHY_342_DATA 0x20000140
+#define DDRSS1_PHY_343_DATA 0x07FF0200
+#define DDRSS1_PHY_344_DATA 0x0000DD01
+#define DDRSS1_PHY_345_DATA 0x10100303
+#define DDRSS1_PHY_346_DATA 0x10101010
+#define DDRSS1_PHY_347_DATA 0x10101010
+#define DDRSS1_PHY_348_DATA 0x00021010
+#define DDRSS1_PHY_349_DATA 0x00100010
+#define DDRSS1_PHY_350_DATA 0x00100010
+#define DDRSS1_PHY_351_DATA 0x00100010
+#define DDRSS1_PHY_352_DATA 0x00100010
+#define DDRSS1_PHY_353_DATA 0x00050010
+#define DDRSS1_PHY_354_DATA 0x51517041
+#define DDRSS1_PHY_355_DATA 0x31C06001
+#define DDRSS1_PHY_356_DATA 0x07AB0340
+#define DDRSS1_PHY_357_DATA 0x00C0C001
+#define DDRSS1_PHY_358_DATA 0x0E0D0001
+#define DDRSS1_PHY_359_DATA 0x10001000
+#define DDRSS1_PHY_360_DATA 0x0C083E42
+#define DDRSS1_PHY_361_DATA 0x0F0C3701
+#define DDRSS1_PHY_362_DATA 0x01000140
+#define DDRSS1_PHY_363_DATA 0x0C000420
+#define DDRSS1_PHY_364_DATA 0x00000198
+#define DDRSS1_PHY_365_DATA 0x0A0000D0
+#define DDRSS1_PHY_366_DATA 0x00030200
+#define DDRSS1_PHY_367_DATA 0x02800000
+#define DDRSS1_PHY_368_DATA 0x80800000
+#define DDRSS1_PHY_369_DATA 0x000E2010
+#define DDRSS1_PHY_370_DATA 0x76543210
+#define DDRSS1_PHY_371_DATA 0x00000008
+#define DDRSS1_PHY_372_DATA 0x02800280
+#define DDRSS1_PHY_373_DATA 0x02800280
+#define DDRSS1_PHY_374_DATA 0x02800280
+#define DDRSS1_PHY_375_DATA 0x02800280
+#define DDRSS1_PHY_376_DATA 0x00000280
+#define DDRSS1_PHY_377_DATA 0x0000A000
+#define DDRSS1_PHY_378_DATA 0x00A000A0
+#define DDRSS1_PHY_379_DATA 0x00A000A0
+#define DDRSS1_PHY_380_DATA 0x00A000A0
+#define DDRSS1_PHY_381_DATA 0x00A000A0
+#define DDRSS1_PHY_382_DATA 0x00A000A0
+#define DDRSS1_PHY_383_DATA 0x00A000A0
+#define DDRSS1_PHY_384_DATA 0x00A000A0
+#define DDRSS1_PHY_385_DATA 0x00A000A0
+#define DDRSS1_PHY_386_DATA 0x01C200A0
+#define DDRSS1_PHY_387_DATA 0x01A00005
+#define DDRSS1_PHY_388_DATA 0x00000000
+#define DDRSS1_PHY_389_DATA 0x00000000
+#define DDRSS1_PHY_390_DATA 0x00080200
+#define DDRSS1_PHY_391_DATA 0x00000000
+#define DDRSS1_PHY_392_DATA 0x20202000
+#define DDRSS1_PHY_393_DATA 0x20202020
+#define DDRSS1_PHY_394_DATA 0xF0F02020
+#define DDRSS1_PHY_395_DATA 0x00000000
+#define DDRSS1_PHY_396_DATA 0x00000000
+#define DDRSS1_PHY_397_DATA 0x00000000
+#define DDRSS1_PHY_398_DATA 0x00000000
+#define DDRSS1_PHY_399_DATA 0x00000000
+#define DDRSS1_PHY_400_DATA 0x00000000
+#define DDRSS1_PHY_401_DATA 0x00000000
+#define DDRSS1_PHY_402_DATA 0x00000000
+#define DDRSS1_PHY_403_DATA 0x00000000
+#define DDRSS1_PHY_404_DATA 0x00000000
+#define DDRSS1_PHY_405_DATA 0x00000000
+#define DDRSS1_PHY_406_DATA 0x00000000
+#define DDRSS1_PHY_407_DATA 0x00000000
+#define DDRSS1_PHY_408_DATA 0x00000000
+#define DDRSS1_PHY_409_DATA 0x00000000
+#define DDRSS1_PHY_410_DATA 0x00000000
+#define DDRSS1_PHY_411_DATA 0x00000000
+#define DDRSS1_PHY_412_DATA 0x00000000
+#define DDRSS1_PHY_413_DATA 0x00000000
+#define DDRSS1_PHY_414_DATA 0x00000000
+#define DDRSS1_PHY_415_DATA 0x00000000
+#define DDRSS1_PHY_416_DATA 0x00000000
+#define DDRSS1_PHY_417_DATA 0x00000000
+#define DDRSS1_PHY_418_DATA 0x00000000
+#define DDRSS1_PHY_419_DATA 0x00000000
+#define DDRSS1_PHY_420_DATA 0x00000000
+#define DDRSS1_PHY_421_DATA 0x00000000
+#define DDRSS1_PHY_422_DATA 0x00000000
+#define DDRSS1_PHY_423_DATA 0x00000000
+#define DDRSS1_PHY_424_DATA 0x00000000
+#define DDRSS1_PHY_425_DATA 0x00000000
+#define DDRSS1_PHY_426_DATA 0x00000000
+#define DDRSS1_PHY_427_DATA 0x00000000
+#define DDRSS1_PHY_428_DATA 0x00000000
+#define DDRSS1_PHY_429_DATA 0x00000000
+#define DDRSS1_PHY_430_DATA 0x00000000
+#define DDRSS1_PHY_431_DATA 0x00000000
+#define DDRSS1_PHY_432_DATA 0x00000000
+#define DDRSS1_PHY_433_DATA 0x00000000
+#define DDRSS1_PHY_434_DATA 0x00000000
+#define DDRSS1_PHY_435_DATA 0x00000000
+#define DDRSS1_PHY_436_DATA 0x00000000
+#define DDRSS1_PHY_437_DATA 0x00000000
+#define DDRSS1_PHY_438_DATA 0x00000000
+#define DDRSS1_PHY_439_DATA 0x00000000
+#define DDRSS1_PHY_440_DATA 0x00000000
+#define DDRSS1_PHY_441_DATA 0x00000000
+#define DDRSS1_PHY_442_DATA 0x00000000
+#define DDRSS1_PHY_443_DATA 0x00000000
+#define DDRSS1_PHY_444_DATA 0x00000000
+#define DDRSS1_PHY_445_DATA 0x00000000
+#define DDRSS1_PHY_446_DATA 0x00000000
+#define DDRSS1_PHY_447_DATA 0x00000000
+#define DDRSS1_PHY_448_DATA 0x00000000
+#define DDRSS1_PHY_449_DATA 0x00000000
+#define DDRSS1_PHY_450_DATA 0x00000000
+#define DDRSS1_PHY_451_DATA 0x00000000
+#define DDRSS1_PHY_452_DATA 0x00000000
+#define DDRSS1_PHY_453_DATA 0x00000000
+#define DDRSS1_PHY_454_DATA 0x00000000
+#define DDRSS1_PHY_455_DATA 0x00000000
+#define DDRSS1_PHY_456_DATA 0x00000000
+#define DDRSS1_PHY_457_DATA 0x00000000
+#define DDRSS1_PHY_458_DATA 0x00000000
+#define DDRSS1_PHY_459_DATA 0x00000000
+#define DDRSS1_PHY_460_DATA 0x00000000
+#define DDRSS1_PHY_461_DATA 0x00000000
+#define DDRSS1_PHY_462_DATA 0x00000000
+#define DDRSS1_PHY_463_DATA 0x00000000
+#define DDRSS1_PHY_464_DATA 0x00000000
+#define DDRSS1_PHY_465_DATA 0x00000000
+#define DDRSS1_PHY_466_DATA 0x00000000
+#define DDRSS1_PHY_467_DATA 0x00000000
+#define DDRSS1_PHY_468_DATA 0x00000000
+#define DDRSS1_PHY_469_DATA 0x00000000
+#define DDRSS1_PHY_470_DATA 0x00000000
+#define DDRSS1_PHY_471_DATA 0x00000000
+#define DDRSS1_PHY_472_DATA 0x00000000
+#define DDRSS1_PHY_473_DATA 0x00000000
+#define DDRSS1_PHY_474_DATA 0x00000000
+#define DDRSS1_PHY_475_DATA 0x00000000
+#define DDRSS1_PHY_476_DATA 0x00000000
+#define DDRSS1_PHY_477_DATA 0x00000000
+#define DDRSS1_PHY_478_DATA 0x00000000
+#define DDRSS1_PHY_479_DATA 0x00000000
+#define DDRSS1_PHY_480_DATA 0x00000000
+#define DDRSS1_PHY_481_DATA 0x00000000
+#define DDRSS1_PHY_482_DATA 0x00000000
+#define DDRSS1_PHY_483_DATA 0x00000000
+#define DDRSS1_PHY_484_DATA 0x00000000
+#define DDRSS1_PHY_485_DATA 0x00000000
+#define DDRSS1_PHY_486_DATA 0x00000000
+#define DDRSS1_PHY_487_DATA 0x00000000
+#define DDRSS1_PHY_488_DATA 0x00000000
+#define DDRSS1_PHY_489_DATA 0x00000000
+#define DDRSS1_PHY_490_DATA 0x00000000
+#define DDRSS1_PHY_491_DATA 0x00000000
+#define DDRSS1_PHY_492_DATA 0x00000000
+#define DDRSS1_PHY_493_DATA 0x00000000
+#define DDRSS1_PHY_494_DATA 0x00000000
+#define DDRSS1_PHY_495_DATA 0x00000000
+#define DDRSS1_PHY_496_DATA 0x00000000
+#define DDRSS1_PHY_497_DATA 0x00000000
+#define DDRSS1_PHY_498_DATA 0x00000000
+#define DDRSS1_PHY_499_DATA 0x00000000
+#define DDRSS1_PHY_500_DATA 0x00000000
+#define DDRSS1_PHY_501_DATA 0x00000000
+#define DDRSS1_PHY_502_DATA 0x00000000
+#define DDRSS1_PHY_503_DATA 0x00000000
+#define DDRSS1_PHY_504_DATA 0x00000000
+#define DDRSS1_PHY_505_DATA 0x00000000
+#define DDRSS1_PHY_506_DATA 0x00000000
+#define DDRSS1_PHY_507_DATA 0x00000000
+#define DDRSS1_PHY_508_DATA 0x00000000
+#define DDRSS1_PHY_509_DATA 0x00000000
+#define DDRSS1_PHY_510_DATA 0x00000000
+#define DDRSS1_PHY_511_DATA 0x00000000
+#define DDRSS1_PHY_512_DATA 0x000004F0
+#define DDRSS1_PHY_513_DATA 0x00000000
+#define DDRSS1_PHY_514_DATA 0x00030200
+#define DDRSS1_PHY_515_DATA 0x00000000
+#define DDRSS1_PHY_516_DATA 0x00000000
+#define DDRSS1_PHY_517_DATA 0x01030000
+#define DDRSS1_PHY_518_DATA 0x00010000
+#define DDRSS1_PHY_519_DATA 0x01030004
+#define DDRSS1_PHY_520_DATA 0x01000000
+#define DDRSS1_PHY_521_DATA 0x00000000
+#define DDRSS1_PHY_522_DATA 0x00000000
+#define DDRSS1_PHY_523_DATA 0x01000001
+#define DDRSS1_PHY_524_DATA 0x00000100
+#define DDRSS1_PHY_525_DATA 0x000800C0
+#define DDRSS1_PHY_526_DATA 0x060100CC
+#define DDRSS1_PHY_527_DATA 0x00030066
+#define DDRSS1_PHY_528_DATA 0x00000000
+#define DDRSS1_PHY_529_DATA 0x00000301
+#define DDRSS1_PHY_530_DATA 0x0000AAAA
+#define DDRSS1_PHY_531_DATA 0x00005555
+#define DDRSS1_PHY_532_DATA 0x0000B5B5
+#define DDRSS1_PHY_533_DATA 0x00004A4A
+#define DDRSS1_PHY_534_DATA 0x00005656
+#define DDRSS1_PHY_535_DATA 0x0000A9A9
+#define DDRSS1_PHY_536_DATA 0x0000A9A9
+#define DDRSS1_PHY_537_DATA 0x0000B5B5
+#define DDRSS1_PHY_538_DATA 0x00000000
+#define DDRSS1_PHY_539_DATA 0x00000000
+#define DDRSS1_PHY_540_DATA 0x2A000000
+#define DDRSS1_PHY_541_DATA 0x00000808
+#define DDRSS1_PHY_542_DATA 0x0F000000
+#define DDRSS1_PHY_543_DATA 0x00000F0F
+#define DDRSS1_PHY_544_DATA 0x10400000
+#define DDRSS1_PHY_545_DATA 0x0C002006
+#define DDRSS1_PHY_546_DATA 0x00000000
+#define DDRSS1_PHY_547_DATA 0x00000000
+#define DDRSS1_PHY_548_DATA 0x55555555
+#define DDRSS1_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_550_DATA 0x55555555
+#define DDRSS1_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_552_DATA 0x00005555
+#define DDRSS1_PHY_553_DATA 0x01000100
+#define DDRSS1_PHY_554_DATA 0x00800180
+#define DDRSS1_PHY_555_DATA 0x00000001
+#define DDRSS1_PHY_556_DATA 0x00000000
+#define DDRSS1_PHY_557_DATA 0x00000000
+#define DDRSS1_PHY_558_DATA 0x00000000
+#define DDRSS1_PHY_559_DATA 0x00000000
+#define DDRSS1_PHY_560_DATA 0x00000000
+#define DDRSS1_PHY_561_DATA 0x00000000
+#define DDRSS1_PHY_562_DATA 0x00000000
+#define DDRSS1_PHY_563_DATA 0x00000000
+#define DDRSS1_PHY_564_DATA 0x00000000
+#define DDRSS1_PHY_565_DATA 0x00000000
+#define DDRSS1_PHY_566_DATA 0x00000000
+#define DDRSS1_PHY_567_DATA 0x00000000
+#define DDRSS1_PHY_568_DATA 0x00000000
+#define DDRSS1_PHY_569_DATA 0x00000000
+#define DDRSS1_PHY_570_DATA 0x00000000
+#define DDRSS1_PHY_571_DATA 0x00000000
+#define DDRSS1_PHY_572_DATA 0x00000000
+#define DDRSS1_PHY_573_DATA 0x00000000
+#define DDRSS1_PHY_574_DATA 0x00000000
+#define DDRSS1_PHY_575_DATA 0x00000000
+#define DDRSS1_PHY_576_DATA 0x00000000
+#define DDRSS1_PHY_577_DATA 0x00000000
+#define DDRSS1_PHY_578_DATA 0x00000104
+#define DDRSS1_PHY_579_DATA 0x00000120
+#define DDRSS1_PHY_580_DATA 0x00000000
+#define DDRSS1_PHY_581_DATA 0x00000000
+#define DDRSS1_PHY_582_DATA 0x00000000
+#define DDRSS1_PHY_583_DATA 0x00000000
+#define DDRSS1_PHY_584_DATA 0x00000000
+#define DDRSS1_PHY_585_DATA 0x00000000
+#define DDRSS1_PHY_586_DATA 0x00000000
+#define DDRSS1_PHY_587_DATA 0x00000001
+#define DDRSS1_PHY_588_DATA 0x07FF0000
+#define DDRSS1_PHY_589_DATA 0x0080081F
+#define DDRSS1_PHY_590_DATA 0x00081020
+#define DDRSS1_PHY_591_DATA 0x04010000
+#define DDRSS1_PHY_592_DATA 0x00000000
+#define DDRSS1_PHY_593_DATA 0x00000000
+#define DDRSS1_PHY_594_DATA 0x00000000
+#define DDRSS1_PHY_595_DATA 0x00000100
+#define DDRSS1_PHY_596_DATA 0x01CC0C01
+#define DDRSS1_PHY_597_DATA 0x1003CC0C
+#define DDRSS1_PHY_598_DATA 0x20000140
+#define DDRSS1_PHY_599_DATA 0x07FF0200
+#define DDRSS1_PHY_600_DATA 0x0000DD01
+#define DDRSS1_PHY_601_DATA 0x10100303
+#define DDRSS1_PHY_602_DATA 0x10101010
+#define DDRSS1_PHY_603_DATA 0x10101010
+#define DDRSS1_PHY_604_DATA 0x00021010
+#define DDRSS1_PHY_605_DATA 0x00100010
+#define DDRSS1_PHY_606_DATA 0x00100010
+#define DDRSS1_PHY_607_DATA 0x00100010
+#define DDRSS1_PHY_608_DATA 0x00100010
+#define DDRSS1_PHY_609_DATA 0x00050010
+#define DDRSS1_PHY_610_DATA 0x51517041
+#define DDRSS1_PHY_611_DATA 0x31C06001
+#define DDRSS1_PHY_612_DATA 0x07AB0340
+#define DDRSS1_PHY_613_DATA 0x00C0C001
+#define DDRSS1_PHY_614_DATA 0x0E0D0001
+#define DDRSS1_PHY_615_DATA 0x10001000
+#define DDRSS1_PHY_616_DATA 0x0C083E42
+#define DDRSS1_PHY_617_DATA 0x0F0C3701
+#define DDRSS1_PHY_618_DATA 0x01000140
+#define DDRSS1_PHY_619_DATA 0x0C000420
+#define DDRSS1_PHY_620_DATA 0x00000198
+#define DDRSS1_PHY_621_DATA 0x0A0000D0
+#define DDRSS1_PHY_622_DATA 0x00030200
+#define DDRSS1_PHY_623_DATA 0x02800000
+#define DDRSS1_PHY_624_DATA 0x80800000
+#define DDRSS1_PHY_625_DATA 0x000E2010
+#define DDRSS1_PHY_626_DATA 0x76543210
+#define DDRSS1_PHY_627_DATA 0x00000008
+#define DDRSS1_PHY_628_DATA 0x02800280
+#define DDRSS1_PHY_629_DATA 0x02800280
+#define DDRSS1_PHY_630_DATA 0x02800280
+#define DDRSS1_PHY_631_DATA 0x02800280
+#define DDRSS1_PHY_632_DATA 0x00000280
+#define DDRSS1_PHY_633_DATA 0x0000A000
+#define DDRSS1_PHY_634_DATA 0x00A000A0
+#define DDRSS1_PHY_635_DATA 0x00A000A0
+#define DDRSS1_PHY_636_DATA 0x00A000A0
+#define DDRSS1_PHY_637_DATA 0x00A000A0
+#define DDRSS1_PHY_638_DATA 0x00A000A0
+#define DDRSS1_PHY_639_DATA 0x00A000A0
+#define DDRSS1_PHY_640_DATA 0x00A000A0
+#define DDRSS1_PHY_641_DATA 0x00A000A0
+#define DDRSS1_PHY_642_DATA 0x01C200A0
+#define DDRSS1_PHY_643_DATA 0x01A00005
+#define DDRSS1_PHY_644_DATA 0x00000000
+#define DDRSS1_PHY_645_DATA 0x00000000
+#define DDRSS1_PHY_646_DATA 0x00080200
+#define DDRSS1_PHY_647_DATA 0x00000000
+#define DDRSS1_PHY_648_DATA 0x20202000
+#define DDRSS1_PHY_649_DATA 0x20202020
+#define DDRSS1_PHY_650_DATA 0xF0F02020
+#define DDRSS1_PHY_651_DATA 0x00000000
+#define DDRSS1_PHY_652_DATA 0x00000000
+#define DDRSS1_PHY_653_DATA 0x00000000
+#define DDRSS1_PHY_654_DATA 0x00000000
+#define DDRSS1_PHY_655_DATA 0x00000000
+#define DDRSS1_PHY_656_DATA 0x00000000
+#define DDRSS1_PHY_657_DATA 0x00000000
+#define DDRSS1_PHY_658_DATA 0x00000000
+#define DDRSS1_PHY_659_DATA 0x00000000
+#define DDRSS1_PHY_660_DATA 0x00000000
+#define DDRSS1_PHY_661_DATA 0x00000000
+#define DDRSS1_PHY_662_DATA 0x00000000
+#define DDRSS1_PHY_663_DATA 0x00000000
+#define DDRSS1_PHY_664_DATA 0x00000000
+#define DDRSS1_PHY_665_DATA 0x00000000
+#define DDRSS1_PHY_666_DATA 0x00000000
+#define DDRSS1_PHY_667_DATA 0x00000000
+#define DDRSS1_PHY_668_DATA 0x00000000
+#define DDRSS1_PHY_669_DATA 0x00000000
+#define DDRSS1_PHY_670_DATA 0x00000000
+#define DDRSS1_PHY_671_DATA 0x00000000
+#define DDRSS1_PHY_672_DATA 0x00000000
+#define DDRSS1_PHY_673_DATA 0x00000000
+#define DDRSS1_PHY_674_DATA 0x00000000
+#define DDRSS1_PHY_675_DATA 0x00000000
+#define DDRSS1_PHY_676_DATA 0x00000000
+#define DDRSS1_PHY_677_DATA 0x00000000
+#define DDRSS1_PHY_678_DATA 0x00000000
+#define DDRSS1_PHY_679_DATA 0x00000000
+#define DDRSS1_PHY_680_DATA 0x00000000
+#define DDRSS1_PHY_681_DATA 0x00000000
+#define DDRSS1_PHY_682_DATA 0x00000000
+#define DDRSS1_PHY_683_DATA 0x00000000
+#define DDRSS1_PHY_684_DATA 0x00000000
+#define DDRSS1_PHY_685_DATA 0x00000000
+#define DDRSS1_PHY_686_DATA 0x00000000
+#define DDRSS1_PHY_687_DATA 0x00000000
+#define DDRSS1_PHY_688_DATA 0x00000000
+#define DDRSS1_PHY_689_DATA 0x00000000
+#define DDRSS1_PHY_690_DATA 0x00000000
+#define DDRSS1_PHY_691_DATA 0x00000000
+#define DDRSS1_PHY_692_DATA 0x00000000
+#define DDRSS1_PHY_693_DATA 0x00000000
+#define DDRSS1_PHY_694_DATA 0x00000000
+#define DDRSS1_PHY_695_DATA 0x00000000
+#define DDRSS1_PHY_696_DATA 0x00000000
+#define DDRSS1_PHY_697_DATA 0x00000000
+#define DDRSS1_PHY_698_DATA 0x00000000
+#define DDRSS1_PHY_699_DATA 0x00000000
+#define DDRSS1_PHY_700_DATA 0x00000000
+#define DDRSS1_PHY_701_DATA 0x00000000
+#define DDRSS1_PHY_702_DATA 0x00000000
+#define DDRSS1_PHY_703_DATA 0x00000000
+#define DDRSS1_PHY_704_DATA 0x00000000
+#define DDRSS1_PHY_705_DATA 0x00000000
+#define DDRSS1_PHY_706_DATA 0x00000000
+#define DDRSS1_PHY_707_DATA 0x00000000
+#define DDRSS1_PHY_708_DATA 0x00000000
+#define DDRSS1_PHY_709_DATA 0x00000000
+#define DDRSS1_PHY_710_DATA 0x00000000
+#define DDRSS1_PHY_711_DATA 0x00000000
+#define DDRSS1_PHY_712_DATA 0x00000000
+#define DDRSS1_PHY_713_DATA 0x00000000
+#define DDRSS1_PHY_714_DATA 0x00000000
+#define DDRSS1_PHY_715_DATA 0x00000000
+#define DDRSS1_PHY_716_DATA 0x00000000
+#define DDRSS1_PHY_717_DATA 0x00000000
+#define DDRSS1_PHY_718_DATA 0x00000000
+#define DDRSS1_PHY_719_DATA 0x00000000
+#define DDRSS1_PHY_720_DATA 0x00000000
+#define DDRSS1_PHY_721_DATA 0x00000000
+#define DDRSS1_PHY_722_DATA 0x00000000
+#define DDRSS1_PHY_723_DATA 0x00000000
+#define DDRSS1_PHY_724_DATA 0x00000000
+#define DDRSS1_PHY_725_DATA 0x00000000
+#define DDRSS1_PHY_726_DATA 0x00000000
+#define DDRSS1_PHY_727_DATA 0x00000000
+#define DDRSS1_PHY_728_DATA 0x00000000
+#define DDRSS1_PHY_729_DATA 0x00000000
+#define DDRSS1_PHY_730_DATA 0x00000000
+#define DDRSS1_PHY_731_DATA 0x00000000
+#define DDRSS1_PHY_732_DATA 0x00000000
+#define DDRSS1_PHY_733_DATA 0x00000000
+#define DDRSS1_PHY_734_DATA 0x00000000
+#define DDRSS1_PHY_735_DATA 0x00000000
+#define DDRSS1_PHY_736_DATA 0x00000000
+#define DDRSS1_PHY_737_DATA 0x00000000
+#define DDRSS1_PHY_738_DATA 0x00000000
+#define DDRSS1_PHY_739_DATA 0x00000000
+#define DDRSS1_PHY_740_DATA 0x00000000
+#define DDRSS1_PHY_741_DATA 0x00000000
+#define DDRSS1_PHY_742_DATA 0x00000000
+#define DDRSS1_PHY_743_DATA 0x00000000
+#define DDRSS1_PHY_744_DATA 0x00000000
+#define DDRSS1_PHY_745_DATA 0x00000000
+#define DDRSS1_PHY_746_DATA 0x00000000
+#define DDRSS1_PHY_747_DATA 0x00000000
+#define DDRSS1_PHY_748_DATA 0x00000000
+#define DDRSS1_PHY_749_DATA 0x00000000
+#define DDRSS1_PHY_750_DATA 0x00000000
+#define DDRSS1_PHY_751_DATA 0x00000000
+#define DDRSS1_PHY_752_DATA 0x00000000
+#define DDRSS1_PHY_753_DATA 0x00000000
+#define DDRSS1_PHY_754_DATA 0x00000000
+#define DDRSS1_PHY_755_DATA 0x00000000
+#define DDRSS1_PHY_756_DATA 0x00000000
+#define DDRSS1_PHY_757_DATA 0x00000000
+#define DDRSS1_PHY_758_DATA 0x00000000
+#define DDRSS1_PHY_759_DATA 0x00000000
+#define DDRSS1_PHY_760_DATA 0x00000000
+#define DDRSS1_PHY_761_DATA 0x00000000
+#define DDRSS1_PHY_762_DATA 0x00000000
+#define DDRSS1_PHY_763_DATA 0x00000000
+#define DDRSS1_PHY_764_DATA 0x00000000
+#define DDRSS1_PHY_765_DATA 0x00000000
+#define DDRSS1_PHY_766_DATA 0x00000000
+#define DDRSS1_PHY_767_DATA 0x00000000
+#define DDRSS1_PHY_768_DATA 0x000004F0
+#define DDRSS1_PHY_769_DATA 0x00000000
+#define DDRSS1_PHY_770_DATA 0x00030200
+#define DDRSS1_PHY_771_DATA 0x00000000
+#define DDRSS1_PHY_772_DATA 0x00000000
+#define DDRSS1_PHY_773_DATA 0x01030000
+#define DDRSS1_PHY_774_DATA 0x00010000
+#define DDRSS1_PHY_775_DATA 0x01030004
+#define DDRSS1_PHY_776_DATA 0x01000000
+#define DDRSS1_PHY_777_DATA 0x00000000
+#define DDRSS1_PHY_778_DATA 0x00000000
+#define DDRSS1_PHY_779_DATA 0x01000001
+#define DDRSS1_PHY_780_DATA 0x00000100
+#define DDRSS1_PHY_781_DATA 0x000800C0
+#define DDRSS1_PHY_782_DATA 0x060100CC
+#define DDRSS1_PHY_783_DATA 0x00030066
+#define DDRSS1_PHY_784_DATA 0x00000000
+#define DDRSS1_PHY_785_DATA 0x00000301
+#define DDRSS1_PHY_786_DATA 0x0000AAAA
+#define DDRSS1_PHY_787_DATA 0x00005555
+#define DDRSS1_PHY_788_DATA 0x0000B5B5
+#define DDRSS1_PHY_789_DATA 0x00004A4A
+#define DDRSS1_PHY_790_DATA 0x00005656
+#define DDRSS1_PHY_791_DATA 0x0000A9A9
+#define DDRSS1_PHY_792_DATA 0x0000A9A9
+#define DDRSS1_PHY_793_DATA 0x0000B5B5
+#define DDRSS1_PHY_794_DATA 0x00000000
+#define DDRSS1_PHY_795_DATA 0x00000000
+#define DDRSS1_PHY_796_DATA 0x2A000000
+#define DDRSS1_PHY_797_DATA 0x00000808
+#define DDRSS1_PHY_798_DATA 0x0F000000
+#define DDRSS1_PHY_799_DATA 0x00000F0F
+#define DDRSS1_PHY_800_DATA 0x10400000
+#define DDRSS1_PHY_801_DATA 0x0C002006
+#define DDRSS1_PHY_802_DATA 0x00000000
+#define DDRSS1_PHY_803_DATA 0x00000000
+#define DDRSS1_PHY_804_DATA 0x55555555
+#define DDRSS1_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_806_DATA 0x55555555
+#define DDRSS1_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS1_PHY_808_DATA 0x00005555
+#define DDRSS1_PHY_809_DATA 0x01000100
+#define DDRSS1_PHY_810_DATA 0x00800180
+#define DDRSS1_PHY_811_DATA 0x00000000
+#define DDRSS1_PHY_812_DATA 0x00000000
+#define DDRSS1_PHY_813_DATA 0x00000000
+#define DDRSS1_PHY_814_DATA 0x00000000
+#define DDRSS1_PHY_815_DATA 0x00000000
+#define DDRSS1_PHY_816_DATA 0x00000000
+#define DDRSS1_PHY_817_DATA 0x00000000
+#define DDRSS1_PHY_818_DATA 0x00000000
+#define DDRSS1_PHY_819_DATA 0x00000000
+#define DDRSS1_PHY_820_DATA 0x00000000
+#define DDRSS1_PHY_821_DATA 0x00000000
+#define DDRSS1_PHY_822_DATA 0x00000000
+#define DDRSS1_PHY_823_DATA 0x00000000
+#define DDRSS1_PHY_824_DATA 0x00000000
+#define DDRSS1_PHY_825_DATA 0x00000000
+#define DDRSS1_PHY_826_DATA 0x00000000
+#define DDRSS1_PHY_827_DATA 0x00000000
+#define DDRSS1_PHY_828_DATA 0x00000000
+#define DDRSS1_PHY_829_DATA 0x00000000
+#define DDRSS1_PHY_830_DATA 0x00000000
+#define DDRSS1_PHY_831_DATA 0x00000000
+#define DDRSS1_PHY_832_DATA 0x00000000
+#define DDRSS1_PHY_833_DATA 0x00000000
+#define DDRSS1_PHY_834_DATA 0x00000104
+#define DDRSS1_PHY_835_DATA 0x00000120
+#define DDRSS1_PHY_836_DATA 0x00000000
+#define DDRSS1_PHY_837_DATA 0x00000000
+#define DDRSS1_PHY_838_DATA 0x00000000
+#define DDRSS1_PHY_839_DATA 0x00000000
+#define DDRSS1_PHY_840_DATA 0x00000000
+#define DDRSS1_PHY_841_DATA 0x00000000
+#define DDRSS1_PHY_842_DATA 0x00000000
+#define DDRSS1_PHY_843_DATA 0x00000001
+#define DDRSS1_PHY_844_DATA 0x07FF0000
+#define DDRSS1_PHY_845_DATA 0x0080081F
+#define DDRSS1_PHY_846_DATA 0x00081020
+#define DDRSS1_PHY_847_DATA 0x04010000
+#define DDRSS1_PHY_848_DATA 0x00000000
+#define DDRSS1_PHY_849_DATA 0x00000000
+#define DDRSS1_PHY_850_DATA 0x00000000
+#define DDRSS1_PHY_851_DATA 0x00000100
+#define DDRSS1_PHY_852_DATA 0x01CC0C01
+#define DDRSS1_PHY_853_DATA 0x1003CC0C
+#define DDRSS1_PHY_854_DATA 0x20000140
+#define DDRSS1_PHY_855_DATA 0x07FF0200
+#define DDRSS1_PHY_856_DATA 0x0000DD01
+#define DDRSS1_PHY_857_DATA 0x10100303
+#define DDRSS1_PHY_858_DATA 0x10101010
+#define DDRSS1_PHY_859_DATA 0x10101010
+#define DDRSS1_PHY_860_DATA 0x00021010
+#define DDRSS1_PHY_861_DATA 0x00100010
+#define DDRSS1_PHY_862_DATA 0x00100010
+#define DDRSS1_PHY_863_DATA 0x00100010
+#define DDRSS1_PHY_864_DATA 0x00100010
+#define DDRSS1_PHY_865_DATA 0x00050010
+#define DDRSS1_PHY_866_DATA 0x51517041
+#define DDRSS1_PHY_867_DATA 0x31C06001
+#define DDRSS1_PHY_868_DATA 0x07AB0340
+#define DDRSS1_PHY_869_DATA 0x00C0C001
+#define DDRSS1_PHY_870_DATA 0x0E0D0001
+#define DDRSS1_PHY_871_DATA 0x10001000
+#define DDRSS1_PHY_872_DATA 0x0C083E42
+#define DDRSS1_PHY_873_DATA 0x0F0C3701
+#define DDRSS1_PHY_874_DATA 0x01000140
+#define DDRSS1_PHY_875_DATA 0x0C000420
+#define DDRSS1_PHY_876_DATA 0x00000198
+#define DDRSS1_PHY_877_DATA 0x0A0000D0
+#define DDRSS1_PHY_878_DATA 0x00030200
+#define DDRSS1_PHY_879_DATA 0x02800000
+#define DDRSS1_PHY_880_DATA 0x80800000
+#define DDRSS1_PHY_881_DATA 0x000E2010
+#define DDRSS1_PHY_882_DATA 0x76543210
+#define DDRSS1_PHY_883_DATA 0x00000008
+#define DDRSS1_PHY_884_DATA 0x02800280
+#define DDRSS1_PHY_885_DATA 0x02800280
+#define DDRSS1_PHY_886_DATA 0x02800280
+#define DDRSS1_PHY_887_DATA 0x02800280
+#define DDRSS1_PHY_888_DATA 0x00000280
+#define DDRSS1_PHY_889_DATA 0x0000A000
+#define DDRSS1_PHY_890_DATA 0x00A000A0
+#define DDRSS1_PHY_891_DATA 0x00A000A0
+#define DDRSS1_PHY_892_DATA 0x00A000A0
+#define DDRSS1_PHY_893_DATA 0x00A000A0
+#define DDRSS1_PHY_894_DATA 0x00A000A0
+#define DDRSS1_PHY_895_DATA 0x00A000A0
+#define DDRSS1_PHY_896_DATA 0x00A000A0
+#define DDRSS1_PHY_897_DATA 0x00A000A0
+#define DDRSS1_PHY_898_DATA 0x01C200A0
+#define DDRSS1_PHY_899_DATA 0x01A00005
+#define DDRSS1_PHY_900_DATA 0x00000000
+#define DDRSS1_PHY_901_DATA 0x00000000
+#define DDRSS1_PHY_902_DATA 0x00080200
+#define DDRSS1_PHY_903_DATA 0x00000000
+#define DDRSS1_PHY_904_DATA 0x20202000
+#define DDRSS1_PHY_905_DATA 0x20202020
+#define DDRSS1_PHY_906_DATA 0xF0F02020
+#define DDRSS1_PHY_907_DATA 0x00000000
+#define DDRSS1_PHY_908_DATA 0x00000000
+#define DDRSS1_PHY_909_DATA 0x00000000
+#define DDRSS1_PHY_910_DATA 0x00000000
+#define DDRSS1_PHY_911_DATA 0x00000000
+#define DDRSS1_PHY_912_DATA 0x00000000
+#define DDRSS1_PHY_913_DATA 0x00000000
+#define DDRSS1_PHY_914_DATA 0x00000000
+#define DDRSS1_PHY_915_DATA 0x00000000
+#define DDRSS1_PHY_916_DATA 0x00000000
+#define DDRSS1_PHY_917_DATA 0x00000000
+#define DDRSS1_PHY_918_DATA 0x00000000
+#define DDRSS1_PHY_919_DATA 0x00000000
+#define DDRSS1_PHY_920_DATA 0x00000000
+#define DDRSS1_PHY_921_DATA 0x00000000
+#define DDRSS1_PHY_922_DATA 0x00000000
+#define DDRSS1_PHY_923_DATA 0x00000000
+#define DDRSS1_PHY_924_DATA 0x00000000
+#define DDRSS1_PHY_925_DATA 0x00000000
+#define DDRSS1_PHY_926_DATA 0x00000000
+#define DDRSS1_PHY_927_DATA 0x00000000
+#define DDRSS1_PHY_928_DATA 0x00000000
+#define DDRSS1_PHY_929_DATA 0x00000000
+#define DDRSS1_PHY_930_DATA 0x00000000
+#define DDRSS1_PHY_931_DATA 0x00000000
+#define DDRSS1_PHY_932_DATA 0x00000000
+#define DDRSS1_PHY_933_DATA 0x00000000
+#define DDRSS1_PHY_934_DATA 0x00000000
+#define DDRSS1_PHY_935_DATA 0x00000000
+#define DDRSS1_PHY_936_DATA 0x00000000
+#define DDRSS1_PHY_937_DATA 0x00000000
+#define DDRSS1_PHY_938_DATA 0x00000000
+#define DDRSS1_PHY_939_DATA 0x00000000
+#define DDRSS1_PHY_940_DATA 0x00000000
+#define DDRSS1_PHY_941_DATA 0x00000000
+#define DDRSS1_PHY_942_DATA 0x00000000
+#define DDRSS1_PHY_943_DATA 0x00000000
+#define DDRSS1_PHY_944_DATA 0x00000000
+#define DDRSS1_PHY_945_DATA 0x00000000
+#define DDRSS1_PHY_946_DATA 0x00000000
+#define DDRSS1_PHY_947_DATA 0x00000000
+#define DDRSS1_PHY_948_DATA 0x00000000
+#define DDRSS1_PHY_949_DATA 0x00000000
+#define DDRSS1_PHY_950_DATA 0x00000000
+#define DDRSS1_PHY_951_DATA 0x00000000
+#define DDRSS1_PHY_952_DATA 0x00000000
+#define DDRSS1_PHY_953_DATA 0x00000000
+#define DDRSS1_PHY_954_DATA 0x00000000
+#define DDRSS1_PHY_955_DATA 0x00000000
+#define DDRSS1_PHY_956_DATA 0x00000000
+#define DDRSS1_PHY_957_DATA 0x00000000
+#define DDRSS1_PHY_958_DATA 0x00000000
+#define DDRSS1_PHY_959_DATA 0x00000000
+#define DDRSS1_PHY_960_DATA 0x00000000
+#define DDRSS1_PHY_961_DATA 0x00000000
+#define DDRSS1_PHY_962_DATA 0x00000000
+#define DDRSS1_PHY_963_DATA 0x00000000
+#define DDRSS1_PHY_964_DATA 0x00000000
+#define DDRSS1_PHY_965_DATA 0x00000000
+#define DDRSS1_PHY_966_DATA 0x00000000
+#define DDRSS1_PHY_967_DATA 0x00000000
+#define DDRSS1_PHY_968_DATA 0x00000000
+#define DDRSS1_PHY_969_DATA 0x00000000
+#define DDRSS1_PHY_970_DATA 0x00000000
+#define DDRSS1_PHY_971_DATA 0x00000000
+#define DDRSS1_PHY_972_DATA 0x00000000
+#define DDRSS1_PHY_973_DATA 0x00000000
+#define DDRSS1_PHY_974_DATA 0x00000000
+#define DDRSS1_PHY_975_DATA 0x00000000
+#define DDRSS1_PHY_976_DATA 0x00000000
+#define DDRSS1_PHY_977_DATA 0x00000000
+#define DDRSS1_PHY_978_DATA 0x00000000
+#define DDRSS1_PHY_979_DATA 0x00000000
+#define DDRSS1_PHY_980_DATA 0x00000000
+#define DDRSS1_PHY_981_DATA 0x00000000
+#define DDRSS1_PHY_982_DATA 0x00000000
+#define DDRSS1_PHY_983_DATA 0x00000000
+#define DDRSS1_PHY_984_DATA 0x00000000
+#define DDRSS1_PHY_985_DATA 0x00000000
+#define DDRSS1_PHY_986_DATA 0x00000000
+#define DDRSS1_PHY_987_DATA 0x00000000
+#define DDRSS1_PHY_988_DATA 0x00000000
+#define DDRSS1_PHY_989_DATA 0x00000000
+#define DDRSS1_PHY_990_DATA 0x00000000
+#define DDRSS1_PHY_991_DATA 0x00000000
+#define DDRSS1_PHY_992_DATA 0x00000000
+#define DDRSS1_PHY_993_DATA 0x00000000
+#define DDRSS1_PHY_994_DATA 0x00000000
+#define DDRSS1_PHY_995_DATA 0x00000000
+#define DDRSS1_PHY_996_DATA 0x00000000
+#define DDRSS1_PHY_997_DATA 0x00000000
+#define DDRSS1_PHY_998_DATA 0x00000000
+#define DDRSS1_PHY_999_DATA 0x00000000
+#define DDRSS1_PHY_1000_DATA 0x00000000
+#define DDRSS1_PHY_1001_DATA 0x00000000
+#define DDRSS1_PHY_1002_DATA 0x00000000
+#define DDRSS1_PHY_1003_DATA 0x00000000
+#define DDRSS1_PHY_1004_DATA 0x00000000
+#define DDRSS1_PHY_1005_DATA 0x00000000
+#define DDRSS1_PHY_1006_DATA 0x00000000
+#define DDRSS1_PHY_1007_DATA 0x00000000
+#define DDRSS1_PHY_1008_DATA 0x00000000
+#define DDRSS1_PHY_1009_DATA 0x00000000
+#define DDRSS1_PHY_1010_DATA 0x00000000
+#define DDRSS1_PHY_1011_DATA 0x00000000
+#define DDRSS1_PHY_1012_DATA 0x00000000
+#define DDRSS1_PHY_1013_DATA 0x00000000
+#define DDRSS1_PHY_1014_DATA 0x00000000
+#define DDRSS1_PHY_1015_DATA 0x00000000
+#define DDRSS1_PHY_1016_DATA 0x00000000
+#define DDRSS1_PHY_1017_DATA 0x00000000
+#define DDRSS1_PHY_1018_DATA 0x00000000
+#define DDRSS1_PHY_1019_DATA 0x00000000
+#define DDRSS1_PHY_1020_DATA 0x00000000
+#define DDRSS1_PHY_1021_DATA 0x00000000
+#define DDRSS1_PHY_1022_DATA 0x00000000
+#define DDRSS1_PHY_1023_DATA 0x00000000
+#define DDRSS1_PHY_1024_DATA 0x00000000
+#define DDRSS1_PHY_1025_DATA 0x00000000
+#define DDRSS1_PHY_1026_DATA 0x00000000
+#define DDRSS1_PHY_1027_DATA 0x00000000
+#define DDRSS1_PHY_1028_DATA 0x00000000
+#define DDRSS1_PHY_1029_DATA 0x00000100
+#define DDRSS1_PHY_1030_DATA 0x00000200
+#define DDRSS1_PHY_1031_DATA 0x00000000
+#define DDRSS1_PHY_1032_DATA 0x00000000
+#define DDRSS1_PHY_1033_DATA 0x00000000
+#define DDRSS1_PHY_1034_DATA 0x00000000
+#define DDRSS1_PHY_1035_DATA 0x00400000
+#define DDRSS1_PHY_1036_DATA 0x00000080
+#define DDRSS1_PHY_1037_DATA 0x00DCBA98
+#define DDRSS1_PHY_1038_DATA 0x03000000
+#define DDRSS1_PHY_1039_DATA 0x00200000
+#define DDRSS1_PHY_1040_DATA 0x00000000
+#define DDRSS1_PHY_1041_DATA 0x00000000
+#define DDRSS1_PHY_1042_DATA 0x00000000
+#define DDRSS1_PHY_1043_DATA 0x00000000
+#define DDRSS1_PHY_1044_DATA 0x00000000
+#define DDRSS1_PHY_1045_DATA 0x0000002A
+#define DDRSS1_PHY_1046_DATA 0x00000015
+#define DDRSS1_PHY_1047_DATA 0x00000015
+#define DDRSS1_PHY_1048_DATA 0x0000002A
+#define DDRSS1_PHY_1049_DATA 0x00000033
+#define DDRSS1_PHY_1050_DATA 0x0000000C
+#define DDRSS1_PHY_1051_DATA 0x0000000C
+#define DDRSS1_PHY_1052_DATA 0x00000033
+#define DDRSS1_PHY_1053_DATA 0x00543210
+#define DDRSS1_PHY_1054_DATA 0x003F0000
+#define DDRSS1_PHY_1055_DATA 0x000F013F
+#define DDRSS1_PHY_1056_DATA 0x20202003
+#define DDRSS1_PHY_1057_DATA 0x00202020
+#define DDRSS1_PHY_1058_DATA 0x20008008
+#define DDRSS1_PHY_1059_DATA 0x00000810
+#define DDRSS1_PHY_1060_DATA 0x00000F00
+#define DDRSS1_PHY_1061_DATA 0x00000000
+#define DDRSS1_PHY_1062_DATA 0x00000000
+#define DDRSS1_PHY_1063_DATA 0x00000000
+#define DDRSS1_PHY_1064_DATA 0x000305CC
+#define DDRSS1_PHY_1065_DATA 0x00030000
+#define DDRSS1_PHY_1066_DATA 0x00000300
+#define DDRSS1_PHY_1067_DATA 0x00000300
+#define DDRSS1_PHY_1068_DATA 0x00000300
+#define DDRSS1_PHY_1069_DATA 0x00000300
+#define DDRSS1_PHY_1070_DATA 0x00000300
+#define DDRSS1_PHY_1071_DATA 0x42080010
+#define DDRSS1_PHY_1072_DATA 0x0000803E
+#define DDRSS1_PHY_1073_DATA 0x00000001
+#define DDRSS1_PHY_1074_DATA 0x01000102
+#define DDRSS1_PHY_1075_DATA 0x00008000
+#define DDRSS1_PHY_1076_DATA 0x00000000
+#define DDRSS1_PHY_1077_DATA 0x00000000
+#define DDRSS1_PHY_1078_DATA 0x00000000
+#define DDRSS1_PHY_1079_DATA 0x00000000
+#define DDRSS1_PHY_1080_DATA 0x00000000
+#define DDRSS1_PHY_1081_DATA 0x00000000
+#define DDRSS1_PHY_1082_DATA 0x00000000
+#define DDRSS1_PHY_1083_DATA 0x00000000
+#define DDRSS1_PHY_1084_DATA 0x00000000
+#define DDRSS1_PHY_1085_DATA 0x00000000
+#define DDRSS1_PHY_1086_DATA 0x00000000
+#define DDRSS1_PHY_1087_DATA 0x00000000
+#define DDRSS1_PHY_1088_DATA 0x00000000
+#define DDRSS1_PHY_1089_DATA 0x00000000
+#define DDRSS1_PHY_1090_DATA 0x00000000
+#define DDRSS1_PHY_1091_DATA 0x00000000
+#define DDRSS1_PHY_1092_DATA 0x00000000
+#define DDRSS1_PHY_1093_DATA 0x00000000
+#define DDRSS1_PHY_1094_DATA 0x00000000
+#define DDRSS1_PHY_1095_DATA 0x00000000
+#define DDRSS1_PHY_1096_DATA 0x00000000
+#define DDRSS1_PHY_1097_DATA 0x00000000
+#define DDRSS1_PHY_1098_DATA 0x00000000
+#define DDRSS1_PHY_1099_DATA 0x00000000
+#define DDRSS1_PHY_1100_DATA 0x00000000
+#define DDRSS1_PHY_1101_DATA 0x00000000
+#define DDRSS1_PHY_1102_DATA 0x00000000
+#define DDRSS1_PHY_1103_DATA 0x00000000
+#define DDRSS1_PHY_1104_DATA 0x00000000
+#define DDRSS1_PHY_1105_DATA 0x00000000
+#define DDRSS1_PHY_1106_DATA 0x00000000
+#define DDRSS1_PHY_1107_DATA 0x00000000
+#define DDRSS1_PHY_1108_DATA 0x00000000
+#define DDRSS1_PHY_1109_DATA 0x00000000
+#define DDRSS1_PHY_1110_DATA 0x00000000
+#define DDRSS1_PHY_1111_DATA 0x00000000
+#define DDRSS1_PHY_1112_DATA 0x00000000
+#define DDRSS1_PHY_1113_DATA 0x00000000
+#define DDRSS1_PHY_1114_DATA 0x00000000
+#define DDRSS1_PHY_1115_DATA 0x00000000
+#define DDRSS1_PHY_1116_DATA 0x00000000
+#define DDRSS1_PHY_1117_DATA 0x00000000
+#define DDRSS1_PHY_1118_DATA 0x00000000
+#define DDRSS1_PHY_1119_DATA 0x00000000
+#define DDRSS1_PHY_1120_DATA 0x00000000
+#define DDRSS1_PHY_1121_DATA 0x00000000
+#define DDRSS1_PHY_1122_DATA 0x00000000
+#define DDRSS1_PHY_1123_DATA 0x00000000
+#define DDRSS1_PHY_1124_DATA 0x00000000
+#define DDRSS1_PHY_1125_DATA 0x00000000
+#define DDRSS1_PHY_1126_DATA 0x00000000
+#define DDRSS1_PHY_1127_DATA 0x00000000
+#define DDRSS1_PHY_1128_DATA 0x00000000
+#define DDRSS1_PHY_1129_DATA 0x00000000
+#define DDRSS1_PHY_1130_DATA 0x00000000
+#define DDRSS1_PHY_1131_DATA 0x00000000
+#define DDRSS1_PHY_1132_DATA 0x00000000
+#define DDRSS1_PHY_1133_DATA 0x00000000
+#define DDRSS1_PHY_1134_DATA 0x00000000
+#define DDRSS1_PHY_1135_DATA 0x00000000
+#define DDRSS1_PHY_1136_DATA 0x00000000
+#define DDRSS1_PHY_1137_DATA 0x00000000
+#define DDRSS1_PHY_1138_DATA 0x00000000
+#define DDRSS1_PHY_1139_DATA 0x00000000
+#define DDRSS1_PHY_1140_DATA 0x00000000
+#define DDRSS1_PHY_1141_DATA 0x00000000
+#define DDRSS1_PHY_1142_DATA 0x00000000
+#define DDRSS1_PHY_1143_DATA 0x00000000
+#define DDRSS1_PHY_1144_DATA 0x00000000
+#define DDRSS1_PHY_1145_DATA 0x00000000
+#define DDRSS1_PHY_1146_DATA 0x00000000
+#define DDRSS1_PHY_1147_DATA 0x00000000
+#define DDRSS1_PHY_1148_DATA 0x00000000
+#define DDRSS1_PHY_1149_DATA 0x00000000
+#define DDRSS1_PHY_1150_DATA 0x00000000
+#define DDRSS1_PHY_1151_DATA 0x00000000
+#define DDRSS1_PHY_1152_DATA 0x00000000
+#define DDRSS1_PHY_1153_DATA 0x00000000
+#define DDRSS1_PHY_1154_DATA 0x00000000
+#define DDRSS1_PHY_1155_DATA 0x00000000
+#define DDRSS1_PHY_1156_DATA 0x00000000
+#define DDRSS1_PHY_1157_DATA 0x00000000
+#define DDRSS1_PHY_1158_DATA 0x00000000
+#define DDRSS1_PHY_1159_DATA 0x00000000
+#define DDRSS1_PHY_1160_DATA 0x00000000
+#define DDRSS1_PHY_1161_DATA 0x00000000
+#define DDRSS1_PHY_1162_DATA 0x00000000
+#define DDRSS1_PHY_1163_DATA 0x00000000
+#define DDRSS1_PHY_1164_DATA 0x00000000
+#define DDRSS1_PHY_1165_DATA 0x00000000
+#define DDRSS1_PHY_1166_DATA 0x00000000
+#define DDRSS1_PHY_1167_DATA 0x00000000
+#define DDRSS1_PHY_1168_DATA 0x00000000
+#define DDRSS1_PHY_1169_DATA 0x00000000
+#define DDRSS1_PHY_1170_DATA 0x00000000
+#define DDRSS1_PHY_1171_DATA 0x00000000
+#define DDRSS1_PHY_1172_DATA 0x00000000
+#define DDRSS1_PHY_1173_DATA 0x00000000
+#define DDRSS1_PHY_1174_DATA 0x00000000
+#define DDRSS1_PHY_1175_DATA 0x00000000
+#define DDRSS1_PHY_1176_DATA 0x00000000
+#define DDRSS1_PHY_1177_DATA 0x00000000
+#define DDRSS1_PHY_1178_DATA 0x00000000
+#define DDRSS1_PHY_1179_DATA 0x00000000
+#define DDRSS1_PHY_1180_DATA 0x00000000
+#define DDRSS1_PHY_1181_DATA 0x00000000
+#define DDRSS1_PHY_1182_DATA 0x00000000
+#define DDRSS1_PHY_1183_DATA 0x00000000
+#define DDRSS1_PHY_1184_DATA 0x00000000
+#define DDRSS1_PHY_1185_DATA 0x00000000
+#define DDRSS1_PHY_1186_DATA 0x00000000
+#define DDRSS1_PHY_1187_DATA 0x00000000
+#define DDRSS1_PHY_1188_DATA 0x00000000
+#define DDRSS1_PHY_1189_DATA 0x00000000
+#define DDRSS1_PHY_1190_DATA 0x00000000
+#define DDRSS1_PHY_1191_DATA 0x00000000
+#define DDRSS1_PHY_1192_DATA 0x00000000
+#define DDRSS1_PHY_1193_DATA 0x00000000
+#define DDRSS1_PHY_1194_DATA 0x00000000
+#define DDRSS1_PHY_1195_DATA 0x00000000
+#define DDRSS1_PHY_1196_DATA 0x00000000
+#define DDRSS1_PHY_1197_DATA 0x00000000
+#define DDRSS1_PHY_1198_DATA 0x00000000
+#define DDRSS1_PHY_1199_DATA 0x00000000
+#define DDRSS1_PHY_1200_DATA 0x00000000
+#define DDRSS1_PHY_1201_DATA 0x00000000
+#define DDRSS1_PHY_1202_DATA 0x00000000
+#define DDRSS1_PHY_1203_DATA 0x00000000
+#define DDRSS1_PHY_1204_DATA 0x00000000
+#define DDRSS1_PHY_1205_DATA 0x00000000
+#define DDRSS1_PHY_1206_DATA 0x00000000
+#define DDRSS1_PHY_1207_DATA 0x00000000
+#define DDRSS1_PHY_1208_DATA 0x00000000
+#define DDRSS1_PHY_1209_DATA 0x00000000
+#define DDRSS1_PHY_1210_DATA 0x00000000
+#define DDRSS1_PHY_1211_DATA 0x00000000
+#define DDRSS1_PHY_1212_DATA 0x00000000
+#define DDRSS1_PHY_1213_DATA 0x00000000
+#define DDRSS1_PHY_1214_DATA 0x00000000
+#define DDRSS1_PHY_1215_DATA 0x00000000
+#define DDRSS1_PHY_1216_DATA 0x00000000
+#define DDRSS1_PHY_1217_DATA 0x00000000
+#define DDRSS1_PHY_1218_DATA 0x00000000
+#define DDRSS1_PHY_1219_DATA 0x00000000
+#define DDRSS1_PHY_1220_DATA 0x00000000
+#define DDRSS1_PHY_1221_DATA 0x00000000
+#define DDRSS1_PHY_1222_DATA 0x00000000
+#define DDRSS1_PHY_1223_DATA 0x00000000
+#define DDRSS1_PHY_1224_DATA 0x00000000
+#define DDRSS1_PHY_1225_DATA 0x00000000
+#define DDRSS1_PHY_1226_DATA 0x00000000
+#define DDRSS1_PHY_1227_DATA 0x00000000
+#define DDRSS1_PHY_1228_DATA 0x00000000
+#define DDRSS1_PHY_1229_DATA 0x00000000
+#define DDRSS1_PHY_1230_DATA 0x00000000
+#define DDRSS1_PHY_1231_DATA 0x00000000
+#define DDRSS1_PHY_1232_DATA 0x00000000
+#define DDRSS1_PHY_1233_DATA 0x00000000
+#define DDRSS1_PHY_1234_DATA 0x00000000
+#define DDRSS1_PHY_1235_DATA 0x00000000
+#define DDRSS1_PHY_1236_DATA 0x00000000
+#define DDRSS1_PHY_1237_DATA 0x00000000
+#define DDRSS1_PHY_1238_DATA 0x00000000
+#define DDRSS1_PHY_1239_DATA 0x00000000
+#define DDRSS1_PHY_1240_DATA 0x00000000
+#define DDRSS1_PHY_1241_DATA 0x00000000
+#define DDRSS1_PHY_1242_DATA 0x00000000
+#define DDRSS1_PHY_1243_DATA 0x00000000
+#define DDRSS1_PHY_1244_DATA 0x00000000
+#define DDRSS1_PHY_1245_DATA 0x00000000
+#define DDRSS1_PHY_1246_DATA 0x00000000
+#define DDRSS1_PHY_1247_DATA 0x00000000
+#define DDRSS1_PHY_1248_DATA 0x00000000
+#define DDRSS1_PHY_1249_DATA 0x00000000
+#define DDRSS1_PHY_1250_DATA 0x00000000
+#define DDRSS1_PHY_1251_DATA 0x00000000
+#define DDRSS1_PHY_1252_DATA 0x00000000
+#define DDRSS1_PHY_1253_DATA 0x00000000
+#define DDRSS1_PHY_1254_DATA 0x00000000
+#define DDRSS1_PHY_1255_DATA 0x00000000
+#define DDRSS1_PHY_1256_DATA 0x00000000
+#define DDRSS1_PHY_1257_DATA 0x00000000
+#define DDRSS1_PHY_1258_DATA 0x00000000
+#define DDRSS1_PHY_1259_DATA 0x00000000
+#define DDRSS1_PHY_1260_DATA 0x00000000
+#define DDRSS1_PHY_1261_DATA 0x00000000
+#define DDRSS1_PHY_1262_DATA 0x00000000
+#define DDRSS1_PHY_1263_DATA 0x00000000
+#define DDRSS1_PHY_1264_DATA 0x00000000
+#define DDRSS1_PHY_1265_DATA 0x00000000
+#define DDRSS1_PHY_1266_DATA 0x00000000
+#define DDRSS1_PHY_1267_DATA 0x00000000
+#define DDRSS1_PHY_1268_DATA 0x00000000
+#define DDRSS1_PHY_1269_DATA 0x00000000
+#define DDRSS1_PHY_1270_DATA 0x00000000
+#define DDRSS1_PHY_1271_DATA 0x00000000
+#define DDRSS1_PHY_1272_DATA 0x00000000
+#define DDRSS1_PHY_1273_DATA 0x00000000
+#define DDRSS1_PHY_1274_DATA 0x00000000
+#define DDRSS1_PHY_1275_DATA 0x00000000
+#define DDRSS1_PHY_1276_DATA 0x00000000
+#define DDRSS1_PHY_1277_DATA 0x00000000
+#define DDRSS1_PHY_1278_DATA 0x00000000
+#define DDRSS1_PHY_1279_DATA 0x00000000
+#define DDRSS1_PHY_1280_DATA 0x00000000
+#define DDRSS1_PHY_1281_DATA 0x00010100
+#define DDRSS1_PHY_1282_DATA 0x00000000
+#define DDRSS1_PHY_1283_DATA 0x00000000
+#define DDRSS1_PHY_1284_DATA 0x00050000
+#define DDRSS1_PHY_1285_DATA 0x04000000
+#define DDRSS1_PHY_1286_DATA 0x00000055
+#define DDRSS1_PHY_1287_DATA 0x00000000
+#define DDRSS1_PHY_1288_DATA 0x00000000
+#define DDRSS1_PHY_1289_DATA 0x00000000
+#define DDRSS1_PHY_1290_DATA 0x00000000
+#define DDRSS1_PHY_1291_DATA 0x00002001
+#define DDRSS1_PHY_1292_DATA 0x0000400F
+#define DDRSS1_PHY_1293_DATA 0x50020028
+#define DDRSS1_PHY_1294_DATA 0x01010000
+#define DDRSS1_PHY_1295_DATA 0x80080001
+#define DDRSS1_PHY_1296_DATA 0x10200000
+#define DDRSS1_PHY_1297_DATA 0x00000008
+#define DDRSS1_PHY_1298_DATA 0x00000000
+#define DDRSS1_PHY_1299_DATA 0x01090E00
+#define DDRSS1_PHY_1300_DATA 0x00040101
+#define DDRSS1_PHY_1301_DATA 0x0000010F
+#define DDRSS1_PHY_1302_DATA 0x00000000
+#define DDRSS1_PHY_1303_DATA 0x0000FFFF
+#define DDRSS1_PHY_1304_DATA 0x00000000
+#define DDRSS1_PHY_1305_DATA 0x01010000
+#define DDRSS1_PHY_1306_DATA 0x01080402
+#define DDRSS1_PHY_1307_DATA 0x01200F02
+#define DDRSS1_PHY_1308_DATA 0x00194280
+#define DDRSS1_PHY_1309_DATA 0x00000004
+#define DDRSS1_PHY_1310_DATA 0x00042000
+#define DDRSS1_PHY_1311_DATA 0x00000000
+#define DDRSS1_PHY_1312_DATA 0x00000000
+#define DDRSS1_PHY_1313_DATA 0x00000000
+#define DDRSS1_PHY_1314_DATA 0x00000000
+#define DDRSS1_PHY_1315_DATA 0x00000000
+#define DDRSS1_PHY_1316_DATA 0x00000000
+#define DDRSS1_PHY_1317_DATA 0x01000000
+#define DDRSS1_PHY_1318_DATA 0x00000705
+#define DDRSS1_PHY_1319_DATA 0x00000054
+#define DDRSS1_PHY_1320_DATA 0x00030820
+#define DDRSS1_PHY_1321_DATA 0x00010820
+#define DDRSS1_PHY_1322_DATA 0x00010820
+#define DDRSS1_PHY_1323_DATA 0x00010820
+#define DDRSS1_PHY_1324_DATA 0x00010820
+#define DDRSS1_PHY_1325_DATA 0x00010820
+#define DDRSS1_PHY_1326_DATA 0x00010820
+#define DDRSS1_PHY_1327_DATA 0x00010820
+#define DDRSS1_PHY_1328_DATA 0x00010820
+#define DDRSS1_PHY_1329_DATA 0x00000000
+#define DDRSS1_PHY_1330_DATA 0x00000074
+#define DDRSS1_PHY_1331_DATA 0x00000400
+#define DDRSS1_PHY_1332_DATA 0x00000108
+#define DDRSS1_PHY_1333_DATA 0x00000000
+#define DDRSS1_PHY_1334_DATA 0x00000000
+#define DDRSS1_PHY_1335_DATA 0x00000000
+#define DDRSS1_PHY_1336_DATA 0x00000000
+#define DDRSS1_PHY_1337_DATA 0x00000000
+#define DDRSS1_PHY_1338_DATA 0x03000000
+#define DDRSS1_PHY_1339_DATA 0x00000000
+#define DDRSS1_PHY_1340_DATA 0x00000000
+#define DDRSS1_PHY_1341_DATA 0x00000000
+#define DDRSS1_PHY_1342_DATA 0x04102006
+#define DDRSS1_PHY_1343_DATA 0x00041020
+#define DDRSS1_PHY_1344_DATA 0x01C98C98
+#define DDRSS1_PHY_1345_DATA 0x3F400000
+#define DDRSS1_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS1_PHY_1347_DATA 0x0000001F
+#define DDRSS1_PHY_1348_DATA 0x00000000
+#define DDRSS1_PHY_1349_DATA 0x00000000
+#define DDRSS1_PHY_1350_DATA 0x00000000
+#define DDRSS1_PHY_1351_DATA 0x00010000
+#define DDRSS1_PHY_1352_DATA 0x00000000
+#define DDRSS1_PHY_1353_DATA 0x00000000
+#define DDRSS1_PHY_1354_DATA 0x00000000
+#define DDRSS1_PHY_1355_DATA 0x00000000
+#define DDRSS1_PHY_1356_DATA 0x76543210
+#define DDRSS1_PHY_1357_DATA 0x00010198
+#define DDRSS1_PHY_1358_DATA 0x00000000
+#define DDRSS1_PHY_1359_DATA 0x00000000
+#define DDRSS1_PHY_1360_DATA 0x00000000
+#define DDRSS1_PHY_1361_DATA 0x00040700
+#define DDRSS1_PHY_1362_DATA 0x00000000
+#define DDRSS1_PHY_1363_DATA 0x00000000
+#define DDRSS1_PHY_1364_DATA 0x00000000
+#define DDRSS1_PHY_1365_DATA 0x00000000
+#define DDRSS1_PHY_1366_DATA 0x00000000
+#define DDRSS1_PHY_1367_DATA 0x00000002
+#define DDRSS1_PHY_1368_DATA 0x00000000
+#define DDRSS1_PHY_1369_DATA 0x00000000
+#define DDRSS1_PHY_1370_DATA 0x00000000
+#define DDRSS1_PHY_1371_DATA 0x00000000
+#define DDRSS1_PHY_1372_DATA 0x00000000
+#define DDRSS1_PHY_1373_DATA 0x00000000
+#define DDRSS1_PHY_1374_DATA 0x00080000
+#define DDRSS1_PHY_1375_DATA 0x000007FF
+#define DDRSS1_PHY_1376_DATA 0x00000000
+#define DDRSS1_PHY_1377_DATA 0x00000000
+#define DDRSS1_PHY_1378_DATA 0x00000000
+#define DDRSS1_PHY_1379_DATA 0x00000000
+#define DDRSS1_PHY_1380_DATA 0x00000000
+#define DDRSS1_PHY_1381_DATA 0x00000000
+#define DDRSS1_PHY_1382_DATA 0x000FFFFF
+#define DDRSS1_PHY_1383_DATA 0x000FFFFF
+#define DDRSS1_PHY_1384_DATA 0x0000FFFF
+#define DDRSS1_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS1_PHY_1386_DATA 0x030FFFFF
+#define DDRSS1_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS1_PHY_1388_DATA 0x0000FFFF
+#define DDRSS1_PHY_1389_DATA 0x00000000
+#define DDRSS1_PHY_1390_DATA 0x00000000
+#define DDRSS1_PHY_1391_DATA 0x00000000
+#define DDRSS1_PHY_1392_DATA 0x00000000
+#define DDRSS1_PHY_1393_DATA 0x0001F7C0
+#define DDRSS1_PHY_1394_DATA 0x00000003
+#define DDRSS1_PHY_1395_DATA 0x00000000
+#define DDRSS1_PHY_1396_DATA 0x00001142
+#define DDRSS1_PHY_1397_DATA 0x010207AB
+#define DDRSS1_PHY_1398_DATA 0x01000080
+#define DDRSS1_PHY_1399_DATA 0x03900390
+#define DDRSS1_PHY_1400_DATA 0x03900390
+#define DDRSS1_PHY_1401_DATA 0x00000390
+#define DDRSS1_PHY_1402_DATA 0x00000390
+#define DDRSS1_PHY_1403_DATA 0x00000390
+#define DDRSS1_PHY_1404_DATA 0x00000390
+#define DDRSS1_PHY_1405_DATA 0x00000005
+#define DDRSS1_PHY_1406_DATA 0x01813FCC
+#define DDRSS1_PHY_1407_DATA 0x000000CC
+#define DDRSS1_PHY_1408_DATA 0x0C000DFF
+#define DDRSS1_PHY_1409_DATA 0x30000DFF
+#define DDRSS1_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1411_DATA 0x000100F0
+#define DDRSS1_PHY_1412_DATA 0x780DFFCC
+#define DDRSS1_PHY_1413_DATA 0x00007E31
+#define DDRSS1_PHY_1414_DATA 0x000CBF11
+#define DDRSS1_PHY_1415_DATA 0x01990010
+#define DDRSS1_PHY_1416_DATA 0x000CBF11
+#define DDRSS1_PHY_1417_DATA 0x01990010
+#define DDRSS1_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1419_DATA 0x00EF00F0
+#define DDRSS1_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS1_PHY_1421_DATA 0x01FF00F0
+#define DDRSS1_PHY_1422_DATA 0x20040006
+
+#define DDRSS2_CTL_00_DATA 0x00000B00
+#define DDRSS2_CTL_01_DATA 0x00000000
+#define DDRSS2_CTL_02_DATA 0x00000000
+#define DDRSS2_CTL_03_DATA 0x00000000
+#define DDRSS2_CTL_04_DATA 0x00000000
+#define DDRSS2_CTL_05_DATA 0x00000000
+#define DDRSS2_CTL_06_DATA 0x00000000
+#define DDRSS2_CTL_07_DATA 0x00002AF8
+#define DDRSS2_CTL_08_DATA 0x0001ADAF
+#define DDRSS2_CTL_09_DATA 0x00000005
+#define DDRSS2_CTL_10_DATA 0x0000006E
+#define DDRSS2_CTL_11_DATA 0x000681C8
+#define DDRSS2_CTL_12_DATA 0x004111C9
+#define DDRSS2_CTL_13_DATA 0x00000005
+#define DDRSS2_CTL_14_DATA 0x000010A9
+#define DDRSS2_CTL_15_DATA 0x000681C8
+#define DDRSS2_CTL_16_DATA 0x004111C9
+#define DDRSS2_CTL_17_DATA 0x00000005
+#define DDRSS2_CTL_18_DATA 0x000010A9
+#define DDRSS2_CTL_19_DATA 0x01010000
+#define DDRSS2_CTL_20_DATA 0x02011001
+#define DDRSS2_CTL_21_DATA 0x02010000
+#define DDRSS2_CTL_22_DATA 0x00020100
+#define DDRSS2_CTL_23_DATA 0x0000000B
+#define DDRSS2_CTL_24_DATA 0x0000001C
+#define DDRSS2_CTL_25_DATA 0x00000000
+#define DDRSS2_CTL_26_DATA 0x00000000
+#define DDRSS2_CTL_27_DATA 0x03020200
+#define DDRSS2_CTL_28_DATA 0x00005656
+#define DDRSS2_CTL_29_DATA 0x00100000
+#define DDRSS2_CTL_30_DATA 0x00000000
+#define DDRSS2_CTL_31_DATA 0x00000000
+#define DDRSS2_CTL_32_DATA 0x00000000
+#define DDRSS2_CTL_33_DATA 0x00000000
+#define DDRSS2_CTL_34_DATA 0x040C0000
+#define DDRSS2_CTL_35_DATA 0x12481248
+#define DDRSS2_CTL_36_DATA 0x00050804
+#define DDRSS2_CTL_37_DATA 0x09040008
+#define DDRSS2_CTL_38_DATA 0x15000204
+#define DDRSS2_CTL_39_DATA 0x1760008B
+#define DDRSS2_CTL_40_DATA 0x1500422B
+#define DDRSS2_CTL_41_DATA 0x1760008B
+#define DDRSS2_CTL_42_DATA 0x2000422B
+#define DDRSS2_CTL_43_DATA 0x000A0A09
+#define DDRSS2_CTL_44_DATA 0x0400078A
+#define DDRSS2_CTL_45_DATA 0x1E161104
+#define DDRSS2_CTL_46_DATA 0x10012458
+#define DDRSS2_CTL_47_DATA 0x1E161110
+#define DDRSS2_CTL_48_DATA 0x10012458
+#define DDRSS2_CTL_49_DATA 0x02030410
+#define DDRSS2_CTL_50_DATA 0x2C040500
+#define DDRSS2_CTL_51_DATA 0x08292C29
+#define DDRSS2_CTL_52_DATA 0x14000E0A
+#define DDRSS2_CTL_53_DATA 0x04010A0A
+#define DDRSS2_CTL_54_DATA 0x01010004
+#define DDRSS2_CTL_55_DATA 0x04545408
+#define DDRSS2_CTL_56_DATA 0x04313104
+#define DDRSS2_CTL_57_DATA 0x00003131
+#define DDRSS2_CTL_58_DATA 0x00010100
+#define DDRSS2_CTL_59_DATA 0x03010000
+#define DDRSS2_CTL_60_DATA 0x00001508
+#define DDRSS2_CTL_61_DATA 0x000000CE
+#define DDRSS2_CTL_62_DATA 0x0000032B
+#define DDRSS2_CTL_63_DATA 0x00002073
+#define DDRSS2_CTL_64_DATA 0x0000032B
+#define DDRSS2_CTL_65_DATA 0x00002073
+#define DDRSS2_CTL_66_DATA 0x00000005
+#define DDRSS2_CTL_67_DATA 0x00050000
+#define DDRSS2_CTL_68_DATA 0x00CB0012
+#define DDRSS2_CTL_69_DATA 0x00CB0408
+#define DDRSS2_CTL_70_DATA 0x00400408
+#define DDRSS2_CTL_71_DATA 0x00120103
+#define DDRSS2_CTL_72_DATA 0x00100005
+#define DDRSS2_CTL_73_DATA 0x2F080010
+#define DDRSS2_CTL_74_DATA 0x0505012F
+#define DDRSS2_CTL_75_DATA 0x0401030A
+#define DDRSS2_CTL_76_DATA 0x041E100B
+#define DDRSS2_CTL_77_DATA 0x100B0401
+#define DDRSS2_CTL_78_DATA 0x0001041E
+#define DDRSS2_CTL_79_DATA 0x00160016
+#define DDRSS2_CTL_80_DATA 0x033B033B
+#define DDRSS2_CTL_81_DATA 0x033B033B
+#define DDRSS2_CTL_82_DATA 0x03050505
+#define DDRSS2_CTL_83_DATA 0x03010303
+#define DDRSS2_CTL_84_DATA 0x200B100B
+#define DDRSS2_CTL_85_DATA 0x04041004
+#define DDRSS2_CTL_86_DATA 0x200B100B
+#define DDRSS2_CTL_87_DATA 0x04041004
+#define DDRSS2_CTL_88_DATA 0x03010000
+#define DDRSS2_CTL_89_DATA 0x00010000
+#define DDRSS2_CTL_90_DATA 0x00000000
+#define DDRSS2_CTL_91_DATA 0x00000000
+#define DDRSS2_CTL_92_DATA 0x01000000
+#define DDRSS2_CTL_93_DATA 0x80104002
+#define DDRSS2_CTL_94_DATA 0x00000000
+#define DDRSS2_CTL_95_DATA 0x00040005
+#define DDRSS2_CTL_96_DATA 0x00000000
+#define DDRSS2_CTL_97_DATA 0x00050000
+#define DDRSS2_CTL_98_DATA 0x00000004
+#define DDRSS2_CTL_99_DATA 0x00000000
+#define DDRSS2_CTL_100_DATA 0x00040005
+#define DDRSS2_CTL_101_DATA 0x00000000
+#define DDRSS2_CTL_102_DATA 0x00003380
+#define DDRSS2_CTL_103_DATA 0x00003380
+#define DDRSS2_CTL_104_DATA 0x00003380
+#define DDRSS2_CTL_105_DATA 0x00003380
+#define DDRSS2_CTL_106_DATA 0x00003380
+#define DDRSS2_CTL_107_DATA 0x00000000
+#define DDRSS2_CTL_108_DATA 0x000005A2
+#define DDRSS2_CTL_109_DATA 0x00081CC0
+#define DDRSS2_CTL_110_DATA 0x00081CC0
+#define DDRSS2_CTL_111_DATA 0x00081CC0
+#define DDRSS2_CTL_112_DATA 0x00081CC0
+#define DDRSS2_CTL_113_DATA 0x00081CC0
+#define DDRSS2_CTL_114_DATA 0x00000000
+#define DDRSS2_CTL_115_DATA 0x0000E325
+#define DDRSS2_CTL_116_DATA 0x00081CC0
+#define DDRSS2_CTL_117_DATA 0x00081CC0
+#define DDRSS2_CTL_118_DATA 0x00081CC0
+#define DDRSS2_CTL_119_DATA 0x00081CC0
+#define DDRSS2_CTL_120_DATA 0x00081CC0
+#define DDRSS2_CTL_121_DATA 0x00000000
+#define DDRSS2_CTL_122_DATA 0x0000E325
+#define DDRSS2_CTL_123_DATA 0x00000000
+#define DDRSS2_CTL_124_DATA 0x00000000
+#define DDRSS2_CTL_125_DATA 0x00000000
+#define DDRSS2_CTL_126_DATA 0x00000000
+#define DDRSS2_CTL_127_DATA 0x00000000
+#define DDRSS2_CTL_128_DATA 0x00000000
+#define DDRSS2_CTL_129_DATA 0x00000000
+#define DDRSS2_CTL_130_DATA 0x00000000
+#define DDRSS2_CTL_131_DATA 0x0B030500
+#define DDRSS2_CTL_132_DATA 0x00040B04
+#define DDRSS2_CTL_133_DATA 0x0A090000
+#define DDRSS2_CTL_134_DATA 0x0A090701
+#define DDRSS2_CTL_135_DATA 0x0900000E
+#define DDRSS2_CTL_136_DATA 0x0907010A
+#define DDRSS2_CTL_137_DATA 0x00000E0A
+#define DDRSS2_CTL_138_DATA 0x07010A09
+#define DDRSS2_CTL_139_DATA 0x000E0A09
+#define DDRSS2_CTL_140_DATA 0x07000401
+#define DDRSS2_CTL_141_DATA 0x00000000
+#define DDRSS2_CTL_142_DATA 0x00000000
+#define DDRSS2_CTL_143_DATA 0x00000000
+#define DDRSS2_CTL_144_DATA 0x00000000
+#define DDRSS2_CTL_145_DATA 0x00000000
+#define DDRSS2_CTL_146_DATA 0x00000000
+#define DDRSS2_CTL_147_DATA 0x00000000
+#define DDRSS2_CTL_148_DATA 0x08080000
+#define DDRSS2_CTL_149_DATA 0x01000000
+#define DDRSS2_CTL_150_DATA 0x800000C0
+#define DDRSS2_CTL_151_DATA 0x800000C0
+#define DDRSS2_CTL_152_DATA 0x800000C0
+#define DDRSS2_CTL_153_DATA 0x00000000
+#define DDRSS2_CTL_154_DATA 0x00001500
+#define DDRSS2_CTL_155_DATA 0x00000000
+#define DDRSS2_CTL_156_DATA 0x00000001
+#define DDRSS2_CTL_157_DATA 0x00000002
+#define DDRSS2_CTL_158_DATA 0x0000100E
+#define DDRSS2_CTL_159_DATA 0x00000000
+#define DDRSS2_CTL_160_DATA 0x00000000
+#define DDRSS2_CTL_161_DATA 0x00000000
+#define DDRSS2_CTL_162_DATA 0x00000000
+#define DDRSS2_CTL_163_DATA 0x00000000
+#define DDRSS2_CTL_164_DATA 0x000B0000
+#define DDRSS2_CTL_165_DATA 0x000E0006
+#define DDRSS2_CTL_166_DATA 0x000E0404
+#define DDRSS2_CTL_167_DATA 0x00D601AB
+#define DDRSS2_CTL_168_DATA 0x10100216
+#define DDRSS2_CTL_169_DATA 0x01AB0216
+#define DDRSS2_CTL_170_DATA 0x021600D6
+#define DDRSS2_CTL_171_DATA 0x02161010
+#define DDRSS2_CTL_172_DATA 0x00000000
+#define DDRSS2_CTL_173_DATA 0x00000000
+#define DDRSS2_CTL_174_DATA 0x00000000
+#define DDRSS2_CTL_175_DATA 0x3FF40084
+#define DDRSS2_CTL_176_DATA 0x33003FF4
+#define DDRSS2_CTL_177_DATA 0x00003333
+#define DDRSS2_CTL_178_DATA 0x35000000
+#define DDRSS2_CTL_179_DATA 0x27270035
+#define DDRSS2_CTL_180_DATA 0x0F0F0000
+#define DDRSS2_CTL_181_DATA 0x16000000
+#define DDRSS2_CTL_182_DATA 0x00841616
+#define DDRSS2_CTL_183_DATA 0x3FF43FF4
+#define DDRSS2_CTL_184_DATA 0x33333300
+#define DDRSS2_CTL_185_DATA 0x00000000
+#define DDRSS2_CTL_186_DATA 0x00353500
+#define DDRSS2_CTL_187_DATA 0x00002727
+#define DDRSS2_CTL_188_DATA 0x00000F0F
+#define DDRSS2_CTL_189_DATA 0x16161600
+#define DDRSS2_CTL_190_DATA 0x00000020
+#define DDRSS2_CTL_191_DATA 0x00000000
+#define DDRSS2_CTL_192_DATA 0x00000001
+#define DDRSS2_CTL_193_DATA 0x00000000
+#define DDRSS2_CTL_194_DATA 0x01000000
+#define DDRSS2_CTL_195_DATA 0x00000001
+#define DDRSS2_CTL_196_DATA 0x00000000
+#define DDRSS2_CTL_197_DATA 0x00000000
+#define DDRSS2_CTL_198_DATA 0x00000000
+#define DDRSS2_CTL_199_DATA 0x00000000
+#define DDRSS2_CTL_200_DATA 0x00000000
+#define DDRSS2_CTL_201_DATA 0x00000000
+#define DDRSS2_CTL_202_DATA 0x00000000
+#define DDRSS2_CTL_203_DATA 0x00000000
+#define DDRSS2_CTL_204_DATA 0x00000000
+#define DDRSS2_CTL_205_DATA 0x00000000
+#define DDRSS2_CTL_206_DATA 0x02000000
+#define DDRSS2_CTL_207_DATA 0x01080101
+#define DDRSS2_CTL_208_DATA 0x00000000
+#define DDRSS2_CTL_209_DATA 0x00000000
+#define DDRSS2_CTL_210_DATA 0x00000000
+#define DDRSS2_CTL_211_DATA 0x00000000
+#define DDRSS2_CTL_212_DATA 0x00000000
+#define DDRSS2_CTL_213_DATA 0x00000000
+#define DDRSS2_CTL_214_DATA 0x00000000
+#define DDRSS2_CTL_215_DATA 0x00000000
+#define DDRSS2_CTL_216_DATA 0x00000000
+#define DDRSS2_CTL_217_DATA 0x00000000
+#define DDRSS2_CTL_218_DATA 0x00000000
+#define DDRSS2_CTL_219_DATA 0x00000000
+#define DDRSS2_CTL_220_DATA 0x00000000
+#define DDRSS2_CTL_221_DATA 0x00000000
+#define DDRSS2_CTL_222_DATA 0x00001000
+#define DDRSS2_CTL_223_DATA 0x006403E8
+#define DDRSS2_CTL_224_DATA 0x00000000
+#define DDRSS2_CTL_225_DATA 0x00000000
+#define DDRSS2_CTL_226_DATA 0x00000000
+#define DDRSS2_CTL_227_DATA 0x15110000
+#define DDRSS2_CTL_228_DATA 0x00040C18
+#define DDRSS2_CTL_229_DATA 0xF000C000
+#define DDRSS2_CTL_230_DATA 0x0000F000
+#define DDRSS2_CTL_231_DATA 0x00000000
+#define DDRSS2_CTL_232_DATA 0x00000000
+#define DDRSS2_CTL_233_DATA 0xC0000000
+#define DDRSS2_CTL_234_DATA 0xF000F000
+#define DDRSS2_CTL_235_DATA 0x00000000
+#define DDRSS2_CTL_236_DATA 0x00000000
+#define DDRSS2_CTL_237_DATA 0x00000000
+#define DDRSS2_CTL_238_DATA 0xF000C000
+#define DDRSS2_CTL_239_DATA 0x0000F000
+#define DDRSS2_CTL_240_DATA 0x00000000
+#define DDRSS2_CTL_241_DATA 0x00000000
+#define DDRSS2_CTL_242_DATA 0x00030000
+#define DDRSS2_CTL_243_DATA 0x00000000
+#define DDRSS2_CTL_244_DATA 0x00000000
+#define DDRSS2_CTL_245_DATA 0x00000000
+#define DDRSS2_CTL_246_DATA 0x00000000
+#define DDRSS2_CTL_247_DATA 0x00000000
+#define DDRSS2_CTL_248_DATA 0x00000000
+#define DDRSS2_CTL_249_DATA 0x00000000
+#define DDRSS2_CTL_250_DATA 0x00000000
+#define DDRSS2_CTL_251_DATA 0x00000000
+#define DDRSS2_CTL_252_DATA 0x00000000
+#define DDRSS2_CTL_253_DATA 0x00000000
+#define DDRSS2_CTL_254_DATA 0x00000000
+#define DDRSS2_CTL_255_DATA 0x00000000
+#define DDRSS2_CTL_256_DATA 0x00000000
+#define DDRSS2_CTL_257_DATA 0x01000200
+#define DDRSS2_CTL_258_DATA 0x00370040
+#define DDRSS2_CTL_259_DATA 0x00020008
+#define DDRSS2_CTL_260_DATA 0x00400100
+#define DDRSS2_CTL_261_DATA 0x00400855
+#define DDRSS2_CTL_262_DATA 0x01000200
+#define DDRSS2_CTL_263_DATA 0x08550040
+#define DDRSS2_CTL_264_DATA 0x00000040
+#define DDRSS2_CTL_265_DATA 0x006B0003
+#define DDRSS2_CTL_266_DATA 0x0100006B
+#define DDRSS2_CTL_267_DATA 0x03030303
+#define DDRSS2_CTL_268_DATA 0x00000000
+#define DDRSS2_CTL_269_DATA 0x00000202
+#define DDRSS2_CTL_270_DATA 0x00001FFF
+#define DDRSS2_CTL_271_DATA 0x3FFF2000
+#define DDRSS2_CTL_272_DATA 0x03FF0000
+#define DDRSS2_CTL_273_DATA 0x000103FF
+#define DDRSS2_CTL_274_DATA 0x0FFF0B00
+#define DDRSS2_CTL_275_DATA 0x01010001
+#define DDRSS2_CTL_276_DATA 0x01010101
+#define DDRSS2_CTL_277_DATA 0x01180101
+#define DDRSS2_CTL_278_DATA 0x00030000
+#define DDRSS2_CTL_279_DATA 0x00000000
+#define DDRSS2_CTL_280_DATA 0x00000000
+#define DDRSS2_CTL_281_DATA 0x00000000
+#define DDRSS2_CTL_282_DATA 0x00000000
+#define DDRSS2_CTL_283_DATA 0x00000000
+#define DDRSS2_CTL_284_DATA 0x00000000
+#define DDRSS2_CTL_285_DATA 0x00000000
+#define DDRSS2_CTL_286_DATA 0x00040101
+#define DDRSS2_CTL_287_DATA 0x04010100
+#define DDRSS2_CTL_288_DATA 0x00000000
+#define DDRSS2_CTL_289_DATA 0x00000000
+#define DDRSS2_CTL_290_DATA 0x03030300
+#define DDRSS2_CTL_291_DATA 0x00000001
+#define DDRSS2_CTL_292_DATA 0x00000000
+#define DDRSS2_CTL_293_DATA 0x00000000
+#define DDRSS2_CTL_294_DATA 0x00000000
+#define DDRSS2_CTL_295_DATA 0x00000000
+#define DDRSS2_CTL_296_DATA 0x00000000
+#define DDRSS2_CTL_297_DATA 0x00000000
+#define DDRSS2_CTL_298_DATA 0x00000000
+#define DDRSS2_CTL_299_DATA 0x00000000
+#define DDRSS2_CTL_300_DATA 0x00000000
+#define DDRSS2_CTL_301_DATA 0x00000000
+#define DDRSS2_CTL_302_DATA 0x00000000
+#define DDRSS2_CTL_303_DATA 0x00000000
+#define DDRSS2_CTL_304_DATA 0x00000000
+#define DDRSS2_CTL_305_DATA 0x00000000
+#define DDRSS2_CTL_306_DATA 0x00000000
+#define DDRSS2_CTL_307_DATA 0x00000000
+#define DDRSS2_CTL_308_DATA 0x00000000
+#define DDRSS2_CTL_309_DATA 0x00000000
+#define DDRSS2_CTL_310_DATA 0x00000000
+#define DDRSS2_CTL_311_DATA 0x00000000
+#define DDRSS2_CTL_312_DATA 0x00000000
+#define DDRSS2_CTL_313_DATA 0x01000000
+#define DDRSS2_CTL_314_DATA 0x00020201
+#define DDRSS2_CTL_315_DATA 0x01000101
+#define DDRSS2_CTL_316_DATA 0x01010001
+#define DDRSS2_CTL_317_DATA 0x00010101
+#define DDRSS2_CTL_318_DATA 0x050A0A03
+#define DDRSS2_CTL_319_DATA 0x10081F1F
+#define DDRSS2_CTL_320_DATA 0x00090310
+#define DDRSS2_CTL_321_DATA 0x0B0C030F
+#define DDRSS2_CTL_322_DATA 0x0B0C0306
+#define DDRSS2_CTL_323_DATA 0x0C090006
+#define DDRSS2_CTL_324_DATA 0x0100000C
+#define DDRSS2_CTL_325_DATA 0x08040801
+#define DDRSS2_CTL_326_DATA 0x00000004
+#define DDRSS2_CTL_327_DATA 0x00000000
+#define DDRSS2_CTL_328_DATA 0x00010000
+#define DDRSS2_CTL_329_DATA 0x00280D00
+#define DDRSS2_CTL_330_DATA 0x00000001
+#define DDRSS2_CTL_331_DATA 0x00030001
+#define DDRSS2_CTL_332_DATA 0x00000000
+#define DDRSS2_CTL_333_DATA 0x00000000
+#define DDRSS2_CTL_334_DATA 0x00000000
+#define DDRSS2_CTL_335_DATA 0x00000000
+#define DDRSS2_CTL_336_DATA 0x00000000
+#define DDRSS2_CTL_337_DATA 0x00000000
+#define DDRSS2_CTL_338_DATA 0x00000000
+#define DDRSS2_CTL_339_DATA 0x00000000
+#define DDRSS2_CTL_340_DATA 0x01000000
+#define DDRSS2_CTL_341_DATA 0x00000001
+#define DDRSS2_CTL_342_DATA 0x00010100
+#define DDRSS2_CTL_343_DATA 0x03030000
+#define DDRSS2_CTL_344_DATA 0x00000000
+#define DDRSS2_CTL_345_DATA 0x00000000
+#define DDRSS2_CTL_346_DATA 0x00000000
+#define DDRSS2_CTL_347_DATA 0x00000000
+#define DDRSS2_CTL_348_DATA 0x00000000
+#define DDRSS2_CTL_349_DATA 0x00000000
+#define DDRSS2_CTL_350_DATA 0x00000000
+#define DDRSS2_CTL_351_DATA 0x00000000
+#define DDRSS2_CTL_352_DATA 0x00000000
+#define DDRSS2_CTL_353_DATA 0x00000000
+#define DDRSS2_CTL_354_DATA 0x00000000
+#define DDRSS2_CTL_355_DATA 0x00000000
+#define DDRSS2_CTL_356_DATA 0x00000000
+#define DDRSS2_CTL_357_DATA 0x00000000
+#define DDRSS2_CTL_358_DATA 0x00000000
+#define DDRSS2_CTL_359_DATA 0x00000000
+#define DDRSS2_CTL_360_DATA 0x000556AA
+#define DDRSS2_CTL_361_DATA 0x000AAAAA
+#define DDRSS2_CTL_362_DATA 0x000AA955
+#define DDRSS2_CTL_363_DATA 0x00055555
+#define DDRSS2_CTL_364_DATA 0x000B3133
+#define DDRSS2_CTL_365_DATA 0x0004CD33
+#define DDRSS2_CTL_366_DATA 0x0004CECC
+#define DDRSS2_CTL_367_DATA 0x000B32CC
+#define DDRSS2_CTL_368_DATA 0x00010300
+#define DDRSS2_CTL_369_DATA 0x03000100
+#define DDRSS2_CTL_370_DATA 0x00000000
+#define DDRSS2_CTL_371_DATA 0x00000000
+#define DDRSS2_CTL_372_DATA 0x00000000
+#define DDRSS2_CTL_373_DATA 0x00000000
+#define DDRSS2_CTL_374_DATA 0x00000000
+#define DDRSS2_CTL_375_DATA 0x00000000
+#define DDRSS2_CTL_376_DATA 0x00000000
+#define DDRSS2_CTL_377_DATA 0x00010000
+#define DDRSS2_CTL_378_DATA 0x00000404
+#define DDRSS2_CTL_379_DATA 0x00000000
+#define DDRSS2_CTL_380_DATA 0x00000000
+#define DDRSS2_CTL_381_DATA 0x00000000
+#define DDRSS2_CTL_382_DATA 0x00000000
+#define DDRSS2_CTL_383_DATA 0x00000000
+#define DDRSS2_CTL_384_DATA 0x00000000
+#define DDRSS2_CTL_385_DATA 0x00000000
+#define DDRSS2_CTL_386_DATA 0x00000000
+#define DDRSS2_CTL_387_DATA 0x3A3A1B00
+#define DDRSS2_CTL_388_DATA 0x000A0000
+#define DDRSS2_CTL_389_DATA 0x0000019C
+#define DDRSS2_CTL_390_DATA 0x00000200
+#define DDRSS2_CTL_391_DATA 0x00000200
+#define DDRSS2_CTL_392_DATA 0x00000200
+#define DDRSS2_CTL_393_DATA 0x00000200
+#define DDRSS2_CTL_394_DATA 0x000004D4
+#define DDRSS2_CTL_395_DATA 0x00001018
+#define DDRSS2_CTL_396_DATA 0x00000204
+#define DDRSS2_CTL_397_DATA 0x000040E6
+#define DDRSS2_CTL_398_DATA 0x00000200
+#define DDRSS2_CTL_399_DATA 0x00000200
+#define DDRSS2_CTL_400_DATA 0x00000200
+#define DDRSS2_CTL_401_DATA 0x00000200
+#define DDRSS2_CTL_402_DATA 0x0000C2B2
+#define DDRSS2_CTL_403_DATA 0x000288FC
+#define DDRSS2_CTL_404_DATA 0x00000E15
+#define DDRSS2_CTL_405_DATA 0x000040E6
+#define DDRSS2_CTL_406_DATA 0x00000200
+#define DDRSS2_CTL_407_DATA 0x00000200
+#define DDRSS2_CTL_408_DATA 0x00000200
+#define DDRSS2_CTL_409_DATA 0x00000200
+#define DDRSS2_CTL_410_DATA 0x0000C2B2
+#define DDRSS2_CTL_411_DATA 0x000288FC
+#define DDRSS2_CTL_412_DATA 0x02020E15
+#define DDRSS2_CTL_413_DATA 0x03030202
+#define DDRSS2_CTL_414_DATA 0x00000022
+#define DDRSS2_CTL_415_DATA 0x00000000
+#define DDRSS2_CTL_416_DATA 0x00000000
+#define DDRSS2_CTL_417_DATA 0x00001403
+#define DDRSS2_CTL_418_DATA 0x000007D0
+#define DDRSS2_CTL_419_DATA 0x00000000
+#define DDRSS2_CTL_420_DATA 0x00000000
+#define DDRSS2_CTL_421_DATA 0x00030000
+#define DDRSS2_CTL_422_DATA 0x0007001F
+#define DDRSS2_CTL_423_DATA 0x001B0033
+#define DDRSS2_CTL_424_DATA 0x001B0033
+#define DDRSS2_CTL_425_DATA 0x00000000
+#define DDRSS2_CTL_426_DATA 0x00000000
+#define DDRSS2_CTL_427_DATA 0x02000000
+#define DDRSS2_CTL_428_DATA 0x01000404
+#define DDRSS2_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS2_CTL_430_DATA 0x00000105
+#define DDRSS2_CTL_431_DATA 0x00010101
+#define DDRSS2_CTL_432_DATA 0x00010101
+#define DDRSS2_CTL_433_DATA 0x00010001
+#define DDRSS2_CTL_434_DATA 0x00000101
+#define DDRSS2_CTL_435_DATA 0x02000201
+#define DDRSS2_CTL_436_DATA 0x02010000
+#define DDRSS2_CTL_437_DATA 0x00000200
+#define DDRSS2_CTL_438_DATA 0x28060000
+#define DDRSS2_CTL_439_DATA 0x00000128
+#define DDRSS2_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS2_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS2_CTL_442_DATA 0x00000000
+#define DDRSS2_CTL_443_DATA 0x00000000
+#define DDRSS2_CTL_444_DATA 0x00000000
+#define DDRSS2_CTL_445_DATA 0x00000000
+#define DDRSS2_CTL_446_DATA 0x00000000
+#define DDRSS2_CTL_447_DATA 0x00000000
+#define DDRSS2_CTL_448_DATA 0x00000000
+#define DDRSS2_CTL_449_DATA 0x00000000
+#define DDRSS2_CTL_450_DATA 0x00000000
+#define DDRSS2_CTL_451_DATA 0x00000000
+#define DDRSS2_CTL_452_DATA 0x00000000
+#define DDRSS2_CTL_453_DATA 0x00000000
+#define DDRSS2_CTL_454_DATA 0x00000000
+#define DDRSS2_CTL_455_DATA 0x00000000
+#define DDRSS2_CTL_456_DATA 0x00000000
+#define DDRSS2_CTL_457_DATA 0x00000000
+#define DDRSS2_CTL_458_DATA 0x00000000
+
+#define DDRSS2_PI_00_DATA 0x00000B00
+#define DDRSS2_PI_01_DATA 0x00000000
+#define DDRSS2_PI_02_DATA 0x00000000
+#define DDRSS2_PI_03_DATA 0x00000000
+#define DDRSS2_PI_04_DATA 0x00000000
+#define DDRSS2_PI_05_DATA 0x00000101
+#define DDRSS2_PI_06_DATA 0x00640000
+#define DDRSS2_PI_07_DATA 0x00000001
+#define DDRSS2_PI_08_DATA 0x00000000
+#define DDRSS2_PI_09_DATA 0x00000000
+#define DDRSS2_PI_10_DATA 0x00000000
+#define DDRSS2_PI_11_DATA 0x00000000
+#define DDRSS2_PI_12_DATA 0x00000007
+#define DDRSS2_PI_13_DATA 0x00010002
+#define DDRSS2_PI_14_DATA 0x0800000F
+#define DDRSS2_PI_15_DATA 0x00000103
+#define DDRSS2_PI_16_DATA 0x00000005
+#define DDRSS2_PI_17_DATA 0x00000000
+#define DDRSS2_PI_18_DATA 0x00000000
+#define DDRSS2_PI_19_DATA 0x00000000
+#define DDRSS2_PI_20_DATA 0x00000000
+#define DDRSS2_PI_21_DATA 0x00000000
+#define DDRSS2_PI_22_DATA 0x00000000
+#define DDRSS2_PI_23_DATA 0x00000000
+#define DDRSS2_PI_24_DATA 0x00000000
+#define DDRSS2_PI_25_DATA 0x00000000
+#define DDRSS2_PI_26_DATA 0x00010100
+#define DDRSS2_PI_27_DATA 0x00280A00
+#define DDRSS2_PI_28_DATA 0x00000000
+#define DDRSS2_PI_29_DATA 0x0F000000
+#define DDRSS2_PI_30_DATA 0x00003200
+#define DDRSS2_PI_31_DATA 0x00000000
+#define DDRSS2_PI_32_DATA 0x00000000
+#define DDRSS2_PI_33_DATA 0x01010102
+#define DDRSS2_PI_34_DATA 0x00000000
+#define DDRSS2_PI_35_DATA 0x000000AA
+#define DDRSS2_PI_36_DATA 0x00000055
+#define DDRSS2_PI_37_DATA 0x000000B5
+#define DDRSS2_PI_38_DATA 0x0000004A
+#define DDRSS2_PI_39_DATA 0x00000056
+#define DDRSS2_PI_40_DATA 0x000000A9
+#define DDRSS2_PI_41_DATA 0x000000A9
+#define DDRSS2_PI_42_DATA 0x000000B5
+#define DDRSS2_PI_43_DATA 0x00000000
+#define DDRSS2_PI_44_DATA 0x00000000
+#define DDRSS2_PI_45_DATA 0x000F0F00
+#define DDRSS2_PI_46_DATA 0x0000001B
+#define DDRSS2_PI_47_DATA 0x000007D0
+#define DDRSS2_PI_48_DATA 0x00000300
+#define DDRSS2_PI_49_DATA 0x00000000
+#define DDRSS2_PI_50_DATA 0x00000000
+#define DDRSS2_PI_51_DATA 0x01000000
+#define DDRSS2_PI_52_DATA 0x00010101
+#define DDRSS2_PI_53_DATA 0x00000000
+#define DDRSS2_PI_54_DATA 0x00030000
+#define DDRSS2_PI_55_DATA 0x0F000000
+#define DDRSS2_PI_56_DATA 0x00000017
+#define DDRSS2_PI_57_DATA 0x00000000
+#define DDRSS2_PI_58_DATA 0x00000000
+#define DDRSS2_PI_59_DATA 0x00000000
+#define DDRSS2_PI_60_DATA 0x0A0A140A
+#define DDRSS2_PI_61_DATA 0x10020101
+#define DDRSS2_PI_62_DATA 0x00020805
+#define DDRSS2_PI_63_DATA 0x01000404
+#define DDRSS2_PI_64_DATA 0x00000000
+#define DDRSS2_PI_65_DATA 0x00000000
+#define DDRSS2_PI_66_DATA 0x00000100
+#define DDRSS2_PI_67_DATA 0x0001010F
+#define DDRSS2_PI_68_DATA 0x00340000
+#define DDRSS2_PI_69_DATA 0x00000000
+#define DDRSS2_PI_70_DATA 0x00000000
+#define DDRSS2_PI_71_DATA 0x0000FFFF
+#define DDRSS2_PI_72_DATA 0x00000000
+#define DDRSS2_PI_73_DATA 0x00080000
+#define DDRSS2_PI_74_DATA 0x02000200
+#define DDRSS2_PI_75_DATA 0x01000100
+#define DDRSS2_PI_76_DATA 0x01000000
+#define DDRSS2_PI_77_DATA 0x02000200
+#define DDRSS2_PI_78_DATA 0x00000200
+#define DDRSS2_PI_79_DATA 0x00000000
+#define DDRSS2_PI_80_DATA 0x00000000
+#define DDRSS2_PI_81_DATA 0x00000000
+#define DDRSS2_PI_82_DATA 0x00000000
+#define DDRSS2_PI_83_DATA 0x00000000
+#define DDRSS2_PI_84_DATA 0x00000000
+#define DDRSS2_PI_85_DATA 0x00000000
+#define DDRSS2_PI_86_DATA 0x00000000
+#define DDRSS2_PI_87_DATA 0x00000000
+#define DDRSS2_PI_88_DATA 0x00000000
+#define DDRSS2_PI_89_DATA 0x00000000
+#define DDRSS2_PI_90_DATA 0x00000000
+#define DDRSS2_PI_91_DATA 0x00000400
+#define DDRSS2_PI_92_DATA 0x02010000
+#define DDRSS2_PI_93_DATA 0x00080003
+#define DDRSS2_PI_94_DATA 0x00080000
+#define DDRSS2_PI_95_DATA 0x00000001
+#define DDRSS2_PI_96_DATA 0x00000000
+#define DDRSS2_PI_97_DATA 0x0000AA00
+#define DDRSS2_PI_98_DATA 0x00000000
+#define DDRSS2_PI_99_DATA 0x00000000
+#define DDRSS2_PI_100_DATA 0x00010000
+#define DDRSS2_PI_101_DATA 0x00000000
+#define DDRSS2_PI_102_DATA 0x00000000
+#define DDRSS2_PI_103_DATA 0x00000000
+#define DDRSS2_PI_104_DATA 0x00000000
+#define DDRSS2_PI_105_DATA 0x00000000
+#define DDRSS2_PI_106_DATA 0x00000000
+#define DDRSS2_PI_107_DATA 0x00000000
+#define DDRSS2_PI_108_DATA 0x00000000
+#define DDRSS2_PI_109_DATA 0x00000000
+#define DDRSS2_PI_110_DATA 0x00000000
+#define DDRSS2_PI_111_DATA 0x00000000
+#define DDRSS2_PI_112_DATA 0x00000000
+#define DDRSS2_PI_113_DATA 0x00000000
+#define DDRSS2_PI_114_DATA 0x00000000
+#define DDRSS2_PI_115_DATA 0x00000000
+#define DDRSS2_PI_116_DATA 0x00000000
+#define DDRSS2_PI_117_DATA 0x00000000
+#define DDRSS2_PI_118_DATA 0x00000000
+#define DDRSS2_PI_119_DATA 0x00000000
+#define DDRSS2_PI_120_DATA 0x00000000
+#define DDRSS2_PI_121_DATA 0x00000000
+#define DDRSS2_PI_122_DATA 0x00000000
+#define DDRSS2_PI_123_DATA 0x00000000
+#define DDRSS2_PI_124_DATA 0x00000000
+#define DDRSS2_PI_125_DATA 0x00000008
+#define DDRSS2_PI_126_DATA 0x00000000
+#define DDRSS2_PI_127_DATA 0x00000000
+#define DDRSS2_PI_128_DATA 0x00000000
+#define DDRSS2_PI_129_DATA 0x00000000
+#define DDRSS2_PI_130_DATA 0x00000000
+#define DDRSS2_PI_131_DATA 0x00000000
+#define DDRSS2_PI_132_DATA 0x00000000
+#define DDRSS2_PI_133_DATA 0x00000000
+#define DDRSS2_PI_134_DATA 0x00000002
+#define DDRSS2_PI_135_DATA 0x00000000
+#define DDRSS2_PI_136_DATA 0x00000000
+#define DDRSS2_PI_137_DATA 0x0000000A
+#define DDRSS2_PI_138_DATA 0x00000019
+#define DDRSS2_PI_139_DATA 0x00000100
+#define DDRSS2_PI_140_DATA 0x00000000
+#define DDRSS2_PI_141_DATA 0x00000000
+#define DDRSS2_PI_142_DATA 0x00000000
+#define DDRSS2_PI_143_DATA 0x00000000
+#define DDRSS2_PI_144_DATA 0x01000000
+#define DDRSS2_PI_145_DATA 0x00010003
+#define DDRSS2_PI_146_DATA 0x02000101
+#define DDRSS2_PI_147_DATA 0x01030001
+#define DDRSS2_PI_148_DATA 0x00010400
+#define DDRSS2_PI_149_DATA 0x06000105
+#define DDRSS2_PI_150_DATA 0x01070001
+#define DDRSS2_PI_151_DATA 0x00000000
+#define DDRSS2_PI_152_DATA 0x00000000
+#define DDRSS2_PI_153_DATA 0x00000000
+#define DDRSS2_PI_154_DATA 0x00010001
+#define DDRSS2_PI_155_DATA 0x00000000
+#define DDRSS2_PI_156_DATA 0x00000000
+#define DDRSS2_PI_157_DATA 0x00000000
+#define DDRSS2_PI_158_DATA 0x00000000
+#define DDRSS2_PI_159_DATA 0x00000401
+#define DDRSS2_PI_160_DATA 0x00000000
+#define DDRSS2_PI_161_DATA 0x00010000
+#define DDRSS2_PI_162_DATA 0x00000000
+#define DDRSS2_PI_163_DATA 0x2B2B0200
+#define DDRSS2_PI_164_DATA 0x00000034
+#define DDRSS2_PI_165_DATA 0x00000064
+#define DDRSS2_PI_166_DATA 0x00020064
+#define DDRSS2_PI_167_DATA 0x02000200
+#define DDRSS2_PI_168_DATA 0x48120C04
+#define DDRSS2_PI_169_DATA 0x00154812
+#define DDRSS2_PI_170_DATA 0x000000CE
+#define DDRSS2_PI_171_DATA 0x0000032B
+#define DDRSS2_PI_172_DATA 0x00002073
+#define DDRSS2_PI_173_DATA 0x0000032B
+#define DDRSS2_PI_174_DATA 0x04002073
+#define DDRSS2_PI_175_DATA 0x01010404
+#define DDRSS2_PI_176_DATA 0x00001501
+#define DDRSS2_PI_177_DATA 0x00150015
+#define DDRSS2_PI_178_DATA 0x01000100
+#define DDRSS2_PI_179_DATA 0x00000100
+#define DDRSS2_PI_180_DATA 0x00000000
+#define DDRSS2_PI_181_DATA 0x01010101
+#define DDRSS2_PI_182_DATA 0x00000101
+#define DDRSS2_PI_183_DATA 0x00000000
+#define DDRSS2_PI_184_DATA 0x00000000
+#define DDRSS2_PI_185_DATA 0x15040000
+#define DDRSS2_PI_186_DATA 0x0E0E0215
+#define DDRSS2_PI_187_DATA 0x00040402
+#define DDRSS2_PI_188_DATA 0x000D0035
+#define DDRSS2_PI_189_DATA 0x00218049
+#define DDRSS2_PI_190_DATA 0x00218049
+#define DDRSS2_PI_191_DATA 0x01010101
+#define DDRSS2_PI_192_DATA 0x0004000E
+#define DDRSS2_PI_193_DATA 0x00040216
+#define DDRSS2_PI_194_DATA 0x01000216
+#define DDRSS2_PI_195_DATA 0x000F000F
+#define DDRSS2_PI_196_DATA 0x02170100
+#define DDRSS2_PI_197_DATA 0x01000217
+#define DDRSS2_PI_198_DATA 0x02170217
+#define DDRSS2_PI_199_DATA 0x32103200
+#define DDRSS2_PI_200_DATA 0x01013210
+#define DDRSS2_PI_201_DATA 0x0A070601
+#define DDRSS2_PI_202_DATA 0x1F130A0D
+#define DDRSS2_PI_203_DATA 0x1F130A14
+#define DDRSS2_PI_204_DATA 0x0000C014
+#define DDRSS2_PI_205_DATA 0x00C01000
+#define DDRSS2_PI_206_DATA 0x00C01000
+#define DDRSS2_PI_207_DATA 0x00021000
+#define DDRSS2_PI_208_DATA 0x0024000E
+#define DDRSS2_PI_209_DATA 0x00240216
+#define DDRSS2_PI_210_DATA 0x00110216
+#define DDRSS2_PI_211_DATA 0x32000056
+#define DDRSS2_PI_212_DATA 0x00000301
+#define DDRSS2_PI_213_DATA 0x005B0036
+#define DDRSS2_PI_214_DATA 0x03013212
+#define DDRSS2_PI_215_DATA 0x00003600
+#define DDRSS2_PI_216_DATA 0x3212005B
+#define DDRSS2_PI_217_DATA 0x09000301
+#define DDRSS2_PI_218_DATA 0x04010504
+#define DDRSS2_PI_219_DATA 0x040006C9
+#define DDRSS2_PI_220_DATA 0x0A032001
+#define DDRSS2_PI_221_DATA 0x2C31110A
+#define DDRSS2_PI_222_DATA 0x00002918
+#define DDRSS2_PI_223_DATA 0x6001071C
+#define DDRSS2_PI_224_DATA 0x1E202008
+#define DDRSS2_PI_225_DATA 0x2C311116
+#define DDRSS2_PI_226_DATA 0x00002918
+#define DDRSS2_PI_227_DATA 0x6001071C
+#define DDRSS2_PI_228_DATA 0x1E202008
+#define DDRSS2_PI_229_DATA 0x00019C16
+#define DDRSS2_PI_230_DATA 0x00001018
+#define DDRSS2_PI_231_DATA 0x000040E6
+#define DDRSS2_PI_232_DATA 0x000288FC
+#define DDRSS2_PI_233_DATA 0x000040E6
+#define DDRSS2_PI_234_DATA 0x000288FC
+#define DDRSS2_PI_235_DATA 0x033B0016
+#define DDRSS2_PI_236_DATA 0x0303033B
+#define DDRSS2_PI_237_DATA 0x002AF803
+#define DDRSS2_PI_238_DATA 0x0001ADAF
+#define DDRSS2_PI_239_DATA 0x00000005
+#define DDRSS2_PI_240_DATA 0x0000006E
+#define DDRSS2_PI_241_DATA 0x00000016
+#define DDRSS2_PI_242_DATA 0x000681C8
+#define DDRSS2_PI_243_DATA 0x0001ADAF
+#define DDRSS2_PI_244_DATA 0x00000005
+#define DDRSS2_PI_245_DATA 0x000010A9
+#define DDRSS2_PI_246_DATA 0x0000033B
+#define DDRSS2_PI_247_DATA 0x000681C8
+#define DDRSS2_PI_248_DATA 0x0001ADAF
+#define DDRSS2_PI_249_DATA 0x00000005
+#define DDRSS2_PI_250_DATA 0x000010A9
+#define DDRSS2_PI_251_DATA 0x0100033B
+#define DDRSS2_PI_252_DATA 0x00370040
+#define DDRSS2_PI_253_DATA 0x00010008
+#define DDRSS2_PI_254_DATA 0x08550040
+#define DDRSS2_PI_255_DATA 0x00010040
+#define DDRSS2_PI_256_DATA 0x08550040
+#define DDRSS2_PI_257_DATA 0x00000340
+#define DDRSS2_PI_258_DATA 0x006B006B
+#define DDRSS2_PI_259_DATA 0x08040404
+#define DDRSS2_PI_260_DATA 0x00000055
+#define DDRSS2_PI_261_DATA 0x55083C5A
+#define DDRSS2_PI_262_DATA 0x5A000000
+#define DDRSS2_PI_263_DATA 0x0055083C
+#define DDRSS2_PI_264_DATA 0x3C5A0000
+#define DDRSS2_PI_265_DATA 0x00005508
+#define DDRSS2_PI_266_DATA 0x0C3C5A00
+#define DDRSS2_PI_267_DATA 0x080F0E0D
+#define DDRSS2_PI_268_DATA 0x000B0A09
+#define DDRSS2_PI_269_DATA 0x00030201
+#define DDRSS2_PI_270_DATA 0x01000000
+#define DDRSS2_PI_271_DATA 0x04020201
+#define DDRSS2_PI_272_DATA 0x00080804
+#define DDRSS2_PI_273_DATA 0x00000000
+#define DDRSS2_PI_274_DATA 0x00000000
+#define DDRSS2_PI_275_DATA 0x00330084
+#define DDRSS2_PI_276_DATA 0x00160000
+#define DDRSS2_PI_277_DATA 0x35333FF4
+#define DDRSS2_PI_278_DATA 0x00160F27
+#define DDRSS2_PI_279_DATA 0x35333FF4
+#define DDRSS2_PI_280_DATA 0x00160F27
+#define DDRSS2_PI_281_DATA 0x00330084
+#define DDRSS2_PI_282_DATA 0x00160000
+#define DDRSS2_PI_283_DATA 0x35333FF4
+#define DDRSS2_PI_284_DATA 0x00160F27
+#define DDRSS2_PI_285_DATA 0x35333FF4
+#define DDRSS2_PI_286_DATA 0x00160F27
+#define DDRSS2_PI_287_DATA 0x00330084
+#define DDRSS2_PI_288_DATA 0x00160000
+#define DDRSS2_PI_289_DATA 0x35333FF4
+#define DDRSS2_PI_290_DATA 0x00160F27
+#define DDRSS2_PI_291_DATA 0x35333FF4
+#define DDRSS2_PI_292_DATA 0x00160F27
+#define DDRSS2_PI_293_DATA 0x00330084
+#define DDRSS2_PI_294_DATA 0x00160000
+#define DDRSS2_PI_295_DATA 0x35333FF4
+#define DDRSS2_PI_296_DATA 0x00160F27
+#define DDRSS2_PI_297_DATA 0x35333FF4
+#define DDRSS2_PI_298_DATA 0x00160F27
+#define DDRSS2_PI_299_DATA 0x00000000
+
+#define DDRSS2_PHY_00_DATA 0x000004F0
+#define DDRSS2_PHY_01_DATA 0x00000000
+#define DDRSS2_PHY_02_DATA 0x00030200
+#define DDRSS2_PHY_03_DATA 0x00000000
+#define DDRSS2_PHY_04_DATA 0x00000000
+#define DDRSS2_PHY_05_DATA 0x01030000
+#define DDRSS2_PHY_06_DATA 0x00010000
+#define DDRSS2_PHY_07_DATA 0x01030004
+#define DDRSS2_PHY_08_DATA 0x01000000
+#define DDRSS2_PHY_09_DATA 0x00000000
+#define DDRSS2_PHY_10_DATA 0x00000000
+#define DDRSS2_PHY_11_DATA 0x01000001
+#define DDRSS2_PHY_12_DATA 0x00000100
+#define DDRSS2_PHY_13_DATA 0x000800C0
+#define DDRSS2_PHY_14_DATA 0x060100CC
+#define DDRSS2_PHY_15_DATA 0x00030066
+#define DDRSS2_PHY_16_DATA 0x00000000
+#define DDRSS2_PHY_17_DATA 0x00000301
+#define DDRSS2_PHY_18_DATA 0x0000AAAA
+#define DDRSS2_PHY_19_DATA 0x00005555
+#define DDRSS2_PHY_20_DATA 0x0000B5B5
+#define DDRSS2_PHY_21_DATA 0x00004A4A
+#define DDRSS2_PHY_22_DATA 0x00005656
+#define DDRSS2_PHY_23_DATA 0x0000A9A9
+#define DDRSS2_PHY_24_DATA 0x0000A9A9
+#define DDRSS2_PHY_25_DATA 0x0000B5B5
+#define DDRSS2_PHY_26_DATA 0x00000000
+#define DDRSS2_PHY_27_DATA 0x00000000
+#define DDRSS2_PHY_28_DATA 0x2A000000
+#define DDRSS2_PHY_29_DATA 0x00000808
+#define DDRSS2_PHY_30_DATA 0x0F000000
+#define DDRSS2_PHY_31_DATA 0x00000F0F
+#define DDRSS2_PHY_32_DATA 0x10400000
+#define DDRSS2_PHY_33_DATA 0x0C002006
+#define DDRSS2_PHY_34_DATA 0x00000000
+#define DDRSS2_PHY_35_DATA 0x00000000
+#define DDRSS2_PHY_36_DATA 0x55555555
+#define DDRSS2_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_38_DATA 0x55555555
+#define DDRSS2_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_40_DATA 0x00005555
+#define DDRSS2_PHY_41_DATA 0x01000100
+#define DDRSS2_PHY_42_DATA 0x00800180
+#define DDRSS2_PHY_43_DATA 0x00000001
+#define DDRSS2_PHY_44_DATA 0x00000000
+#define DDRSS2_PHY_45_DATA 0x00000000
+#define DDRSS2_PHY_46_DATA 0x00000000
+#define DDRSS2_PHY_47_DATA 0x00000000
+#define DDRSS2_PHY_48_DATA 0x00000000
+#define DDRSS2_PHY_49_DATA 0x00000000
+#define DDRSS2_PHY_50_DATA 0x00000000
+#define DDRSS2_PHY_51_DATA 0x00000000
+#define DDRSS2_PHY_52_DATA 0x00000000
+#define DDRSS2_PHY_53_DATA 0x00000000
+#define DDRSS2_PHY_54_DATA 0x00000000
+#define DDRSS2_PHY_55_DATA 0x00000000
+#define DDRSS2_PHY_56_DATA 0x00000000
+#define DDRSS2_PHY_57_DATA 0x00000000
+#define DDRSS2_PHY_58_DATA 0x00000000
+#define DDRSS2_PHY_59_DATA 0x00000000
+#define DDRSS2_PHY_60_DATA 0x00000000
+#define DDRSS2_PHY_61_DATA 0x00000000
+#define DDRSS2_PHY_62_DATA 0x00000000
+#define DDRSS2_PHY_63_DATA 0x00000000
+#define DDRSS2_PHY_64_DATA 0x00000000
+#define DDRSS2_PHY_65_DATA 0x00000000
+#define DDRSS2_PHY_66_DATA 0x00000104
+#define DDRSS2_PHY_67_DATA 0x00000120
+#define DDRSS2_PHY_68_DATA 0x00000000
+#define DDRSS2_PHY_69_DATA 0x00000000
+#define DDRSS2_PHY_70_DATA 0x00000000
+#define DDRSS2_PHY_71_DATA 0x00000000
+#define DDRSS2_PHY_72_DATA 0x00000000
+#define DDRSS2_PHY_73_DATA 0x00000000
+#define DDRSS2_PHY_74_DATA 0x00000000
+#define DDRSS2_PHY_75_DATA 0x00000001
+#define DDRSS2_PHY_76_DATA 0x07FF0000
+#define DDRSS2_PHY_77_DATA 0x0080081F
+#define DDRSS2_PHY_78_DATA 0x00081020
+#define DDRSS2_PHY_79_DATA 0x04010000
+#define DDRSS2_PHY_80_DATA 0x00000000
+#define DDRSS2_PHY_81_DATA 0x00000000
+#define DDRSS2_PHY_82_DATA 0x00000000
+#define DDRSS2_PHY_83_DATA 0x00000100
+#define DDRSS2_PHY_84_DATA 0x01CC0C01
+#define DDRSS2_PHY_85_DATA 0x1003CC0C
+#define DDRSS2_PHY_86_DATA 0x20000140
+#define DDRSS2_PHY_87_DATA 0x07FF0200
+#define DDRSS2_PHY_88_DATA 0x0000DD01
+#define DDRSS2_PHY_89_DATA 0x10100303
+#define DDRSS2_PHY_90_DATA 0x10101010
+#define DDRSS2_PHY_91_DATA 0x10101010
+#define DDRSS2_PHY_92_DATA 0x00021010
+#define DDRSS2_PHY_93_DATA 0x00100010
+#define DDRSS2_PHY_94_DATA 0x00100010
+#define DDRSS2_PHY_95_DATA 0x00100010
+#define DDRSS2_PHY_96_DATA 0x00100010
+#define DDRSS2_PHY_97_DATA 0x00050010
+#define DDRSS2_PHY_98_DATA 0x51517041
+#define DDRSS2_PHY_99_DATA 0x31C06001
+#define DDRSS2_PHY_100_DATA 0x07AB0340
+#define DDRSS2_PHY_101_DATA 0x00C0C001
+#define DDRSS2_PHY_102_DATA 0x0E0D0001
+#define DDRSS2_PHY_103_DATA 0x10001000
+#define DDRSS2_PHY_104_DATA 0x0C083E42
+#define DDRSS2_PHY_105_DATA 0x0F0C3701
+#define DDRSS2_PHY_106_DATA 0x01000140
+#define DDRSS2_PHY_107_DATA 0x0C000420
+#define DDRSS2_PHY_108_DATA 0x00000198
+#define DDRSS2_PHY_109_DATA 0x0A0000D0
+#define DDRSS2_PHY_110_DATA 0x00030200
+#define DDRSS2_PHY_111_DATA 0x02800000
+#define DDRSS2_PHY_112_DATA 0x80800000
+#define DDRSS2_PHY_113_DATA 0x000E2010
+#define DDRSS2_PHY_114_DATA 0x76543210
+#define DDRSS2_PHY_115_DATA 0x00000008
+#define DDRSS2_PHY_116_DATA 0x02800280
+#define DDRSS2_PHY_117_DATA 0x02800280
+#define DDRSS2_PHY_118_DATA 0x02800280
+#define DDRSS2_PHY_119_DATA 0x02800280
+#define DDRSS2_PHY_120_DATA 0x00000280
+#define DDRSS2_PHY_121_DATA 0x0000A000
+#define DDRSS2_PHY_122_DATA 0x00A000A0
+#define DDRSS2_PHY_123_DATA 0x00A000A0
+#define DDRSS2_PHY_124_DATA 0x00A000A0
+#define DDRSS2_PHY_125_DATA 0x00A000A0
+#define DDRSS2_PHY_126_DATA 0x00A000A0
+#define DDRSS2_PHY_127_DATA 0x00A000A0
+#define DDRSS2_PHY_128_DATA 0x00A000A0
+#define DDRSS2_PHY_129_DATA 0x00A000A0
+#define DDRSS2_PHY_130_DATA 0x01C200A0
+#define DDRSS2_PHY_131_DATA 0x01A00005
+#define DDRSS2_PHY_132_DATA 0x00000000
+#define DDRSS2_PHY_133_DATA 0x00000000
+#define DDRSS2_PHY_134_DATA 0x00080200
+#define DDRSS2_PHY_135_DATA 0x00000000
+#define DDRSS2_PHY_136_DATA 0x20202000
+#define DDRSS2_PHY_137_DATA 0x20202020
+#define DDRSS2_PHY_138_DATA 0xF0F02020
+#define DDRSS2_PHY_139_DATA 0x00000000
+#define DDRSS2_PHY_140_DATA 0x00000000
+#define DDRSS2_PHY_141_DATA 0x00000000
+#define DDRSS2_PHY_142_DATA 0x00000000
+#define DDRSS2_PHY_143_DATA 0x00000000
+#define DDRSS2_PHY_144_DATA 0x00000000
+#define DDRSS2_PHY_145_DATA 0x00000000
+#define DDRSS2_PHY_146_DATA 0x00000000
+#define DDRSS2_PHY_147_DATA 0x00000000
+#define DDRSS2_PHY_148_DATA 0x00000000
+#define DDRSS2_PHY_149_DATA 0x00000000
+#define DDRSS2_PHY_150_DATA 0x00000000
+#define DDRSS2_PHY_151_DATA 0x00000000
+#define DDRSS2_PHY_152_DATA 0x00000000
+#define DDRSS2_PHY_153_DATA 0x00000000
+#define DDRSS2_PHY_154_DATA 0x00000000
+#define DDRSS2_PHY_155_DATA 0x00000000
+#define DDRSS2_PHY_156_DATA 0x00000000
+#define DDRSS2_PHY_157_DATA 0x00000000
+#define DDRSS2_PHY_158_DATA 0x00000000
+#define DDRSS2_PHY_159_DATA 0x00000000
+#define DDRSS2_PHY_160_DATA 0x00000000
+#define DDRSS2_PHY_161_DATA 0x00000000
+#define DDRSS2_PHY_162_DATA 0x00000000
+#define DDRSS2_PHY_163_DATA 0x00000000
+#define DDRSS2_PHY_164_DATA 0x00000000
+#define DDRSS2_PHY_165_DATA 0x00000000
+#define DDRSS2_PHY_166_DATA 0x00000000
+#define DDRSS2_PHY_167_DATA 0x00000000
+#define DDRSS2_PHY_168_DATA 0x00000000
+#define DDRSS2_PHY_169_DATA 0x00000000
+#define DDRSS2_PHY_170_DATA 0x00000000
+#define DDRSS2_PHY_171_DATA 0x00000000
+#define DDRSS2_PHY_172_DATA 0x00000000
+#define DDRSS2_PHY_173_DATA 0x00000000
+#define DDRSS2_PHY_174_DATA 0x00000000
+#define DDRSS2_PHY_175_DATA 0x00000000
+#define DDRSS2_PHY_176_DATA 0x00000000
+#define DDRSS2_PHY_177_DATA 0x00000000
+#define DDRSS2_PHY_178_DATA 0x00000000
+#define DDRSS2_PHY_179_DATA 0x00000000
+#define DDRSS2_PHY_180_DATA 0x00000000
+#define DDRSS2_PHY_181_DATA 0x00000000
+#define DDRSS2_PHY_182_DATA 0x00000000
+#define DDRSS2_PHY_183_DATA 0x00000000
+#define DDRSS2_PHY_184_DATA 0x00000000
+#define DDRSS2_PHY_185_DATA 0x00000000
+#define DDRSS2_PHY_186_DATA 0x00000000
+#define DDRSS2_PHY_187_DATA 0x00000000
+#define DDRSS2_PHY_188_DATA 0x00000000
+#define DDRSS2_PHY_189_DATA 0x00000000
+#define DDRSS2_PHY_190_DATA 0x00000000
+#define DDRSS2_PHY_191_DATA 0x00000000
+#define DDRSS2_PHY_192_DATA 0x00000000
+#define DDRSS2_PHY_193_DATA 0x00000000
+#define DDRSS2_PHY_194_DATA 0x00000000
+#define DDRSS2_PHY_195_DATA 0x00000000
+#define DDRSS2_PHY_196_DATA 0x00000000
+#define DDRSS2_PHY_197_DATA 0x00000000
+#define DDRSS2_PHY_198_DATA 0x00000000
+#define DDRSS2_PHY_199_DATA 0x00000000
+#define DDRSS2_PHY_200_DATA 0x00000000
+#define DDRSS2_PHY_201_DATA 0x00000000
+#define DDRSS2_PHY_202_DATA 0x00000000
+#define DDRSS2_PHY_203_DATA 0x00000000
+#define DDRSS2_PHY_204_DATA 0x00000000
+#define DDRSS2_PHY_205_DATA 0x00000000
+#define DDRSS2_PHY_206_DATA 0x00000000
+#define DDRSS2_PHY_207_DATA 0x00000000
+#define DDRSS2_PHY_208_DATA 0x00000000
+#define DDRSS2_PHY_209_DATA 0x00000000
+#define DDRSS2_PHY_210_DATA 0x00000000
+#define DDRSS2_PHY_211_DATA 0x00000000
+#define DDRSS2_PHY_212_DATA 0x00000000
+#define DDRSS2_PHY_213_DATA 0x00000000
+#define DDRSS2_PHY_214_DATA 0x00000000
+#define DDRSS2_PHY_215_DATA 0x00000000
+#define DDRSS2_PHY_216_DATA 0x00000000
+#define DDRSS2_PHY_217_DATA 0x00000000
+#define DDRSS2_PHY_218_DATA 0x00000000
+#define DDRSS2_PHY_219_DATA 0x00000000
+#define DDRSS2_PHY_220_DATA 0x00000000
+#define DDRSS2_PHY_221_DATA 0x00000000
+#define DDRSS2_PHY_222_DATA 0x00000000
+#define DDRSS2_PHY_223_DATA 0x00000000
+#define DDRSS2_PHY_224_DATA 0x00000000
+#define DDRSS2_PHY_225_DATA 0x00000000
+#define DDRSS2_PHY_226_DATA 0x00000000
+#define DDRSS2_PHY_227_DATA 0x00000000
+#define DDRSS2_PHY_228_DATA 0x00000000
+#define DDRSS2_PHY_229_DATA 0x00000000
+#define DDRSS2_PHY_230_DATA 0x00000000
+#define DDRSS2_PHY_231_DATA 0x00000000
+#define DDRSS2_PHY_232_DATA 0x00000000
+#define DDRSS2_PHY_233_DATA 0x00000000
+#define DDRSS2_PHY_234_DATA 0x00000000
+#define DDRSS2_PHY_235_DATA 0x00000000
+#define DDRSS2_PHY_236_DATA 0x00000000
+#define DDRSS2_PHY_237_DATA 0x00000000
+#define DDRSS2_PHY_238_DATA 0x00000000
+#define DDRSS2_PHY_239_DATA 0x00000000
+#define DDRSS2_PHY_240_DATA 0x00000000
+#define DDRSS2_PHY_241_DATA 0x00000000
+#define DDRSS2_PHY_242_DATA 0x00000000
+#define DDRSS2_PHY_243_DATA 0x00000000
+#define DDRSS2_PHY_244_DATA 0x00000000
+#define DDRSS2_PHY_245_DATA 0x00000000
+#define DDRSS2_PHY_246_DATA 0x00000000
+#define DDRSS2_PHY_247_DATA 0x00000000
+#define DDRSS2_PHY_248_DATA 0x00000000
+#define DDRSS2_PHY_249_DATA 0x00000000
+#define DDRSS2_PHY_250_DATA 0x00000000
+#define DDRSS2_PHY_251_DATA 0x00000000
+#define DDRSS2_PHY_252_DATA 0x00000000
+#define DDRSS2_PHY_253_DATA 0x00000000
+#define DDRSS2_PHY_254_DATA 0x00000000
+#define DDRSS2_PHY_255_DATA 0x00000000
+#define DDRSS2_PHY_256_DATA 0x000004F0
+#define DDRSS2_PHY_257_DATA 0x00000000
+#define DDRSS2_PHY_258_DATA 0x00030200
+#define DDRSS2_PHY_259_DATA 0x00000000
+#define DDRSS2_PHY_260_DATA 0x00000000
+#define DDRSS2_PHY_261_DATA 0x01030000
+#define DDRSS2_PHY_262_DATA 0x00010000
+#define DDRSS2_PHY_263_DATA 0x01030004
+#define DDRSS2_PHY_264_DATA 0x01000000
+#define DDRSS2_PHY_265_DATA 0x00000000
+#define DDRSS2_PHY_266_DATA 0x00000000
+#define DDRSS2_PHY_267_DATA 0x01000001
+#define DDRSS2_PHY_268_DATA 0x00000100
+#define DDRSS2_PHY_269_DATA 0x000800C0
+#define DDRSS2_PHY_270_DATA 0x060100CC
+#define DDRSS2_PHY_271_DATA 0x00030066
+#define DDRSS2_PHY_272_DATA 0x00000000
+#define DDRSS2_PHY_273_DATA 0x00000301
+#define DDRSS2_PHY_274_DATA 0x0000AAAA
+#define DDRSS2_PHY_275_DATA 0x00005555
+#define DDRSS2_PHY_276_DATA 0x0000B5B5
+#define DDRSS2_PHY_277_DATA 0x00004A4A
+#define DDRSS2_PHY_278_DATA 0x00005656
+#define DDRSS2_PHY_279_DATA 0x0000A9A9
+#define DDRSS2_PHY_280_DATA 0x0000A9A9
+#define DDRSS2_PHY_281_DATA 0x0000B5B5
+#define DDRSS2_PHY_282_DATA 0x00000000
+#define DDRSS2_PHY_283_DATA 0x00000000
+#define DDRSS2_PHY_284_DATA 0x2A000000
+#define DDRSS2_PHY_285_DATA 0x00000808
+#define DDRSS2_PHY_286_DATA 0x0F000000
+#define DDRSS2_PHY_287_DATA 0x00000F0F
+#define DDRSS2_PHY_288_DATA 0x10400000
+#define DDRSS2_PHY_289_DATA 0x0C002006
+#define DDRSS2_PHY_290_DATA 0x00000000
+#define DDRSS2_PHY_291_DATA 0x00000000
+#define DDRSS2_PHY_292_DATA 0x55555555
+#define DDRSS2_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_294_DATA 0x55555555
+#define DDRSS2_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_296_DATA 0x00005555
+#define DDRSS2_PHY_297_DATA 0x01000100
+#define DDRSS2_PHY_298_DATA 0x00800180
+#define DDRSS2_PHY_299_DATA 0x00000000
+#define DDRSS2_PHY_300_DATA 0x00000000
+#define DDRSS2_PHY_301_DATA 0x00000000
+#define DDRSS2_PHY_302_DATA 0x00000000
+#define DDRSS2_PHY_303_DATA 0x00000000
+#define DDRSS2_PHY_304_DATA 0x00000000
+#define DDRSS2_PHY_305_DATA 0x00000000
+#define DDRSS2_PHY_306_DATA 0x00000000
+#define DDRSS2_PHY_307_DATA 0x00000000
+#define DDRSS2_PHY_308_DATA 0x00000000
+#define DDRSS2_PHY_309_DATA 0x00000000
+#define DDRSS2_PHY_310_DATA 0x00000000
+#define DDRSS2_PHY_311_DATA 0x00000000
+#define DDRSS2_PHY_312_DATA 0x00000000
+#define DDRSS2_PHY_313_DATA 0x00000000
+#define DDRSS2_PHY_314_DATA 0x00000000
+#define DDRSS2_PHY_315_DATA 0x00000000
+#define DDRSS2_PHY_316_DATA 0x00000000
+#define DDRSS2_PHY_317_DATA 0x00000000
+#define DDRSS2_PHY_318_DATA 0x00000000
+#define DDRSS2_PHY_319_DATA 0x00000000
+#define DDRSS2_PHY_320_DATA 0x00000000
+#define DDRSS2_PHY_321_DATA 0x00000000
+#define DDRSS2_PHY_322_DATA 0x00000104
+#define DDRSS2_PHY_323_DATA 0x00000120
+#define DDRSS2_PHY_324_DATA 0x00000000
+#define DDRSS2_PHY_325_DATA 0x00000000
+#define DDRSS2_PHY_326_DATA 0x00000000
+#define DDRSS2_PHY_327_DATA 0x00000000
+#define DDRSS2_PHY_328_DATA 0x00000000
+#define DDRSS2_PHY_329_DATA 0x00000000
+#define DDRSS2_PHY_330_DATA 0x00000000
+#define DDRSS2_PHY_331_DATA 0x00000001
+#define DDRSS2_PHY_332_DATA 0x07FF0000
+#define DDRSS2_PHY_333_DATA 0x0080081F
+#define DDRSS2_PHY_334_DATA 0x00081020
+#define DDRSS2_PHY_335_DATA 0x04010000
+#define DDRSS2_PHY_336_DATA 0x00000000
+#define DDRSS2_PHY_337_DATA 0x00000000
+#define DDRSS2_PHY_338_DATA 0x00000000
+#define DDRSS2_PHY_339_DATA 0x00000100
+#define DDRSS2_PHY_340_DATA 0x01CC0C01
+#define DDRSS2_PHY_341_DATA 0x1003CC0C
+#define DDRSS2_PHY_342_DATA 0x20000140
+#define DDRSS2_PHY_343_DATA 0x07FF0200
+#define DDRSS2_PHY_344_DATA 0x0000DD01
+#define DDRSS2_PHY_345_DATA 0x10100303
+#define DDRSS2_PHY_346_DATA 0x10101010
+#define DDRSS2_PHY_347_DATA 0x10101010
+#define DDRSS2_PHY_348_DATA 0x00021010
+#define DDRSS2_PHY_349_DATA 0x00100010
+#define DDRSS2_PHY_350_DATA 0x00100010
+#define DDRSS2_PHY_351_DATA 0x00100010
+#define DDRSS2_PHY_352_DATA 0x00100010
+#define DDRSS2_PHY_353_DATA 0x00050010
+#define DDRSS2_PHY_354_DATA 0x51517041
+#define DDRSS2_PHY_355_DATA 0x31C06001
+#define DDRSS2_PHY_356_DATA 0x07AB0340
+#define DDRSS2_PHY_357_DATA 0x00C0C001
+#define DDRSS2_PHY_358_DATA 0x0E0D0001
+#define DDRSS2_PHY_359_DATA 0x10001000
+#define DDRSS2_PHY_360_DATA 0x0C083E42
+#define DDRSS2_PHY_361_DATA 0x0F0C3701
+#define DDRSS2_PHY_362_DATA 0x01000140
+#define DDRSS2_PHY_363_DATA 0x0C000420
+#define DDRSS2_PHY_364_DATA 0x00000198
+#define DDRSS2_PHY_365_DATA 0x0A0000D0
+#define DDRSS2_PHY_366_DATA 0x00030200
+#define DDRSS2_PHY_367_DATA 0x02800000
+#define DDRSS2_PHY_368_DATA 0x80800000
+#define DDRSS2_PHY_369_DATA 0x000E2010
+#define DDRSS2_PHY_370_DATA 0x76543210
+#define DDRSS2_PHY_371_DATA 0x00000008
+#define DDRSS2_PHY_372_DATA 0x02800280
+#define DDRSS2_PHY_373_DATA 0x02800280
+#define DDRSS2_PHY_374_DATA 0x02800280
+#define DDRSS2_PHY_375_DATA 0x02800280
+#define DDRSS2_PHY_376_DATA 0x00000280
+#define DDRSS2_PHY_377_DATA 0x0000A000
+#define DDRSS2_PHY_378_DATA 0x00A000A0
+#define DDRSS2_PHY_379_DATA 0x00A000A0
+#define DDRSS2_PHY_380_DATA 0x00A000A0
+#define DDRSS2_PHY_381_DATA 0x00A000A0
+#define DDRSS2_PHY_382_DATA 0x00A000A0
+#define DDRSS2_PHY_383_DATA 0x00A000A0
+#define DDRSS2_PHY_384_DATA 0x00A000A0
+#define DDRSS2_PHY_385_DATA 0x00A000A0
+#define DDRSS2_PHY_386_DATA 0x01C200A0
+#define DDRSS2_PHY_387_DATA 0x01A00005
+#define DDRSS2_PHY_388_DATA 0x00000000
+#define DDRSS2_PHY_389_DATA 0x00000000
+#define DDRSS2_PHY_390_DATA 0x00080200
+#define DDRSS2_PHY_391_DATA 0x00000000
+#define DDRSS2_PHY_392_DATA 0x20202000
+#define DDRSS2_PHY_393_DATA 0x20202020
+#define DDRSS2_PHY_394_DATA 0xF0F02020
+#define DDRSS2_PHY_395_DATA 0x00000000
+#define DDRSS2_PHY_396_DATA 0x00000000
+#define DDRSS2_PHY_397_DATA 0x00000000
+#define DDRSS2_PHY_398_DATA 0x00000000
+#define DDRSS2_PHY_399_DATA 0x00000000
+#define DDRSS2_PHY_400_DATA 0x00000000
+#define DDRSS2_PHY_401_DATA 0x00000000
+#define DDRSS2_PHY_402_DATA 0x00000000
+#define DDRSS2_PHY_403_DATA 0x00000000
+#define DDRSS2_PHY_404_DATA 0x00000000
+#define DDRSS2_PHY_405_DATA 0x00000000
+#define DDRSS2_PHY_406_DATA 0x00000000
+#define DDRSS2_PHY_407_DATA 0x00000000
+#define DDRSS2_PHY_408_DATA 0x00000000
+#define DDRSS2_PHY_409_DATA 0x00000000
+#define DDRSS2_PHY_410_DATA 0x00000000
+#define DDRSS2_PHY_411_DATA 0x00000000
+#define DDRSS2_PHY_412_DATA 0x00000000
+#define DDRSS2_PHY_413_DATA 0x00000000
+#define DDRSS2_PHY_414_DATA 0x00000000
+#define DDRSS2_PHY_415_DATA 0x00000000
+#define DDRSS2_PHY_416_DATA 0x00000000
+#define DDRSS2_PHY_417_DATA 0x00000000
+#define DDRSS2_PHY_418_DATA 0x00000000
+#define DDRSS2_PHY_419_DATA 0x00000000
+#define DDRSS2_PHY_420_DATA 0x00000000
+#define DDRSS2_PHY_421_DATA 0x00000000
+#define DDRSS2_PHY_422_DATA 0x00000000
+#define DDRSS2_PHY_423_DATA 0x00000000
+#define DDRSS2_PHY_424_DATA 0x00000000
+#define DDRSS2_PHY_425_DATA 0x00000000
+#define DDRSS2_PHY_426_DATA 0x00000000
+#define DDRSS2_PHY_427_DATA 0x00000000
+#define DDRSS2_PHY_428_DATA 0x00000000
+#define DDRSS2_PHY_429_DATA 0x00000000
+#define DDRSS2_PHY_430_DATA 0x00000000
+#define DDRSS2_PHY_431_DATA 0x00000000
+#define DDRSS2_PHY_432_DATA 0x00000000
+#define DDRSS2_PHY_433_DATA 0x00000000
+#define DDRSS2_PHY_434_DATA 0x00000000
+#define DDRSS2_PHY_435_DATA 0x00000000
+#define DDRSS2_PHY_436_DATA 0x00000000
+#define DDRSS2_PHY_437_DATA 0x00000000
+#define DDRSS2_PHY_438_DATA 0x00000000
+#define DDRSS2_PHY_439_DATA 0x00000000
+#define DDRSS2_PHY_440_DATA 0x00000000
+#define DDRSS2_PHY_441_DATA 0x00000000
+#define DDRSS2_PHY_442_DATA 0x00000000
+#define DDRSS2_PHY_443_DATA 0x00000000
+#define DDRSS2_PHY_444_DATA 0x00000000
+#define DDRSS2_PHY_445_DATA 0x00000000
+#define DDRSS2_PHY_446_DATA 0x00000000
+#define DDRSS2_PHY_447_DATA 0x00000000
+#define DDRSS2_PHY_448_DATA 0x00000000
+#define DDRSS2_PHY_449_DATA 0x00000000
+#define DDRSS2_PHY_450_DATA 0x00000000
+#define DDRSS2_PHY_451_DATA 0x00000000
+#define DDRSS2_PHY_452_DATA 0x00000000
+#define DDRSS2_PHY_453_DATA 0x00000000
+#define DDRSS2_PHY_454_DATA 0x00000000
+#define DDRSS2_PHY_455_DATA 0x00000000
+#define DDRSS2_PHY_456_DATA 0x00000000
+#define DDRSS2_PHY_457_DATA 0x00000000
+#define DDRSS2_PHY_458_DATA 0x00000000
+#define DDRSS2_PHY_459_DATA 0x00000000
+#define DDRSS2_PHY_460_DATA 0x00000000
+#define DDRSS2_PHY_461_DATA 0x00000000
+#define DDRSS2_PHY_462_DATA 0x00000000
+#define DDRSS2_PHY_463_DATA 0x00000000
+#define DDRSS2_PHY_464_DATA 0x00000000
+#define DDRSS2_PHY_465_DATA 0x00000000
+#define DDRSS2_PHY_466_DATA 0x00000000
+#define DDRSS2_PHY_467_DATA 0x00000000
+#define DDRSS2_PHY_468_DATA 0x00000000
+#define DDRSS2_PHY_469_DATA 0x00000000
+#define DDRSS2_PHY_470_DATA 0x00000000
+#define DDRSS2_PHY_471_DATA 0x00000000
+#define DDRSS2_PHY_472_DATA 0x00000000
+#define DDRSS2_PHY_473_DATA 0x00000000
+#define DDRSS2_PHY_474_DATA 0x00000000
+#define DDRSS2_PHY_475_DATA 0x00000000
+#define DDRSS2_PHY_476_DATA 0x00000000
+#define DDRSS2_PHY_477_DATA 0x00000000
+#define DDRSS2_PHY_478_DATA 0x00000000
+#define DDRSS2_PHY_479_DATA 0x00000000
+#define DDRSS2_PHY_480_DATA 0x00000000
+#define DDRSS2_PHY_481_DATA 0x00000000
+#define DDRSS2_PHY_482_DATA 0x00000000
+#define DDRSS2_PHY_483_DATA 0x00000000
+#define DDRSS2_PHY_484_DATA 0x00000000
+#define DDRSS2_PHY_485_DATA 0x00000000
+#define DDRSS2_PHY_486_DATA 0x00000000
+#define DDRSS2_PHY_487_DATA 0x00000000
+#define DDRSS2_PHY_488_DATA 0x00000000
+#define DDRSS2_PHY_489_DATA 0x00000000
+#define DDRSS2_PHY_490_DATA 0x00000000
+#define DDRSS2_PHY_491_DATA 0x00000000
+#define DDRSS2_PHY_492_DATA 0x00000000
+#define DDRSS2_PHY_493_DATA 0x00000000
+#define DDRSS2_PHY_494_DATA 0x00000000
+#define DDRSS2_PHY_495_DATA 0x00000000
+#define DDRSS2_PHY_496_DATA 0x00000000
+#define DDRSS2_PHY_497_DATA 0x00000000
+#define DDRSS2_PHY_498_DATA 0x00000000
+#define DDRSS2_PHY_499_DATA 0x00000000
+#define DDRSS2_PHY_500_DATA 0x00000000
+#define DDRSS2_PHY_501_DATA 0x00000000
+#define DDRSS2_PHY_502_DATA 0x00000000
+#define DDRSS2_PHY_503_DATA 0x00000000
+#define DDRSS2_PHY_504_DATA 0x00000000
+#define DDRSS2_PHY_505_DATA 0x00000000
+#define DDRSS2_PHY_506_DATA 0x00000000
+#define DDRSS2_PHY_507_DATA 0x00000000
+#define DDRSS2_PHY_508_DATA 0x00000000
+#define DDRSS2_PHY_509_DATA 0x00000000
+#define DDRSS2_PHY_510_DATA 0x00000000
+#define DDRSS2_PHY_511_DATA 0x00000000
+#define DDRSS2_PHY_512_DATA 0x000004F0
+#define DDRSS2_PHY_513_DATA 0x00000000
+#define DDRSS2_PHY_514_DATA 0x00030200
+#define DDRSS2_PHY_515_DATA 0x00000000
+#define DDRSS2_PHY_516_DATA 0x00000000
+#define DDRSS2_PHY_517_DATA 0x01030000
+#define DDRSS2_PHY_518_DATA 0x00010000
+#define DDRSS2_PHY_519_DATA 0x01030004
+#define DDRSS2_PHY_520_DATA 0x01000000
+#define DDRSS2_PHY_521_DATA 0x00000000
+#define DDRSS2_PHY_522_DATA 0x00000000
+#define DDRSS2_PHY_523_DATA 0x01000001
+#define DDRSS2_PHY_524_DATA 0x00000100
+#define DDRSS2_PHY_525_DATA 0x000800C0
+#define DDRSS2_PHY_526_DATA 0x060100CC
+#define DDRSS2_PHY_527_DATA 0x00030066
+#define DDRSS2_PHY_528_DATA 0x00000000
+#define DDRSS2_PHY_529_DATA 0x00000301
+#define DDRSS2_PHY_530_DATA 0x0000AAAA
+#define DDRSS2_PHY_531_DATA 0x00005555
+#define DDRSS2_PHY_532_DATA 0x0000B5B5
+#define DDRSS2_PHY_533_DATA 0x00004A4A
+#define DDRSS2_PHY_534_DATA 0x00005656
+#define DDRSS2_PHY_535_DATA 0x0000A9A9
+#define DDRSS2_PHY_536_DATA 0x0000A9A9
+#define DDRSS2_PHY_537_DATA 0x0000B5B5
+#define DDRSS2_PHY_538_DATA 0x00000000
+#define DDRSS2_PHY_539_DATA 0x00000000
+#define DDRSS2_PHY_540_DATA 0x2A000000
+#define DDRSS2_PHY_541_DATA 0x00000808
+#define DDRSS2_PHY_542_DATA 0x0F000000
+#define DDRSS2_PHY_543_DATA 0x00000F0F
+#define DDRSS2_PHY_544_DATA 0x10400000
+#define DDRSS2_PHY_545_DATA 0x0C002006
+#define DDRSS2_PHY_546_DATA 0x00000000
+#define DDRSS2_PHY_547_DATA 0x00000000
+#define DDRSS2_PHY_548_DATA 0x55555555
+#define DDRSS2_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_550_DATA 0x55555555
+#define DDRSS2_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_552_DATA 0x00005555
+#define DDRSS2_PHY_553_DATA 0x01000100
+#define DDRSS2_PHY_554_DATA 0x00800180
+#define DDRSS2_PHY_555_DATA 0x00000001
+#define DDRSS2_PHY_556_DATA 0x00000000
+#define DDRSS2_PHY_557_DATA 0x00000000
+#define DDRSS2_PHY_558_DATA 0x00000000
+#define DDRSS2_PHY_559_DATA 0x00000000
+#define DDRSS2_PHY_560_DATA 0x00000000
+#define DDRSS2_PHY_561_DATA 0x00000000
+#define DDRSS2_PHY_562_DATA 0x00000000
+#define DDRSS2_PHY_563_DATA 0x00000000
+#define DDRSS2_PHY_564_DATA 0x00000000
+#define DDRSS2_PHY_565_DATA 0x00000000
+#define DDRSS2_PHY_566_DATA 0x00000000
+#define DDRSS2_PHY_567_DATA 0x00000000
+#define DDRSS2_PHY_568_DATA 0x00000000
+#define DDRSS2_PHY_569_DATA 0x00000000
+#define DDRSS2_PHY_570_DATA 0x00000000
+#define DDRSS2_PHY_571_DATA 0x00000000
+#define DDRSS2_PHY_572_DATA 0x00000000
+#define DDRSS2_PHY_573_DATA 0x00000000
+#define DDRSS2_PHY_574_DATA 0x00000000
+#define DDRSS2_PHY_575_DATA 0x00000000
+#define DDRSS2_PHY_576_DATA 0x00000000
+#define DDRSS2_PHY_577_DATA 0x00000000
+#define DDRSS2_PHY_578_DATA 0x00000104
+#define DDRSS2_PHY_579_DATA 0x00000120
+#define DDRSS2_PHY_580_DATA 0x00000000
+#define DDRSS2_PHY_581_DATA 0x00000000
+#define DDRSS2_PHY_582_DATA 0x00000000
+#define DDRSS2_PHY_583_DATA 0x00000000
+#define DDRSS2_PHY_584_DATA 0x00000000
+#define DDRSS2_PHY_585_DATA 0x00000000
+#define DDRSS2_PHY_586_DATA 0x00000000
+#define DDRSS2_PHY_587_DATA 0x00000001
+#define DDRSS2_PHY_588_DATA 0x07FF0000
+#define DDRSS2_PHY_589_DATA 0x0080081F
+#define DDRSS2_PHY_590_DATA 0x00081020
+#define DDRSS2_PHY_591_DATA 0x04010000
+#define DDRSS2_PHY_592_DATA 0x00000000
+#define DDRSS2_PHY_593_DATA 0x00000000
+#define DDRSS2_PHY_594_DATA 0x00000000
+#define DDRSS2_PHY_595_DATA 0x00000100
+#define DDRSS2_PHY_596_DATA 0x01CC0C01
+#define DDRSS2_PHY_597_DATA 0x1003CC0C
+#define DDRSS2_PHY_598_DATA 0x20000140
+#define DDRSS2_PHY_599_DATA 0x07FF0200
+#define DDRSS2_PHY_600_DATA 0x0000DD01
+#define DDRSS2_PHY_601_DATA 0x10100303
+#define DDRSS2_PHY_602_DATA 0x10101010
+#define DDRSS2_PHY_603_DATA 0x10101010
+#define DDRSS2_PHY_604_DATA 0x00021010
+#define DDRSS2_PHY_605_DATA 0x00100010
+#define DDRSS2_PHY_606_DATA 0x00100010
+#define DDRSS2_PHY_607_DATA 0x00100010
+#define DDRSS2_PHY_608_DATA 0x00100010
+#define DDRSS2_PHY_609_DATA 0x00050010
+#define DDRSS2_PHY_610_DATA 0x51517041
+#define DDRSS2_PHY_611_DATA 0x31C06001
+#define DDRSS2_PHY_612_DATA 0x07AB0340
+#define DDRSS2_PHY_613_DATA 0x00C0C001
+#define DDRSS2_PHY_614_DATA 0x0E0D0001
+#define DDRSS2_PHY_615_DATA 0x10001000
+#define DDRSS2_PHY_616_DATA 0x0C083E42
+#define DDRSS2_PHY_617_DATA 0x0F0C3701
+#define DDRSS2_PHY_618_DATA 0x01000140
+#define DDRSS2_PHY_619_DATA 0x0C000420
+#define DDRSS2_PHY_620_DATA 0x00000198
+#define DDRSS2_PHY_621_DATA 0x0A0000D0
+#define DDRSS2_PHY_622_DATA 0x00030200
+#define DDRSS2_PHY_623_DATA 0x02800000
+#define DDRSS2_PHY_624_DATA 0x80800000
+#define DDRSS2_PHY_625_DATA 0x000E2010
+#define DDRSS2_PHY_626_DATA 0x76543210
+#define DDRSS2_PHY_627_DATA 0x00000008
+#define DDRSS2_PHY_628_DATA 0x02800280
+#define DDRSS2_PHY_629_DATA 0x02800280
+#define DDRSS2_PHY_630_DATA 0x02800280
+#define DDRSS2_PHY_631_DATA 0x02800280
+#define DDRSS2_PHY_632_DATA 0x00000280
+#define DDRSS2_PHY_633_DATA 0x0000A000
+#define DDRSS2_PHY_634_DATA 0x00A000A0
+#define DDRSS2_PHY_635_DATA 0x00A000A0
+#define DDRSS2_PHY_636_DATA 0x00A000A0
+#define DDRSS2_PHY_637_DATA 0x00A000A0
+#define DDRSS2_PHY_638_DATA 0x00A000A0
+#define DDRSS2_PHY_639_DATA 0x00A000A0
+#define DDRSS2_PHY_640_DATA 0x00A000A0
+#define DDRSS2_PHY_641_DATA 0x00A000A0
+#define DDRSS2_PHY_642_DATA 0x01C200A0
+#define DDRSS2_PHY_643_DATA 0x01A00005
+#define DDRSS2_PHY_644_DATA 0x00000000
+#define DDRSS2_PHY_645_DATA 0x00000000
+#define DDRSS2_PHY_646_DATA 0x00080200
+#define DDRSS2_PHY_647_DATA 0x00000000
+#define DDRSS2_PHY_648_DATA 0x20202000
+#define DDRSS2_PHY_649_DATA 0x20202020
+#define DDRSS2_PHY_650_DATA 0xF0F02020
+#define DDRSS2_PHY_651_DATA 0x00000000
+#define DDRSS2_PHY_652_DATA 0x00000000
+#define DDRSS2_PHY_653_DATA 0x00000000
+#define DDRSS2_PHY_654_DATA 0x00000000
+#define DDRSS2_PHY_655_DATA 0x00000000
+#define DDRSS2_PHY_656_DATA 0x00000000
+#define DDRSS2_PHY_657_DATA 0x00000000
+#define DDRSS2_PHY_658_DATA 0x00000000
+#define DDRSS2_PHY_659_DATA 0x00000000
+#define DDRSS2_PHY_660_DATA 0x00000000
+#define DDRSS2_PHY_661_DATA 0x00000000
+#define DDRSS2_PHY_662_DATA 0x00000000
+#define DDRSS2_PHY_663_DATA 0x00000000
+#define DDRSS2_PHY_664_DATA 0x00000000
+#define DDRSS2_PHY_665_DATA 0x00000000
+#define DDRSS2_PHY_666_DATA 0x00000000
+#define DDRSS2_PHY_667_DATA 0x00000000
+#define DDRSS2_PHY_668_DATA 0x00000000
+#define DDRSS2_PHY_669_DATA 0x00000000
+#define DDRSS2_PHY_670_DATA 0x00000000
+#define DDRSS2_PHY_671_DATA 0x00000000
+#define DDRSS2_PHY_672_DATA 0x00000000
+#define DDRSS2_PHY_673_DATA 0x00000000
+#define DDRSS2_PHY_674_DATA 0x00000000
+#define DDRSS2_PHY_675_DATA 0x00000000
+#define DDRSS2_PHY_676_DATA 0x00000000
+#define DDRSS2_PHY_677_DATA 0x00000000
+#define DDRSS2_PHY_678_DATA 0x00000000
+#define DDRSS2_PHY_679_DATA 0x00000000
+#define DDRSS2_PHY_680_DATA 0x00000000
+#define DDRSS2_PHY_681_DATA 0x00000000
+#define DDRSS2_PHY_682_DATA 0x00000000
+#define DDRSS2_PHY_683_DATA 0x00000000
+#define DDRSS2_PHY_684_DATA 0x00000000
+#define DDRSS2_PHY_685_DATA 0x00000000
+#define DDRSS2_PHY_686_DATA 0x00000000
+#define DDRSS2_PHY_687_DATA 0x00000000
+#define DDRSS2_PHY_688_DATA 0x00000000
+#define DDRSS2_PHY_689_DATA 0x00000000
+#define DDRSS2_PHY_690_DATA 0x00000000
+#define DDRSS2_PHY_691_DATA 0x00000000
+#define DDRSS2_PHY_692_DATA 0x00000000
+#define DDRSS2_PHY_693_DATA 0x00000000
+#define DDRSS2_PHY_694_DATA 0x00000000
+#define DDRSS2_PHY_695_DATA 0x00000000
+#define DDRSS2_PHY_696_DATA 0x00000000
+#define DDRSS2_PHY_697_DATA 0x00000000
+#define DDRSS2_PHY_698_DATA 0x00000000
+#define DDRSS2_PHY_699_DATA 0x00000000
+#define DDRSS2_PHY_700_DATA 0x00000000
+#define DDRSS2_PHY_701_DATA 0x00000000
+#define DDRSS2_PHY_702_DATA 0x00000000
+#define DDRSS2_PHY_703_DATA 0x00000000
+#define DDRSS2_PHY_704_DATA 0x00000000
+#define DDRSS2_PHY_705_DATA 0x00000000
+#define DDRSS2_PHY_706_DATA 0x00000000
+#define DDRSS2_PHY_707_DATA 0x00000000
+#define DDRSS2_PHY_708_DATA 0x00000000
+#define DDRSS2_PHY_709_DATA 0x00000000
+#define DDRSS2_PHY_710_DATA 0x00000000
+#define DDRSS2_PHY_711_DATA 0x00000000
+#define DDRSS2_PHY_712_DATA 0x00000000
+#define DDRSS2_PHY_713_DATA 0x00000000
+#define DDRSS2_PHY_714_DATA 0x00000000
+#define DDRSS2_PHY_715_DATA 0x00000000
+#define DDRSS2_PHY_716_DATA 0x00000000
+#define DDRSS2_PHY_717_DATA 0x00000000
+#define DDRSS2_PHY_718_DATA 0x00000000
+#define DDRSS2_PHY_719_DATA 0x00000000
+#define DDRSS2_PHY_720_DATA 0x00000000
+#define DDRSS2_PHY_721_DATA 0x00000000
+#define DDRSS2_PHY_722_DATA 0x00000000
+#define DDRSS2_PHY_723_DATA 0x00000000
+#define DDRSS2_PHY_724_DATA 0x00000000
+#define DDRSS2_PHY_725_DATA 0x00000000
+#define DDRSS2_PHY_726_DATA 0x00000000
+#define DDRSS2_PHY_727_DATA 0x00000000
+#define DDRSS2_PHY_728_DATA 0x00000000
+#define DDRSS2_PHY_729_DATA 0x00000000
+#define DDRSS2_PHY_730_DATA 0x00000000
+#define DDRSS2_PHY_731_DATA 0x00000000
+#define DDRSS2_PHY_732_DATA 0x00000000
+#define DDRSS2_PHY_733_DATA 0x00000000
+#define DDRSS2_PHY_734_DATA 0x00000000
+#define DDRSS2_PHY_735_DATA 0x00000000
+#define DDRSS2_PHY_736_DATA 0x00000000
+#define DDRSS2_PHY_737_DATA 0x00000000
+#define DDRSS2_PHY_738_DATA 0x00000000
+#define DDRSS2_PHY_739_DATA 0x00000000
+#define DDRSS2_PHY_740_DATA 0x00000000
+#define DDRSS2_PHY_741_DATA 0x00000000
+#define DDRSS2_PHY_742_DATA 0x00000000
+#define DDRSS2_PHY_743_DATA 0x00000000
+#define DDRSS2_PHY_744_DATA 0x00000000
+#define DDRSS2_PHY_745_DATA 0x00000000
+#define DDRSS2_PHY_746_DATA 0x00000000
+#define DDRSS2_PHY_747_DATA 0x00000000
+#define DDRSS2_PHY_748_DATA 0x00000000
+#define DDRSS2_PHY_749_DATA 0x00000000
+#define DDRSS2_PHY_750_DATA 0x00000000
+#define DDRSS2_PHY_751_DATA 0x00000000
+#define DDRSS2_PHY_752_DATA 0x00000000
+#define DDRSS2_PHY_753_DATA 0x00000000
+#define DDRSS2_PHY_754_DATA 0x00000000
+#define DDRSS2_PHY_755_DATA 0x00000000
+#define DDRSS2_PHY_756_DATA 0x00000000
+#define DDRSS2_PHY_757_DATA 0x00000000
+#define DDRSS2_PHY_758_DATA 0x00000000
+#define DDRSS2_PHY_759_DATA 0x00000000
+#define DDRSS2_PHY_760_DATA 0x00000000
+#define DDRSS2_PHY_761_DATA 0x00000000
+#define DDRSS2_PHY_762_DATA 0x00000000
+#define DDRSS2_PHY_763_DATA 0x00000000
+#define DDRSS2_PHY_764_DATA 0x00000000
+#define DDRSS2_PHY_765_DATA 0x00000000
+#define DDRSS2_PHY_766_DATA 0x00000000
+#define DDRSS2_PHY_767_DATA 0x00000000
+#define DDRSS2_PHY_768_DATA 0x000004F0
+#define DDRSS2_PHY_769_DATA 0x00000000
+#define DDRSS2_PHY_770_DATA 0x00030200
+#define DDRSS2_PHY_771_DATA 0x00000000
+#define DDRSS2_PHY_772_DATA 0x00000000
+#define DDRSS2_PHY_773_DATA 0x01030000
+#define DDRSS2_PHY_774_DATA 0x00010000
+#define DDRSS2_PHY_775_DATA 0x01030004
+#define DDRSS2_PHY_776_DATA 0x01000000
+#define DDRSS2_PHY_777_DATA 0x00000000
+#define DDRSS2_PHY_778_DATA 0x00000000
+#define DDRSS2_PHY_779_DATA 0x01000001
+#define DDRSS2_PHY_780_DATA 0x00000100
+#define DDRSS2_PHY_781_DATA 0x000800C0
+#define DDRSS2_PHY_782_DATA 0x060100CC
+#define DDRSS2_PHY_783_DATA 0x00030066
+#define DDRSS2_PHY_784_DATA 0x00000000
+#define DDRSS2_PHY_785_DATA 0x00000301
+#define DDRSS2_PHY_786_DATA 0x0000AAAA
+#define DDRSS2_PHY_787_DATA 0x00005555
+#define DDRSS2_PHY_788_DATA 0x0000B5B5
+#define DDRSS2_PHY_789_DATA 0x00004A4A
+#define DDRSS2_PHY_790_DATA 0x00005656
+#define DDRSS2_PHY_791_DATA 0x0000A9A9
+#define DDRSS2_PHY_792_DATA 0x0000A9A9
+#define DDRSS2_PHY_793_DATA 0x0000B5B5
+#define DDRSS2_PHY_794_DATA 0x00000000
+#define DDRSS2_PHY_795_DATA 0x00000000
+#define DDRSS2_PHY_796_DATA 0x2A000000
+#define DDRSS2_PHY_797_DATA 0x00000808
+#define DDRSS2_PHY_798_DATA 0x0F000000
+#define DDRSS2_PHY_799_DATA 0x00000F0F
+#define DDRSS2_PHY_800_DATA 0x10400000
+#define DDRSS2_PHY_801_DATA 0x0C002006
+#define DDRSS2_PHY_802_DATA 0x00000000
+#define DDRSS2_PHY_803_DATA 0x00000000
+#define DDRSS2_PHY_804_DATA 0x55555555
+#define DDRSS2_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_806_DATA 0x55555555
+#define DDRSS2_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS2_PHY_808_DATA 0x00005555
+#define DDRSS2_PHY_809_DATA 0x01000100
+#define DDRSS2_PHY_810_DATA 0x00800180
+#define DDRSS2_PHY_811_DATA 0x00000000
+#define DDRSS2_PHY_812_DATA 0x00000000
+#define DDRSS2_PHY_813_DATA 0x00000000
+#define DDRSS2_PHY_814_DATA 0x00000000
+#define DDRSS2_PHY_815_DATA 0x00000000
+#define DDRSS2_PHY_816_DATA 0x00000000
+#define DDRSS2_PHY_817_DATA 0x00000000
+#define DDRSS2_PHY_818_DATA 0x00000000
+#define DDRSS2_PHY_819_DATA 0x00000000
+#define DDRSS2_PHY_820_DATA 0x00000000
+#define DDRSS2_PHY_821_DATA 0x00000000
+#define DDRSS2_PHY_822_DATA 0x00000000
+#define DDRSS2_PHY_823_DATA 0x00000000
+#define DDRSS2_PHY_824_DATA 0x00000000
+#define DDRSS2_PHY_825_DATA 0x00000000
+#define DDRSS2_PHY_826_DATA 0x00000000
+#define DDRSS2_PHY_827_DATA 0x00000000
+#define DDRSS2_PHY_828_DATA 0x00000000
+#define DDRSS2_PHY_829_DATA 0x00000000
+#define DDRSS2_PHY_830_DATA 0x00000000
+#define DDRSS2_PHY_831_DATA 0x00000000
+#define DDRSS2_PHY_832_DATA 0x00000000
+#define DDRSS2_PHY_833_DATA 0x00000000
+#define DDRSS2_PHY_834_DATA 0x00000104
+#define DDRSS2_PHY_835_DATA 0x00000120
+#define DDRSS2_PHY_836_DATA 0x00000000
+#define DDRSS2_PHY_837_DATA 0x00000000
+#define DDRSS2_PHY_838_DATA 0x00000000
+#define DDRSS2_PHY_839_DATA 0x00000000
+#define DDRSS2_PHY_840_DATA 0x00000000
+#define DDRSS2_PHY_841_DATA 0x00000000
+#define DDRSS2_PHY_842_DATA 0x00000000
+#define DDRSS2_PHY_843_DATA 0x00000001
+#define DDRSS2_PHY_844_DATA 0x07FF0000
+#define DDRSS2_PHY_845_DATA 0x0080081F
+#define DDRSS2_PHY_846_DATA 0x00081020
+#define DDRSS2_PHY_847_DATA 0x04010000
+#define DDRSS2_PHY_848_DATA 0x00000000
+#define DDRSS2_PHY_849_DATA 0x00000000
+#define DDRSS2_PHY_850_DATA 0x00000000
+#define DDRSS2_PHY_851_DATA 0x00000100
+#define DDRSS2_PHY_852_DATA 0x01CC0C01
+#define DDRSS2_PHY_853_DATA 0x1003CC0C
+#define DDRSS2_PHY_854_DATA 0x20000140
+#define DDRSS2_PHY_855_DATA 0x07FF0200
+#define DDRSS2_PHY_856_DATA 0x0000DD01
+#define DDRSS2_PHY_857_DATA 0x10100303
+#define DDRSS2_PHY_858_DATA 0x10101010
+#define DDRSS2_PHY_859_DATA 0x10101010
+#define DDRSS2_PHY_860_DATA 0x00021010
+#define DDRSS2_PHY_861_DATA 0x00100010
+#define DDRSS2_PHY_862_DATA 0x00100010
+#define DDRSS2_PHY_863_DATA 0x00100010
+#define DDRSS2_PHY_864_DATA 0x00100010
+#define DDRSS2_PHY_865_DATA 0x00050010
+#define DDRSS2_PHY_866_DATA 0x51517041
+#define DDRSS2_PHY_867_DATA 0x31C06001
+#define DDRSS2_PHY_868_DATA 0x07AB0340
+#define DDRSS2_PHY_869_DATA 0x00C0C001
+#define DDRSS2_PHY_870_DATA 0x0E0D0001
+#define DDRSS2_PHY_871_DATA 0x10001000
+#define DDRSS2_PHY_872_DATA 0x0C083E42
+#define DDRSS2_PHY_873_DATA 0x0F0C3701
+#define DDRSS2_PHY_874_DATA 0x01000140
+#define DDRSS2_PHY_875_DATA 0x0C000420
+#define DDRSS2_PHY_876_DATA 0x00000198
+#define DDRSS2_PHY_877_DATA 0x0A0000D0
+#define DDRSS2_PHY_878_DATA 0x00030200
+#define DDRSS2_PHY_879_DATA 0x02800000
+#define DDRSS2_PHY_880_DATA 0x80800000
+#define DDRSS2_PHY_881_DATA 0x000E2010
+#define DDRSS2_PHY_882_DATA 0x76543210
+#define DDRSS2_PHY_883_DATA 0x00000008
+#define DDRSS2_PHY_884_DATA 0x02800280
+#define DDRSS2_PHY_885_DATA 0x02800280
+#define DDRSS2_PHY_886_DATA 0x02800280
+#define DDRSS2_PHY_887_DATA 0x02800280
+#define DDRSS2_PHY_888_DATA 0x00000280
+#define DDRSS2_PHY_889_DATA 0x0000A000
+#define DDRSS2_PHY_890_DATA 0x00A000A0
+#define DDRSS2_PHY_891_DATA 0x00A000A0
+#define DDRSS2_PHY_892_DATA 0x00A000A0
+#define DDRSS2_PHY_893_DATA 0x00A000A0
+#define DDRSS2_PHY_894_DATA 0x00A000A0
+#define DDRSS2_PHY_895_DATA 0x00A000A0
+#define DDRSS2_PHY_896_DATA 0x00A000A0
+#define DDRSS2_PHY_897_DATA 0x00A000A0
+#define DDRSS2_PHY_898_DATA 0x01C200A0
+#define DDRSS2_PHY_899_DATA 0x01A00005
+#define DDRSS2_PHY_900_DATA 0x00000000
+#define DDRSS2_PHY_901_DATA 0x00000000
+#define DDRSS2_PHY_902_DATA 0x00080200
+#define DDRSS2_PHY_903_DATA 0x00000000
+#define DDRSS2_PHY_904_DATA 0x20202000
+#define DDRSS2_PHY_905_DATA 0x20202020
+#define DDRSS2_PHY_906_DATA 0xF0F02020
+#define DDRSS2_PHY_907_DATA 0x00000000
+#define DDRSS2_PHY_908_DATA 0x00000000
+#define DDRSS2_PHY_909_DATA 0x00000000
+#define DDRSS2_PHY_910_DATA 0x00000000
+#define DDRSS2_PHY_911_DATA 0x00000000
+#define DDRSS2_PHY_912_DATA 0x00000000
+#define DDRSS2_PHY_913_DATA 0x00000000
+#define DDRSS2_PHY_914_DATA 0x00000000
+#define DDRSS2_PHY_915_DATA 0x00000000
+#define DDRSS2_PHY_916_DATA 0x00000000
+#define DDRSS2_PHY_917_DATA 0x00000000
+#define DDRSS2_PHY_918_DATA 0x00000000
+#define DDRSS2_PHY_919_DATA 0x00000000
+#define DDRSS2_PHY_920_DATA 0x00000000
+#define DDRSS2_PHY_921_DATA 0x00000000
+#define DDRSS2_PHY_922_DATA 0x00000000
+#define DDRSS2_PHY_923_DATA 0x00000000
+#define DDRSS2_PHY_924_DATA 0x00000000
+#define DDRSS2_PHY_925_DATA 0x00000000
+#define DDRSS2_PHY_926_DATA 0x00000000
+#define DDRSS2_PHY_927_DATA 0x00000000
+#define DDRSS2_PHY_928_DATA 0x00000000
+#define DDRSS2_PHY_929_DATA 0x00000000
+#define DDRSS2_PHY_930_DATA 0x00000000
+#define DDRSS2_PHY_931_DATA 0x00000000
+#define DDRSS2_PHY_932_DATA 0x00000000
+#define DDRSS2_PHY_933_DATA 0x00000000
+#define DDRSS2_PHY_934_DATA 0x00000000
+#define DDRSS2_PHY_935_DATA 0x00000000
+#define DDRSS2_PHY_936_DATA 0x00000000
+#define DDRSS2_PHY_937_DATA 0x00000000
+#define DDRSS2_PHY_938_DATA 0x00000000
+#define DDRSS2_PHY_939_DATA 0x00000000
+#define DDRSS2_PHY_940_DATA 0x00000000
+#define DDRSS2_PHY_941_DATA 0x00000000
+#define DDRSS2_PHY_942_DATA 0x00000000
+#define DDRSS2_PHY_943_DATA 0x00000000
+#define DDRSS2_PHY_944_DATA 0x00000000
+#define DDRSS2_PHY_945_DATA 0x00000000
+#define DDRSS2_PHY_946_DATA 0x00000000
+#define DDRSS2_PHY_947_DATA 0x00000000
+#define DDRSS2_PHY_948_DATA 0x00000000
+#define DDRSS2_PHY_949_DATA 0x00000000
+#define DDRSS2_PHY_950_DATA 0x00000000
+#define DDRSS2_PHY_951_DATA 0x00000000
+#define DDRSS2_PHY_952_DATA 0x00000000
+#define DDRSS2_PHY_953_DATA 0x00000000
+#define DDRSS2_PHY_954_DATA 0x00000000
+#define DDRSS2_PHY_955_DATA 0x00000000
+#define DDRSS2_PHY_956_DATA 0x00000000
+#define DDRSS2_PHY_957_DATA 0x00000000
+#define DDRSS2_PHY_958_DATA 0x00000000
+#define DDRSS2_PHY_959_DATA 0x00000000
+#define DDRSS2_PHY_960_DATA 0x00000000
+#define DDRSS2_PHY_961_DATA 0x00000000
+#define DDRSS2_PHY_962_DATA 0x00000000
+#define DDRSS2_PHY_963_DATA 0x00000000
+#define DDRSS2_PHY_964_DATA 0x00000000
+#define DDRSS2_PHY_965_DATA 0x00000000
+#define DDRSS2_PHY_966_DATA 0x00000000
+#define DDRSS2_PHY_967_DATA 0x00000000
+#define DDRSS2_PHY_968_DATA 0x00000000
+#define DDRSS2_PHY_969_DATA 0x00000000
+#define DDRSS2_PHY_970_DATA 0x00000000
+#define DDRSS2_PHY_971_DATA 0x00000000
+#define DDRSS2_PHY_972_DATA 0x00000000
+#define DDRSS2_PHY_973_DATA 0x00000000
+#define DDRSS2_PHY_974_DATA 0x00000000
+#define DDRSS2_PHY_975_DATA 0x00000000
+#define DDRSS2_PHY_976_DATA 0x00000000
+#define DDRSS2_PHY_977_DATA 0x00000000
+#define DDRSS2_PHY_978_DATA 0x00000000
+#define DDRSS2_PHY_979_DATA 0x00000000
+#define DDRSS2_PHY_980_DATA 0x00000000
+#define DDRSS2_PHY_981_DATA 0x00000000
+#define DDRSS2_PHY_982_DATA 0x00000000
+#define DDRSS2_PHY_983_DATA 0x00000000
+#define DDRSS2_PHY_984_DATA 0x00000000
+#define DDRSS2_PHY_985_DATA 0x00000000
+#define DDRSS2_PHY_986_DATA 0x00000000
+#define DDRSS2_PHY_987_DATA 0x00000000
+#define DDRSS2_PHY_988_DATA 0x00000000
+#define DDRSS2_PHY_989_DATA 0x00000000
+#define DDRSS2_PHY_990_DATA 0x00000000
+#define DDRSS2_PHY_991_DATA 0x00000000
+#define DDRSS2_PHY_992_DATA 0x00000000
+#define DDRSS2_PHY_993_DATA 0x00000000
+#define DDRSS2_PHY_994_DATA 0x00000000
+#define DDRSS2_PHY_995_DATA 0x00000000
+#define DDRSS2_PHY_996_DATA 0x00000000
+#define DDRSS2_PHY_997_DATA 0x00000000
+#define DDRSS2_PHY_998_DATA 0x00000000
+#define DDRSS2_PHY_999_DATA 0x00000000
+#define DDRSS2_PHY_1000_DATA 0x00000000
+#define DDRSS2_PHY_1001_DATA 0x00000000
+#define DDRSS2_PHY_1002_DATA 0x00000000
+#define DDRSS2_PHY_1003_DATA 0x00000000
+#define DDRSS2_PHY_1004_DATA 0x00000000
+#define DDRSS2_PHY_1005_DATA 0x00000000
+#define DDRSS2_PHY_1006_DATA 0x00000000
+#define DDRSS2_PHY_1007_DATA 0x00000000
+#define DDRSS2_PHY_1008_DATA 0x00000000
+#define DDRSS2_PHY_1009_DATA 0x00000000
+#define DDRSS2_PHY_1010_DATA 0x00000000
+#define DDRSS2_PHY_1011_DATA 0x00000000
+#define DDRSS2_PHY_1012_DATA 0x00000000
+#define DDRSS2_PHY_1013_DATA 0x00000000
+#define DDRSS2_PHY_1014_DATA 0x00000000
+#define DDRSS2_PHY_1015_DATA 0x00000000
+#define DDRSS2_PHY_1016_DATA 0x00000000
+#define DDRSS2_PHY_1017_DATA 0x00000000
+#define DDRSS2_PHY_1018_DATA 0x00000000
+#define DDRSS2_PHY_1019_DATA 0x00000000
+#define DDRSS2_PHY_1020_DATA 0x00000000
+#define DDRSS2_PHY_1021_DATA 0x00000000
+#define DDRSS2_PHY_1022_DATA 0x00000000
+#define DDRSS2_PHY_1023_DATA 0x00000000
+#define DDRSS2_PHY_1024_DATA 0x00000000
+#define DDRSS2_PHY_1025_DATA 0x00000000
+#define DDRSS2_PHY_1026_DATA 0x00000000
+#define DDRSS2_PHY_1027_DATA 0x00000000
+#define DDRSS2_PHY_1028_DATA 0x00000000
+#define DDRSS2_PHY_1029_DATA 0x00000100
+#define DDRSS2_PHY_1030_DATA 0x00000200
+#define DDRSS2_PHY_1031_DATA 0x00000000
+#define DDRSS2_PHY_1032_DATA 0x00000000
+#define DDRSS2_PHY_1033_DATA 0x00000000
+#define DDRSS2_PHY_1034_DATA 0x00000000
+#define DDRSS2_PHY_1035_DATA 0x00400000
+#define DDRSS2_PHY_1036_DATA 0x00000080
+#define DDRSS2_PHY_1037_DATA 0x00DCBA98
+#define DDRSS2_PHY_1038_DATA 0x03000000
+#define DDRSS2_PHY_1039_DATA 0x00200000
+#define DDRSS2_PHY_1040_DATA 0x00000000
+#define DDRSS2_PHY_1041_DATA 0x00000000
+#define DDRSS2_PHY_1042_DATA 0x00000000
+#define DDRSS2_PHY_1043_DATA 0x00000000
+#define DDRSS2_PHY_1044_DATA 0x00000000
+#define DDRSS2_PHY_1045_DATA 0x0000002A
+#define DDRSS2_PHY_1046_DATA 0x00000015
+#define DDRSS2_PHY_1047_DATA 0x00000015
+#define DDRSS2_PHY_1048_DATA 0x0000002A
+#define DDRSS2_PHY_1049_DATA 0x00000033
+#define DDRSS2_PHY_1050_DATA 0x0000000C
+#define DDRSS2_PHY_1051_DATA 0x0000000C
+#define DDRSS2_PHY_1052_DATA 0x00000033
+#define DDRSS2_PHY_1053_DATA 0x00543210
+#define DDRSS2_PHY_1054_DATA 0x003F0000
+#define DDRSS2_PHY_1055_DATA 0x000F013F
+#define DDRSS2_PHY_1056_DATA 0x20202003
+#define DDRSS2_PHY_1057_DATA 0x00202020
+#define DDRSS2_PHY_1058_DATA 0x20008008
+#define DDRSS2_PHY_1059_DATA 0x00000810
+#define DDRSS2_PHY_1060_DATA 0x00000F00
+#define DDRSS2_PHY_1061_DATA 0x00000000
+#define DDRSS2_PHY_1062_DATA 0x00000000
+#define DDRSS2_PHY_1063_DATA 0x00000000
+#define DDRSS2_PHY_1064_DATA 0x000305CC
+#define DDRSS2_PHY_1065_DATA 0x00030000
+#define DDRSS2_PHY_1066_DATA 0x00000300
+#define DDRSS2_PHY_1067_DATA 0x00000300
+#define DDRSS2_PHY_1068_DATA 0x00000300
+#define DDRSS2_PHY_1069_DATA 0x00000300
+#define DDRSS2_PHY_1070_DATA 0x00000300
+#define DDRSS2_PHY_1071_DATA 0x42080010
+#define DDRSS2_PHY_1072_DATA 0x0000803E
+#define DDRSS2_PHY_1073_DATA 0x00000001
+#define DDRSS2_PHY_1074_DATA 0x01000102
+#define DDRSS2_PHY_1075_DATA 0x00008000
+#define DDRSS2_PHY_1076_DATA 0x00000000
+#define DDRSS2_PHY_1077_DATA 0x00000000
+#define DDRSS2_PHY_1078_DATA 0x00000000
+#define DDRSS2_PHY_1079_DATA 0x00000000
+#define DDRSS2_PHY_1080_DATA 0x00000000
+#define DDRSS2_PHY_1081_DATA 0x00000000
+#define DDRSS2_PHY_1082_DATA 0x00000000
+#define DDRSS2_PHY_1083_DATA 0x00000000
+#define DDRSS2_PHY_1084_DATA 0x00000000
+#define DDRSS2_PHY_1085_DATA 0x00000000
+#define DDRSS2_PHY_1086_DATA 0x00000000
+#define DDRSS2_PHY_1087_DATA 0x00000000
+#define DDRSS2_PHY_1088_DATA 0x00000000
+#define DDRSS2_PHY_1089_DATA 0x00000000
+#define DDRSS2_PHY_1090_DATA 0x00000000
+#define DDRSS2_PHY_1091_DATA 0x00000000
+#define DDRSS2_PHY_1092_DATA 0x00000000
+#define DDRSS2_PHY_1093_DATA 0x00000000
+#define DDRSS2_PHY_1094_DATA 0x00000000
+#define DDRSS2_PHY_1095_DATA 0x00000000
+#define DDRSS2_PHY_1096_DATA 0x00000000
+#define DDRSS2_PHY_1097_DATA 0x00000000
+#define DDRSS2_PHY_1098_DATA 0x00000000
+#define DDRSS2_PHY_1099_DATA 0x00000000
+#define DDRSS2_PHY_1100_DATA 0x00000000
+#define DDRSS2_PHY_1101_DATA 0x00000000
+#define DDRSS2_PHY_1102_DATA 0x00000000
+#define DDRSS2_PHY_1103_DATA 0x00000000
+#define DDRSS2_PHY_1104_DATA 0x00000000
+#define DDRSS2_PHY_1105_DATA 0x00000000
+#define DDRSS2_PHY_1106_DATA 0x00000000
+#define DDRSS2_PHY_1107_DATA 0x00000000
+#define DDRSS2_PHY_1108_DATA 0x00000000
+#define DDRSS2_PHY_1109_DATA 0x00000000
+#define DDRSS2_PHY_1110_DATA 0x00000000
+#define DDRSS2_PHY_1111_DATA 0x00000000
+#define DDRSS2_PHY_1112_DATA 0x00000000
+#define DDRSS2_PHY_1113_DATA 0x00000000
+#define DDRSS2_PHY_1114_DATA 0x00000000
+#define DDRSS2_PHY_1115_DATA 0x00000000
+#define DDRSS2_PHY_1116_DATA 0x00000000
+#define DDRSS2_PHY_1117_DATA 0x00000000
+#define DDRSS2_PHY_1118_DATA 0x00000000
+#define DDRSS2_PHY_1119_DATA 0x00000000
+#define DDRSS2_PHY_1120_DATA 0x00000000
+#define DDRSS2_PHY_1121_DATA 0x00000000
+#define DDRSS2_PHY_1122_DATA 0x00000000
+#define DDRSS2_PHY_1123_DATA 0x00000000
+#define DDRSS2_PHY_1124_DATA 0x00000000
+#define DDRSS2_PHY_1125_DATA 0x00000000
+#define DDRSS2_PHY_1126_DATA 0x00000000
+#define DDRSS2_PHY_1127_DATA 0x00000000
+#define DDRSS2_PHY_1128_DATA 0x00000000
+#define DDRSS2_PHY_1129_DATA 0x00000000
+#define DDRSS2_PHY_1130_DATA 0x00000000
+#define DDRSS2_PHY_1131_DATA 0x00000000
+#define DDRSS2_PHY_1132_DATA 0x00000000
+#define DDRSS2_PHY_1133_DATA 0x00000000
+#define DDRSS2_PHY_1134_DATA 0x00000000
+#define DDRSS2_PHY_1135_DATA 0x00000000
+#define DDRSS2_PHY_1136_DATA 0x00000000
+#define DDRSS2_PHY_1137_DATA 0x00000000
+#define DDRSS2_PHY_1138_DATA 0x00000000
+#define DDRSS2_PHY_1139_DATA 0x00000000
+#define DDRSS2_PHY_1140_DATA 0x00000000
+#define DDRSS2_PHY_1141_DATA 0x00000000
+#define DDRSS2_PHY_1142_DATA 0x00000000
+#define DDRSS2_PHY_1143_DATA 0x00000000
+#define DDRSS2_PHY_1144_DATA 0x00000000
+#define DDRSS2_PHY_1145_DATA 0x00000000
+#define DDRSS2_PHY_1146_DATA 0x00000000
+#define DDRSS2_PHY_1147_DATA 0x00000000
+#define DDRSS2_PHY_1148_DATA 0x00000000
+#define DDRSS2_PHY_1149_DATA 0x00000000
+#define DDRSS2_PHY_1150_DATA 0x00000000
+#define DDRSS2_PHY_1151_DATA 0x00000000
+#define DDRSS2_PHY_1152_DATA 0x00000000
+#define DDRSS2_PHY_1153_DATA 0x00000000
+#define DDRSS2_PHY_1154_DATA 0x00000000
+#define DDRSS2_PHY_1155_DATA 0x00000000
+#define DDRSS2_PHY_1156_DATA 0x00000000
+#define DDRSS2_PHY_1157_DATA 0x00000000
+#define DDRSS2_PHY_1158_DATA 0x00000000
+#define DDRSS2_PHY_1159_DATA 0x00000000
+#define DDRSS2_PHY_1160_DATA 0x00000000
+#define DDRSS2_PHY_1161_DATA 0x00000000
+#define DDRSS2_PHY_1162_DATA 0x00000000
+#define DDRSS2_PHY_1163_DATA 0x00000000
+#define DDRSS2_PHY_1164_DATA 0x00000000
+#define DDRSS2_PHY_1165_DATA 0x00000000
+#define DDRSS2_PHY_1166_DATA 0x00000000
+#define DDRSS2_PHY_1167_DATA 0x00000000
+#define DDRSS2_PHY_1168_DATA 0x00000000
+#define DDRSS2_PHY_1169_DATA 0x00000000
+#define DDRSS2_PHY_1170_DATA 0x00000000
+#define DDRSS2_PHY_1171_DATA 0x00000000
+#define DDRSS2_PHY_1172_DATA 0x00000000
+#define DDRSS2_PHY_1173_DATA 0x00000000
+#define DDRSS2_PHY_1174_DATA 0x00000000
+#define DDRSS2_PHY_1175_DATA 0x00000000
+#define DDRSS2_PHY_1176_DATA 0x00000000
+#define DDRSS2_PHY_1177_DATA 0x00000000
+#define DDRSS2_PHY_1178_DATA 0x00000000
+#define DDRSS2_PHY_1179_DATA 0x00000000
+#define DDRSS2_PHY_1180_DATA 0x00000000
+#define DDRSS2_PHY_1181_DATA 0x00000000
+#define DDRSS2_PHY_1182_DATA 0x00000000
+#define DDRSS2_PHY_1183_DATA 0x00000000
+#define DDRSS2_PHY_1184_DATA 0x00000000
+#define DDRSS2_PHY_1185_DATA 0x00000000
+#define DDRSS2_PHY_1186_DATA 0x00000000
+#define DDRSS2_PHY_1187_DATA 0x00000000
+#define DDRSS2_PHY_1188_DATA 0x00000000
+#define DDRSS2_PHY_1189_DATA 0x00000000
+#define DDRSS2_PHY_1190_DATA 0x00000000
+#define DDRSS2_PHY_1191_DATA 0x00000000
+#define DDRSS2_PHY_1192_DATA 0x00000000
+#define DDRSS2_PHY_1193_DATA 0x00000000
+#define DDRSS2_PHY_1194_DATA 0x00000000
+#define DDRSS2_PHY_1195_DATA 0x00000000
+#define DDRSS2_PHY_1196_DATA 0x00000000
+#define DDRSS2_PHY_1197_DATA 0x00000000
+#define DDRSS2_PHY_1198_DATA 0x00000000
+#define DDRSS2_PHY_1199_DATA 0x00000000
+#define DDRSS2_PHY_1200_DATA 0x00000000
+#define DDRSS2_PHY_1201_DATA 0x00000000
+#define DDRSS2_PHY_1202_DATA 0x00000000
+#define DDRSS2_PHY_1203_DATA 0x00000000
+#define DDRSS2_PHY_1204_DATA 0x00000000
+#define DDRSS2_PHY_1205_DATA 0x00000000
+#define DDRSS2_PHY_1206_DATA 0x00000000
+#define DDRSS2_PHY_1207_DATA 0x00000000
+#define DDRSS2_PHY_1208_DATA 0x00000000
+#define DDRSS2_PHY_1209_DATA 0x00000000
+#define DDRSS2_PHY_1210_DATA 0x00000000
+#define DDRSS2_PHY_1211_DATA 0x00000000
+#define DDRSS2_PHY_1212_DATA 0x00000000
+#define DDRSS2_PHY_1213_DATA 0x00000000
+#define DDRSS2_PHY_1214_DATA 0x00000000
+#define DDRSS2_PHY_1215_DATA 0x00000000
+#define DDRSS2_PHY_1216_DATA 0x00000000
+#define DDRSS2_PHY_1217_DATA 0x00000000
+#define DDRSS2_PHY_1218_DATA 0x00000000
+#define DDRSS2_PHY_1219_DATA 0x00000000
+#define DDRSS2_PHY_1220_DATA 0x00000000
+#define DDRSS2_PHY_1221_DATA 0x00000000
+#define DDRSS2_PHY_1222_DATA 0x00000000
+#define DDRSS2_PHY_1223_DATA 0x00000000
+#define DDRSS2_PHY_1224_DATA 0x00000000
+#define DDRSS2_PHY_1225_DATA 0x00000000
+#define DDRSS2_PHY_1226_DATA 0x00000000
+#define DDRSS2_PHY_1227_DATA 0x00000000
+#define DDRSS2_PHY_1228_DATA 0x00000000
+#define DDRSS2_PHY_1229_DATA 0x00000000
+#define DDRSS2_PHY_1230_DATA 0x00000000
+#define DDRSS2_PHY_1231_DATA 0x00000000
+#define DDRSS2_PHY_1232_DATA 0x00000000
+#define DDRSS2_PHY_1233_DATA 0x00000000
+#define DDRSS2_PHY_1234_DATA 0x00000000
+#define DDRSS2_PHY_1235_DATA 0x00000000
+#define DDRSS2_PHY_1236_DATA 0x00000000
+#define DDRSS2_PHY_1237_DATA 0x00000000
+#define DDRSS2_PHY_1238_DATA 0x00000000
+#define DDRSS2_PHY_1239_DATA 0x00000000
+#define DDRSS2_PHY_1240_DATA 0x00000000
+#define DDRSS2_PHY_1241_DATA 0x00000000
+#define DDRSS2_PHY_1242_DATA 0x00000000
+#define DDRSS2_PHY_1243_DATA 0x00000000
+#define DDRSS2_PHY_1244_DATA 0x00000000
+#define DDRSS2_PHY_1245_DATA 0x00000000
+#define DDRSS2_PHY_1246_DATA 0x00000000
+#define DDRSS2_PHY_1247_DATA 0x00000000
+#define DDRSS2_PHY_1248_DATA 0x00000000
+#define DDRSS2_PHY_1249_DATA 0x00000000
+#define DDRSS2_PHY_1250_DATA 0x00000000
+#define DDRSS2_PHY_1251_DATA 0x00000000
+#define DDRSS2_PHY_1252_DATA 0x00000000
+#define DDRSS2_PHY_1253_DATA 0x00000000
+#define DDRSS2_PHY_1254_DATA 0x00000000
+#define DDRSS2_PHY_1255_DATA 0x00000000
+#define DDRSS2_PHY_1256_DATA 0x00000000
+#define DDRSS2_PHY_1257_DATA 0x00000000
+#define DDRSS2_PHY_1258_DATA 0x00000000
+#define DDRSS2_PHY_1259_DATA 0x00000000
+#define DDRSS2_PHY_1260_DATA 0x00000000
+#define DDRSS2_PHY_1261_DATA 0x00000000
+#define DDRSS2_PHY_1262_DATA 0x00000000
+#define DDRSS2_PHY_1263_DATA 0x00000000
+#define DDRSS2_PHY_1264_DATA 0x00000000
+#define DDRSS2_PHY_1265_DATA 0x00000000
+#define DDRSS2_PHY_1266_DATA 0x00000000
+#define DDRSS2_PHY_1267_DATA 0x00000000
+#define DDRSS2_PHY_1268_DATA 0x00000000
+#define DDRSS2_PHY_1269_DATA 0x00000000
+#define DDRSS2_PHY_1270_DATA 0x00000000
+#define DDRSS2_PHY_1271_DATA 0x00000000
+#define DDRSS2_PHY_1272_DATA 0x00000000
+#define DDRSS2_PHY_1273_DATA 0x00000000
+#define DDRSS2_PHY_1274_DATA 0x00000000
+#define DDRSS2_PHY_1275_DATA 0x00000000
+#define DDRSS2_PHY_1276_DATA 0x00000000
+#define DDRSS2_PHY_1277_DATA 0x00000000
+#define DDRSS2_PHY_1278_DATA 0x00000000
+#define DDRSS2_PHY_1279_DATA 0x00000000
+#define DDRSS2_PHY_1280_DATA 0x00000000
+#define DDRSS2_PHY_1281_DATA 0x00010100
+#define DDRSS2_PHY_1282_DATA 0x00000000
+#define DDRSS2_PHY_1283_DATA 0x00000000
+#define DDRSS2_PHY_1284_DATA 0x00050000
+#define DDRSS2_PHY_1285_DATA 0x04000000
+#define DDRSS2_PHY_1286_DATA 0x00000055
+#define DDRSS2_PHY_1287_DATA 0x00000000
+#define DDRSS2_PHY_1288_DATA 0x00000000
+#define DDRSS2_PHY_1289_DATA 0x00000000
+#define DDRSS2_PHY_1290_DATA 0x00000000
+#define DDRSS2_PHY_1291_DATA 0x00002001
+#define DDRSS2_PHY_1292_DATA 0x0000400F
+#define DDRSS2_PHY_1293_DATA 0x50020028
+#define DDRSS2_PHY_1294_DATA 0x01010000
+#define DDRSS2_PHY_1295_DATA 0x80080001
+#define DDRSS2_PHY_1296_DATA 0x10200000
+#define DDRSS2_PHY_1297_DATA 0x00000008
+#define DDRSS2_PHY_1298_DATA 0x00000000
+#define DDRSS2_PHY_1299_DATA 0x01090E00
+#define DDRSS2_PHY_1300_DATA 0x00040101
+#define DDRSS2_PHY_1301_DATA 0x0000010F
+#define DDRSS2_PHY_1302_DATA 0x00000000
+#define DDRSS2_PHY_1303_DATA 0x0000FFFF
+#define DDRSS2_PHY_1304_DATA 0x00000000
+#define DDRSS2_PHY_1305_DATA 0x01010000
+#define DDRSS2_PHY_1306_DATA 0x01080402
+#define DDRSS2_PHY_1307_DATA 0x01200F02
+#define DDRSS2_PHY_1308_DATA 0x00194280
+#define DDRSS2_PHY_1309_DATA 0x00000004
+#define DDRSS2_PHY_1310_DATA 0x00042000
+#define DDRSS2_PHY_1311_DATA 0x00000000
+#define DDRSS2_PHY_1312_DATA 0x00000000
+#define DDRSS2_PHY_1313_DATA 0x00000000
+#define DDRSS2_PHY_1314_DATA 0x00000000
+#define DDRSS2_PHY_1315_DATA 0x00000000
+#define DDRSS2_PHY_1316_DATA 0x00000000
+#define DDRSS2_PHY_1317_DATA 0x01000000
+#define DDRSS2_PHY_1318_DATA 0x00000705
+#define DDRSS2_PHY_1319_DATA 0x00000054
+#define DDRSS2_PHY_1320_DATA 0x00030820
+#define DDRSS2_PHY_1321_DATA 0x00010820
+#define DDRSS2_PHY_1322_DATA 0x00010820
+#define DDRSS2_PHY_1323_DATA 0x00010820
+#define DDRSS2_PHY_1324_DATA 0x00010820
+#define DDRSS2_PHY_1325_DATA 0x00010820
+#define DDRSS2_PHY_1326_DATA 0x00010820
+#define DDRSS2_PHY_1327_DATA 0x00010820
+#define DDRSS2_PHY_1328_DATA 0x00010820
+#define DDRSS2_PHY_1329_DATA 0x00000000
+#define DDRSS2_PHY_1330_DATA 0x00000074
+#define DDRSS2_PHY_1331_DATA 0x00000400
+#define DDRSS2_PHY_1332_DATA 0x00000108
+#define DDRSS2_PHY_1333_DATA 0x00000000
+#define DDRSS2_PHY_1334_DATA 0x00000000
+#define DDRSS2_PHY_1335_DATA 0x00000000
+#define DDRSS2_PHY_1336_DATA 0x00000000
+#define DDRSS2_PHY_1337_DATA 0x00000000
+#define DDRSS2_PHY_1338_DATA 0x03000000
+#define DDRSS2_PHY_1339_DATA 0x00000000
+#define DDRSS2_PHY_1340_DATA 0x00000000
+#define DDRSS2_PHY_1341_DATA 0x00000000
+#define DDRSS2_PHY_1342_DATA 0x04102006
+#define DDRSS2_PHY_1343_DATA 0x00041020
+#define DDRSS2_PHY_1344_DATA 0x01C98C98
+#define DDRSS2_PHY_1345_DATA 0x3F400000
+#define DDRSS2_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS2_PHY_1347_DATA 0x0000001F
+#define DDRSS2_PHY_1348_DATA 0x00000000
+#define DDRSS2_PHY_1349_DATA 0x00000000
+#define DDRSS2_PHY_1350_DATA 0x00000000
+#define DDRSS2_PHY_1351_DATA 0x00010000
+#define DDRSS2_PHY_1352_DATA 0x00000000
+#define DDRSS2_PHY_1353_DATA 0x00000000
+#define DDRSS2_PHY_1354_DATA 0x00000000
+#define DDRSS2_PHY_1355_DATA 0x00000000
+#define DDRSS2_PHY_1356_DATA 0x76543210
+#define DDRSS2_PHY_1357_DATA 0x00010198
+#define DDRSS2_PHY_1358_DATA 0x00000000
+#define DDRSS2_PHY_1359_DATA 0x00000000
+#define DDRSS2_PHY_1360_DATA 0x00000000
+#define DDRSS2_PHY_1361_DATA 0x00040700
+#define DDRSS2_PHY_1362_DATA 0x00000000
+#define DDRSS2_PHY_1363_DATA 0x00000000
+#define DDRSS2_PHY_1364_DATA 0x00000000
+#define DDRSS2_PHY_1365_DATA 0x00000000
+#define DDRSS2_PHY_1366_DATA 0x00000000
+#define DDRSS2_PHY_1367_DATA 0x00000002
+#define DDRSS2_PHY_1368_DATA 0x00000000
+#define DDRSS2_PHY_1369_DATA 0x00000000
+#define DDRSS2_PHY_1370_DATA 0x00000000
+#define DDRSS2_PHY_1371_DATA 0x00000000
+#define DDRSS2_PHY_1372_DATA 0x00000000
+#define DDRSS2_PHY_1373_DATA 0x00000000
+#define DDRSS2_PHY_1374_DATA 0x00080000
+#define DDRSS2_PHY_1375_DATA 0x000007FF
+#define DDRSS2_PHY_1376_DATA 0x00000000
+#define DDRSS2_PHY_1377_DATA 0x00000000
+#define DDRSS2_PHY_1378_DATA 0x00000000
+#define DDRSS2_PHY_1379_DATA 0x00000000
+#define DDRSS2_PHY_1380_DATA 0x00000000
+#define DDRSS2_PHY_1381_DATA 0x00000000
+#define DDRSS2_PHY_1382_DATA 0x000FFFFF
+#define DDRSS2_PHY_1383_DATA 0x000FFFFF
+#define DDRSS2_PHY_1384_DATA 0x0000FFFF
+#define DDRSS2_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS2_PHY_1386_DATA 0x030FFFFF
+#define DDRSS2_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS2_PHY_1388_DATA 0x0000FFFF
+#define DDRSS2_PHY_1389_DATA 0x00000000
+#define DDRSS2_PHY_1390_DATA 0x00000000
+#define DDRSS2_PHY_1391_DATA 0x00000000
+#define DDRSS2_PHY_1392_DATA 0x00000000
+#define DDRSS2_PHY_1393_DATA 0x0001F7C0
+#define DDRSS2_PHY_1394_DATA 0x00000003
+#define DDRSS2_PHY_1395_DATA 0x00000000
+#define DDRSS2_PHY_1396_DATA 0x00001142
+#define DDRSS2_PHY_1397_DATA 0x010207AB
+#define DDRSS2_PHY_1398_DATA 0x01000080
+#define DDRSS2_PHY_1399_DATA 0x03900390
+#define DDRSS2_PHY_1400_DATA 0x03900390
+#define DDRSS2_PHY_1401_DATA 0x00000390
+#define DDRSS2_PHY_1402_DATA 0x00000390
+#define DDRSS2_PHY_1403_DATA 0x00000390
+#define DDRSS2_PHY_1404_DATA 0x00000390
+#define DDRSS2_PHY_1405_DATA 0x00000005
+#define DDRSS2_PHY_1406_DATA 0x01813FCC
+#define DDRSS2_PHY_1407_DATA 0x000000CC
+#define DDRSS2_PHY_1408_DATA 0x0C000DFF
+#define DDRSS2_PHY_1409_DATA 0x30000DFF
+#define DDRSS2_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS2_PHY_1411_DATA 0x000100F0
+#define DDRSS2_PHY_1412_DATA 0x780DFFCC
+#define DDRSS2_PHY_1413_DATA 0x00007E31
+#define DDRSS2_PHY_1414_DATA 0x000CBF11
+#define DDRSS2_PHY_1415_DATA 0x01990010
+#define DDRSS2_PHY_1416_DATA 0x000CBF11
+#define DDRSS2_PHY_1417_DATA 0x01990010
+#define DDRSS2_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS2_PHY_1419_DATA 0x00EF00F0
+#define DDRSS2_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS2_PHY_1421_DATA 0x01FF00F0
+#define DDRSS2_PHY_1422_DATA 0x20040006
+
+#define DDRSS3_CTL_00_DATA 0x00000B00
+#define DDRSS3_CTL_01_DATA 0x00000000
+#define DDRSS3_CTL_02_DATA 0x00000000
+#define DDRSS3_CTL_03_DATA 0x00000000
+#define DDRSS3_CTL_04_DATA 0x00000000
+#define DDRSS3_CTL_05_DATA 0x00000000
+#define DDRSS3_CTL_06_DATA 0x00000000
+#define DDRSS3_CTL_07_DATA 0x00002AF8
+#define DDRSS3_CTL_08_DATA 0x0001ADAF
+#define DDRSS3_CTL_09_DATA 0x00000005
+#define DDRSS3_CTL_10_DATA 0x0000006E
+#define DDRSS3_CTL_11_DATA 0x000681C8
+#define DDRSS3_CTL_12_DATA 0x004111C9
+#define DDRSS3_CTL_13_DATA 0x00000005
+#define DDRSS3_CTL_14_DATA 0x000010A9
+#define DDRSS3_CTL_15_DATA 0x000681C8
+#define DDRSS3_CTL_16_DATA 0x004111C9
+#define DDRSS3_CTL_17_DATA 0x00000005
+#define DDRSS3_CTL_18_DATA 0x000010A9
+#define DDRSS3_CTL_19_DATA 0x01010000
+#define DDRSS3_CTL_20_DATA 0x02011001
+#define DDRSS3_CTL_21_DATA 0x02010000
+#define DDRSS3_CTL_22_DATA 0x00020100
+#define DDRSS3_CTL_23_DATA 0x0000000B
+#define DDRSS3_CTL_24_DATA 0x0000001C
+#define DDRSS3_CTL_25_DATA 0x00000000
+#define DDRSS3_CTL_26_DATA 0x00000000
+#define DDRSS3_CTL_27_DATA 0x03020200
+#define DDRSS3_CTL_28_DATA 0x00005656
+#define DDRSS3_CTL_29_DATA 0x00100000
+#define DDRSS3_CTL_30_DATA 0x00000000
+#define DDRSS3_CTL_31_DATA 0x00000000
+#define DDRSS3_CTL_32_DATA 0x00000000
+#define DDRSS3_CTL_33_DATA 0x00000000
+#define DDRSS3_CTL_34_DATA 0x040C0000
+#define DDRSS3_CTL_35_DATA 0x12481248
+#define DDRSS3_CTL_36_DATA 0x00050804
+#define DDRSS3_CTL_37_DATA 0x09040008
+#define DDRSS3_CTL_38_DATA 0x15000204
+#define DDRSS3_CTL_39_DATA 0x1760008B
+#define DDRSS3_CTL_40_DATA 0x1500422B
+#define DDRSS3_CTL_41_DATA 0x1760008B
+#define DDRSS3_CTL_42_DATA 0x2000422B
+#define DDRSS3_CTL_43_DATA 0x000A0A09
+#define DDRSS3_CTL_44_DATA 0x0400078A
+#define DDRSS3_CTL_45_DATA 0x1E161104
+#define DDRSS3_CTL_46_DATA 0x10012458
+#define DDRSS3_CTL_47_DATA 0x1E161110
+#define DDRSS3_CTL_48_DATA 0x10012458
+#define DDRSS3_CTL_49_DATA 0x02030410
+#define DDRSS3_CTL_50_DATA 0x2C040500
+#define DDRSS3_CTL_51_DATA 0x08292C29
+#define DDRSS3_CTL_52_DATA 0x14000E0A
+#define DDRSS3_CTL_53_DATA 0x04010A0A
+#define DDRSS3_CTL_54_DATA 0x01010004
+#define DDRSS3_CTL_55_DATA 0x04545408
+#define DDRSS3_CTL_56_DATA 0x04313104
+#define DDRSS3_CTL_57_DATA 0x00003131
+#define DDRSS3_CTL_58_DATA 0x00010100
+#define DDRSS3_CTL_59_DATA 0x03010000
+#define DDRSS3_CTL_60_DATA 0x00001508
+#define DDRSS3_CTL_61_DATA 0x000000CE
+#define DDRSS3_CTL_62_DATA 0x0000032B
+#define DDRSS3_CTL_63_DATA 0x00002073
+#define DDRSS3_CTL_64_DATA 0x0000032B
+#define DDRSS3_CTL_65_DATA 0x00002073
+#define DDRSS3_CTL_66_DATA 0x00000005
+#define DDRSS3_CTL_67_DATA 0x00050000
+#define DDRSS3_CTL_68_DATA 0x00CB0012
+#define DDRSS3_CTL_69_DATA 0x00CB0408
+#define DDRSS3_CTL_70_DATA 0x00400408
+#define DDRSS3_CTL_71_DATA 0x00120103
+#define DDRSS3_CTL_72_DATA 0x00100005
+#define DDRSS3_CTL_73_DATA 0x2F080010
+#define DDRSS3_CTL_74_DATA 0x0505012F
+#define DDRSS3_CTL_75_DATA 0x0401030A
+#define DDRSS3_CTL_76_DATA 0x041E100B
+#define DDRSS3_CTL_77_DATA 0x100B0401
+#define DDRSS3_CTL_78_DATA 0x0001041E
+#define DDRSS3_CTL_79_DATA 0x00160016
+#define DDRSS3_CTL_80_DATA 0x033B033B
+#define DDRSS3_CTL_81_DATA 0x033B033B
+#define DDRSS3_CTL_82_DATA 0x03050505
+#define DDRSS3_CTL_83_DATA 0x03010303
+#define DDRSS3_CTL_84_DATA 0x200B100B
+#define DDRSS3_CTL_85_DATA 0x04041004
+#define DDRSS3_CTL_86_DATA 0x200B100B
+#define DDRSS3_CTL_87_DATA 0x04041004
+#define DDRSS3_CTL_88_DATA 0x03010000
+#define DDRSS3_CTL_89_DATA 0x00010000
+#define DDRSS3_CTL_90_DATA 0x00000000
+#define DDRSS3_CTL_91_DATA 0x00000000
+#define DDRSS3_CTL_92_DATA 0x01000000
+#define DDRSS3_CTL_93_DATA 0x80104002
+#define DDRSS3_CTL_94_DATA 0x00000000
+#define DDRSS3_CTL_95_DATA 0x00040005
+#define DDRSS3_CTL_96_DATA 0x00000000
+#define DDRSS3_CTL_97_DATA 0x00050000
+#define DDRSS3_CTL_98_DATA 0x00000004
+#define DDRSS3_CTL_99_DATA 0x00000000
+#define DDRSS3_CTL_100_DATA 0x00040005
+#define DDRSS3_CTL_101_DATA 0x00000000
+#define DDRSS3_CTL_102_DATA 0x00003380
+#define DDRSS3_CTL_103_DATA 0x00003380
+#define DDRSS3_CTL_104_DATA 0x00003380
+#define DDRSS3_CTL_105_DATA 0x00003380
+#define DDRSS3_CTL_106_DATA 0x00003380
+#define DDRSS3_CTL_107_DATA 0x00000000
+#define DDRSS3_CTL_108_DATA 0x000005A2
+#define DDRSS3_CTL_109_DATA 0x00081CC0
+#define DDRSS3_CTL_110_DATA 0x00081CC0
+#define DDRSS3_CTL_111_DATA 0x00081CC0
+#define DDRSS3_CTL_112_DATA 0x00081CC0
+#define DDRSS3_CTL_113_DATA 0x00081CC0
+#define DDRSS3_CTL_114_DATA 0x00000000
+#define DDRSS3_CTL_115_DATA 0x0000E325
+#define DDRSS3_CTL_116_DATA 0x00081CC0
+#define DDRSS3_CTL_117_DATA 0x00081CC0
+#define DDRSS3_CTL_118_DATA 0x00081CC0
+#define DDRSS3_CTL_119_DATA 0x00081CC0
+#define DDRSS3_CTL_120_DATA 0x00081CC0
+#define DDRSS3_CTL_121_DATA 0x00000000
+#define DDRSS3_CTL_122_DATA 0x0000E325
+#define DDRSS3_CTL_123_DATA 0x00000000
+#define DDRSS3_CTL_124_DATA 0x00000000
+#define DDRSS3_CTL_125_DATA 0x00000000
+#define DDRSS3_CTL_126_DATA 0x00000000
+#define DDRSS3_CTL_127_DATA 0x00000000
+#define DDRSS3_CTL_128_DATA 0x00000000
+#define DDRSS3_CTL_129_DATA 0x00000000
+#define DDRSS3_CTL_130_DATA 0x00000000
+#define DDRSS3_CTL_131_DATA 0x0B030500
+#define DDRSS3_CTL_132_DATA 0x00040B04
+#define DDRSS3_CTL_133_DATA 0x0A090000
+#define DDRSS3_CTL_134_DATA 0x0A090701
+#define DDRSS3_CTL_135_DATA 0x0900000E
+#define DDRSS3_CTL_136_DATA 0x0907010A
+#define DDRSS3_CTL_137_DATA 0x00000E0A
+#define DDRSS3_CTL_138_DATA 0x07010A09
+#define DDRSS3_CTL_139_DATA 0x000E0A09
+#define DDRSS3_CTL_140_DATA 0x07000401
+#define DDRSS3_CTL_141_DATA 0x00000000
+#define DDRSS3_CTL_142_DATA 0x00000000
+#define DDRSS3_CTL_143_DATA 0x00000000
+#define DDRSS3_CTL_144_DATA 0x00000000
+#define DDRSS3_CTL_145_DATA 0x00000000
+#define DDRSS3_CTL_146_DATA 0x00000000
+#define DDRSS3_CTL_147_DATA 0x00000000
+#define DDRSS3_CTL_148_DATA 0x08080000
+#define DDRSS3_CTL_149_DATA 0x01000000
+#define DDRSS3_CTL_150_DATA 0x800000C0
+#define DDRSS3_CTL_151_DATA 0x800000C0
+#define DDRSS3_CTL_152_DATA 0x800000C0
+#define DDRSS3_CTL_153_DATA 0x00000000
+#define DDRSS3_CTL_154_DATA 0x00001500
+#define DDRSS3_CTL_155_DATA 0x00000000
+#define DDRSS3_CTL_156_DATA 0x00000001
+#define DDRSS3_CTL_157_DATA 0x00000002
+#define DDRSS3_CTL_158_DATA 0x0000100E
+#define DDRSS3_CTL_159_DATA 0x00000000
+#define DDRSS3_CTL_160_DATA 0x00000000
+#define DDRSS3_CTL_161_DATA 0x00000000
+#define DDRSS3_CTL_162_DATA 0x00000000
+#define DDRSS3_CTL_163_DATA 0x00000000
+#define DDRSS3_CTL_164_DATA 0x000B0000
+#define DDRSS3_CTL_165_DATA 0x000E0006
+#define DDRSS3_CTL_166_DATA 0x000E0404
+#define DDRSS3_CTL_167_DATA 0x00D601AB
+#define DDRSS3_CTL_168_DATA 0x10100216
+#define DDRSS3_CTL_169_DATA 0x01AB0216
+#define DDRSS3_CTL_170_DATA 0x021600D6
+#define DDRSS3_CTL_171_DATA 0x02161010
+#define DDRSS3_CTL_172_DATA 0x00000000
+#define DDRSS3_CTL_173_DATA 0x00000000
+#define DDRSS3_CTL_174_DATA 0x00000000
+#define DDRSS3_CTL_175_DATA 0x3FF40084
+#define DDRSS3_CTL_176_DATA 0x33003FF4
+#define DDRSS3_CTL_177_DATA 0x00003333
+#define DDRSS3_CTL_178_DATA 0x35000000
+#define DDRSS3_CTL_179_DATA 0x27270035
+#define DDRSS3_CTL_180_DATA 0x0F0F0000
+#define DDRSS3_CTL_181_DATA 0x16000000
+#define DDRSS3_CTL_182_DATA 0x00841616
+#define DDRSS3_CTL_183_DATA 0x3FF43FF4
+#define DDRSS3_CTL_184_DATA 0x33333300
+#define DDRSS3_CTL_185_DATA 0x00000000
+#define DDRSS3_CTL_186_DATA 0x00353500
+#define DDRSS3_CTL_187_DATA 0x00002727
+#define DDRSS3_CTL_188_DATA 0x00000F0F
+#define DDRSS3_CTL_189_DATA 0x16161600
+#define DDRSS3_CTL_190_DATA 0x00000020
+#define DDRSS3_CTL_191_DATA 0x00000000
+#define DDRSS3_CTL_192_DATA 0x00000001
+#define DDRSS3_CTL_193_DATA 0x00000000
+#define DDRSS3_CTL_194_DATA 0x01000000
+#define DDRSS3_CTL_195_DATA 0x00000001
+#define DDRSS3_CTL_196_DATA 0x00000000
+#define DDRSS3_CTL_197_DATA 0x00000000
+#define DDRSS3_CTL_198_DATA 0x00000000
+#define DDRSS3_CTL_199_DATA 0x00000000
+#define DDRSS3_CTL_200_DATA 0x00000000
+#define DDRSS3_CTL_201_DATA 0x00000000
+#define DDRSS3_CTL_202_DATA 0x00000000
+#define DDRSS3_CTL_203_DATA 0x00000000
+#define DDRSS3_CTL_204_DATA 0x00000000
+#define DDRSS3_CTL_205_DATA 0x00000000
+#define DDRSS3_CTL_206_DATA 0x02000000
+#define DDRSS3_CTL_207_DATA 0x01080101
+#define DDRSS3_CTL_208_DATA 0x00000000
+#define DDRSS3_CTL_209_DATA 0x00000000
+#define DDRSS3_CTL_210_DATA 0x00000000
+#define DDRSS3_CTL_211_DATA 0x00000000
+#define DDRSS3_CTL_212_DATA 0x00000000
+#define DDRSS3_CTL_213_DATA 0x00000000
+#define DDRSS3_CTL_214_DATA 0x00000000
+#define DDRSS3_CTL_215_DATA 0x00000000
+#define DDRSS3_CTL_216_DATA 0x00000000
+#define DDRSS3_CTL_217_DATA 0x00000000
+#define DDRSS3_CTL_218_DATA 0x00000000
+#define DDRSS3_CTL_219_DATA 0x00000000
+#define DDRSS3_CTL_220_DATA 0x00000000
+#define DDRSS3_CTL_221_DATA 0x00000000
+#define DDRSS3_CTL_222_DATA 0x00001000
+#define DDRSS3_CTL_223_DATA 0x006403E8
+#define DDRSS3_CTL_224_DATA 0x00000000
+#define DDRSS3_CTL_225_DATA 0x00000000
+#define DDRSS3_CTL_226_DATA 0x00000000
+#define DDRSS3_CTL_227_DATA 0x15110000
+#define DDRSS3_CTL_228_DATA 0x00040C18
+#define DDRSS3_CTL_229_DATA 0xF000C000
+#define DDRSS3_CTL_230_DATA 0x0000F000
+#define DDRSS3_CTL_231_DATA 0x00000000
+#define DDRSS3_CTL_232_DATA 0x00000000
+#define DDRSS3_CTL_233_DATA 0xC0000000
+#define DDRSS3_CTL_234_DATA 0xF000F000
+#define DDRSS3_CTL_235_DATA 0x00000000
+#define DDRSS3_CTL_236_DATA 0x00000000
+#define DDRSS3_CTL_237_DATA 0x00000000
+#define DDRSS3_CTL_238_DATA 0xF000C000
+#define DDRSS3_CTL_239_DATA 0x0000F000
+#define DDRSS3_CTL_240_DATA 0x00000000
+#define DDRSS3_CTL_241_DATA 0x00000000
+#define DDRSS3_CTL_242_DATA 0x00030000
+#define DDRSS3_CTL_243_DATA 0x00000000
+#define DDRSS3_CTL_244_DATA 0x00000000
+#define DDRSS3_CTL_245_DATA 0x00000000
+#define DDRSS3_CTL_246_DATA 0x00000000
+#define DDRSS3_CTL_247_DATA 0x00000000
+#define DDRSS3_CTL_248_DATA 0x00000000
+#define DDRSS3_CTL_249_DATA 0x00000000
+#define DDRSS3_CTL_250_DATA 0x00000000
+#define DDRSS3_CTL_251_DATA 0x00000000
+#define DDRSS3_CTL_252_DATA 0x00000000
+#define DDRSS3_CTL_253_DATA 0x00000000
+#define DDRSS3_CTL_254_DATA 0x00000000
+#define DDRSS3_CTL_255_DATA 0x00000000
+#define DDRSS3_CTL_256_DATA 0x00000000
+#define DDRSS3_CTL_257_DATA 0x01000200
+#define DDRSS3_CTL_258_DATA 0x00370040
+#define DDRSS3_CTL_259_DATA 0x00020008
+#define DDRSS3_CTL_260_DATA 0x00400100
+#define DDRSS3_CTL_261_DATA 0x00400855
+#define DDRSS3_CTL_262_DATA 0x01000200
+#define DDRSS3_CTL_263_DATA 0x08550040
+#define DDRSS3_CTL_264_DATA 0x00000040
+#define DDRSS3_CTL_265_DATA 0x006B0003
+#define DDRSS3_CTL_266_DATA 0x0100006B
+#define DDRSS3_CTL_267_DATA 0x03030303
+#define DDRSS3_CTL_268_DATA 0x00000000
+#define DDRSS3_CTL_269_DATA 0x00000202
+#define DDRSS3_CTL_270_DATA 0x00001FFF
+#define DDRSS3_CTL_271_DATA 0x3FFF2000
+#define DDRSS3_CTL_272_DATA 0x03FF0000
+#define DDRSS3_CTL_273_DATA 0x000103FF
+#define DDRSS3_CTL_274_DATA 0x0FFF0B00
+#define DDRSS3_CTL_275_DATA 0x01010001
+#define DDRSS3_CTL_276_DATA 0x01010101
+#define DDRSS3_CTL_277_DATA 0x01180101
+#define DDRSS3_CTL_278_DATA 0x00030000
+#define DDRSS3_CTL_279_DATA 0x00000000
+#define DDRSS3_CTL_280_DATA 0x00000000
+#define DDRSS3_CTL_281_DATA 0x00000000
+#define DDRSS3_CTL_282_DATA 0x00000000
+#define DDRSS3_CTL_283_DATA 0x00000000
+#define DDRSS3_CTL_284_DATA 0x00000000
+#define DDRSS3_CTL_285_DATA 0x00000000
+#define DDRSS3_CTL_286_DATA 0x00040101
+#define DDRSS3_CTL_287_DATA 0x04010100
+#define DDRSS3_CTL_288_DATA 0x00000000
+#define DDRSS3_CTL_289_DATA 0x00000000
+#define DDRSS3_CTL_290_DATA 0x03030300
+#define DDRSS3_CTL_291_DATA 0x00000001
+#define DDRSS3_CTL_292_DATA 0x00000000
+#define DDRSS3_CTL_293_DATA 0x00000000
+#define DDRSS3_CTL_294_DATA 0x00000000
+#define DDRSS3_CTL_295_DATA 0x00000000
+#define DDRSS3_CTL_296_DATA 0x00000000
+#define DDRSS3_CTL_297_DATA 0x00000000
+#define DDRSS3_CTL_298_DATA 0x00000000
+#define DDRSS3_CTL_299_DATA 0x00000000
+#define DDRSS3_CTL_300_DATA 0x00000000
+#define DDRSS3_CTL_301_DATA 0x00000000
+#define DDRSS3_CTL_302_DATA 0x00000000
+#define DDRSS3_CTL_303_DATA 0x00000000
+#define DDRSS3_CTL_304_DATA 0x00000000
+#define DDRSS3_CTL_305_DATA 0x00000000
+#define DDRSS3_CTL_306_DATA 0x00000000
+#define DDRSS3_CTL_307_DATA 0x00000000
+#define DDRSS3_CTL_308_DATA 0x00000000
+#define DDRSS3_CTL_309_DATA 0x00000000
+#define DDRSS3_CTL_310_DATA 0x00000000
+#define DDRSS3_CTL_311_DATA 0x00000000
+#define DDRSS3_CTL_312_DATA 0x00000000
+#define DDRSS3_CTL_313_DATA 0x01000000
+#define DDRSS3_CTL_314_DATA 0x00020201
+#define DDRSS3_CTL_315_DATA 0x01000101
+#define DDRSS3_CTL_316_DATA 0x01010001
+#define DDRSS3_CTL_317_DATA 0x00010101
+#define DDRSS3_CTL_318_DATA 0x050A0A03
+#define DDRSS3_CTL_319_DATA 0x10081F1F
+#define DDRSS3_CTL_320_DATA 0x00090310
+#define DDRSS3_CTL_321_DATA 0x0B0C030F
+#define DDRSS3_CTL_322_DATA 0x0B0C0306
+#define DDRSS3_CTL_323_DATA 0x0C090006
+#define DDRSS3_CTL_324_DATA 0x0100000C
+#define DDRSS3_CTL_325_DATA 0x08040801
+#define DDRSS3_CTL_326_DATA 0x00000004
+#define DDRSS3_CTL_327_DATA 0x00000000
+#define DDRSS3_CTL_328_DATA 0x00010000
+#define DDRSS3_CTL_329_DATA 0x00280D00
+#define DDRSS3_CTL_330_DATA 0x00000001
+#define DDRSS3_CTL_331_DATA 0x00030001
+#define DDRSS3_CTL_332_DATA 0x00000000
+#define DDRSS3_CTL_333_DATA 0x00000000
+#define DDRSS3_CTL_334_DATA 0x00000000
+#define DDRSS3_CTL_335_DATA 0x00000000
+#define DDRSS3_CTL_336_DATA 0x00000000
+#define DDRSS3_CTL_337_DATA 0x00000000
+#define DDRSS3_CTL_338_DATA 0x00000000
+#define DDRSS3_CTL_339_DATA 0x00000000
+#define DDRSS3_CTL_340_DATA 0x01000000
+#define DDRSS3_CTL_341_DATA 0x00000001
+#define DDRSS3_CTL_342_DATA 0x00010100
+#define DDRSS3_CTL_343_DATA 0x03030000
+#define DDRSS3_CTL_344_DATA 0x00000000
+#define DDRSS3_CTL_345_DATA 0x00000000
+#define DDRSS3_CTL_346_DATA 0x00000000
+#define DDRSS3_CTL_347_DATA 0x00000000
+#define DDRSS3_CTL_348_DATA 0x00000000
+#define DDRSS3_CTL_349_DATA 0x00000000
+#define DDRSS3_CTL_350_DATA 0x00000000
+#define DDRSS3_CTL_351_DATA 0x00000000
+#define DDRSS3_CTL_352_DATA 0x00000000
+#define DDRSS3_CTL_353_DATA 0x00000000
+#define DDRSS3_CTL_354_DATA 0x00000000
+#define DDRSS3_CTL_355_DATA 0x00000000
+#define DDRSS3_CTL_356_DATA 0x00000000
+#define DDRSS3_CTL_357_DATA 0x00000000
+#define DDRSS3_CTL_358_DATA 0x00000000
+#define DDRSS3_CTL_359_DATA 0x00000000
+#define DDRSS3_CTL_360_DATA 0x000556AA
+#define DDRSS3_CTL_361_DATA 0x000AAAAA
+#define DDRSS3_CTL_362_DATA 0x000AA955
+#define DDRSS3_CTL_363_DATA 0x00055555
+#define DDRSS3_CTL_364_DATA 0x000B3133
+#define DDRSS3_CTL_365_DATA 0x0004CD33
+#define DDRSS3_CTL_366_DATA 0x0004CECC
+#define DDRSS3_CTL_367_DATA 0x000B32CC
+#define DDRSS3_CTL_368_DATA 0x00010300
+#define DDRSS3_CTL_369_DATA 0x03000100
+#define DDRSS3_CTL_370_DATA 0x00000000
+#define DDRSS3_CTL_371_DATA 0x00000000
+#define DDRSS3_CTL_372_DATA 0x00000000
+#define DDRSS3_CTL_373_DATA 0x00000000
+#define DDRSS3_CTL_374_DATA 0x00000000
+#define DDRSS3_CTL_375_DATA 0x00000000
+#define DDRSS3_CTL_376_DATA 0x00000000
+#define DDRSS3_CTL_377_DATA 0x00010000
+#define DDRSS3_CTL_378_DATA 0x00000404
+#define DDRSS3_CTL_379_DATA 0x00000000
+#define DDRSS3_CTL_380_DATA 0x00000000
+#define DDRSS3_CTL_381_DATA 0x00000000
+#define DDRSS3_CTL_382_DATA 0x00000000
+#define DDRSS3_CTL_383_DATA 0x00000000
+#define DDRSS3_CTL_384_DATA 0x00000000
+#define DDRSS3_CTL_385_DATA 0x00000000
+#define DDRSS3_CTL_386_DATA 0x00000000
+#define DDRSS3_CTL_387_DATA 0x3A3A1B00
+#define DDRSS3_CTL_388_DATA 0x000A0000
+#define DDRSS3_CTL_389_DATA 0x0000019C
+#define DDRSS3_CTL_390_DATA 0x00000200
+#define DDRSS3_CTL_391_DATA 0x00000200
+#define DDRSS3_CTL_392_DATA 0x00000200
+#define DDRSS3_CTL_393_DATA 0x00000200
+#define DDRSS3_CTL_394_DATA 0x000004D4
+#define DDRSS3_CTL_395_DATA 0x00001018
+#define DDRSS3_CTL_396_DATA 0x00000204
+#define DDRSS3_CTL_397_DATA 0x000040E6
+#define DDRSS3_CTL_398_DATA 0x00000200
+#define DDRSS3_CTL_399_DATA 0x00000200
+#define DDRSS3_CTL_400_DATA 0x00000200
+#define DDRSS3_CTL_401_DATA 0x00000200
+#define DDRSS3_CTL_402_DATA 0x0000C2B2
+#define DDRSS3_CTL_403_DATA 0x000288FC
+#define DDRSS3_CTL_404_DATA 0x00000E15
+#define DDRSS3_CTL_405_DATA 0x000040E6
+#define DDRSS3_CTL_406_DATA 0x00000200
+#define DDRSS3_CTL_407_DATA 0x00000200
+#define DDRSS3_CTL_408_DATA 0x00000200
+#define DDRSS3_CTL_409_DATA 0x00000200
+#define DDRSS3_CTL_410_DATA 0x0000C2B2
+#define DDRSS3_CTL_411_DATA 0x000288FC
+#define DDRSS3_CTL_412_DATA 0x02020E15
+#define DDRSS3_CTL_413_DATA 0x03030202
+#define DDRSS3_CTL_414_DATA 0x00000022
+#define DDRSS3_CTL_415_DATA 0x00000000
+#define DDRSS3_CTL_416_DATA 0x00000000
+#define DDRSS3_CTL_417_DATA 0x00001403
+#define DDRSS3_CTL_418_DATA 0x000007D0
+#define DDRSS3_CTL_419_DATA 0x00000000
+#define DDRSS3_CTL_420_DATA 0x00000000
+#define DDRSS3_CTL_421_DATA 0x00030000
+#define DDRSS3_CTL_422_DATA 0x0007001F
+#define DDRSS3_CTL_423_DATA 0x001B0033
+#define DDRSS3_CTL_424_DATA 0x001B0033
+#define DDRSS3_CTL_425_DATA 0x00000000
+#define DDRSS3_CTL_426_DATA 0x00000000
+#define DDRSS3_CTL_427_DATA 0x02000000
+#define DDRSS3_CTL_428_DATA 0x01000404
+#define DDRSS3_CTL_429_DATA 0x0B1E0B1E
+#define DDRSS3_CTL_430_DATA 0x00000105
+#define DDRSS3_CTL_431_DATA 0x00010101
+#define DDRSS3_CTL_432_DATA 0x00010101
+#define DDRSS3_CTL_433_DATA 0x00010001
+#define DDRSS3_CTL_434_DATA 0x00000101
+#define DDRSS3_CTL_435_DATA 0x02000201
+#define DDRSS3_CTL_436_DATA 0x02010000
+#define DDRSS3_CTL_437_DATA 0x00000200
+#define DDRSS3_CTL_438_DATA 0x28060000
+#define DDRSS3_CTL_439_DATA 0x00000128
+#define DDRSS3_CTL_440_DATA 0xFFFFFFFF
+#define DDRSS3_CTL_441_DATA 0xFFFFFFFF
+#define DDRSS3_CTL_442_DATA 0x00000000
+#define DDRSS3_CTL_443_DATA 0x00000000
+#define DDRSS3_CTL_444_DATA 0x00000000
+#define DDRSS3_CTL_445_DATA 0x00000000
+#define DDRSS3_CTL_446_DATA 0x00000000
+#define DDRSS3_CTL_447_DATA 0x00000000
+#define DDRSS3_CTL_448_DATA 0x00000000
+#define DDRSS3_CTL_449_DATA 0x00000000
+#define DDRSS3_CTL_450_DATA 0x00000000
+#define DDRSS3_CTL_451_DATA 0x00000000
+#define DDRSS3_CTL_452_DATA 0x00000000
+#define DDRSS3_CTL_453_DATA 0x00000000
+#define DDRSS3_CTL_454_DATA 0x00000000
+#define DDRSS3_CTL_455_DATA 0x00000000
+#define DDRSS3_CTL_456_DATA 0x00000000
+#define DDRSS3_CTL_457_DATA 0x00000000
+#define DDRSS3_CTL_458_DATA 0x00000000
+
+#define DDRSS3_PI_00_DATA 0x00000B00
+#define DDRSS3_PI_01_DATA 0x00000000
+#define DDRSS3_PI_02_DATA 0x00000000
+#define DDRSS3_PI_03_DATA 0x00000000
+#define DDRSS3_PI_04_DATA 0x00000000
+#define DDRSS3_PI_05_DATA 0x00000101
+#define DDRSS3_PI_06_DATA 0x00640000
+#define DDRSS3_PI_07_DATA 0x00000001
+#define DDRSS3_PI_08_DATA 0x00000000
+#define DDRSS3_PI_09_DATA 0x00000000
+#define DDRSS3_PI_10_DATA 0x00000000
+#define DDRSS3_PI_11_DATA 0x00000000
+#define DDRSS3_PI_12_DATA 0x00000007
+#define DDRSS3_PI_13_DATA 0x00010002
+#define DDRSS3_PI_14_DATA 0x0800000F
+#define DDRSS3_PI_15_DATA 0x00000103
+#define DDRSS3_PI_16_DATA 0x00000005
+#define DDRSS3_PI_17_DATA 0x00000000
+#define DDRSS3_PI_18_DATA 0x00000000
+#define DDRSS3_PI_19_DATA 0x00000000
+#define DDRSS3_PI_20_DATA 0x00000000
+#define DDRSS3_PI_21_DATA 0x00000000
+#define DDRSS3_PI_22_DATA 0x00000000
+#define DDRSS3_PI_23_DATA 0x00000000
+#define DDRSS3_PI_24_DATA 0x00000000
+#define DDRSS3_PI_25_DATA 0x00000000
+#define DDRSS3_PI_26_DATA 0x00010100
+#define DDRSS3_PI_27_DATA 0x00280A00
+#define DDRSS3_PI_28_DATA 0x00000000
+#define DDRSS3_PI_29_DATA 0x0F000000
+#define DDRSS3_PI_30_DATA 0x00003200
+#define DDRSS3_PI_31_DATA 0x00000000
+#define DDRSS3_PI_32_DATA 0x00000000
+#define DDRSS3_PI_33_DATA 0x01010102
+#define DDRSS3_PI_34_DATA 0x00000000
+#define DDRSS3_PI_35_DATA 0x000000AA
+#define DDRSS3_PI_36_DATA 0x00000055
+#define DDRSS3_PI_37_DATA 0x000000B5
+#define DDRSS3_PI_38_DATA 0x0000004A
+#define DDRSS3_PI_39_DATA 0x00000056
+#define DDRSS3_PI_40_DATA 0x000000A9
+#define DDRSS3_PI_41_DATA 0x000000A9
+#define DDRSS3_PI_42_DATA 0x000000B5
+#define DDRSS3_PI_43_DATA 0x00000000
+#define DDRSS3_PI_44_DATA 0x00000000
+#define DDRSS3_PI_45_DATA 0x000F0F00
+#define DDRSS3_PI_46_DATA 0x0000001B
+#define DDRSS3_PI_47_DATA 0x000007D0
+#define DDRSS3_PI_48_DATA 0x00000300
+#define DDRSS3_PI_49_DATA 0x00000000
+#define DDRSS3_PI_50_DATA 0x00000000
+#define DDRSS3_PI_51_DATA 0x01000000
+#define DDRSS3_PI_52_DATA 0x00010101
+#define DDRSS3_PI_53_DATA 0x00000000
+#define DDRSS3_PI_54_DATA 0x00030000
+#define DDRSS3_PI_55_DATA 0x0F000000
+#define DDRSS3_PI_56_DATA 0x00000017
+#define DDRSS3_PI_57_DATA 0x00000000
+#define DDRSS3_PI_58_DATA 0x00000000
+#define DDRSS3_PI_59_DATA 0x00000000
+#define DDRSS3_PI_60_DATA 0x0A0A140A
+#define DDRSS3_PI_61_DATA 0x10020101
+#define DDRSS3_PI_62_DATA 0x00020805
+#define DDRSS3_PI_63_DATA 0x01000404
+#define DDRSS3_PI_64_DATA 0x00000000
+#define DDRSS3_PI_65_DATA 0x00000000
+#define DDRSS3_PI_66_DATA 0x00000100
+#define DDRSS3_PI_67_DATA 0x0001010F
+#define DDRSS3_PI_68_DATA 0x00340000
+#define DDRSS3_PI_69_DATA 0x00000000
+#define DDRSS3_PI_70_DATA 0x00000000
+#define DDRSS3_PI_71_DATA 0x0000FFFF
+#define DDRSS3_PI_72_DATA 0x00000000
+#define DDRSS3_PI_73_DATA 0x00080000
+#define DDRSS3_PI_74_DATA 0x02000200
+#define DDRSS3_PI_75_DATA 0x01000100
+#define DDRSS3_PI_76_DATA 0x01000000
+#define DDRSS3_PI_77_DATA 0x02000200
+#define DDRSS3_PI_78_DATA 0x00000200
+#define DDRSS3_PI_79_DATA 0x00000000
+#define DDRSS3_PI_80_DATA 0x00000000
+#define DDRSS3_PI_81_DATA 0x00000000
+#define DDRSS3_PI_82_DATA 0x00000000
+#define DDRSS3_PI_83_DATA 0x00000000
+#define DDRSS3_PI_84_DATA 0x00000000
+#define DDRSS3_PI_85_DATA 0x00000000
+#define DDRSS3_PI_86_DATA 0x00000000
+#define DDRSS3_PI_87_DATA 0x00000000
+#define DDRSS3_PI_88_DATA 0x00000000
+#define DDRSS3_PI_89_DATA 0x00000000
+#define DDRSS3_PI_90_DATA 0x00000000
+#define DDRSS3_PI_91_DATA 0x00000400
+#define DDRSS3_PI_92_DATA 0x02010000
+#define DDRSS3_PI_93_DATA 0x00080003
+#define DDRSS3_PI_94_DATA 0x00080000
+#define DDRSS3_PI_95_DATA 0x00000001
+#define DDRSS3_PI_96_DATA 0x00000000
+#define DDRSS3_PI_97_DATA 0x0000AA00
+#define DDRSS3_PI_98_DATA 0x00000000
+#define DDRSS3_PI_99_DATA 0x00000000
+#define DDRSS3_PI_100_DATA 0x00010000
+#define DDRSS3_PI_101_DATA 0x00000000
+#define DDRSS3_PI_102_DATA 0x00000000
+#define DDRSS3_PI_103_DATA 0x00000000
+#define DDRSS3_PI_104_DATA 0x00000000
+#define DDRSS3_PI_105_DATA 0x00000000
+#define DDRSS3_PI_106_DATA 0x00000000
+#define DDRSS3_PI_107_DATA 0x00000000
+#define DDRSS3_PI_108_DATA 0x00000000
+#define DDRSS3_PI_109_DATA 0x00000000
+#define DDRSS3_PI_110_DATA 0x00000000
+#define DDRSS3_PI_111_DATA 0x00000000
+#define DDRSS3_PI_112_DATA 0x00000000
+#define DDRSS3_PI_113_DATA 0x00000000
+#define DDRSS3_PI_114_DATA 0x00000000
+#define DDRSS3_PI_115_DATA 0x00000000
+#define DDRSS3_PI_116_DATA 0x00000000
+#define DDRSS3_PI_117_DATA 0x00000000
+#define DDRSS3_PI_118_DATA 0x00000000
+#define DDRSS3_PI_119_DATA 0x00000000
+#define DDRSS3_PI_120_DATA 0x00000000
+#define DDRSS3_PI_121_DATA 0x00000000
+#define DDRSS3_PI_122_DATA 0x00000000
+#define DDRSS3_PI_123_DATA 0x00000000
+#define DDRSS3_PI_124_DATA 0x00000000
+#define DDRSS3_PI_125_DATA 0x00000008
+#define DDRSS3_PI_126_DATA 0x00000000
+#define DDRSS3_PI_127_DATA 0x00000000
+#define DDRSS3_PI_128_DATA 0x00000000
+#define DDRSS3_PI_129_DATA 0x00000000
+#define DDRSS3_PI_130_DATA 0x00000000
+#define DDRSS3_PI_131_DATA 0x00000000
+#define DDRSS3_PI_132_DATA 0x00000000
+#define DDRSS3_PI_133_DATA 0x00000000
+#define DDRSS3_PI_134_DATA 0x00000002
+#define DDRSS3_PI_135_DATA 0x00000000
+#define DDRSS3_PI_136_DATA 0x00000000
+#define DDRSS3_PI_137_DATA 0x0000000A
+#define DDRSS3_PI_138_DATA 0x00000019
+#define DDRSS3_PI_139_DATA 0x00000100
+#define DDRSS3_PI_140_DATA 0x00000000
+#define DDRSS3_PI_141_DATA 0x00000000
+#define DDRSS3_PI_142_DATA 0x00000000
+#define DDRSS3_PI_143_DATA 0x00000000
+#define DDRSS3_PI_144_DATA 0x01000000
+#define DDRSS3_PI_145_DATA 0x00010003
+#define DDRSS3_PI_146_DATA 0x02000101
+#define DDRSS3_PI_147_DATA 0x01030001
+#define DDRSS3_PI_148_DATA 0x00010400
+#define DDRSS3_PI_149_DATA 0x06000105
+#define DDRSS3_PI_150_DATA 0x01070001
+#define DDRSS3_PI_151_DATA 0x00000000
+#define DDRSS3_PI_152_DATA 0x00000000
+#define DDRSS3_PI_153_DATA 0x00000000
+#define DDRSS3_PI_154_DATA 0x00010001
+#define DDRSS3_PI_155_DATA 0x00000000
+#define DDRSS3_PI_156_DATA 0x00000000
+#define DDRSS3_PI_157_DATA 0x00000000
+#define DDRSS3_PI_158_DATA 0x00000000
+#define DDRSS3_PI_159_DATA 0x00000401
+#define DDRSS3_PI_160_DATA 0x00000000
+#define DDRSS3_PI_161_DATA 0x00010000
+#define DDRSS3_PI_162_DATA 0x00000000
+#define DDRSS3_PI_163_DATA 0x2B2B0200
+#define DDRSS3_PI_164_DATA 0x00000034
+#define DDRSS3_PI_165_DATA 0x00000064
+#define DDRSS3_PI_166_DATA 0x00020064
+#define DDRSS3_PI_167_DATA 0x02000200
+#define DDRSS3_PI_168_DATA 0x48120C04
+#define DDRSS3_PI_169_DATA 0x00154812
+#define DDRSS3_PI_170_DATA 0x000000CE
+#define DDRSS3_PI_171_DATA 0x0000032B
+#define DDRSS3_PI_172_DATA 0x00002073
+#define DDRSS3_PI_173_DATA 0x0000032B
+#define DDRSS3_PI_174_DATA 0x04002073
+#define DDRSS3_PI_175_DATA 0x01010404
+#define DDRSS3_PI_176_DATA 0x00001501
+#define DDRSS3_PI_177_DATA 0x00150015
+#define DDRSS3_PI_178_DATA 0x01000100
+#define DDRSS3_PI_179_DATA 0x00000100
+#define DDRSS3_PI_180_DATA 0x00000000
+#define DDRSS3_PI_181_DATA 0x01010101
+#define DDRSS3_PI_182_DATA 0x00000101
+#define DDRSS3_PI_183_DATA 0x00000000
+#define DDRSS3_PI_184_DATA 0x00000000
+#define DDRSS3_PI_185_DATA 0x15040000
+#define DDRSS3_PI_186_DATA 0x0E0E0215
+#define DDRSS3_PI_187_DATA 0x00040402
+#define DDRSS3_PI_188_DATA 0x000D0035
+#define DDRSS3_PI_189_DATA 0x00218049
+#define DDRSS3_PI_190_DATA 0x00218049
+#define DDRSS3_PI_191_DATA 0x01010101
+#define DDRSS3_PI_192_DATA 0x0004000E
+#define DDRSS3_PI_193_DATA 0x00040216
+#define DDRSS3_PI_194_DATA 0x01000216
+#define DDRSS3_PI_195_DATA 0x000F000F
+#define DDRSS3_PI_196_DATA 0x02170100
+#define DDRSS3_PI_197_DATA 0x01000217
+#define DDRSS3_PI_198_DATA 0x02170217
+#define DDRSS3_PI_199_DATA 0x32103200
+#define DDRSS3_PI_200_DATA 0x01013210
+#define DDRSS3_PI_201_DATA 0x0A070601
+#define DDRSS3_PI_202_DATA 0x1F130A0D
+#define DDRSS3_PI_203_DATA 0x1F130A14
+#define DDRSS3_PI_204_DATA 0x0000C014
+#define DDRSS3_PI_205_DATA 0x00C01000
+#define DDRSS3_PI_206_DATA 0x00C01000
+#define DDRSS3_PI_207_DATA 0x00021000
+#define DDRSS3_PI_208_DATA 0x0024000E
+#define DDRSS3_PI_209_DATA 0x00240216
+#define DDRSS3_PI_210_DATA 0x00110216
+#define DDRSS3_PI_211_DATA 0x32000056
+#define DDRSS3_PI_212_DATA 0x00000301
+#define DDRSS3_PI_213_DATA 0x005B0036
+#define DDRSS3_PI_214_DATA 0x03013212
+#define DDRSS3_PI_215_DATA 0x00003600
+#define DDRSS3_PI_216_DATA 0x3212005B
+#define DDRSS3_PI_217_DATA 0x09000301
+#define DDRSS3_PI_218_DATA 0x04010504
+#define DDRSS3_PI_219_DATA 0x040006C9
+#define DDRSS3_PI_220_DATA 0x0A032001
+#define DDRSS3_PI_221_DATA 0x2C31110A
+#define DDRSS3_PI_222_DATA 0x00002918
+#define DDRSS3_PI_223_DATA 0x6001071C
+#define DDRSS3_PI_224_DATA 0x1E202008
+#define DDRSS3_PI_225_DATA 0x2C311116
+#define DDRSS3_PI_226_DATA 0x00002918
+#define DDRSS3_PI_227_DATA 0x6001071C
+#define DDRSS3_PI_228_DATA 0x1E202008
+#define DDRSS3_PI_229_DATA 0x00019C16
+#define DDRSS3_PI_230_DATA 0x00001018
+#define DDRSS3_PI_231_DATA 0x000040E6
+#define DDRSS3_PI_232_DATA 0x000288FC
+#define DDRSS3_PI_233_DATA 0x000040E6
+#define DDRSS3_PI_234_DATA 0x000288FC
+#define DDRSS3_PI_235_DATA 0x033B0016
+#define DDRSS3_PI_236_DATA 0x0303033B
+#define DDRSS3_PI_237_DATA 0x002AF803
+#define DDRSS3_PI_238_DATA 0x0001ADAF
+#define DDRSS3_PI_239_DATA 0x00000005
+#define DDRSS3_PI_240_DATA 0x0000006E
+#define DDRSS3_PI_241_DATA 0x00000016
+#define DDRSS3_PI_242_DATA 0x000681C8
+#define DDRSS3_PI_243_DATA 0x0001ADAF
+#define DDRSS3_PI_244_DATA 0x00000005
+#define DDRSS3_PI_245_DATA 0x000010A9
+#define DDRSS3_PI_246_DATA 0x0000033B
+#define DDRSS3_PI_247_DATA 0x000681C8
+#define DDRSS3_PI_248_DATA 0x0001ADAF
+#define DDRSS3_PI_249_DATA 0x00000005
+#define DDRSS3_PI_250_DATA 0x000010A9
+#define DDRSS3_PI_251_DATA 0x0100033B
+#define DDRSS3_PI_252_DATA 0x00370040
+#define DDRSS3_PI_253_DATA 0x00010008
+#define DDRSS3_PI_254_DATA 0x08550040
+#define DDRSS3_PI_255_DATA 0x00010040
+#define DDRSS3_PI_256_DATA 0x08550040
+#define DDRSS3_PI_257_DATA 0x00000340
+#define DDRSS3_PI_258_DATA 0x006B006B
+#define DDRSS3_PI_259_DATA 0x08040404
+#define DDRSS3_PI_260_DATA 0x00000055
+#define DDRSS3_PI_261_DATA 0x55083C5A
+#define DDRSS3_PI_262_DATA 0x5A000000
+#define DDRSS3_PI_263_DATA 0x0055083C
+#define DDRSS3_PI_264_DATA 0x3C5A0000
+#define DDRSS3_PI_265_DATA 0x00005508
+#define DDRSS3_PI_266_DATA 0x0C3C5A00
+#define DDRSS3_PI_267_DATA 0x080F0E0D
+#define DDRSS3_PI_268_DATA 0x000B0A09
+#define DDRSS3_PI_269_DATA 0x00030201
+#define DDRSS3_PI_270_DATA 0x01000000
+#define DDRSS3_PI_271_DATA 0x04020201
+#define DDRSS3_PI_272_DATA 0x00080804
+#define DDRSS3_PI_273_DATA 0x00000000
+#define DDRSS3_PI_274_DATA 0x00000000
+#define DDRSS3_PI_275_DATA 0x00330084
+#define DDRSS3_PI_276_DATA 0x00160000
+#define DDRSS3_PI_277_DATA 0x35333FF4
+#define DDRSS3_PI_278_DATA 0x00160F27
+#define DDRSS3_PI_279_DATA 0x35333FF4
+#define DDRSS3_PI_280_DATA 0x00160F27
+#define DDRSS3_PI_281_DATA 0x00330084
+#define DDRSS3_PI_282_DATA 0x00160000
+#define DDRSS3_PI_283_DATA 0x35333FF4
+#define DDRSS3_PI_284_DATA 0x00160F27
+#define DDRSS3_PI_285_DATA 0x35333FF4
+#define DDRSS3_PI_286_DATA 0x00160F27
+#define DDRSS3_PI_287_DATA 0x00330084
+#define DDRSS3_PI_288_DATA 0x00160000
+#define DDRSS3_PI_289_DATA 0x35333FF4
+#define DDRSS3_PI_290_DATA 0x00160F27
+#define DDRSS3_PI_291_DATA 0x35333FF4
+#define DDRSS3_PI_292_DATA 0x00160F27
+#define DDRSS3_PI_293_DATA 0x00330084
+#define DDRSS3_PI_294_DATA 0x00160000
+#define DDRSS3_PI_295_DATA 0x35333FF4
+#define DDRSS3_PI_296_DATA 0x00160F27
+#define DDRSS3_PI_297_DATA 0x35333FF4
+#define DDRSS3_PI_298_DATA 0x00160F27
+#define DDRSS3_PI_299_DATA 0x00000000
+
+#define DDRSS3_PHY_00_DATA 0x000004F0
+#define DDRSS3_PHY_01_DATA 0x00000000
+#define DDRSS3_PHY_02_DATA 0x00030200
+#define DDRSS3_PHY_03_DATA 0x00000000
+#define DDRSS3_PHY_04_DATA 0x00000000
+#define DDRSS3_PHY_05_DATA 0x01030000
+#define DDRSS3_PHY_06_DATA 0x00010000
+#define DDRSS3_PHY_07_DATA 0x01030004
+#define DDRSS3_PHY_08_DATA 0x01000000
+#define DDRSS3_PHY_09_DATA 0x00000000
+#define DDRSS3_PHY_10_DATA 0x00000000
+#define DDRSS3_PHY_11_DATA 0x01000001
+#define DDRSS3_PHY_12_DATA 0x00000100
+#define DDRSS3_PHY_13_DATA 0x000800C0
+#define DDRSS3_PHY_14_DATA 0x060100CC
+#define DDRSS3_PHY_15_DATA 0x00030066
+#define DDRSS3_PHY_16_DATA 0x00000000
+#define DDRSS3_PHY_17_DATA 0x00000301
+#define DDRSS3_PHY_18_DATA 0x0000AAAA
+#define DDRSS3_PHY_19_DATA 0x00005555
+#define DDRSS3_PHY_20_DATA 0x0000B5B5
+#define DDRSS3_PHY_21_DATA 0x00004A4A
+#define DDRSS3_PHY_22_DATA 0x00005656
+#define DDRSS3_PHY_23_DATA 0x0000A9A9
+#define DDRSS3_PHY_24_DATA 0x0000A9A9
+#define DDRSS3_PHY_25_DATA 0x0000B5B5
+#define DDRSS3_PHY_26_DATA 0x00000000
+#define DDRSS3_PHY_27_DATA 0x00000000
+#define DDRSS3_PHY_28_DATA 0x2A000000
+#define DDRSS3_PHY_29_DATA 0x00000808
+#define DDRSS3_PHY_30_DATA 0x0F000000
+#define DDRSS3_PHY_31_DATA 0x00000F0F
+#define DDRSS3_PHY_32_DATA 0x10400000
+#define DDRSS3_PHY_33_DATA 0x0C002006
+#define DDRSS3_PHY_34_DATA 0x00000000
+#define DDRSS3_PHY_35_DATA 0x00000000
+#define DDRSS3_PHY_36_DATA 0x55555555
+#define DDRSS3_PHY_37_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_38_DATA 0x55555555
+#define DDRSS3_PHY_39_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_40_DATA 0x00005555
+#define DDRSS3_PHY_41_DATA 0x01000100
+#define DDRSS3_PHY_42_DATA 0x00800180
+#define DDRSS3_PHY_43_DATA 0x00000001
+#define DDRSS3_PHY_44_DATA 0x00000000
+#define DDRSS3_PHY_45_DATA 0x00000000
+#define DDRSS3_PHY_46_DATA 0x00000000
+#define DDRSS3_PHY_47_DATA 0x00000000
+#define DDRSS3_PHY_48_DATA 0x00000000
+#define DDRSS3_PHY_49_DATA 0x00000000
+#define DDRSS3_PHY_50_DATA 0x00000000
+#define DDRSS3_PHY_51_DATA 0x00000000
+#define DDRSS3_PHY_52_DATA 0x00000000
+#define DDRSS3_PHY_53_DATA 0x00000000
+#define DDRSS3_PHY_54_DATA 0x00000000
+#define DDRSS3_PHY_55_DATA 0x00000000
+#define DDRSS3_PHY_56_DATA 0x00000000
+#define DDRSS3_PHY_57_DATA 0x00000000
+#define DDRSS3_PHY_58_DATA 0x00000000
+#define DDRSS3_PHY_59_DATA 0x00000000
+#define DDRSS3_PHY_60_DATA 0x00000000
+#define DDRSS3_PHY_61_DATA 0x00000000
+#define DDRSS3_PHY_62_DATA 0x00000000
+#define DDRSS3_PHY_63_DATA 0x00000000
+#define DDRSS3_PHY_64_DATA 0x00000000
+#define DDRSS3_PHY_65_DATA 0x00000000
+#define DDRSS3_PHY_66_DATA 0x00000104
+#define DDRSS3_PHY_67_DATA 0x00000120
+#define DDRSS3_PHY_68_DATA 0x00000000
+#define DDRSS3_PHY_69_DATA 0x00000000
+#define DDRSS3_PHY_70_DATA 0x00000000
+#define DDRSS3_PHY_71_DATA 0x00000000
+#define DDRSS3_PHY_72_DATA 0x00000000
+#define DDRSS3_PHY_73_DATA 0x00000000
+#define DDRSS3_PHY_74_DATA 0x00000000
+#define DDRSS3_PHY_75_DATA 0x00000001
+#define DDRSS3_PHY_76_DATA 0x07FF0000
+#define DDRSS3_PHY_77_DATA 0x0080081F
+#define DDRSS3_PHY_78_DATA 0x00081020
+#define DDRSS3_PHY_79_DATA 0x04010000
+#define DDRSS3_PHY_80_DATA 0x00000000
+#define DDRSS3_PHY_81_DATA 0x00000000
+#define DDRSS3_PHY_82_DATA 0x00000000
+#define DDRSS3_PHY_83_DATA 0x00000100
+#define DDRSS3_PHY_84_DATA 0x01CC0C01
+#define DDRSS3_PHY_85_DATA 0x1003CC0C
+#define DDRSS3_PHY_86_DATA 0x20000140
+#define DDRSS3_PHY_87_DATA 0x07FF0200
+#define DDRSS3_PHY_88_DATA 0x0000DD01
+#define DDRSS3_PHY_89_DATA 0x10100303
+#define DDRSS3_PHY_90_DATA 0x10101010
+#define DDRSS3_PHY_91_DATA 0x10101010
+#define DDRSS3_PHY_92_DATA 0x00021010
+#define DDRSS3_PHY_93_DATA 0x00100010
+#define DDRSS3_PHY_94_DATA 0x00100010
+#define DDRSS3_PHY_95_DATA 0x00100010
+#define DDRSS3_PHY_96_DATA 0x00100010
+#define DDRSS3_PHY_97_DATA 0x00050010
+#define DDRSS3_PHY_98_DATA 0x51517041
+#define DDRSS3_PHY_99_DATA 0x31C06001
+#define DDRSS3_PHY_100_DATA 0x07AB0340
+#define DDRSS3_PHY_101_DATA 0x00C0C001
+#define DDRSS3_PHY_102_DATA 0x0E0D0001
+#define DDRSS3_PHY_103_DATA 0x10001000
+#define DDRSS3_PHY_104_DATA 0x0C083E42
+#define DDRSS3_PHY_105_DATA 0x0F0C3701
+#define DDRSS3_PHY_106_DATA 0x01000140
+#define DDRSS3_PHY_107_DATA 0x0C000420
+#define DDRSS3_PHY_108_DATA 0x00000198
+#define DDRSS3_PHY_109_DATA 0x0A0000D0
+#define DDRSS3_PHY_110_DATA 0x00030200
+#define DDRSS3_PHY_111_DATA 0x02800000
+#define DDRSS3_PHY_112_DATA 0x80800000
+#define DDRSS3_PHY_113_DATA 0x000E2010
+#define DDRSS3_PHY_114_DATA 0x76543210
+#define DDRSS3_PHY_115_DATA 0x00000008
+#define DDRSS3_PHY_116_DATA 0x02800280
+#define DDRSS3_PHY_117_DATA 0x02800280
+#define DDRSS3_PHY_118_DATA 0x02800280
+#define DDRSS3_PHY_119_DATA 0x02800280
+#define DDRSS3_PHY_120_DATA 0x00000280
+#define DDRSS3_PHY_121_DATA 0x0000A000
+#define DDRSS3_PHY_122_DATA 0x00A000A0
+#define DDRSS3_PHY_123_DATA 0x00A000A0
+#define DDRSS3_PHY_124_DATA 0x00A000A0
+#define DDRSS3_PHY_125_DATA 0x00A000A0
+#define DDRSS3_PHY_126_DATA 0x00A000A0
+#define DDRSS3_PHY_127_DATA 0x00A000A0
+#define DDRSS3_PHY_128_DATA 0x00A000A0
+#define DDRSS3_PHY_129_DATA 0x00A000A0
+#define DDRSS3_PHY_130_DATA 0x01C200A0
+#define DDRSS3_PHY_131_DATA 0x01A00005
+#define DDRSS3_PHY_132_DATA 0x00000000
+#define DDRSS3_PHY_133_DATA 0x00000000
+#define DDRSS3_PHY_134_DATA 0x00080200
+#define DDRSS3_PHY_135_DATA 0x00000000
+#define DDRSS3_PHY_136_DATA 0x20202000
+#define DDRSS3_PHY_137_DATA 0x20202020
+#define DDRSS3_PHY_138_DATA 0xF0F02020
+#define DDRSS3_PHY_139_DATA 0x00000000
+#define DDRSS3_PHY_140_DATA 0x00000000
+#define DDRSS3_PHY_141_DATA 0x00000000
+#define DDRSS3_PHY_142_DATA 0x00000000
+#define DDRSS3_PHY_143_DATA 0x00000000
+#define DDRSS3_PHY_144_DATA 0x00000000
+#define DDRSS3_PHY_145_DATA 0x00000000
+#define DDRSS3_PHY_146_DATA 0x00000000
+#define DDRSS3_PHY_147_DATA 0x00000000
+#define DDRSS3_PHY_148_DATA 0x00000000
+#define DDRSS3_PHY_149_DATA 0x00000000
+#define DDRSS3_PHY_150_DATA 0x00000000
+#define DDRSS3_PHY_151_DATA 0x00000000
+#define DDRSS3_PHY_152_DATA 0x00000000
+#define DDRSS3_PHY_153_DATA 0x00000000
+#define DDRSS3_PHY_154_DATA 0x00000000
+#define DDRSS3_PHY_155_DATA 0x00000000
+#define DDRSS3_PHY_156_DATA 0x00000000
+#define DDRSS3_PHY_157_DATA 0x00000000
+#define DDRSS3_PHY_158_DATA 0x00000000
+#define DDRSS3_PHY_159_DATA 0x00000000
+#define DDRSS3_PHY_160_DATA 0x00000000
+#define DDRSS3_PHY_161_DATA 0x00000000
+#define DDRSS3_PHY_162_DATA 0x00000000
+#define DDRSS3_PHY_163_DATA 0x00000000
+#define DDRSS3_PHY_164_DATA 0x00000000
+#define DDRSS3_PHY_165_DATA 0x00000000
+#define DDRSS3_PHY_166_DATA 0x00000000
+#define DDRSS3_PHY_167_DATA 0x00000000
+#define DDRSS3_PHY_168_DATA 0x00000000
+#define DDRSS3_PHY_169_DATA 0x00000000
+#define DDRSS3_PHY_170_DATA 0x00000000
+#define DDRSS3_PHY_171_DATA 0x00000000
+#define DDRSS3_PHY_172_DATA 0x00000000
+#define DDRSS3_PHY_173_DATA 0x00000000
+#define DDRSS3_PHY_174_DATA 0x00000000
+#define DDRSS3_PHY_175_DATA 0x00000000
+#define DDRSS3_PHY_176_DATA 0x00000000
+#define DDRSS3_PHY_177_DATA 0x00000000
+#define DDRSS3_PHY_178_DATA 0x00000000
+#define DDRSS3_PHY_179_DATA 0x00000000
+#define DDRSS3_PHY_180_DATA 0x00000000
+#define DDRSS3_PHY_181_DATA 0x00000000
+#define DDRSS3_PHY_182_DATA 0x00000000
+#define DDRSS3_PHY_183_DATA 0x00000000
+#define DDRSS3_PHY_184_DATA 0x00000000
+#define DDRSS3_PHY_185_DATA 0x00000000
+#define DDRSS3_PHY_186_DATA 0x00000000
+#define DDRSS3_PHY_187_DATA 0x00000000
+#define DDRSS3_PHY_188_DATA 0x00000000
+#define DDRSS3_PHY_189_DATA 0x00000000
+#define DDRSS3_PHY_190_DATA 0x00000000
+#define DDRSS3_PHY_191_DATA 0x00000000
+#define DDRSS3_PHY_192_DATA 0x00000000
+#define DDRSS3_PHY_193_DATA 0x00000000
+#define DDRSS3_PHY_194_DATA 0x00000000
+#define DDRSS3_PHY_195_DATA 0x00000000
+#define DDRSS3_PHY_196_DATA 0x00000000
+#define DDRSS3_PHY_197_DATA 0x00000000
+#define DDRSS3_PHY_198_DATA 0x00000000
+#define DDRSS3_PHY_199_DATA 0x00000000
+#define DDRSS3_PHY_200_DATA 0x00000000
+#define DDRSS3_PHY_201_DATA 0x00000000
+#define DDRSS3_PHY_202_DATA 0x00000000
+#define DDRSS3_PHY_203_DATA 0x00000000
+#define DDRSS3_PHY_204_DATA 0x00000000
+#define DDRSS3_PHY_205_DATA 0x00000000
+#define DDRSS3_PHY_206_DATA 0x00000000
+#define DDRSS3_PHY_207_DATA 0x00000000
+#define DDRSS3_PHY_208_DATA 0x00000000
+#define DDRSS3_PHY_209_DATA 0x00000000
+#define DDRSS3_PHY_210_DATA 0x00000000
+#define DDRSS3_PHY_211_DATA 0x00000000
+#define DDRSS3_PHY_212_DATA 0x00000000
+#define DDRSS3_PHY_213_DATA 0x00000000
+#define DDRSS3_PHY_214_DATA 0x00000000
+#define DDRSS3_PHY_215_DATA 0x00000000
+#define DDRSS3_PHY_216_DATA 0x00000000
+#define DDRSS3_PHY_217_DATA 0x00000000
+#define DDRSS3_PHY_218_DATA 0x00000000
+#define DDRSS3_PHY_219_DATA 0x00000000
+#define DDRSS3_PHY_220_DATA 0x00000000
+#define DDRSS3_PHY_221_DATA 0x00000000
+#define DDRSS3_PHY_222_DATA 0x00000000
+#define DDRSS3_PHY_223_DATA 0x00000000
+#define DDRSS3_PHY_224_DATA 0x00000000
+#define DDRSS3_PHY_225_DATA 0x00000000
+#define DDRSS3_PHY_226_DATA 0x00000000
+#define DDRSS3_PHY_227_DATA 0x00000000
+#define DDRSS3_PHY_228_DATA 0x00000000
+#define DDRSS3_PHY_229_DATA 0x00000000
+#define DDRSS3_PHY_230_DATA 0x00000000
+#define DDRSS3_PHY_231_DATA 0x00000000
+#define DDRSS3_PHY_232_DATA 0x00000000
+#define DDRSS3_PHY_233_DATA 0x00000000
+#define DDRSS3_PHY_234_DATA 0x00000000
+#define DDRSS3_PHY_235_DATA 0x00000000
+#define DDRSS3_PHY_236_DATA 0x00000000
+#define DDRSS3_PHY_237_DATA 0x00000000
+#define DDRSS3_PHY_238_DATA 0x00000000
+#define DDRSS3_PHY_239_DATA 0x00000000
+#define DDRSS3_PHY_240_DATA 0x00000000
+#define DDRSS3_PHY_241_DATA 0x00000000
+#define DDRSS3_PHY_242_DATA 0x00000000
+#define DDRSS3_PHY_243_DATA 0x00000000
+#define DDRSS3_PHY_244_DATA 0x00000000
+#define DDRSS3_PHY_245_DATA 0x00000000
+#define DDRSS3_PHY_246_DATA 0x00000000
+#define DDRSS3_PHY_247_DATA 0x00000000
+#define DDRSS3_PHY_248_DATA 0x00000000
+#define DDRSS3_PHY_249_DATA 0x00000000
+#define DDRSS3_PHY_250_DATA 0x00000000
+#define DDRSS3_PHY_251_DATA 0x00000000
+#define DDRSS3_PHY_252_DATA 0x00000000
+#define DDRSS3_PHY_253_DATA 0x00000000
+#define DDRSS3_PHY_254_DATA 0x00000000
+#define DDRSS3_PHY_255_DATA 0x00000000
+#define DDRSS3_PHY_256_DATA 0x000004F0
+#define DDRSS3_PHY_257_DATA 0x00000000
+#define DDRSS3_PHY_258_DATA 0x00030200
+#define DDRSS3_PHY_259_DATA 0x00000000
+#define DDRSS3_PHY_260_DATA 0x00000000
+#define DDRSS3_PHY_261_DATA 0x01030000
+#define DDRSS3_PHY_262_DATA 0x00010000
+#define DDRSS3_PHY_263_DATA 0x01030004
+#define DDRSS3_PHY_264_DATA 0x01000000
+#define DDRSS3_PHY_265_DATA 0x00000000
+#define DDRSS3_PHY_266_DATA 0x00000000
+#define DDRSS3_PHY_267_DATA 0x01000001
+#define DDRSS3_PHY_268_DATA 0x00000100
+#define DDRSS3_PHY_269_DATA 0x000800C0
+#define DDRSS3_PHY_270_DATA 0x060100CC
+#define DDRSS3_PHY_271_DATA 0x00030066
+#define DDRSS3_PHY_272_DATA 0x00000000
+#define DDRSS3_PHY_273_DATA 0x00000301
+#define DDRSS3_PHY_274_DATA 0x0000AAAA
+#define DDRSS3_PHY_275_DATA 0x00005555
+#define DDRSS3_PHY_276_DATA 0x0000B5B5
+#define DDRSS3_PHY_277_DATA 0x00004A4A
+#define DDRSS3_PHY_278_DATA 0x00005656
+#define DDRSS3_PHY_279_DATA 0x0000A9A9
+#define DDRSS3_PHY_280_DATA 0x0000A9A9
+#define DDRSS3_PHY_281_DATA 0x0000B5B5
+#define DDRSS3_PHY_282_DATA 0x00000000
+#define DDRSS3_PHY_283_DATA 0x00000000
+#define DDRSS3_PHY_284_DATA 0x2A000000
+#define DDRSS3_PHY_285_DATA 0x00000808
+#define DDRSS3_PHY_286_DATA 0x0F000000
+#define DDRSS3_PHY_287_DATA 0x00000F0F
+#define DDRSS3_PHY_288_DATA 0x10400000
+#define DDRSS3_PHY_289_DATA 0x0C002006
+#define DDRSS3_PHY_290_DATA 0x00000000
+#define DDRSS3_PHY_291_DATA 0x00000000
+#define DDRSS3_PHY_292_DATA 0x55555555
+#define DDRSS3_PHY_293_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_294_DATA 0x55555555
+#define DDRSS3_PHY_295_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_296_DATA 0x00005555
+#define DDRSS3_PHY_297_DATA 0x01000100
+#define DDRSS3_PHY_298_DATA 0x00800180
+#define DDRSS3_PHY_299_DATA 0x00000000
+#define DDRSS3_PHY_300_DATA 0x00000000
+#define DDRSS3_PHY_301_DATA 0x00000000
+#define DDRSS3_PHY_302_DATA 0x00000000
+#define DDRSS3_PHY_303_DATA 0x00000000
+#define DDRSS3_PHY_304_DATA 0x00000000
+#define DDRSS3_PHY_305_DATA 0x00000000
+#define DDRSS3_PHY_306_DATA 0x00000000
+#define DDRSS3_PHY_307_DATA 0x00000000
+#define DDRSS3_PHY_308_DATA 0x00000000
+#define DDRSS3_PHY_309_DATA 0x00000000
+#define DDRSS3_PHY_310_DATA 0x00000000
+#define DDRSS3_PHY_311_DATA 0x00000000
+#define DDRSS3_PHY_312_DATA 0x00000000
+#define DDRSS3_PHY_313_DATA 0x00000000
+#define DDRSS3_PHY_314_DATA 0x00000000
+#define DDRSS3_PHY_315_DATA 0x00000000
+#define DDRSS3_PHY_316_DATA 0x00000000
+#define DDRSS3_PHY_317_DATA 0x00000000
+#define DDRSS3_PHY_318_DATA 0x00000000
+#define DDRSS3_PHY_319_DATA 0x00000000
+#define DDRSS3_PHY_320_DATA 0x00000000
+#define DDRSS3_PHY_321_DATA 0x00000000
+#define DDRSS3_PHY_322_DATA 0x00000104
+#define DDRSS3_PHY_323_DATA 0x00000120
+#define DDRSS3_PHY_324_DATA 0x00000000
+#define DDRSS3_PHY_325_DATA 0x00000000
+#define DDRSS3_PHY_326_DATA 0x00000000
+#define DDRSS3_PHY_327_DATA 0x00000000
+#define DDRSS3_PHY_328_DATA 0x00000000
+#define DDRSS3_PHY_329_DATA 0x00000000
+#define DDRSS3_PHY_330_DATA 0x00000000
+#define DDRSS3_PHY_331_DATA 0x00000001
+#define DDRSS3_PHY_332_DATA 0x07FF0000
+#define DDRSS3_PHY_333_DATA 0x0080081F
+#define DDRSS3_PHY_334_DATA 0x00081020
+#define DDRSS3_PHY_335_DATA 0x04010000
+#define DDRSS3_PHY_336_DATA 0x00000000
+#define DDRSS3_PHY_337_DATA 0x00000000
+#define DDRSS3_PHY_338_DATA 0x00000000
+#define DDRSS3_PHY_339_DATA 0x00000100
+#define DDRSS3_PHY_340_DATA 0x01CC0C01
+#define DDRSS3_PHY_341_DATA 0x1003CC0C
+#define DDRSS3_PHY_342_DATA 0x20000140
+#define DDRSS3_PHY_343_DATA 0x07FF0200
+#define DDRSS3_PHY_344_DATA 0x0000DD01
+#define DDRSS3_PHY_345_DATA 0x10100303
+#define DDRSS3_PHY_346_DATA 0x10101010
+#define DDRSS3_PHY_347_DATA 0x10101010
+#define DDRSS3_PHY_348_DATA 0x00021010
+#define DDRSS3_PHY_349_DATA 0x00100010
+#define DDRSS3_PHY_350_DATA 0x00100010
+#define DDRSS3_PHY_351_DATA 0x00100010
+#define DDRSS3_PHY_352_DATA 0x00100010
+#define DDRSS3_PHY_353_DATA 0x00050010
+#define DDRSS3_PHY_354_DATA 0x51517041
+#define DDRSS3_PHY_355_DATA 0x31C06001
+#define DDRSS3_PHY_356_DATA 0x07AB0340
+#define DDRSS3_PHY_357_DATA 0x00C0C001
+#define DDRSS3_PHY_358_DATA 0x0E0D0001
+#define DDRSS3_PHY_359_DATA 0x10001000
+#define DDRSS3_PHY_360_DATA 0x0C083E42
+#define DDRSS3_PHY_361_DATA 0x0F0C3701
+#define DDRSS3_PHY_362_DATA 0x01000140
+#define DDRSS3_PHY_363_DATA 0x0C000420
+#define DDRSS3_PHY_364_DATA 0x00000198
+#define DDRSS3_PHY_365_DATA 0x0A0000D0
+#define DDRSS3_PHY_366_DATA 0x00030200
+#define DDRSS3_PHY_367_DATA 0x02800000
+#define DDRSS3_PHY_368_DATA 0x80800000
+#define DDRSS3_PHY_369_DATA 0x000E2010
+#define DDRSS3_PHY_370_DATA 0x76543210
+#define DDRSS3_PHY_371_DATA 0x00000008
+#define DDRSS3_PHY_372_DATA 0x02800280
+#define DDRSS3_PHY_373_DATA 0x02800280
+#define DDRSS3_PHY_374_DATA 0x02800280
+#define DDRSS3_PHY_375_DATA 0x02800280
+#define DDRSS3_PHY_376_DATA 0x00000280
+#define DDRSS3_PHY_377_DATA 0x0000A000
+#define DDRSS3_PHY_378_DATA 0x00A000A0
+#define DDRSS3_PHY_379_DATA 0x00A000A0
+#define DDRSS3_PHY_380_DATA 0x00A000A0
+#define DDRSS3_PHY_381_DATA 0x00A000A0
+#define DDRSS3_PHY_382_DATA 0x00A000A0
+#define DDRSS3_PHY_383_DATA 0x00A000A0
+#define DDRSS3_PHY_384_DATA 0x00A000A0
+#define DDRSS3_PHY_385_DATA 0x00A000A0
+#define DDRSS3_PHY_386_DATA 0x01C200A0
+#define DDRSS3_PHY_387_DATA 0x01A00005
+#define DDRSS3_PHY_388_DATA 0x00000000
+#define DDRSS3_PHY_389_DATA 0x00000000
+#define DDRSS3_PHY_390_DATA 0x00080200
+#define DDRSS3_PHY_391_DATA 0x00000000
+#define DDRSS3_PHY_392_DATA 0x20202000
+#define DDRSS3_PHY_393_DATA 0x20202020
+#define DDRSS3_PHY_394_DATA 0xF0F02020
+#define DDRSS3_PHY_395_DATA 0x00000000
+#define DDRSS3_PHY_396_DATA 0x00000000
+#define DDRSS3_PHY_397_DATA 0x00000000
+#define DDRSS3_PHY_398_DATA 0x00000000
+#define DDRSS3_PHY_399_DATA 0x00000000
+#define DDRSS3_PHY_400_DATA 0x00000000
+#define DDRSS3_PHY_401_DATA 0x00000000
+#define DDRSS3_PHY_402_DATA 0x00000000
+#define DDRSS3_PHY_403_DATA 0x00000000
+#define DDRSS3_PHY_404_DATA 0x00000000
+#define DDRSS3_PHY_405_DATA 0x00000000
+#define DDRSS3_PHY_406_DATA 0x00000000
+#define DDRSS3_PHY_407_DATA 0x00000000
+#define DDRSS3_PHY_408_DATA 0x00000000
+#define DDRSS3_PHY_409_DATA 0x00000000
+#define DDRSS3_PHY_410_DATA 0x00000000
+#define DDRSS3_PHY_411_DATA 0x00000000
+#define DDRSS3_PHY_412_DATA 0x00000000
+#define DDRSS3_PHY_413_DATA 0x00000000
+#define DDRSS3_PHY_414_DATA 0x00000000
+#define DDRSS3_PHY_415_DATA 0x00000000
+#define DDRSS3_PHY_416_DATA 0x00000000
+#define DDRSS3_PHY_417_DATA 0x00000000
+#define DDRSS3_PHY_418_DATA 0x00000000
+#define DDRSS3_PHY_419_DATA 0x00000000
+#define DDRSS3_PHY_420_DATA 0x00000000
+#define DDRSS3_PHY_421_DATA 0x00000000
+#define DDRSS3_PHY_422_DATA 0x00000000
+#define DDRSS3_PHY_423_DATA 0x00000000
+#define DDRSS3_PHY_424_DATA 0x00000000
+#define DDRSS3_PHY_425_DATA 0x00000000
+#define DDRSS3_PHY_426_DATA 0x00000000
+#define DDRSS3_PHY_427_DATA 0x00000000
+#define DDRSS3_PHY_428_DATA 0x00000000
+#define DDRSS3_PHY_429_DATA 0x00000000
+#define DDRSS3_PHY_430_DATA 0x00000000
+#define DDRSS3_PHY_431_DATA 0x00000000
+#define DDRSS3_PHY_432_DATA 0x00000000
+#define DDRSS3_PHY_433_DATA 0x00000000
+#define DDRSS3_PHY_434_DATA 0x00000000
+#define DDRSS3_PHY_435_DATA 0x00000000
+#define DDRSS3_PHY_436_DATA 0x00000000
+#define DDRSS3_PHY_437_DATA 0x00000000
+#define DDRSS3_PHY_438_DATA 0x00000000
+#define DDRSS3_PHY_439_DATA 0x00000000
+#define DDRSS3_PHY_440_DATA 0x00000000
+#define DDRSS3_PHY_441_DATA 0x00000000
+#define DDRSS3_PHY_442_DATA 0x00000000
+#define DDRSS3_PHY_443_DATA 0x00000000
+#define DDRSS3_PHY_444_DATA 0x00000000
+#define DDRSS3_PHY_445_DATA 0x00000000
+#define DDRSS3_PHY_446_DATA 0x00000000
+#define DDRSS3_PHY_447_DATA 0x00000000
+#define DDRSS3_PHY_448_DATA 0x00000000
+#define DDRSS3_PHY_449_DATA 0x00000000
+#define DDRSS3_PHY_450_DATA 0x00000000
+#define DDRSS3_PHY_451_DATA 0x00000000
+#define DDRSS3_PHY_452_DATA 0x00000000
+#define DDRSS3_PHY_453_DATA 0x00000000
+#define DDRSS3_PHY_454_DATA 0x00000000
+#define DDRSS3_PHY_455_DATA 0x00000000
+#define DDRSS3_PHY_456_DATA 0x00000000
+#define DDRSS3_PHY_457_DATA 0x00000000
+#define DDRSS3_PHY_458_DATA 0x00000000
+#define DDRSS3_PHY_459_DATA 0x00000000
+#define DDRSS3_PHY_460_DATA 0x00000000
+#define DDRSS3_PHY_461_DATA 0x00000000
+#define DDRSS3_PHY_462_DATA 0x00000000
+#define DDRSS3_PHY_463_DATA 0x00000000
+#define DDRSS3_PHY_464_DATA 0x00000000
+#define DDRSS3_PHY_465_DATA 0x00000000
+#define DDRSS3_PHY_466_DATA 0x00000000
+#define DDRSS3_PHY_467_DATA 0x00000000
+#define DDRSS3_PHY_468_DATA 0x00000000
+#define DDRSS3_PHY_469_DATA 0x00000000
+#define DDRSS3_PHY_470_DATA 0x00000000
+#define DDRSS3_PHY_471_DATA 0x00000000
+#define DDRSS3_PHY_472_DATA 0x00000000
+#define DDRSS3_PHY_473_DATA 0x00000000
+#define DDRSS3_PHY_474_DATA 0x00000000
+#define DDRSS3_PHY_475_DATA 0x00000000
+#define DDRSS3_PHY_476_DATA 0x00000000
+#define DDRSS3_PHY_477_DATA 0x00000000
+#define DDRSS3_PHY_478_DATA 0x00000000
+#define DDRSS3_PHY_479_DATA 0x00000000
+#define DDRSS3_PHY_480_DATA 0x00000000
+#define DDRSS3_PHY_481_DATA 0x00000000
+#define DDRSS3_PHY_482_DATA 0x00000000
+#define DDRSS3_PHY_483_DATA 0x00000000
+#define DDRSS3_PHY_484_DATA 0x00000000
+#define DDRSS3_PHY_485_DATA 0x00000000
+#define DDRSS3_PHY_486_DATA 0x00000000
+#define DDRSS3_PHY_487_DATA 0x00000000
+#define DDRSS3_PHY_488_DATA 0x00000000
+#define DDRSS3_PHY_489_DATA 0x00000000
+#define DDRSS3_PHY_490_DATA 0x00000000
+#define DDRSS3_PHY_491_DATA 0x00000000
+#define DDRSS3_PHY_492_DATA 0x00000000
+#define DDRSS3_PHY_493_DATA 0x00000000
+#define DDRSS3_PHY_494_DATA 0x00000000
+#define DDRSS3_PHY_495_DATA 0x00000000
+#define DDRSS3_PHY_496_DATA 0x00000000
+#define DDRSS3_PHY_497_DATA 0x00000000
+#define DDRSS3_PHY_498_DATA 0x00000000
+#define DDRSS3_PHY_499_DATA 0x00000000
+#define DDRSS3_PHY_500_DATA 0x00000000
+#define DDRSS3_PHY_501_DATA 0x00000000
+#define DDRSS3_PHY_502_DATA 0x00000000
+#define DDRSS3_PHY_503_DATA 0x00000000
+#define DDRSS3_PHY_504_DATA 0x00000000
+#define DDRSS3_PHY_505_DATA 0x00000000
+#define DDRSS3_PHY_506_DATA 0x00000000
+#define DDRSS3_PHY_507_DATA 0x00000000
+#define DDRSS3_PHY_508_DATA 0x00000000
+#define DDRSS3_PHY_509_DATA 0x00000000
+#define DDRSS3_PHY_510_DATA 0x00000000
+#define DDRSS3_PHY_511_DATA 0x00000000
+#define DDRSS3_PHY_512_DATA 0x000004F0
+#define DDRSS3_PHY_513_DATA 0x00000000
+#define DDRSS3_PHY_514_DATA 0x00030200
+#define DDRSS3_PHY_515_DATA 0x00000000
+#define DDRSS3_PHY_516_DATA 0x00000000
+#define DDRSS3_PHY_517_DATA 0x01030000
+#define DDRSS3_PHY_518_DATA 0x00010000
+#define DDRSS3_PHY_519_DATA 0x01030004
+#define DDRSS3_PHY_520_DATA 0x01000000
+#define DDRSS3_PHY_521_DATA 0x00000000
+#define DDRSS3_PHY_522_DATA 0x00000000
+#define DDRSS3_PHY_523_DATA 0x01000001
+#define DDRSS3_PHY_524_DATA 0x00000100
+#define DDRSS3_PHY_525_DATA 0x000800C0
+#define DDRSS3_PHY_526_DATA 0x060100CC
+#define DDRSS3_PHY_527_DATA 0x00030066
+#define DDRSS3_PHY_528_DATA 0x00000000
+#define DDRSS3_PHY_529_DATA 0x00000301
+#define DDRSS3_PHY_530_DATA 0x0000AAAA
+#define DDRSS3_PHY_531_DATA 0x00005555
+#define DDRSS3_PHY_532_DATA 0x0000B5B5
+#define DDRSS3_PHY_533_DATA 0x00004A4A
+#define DDRSS3_PHY_534_DATA 0x00005656
+#define DDRSS3_PHY_535_DATA 0x0000A9A9
+#define DDRSS3_PHY_536_DATA 0x0000A9A9
+#define DDRSS3_PHY_537_DATA 0x0000B5B5
+#define DDRSS3_PHY_538_DATA 0x00000000
+#define DDRSS3_PHY_539_DATA 0x00000000
+#define DDRSS3_PHY_540_DATA 0x2A000000
+#define DDRSS3_PHY_541_DATA 0x00000808
+#define DDRSS3_PHY_542_DATA 0x0F000000
+#define DDRSS3_PHY_543_DATA 0x00000F0F
+#define DDRSS3_PHY_544_DATA 0x10400000
+#define DDRSS3_PHY_545_DATA 0x0C002006
+#define DDRSS3_PHY_546_DATA 0x00000000
+#define DDRSS3_PHY_547_DATA 0x00000000
+#define DDRSS3_PHY_548_DATA 0x55555555
+#define DDRSS3_PHY_549_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_550_DATA 0x55555555
+#define DDRSS3_PHY_551_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_552_DATA 0x00005555
+#define DDRSS3_PHY_553_DATA 0x01000100
+#define DDRSS3_PHY_554_DATA 0x00800180
+#define DDRSS3_PHY_555_DATA 0x00000001
+#define DDRSS3_PHY_556_DATA 0x00000000
+#define DDRSS3_PHY_557_DATA 0x00000000
+#define DDRSS3_PHY_558_DATA 0x00000000
+#define DDRSS3_PHY_559_DATA 0x00000000
+#define DDRSS3_PHY_560_DATA 0x00000000
+#define DDRSS3_PHY_561_DATA 0x00000000
+#define DDRSS3_PHY_562_DATA 0x00000000
+#define DDRSS3_PHY_563_DATA 0x00000000
+#define DDRSS3_PHY_564_DATA 0x00000000
+#define DDRSS3_PHY_565_DATA 0x00000000
+#define DDRSS3_PHY_566_DATA 0x00000000
+#define DDRSS3_PHY_567_DATA 0x00000000
+#define DDRSS3_PHY_568_DATA 0x00000000
+#define DDRSS3_PHY_569_DATA 0x00000000
+#define DDRSS3_PHY_570_DATA 0x00000000
+#define DDRSS3_PHY_571_DATA 0x00000000
+#define DDRSS3_PHY_572_DATA 0x00000000
+#define DDRSS3_PHY_573_DATA 0x00000000
+#define DDRSS3_PHY_574_DATA 0x00000000
+#define DDRSS3_PHY_575_DATA 0x00000000
+#define DDRSS3_PHY_576_DATA 0x00000000
+#define DDRSS3_PHY_577_DATA 0x00000000
+#define DDRSS3_PHY_578_DATA 0x00000104
+#define DDRSS3_PHY_579_DATA 0x00000120
+#define DDRSS3_PHY_580_DATA 0x00000000
+#define DDRSS3_PHY_581_DATA 0x00000000
+#define DDRSS3_PHY_582_DATA 0x00000000
+#define DDRSS3_PHY_583_DATA 0x00000000
+#define DDRSS3_PHY_584_DATA 0x00000000
+#define DDRSS3_PHY_585_DATA 0x00000000
+#define DDRSS3_PHY_586_DATA 0x00000000
+#define DDRSS3_PHY_587_DATA 0x00000001
+#define DDRSS3_PHY_588_DATA 0x07FF0000
+#define DDRSS3_PHY_589_DATA 0x0080081F
+#define DDRSS3_PHY_590_DATA 0x00081020
+#define DDRSS3_PHY_591_DATA 0x04010000
+#define DDRSS3_PHY_592_DATA 0x00000000
+#define DDRSS3_PHY_593_DATA 0x00000000
+#define DDRSS3_PHY_594_DATA 0x00000000
+#define DDRSS3_PHY_595_DATA 0x00000100
+#define DDRSS3_PHY_596_DATA 0x01CC0C01
+#define DDRSS3_PHY_597_DATA 0x1003CC0C
+#define DDRSS3_PHY_598_DATA 0x20000140
+#define DDRSS3_PHY_599_DATA 0x07FF0200
+#define DDRSS3_PHY_600_DATA 0x0000DD01
+#define DDRSS3_PHY_601_DATA 0x10100303
+#define DDRSS3_PHY_602_DATA 0x10101010
+#define DDRSS3_PHY_603_DATA 0x10101010
+#define DDRSS3_PHY_604_DATA 0x00021010
+#define DDRSS3_PHY_605_DATA 0x00100010
+#define DDRSS3_PHY_606_DATA 0x00100010
+#define DDRSS3_PHY_607_DATA 0x00100010
+#define DDRSS3_PHY_608_DATA 0x00100010
+#define DDRSS3_PHY_609_DATA 0x00050010
+#define DDRSS3_PHY_610_DATA 0x51517041
+#define DDRSS3_PHY_611_DATA 0x31C06001
+#define DDRSS3_PHY_612_DATA 0x07AB0340
+#define DDRSS3_PHY_613_DATA 0x00C0C001
+#define DDRSS3_PHY_614_DATA 0x0E0D0001
+#define DDRSS3_PHY_615_DATA 0x10001000
+#define DDRSS3_PHY_616_DATA 0x0C083E42
+#define DDRSS3_PHY_617_DATA 0x0F0C3701
+#define DDRSS3_PHY_618_DATA 0x01000140
+#define DDRSS3_PHY_619_DATA 0x0C000420
+#define DDRSS3_PHY_620_DATA 0x00000198
+#define DDRSS3_PHY_621_DATA 0x0A0000D0
+#define DDRSS3_PHY_622_DATA 0x00030200
+#define DDRSS3_PHY_623_DATA 0x02800000
+#define DDRSS3_PHY_624_DATA 0x80800000
+#define DDRSS3_PHY_625_DATA 0x000E2010
+#define DDRSS3_PHY_626_DATA 0x76543210
+#define DDRSS3_PHY_627_DATA 0x00000008
+#define DDRSS3_PHY_628_DATA 0x02800280
+#define DDRSS3_PHY_629_DATA 0x02800280
+#define DDRSS3_PHY_630_DATA 0x02800280
+#define DDRSS3_PHY_631_DATA 0x02800280
+#define DDRSS3_PHY_632_DATA 0x00000280
+#define DDRSS3_PHY_633_DATA 0x0000A000
+#define DDRSS3_PHY_634_DATA 0x00A000A0
+#define DDRSS3_PHY_635_DATA 0x00A000A0
+#define DDRSS3_PHY_636_DATA 0x00A000A0
+#define DDRSS3_PHY_637_DATA 0x00A000A0
+#define DDRSS3_PHY_638_DATA 0x00A000A0
+#define DDRSS3_PHY_639_DATA 0x00A000A0
+#define DDRSS3_PHY_640_DATA 0x00A000A0
+#define DDRSS3_PHY_641_DATA 0x00A000A0
+#define DDRSS3_PHY_642_DATA 0x01C200A0
+#define DDRSS3_PHY_643_DATA 0x01A00005
+#define DDRSS3_PHY_644_DATA 0x00000000
+#define DDRSS3_PHY_645_DATA 0x00000000
+#define DDRSS3_PHY_646_DATA 0x00080200
+#define DDRSS3_PHY_647_DATA 0x00000000
+#define DDRSS3_PHY_648_DATA 0x20202000
+#define DDRSS3_PHY_649_DATA 0x20202020
+#define DDRSS3_PHY_650_DATA 0xF0F02020
+#define DDRSS3_PHY_651_DATA 0x00000000
+#define DDRSS3_PHY_652_DATA 0x00000000
+#define DDRSS3_PHY_653_DATA 0x00000000
+#define DDRSS3_PHY_654_DATA 0x00000000
+#define DDRSS3_PHY_655_DATA 0x00000000
+#define DDRSS3_PHY_656_DATA 0x00000000
+#define DDRSS3_PHY_657_DATA 0x00000000
+#define DDRSS3_PHY_658_DATA 0x00000000
+#define DDRSS3_PHY_659_DATA 0x00000000
+#define DDRSS3_PHY_660_DATA 0x00000000
+#define DDRSS3_PHY_661_DATA 0x00000000
+#define DDRSS3_PHY_662_DATA 0x00000000
+#define DDRSS3_PHY_663_DATA 0x00000000
+#define DDRSS3_PHY_664_DATA 0x00000000
+#define DDRSS3_PHY_665_DATA 0x00000000
+#define DDRSS3_PHY_666_DATA 0x00000000
+#define DDRSS3_PHY_667_DATA 0x00000000
+#define DDRSS3_PHY_668_DATA 0x00000000
+#define DDRSS3_PHY_669_DATA 0x00000000
+#define DDRSS3_PHY_670_DATA 0x00000000
+#define DDRSS3_PHY_671_DATA 0x00000000
+#define DDRSS3_PHY_672_DATA 0x00000000
+#define DDRSS3_PHY_673_DATA 0x00000000
+#define DDRSS3_PHY_674_DATA 0x00000000
+#define DDRSS3_PHY_675_DATA 0x00000000
+#define DDRSS3_PHY_676_DATA 0x00000000
+#define DDRSS3_PHY_677_DATA 0x00000000
+#define DDRSS3_PHY_678_DATA 0x00000000
+#define DDRSS3_PHY_679_DATA 0x00000000
+#define DDRSS3_PHY_680_DATA 0x00000000
+#define DDRSS3_PHY_681_DATA 0x00000000
+#define DDRSS3_PHY_682_DATA 0x00000000
+#define DDRSS3_PHY_683_DATA 0x00000000
+#define DDRSS3_PHY_684_DATA 0x00000000
+#define DDRSS3_PHY_685_DATA 0x00000000
+#define DDRSS3_PHY_686_DATA 0x00000000
+#define DDRSS3_PHY_687_DATA 0x00000000
+#define DDRSS3_PHY_688_DATA 0x00000000
+#define DDRSS3_PHY_689_DATA 0x00000000
+#define DDRSS3_PHY_690_DATA 0x00000000
+#define DDRSS3_PHY_691_DATA 0x00000000
+#define DDRSS3_PHY_692_DATA 0x00000000
+#define DDRSS3_PHY_693_DATA 0x00000000
+#define DDRSS3_PHY_694_DATA 0x00000000
+#define DDRSS3_PHY_695_DATA 0x00000000
+#define DDRSS3_PHY_696_DATA 0x00000000
+#define DDRSS3_PHY_697_DATA 0x00000000
+#define DDRSS3_PHY_698_DATA 0x00000000
+#define DDRSS3_PHY_699_DATA 0x00000000
+#define DDRSS3_PHY_700_DATA 0x00000000
+#define DDRSS3_PHY_701_DATA 0x00000000
+#define DDRSS3_PHY_702_DATA 0x00000000
+#define DDRSS3_PHY_703_DATA 0x00000000
+#define DDRSS3_PHY_704_DATA 0x00000000
+#define DDRSS3_PHY_705_DATA 0x00000000
+#define DDRSS3_PHY_706_DATA 0x00000000
+#define DDRSS3_PHY_707_DATA 0x00000000
+#define DDRSS3_PHY_708_DATA 0x00000000
+#define DDRSS3_PHY_709_DATA 0x00000000
+#define DDRSS3_PHY_710_DATA 0x00000000
+#define DDRSS3_PHY_711_DATA 0x00000000
+#define DDRSS3_PHY_712_DATA 0x00000000
+#define DDRSS3_PHY_713_DATA 0x00000000
+#define DDRSS3_PHY_714_DATA 0x00000000
+#define DDRSS3_PHY_715_DATA 0x00000000
+#define DDRSS3_PHY_716_DATA 0x00000000
+#define DDRSS3_PHY_717_DATA 0x00000000
+#define DDRSS3_PHY_718_DATA 0x00000000
+#define DDRSS3_PHY_719_DATA 0x00000000
+#define DDRSS3_PHY_720_DATA 0x00000000
+#define DDRSS3_PHY_721_DATA 0x00000000
+#define DDRSS3_PHY_722_DATA 0x00000000
+#define DDRSS3_PHY_723_DATA 0x00000000
+#define DDRSS3_PHY_724_DATA 0x00000000
+#define DDRSS3_PHY_725_DATA 0x00000000
+#define DDRSS3_PHY_726_DATA 0x00000000
+#define DDRSS3_PHY_727_DATA 0x00000000
+#define DDRSS3_PHY_728_DATA 0x00000000
+#define DDRSS3_PHY_729_DATA 0x00000000
+#define DDRSS3_PHY_730_DATA 0x00000000
+#define DDRSS3_PHY_731_DATA 0x00000000
+#define DDRSS3_PHY_732_DATA 0x00000000
+#define DDRSS3_PHY_733_DATA 0x00000000
+#define DDRSS3_PHY_734_DATA 0x00000000
+#define DDRSS3_PHY_735_DATA 0x00000000
+#define DDRSS3_PHY_736_DATA 0x00000000
+#define DDRSS3_PHY_737_DATA 0x00000000
+#define DDRSS3_PHY_738_DATA 0x00000000
+#define DDRSS3_PHY_739_DATA 0x00000000
+#define DDRSS3_PHY_740_DATA 0x00000000
+#define DDRSS3_PHY_741_DATA 0x00000000
+#define DDRSS3_PHY_742_DATA 0x00000000
+#define DDRSS3_PHY_743_DATA 0x00000000
+#define DDRSS3_PHY_744_DATA 0x00000000
+#define DDRSS3_PHY_745_DATA 0x00000000
+#define DDRSS3_PHY_746_DATA 0x00000000
+#define DDRSS3_PHY_747_DATA 0x00000000
+#define DDRSS3_PHY_748_DATA 0x00000000
+#define DDRSS3_PHY_749_DATA 0x00000000
+#define DDRSS3_PHY_750_DATA 0x00000000
+#define DDRSS3_PHY_751_DATA 0x00000000
+#define DDRSS3_PHY_752_DATA 0x00000000
+#define DDRSS3_PHY_753_DATA 0x00000000
+#define DDRSS3_PHY_754_DATA 0x00000000
+#define DDRSS3_PHY_755_DATA 0x00000000
+#define DDRSS3_PHY_756_DATA 0x00000000
+#define DDRSS3_PHY_757_DATA 0x00000000
+#define DDRSS3_PHY_758_DATA 0x00000000
+#define DDRSS3_PHY_759_DATA 0x00000000
+#define DDRSS3_PHY_760_DATA 0x00000000
+#define DDRSS3_PHY_761_DATA 0x00000000
+#define DDRSS3_PHY_762_DATA 0x00000000
+#define DDRSS3_PHY_763_DATA 0x00000000
+#define DDRSS3_PHY_764_DATA 0x00000000
+#define DDRSS3_PHY_765_DATA 0x00000000
+#define DDRSS3_PHY_766_DATA 0x00000000
+#define DDRSS3_PHY_767_DATA 0x00000000
+#define DDRSS3_PHY_768_DATA 0x000004F0
+#define DDRSS3_PHY_769_DATA 0x00000000
+#define DDRSS3_PHY_770_DATA 0x00030200
+#define DDRSS3_PHY_771_DATA 0x00000000
+#define DDRSS3_PHY_772_DATA 0x00000000
+#define DDRSS3_PHY_773_DATA 0x01030000
+#define DDRSS3_PHY_774_DATA 0x00010000
+#define DDRSS3_PHY_775_DATA 0x01030004
+#define DDRSS3_PHY_776_DATA 0x01000000
+#define DDRSS3_PHY_777_DATA 0x00000000
+#define DDRSS3_PHY_778_DATA 0x00000000
+#define DDRSS3_PHY_779_DATA 0x01000001
+#define DDRSS3_PHY_780_DATA 0x00000100
+#define DDRSS3_PHY_781_DATA 0x000800C0
+#define DDRSS3_PHY_782_DATA 0x060100CC
+#define DDRSS3_PHY_783_DATA 0x00030066
+#define DDRSS3_PHY_784_DATA 0x00000000
+#define DDRSS3_PHY_785_DATA 0x00000301
+#define DDRSS3_PHY_786_DATA 0x0000AAAA
+#define DDRSS3_PHY_787_DATA 0x00005555
+#define DDRSS3_PHY_788_DATA 0x0000B5B5
+#define DDRSS3_PHY_789_DATA 0x00004A4A
+#define DDRSS3_PHY_790_DATA 0x00005656
+#define DDRSS3_PHY_791_DATA 0x0000A9A9
+#define DDRSS3_PHY_792_DATA 0x0000A9A9
+#define DDRSS3_PHY_793_DATA 0x0000B5B5
+#define DDRSS3_PHY_794_DATA 0x00000000
+#define DDRSS3_PHY_795_DATA 0x00000000
+#define DDRSS3_PHY_796_DATA 0x2A000000
+#define DDRSS3_PHY_797_DATA 0x00000808
+#define DDRSS3_PHY_798_DATA 0x0F000000
+#define DDRSS3_PHY_799_DATA 0x00000F0F
+#define DDRSS3_PHY_800_DATA 0x10400000
+#define DDRSS3_PHY_801_DATA 0x0C002006
+#define DDRSS3_PHY_802_DATA 0x00000000
+#define DDRSS3_PHY_803_DATA 0x00000000
+#define DDRSS3_PHY_804_DATA 0x55555555
+#define DDRSS3_PHY_805_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_806_DATA 0x55555555
+#define DDRSS3_PHY_807_DATA 0xAAAAAAAA
+#define DDRSS3_PHY_808_DATA 0x00005555
+#define DDRSS3_PHY_809_DATA 0x01000100
+#define DDRSS3_PHY_810_DATA 0x00800180
+#define DDRSS3_PHY_811_DATA 0x00000000
+#define DDRSS3_PHY_812_DATA 0x00000000
+#define DDRSS3_PHY_813_DATA 0x00000000
+#define DDRSS3_PHY_814_DATA 0x00000000
+#define DDRSS3_PHY_815_DATA 0x00000000
+#define DDRSS3_PHY_816_DATA 0x00000000
+#define DDRSS3_PHY_817_DATA 0x00000000
+#define DDRSS3_PHY_818_DATA 0x00000000
+#define DDRSS3_PHY_819_DATA 0x00000000
+#define DDRSS3_PHY_820_DATA 0x00000000
+#define DDRSS3_PHY_821_DATA 0x00000000
+#define DDRSS3_PHY_822_DATA 0x00000000
+#define DDRSS3_PHY_823_DATA 0x00000000
+#define DDRSS3_PHY_824_DATA 0x00000000
+#define DDRSS3_PHY_825_DATA 0x00000000
+#define DDRSS3_PHY_826_DATA 0x00000000
+#define DDRSS3_PHY_827_DATA 0x00000000
+#define DDRSS3_PHY_828_DATA 0x00000000
+#define DDRSS3_PHY_829_DATA 0x00000000
+#define DDRSS3_PHY_830_DATA 0x00000000
+#define DDRSS3_PHY_831_DATA 0x00000000
+#define DDRSS3_PHY_832_DATA 0x00000000
+#define DDRSS3_PHY_833_DATA 0x00000000
+#define DDRSS3_PHY_834_DATA 0x00000104
+#define DDRSS3_PHY_835_DATA 0x00000120
+#define DDRSS3_PHY_836_DATA 0x00000000
+#define DDRSS3_PHY_837_DATA 0x00000000
+#define DDRSS3_PHY_838_DATA 0x00000000
+#define DDRSS3_PHY_839_DATA 0x00000000
+#define DDRSS3_PHY_840_DATA 0x00000000
+#define DDRSS3_PHY_841_DATA 0x00000000
+#define DDRSS3_PHY_842_DATA 0x00000000
+#define DDRSS3_PHY_843_DATA 0x00000001
+#define DDRSS3_PHY_844_DATA 0x07FF0000
+#define DDRSS3_PHY_845_DATA 0x0080081F
+#define DDRSS3_PHY_846_DATA 0x00081020
+#define DDRSS3_PHY_847_DATA 0x04010000
+#define DDRSS3_PHY_848_DATA 0x00000000
+#define DDRSS3_PHY_849_DATA 0x00000000
+#define DDRSS3_PHY_850_DATA 0x00000000
+#define DDRSS3_PHY_851_DATA 0x00000100
+#define DDRSS3_PHY_852_DATA 0x01CC0C01
+#define DDRSS3_PHY_853_DATA 0x1003CC0C
+#define DDRSS3_PHY_854_DATA 0x20000140
+#define DDRSS3_PHY_855_DATA 0x07FF0200
+#define DDRSS3_PHY_856_DATA 0x0000DD01
+#define DDRSS3_PHY_857_DATA 0x10100303
+#define DDRSS3_PHY_858_DATA 0x10101010
+#define DDRSS3_PHY_859_DATA 0x10101010
+#define DDRSS3_PHY_860_DATA 0x00021010
+#define DDRSS3_PHY_861_DATA 0x00100010
+#define DDRSS3_PHY_862_DATA 0x00100010
+#define DDRSS3_PHY_863_DATA 0x00100010
+#define DDRSS3_PHY_864_DATA 0x00100010
+#define DDRSS3_PHY_865_DATA 0x00050010
+#define DDRSS3_PHY_866_DATA 0x51517041
+#define DDRSS3_PHY_867_DATA 0x31C06001
+#define DDRSS3_PHY_868_DATA 0x07AB0340
+#define DDRSS3_PHY_869_DATA 0x00C0C001
+#define DDRSS3_PHY_870_DATA 0x0E0D0001
+#define DDRSS3_PHY_871_DATA 0x10001000
+#define DDRSS3_PHY_872_DATA 0x0C083E42
+#define DDRSS3_PHY_873_DATA 0x0F0C3701
+#define DDRSS3_PHY_874_DATA 0x01000140
+#define DDRSS3_PHY_875_DATA 0x0C000420
+#define DDRSS3_PHY_876_DATA 0x00000198
+#define DDRSS3_PHY_877_DATA 0x0A0000D0
+#define DDRSS3_PHY_878_DATA 0x00030200
+#define DDRSS3_PHY_879_DATA 0x02800000
+#define DDRSS3_PHY_880_DATA 0x80800000
+#define DDRSS3_PHY_881_DATA 0x000E2010
+#define DDRSS3_PHY_882_DATA 0x76543210
+#define DDRSS3_PHY_883_DATA 0x00000008
+#define DDRSS3_PHY_884_DATA 0x02800280
+#define DDRSS3_PHY_885_DATA 0x02800280
+#define DDRSS3_PHY_886_DATA 0x02800280
+#define DDRSS3_PHY_887_DATA 0x02800280
+#define DDRSS3_PHY_888_DATA 0x00000280
+#define DDRSS3_PHY_889_DATA 0x0000A000
+#define DDRSS3_PHY_890_DATA 0x00A000A0
+#define DDRSS3_PHY_891_DATA 0x00A000A0
+#define DDRSS3_PHY_892_DATA 0x00A000A0
+#define DDRSS3_PHY_893_DATA 0x00A000A0
+#define DDRSS3_PHY_894_DATA 0x00A000A0
+#define DDRSS3_PHY_895_DATA 0x00A000A0
+#define DDRSS3_PHY_896_DATA 0x00A000A0
+#define DDRSS3_PHY_897_DATA 0x00A000A0
+#define DDRSS3_PHY_898_DATA 0x01C200A0
+#define DDRSS3_PHY_899_DATA 0x01A00005
+#define DDRSS3_PHY_900_DATA 0x00000000
+#define DDRSS3_PHY_901_DATA 0x00000000
+#define DDRSS3_PHY_902_DATA 0x00080200
+#define DDRSS3_PHY_903_DATA 0x00000000
+#define DDRSS3_PHY_904_DATA 0x20202000
+#define DDRSS3_PHY_905_DATA 0x20202020
+#define DDRSS3_PHY_906_DATA 0xF0F02020
+#define DDRSS3_PHY_907_DATA 0x00000000
+#define DDRSS3_PHY_908_DATA 0x00000000
+#define DDRSS3_PHY_909_DATA 0x00000000
+#define DDRSS3_PHY_910_DATA 0x00000000
+#define DDRSS3_PHY_911_DATA 0x00000000
+#define DDRSS3_PHY_912_DATA 0x00000000
+#define DDRSS3_PHY_913_DATA 0x00000000
+#define DDRSS3_PHY_914_DATA 0x00000000
+#define DDRSS3_PHY_915_DATA 0x00000000
+#define DDRSS3_PHY_916_DATA 0x00000000
+#define DDRSS3_PHY_917_DATA 0x00000000
+#define DDRSS3_PHY_918_DATA 0x00000000
+#define DDRSS3_PHY_919_DATA 0x00000000
+#define DDRSS3_PHY_920_DATA 0x00000000
+#define DDRSS3_PHY_921_DATA 0x00000000
+#define DDRSS3_PHY_922_DATA 0x00000000
+#define DDRSS3_PHY_923_DATA 0x00000000
+#define DDRSS3_PHY_924_DATA 0x00000000
+#define DDRSS3_PHY_925_DATA 0x00000000
+#define DDRSS3_PHY_926_DATA 0x00000000
+#define DDRSS3_PHY_927_DATA 0x00000000
+#define DDRSS3_PHY_928_DATA 0x00000000
+#define DDRSS3_PHY_929_DATA 0x00000000
+#define DDRSS3_PHY_930_DATA 0x00000000
+#define DDRSS3_PHY_931_DATA 0x00000000
+#define DDRSS3_PHY_932_DATA 0x00000000
+#define DDRSS3_PHY_933_DATA 0x00000000
+#define DDRSS3_PHY_934_DATA 0x00000000
+#define DDRSS3_PHY_935_DATA 0x00000000
+#define DDRSS3_PHY_936_DATA 0x00000000
+#define DDRSS3_PHY_937_DATA 0x00000000
+#define DDRSS3_PHY_938_DATA 0x00000000
+#define DDRSS3_PHY_939_DATA 0x00000000
+#define DDRSS3_PHY_940_DATA 0x00000000
+#define DDRSS3_PHY_941_DATA 0x00000000
+#define DDRSS3_PHY_942_DATA 0x00000000
+#define DDRSS3_PHY_943_DATA 0x00000000
+#define DDRSS3_PHY_944_DATA 0x00000000
+#define DDRSS3_PHY_945_DATA 0x00000000
+#define DDRSS3_PHY_946_DATA 0x00000000
+#define DDRSS3_PHY_947_DATA 0x00000000
+#define DDRSS3_PHY_948_DATA 0x00000000
+#define DDRSS3_PHY_949_DATA 0x00000000
+#define DDRSS3_PHY_950_DATA 0x00000000
+#define DDRSS3_PHY_951_DATA 0x00000000
+#define DDRSS3_PHY_952_DATA 0x00000000
+#define DDRSS3_PHY_953_DATA 0x00000000
+#define DDRSS3_PHY_954_DATA 0x00000000
+#define DDRSS3_PHY_955_DATA 0x00000000
+#define DDRSS3_PHY_956_DATA 0x00000000
+#define DDRSS3_PHY_957_DATA 0x00000000
+#define DDRSS3_PHY_958_DATA 0x00000000
+#define DDRSS3_PHY_959_DATA 0x00000000
+#define DDRSS3_PHY_960_DATA 0x00000000
+#define DDRSS3_PHY_961_DATA 0x00000000
+#define DDRSS3_PHY_962_DATA 0x00000000
+#define DDRSS3_PHY_963_DATA 0x00000000
+#define DDRSS3_PHY_964_DATA 0x00000000
+#define DDRSS3_PHY_965_DATA 0x00000000
+#define DDRSS3_PHY_966_DATA 0x00000000
+#define DDRSS3_PHY_967_DATA 0x00000000
+#define DDRSS3_PHY_968_DATA 0x00000000
+#define DDRSS3_PHY_969_DATA 0x00000000
+#define DDRSS3_PHY_970_DATA 0x00000000
+#define DDRSS3_PHY_971_DATA 0x00000000
+#define DDRSS3_PHY_972_DATA 0x00000000
+#define DDRSS3_PHY_973_DATA 0x00000000
+#define DDRSS3_PHY_974_DATA 0x00000000
+#define DDRSS3_PHY_975_DATA 0x00000000
+#define DDRSS3_PHY_976_DATA 0x00000000
+#define DDRSS3_PHY_977_DATA 0x00000000
+#define DDRSS3_PHY_978_DATA 0x00000000
+#define DDRSS3_PHY_979_DATA 0x00000000
+#define DDRSS3_PHY_980_DATA 0x00000000
+#define DDRSS3_PHY_981_DATA 0x00000000
+#define DDRSS3_PHY_982_DATA 0x00000000
+#define DDRSS3_PHY_983_DATA 0x00000000
+#define DDRSS3_PHY_984_DATA 0x00000000
+#define DDRSS3_PHY_985_DATA 0x00000000
+#define DDRSS3_PHY_986_DATA 0x00000000
+#define DDRSS3_PHY_987_DATA 0x00000000
+#define DDRSS3_PHY_988_DATA 0x00000000
+#define DDRSS3_PHY_989_DATA 0x00000000
+#define DDRSS3_PHY_990_DATA 0x00000000
+#define DDRSS3_PHY_991_DATA 0x00000000
+#define DDRSS3_PHY_992_DATA 0x00000000
+#define DDRSS3_PHY_993_DATA 0x00000000
+#define DDRSS3_PHY_994_DATA 0x00000000
+#define DDRSS3_PHY_995_DATA 0x00000000
+#define DDRSS3_PHY_996_DATA 0x00000000
+#define DDRSS3_PHY_997_DATA 0x00000000
+#define DDRSS3_PHY_998_DATA 0x00000000
+#define DDRSS3_PHY_999_DATA 0x00000000
+#define DDRSS3_PHY_1000_DATA 0x00000000
+#define DDRSS3_PHY_1001_DATA 0x00000000
+#define DDRSS3_PHY_1002_DATA 0x00000000
+#define DDRSS3_PHY_1003_DATA 0x00000000
+#define DDRSS3_PHY_1004_DATA 0x00000000
+#define DDRSS3_PHY_1005_DATA 0x00000000
+#define DDRSS3_PHY_1006_DATA 0x00000000
+#define DDRSS3_PHY_1007_DATA 0x00000000
+#define DDRSS3_PHY_1008_DATA 0x00000000
+#define DDRSS3_PHY_1009_DATA 0x00000000
+#define DDRSS3_PHY_1010_DATA 0x00000000
+#define DDRSS3_PHY_1011_DATA 0x00000000
+#define DDRSS3_PHY_1012_DATA 0x00000000
+#define DDRSS3_PHY_1013_DATA 0x00000000
+#define DDRSS3_PHY_1014_DATA 0x00000000
+#define DDRSS3_PHY_1015_DATA 0x00000000
+#define DDRSS3_PHY_1016_DATA 0x00000000
+#define DDRSS3_PHY_1017_DATA 0x00000000
+#define DDRSS3_PHY_1018_DATA 0x00000000
+#define DDRSS3_PHY_1019_DATA 0x00000000
+#define DDRSS3_PHY_1020_DATA 0x00000000
+#define DDRSS3_PHY_1021_DATA 0x00000000
+#define DDRSS3_PHY_1022_DATA 0x00000000
+#define DDRSS3_PHY_1023_DATA 0x00000000
+#define DDRSS3_PHY_1024_DATA 0x00000000
+#define DDRSS3_PHY_1025_DATA 0x00000000
+#define DDRSS3_PHY_1026_DATA 0x00000000
+#define DDRSS3_PHY_1027_DATA 0x00000000
+#define DDRSS3_PHY_1028_DATA 0x00000000
+#define DDRSS3_PHY_1029_DATA 0x00000100
+#define DDRSS3_PHY_1030_DATA 0x00000200
+#define DDRSS3_PHY_1031_DATA 0x00000000
+#define DDRSS3_PHY_1032_DATA 0x00000000
+#define DDRSS3_PHY_1033_DATA 0x00000000
+#define DDRSS3_PHY_1034_DATA 0x00000000
+#define DDRSS3_PHY_1035_DATA 0x00400000
+#define DDRSS3_PHY_1036_DATA 0x00000080
+#define DDRSS3_PHY_1037_DATA 0x00DCBA98
+#define DDRSS3_PHY_1038_DATA 0x03000000
+#define DDRSS3_PHY_1039_DATA 0x00200000
+#define DDRSS3_PHY_1040_DATA 0x00000000
+#define DDRSS3_PHY_1041_DATA 0x00000000
+#define DDRSS3_PHY_1042_DATA 0x00000000
+#define DDRSS3_PHY_1043_DATA 0x00000000
+#define DDRSS3_PHY_1044_DATA 0x00000000
+#define DDRSS3_PHY_1045_DATA 0x0000002A
+#define DDRSS3_PHY_1046_DATA 0x00000015
+#define DDRSS3_PHY_1047_DATA 0x00000015
+#define DDRSS3_PHY_1048_DATA 0x0000002A
+#define DDRSS3_PHY_1049_DATA 0x00000033
+#define DDRSS3_PHY_1050_DATA 0x0000000C
+#define DDRSS3_PHY_1051_DATA 0x0000000C
+#define DDRSS3_PHY_1052_DATA 0x00000033
+#define DDRSS3_PHY_1053_DATA 0x00543210
+#define DDRSS3_PHY_1054_DATA 0x003F0000
+#define DDRSS3_PHY_1055_DATA 0x000F013F
+#define DDRSS3_PHY_1056_DATA 0x20202003
+#define DDRSS3_PHY_1057_DATA 0x00202020
+#define DDRSS3_PHY_1058_DATA 0x20008008
+#define DDRSS3_PHY_1059_DATA 0x00000810
+#define DDRSS3_PHY_1060_DATA 0x00000F00
+#define DDRSS3_PHY_1061_DATA 0x00000000
+#define DDRSS3_PHY_1062_DATA 0x00000000
+#define DDRSS3_PHY_1063_DATA 0x00000000
+#define DDRSS3_PHY_1064_DATA 0x000305CC
+#define DDRSS3_PHY_1065_DATA 0x00030000
+#define DDRSS3_PHY_1066_DATA 0x00000300
+#define DDRSS3_PHY_1067_DATA 0x00000300
+#define DDRSS3_PHY_1068_DATA 0x00000300
+#define DDRSS3_PHY_1069_DATA 0x00000300
+#define DDRSS3_PHY_1070_DATA 0x00000300
+#define DDRSS3_PHY_1071_DATA 0x42080010
+#define DDRSS3_PHY_1072_DATA 0x0000803E
+#define DDRSS3_PHY_1073_DATA 0x00000001
+#define DDRSS3_PHY_1074_DATA 0x01000102
+#define DDRSS3_PHY_1075_DATA 0x00008000
+#define DDRSS3_PHY_1076_DATA 0x00000000
+#define DDRSS3_PHY_1077_DATA 0x00000000
+#define DDRSS3_PHY_1078_DATA 0x00000000
+#define DDRSS3_PHY_1079_DATA 0x00000000
+#define DDRSS3_PHY_1080_DATA 0x00000000
+#define DDRSS3_PHY_1081_DATA 0x00000000
+#define DDRSS3_PHY_1082_DATA 0x00000000
+#define DDRSS3_PHY_1083_DATA 0x00000000
+#define DDRSS3_PHY_1084_DATA 0x00000000
+#define DDRSS3_PHY_1085_DATA 0x00000000
+#define DDRSS3_PHY_1086_DATA 0x00000000
+#define DDRSS3_PHY_1087_DATA 0x00000000
+#define DDRSS3_PHY_1088_DATA 0x00000000
+#define DDRSS3_PHY_1089_DATA 0x00000000
+#define DDRSS3_PHY_1090_DATA 0x00000000
+#define DDRSS3_PHY_1091_DATA 0x00000000
+#define DDRSS3_PHY_1092_DATA 0x00000000
+#define DDRSS3_PHY_1093_DATA 0x00000000
+#define DDRSS3_PHY_1094_DATA 0x00000000
+#define DDRSS3_PHY_1095_DATA 0x00000000
+#define DDRSS3_PHY_1096_DATA 0x00000000
+#define DDRSS3_PHY_1097_DATA 0x00000000
+#define DDRSS3_PHY_1098_DATA 0x00000000
+#define DDRSS3_PHY_1099_DATA 0x00000000
+#define DDRSS3_PHY_1100_DATA 0x00000000
+#define DDRSS3_PHY_1101_DATA 0x00000000
+#define DDRSS3_PHY_1102_DATA 0x00000000
+#define DDRSS3_PHY_1103_DATA 0x00000000
+#define DDRSS3_PHY_1104_DATA 0x00000000
+#define DDRSS3_PHY_1105_DATA 0x00000000
+#define DDRSS3_PHY_1106_DATA 0x00000000
+#define DDRSS3_PHY_1107_DATA 0x00000000
+#define DDRSS3_PHY_1108_DATA 0x00000000
+#define DDRSS3_PHY_1109_DATA 0x00000000
+#define DDRSS3_PHY_1110_DATA 0x00000000
+#define DDRSS3_PHY_1111_DATA 0x00000000
+#define DDRSS3_PHY_1112_DATA 0x00000000
+#define DDRSS3_PHY_1113_DATA 0x00000000
+#define DDRSS3_PHY_1114_DATA 0x00000000
+#define DDRSS3_PHY_1115_DATA 0x00000000
+#define DDRSS3_PHY_1116_DATA 0x00000000
+#define DDRSS3_PHY_1117_DATA 0x00000000
+#define DDRSS3_PHY_1118_DATA 0x00000000
+#define DDRSS3_PHY_1119_DATA 0x00000000
+#define DDRSS3_PHY_1120_DATA 0x00000000
+#define DDRSS3_PHY_1121_DATA 0x00000000
+#define DDRSS3_PHY_1122_DATA 0x00000000
+#define DDRSS3_PHY_1123_DATA 0x00000000
+#define DDRSS3_PHY_1124_DATA 0x00000000
+#define DDRSS3_PHY_1125_DATA 0x00000000
+#define DDRSS3_PHY_1126_DATA 0x00000000
+#define DDRSS3_PHY_1127_DATA 0x00000000
+#define DDRSS3_PHY_1128_DATA 0x00000000
+#define DDRSS3_PHY_1129_DATA 0x00000000
+#define DDRSS3_PHY_1130_DATA 0x00000000
+#define DDRSS3_PHY_1131_DATA 0x00000000
+#define DDRSS3_PHY_1132_DATA 0x00000000
+#define DDRSS3_PHY_1133_DATA 0x00000000
+#define DDRSS3_PHY_1134_DATA 0x00000000
+#define DDRSS3_PHY_1135_DATA 0x00000000
+#define DDRSS3_PHY_1136_DATA 0x00000000
+#define DDRSS3_PHY_1137_DATA 0x00000000
+#define DDRSS3_PHY_1138_DATA 0x00000000
+#define DDRSS3_PHY_1139_DATA 0x00000000
+#define DDRSS3_PHY_1140_DATA 0x00000000
+#define DDRSS3_PHY_1141_DATA 0x00000000
+#define DDRSS3_PHY_1142_DATA 0x00000000
+#define DDRSS3_PHY_1143_DATA 0x00000000
+#define DDRSS3_PHY_1144_DATA 0x00000000
+#define DDRSS3_PHY_1145_DATA 0x00000000
+#define DDRSS3_PHY_1146_DATA 0x00000000
+#define DDRSS3_PHY_1147_DATA 0x00000000
+#define DDRSS3_PHY_1148_DATA 0x00000000
+#define DDRSS3_PHY_1149_DATA 0x00000000
+#define DDRSS3_PHY_1150_DATA 0x00000000
+#define DDRSS3_PHY_1151_DATA 0x00000000
+#define DDRSS3_PHY_1152_DATA 0x00000000
+#define DDRSS3_PHY_1153_DATA 0x00000000
+#define DDRSS3_PHY_1154_DATA 0x00000000
+#define DDRSS3_PHY_1155_DATA 0x00000000
+#define DDRSS3_PHY_1156_DATA 0x00000000
+#define DDRSS3_PHY_1157_DATA 0x00000000
+#define DDRSS3_PHY_1158_DATA 0x00000000
+#define DDRSS3_PHY_1159_DATA 0x00000000
+#define DDRSS3_PHY_1160_DATA 0x00000000
+#define DDRSS3_PHY_1161_DATA 0x00000000
+#define DDRSS3_PHY_1162_DATA 0x00000000
+#define DDRSS3_PHY_1163_DATA 0x00000000
+#define DDRSS3_PHY_1164_DATA 0x00000000
+#define DDRSS3_PHY_1165_DATA 0x00000000
+#define DDRSS3_PHY_1166_DATA 0x00000000
+#define DDRSS3_PHY_1167_DATA 0x00000000
+#define DDRSS3_PHY_1168_DATA 0x00000000
+#define DDRSS3_PHY_1169_DATA 0x00000000
+#define DDRSS3_PHY_1170_DATA 0x00000000
+#define DDRSS3_PHY_1171_DATA 0x00000000
+#define DDRSS3_PHY_1172_DATA 0x00000000
+#define DDRSS3_PHY_1173_DATA 0x00000000
+#define DDRSS3_PHY_1174_DATA 0x00000000
+#define DDRSS3_PHY_1175_DATA 0x00000000
+#define DDRSS3_PHY_1176_DATA 0x00000000
+#define DDRSS3_PHY_1177_DATA 0x00000000
+#define DDRSS3_PHY_1178_DATA 0x00000000
+#define DDRSS3_PHY_1179_DATA 0x00000000
+#define DDRSS3_PHY_1180_DATA 0x00000000
+#define DDRSS3_PHY_1181_DATA 0x00000000
+#define DDRSS3_PHY_1182_DATA 0x00000000
+#define DDRSS3_PHY_1183_DATA 0x00000000
+#define DDRSS3_PHY_1184_DATA 0x00000000
+#define DDRSS3_PHY_1185_DATA 0x00000000
+#define DDRSS3_PHY_1186_DATA 0x00000000
+#define DDRSS3_PHY_1187_DATA 0x00000000
+#define DDRSS3_PHY_1188_DATA 0x00000000
+#define DDRSS3_PHY_1189_DATA 0x00000000
+#define DDRSS3_PHY_1190_DATA 0x00000000
+#define DDRSS3_PHY_1191_DATA 0x00000000
+#define DDRSS3_PHY_1192_DATA 0x00000000
+#define DDRSS3_PHY_1193_DATA 0x00000000
+#define DDRSS3_PHY_1194_DATA 0x00000000
+#define DDRSS3_PHY_1195_DATA 0x00000000
+#define DDRSS3_PHY_1196_DATA 0x00000000
+#define DDRSS3_PHY_1197_DATA 0x00000000
+#define DDRSS3_PHY_1198_DATA 0x00000000
+#define DDRSS3_PHY_1199_DATA 0x00000000
+#define DDRSS3_PHY_1200_DATA 0x00000000
+#define DDRSS3_PHY_1201_DATA 0x00000000
+#define DDRSS3_PHY_1202_DATA 0x00000000
+#define DDRSS3_PHY_1203_DATA 0x00000000
+#define DDRSS3_PHY_1204_DATA 0x00000000
+#define DDRSS3_PHY_1205_DATA 0x00000000
+#define DDRSS3_PHY_1206_DATA 0x00000000
+#define DDRSS3_PHY_1207_DATA 0x00000000
+#define DDRSS3_PHY_1208_DATA 0x00000000
+#define DDRSS3_PHY_1209_DATA 0x00000000
+#define DDRSS3_PHY_1210_DATA 0x00000000
+#define DDRSS3_PHY_1211_DATA 0x00000000
+#define DDRSS3_PHY_1212_DATA 0x00000000
+#define DDRSS3_PHY_1213_DATA 0x00000000
+#define DDRSS3_PHY_1214_DATA 0x00000000
+#define DDRSS3_PHY_1215_DATA 0x00000000
+#define DDRSS3_PHY_1216_DATA 0x00000000
+#define DDRSS3_PHY_1217_DATA 0x00000000
+#define DDRSS3_PHY_1218_DATA 0x00000000
+#define DDRSS3_PHY_1219_DATA 0x00000000
+#define DDRSS3_PHY_1220_DATA 0x00000000
+#define DDRSS3_PHY_1221_DATA 0x00000000
+#define DDRSS3_PHY_1222_DATA 0x00000000
+#define DDRSS3_PHY_1223_DATA 0x00000000
+#define DDRSS3_PHY_1224_DATA 0x00000000
+#define DDRSS3_PHY_1225_DATA 0x00000000
+#define DDRSS3_PHY_1226_DATA 0x00000000
+#define DDRSS3_PHY_1227_DATA 0x00000000
+#define DDRSS3_PHY_1228_DATA 0x00000000
+#define DDRSS3_PHY_1229_DATA 0x00000000
+#define DDRSS3_PHY_1230_DATA 0x00000000
+#define DDRSS3_PHY_1231_DATA 0x00000000
+#define DDRSS3_PHY_1232_DATA 0x00000000
+#define DDRSS3_PHY_1233_DATA 0x00000000
+#define DDRSS3_PHY_1234_DATA 0x00000000
+#define DDRSS3_PHY_1235_DATA 0x00000000
+#define DDRSS3_PHY_1236_DATA 0x00000000
+#define DDRSS3_PHY_1237_DATA 0x00000000
+#define DDRSS3_PHY_1238_DATA 0x00000000
+#define DDRSS3_PHY_1239_DATA 0x00000000
+#define DDRSS3_PHY_1240_DATA 0x00000000
+#define DDRSS3_PHY_1241_DATA 0x00000000
+#define DDRSS3_PHY_1242_DATA 0x00000000
+#define DDRSS3_PHY_1243_DATA 0x00000000
+#define DDRSS3_PHY_1244_DATA 0x00000000
+#define DDRSS3_PHY_1245_DATA 0x00000000
+#define DDRSS3_PHY_1246_DATA 0x00000000
+#define DDRSS3_PHY_1247_DATA 0x00000000
+#define DDRSS3_PHY_1248_DATA 0x00000000
+#define DDRSS3_PHY_1249_DATA 0x00000000
+#define DDRSS3_PHY_1250_DATA 0x00000000
+#define DDRSS3_PHY_1251_DATA 0x00000000
+#define DDRSS3_PHY_1252_DATA 0x00000000
+#define DDRSS3_PHY_1253_DATA 0x00000000
+#define DDRSS3_PHY_1254_DATA 0x00000000
+#define DDRSS3_PHY_1255_DATA 0x00000000
+#define DDRSS3_PHY_1256_DATA 0x00000000
+#define DDRSS3_PHY_1257_DATA 0x00000000
+#define DDRSS3_PHY_1258_DATA 0x00000000
+#define DDRSS3_PHY_1259_DATA 0x00000000
+#define DDRSS3_PHY_1260_DATA 0x00000000
+#define DDRSS3_PHY_1261_DATA 0x00000000
+#define DDRSS3_PHY_1262_DATA 0x00000000
+#define DDRSS3_PHY_1263_DATA 0x00000000
+#define DDRSS3_PHY_1264_DATA 0x00000000
+#define DDRSS3_PHY_1265_DATA 0x00000000
+#define DDRSS3_PHY_1266_DATA 0x00000000
+#define DDRSS3_PHY_1267_DATA 0x00000000
+#define DDRSS3_PHY_1268_DATA 0x00000000
+#define DDRSS3_PHY_1269_DATA 0x00000000
+#define DDRSS3_PHY_1270_DATA 0x00000000
+#define DDRSS3_PHY_1271_DATA 0x00000000
+#define DDRSS3_PHY_1272_DATA 0x00000000
+#define DDRSS3_PHY_1273_DATA 0x00000000
+#define DDRSS3_PHY_1274_DATA 0x00000000
+#define DDRSS3_PHY_1275_DATA 0x00000000
+#define DDRSS3_PHY_1276_DATA 0x00000000
+#define DDRSS3_PHY_1277_DATA 0x00000000
+#define DDRSS3_PHY_1278_DATA 0x00000000
+#define DDRSS3_PHY_1279_DATA 0x00000000
+#define DDRSS3_PHY_1280_DATA 0x00000000
+#define DDRSS3_PHY_1281_DATA 0x00010100
+#define DDRSS3_PHY_1282_DATA 0x00000000
+#define DDRSS3_PHY_1283_DATA 0x00000000
+#define DDRSS3_PHY_1284_DATA 0x00050000
+#define DDRSS3_PHY_1285_DATA 0x04000000
+#define DDRSS3_PHY_1286_DATA 0x00000055
+#define DDRSS3_PHY_1287_DATA 0x00000000
+#define DDRSS3_PHY_1288_DATA 0x00000000
+#define DDRSS3_PHY_1289_DATA 0x00000000
+#define DDRSS3_PHY_1290_DATA 0x00000000
+#define DDRSS3_PHY_1291_DATA 0x00002001
+#define DDRSS3_PHY_1292_DATA 0x0000400F
+#define DDRSS3_PHY_1293_DATA 0x50020028
+#define DDRSS3_PHY_1294_DATA 0x01010000
+#define DDRSS3_PHY_1295_DATA 0x80080001
+#define DDRSS3_PHY_1296_DATA 0x10200000
+#define DDRSS3_PHY_1297_DATA 0x00000008
+#define DDRSS3_PHY_1298_DATA 0x00000000
+#define DDRSS3_PHY_1299_DATA 0x01090E00
+#define DDRSS3_PHY_1300_DATA 0x00040101
+#define DDRSS3_PHY_1301_DATA 0x0000010F
+#define DDRSS3_PHY_1302_DATA 0x00000000
+#define DDRSS3_PHY_1303_DATA 0x0000FFFF
+#define DDRSS3_PHY_1304_DATA 0x00000000
+#define DDRSS3_PHY_1305_DATA 0x01010000
+#define DDRSS3_PHY_1306_DATA 0x01080402
+#define DDRSS3_PHY_1307_DATA 0x01200F02
+#define DDRSS3_PHY_1308_DATA 0x00194280
+#define DDRSS3_PHY_1309_DATA 0x00000004
+#define DDRSS3_PHY_1310_DATA 0x00042000
+#define DDRSS3_PHY_1311_DATA 0x00000000
+#define DDRSS3_PHY_1312_DATA 0x00000000
+#define DDRSS3_PHY_1313_DATA 0x00000000
+#define DDRSS3_PHY_1314_DATA 0x00000000
+#define DDRSS3_PHY_1315_DATA 0x00000000
+#define DDRSS3_PHY_1316_DATA 0x00000000
+#define DDRSS3_PHY_1317_DATA 0x01000000
+#define DDRSS3_PHY_1318_DATA 0x00000705
+#define DDRSS3_PHY_1319_DATA 0x00000054
+#define DDRSS3_PHY_1320_DATA 0x00030820
+#define DDRSS3_PHY_1321_DATA 0x00010820
+#define DDRSS3_PHY_1322_DATA 0x00010820
+#define DDRSS3_PHY_1323_DATA 0x00010820
+#define DDRSS3_PHY_1324_DATA 0x00010820
+#define DDRSS3_PHY_1325_DATA 0x00010820
+#define DDRSS3_PHY_1326_DATA 0x00010820
+#define DDRSS3_PHY_1327_DATA 0x00010820
+#define DDRSS3_PHY_1328_DATA 0x00010820
+#define DDRSS3_PHY_1329_DATA 0x00000000
+#define DDRSS3_PHY_1330_DATA 0x00000074
+#define DDRSS3_PHY_1331_DATA 0x00000400
+#define DDRSS3_PHY_1332_DATA 0x00000108
+#define DDRSS3_PHY_1333_DATA 0x00000000
+#define DDRSS3_PHY_1334_DATA 0x00000000
+#define DDRSS3_PHY_1335_DATA 0x00000000
+#define DDRSS3_PHY_1336_DATA 0x00000000
+#define DDRSS3_PHY_1337_DATA 0x00000000
+#define DDRSS3_PHY_1338_DATA 0x03000000
+#define DDRSS3_PHY_1339_DATA 0x00000000
+#define DDRSS3_PHY_1340_DATA 0x00000000
+#define DDRSS3_PHY_1341_DATA 0x00000000
+#define DDRSS3_PHY_1342_DATA 0x04102006
+#define DDRSS3_PHY_1343_DATA 0x00041020
+#define DDRSS3_PHY_1344_DATA 0x01C98C98
+#define DDRSS3_PHY_1345_DATA 0x3F400000
+#define DDRSS3_PHY_1346_DATA 0x3F3F1F3F
+#define DDRSS3_PHY_1347_DATA 0x0000001F
+#define DDRSS3_PHY_1348_DATA 0x00000000
+#define DDRSS3_PHY_1349_DATA 0x00000000
+#define DDRSS3_PHY_1350_DATA 0x00000000
+#define DDRSS3_PHY_1351_DATA 0x00010000
+#define DDRSS3_PHY_1352_DATA 0x00000000
+#define DDRSS3_PHY_1353_DATA 0x00000000
+#define DDRSS3_PHY_1354_DATA 0x00000000
+#define DDRSS3_PHY_1355_DATA 0x00000000
+#define DDRSS3_PHY_1356_DATA 0x76543210
+#define DDRSS3_PHY_1357_DATA 0x00010198
+#define DDRSS3_PHY_1358_DATA 0x00000000
+#define DDRSS3_PHY_1359_DATA 0x00000000
+#define DDRSS3_PHY_1360_DATA 0x00000000
+#define DDRSS3_PHY_1361_DATA 0x00040700
+#define DDRSS3_PHY_1362_DATA 0x00000000
+#define DDRSS3_PHY_1363_DATA 0x00000000
+#define DDRSS3_PHY_1364_DATA 0x00000000
+#define DDRSS3_PHY_1365_DATA 0x00000000
+#define DDRSS3_PHY_1366_DATA 0x00000000
+#define DDRSS3_PHY_1367_DATA 0x00000002
+#define DDRSS3_PHY_1368_DATA 0x00000000
+#define DDRSS3_PHY_1369_DATA 0x00000000
+#define DDRSS3_PHY_1370_DATA 0x00000000
+#define DDRSS3_PHY_1371_DATA 0x00000000
+#define DDRSS3_PHY_1372_DATA 0x00000000
+#define DDRSS3_PHY_1373_DATA 0x00000000
+#define DDRSS3_PHY_1374_DATA 0x00080000
+#define DDRSS3_PHY_1375_DATA 0x000007FF
+#define DDRSS3_PHY_1376_DATA 0x00000000
+#define DDRSS3_PHY_1377_DATA 0x00000000
+#define DDRSS3_PHY_1378_DATA 0x00000000
+#define DDRSS3_PHY_1379_DATA 0x00000000
+#define DDRSS3_PHY_1380_DATA 0x00000000
+#define DDRSS3_PHY_1381_DATA 0x00000000
+#define DDRSS3_PHY_1382_DATA 0x000FFFFF
+#define DDRSS3_PHY_1383_DATA 0x000FFFFF
+#define DDRSS3_PHY_1384_DATA 0x0000FFFF
+#define DDRSS3_PHY_1385_DATA 0xFFFFFFF0
+#define DDRSS3_PHY_1386_DATA 0x030FFFFF
+#define DDRSS3_PHY_1387_DATA 0x01FFFFFF
+#define DDRSS3_PHY_1388_DATA 0x0000FFFF
+#define DDRSS3_PHY_1389_DATA 0x00000000
+#define DDRSS3_PHY_1390_DATA 0x00000000
+#define DDRSS3_PHY_1391_DATA 0x00000000
+#define DDRSS3_PHY_1392_DATA 0x00000000
+#define DDRSS3_PHY_1393_DATA 0x0001F7C0
+#define DDRSS3_PHY_1394_DATA 0x00000003
+#define DDRSS3_PHY_1395_DATA 0x00000000
+#define DDRSS3_PHY_1396_DATA 0x00001142
+#define DDRSS3_PHY_1397_DATA 0x010207AB
+#define DDRSS3_PHY_1398_DATA 0x01000080
+#define DDRSS3_PHY_1399_DATA 0x03900390
+#define DDRSS3_PHY_1400_DATA 0x03900390
+#define DDRSS3_PHY_1401_DATA 0x00000390
+#define DDRSS3_PHY_1402_DATA 0x00000390
+#define DDRSS3_PHY_1403_DATA 0x00000390
+#define DDRSS3_PHY_1404_DATA 0x00000390
+#define DDRSS3_PHY_1405_DATA 0x00000005
+#define DDRSS3_PHY_1406_DATA 0x01813FCC
+#define DDRSS3_PHY_1407_DATA 0x000000CC
+#define DDRSS3_PHY_1408_DATA 0x0C000DFF
+#define DDRSS3_PHY_1409_DATA 0x30000DFF
+#define DDRSS3_PHY_1410_DATA 0x3F0DFF11
+#define DDRSS3_PHY_1411_DATA 0x000100F0
+#define DDRSS3_PHY_1412_DATA 0x780DFFCC
+#define DDRSS3_PHY_1413_DATA 0x00007E31
+#define DDRSS3_PHY_1414_DATA 0x000CBF11
+#define DDRSS3_PHY_1415_DATA 0x01990010
+#define DDRSS3_PHY_1416_DATA 0x000CBF11
+#define DDRSS3_PHY_1417_DATA 0x01990010
+#define DDRSS3_PHY_1418_DATA 0x3F0DFF11
+#define DDRSS3_PHY_1419_DATA 0x00EF00F0
+#define DDRSS3_PHY_1420_DATA 0x3F0DFF11
+#define DDRSS3_PHY_1421_DATA 0x01FF00F0
+#define DDRSS3_PHY_1422_DATA 0x20040006
diff --git a/arch/arm/dts/k3-j784s4-ddr.dtsi b/arch/arm/dts/k3-j784s4-ddr.dtsi
new file mode 100644
index 0000000000..69f5bbe6fc
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-ddr.dtsi
@@ -0,0 +1,8858 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&main_navss {
+ ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr
+ <0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg
+ <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
+ <0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg
+ <0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg
+ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+
+ msmc0: msmc {
+ compatible = "ti,j721s2-msmc";
+ intrlv-gran = <MULTI_DDR_CFG_INTRLV_GRAN>;
+ intrlv-size = <MULTI_DDR_CFG_INTRLV_SIZE>;
+ ecc-enable = <MULTI_DDR_CFG_ECC_ENABLE>;
+ emif-config = <MULTI_DDR_CFG_HYBRID_SELECT>;
+ emif-active = <MULTI_DDR_CFG_EMIFS_ACTIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ u-boot,dm-spl;
+
+ memorycontroller0: memorycontroller@2990000 {
+ compatible = "ti,j721s2-ddrss";
+ reg = <0x0 0x02990000 0x0 0x4000>,
+ <0x0 0x0114000 0x0 0x100>;
+ reg-names = "cfg", "ctrl_mmr_lp4";
+ power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
+ <&k3_pds 131 TI_SCI_PD_SHARED>;
+ clocks = <&k3_clks 191 1>, <&k3_clks 78 2>;
+ ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+ ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+ ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+ ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+ instance = <0>;
+
+ u-boot,dm-spl;
+
+ ti,ctl-data = <
+ DDRSS0_CTL_00_DATA
+ DDRSS0_CTL_01_DATA
+ DDRSS0_CTL_02_DATA
+ DDRSS0_CTL_03_DATA
+ DDRSS0_CTL_04_DATA
+ DDRSS0_CTL_05_DATA
+ DDRSS0_CTL_06_DATA
+ DDRSS0_CTL_07_DATA
+ DDRSS0_CTL_08_DATA
+ DDRSS0_CTL_09_DATA
+ DDRSS0_CTL_10_DATA
+ DDRSS0_CTL_11_DATA
+ DDRSS0_CTL_12_DATA
+ DDRSS0_CTL_13_DATA
+ DDRSS0_CTL_14_DATA
+ DDRSS0_CTL_15_DATA
+ DDRSS0_CTL_16_DATA
+ DDRSS0_CTL_17_DATA
+ DDRSS0_CTL_18_DATA
+ DDRSS0_CTL_19_DATA
+ DDRSS0_CTL_20_DATA
+ DDRSS0_CTL_21_DATA
+ DDRSS0_CTL_22_DATA
+ DDRSS0_CTL_23_DATA
+ DDRSS0_CTL_24_DATA
+ DDRSS0_CTL_25_DATA
+ DDRSS0_CTL_26_DATA
+ DDRSS0_CTL_27_DATA
+ DDRSS0_CTL_28_DATA
+ DDRSS0_CTL_29_DATA
+ DDRSS0_CTL_30_DATA
+ DDRSS0_CTL_31_DATA
+ DDRSS0_CTL_32_DATA
+ DDRSS0_CTL_33_DATA
+ DDRSS0_CTL_34_DATA
+ DDRSS0_CTL_35_DATA
+ DDRSS0_CTL_36_DATA
+ DDRSS0_CTL_37_DATA
+ DDRSS0_CTL_38_DATA
+ DDRSS0_CTL_39_DATA
+ DDRSS0_CTL_40_DATA
+ DDRSS0_CTL_41_DATA
+ DDRSS0_CTL_42_DATA
+ DDRSS0_CTL_43_DATA
+ DDRSS0_CTL_44_DATA
+ DDRSS0_CTL_45_DATA
+ DDRSS0_CTL_46_DATA
+ DDRSS0_CTL_47_DATA
+ DDRSS0_CTL_48_DATA
+ DDRSS0_CTL_49_DATA
+ DDRSS0_CTL_50_DATA
+ DDRSS0_CTL_51_DATA
+ DDRSS0_CTL_52_DATA
+ DDRSS0_CTL_53_DATA
+ DDRSS0_CTL_54_DATA
+ DDRSS0_CTL_55_DATA
+ DDRSS0_CTL_56_DATA
+ DDRSS0_CTL_57_DATA
+ DDRSS0_CTL_58_DATA
+ DDRSS0_CTL_59_DATA
+ DDRSS0_CTL_60_DATA
+ DDRSS0_CTL_61_DATA
+ DDRSS0_CTL_62_DATA
+ DDRSS0_CTL_63_DATA
+ DDRSS0_CTL_64_DATA
+ DDRSS0_CTL_65_DATA
+ DDRSS0_CTL_66_DATA
+ DDRSS0_CTL_67_DATA
+ DDRSS0_CTL_68_DATA
+ DDRSS0_CTL_69_DATA
+ DDRSS0_CTL_70_DATA
+ DDRSS0_CTL_71_DATA
+ DDRSS0_CTL_72_DATA
+ DDRSS0_CTL_73_DATA
+ DDRSS0_CTL_74_DATA
+ DDRSS0_CTL_75_DATA
+ DDRSS0_CTL_76_DATA
+ DDRSS0_CTL_77_DATA
+ DDRSS0_CTL_78_DATA
+ DDRSS0_CTL_79_DATA
+ DDRSS0_CTL_80_DATA
+ DDRSS0_CTL_81_DATA
+ DDRSS0_CTL_82_DATA
+ DDRSS0_CTL_83_DATA
+ DDRSS0_CTL_84_DATA
+ DDRSS0_CTL_85_DATA
+ DDRSS0_CTL_86_DATA
+ DDRSS0_CTL_87_DATA
+ DDRSS0_CTL_88_DATA
+ DDRSS0_CTL_89_DATA
+ DDRSS0_CTL_90_DATA
+ DDRSS0_CTL_91_DATA
+ DDRSS0_CTL_92_DATA
+ DDRSS0_CTL_93_DATA
+ DDRSS0_CTL_94_DATA
+ DDRSS0_CTL_95_DATA
+ DDRSS0_CTL_96_DATA
+ DDRSS0_CTL_97_DATA
+ DDRSS0_CTL_98_DATA
+ DDRSS0_CTL_99_DATA
+ DDRSS0_CTL_100_DATA
+ DDRSS0_CTL_101_DATA
+ DDRSS0_CTL_102_DATA
+ DDRSS0_CTL_103_DATA
+ DDRSS0_CTL_104_DATA
+ DDRSS0_CTL_105_DATA
+ DDRSS0_CTL_106_DATA
+ DDRSS0_CTL_107_DATA
+ DDRSS0_CTL_108_DATA
+ DDRSS0_CTL_109_DATA
+ DDRSS0_CTL_110_DATA
+ DDRSS0_CTL_111_DATA
+ DDRSS0_CTL_112_DATA
+ DDRSS0_CTL_113_DATA
+ DDRSS0_CTL_114_DATA
+ DDRSS0_CTL_115_DATA
+ DDRSS0_CTL_116_DATA
+ DDRSS0_CTL_117_DATA
+ DDRSS0_CTL_118_DATA
+ DDRSS0_CTL_119_DATA
+ DDRSS0_CTL_120_DATA
+ DDRSS0_CTL_121_DATA
+ DDRSS0_CTL_122_DATA
+ DDRSS0_CTL_123_DATA
+ DDRSS0_CTL_124_DATA
+ DDRSS0_CTL_125_DATA
+ DDRSS0_CTL_126_DATA
+ DDRSS0_CTL_127_DATA
+ DDRSS0_CTL_128_DATA
+ DDRSS0_CTL_129_DATA
+ DDRSS0_CTL_130_DATA
+ DDRSS0_CTL_131_DATA
+ DDRSS0_CTL_132_DATA
+ DDRSS0_CTL_133_DATA
+ DDRSS0_CTL_134_DATA
+ DDRSS0_CTL_135_DATA
+ DDRSS0_CTL_136_DATA
+ DDRSS0_CTL_137_DATA
+ DDRSS0_CTL_138_DATA
+ DDRSS0_CTL_139_DATA
+ DDRSS0_CTL_140_DATA
+ DDRSS0_CTL_141_DATA
+ DDRSS0_CTL_142_DATA
+ DDRSS0_CTL_143_DATA
+ DDRSS0_CTL_144_DATA
+ DDRSS0_CTL_145_DATA
+ DDRSS0_CTL_146_DATA
+ DDRSS0_CTL_147_DATA
+ DDRSS0_CTL_148_DATA
+ DDRSS0_CTL_149_DATA
+ DDRSS0_CTL_150_DATA
+ DDRSS0_CTL_151_DATA
+ DDRSS0_CTL_152_DATA
+ DDRSS0_CTL_153_DATA
+ DDRSS0_CTL_154_DATA
+ DDRSS0_CTL_155_DATA
+ DDRSS0_CTL_156_DATA
+ DDRSS0_CTL_157_DATA
+ DDRSS0_CTL_158_DATA
+ DDRSS0_CTL_159_DATA
+ DDRSS0_CTL_160_DATA
+ DDRSS0_CTL_161_DATA
+ DDRSS0_CTL_162_DATA
+ DDRSS0_CTL_163_DATA
+ DDRSS0_CTL_164_DATA
+ DDRSS0_CTL_165_DATA
+ DDRSS0_CTL_166_DATA
+ DDRSS0_CTL_167_DATA
+ DDRSS0_CTL_168_DATA
+ DDRSS0_CTL_169_DATA
+ DDRSS0_CTL_170_DATA
+ DDRSS0_CTL_171_DATA
+ DDRSS0_CTL_172_DATA
+ DDRSS0_CTL_173_DATA
+ DDRSS0_CTL_174_DATA
+ DDRSS0_CTL_175_DATA
+ DDRSS0_CTL_176_DATA
+ DDRSS0_CTL_177_DATA
+ DDRSS0_CTL_178_DATA
+ DDRSS0_CTL_179_DATA
+ DDRSS0_CTL_180_DATA
+ DDRSS0_CTL_181_DATA
+ DDRSS0_CTL_182_DATA
+ DDRSS0_CTL_183_DATA
+ DDRSS0_CTL_184_DATA
+ DDRSS0_CTL_185_DATA
+ DDRSS0_CTL_186_DATA
+ DDRSS0_CTL_187_DATA
+ DDRSS0_CTL_188_DATA
+ DDRSS0_CTL_189_DATA
+ DDRSS0_CTL_190_DATA
+ DDRSS0_CTL_191_DATA
+ DDRSS0_CTL_192_DATA
+ DDRSS0_CTL_193_DATA
+ DDRSS0_CTL_194_DATA
+ DDRSS0_CTL_195_DATA
+ DDRSS0_CTL_196_DATA
+ DDRSS0_CTL_197_DATA
+ DDRSS0_CTL_198_DATA
+ DDRSS0_CTL_199_DATA
+ DDRSS0_CTL_200_DATA
+ DDRSS0_CTL_201_DATA
+ DDRSS0_CTL_202_DATA
+ DDRSS0_CTL_203_DATA
+ DDRSS0_CTL_204_DATA
+ DDRSS0_CTL_205_DATA
+ DDRSS0_CTL_206_DATA
+ DDRSS0_CTL_207_DATA
+ DDRSS0_CTL_208_DATA
+ DDRSS0_CTL_209_DATA
+ DDRSS0_CTL_210_DATA
+ DDRSS0_CTL_211_DATA
+ DDRSS0_CTL_212_DATA
+ DDRSS0_CTL_213_DATA
+ DDRSS0_CTL_214_DATA
+ DDRSS0_CTL_215_DATA
+ DDRSS0_CTL_216_DATA
+ DDRSS0_CTL_217_DATA
+ DDRSS0_CTL_218_DATA
+ DDRSS0_CTL_219_DATA
+ DDRSS0_CTL_220_DATA
+ DDRSS0_CTL_221_DATA
+ DDRSS0_CTL_222_DATA
+ DDRSS0_CTL_223_DATA
+ DDRSS0_CTL_224_DATA
+ DDRSS0_CTL_225_DATA
+ DDRSS0_CTL_226_DATA
+ DDRSS0_CTL_227_DATA
+ DDRSS0_CTL_228_DATA
+ DDRSS0_CTL_229_DATA
+ DDRSS0_CTL_230_DATA
+ DDRSS0_CTL_231_DATA
+ DDRSS0_CTL_232_DATA
+ DDRSS0_CTL_233_DATA
+ DDRSS0_CTL_234_DATA
+ DDRSS0_CTL_235_DATA
+ DDRSS0_CTL_236_DATA
+ DDRSS0_CTL_237_DATA
+ DDRSS0_CTL_238_DATA
+ DDRSS0_CTL_239_DATA
+ DDRSS0_CTL_240_DATA
+ DDRSS0_CTL_241_DATA
+ DDRSS0_CTL_242_DATA
+ DDRSS0_CTL_243_DATA
+ DDRSS0_CTL_244_DATA
+ DDRSS0_CTL_245_DATA
+ DDRSS0_CTL_246_DATA
+ DDRSS0_CTL_247_DATA
+ DDRSS0_CTL_248_DATA
+ DDRSS0_CTL_249_DATA
+ DDRSS0_CTL_250_DATA
+ DDRSS0_CTL_251_DATA
+ DDRSS0_CTL_252_DATA
+ DDRSS0_CTL_253_DATA
+ DDRSS0_CTL_254_DATA
+ DDRSS0_CTL_255_DATA
+ DDRSS0_CTL_256_DATA
+ DDRSS0_CTL_257_DATA
+ DDRSS0_CTL_258_DATA
+ DDRSS0_CTL_259_DATA
+ DDRSS0_CTL_260_DATA
+ DDRSS0_CTL_261_DATA
+ DDRSS0_CTL_262_DATA
+ DDRSS0_CTL_263_DATA
+ DDRSS0_CTL_264_DATA
+ DDRSS0_CTL_265_DATA
+ DDRSS0_CTL_266_DATA
+ DDRSS0_CTL_267_DATA
+ DDRSS0_CTL_268_DATA
+ DDRSS0_CTL_269_DATA
+ DDRSS0_CTL_270_DATA
+ DDRSS0_CTL_271_DATA
+ DDRSS0_CTL_272_DATA
+ DDRSS0_CTL_273_DATA
+ DDRSS0_CTL_274_DATA
+ DDRSS0_CTL_275_DATA
+ DDRSS0_CTL_276_DATA
+ DDRSS0_CTL_277_DATA
+ DDRSS0_CTL_278_DATA
+ DDRSS0_CTL_279_DATA
+ DDRSS0_CTL_280_DATA
+ DDRSS0_CTL_281_DATA
+ DDRSS0_CTL_282_DATA
+ DDRSS0_CTL_283_DATA
+ DDRSS0_CTL_284_DATA
+ DDRSS0_CTL_285_DATA
+ DDRSS0_CTL_286_DATA
+ DDRSS0_CTL_287_DATA
+ DDRSS0_CTL_288_DATA
+ DDRSS0_CTL_289_DATA
+ DDRSS0_CTL_290_DATA
+ DDRSS0_CTL_291_DATA
+ DDRSS0_CTL_292_DATA
+ DDRSS0_CTL_293_DATA
+ DDRSS0_CTL_294_DATA
+ DDRSS0_CTL_295_DATA
+ DDRSS0_CTL_296_DATA
+ DDRSS0_CTL_297_DATA
+ DDRSS0_CTL_298_DATA
+ DDRSS0_CTL_299_DATA
+ DDRSS0_CTL_300_DATA
+ DDRSS0_CTL_301_DATA
+ DDRSS0_CTL_302_DATA
+ DDRSS0_CTL_303_DATA
+ DDRSS0_CTL_304_DATA
+ DDRSS0_CTL_305_DATA
+ DDRSS0_CTL_306_DATA
+ DDRSS0_CTL_307_DATA
+ DDRSS0_CTL_308_DATA
+ DDRSS0_CTL_309_DATA
+ DDRSS0_CTL_310_DATA
+ DDRSS0_CTL_311_DATA
+ DDRSS0_CTL_312_DATA
+ DDRSS0_CTL_313_DATA
+ DDRSS0_CTL_314_DATA
+ DDRSS0_CTL_315_DATA
+ DDRSS0_CTL_316_DATA
+ DDRSS0_CTL_317_DATA
+ DDRSS0_CTL_318_DATA
+ DDRSS0_CTL_319_DATA
+ DDRSS0_CTL_320_DATA
+ DDRSS0_CTL_321_DATA
+ DDRSS0_CTL_322_DATA
+ DDRSS0_CTL_323_DATA
+ DDRSS0_CTL_324_DATA
+ DDRSS0_CTL_325_DATA
+ DDRSS0_CTL_326_DATA
+ DDRSS0_CTL_327_DATA
+ DDRSS0_CTL_328_DATA
+ DDRSS0_CTL_329_DATA
+ DDRSS0_CTL_330_DATA
+ DDRSS0_CTL_331_DATA
+ DDRSS0_CTL_332_DATA
+ DDRSS0_CTL_333_DATA
+ DDRSS0_CTL_334_DATA
+ DDRSS0_CTL_335_DATA
+ DDRSS0_CTL_336_DATA
+ DDRSS0_CTL_337_DATA
+ DDRSS0_CTL_338_DATA
+ DDRSS0_CTL_339_DATA
+ DDRSS0_CTL_340_DATA
+ DDRSS0_CTL_341_DATA
+ DDRSS0_CTL_342_DATA
+ DDRSS0_CTL_343_DATA
+ DDRSS0_CTL_344_DATA
+ DDRSS0_CTL_345_DATA
+ DDRSS0_CTL_346_DATA
+ DDRSS0_CTL_347_DATA
+ DDRSS0_CTL_348_DATA
+ DDRSS0_CTL_349_DATA
+ DDRSS0_CTL_350_DATA
+ DDRSS0_CTL_351_DATA
+ DDRSS0_CTL_352_DATA
+ DDRSS0_CTL_353_DATA
+ DDRSS0_CTL_354_DATA
+ DDRSS0_CTL_355_DATA
+ DDRSS0_CTL_356_DATA
+ DDRSS0_CTL_357_DATA
+ DDRSS0_CTL_358_DATA
+ DDRSS0_CTL_359_DATA
+ DDRSS0_CTL_360_DATA
+ DDRSS0_CTL_361_DATA
+ DDRSS0_CTL_362_DATA
+ DDRSS0_CTL_363_DATA
+ DDRSS0_CTL_364_DATA
+ DDRSS0_CTL_365_DATA
+ DDRSS0_CTL_366_DATA
+ DDRSS0_CTL_367_DATA
+ DDRSS0_CTL_368_DATA
+ DDRSS0_CTL_369_DATA
+ DDRSS0_CTL_370_DATA
+ DDRSS0_CTL_371_DATA
+ DDRSS0_CTL_372_DATA
+ DDRSS0_CTL_373_DATA
+ DDRSS0_CTL_374_DATA
+ DDRSS0_CTL_375_DATA
+ DDRSS0_CTL_376_DATA
+ DDRSS0_CTL_377_DATA
+ DDRSS0_CTL_378_DATA
+ DDRSS0_CTL_379_DATA
+ DDRSS0_CTL_380_DATA
+ DDRSS0_CTL_381_DATA
+ DDRSS0_CTL_382_DATA
+ DDRSS0_CTL_383_DATA
+ DDRSS0_CTL_384_DATA
+ DDRSS0_CTL_385_DATA
+ DDRSS0_CTL_386_DATA
+ DDRSS0_CTL_387_DATA
+ DDRSS0_CTL_388_DATA
+ DDRSS0_CTL_389_DATA
+ DDRSS0_CTL_390_DATA
+ DDRSS0_CTL_391_DATA
+ DDRSS0_CTL_392_DATA
+ DDRSS0_CTL_393_DATA
+ DDRSS0_CTL_394_DATA
+ DDRSS0_CTL_395_DATA
+ DDRSS0_CTL_396_DATA
+ DDRSS0_CTL_397_DATA
+ DDRSS0_CTL_398_DATA
+ DDRSS0_CTL_399_DATA
+ DDRSS0_CTL_400_DATA
+ DDRSS0_CTL_401_DATA
+ DDRSS0_CTL_402_DATA
+ DDRSS0_CTL_403_DATA
+ DDRSS0_CTL_404_DATA
+ DDRSS0_CTL_405_DATA
+ DDRSS0_CTL_406_DATA
+ DDRSS0_CTL_407_DATA
+ DDRSS0_CTL_408_DATA
+ DDRSS0_CTL_409_DATA
+ DDRSS0_CTL_410_DATA
+ DDRSS0_CTL_411_DATA
+ DDRSS0_CTL_412_DATA
+ DDRSS0_CTL_413_DATA
+ DDRSS0_CTL_414_DATA
+ DDRSS0_CTL_415_DATA
+ DDRSS0_CTL_416_DATA
+ DDRSS0_CTL_417_DATA
+ DDRSS0_CTL_418_DATA
+ DDRSS0_CTL_419_DATA
+ DDRSS0_CTL_420_DATA
+ DDRSS0_CTL_421_DATA
+ DDRSS0_CTL_422_DATA
+ DDRSS0_CTL_423_DATA
+ DDRSS0_CTL_424_DATA
+ DDRSS0_CTL_425_DATA
+ DDRSS0_CTL_426_DATA
+ DDRSS0_CTL_427_DATA
+ DDRSS0_CTL_428_DATA
+ DDRSS0_CTL_429_DATA
+ DDRSS0_CTL_430_DATA
+ DDRSS0_CTL_431_DATA
+ DDRSS0_CTL_432_DATA
+ DDRSS0_CTL_433_DATA
+ DDRSS0_CTL_434_DATA
+ DDRSS0_CTL_435_DATA
+ DDRSS0_CTL_436_DATA
+ DDRSS0_CTL_437_DATA
+ DDRSS0_CTL_438_DATA
+ DDRSS0_CTL_439_DATA
+ DDRSS0_CTL_440_DATA
+ DDRSS0_CTL_441_DATA
+ DDRSS0_CTL_442_DATA
+ DDRSS0_CTL_443_DATA
+ DDRSS0_CTL_444_DATA
+ DDRSS0_CTL_445_DATA
+ DDRSS0_CTL_446_DATA
+ DDRSS0_CTL_447_DATA
+ DDRSS0_CTL_448_DATA
+ DDRSS0_CTL_449_DATA
+ DDRSS0_CTL_450_DATA
+ DDRSS0_CTL_451_DATA
+ DDRSS0_CTL_452_DATA
+ DDRSS0_CTL_453_DATA
+ DDRSS0_CTL_454_DATA
+ DDRSS0_CTL_455_DATA
+ DDRSS0_CTL_456_DATA
+ DDRSS0_CTL_457_DATA
+ DDRSS0_CTL_458_DATA
+ >;
+
+ ti,pi-data = <
+ DDRSS0_PI_00_DATA
+ DDRSS0_PI_01_DATA
+ DDRSS0_PI_02_DATA
+ DDRSS0_PI_03_DATA
+ DDRSS0_PI_04_DATA
+ DDRSS0_PI_05_DATA
+ DDRSS0_PI_06_DATA
+ DDRSS0_PI_07_DATA
+ DDRSS0_PI_08_DATA
+ DDRSS0_PI_09_DATA
+ DDRSS0_PI_10_DATA
+ DDRSS0_PI_11_DATA
+ DDRSS0_PI_12_DATA
+ DDRSS0_PI_13_DATA
+ DDRSS0_PI_14_DATA
+ DDRSS0_PI_15_DATA
+ DDRSS0_PI_16_DATA
+ DDRSS0_PI_17_DATA
+ DDRSS0_PI_18_DATA
+ DDRSS0_PI_19_DATA
+ DDRSS0_PI_20_DATA
+ DDRSS0_PI_21_DATA
+ DDRSS0_PI_22_DATA
+ DDRSS0_PI_23_DATA
+ DDRSS0_PI_24_DATA
+ DDRSS0_PI_25_DATA
+ DDRSS0_PI_26_DATA
+ DDRSS0_PI_27_DATA
+ DDRSS0_PI_28_DATA
+ DDRSS0_PI_29_DATA
+ DDRSS0_PI_30_DATA
+ DDRSS0_PI_31_DATA
+ DDRSS0_PI_32_DATA
+ DDRSS0_PI_33_DATA
+ DDRSS0_PI_34_DATA
+ DDRSS0_PI_35_DATA
+ DDRSS0_PI_36_DATA
+ DDRSS0_PI_37_DATA
+ DDRSS0_PI_38_DATA
+ DDRSS0_PI_39_DATA
+ DDRSS0_PI_40_DATA
+ DDRSS0_PI_41_DATA
+ DDRSS0_PI_42_DATA
+ DDRSS0_PI_43_DATA
+ DDRSS0_PI_44_DATA
+ DDRSS0_PI_45_DATA
+ DDRSS0_PI_46_DATA
+ DDRSS0_PI_47_DATA
+ DDRSS0_PI_48_DATA
+ DDRSS0_PI_49_DATA
+ DDRSS0_PI_50_DATA
+ DDRSS0_PI_51_DATA
+ DDRSS0_PI_52_DATA
+ DDRSS0_PI_53_DATA
+ DDRSS0_PI_54_DATA
+ DDRSS0_PI_55_DATA
+ DDRSS0_PI_56_DATA
+ DDRSS0_PI_57_DATA
+ DDRSS0_PI_58_DATA
+ DDRSS0_PI_59_DATA
+ DDRSS0_PI_60_DATA
+ DDRSS0_PI_61_DATA
+ DDRSS0_PI_62_DATA
+ DDRSS0_PI_63_DATA
+ DDRSS0_PI_64_DATA
+ DDRSS0_PI_65_DATA
+ DDRSS0_PI_66_DATA
+ DDRSS0_PI_67_DATA
+ DDRSS0_PI_68_DATA
+ DDRSS0_PI_69_DATA
+ DDRSS0_PI_70_DATA
+ DDRSS0_PI_71_DATA
+ DDRSS0_PI_72_DATA
+ DDRSS0_PI_73_DATA
+ DDRSS0_PI_74_DATA
+ DDRSS0_PI_75_DATA
+ DDRSS0_PI_76_DATA
+ DDRSS0_PI_77_DATA
+ DDRSS0_PI_78_DATA
+ DDRSS0_PI_79_DATA
+ DDRSS0_PI_80_DATA
+ DDRSS0_PI_81_DATA
+ DDRSS0_PI_82_DATA
+ DDRSS0_PI_83_DATA
+ DDRSS0_PI_84_DATA
+ DDRSS0_PI_85_DATA
+ DDRSS0_PI_86_DATA
+ DDRSS0_PI_87_DATA
+ DDRSS0_PI_88_DATA
+ DDRSS0_PI_89_DATA
+ DDRSS0_PI_90_DATA
+ DDRSS0_PI_91_DATA
+ DDRSS0_PI_92_DATA
+ DDRSS0_PI_93_DATA
+ DDRSS0_PI_94_DATA
+ DDRSS0_PI_95_DATA
+ DDRSS0_PI_96_DATA
+ DDRSS0_PI_97_DATA
+ DDRSS0_PI_98_DATA
+ DDRSS0_PI_99_DATA
+ DDRSS0_PI_100_DATA
+ DDRSS0_PI_101_DATA
+ DDRSS0_PI_102_DATA
+ DDRSS0_PI_103_DATA
+ DDRSS0_PI_104_DATA
+ DDRSS0_PI_105_DATA
+ DDRSS0_PI_106_DATA
+ DDRSS0_PI_107_DATA
+ DDRSS0_PI_108_DATA
+ DDRSS0_PI_109_DATA
+ DDRSS0_PI_110_DATA
+ DDRSS0_PI_111_DATA
+ DDRSS0_PI_112_DATA
+ DDRSS0_PI_113_DATA
+ DDRSS0_PI_114_DATA
+ DDRSS0_PI_115_DATA
+ DDRSS0_PI_116_DATA
+ DDRSS0_PI_117_DATA
+ DDRSS0_PI_118_DATA
+ DDRSS0_PI_119_DATA
+ DDRSS0_PI_120_DATA
+ DDRSS0_PI_121_DATA
+ DDRSS0_PI_122_DATA
+ DDRSS0_PI_123_DATA
+ DDRSS0_PI_124_DATA
+ DDRSS0_PI_125_DATA
+ DDRSS0_PI_126_DATA
+ DDRSS0_PI_127_DATA
+ DDRSS0_PI_128_DATA
+ DDRSS0_PI_129_DATA
+ DDRSS0_PI_130_DATA
+ DDRSS0_PI_131_DATA
+ DDRSS0_PI_132_DATA
+ DDRSS0_PI_133_DATA
+ DDRSS0_PI_134_DATA
+ DDRSS0_PI_135_DATA
+ DDRSS0_PI_136_DATA
+ DDRSS0_PI_137_DATA
+ DDRSS0_PI_138_DATA
+ DDRSS0_PI_139_DATA
+ DDRSS0_PI_140_DATA
+ DDRSS0_PI_141_DATA
+ DDRSS0_PI_142_DATA
+ DDRSS0_PI_143_DATA
+ DDRSS0_PI_144_DATA
+ DDRSS0_PI_145_DATA
+ DDRSS0_PI_146_DATA
+ DDRSS0_PI_147_DATA
+ DDRSS0_PI_148_DATA
+ DDRSS0_PI_149_DATA
+ DDRSS0_PI_150_DATA
+ DDRSS0_PI_151_DATA
+ DDRSS0_PI_152_DATA
+ DDRSS0_PI_153_DATA
+ DDRSS0_PI_154_DATA
+ DDRSS0_PI_155_DATA
+ DDRSS0_PI_156_DATA
+ DDRSS0_PI_157_DATA
+ DDRSS0_PI_158_DATA
+ DDRSS0_PI_159_DATA
+ DDRSS0_PI_160_DATA
+ DDRSS0_PI_161_DATA
+ DDRSS0_PI_162_DATA
+ DDRSS0_PI_163_DATA
+ DDRSS0_PI_164_DATA
+ DDRSS0_PI_165_DATA
+ DDRSS0_PI_166_DATA
+ DDRSS0_PI_167_DATA
+ DDRSS0_PI_168_DATA
+ DDRSS0_PI_169_DATA
+ DDRSS0_PI_170_DATA
+ DDRSS0_PI_171_DATA
+ DDRSS0_PI_172_DATA
+ DDRSS0_PI_173_DATA
+ DDRSS0_PI_174_DATA
+ DDRSS0_PI_175_DATA
+ DDRSS0_PI_176_DATA
+ DDRSS0_PI_177_DATA
+ DDRSS0_PI_178_DATA
+ DDRSS0_PI_179_DATA
+ DDRSS0_PI_180_DATA
+ DDRSS0_PI_181_DATA
+ DDRSS0_PI_182_DATA
+ DDRSS0_PI_183_DATA
+ DDRSS0_PI_184_DATA
+ DDRSS0_PI_185_DATA
+ DDRSS0_PI_186_DATA
+ DDRSS0_PI_187_DATA
+ DDRSS0_PI_188_DATA
+ DDRSS0_PI_189_DATA
+ DDRSS0_PI_190_DATA
+ DDRSS0_PI_191_DATA
+ DDRSS0_PI_192_DATA
+ DDRSS0_PI_193_DATA
+ DDRSS0_PI_194_DATA
+ DDRSS0_PI_195_DATA
+ DDRSS0_PI_196_DATA
+ DDRSS0_PI_197_DATA
+ DDRSS0_PI_198_DATA
+ DDRSS0_PI_199_DATA
+ DDRSS0_PI_200_DATA
+ DDRSS0_PI_201_DATA
+ DDRSS0_PI_202_DATA
+ DDRSS0_PI_203_DATA
+ DDRSS0_PI_204_DATA
+ DDRSS0_PI_205_DATA
+ DDRSS0_PI_206_DATA
+ DDRSS0_PI_207_DATA
+ DDRSS0_PI_208_DATA
+ DDRSS0_PI_209_DATA
+ DDRSS0_PI_210_DATA
+ DDRSS0_PI_211_DATA
+ DDRSS0_PI_212_DATA
+ DDRSS0_PI_213_DATA
+ DDRSS0_PI_214_DATA
+ DDRSS0_PI_215_DATA
+ DDRSS0_PI_216_DATA
+ DDRSS0_PI_217_DATA
+ DDRSS0_PI_218_DATA
+ DDRSS0_PI_219_DATA
+ DDRSS0_PI_220_DATA
+ DDRSS0_PI_221_DATA
+ DDRSS0_PI_222_DATA
+ DDRSS0_PI_223_DATA
+ DDRSS0_PI_224_DATA
+ DDRSS0_PI_225_DATA
+ DDRSS0_PI_226_DATA
+ DDRSS0_PI_227_DATA
+ DDRSS0_PI_228_DATA
+ DDRSS0_PI_229_DATA
+ DDRSS0_PI_230_DATA
+ DDRSS0_PI_231_DATA
+ DDRSS0_PI_232_DATA
+ DDRSS0_PI_233_DATA
+ DDRSS0_PI_234_DATA
+ DDRSS0_PI_235_DATA
+ DDRSS0_PI_236_DATA
+ DDRSS0_PI_237_DATA
+ DDRSS0_PI_238_DATA
+ DDRSS0_PI_239_DATA
+ DDRSS0_PI_240_DATA
+ DDRSS0_PI_241_DATA
+ DDRSS0_PI_242_DATA
+ DDRSS0_PI_243_DATA
+ DDRSS0_PI_244_DATA
+ DDRSS0_PI_245_DATA
+ DDRSS0_PI_246_DATA
+ DDRSS0_PI_247_DATA
+ DDRSS0_PI_248_DATA
+ DDRSS0_PI_249_DATA
+ DDRSS0_PI_250_DATA
+ DDRSS0_PI_251_DATA
+ DDRSS0_PI_252_DATA
+ DDRSS0_PI_253_DATA
+ DDRSS0_PI_254_DATA
+ DDRSS0_PI_255_DATA
+ DDRSS0_PI_256_DATA
+ DDRSS0_PI_257_DATA
+ DDRSS0_PI_258_DATA
+ DDRSS0_PI_259_DATA
+ DDRSS0_PI_260_DATA
+ DDRSS0_PI_261_DATA
+ DDRSS0_PI_262_DATA
+ DDRSS0_PI_263_DATA
+ DDRSS0_PI_264_DATA
+ DDRSS0_PI_265_DATA
+ DDRSS0_PI_266_DATA
+ DDRSS0_PI_267_DATA
+ DDRSS0_PI_268_DATA
+ DDRSS0_PI_269_DATA
+ DDRSS0_PI_270_DATA
+ DDRSS0_PI_271_DATA
+ DDRSS0_PI_272_DATA
+ DDRSS0_PI_273_DATA
+ DDRSS0_PI_274_DATA
+ DDRSS0_PI_275_DATA
+ DDRSS0_PI_276_DATA
+ DDRSS0_PI_277_DATA
+ DDRSS0_PI_278_DATA
+ DDRSS0_PI_279_DATA
+ DDRSS0_PI_280_DATA
+ DDRSS0_PI_281_DATA
+ DDRSS0_PI_282_DATA
+ DDRSS0_PI_283_DATA
+ DDRSS0_PI_284_DATA
+ DDRSS0_PI_285_DATA
+ DDRSS0_PI_286_DATA
+ DDRSS0_PI_287_DATA
+ DDRSS0_PI_288_DATA
+ DDRSS0_PI_289_DATA
+ DDRSS0_PI_290_DATA
+ DDRSS0_PI_291_DATA
+ DDRSS0_PI_292_DATA
+ DDRSS0_PI_293_DATA
+ DDRSS0_PI_294_DATA
+ DDRSS0_PI_295_DATA
+ DDRSS0_PI_296_DATA
+ DDRSS0_PI_297_DATA
+ DDRSS0_PI_298_DATA
+ DDRSS0_PI_299_DATA
+ >;
+
+ ti,phy-data = <
+ DDRSS0_PHY_00_DATA
+ DDRSS0_PHY_01_DATA
+ DDRSS0_PHY_02_DATA
+ DDRSS0_PHY_03_DATA
+ DDRSS0_PHY_04_DATA
+ DDRSS0_PHY_05_DATA
+ DDRSS0_PHY_06_DATA
+ DDRSS0_PHY_07_DATA
+ DDRSS0_PHY_08_DATA
+ DDRSS0_PHY_09_DATA
+ DDRSS0_PHY_10_DATA
+ DDRSS0_PHY_11_DATA
+ DDRSS0_PHY_12_DATA
+ DDRSS0_PHY_13_DATA
+ DDRSS0_PHY_14_DATA
+ DDRSS0_PHY_15_DATA
+ DDRSS0_PHY_16_DATA
+ DDRSS0_PHY_17_DATA
+ DDRSS0_PHY_18_DATA
+ DDRSS0_PHY_19_DATA
+ DDRSS0_PHY_20_DATA
+ DDRSS0_PHY_21_DATA
+ DDRSS0_PHY_22_DATA
+ DDRSS0_PHY_23_DATA
+ DDRSS0_PHY_24_DATA
+ DDRSS0_PHY_25_DATA
+ DDRSS0_PHY_26_DATA
+ DDRSS0_PHY_27_DATA
+ DDRSS0_PHY_28_DATA
+ DDRSS0_PHY_29_DATA
+ DDRSS0_PHY_30_DATA
+ DDRSS0_PHY_31_DATA
+ DDRSS0_PHY_32_DATA
+ DDRSS0_PHY_33_DATA
+ DDRSS0_PHY_34_DATA
+ DDRSS0_PHY_35_DATA
+ DDRSS0_PHY_36_DATA
+ DDRSS0_PHY_37_DATA
+ DDRSS0_PHY_38_DATA
+ DDRSS0_PHY_39_DATA
+ DDRSS0_PHY_40_DATA
+ DDRSS0_PHY_41_DATA
+ DDRSS0_PHY_42_DATA
+ DDRSS0_PHY_43_DATA
+ DDRSS0_PHY_44_DATA
+ DDRSS0_PHY_45_DATA
+ DDRSS0_PHY_46_DATA
+ DDRSS0_PHY_47_DATA
+ DDRSS0_PHY_48_DATA
+ DDRSS0_PHY_49_DATA
+ DDRSS0_PHY_50_DATA
+ DDRSS0_PHY_51_DATA
+ DDRSS0_PHY_52_DATA
+ DDRSS0_PHY_53_DATA
+ DDRSS0_PHY_54_DATA
+ DDRSS0_PHY_55_DATA
+ DDRSS0_PHY_56_DATA
+ DDRSS0_PHY_57_DATA
+ DDRSS0_PHY_58_DATA
+ DDRSS0_PHY_59_DATA
+ DDRSS0_PHY_60_DATA
+ DDRSS0_PHY_61_DATA
+ DDRSS0_PHY_62_DATA
+ DDRSS0_PHY_63_DATA
+ DDRSS0_PHY_64_DATA
+ DDRSS0_PHY_65_DATA
+ DDRSS0_PHY_66_DATA
+ DDRSS0_PHY_67_DATA
+ DDRSS0_PHY_68_DATA
+ DDRSS0_PHY_69_DATA
+ DDRSS0_PHY_70_DATA
+ DDRSS0_PHY_71_DATA
+ DDRSS0_PHY_72_DATA
+ DDRSS0_PHY_73_DATA
+ DDRSS0_PHY_74_DATA
+ DDRSS0_PHY_75_DATA
+ DDRSS0_PHY_76_DATA
+ DDRSS0_PHY_77_DATA
+ DDRSS0_PHY_78_DATA
+ DDRSS0_PHY_79_DATA
+ DDRSS0_PHY_80_DATA
+ DDRSS0_PHY_81_DATA
+ DDRSS0_PHY_82_DATA
+ DDRSS0_PHY_83_DATA
+ DDRSS0_PHY_84_DATA
+ DDRSS0_PHY_85_DATA
+ DDRSS0_PHY_86_DATA
+ DDRSS0_PHY_87_DATA
+ DDRSS0_PHY_88_DATA
+ DDRSS0_PHY_89_DATA
+ DDRSS0_PHY_90_DATA
+ DDRSS0_PHY_91_DATA
+ DDRSS0_PHY_92_DATA
+ DDRSS0_PHY_93_DATA
+ DDRSS0_PHY_94_DATA
+ DDRSS0_PHY_95_DATA
+ DDRSS0_PHY_96_DATA
+ DDRSS0_PHY_97_DATA
+ DDRSS0_PHY_98_DATA
+ DDRSS0_PHY_99_DATA
+ DDRSS0_PHY_100_DATA
+ DDRSS0_PHY_101_DATA
+ DDRSS0_PHY_102_DATA
+ DDRSS0_PHY_103_DATA
+ DDRSS0_PHY_104_DATA
+ DDRSS0_PHY_105_DATA
+ DDRSS0_PHY_106_DATA
+ DDRSS0_PHY_107_DATA
+ DDRSS0_PHY_108_DATA
+ DDRSS0_PHY_109_DATA
+ DDRSS0_PHY_110_DATA
+ DDRSS0_PHY_111_DATA
+ DDRSS0_PHY_112_DATA
+ DDRSS0_PHY_113_DATA
+ DDRSS0_PHY_114_DATA
+ DDRSS0_PHY_115_DATA
+ DDRSS0_PHY_116_DATA
+ DDRSS0_PHY_117_DATA
+ DDRSS0_PHY_118_DATA
+ DDRSS0_PHY_119_DATA
+ DDRSS0_PHY_120_DATA
+ DDRSS0_PHY_121_DATA
+ DDRSS0_PHY_122_DATA
+ DDRSS0_PHY_123_DATA
+ DDRSS0_PHY_124_DATA
+ DDRSS0_PHY_125_DATA
+ DDRSS0_PHY_126_DATA
+ DDRSS0_PHY_127_DATA
+ DDRSS0_PHY_128_DATA
+ DDRSS0_PHY_129_DATA
+ DDRSS0_PHY_130_DATA
+ DDRSS0_PHY_131_DATA
+ DDRSS0_PHY_132_DATA
+ DDRSS0_PHY_133_DATA
+ DDRSS0_PHY_134_DATA
+ DDRSS0_PHY_135_DATA
+ DDRSS0_PHY_136_DATA
+ DDRSS0_PHY_137_DATA
+ DDRSS0_PHY_138_DATA
+ DDRSS0_PHY_139_DATA
+ DDRSS0_PHY_140_DATA
+ DDRSS0_PHY_141_DATA
+ DDRSS0_PHY_142_DATA
+ DDRSS0_PHY_143_DATA
+ DDRSS0_PHY_144_DATA
+ DDRSS0_PHY_145_DATA
+ DDRSS0_PHY_146_DATA
+ DDRSS0_PHY_147_DATA
+ DDRSS0_PHY_148_DATA
+ DDRSS0_PHY_149_DATA
+ DDRSS0_PHY_150_DATA
+ DDRSS0_PHY_151_DATA
+ DDRSS0_PHY_152_DATA
+ DDRSS0_PHY_153_DATA
+ DDRSS0_PHY_154_DATA
+ DDRSS0_PHY_155_DATA
+ DDRSS0_PHY_156_DATA
+ DDRSS0_PHY_157_DATA
+ DDRSS0_PHY_158_DATA
+ DDRSS0_PHY_159_DATA
+ DDRSS0_PHY_160_DATA
+ DDRSS0_PHY_161_DATA
+ DDRSS0_PHY_162_DATA
+ DDRSS0_PHY_163_DATA
+ DDRSS0_PHY_164_DATA
+ DDRSS0_PHY_165_DATA
+ DDRSS0_PHY_166_DATA
+ DDRSS0_PHY_167_DATA
+ DDRSS0_PHY_168_DATA
+ DDRSS0_PHY_169_DATA
+ DDRSS0_PHY_170_DATA
+ DDRSS0_PHY_171_DATA
+ DDRSS0_PHY_172_DATA
+ DDRSS0_PHY_173_DATA
+ DDRSS0_PHY_174_DATA
+ DDRSS0_PHY_175_DATA
+ DDRSS0_PHY_176_DATA
+ DDRSS0_PHY_177_DATA
+ DDRSS0_PHY_178_DATA
+ DDRSS0_PHY_179_DATA
+ DDRSS0_PHY_180_DATA
+ DDRSS0_PHY_181_DATA
+ DDRSS0_PHY_182_DATA
+ DDRSS0_PHY_183_DATA
+ DDRSS0_PHY_184_DATA
+ DDRSS0_PHY_185_DATA
+ DDRSS0_PHY_186_DATA
+ DDRSS0_PHY_187_DATA
+ DDRSS0_PHY_188_DATA
+ DDRSS0_PHY_189_DATA
+ DDRSS0_PHY_190_DATA
+ DDRSS0_PHY_191_DATA
+ DDRSS0_PHY_192_DATA
+ DDRSS0_PHY_193_DATA
+ DDRSS0_PHY_194_DATA
+ DDRSS0_PHY_195_DATA
+ DDRSS0_PHY_196_DATA
+ DDRSS0_PHY_197_DATA
+ DDRSS0_PHY_198_DATA
+ DDRSS0_PHY_199_DATA
+ DDRSS0_PHY_200_DATA
+ DDRSS0_PHY_201_DATA
+ DDRSS0_PHY_202_DATA
+ DDRSS0_PHY_203_DATA
+ DDRSS0_PHY_204_DATA
+ DDRSS0_PHY_205_DATA
+ DDRSS0_PHY_206_DATA
+ DDRSS0_PHY_207_DATA
+ DDRSS0_PHY_208_DATA
+ DDRSS0_PHY_209_DATA
+ DDRSS0_PHY_210_DATA
+ DDRSS0_PHY_211_DATA
+ DDRSS0_PHY_212_DATA
+ DDRSS0_PHY_213_DATA
+ DDRSS0_PHY_214_DATA
+ DDRSS0_PHY_215_DATA
+ DDRSS0_PHY_216_DATA
+ DDRSS0_PHY_217_DATA
+ DDRSS0_PHY_218_DATA
+ DDRSS0_PHY_219_DATA
+ DDRSS0_PHY_220_DATA
+ DDRSS0_PHY_221_DATA
+ DDRSS0_PHY_222_DATA
+ DDRSS0_PHY_223_DATA
+ DDRSS0_PHY_224_DATA
+ DDRSS0_PHY_225_DATA
+ DDRSS0_PHY_226_DATA
+ DDRSS0_PHY_227_DATA
+ DDRSS0_PHY_228_DATA
+ DDRSS0_PHY_229_DATA
+ DDRSS0_PHY_230_DATA
+ DDRSS0_PHY_231_DATA
+ DDRSS0_PHY_232_DATA
+ DDRSS0_PHY_233_DATA
+ DDRSS0_PHY_234_DATA
+ DDRSS0_PHY_235_DATA
+ DDRSS0_PHY_236_DATA
+ DDRSS0_PHY_237_DATA
+ DDRSS0_PHY_238_DATA
+ DDRSS0_PHY_239_DATA
+ DDRSS0_PHY_240_DATA
+ DDRSS0_PHY_241_DATA
+ DDRSS0_PHY_242_DATA
+ DDRSS0_PHY_243_DATA
+ DDRSS0_PHY_244_DATA
+ DDRSS0_PHY_245_DATA
+ DDRSS0_PHY_246_DATA
+ DDRSS0_PHY_247_DATA
+ DDRSS0_PHY_248_DATA
+ DDRSS0_PHY_249_DATA
+ DDRSS0_PHY_250_DATA
+ DDRSS0_PHY_251_DATA
+ DDRSS0_PHY_252_DATA
+ DDRSS0_PHY_253_DATA
+ DDRSS0_PHY_254_DATA
+ DDRSS0_PHY_255_DATA
+ DDRSS0_PHY_256_DATA
+ DDRSS0_PHY_257_DATA
+ DDRSS0_PHY_258_DATA
+ DDRSS0_PHY_259_DATA
+ DDRSS0_PHY_260_DATA
+ DDRSS0_PHY_261_DATA
+ DDRSS0_PHY_262_DATA
+ DDRSS0_PHY_263_DATA
+ DDRSS0_PHY_264_DATA
+ DDRSS0_PHY_265_DATA
+ DDRSS0_PHY_266_DATA
+ DDRSS0_PHY_267_DATA
+ DDRSS0_PHY_268_DATA
+ DDRSS0_PHY_269_DATA
+ DDRSS0_PHY_270_DATA
+ DDRSS0_PHY_271_DATA
+ DDRSS0_PHY_272_DATA
+ DDRSS0_PHY_273_DATA
+ DDRSS0_PHY_274_DATA
+ DDRSS0_PHY_275_DATA
+ DDRSS0_PHY_276_DATA
+ DDRSS0_PHY_277_DATA
+ DDRSS0_PHY_278_DATA
+ DDRSS0_PHY_279_DATA
+ DDRSS0_PHY_280_DATA
+ DDRSS0_PHY_281_DATA
+ DDRSS0_PHY_282_DATA
+ DDRSS0_PHY_283_DATA
+ DDRSS0_PHY_284_DATA
+ DDRSS0_PHY_285_DATA
+ DDRSS0_PHY_286_DATA
+ DDRSS0_PHY_287_DATA
+ DDRSS0_PHY_288_DATA
+ DDRSS0_PHY_289_DATA
+ DDRSS0_PHY_290_DATA
+ DDRSS0_PHY_291_DATA
+ DDRSS0_PHY_292_DATA
+ DDRSS0_PHY_293_DATA
+ DDRSS0_PHY_294_DATA
+ DDRSS0_PHY_295_DATA
+ DDRSS0_PHY_296_DATA
+ DDRSS0_PHY_297_DATA
+ DDRSS0_PHY_298_DATA
+ DDRSS0_PHY_299_DATA
+ DDRSS0_PHY_300_DATA
+ DDRSS0_PHY_301_DATA
+ DDRSS0_PHY_302_DATA
+ DDRSS0_PHY_303_DATA
+ DDRSS0_PHY_304_DATA
+ DDRSS0_PHY_305_DATA
+ DDRSS0_PHY_306_DATA
+ DDRSS0_PHY_307_DATA
+ DDRSS0_PHY_308_DATA
+ DDRSS0_PHY_309_DATA
+ DDRSS0_PHY_310_DATA
+ DDRSS0_PHY_311_DATA
+ DDRSS0_PHY_312_DATA
+ DDRSS0_PHY_313_DATA
+ DDRSS0_PHY_314_DATA
+ DDRSS0_PHY_315_DATA
+ DDRSS0_PHY_316_DATA
+ DDRSS0_PHY_317_DATA
+ DDRSS0_PHY_318_DATA
+ DDRSS0_PHY_319_DATA
+ DDRSS0_PHY_320_DATA
+ DDRSS0_PHY_321_DATA
+ DDRSS0_PHY_322_DATA
+ DDRSS0_PHY_323_DATA
+ DDRSS0_PHY_324_DATA
+ DDRSS0_PHY_325_DATA
+ DDRSS0_PHY_326_DATA
+ DDRSS0_PHY_327_DATA
+ DDRSS0_PHY_328_DATA
+ DDRSS0_PHY_329_DATA
+ DDRSS0_PHY_330_DATA
+ DDRSS0_PHY_331_DATA
+ DDRSS0_PHY_332_DATA
+ DDRSS0_PHY_333_DATA
+ DDRSS0_PHY_334_DATA
+ DDRSS0_PHY_335_DATA
+ DDRSS0_PHY_336_DATA
+ DDRSS0_PHY_337_DATA
+ DDRSS0_PHY_338_DATA
+ DDRSS0_PHY_339_DATA
+ DDRSS0_PHY_340_DATA
+ DDRSS0_PHY_341_DATA
+ DDRSS0_PHY_342_DATA
+ DDRSS0_PHY_343_DATA
+ DDRSS0_PHY_344_DATA
+ DDRSS0_PHY_345_DATA
+ DDRSS0_PHY_346_DATA
+ DDRSS0_PHY_347_DATA
+ DDRSS0_PHY_348_DATA
+ DDRSS0_PHY_349_DATA
+ DDRSS0_PHY_350_DATA
+ DDRSS0_PHY_351_DATA
+ DDRSS0_PHY_352_DATA
+ DDRSS0_PHY_353_DATA
+ DDRSS0_PHY_354_DATA
+ DDRSS0_PHY_355_DATA
+ DDRSS0_PHY_356_DATA
+ DDRSS0_PHY_357_DATA
+ DDRSS0_PHY_358_DATA
+ DDRSS0_PHY_359_DATA
+ DDRSS0_PHY_360_DATA
+ DDRSS0_PHY_361_DATA
+ DDRSS0_PHY_362_DATA
+ DDRSS0_PHY_363_DATA
+ DDRSS0_PHY_364_DATA
+ DDRSS0_PHY_365_DATA
+ DDRSS0_PHY_366_DATA
+ DDRSS0_PHY_367_DATA
+ DDRSS0_PHY_368_DATA
+ DDRSS0_PHY_369_DATA
+ DDRSS0_PHY_370_DATA
+ DDRSS0_PHY_371_DATA
+ DDRSS0_PHY_372_DATA
+ DDRSS0_PHY_373_DATA
+ DDRSS0_PHY_374_DATA
+ DDRSS0_PHY_375_DATA
+ DDRSS0_PHY_376_DATA
+ DDRSS0_PHY_377_DATA
+ DDRSS0_PHY_378_DATA
+ DDRSS0_PHY_379_DATA
+ DDRSS0_PHY_380_DATA
+ DDRSS0_PHY_381_DATA
+ DDRSS0_PHY_382_DATA
+ DDRSS0_PHY_383_DATA
+ DDRSS0_PHY_384_DATA
+ DDRSS0_PHY_385_DATA
+ DDRSS0_PHY_386_DATA
+ DDRSS0_PHY_387_DATA
+ DDRSS0_PHY_388_DATA
+ DDRSS0_PHY_389_DATA
+ DDRSS0_PHY_390_DATA
+ DDRSS0_PHY_391_DATA
+ DDRSS0_PHY_392_DATA
+ DDRSS0_PHY_393_DATA
+ DDRSS0_PHY_394_DATA
+ DDRSS0_PHY_395_DATA
+ DDRSS0_PHY_396_DATA
+ DDRSS0_PHY_397_DATA
+ DDRSS0_PHY_398_DATA
+ DDRSS0_PHY_399_DATA
+ DDRSS0_PHY_400_DATA
+ DDRSS0_PHY_401_DATA
+ DDRSS0_PHY_402_DATA
+ DDRSS0_PHY_403_DATA
+ DDRSS0_PHY_404_DATA
+ DDRSS0_PHY_405_DATA
+ DDRSS0_PHY_406_DATA
+ DDRSS0_PHY_407_DATA
+ DDRSS0_PHY_408_DATA
+ DDRSS0_PHY_409_DATA
+ DDRSS0_PHY_410_DATA
+ DDRSS0_PHY_411_DATA
+ DDRSS0_PHY_412_DATA
+ DDRSS0_PHY_413_DATA
+ DDRSS0_PHY_414_DATA
+ DDRSS0_PHY_415_DATA
+ DDRSS0_PHY_416_DATA
+ DDRSS0_PHY_417_DATA
+ DDRSS0_PHY_418_DATA
+ DDRSS0_PHY_419_DATA
+ DDRSS0_PHY_420_DATA
+ DDRSS0_PHY_421_DATA
+ DDRSS0_PHY_422_DATA
+ DDRSS0_PHY_423_DATA
+ DDRSS0_PHY_424_DATA
+ DDRSS0_PHY_425_DATA
+ DDRSS0_PHY_426_DATA
+ DDRSS0_PHY_427_DATA
+ DDRSS0_PHY_428_DATA
+ DDRSS0_PHY_429_DATA
+ DDRSS0_PHY_430_DATA
+ DDRSS0_PHY_431_DATA
+ DDRSS0_PHY_432_DATA
+ DDRSS0_PHY_433_DATA
+ DDRSS0_PHY_434_DATA
+ DDRSS0_PHY_435_DATA
+ DDRSS0_PHY_436_DATA
+ DDRSS0_PHY_437_DATA
+ DDRSS0_PHY_438_DATA
+ DDRSS0_PHY_439_DATA
+ DDRSS0_PHY_440_DATA
+ DDRSS0_PHY_441_DATA
+ DDRSS0_PHY_442_DATA
+ DDRSS0_PHY_443_DATA
+ DDRSS0_PHY_444_DATA
+ DDRSS0_PHY_445_DATA
+ DDRSS0_PHY_446_DATA
+ DDRSS0_PHY_447_DATA
+ DDRSS0_PHY_448_DATA
+ DDRSS0_PHY_449_DATA
+ DDRSS0_PHY_450_DATA
+ DDRSS0_PHY_451_DATA
+ DDRSS0_PHY_452_DATA
+ DDRSS0_PHY_453_DATA
+ DDRSS0_PHY_454_DATA
+ DDRSS0_PHY_455_DATA
+ DDRSS0_PHY_456_DATA
+ DDRSS0_PHY_457_DATA
+ DDRSS0_PHY_458_DATA
+ DDRSS0_PHY_459_DATA
+ DDRSS0_PHY_460_DATA
+ DDRSS0_PHY_461_DATA
+ DDRSS0_PHY_462_DATA
+ DDRSS0_PHY_463_DATA
+ DDRSS0_PHY_464_DATA
+ DDRSS0_PHY_465_DATA
+ DDRSS0_PHY_466_DATA
+ DDRSS0_PHY_467_DATA
+ DDRSS0_PHY_468_DATA
+ DDRSS0_PHY_469_DATA
+ DDRSS0_PHY_470_DATA
+ DDRSS0_PHY_471_DATA
+ DDRSS0_PHY_472_DATA
+ DDRSS0_PHY_473_DATA
+ DDRSS0_PHY_474_DATA
+ DDRSS0_PHY_475_DATA
+ DDRSS0_PHY_476_DATA
+ DDRSS0_PHY_477_DATA
+ DDRSS0_PHY_478_DATA
+ DDRSS0_PHY_479_DATA
+ DDRSS0_PHY_480_DATA
+ DDRSS0_PHY_481_DATA
+ DDRSS0_PHY_482_DATA
+ DDRSS0_PHY_483_DATA
+ DDRSS0_PHY_484_DATA
+ DDRSS0_PHY_485_DATA
+ DDRSS0_PHY_486_DATA
+ DDRSS0_PHY_487_DATA
+ DDRSS0_PHY_488_DATA
+ DDRSS0_PHY_489_DATA
+ DDRSS0_PHY_490_DATA
+ DDRSS0_PHY_491_DATA
+ DDRSS0_PHY_492_DATA
+ DDRSS0_PHY_493_DATA
+ DDRSS0_PHY_494_DATA
+ DDRSS0_PHY_495_DATA
+ DDRSS0_PHY_496_DATA
+ DDRSS0_PHY_497_DATA
+ DDRSS0_PHY_498_DATA
+ DDRSS0_PHY_499_DATA
+ DDRSS0_PHY_500_DATA
+ DDRSS0_PHY_501_DATA
+ DDRSS0_PHY_502_DATA
+ DDRSS0_PHY_503_DATA
+ DDRSS0_PHY_504_DATA
+ DDRSS0_PHY_505_DATA
+ DDRSS0_PHY_506_DATA
+ DDRSS0_PHY_507_DATA
+ DDRSS0_PHY_508_DATA
+ DDRSS0_PHY_509_DATA
+ DDRSS0_PHY_510_DATA
+ DDRSS0_PHY_511_DATA
+ DDRSS0_PHY_512_DATA
+ DDRSS0_PHY_513_DATA
+ DDRSS0_PHY_514_DATA
+ DDRSS0_PHY_515_DATA
+ DDRSS0_PHY_516_DATA
+ DDRSS0_PHY_517_DATA
+ DDRSS0_PHY_518_DATA
+ DDRSS0_PHY_519_DATA
+ DDRSS0_PHY_520_DATA
+ DDRSS0_PHY_521_DATA
+ DDRSS0_PHY_522_DATA
+ DDRSS0_PHY_523_DATA
+ DDRSS0_PHY_524_DATA
+ DDRSS0_PHY_525_DATA
+ DDRSS0_PHY_526_DATA
+ DDRSS0_PHY_527_DATA
+ DDRSS0_PHY_528_DATA
+ DDRSS0_PHY_529_DATA
+ DDRSS0_PHY_530_DATA
+ DDRSS0_PHY_531_DATA
+ DDRSS0_PHY_532_DATA
+ DDRSS0_PHY_533_DATA
+ DDRSS0_PHY_534_DATA
+ DDRSS0_PHY_535_DATA
+ DDRSS0_PHY_536_DATA
+ DDRSS0_PHY_537_DATA
+ DDRSS0_PHY_538_DATA
+ DDRSS0_PHY_539_DATA
+ DDRSS0_PHY_540_DATA
+ DDRSS0_PHY_541_DATA
+ DDRSS0_PHY_542_DATA
+ DDRSS0_PHY_543_DATA
+ DDRSS0_PHY_544_DATA
+ DDRSS0_PHY_545_DATA
+ DDRSS0_PHY_546_DATA
+ DDRSS0_PHY_547_DATA
+ DDRSS0_PHY_548_DATA
+ DDRSS0_PHY_549_DATA
+ DDRSS0_PHY_550_DATA
+ DDRSS0_PHY_551_DATA
+ DDRSS0_PHY_552_DATA
+ DDRSS0_PHY_553_DATA
+ DDRSS0_PHY_554_DATA
+ DDRSS0_PHY_555_DATA
+ DDRSS0_PHY_556_DATA
+ DDRSS0_PHY_557_DATA
+ DDRSS0_PHY_558_DATA
+ DDRSS0_PHY_559_DATA
+ DDRSS0_PHY_560_DATA
+ DDRSS0_PHY_561_DATA
+ DDRSS0_PHY_562_DATA
+ DDRSS0_PHY_563_DATA
+ DDRSS0_PHY_564_DATA
+ DDRSS0_PHY_565_DATA
+ DDRSS0_PHY_566_DATA
+ DDRSS0_PHY_567_DATA
+ DDRSS0_PHY_568_DATA
+ DDRSS0_PHY_569_DATA
+ DDRSS0_PHY_570_DATA
+ DDRSS0_PHY_571_DATA
+ DDRSS0_PHY_572_DATA
+ DDRSS0_PHY_573_DATA
+ DDRSS0_PHY_574_DATA
+ DDRSS0_PHY_575_DATA
+ DDRSS0_PHY_576_DATA
+ DDRSS0_PHY_577_DATA
+ DDRSS0_PHY_578_DATA
+ DDRSS0_PHY_579_DATA
+ DDRSS0_PHY_580_DATA
+ DDRSS0_PHY_581_DATA
+ DDRSS0_PHY_582_DATA
+ DDRSS0_PHY_583_DATA
+ DDRSS0_PHY_584_DATA
+ DDRSS0_PHY_585_DATA
+ DDRSS0_PHY_586_DATA
+ DDRSS0_PHY_587_DATA
+ DDRSS0_PHY_588_DATA
+ DDRSS0_PHY_589_DATA
+ DDRSS0_PHY_590_DATA
+ DDRSS0_PHY_591_DATA
+ DDRSS0_PHY_592_DATA
+ DDRSS0_PHY_593_DATA
+ DDRSS0_PHY_594_DATA
+ DDRSS0_PHY_595_DATA
+ DDRSS0_PHY_596_DATA
+ DDRSS0_PHY_597_DATA
+ DDRSS0_PHY_598_DATA
+ DDRSS0_PHY_599_DATA
+ DDRSS0_PHY_600_DATA
+ DDRSS0_PHY_601_DATA
+ DDRSS0_PHY_602_DATA
+ DDRSS0_PHY_603_DATA
+ DDRSS0_PHY_604_DATA
+ DDRSS0_PHY_605_DATA
+ DDRSS0_PHY_606_DATA
+ DDRSS0_PHY_607_DATA
+ DDRSS0_PHY_608_DATA
+ DDRSS0_PHY_609_DATA
+ DDRSS0_PHY_610_DATA
+ DDRSS0_PHY_611_DATA
+ DDRSS0_PHY_612_DATA
+ DDRSS0_PHY_613_DATA
+ DDRSS0_PHY_614_DATA
+ DDRSS0_PHY_615_DATA
+ DDRSS0_PHY_616_DATA
+ DDRSS0_PHY_617_DATA
+ DDRSS0_PHY_618_DATA
+ DDRSS0_PHY_619_DATA
+ DDRSS0_PHY_620_DATA
+ DDRSS0_PHY_621_DATA
+ DDRSS0_PHY_622_DATA
+ DDRSS0_PHY_623_DATA
+ DDRSS0_PHY_624_DATA
+ DDRSS0_PHY_625_DATA
+ DDRSS0_PHY_626_DATA
+ DDRSS0_PHY_627_DATA
+ DDRSS0_PHY_628_DATA
+ DDRSS0_PHY_629_DATA
+ DDRSS0_PHY_630_DATA
+ DDRSS0_PHY_631_DATA
+ DDRSS0_PHY_632_DATA
+ DDRSS0_PHY_633_DATA
+ DDRSS0_PHY_634_DATA
+ DDRSS0_PHY_635_DATA
+ DDRSS0_PHY_636_DATA
+ DDRSS0_PHY_637_DATA
+ DDRSS0_PHY_638_DATA
+ DDRSS0_PHY_639_DATA
+ DDRSS0_PHY_640_DATA
+ DDRSS0_PHY_641_DATA
+ DDRSS0_PHY_642_DATA
+ DDRSS0_PHY_643_DATA
+ DDRSS0_PHY_644_DATA
+ DDRSS0_PHY_645_DATA
+ DDRSS0_PHY_646_DATA
+ DDRSS0_PHY_647_DATA
+ DDRSS0_PHY_648_DATA
+ DDRSS0_PHY_649_DATA
+ DDRSS0_PHY_650_DATA
+ DDRSS0_PHY_651_DATA
+ DDRSS0_PHY_652_DATA
+ DDRSS0_PHY_653_DATA
+ DDRSS0_PHY_654_DATA
+ DDRSS0_PHY_655_DATA
+ DDRSS0_PHY_656_DATA
+ DDRSS0_PHY_657_DATA
+ DDRSS0_PHY_658_DATA
+ DDRSS0_PHY_659_DATA
+ DDRSS0_PHY_660_DATA
+ DDRSS0_PHY_661_DATA
+ DDRSS0_PHY_662_DATA
+ DDRSS0_PHY_663_DATA
+ DDRSS0_PHY_664_DATA
+ DDRSS0_PHY_665_DATA
+ DDRSS0_PHY_666_DATA
+ DDRSS0_PHY_667_DATA
+ DDRSS0_PHY_668_DATA
+ DDRSS0_PHY_669_DATA
+ DDRSS0_PHY_670_DATA
+ DDRSS0_PHY_671_DATA
+ DDRSS0_PHY_672_DATA
+ DDRSS0_PHY_673_DATA
+ DDRSS0_PHY_674_DATA
+ DDRSS0_PHY_675_DATA
+ DDRSS0_PHY_676_DATA
+ DDRSS0_PHY_677_DATA
+ DDRSS0_PHY_678_DATA
+ DDRSS0_PHY_679_DATA
+ DDRSS0_PHY_680_DATA
+ DDRSS0_PHY_681_DATA
+ DDRSS0_PHY_682_DATA
+ DDRSS0_PHY_683_DATA
+ DDRSS0_PHY_684_DATA
+ DDRSS0_PHY_685_DATA
+ DDRSS0_PHY_686_DATA
+ DDRSS0_PHY_687_DATA
+ DDRSS0_PHY_688_DATA
+ DDRSS0_PHY_689_DATA
+ DDRSS0_PHY_690_DATA
+ DDRSS0_PHY_691_DATA
+ DDRSS0_PHY_692_DATA
+ DDRSS0_PHY_693_DATA
+ DDRSS0_PHY_694_DATA
+ DDRSS0_PHY_695_DATA
+ DDRSS0_PHY_696_DATA
+ DDRSS0_PHY_697_DATA
+ DDRSS0_PHY_698_DATA
+ DDRSS0_PHY_699_DATA
+ DDRSS0_PHY_700_DATA
+ DDRSS0_PHY_701_DATA
+ DDRSS0_PHY_702_DATA
+ DDRSS0_PHY_703_DATA
+ DDRSS0_PHY_704_DATA
+ DDRSS0_PHY_705_DATA
+ DDRSS0_PHY_706_DATA
+ DDRSS0_PHY_707_DATA
+ DDRSS0_PHY_708_DATA
+ DDRSS0_PHY_709_DATA
+ DDRSS0_PHY_710_DATA
+ DDRSS0_PHY_711_DATA
+ DDRSS0_PHY_712_DATA
+ DDRSS0_PHY_713_DATA
+ DDRSS0_PHY_714_DATA
+ DDRSS0_PHY_715_DATA
+ DDRSS0_PHY_716_DATA
+ DDRSS0_PHY_717_DATA
+ DDRSS0_PHY_718_DATA
+ DDRSS0_PHY_719_DATA
+ DDRSS0_PHY_720_DATA
+ DDRSS0_PHY_721_DATA
+ DDRSS0_PHY_722_DATA
+ DDRSS0_PHY_723_DATA
+ DDRSS0_PHY_724_DATA
+ DDRSS0_PHY_725_DATA
+ DDRSS0_PHY_726_DATA
+ DDRSS0_PHY_727_DATA
+ DDRSS0_PHY_728_DATA
+ DDRSS0_PHY_729_DATA
+ DDRSS0_PHY_730_DATA
+ DDRSS0_PHY_731_DATA
+ DDRSS0_PHY_732_DATA
+ DDRSS0_PHY_733_DATA
+ DDRSS0_PHY_734_DATA
+ DDRSS0_PHY_735_DATA
+ DDRSS0_PHY_736_DATA
+ DDRSS0_PHY_737_DATA
+ DDRSS0_PHY_738_DATA
+ DDRSS0_PHY_739_DATA
+ DDRSS0_PHY_740_DATA
+ DDRSS0_PHY_741_DATA
+ DDRSS0_PHY_742_DATA
+ DDRSS0_PHY_743_DATA
+ DDRSS0_PHY_744_DATA
+ DDRSS0_PHY_745_DATA
+ DDRSS0_PHY_746_DATA
+ DDRSS0_PHY_747_DATA
+ DDRSS0_PHY_748_DATA
+ DDRSS0_PHY_749_DATA
+ DDRSS0_PHY_750_DATA
+ DDRSS0_PHY_751_DATA
+ DDRSS0_PHY_752_DATA
+ DDRSS0_PHY_753_DATA
+ DDRSS0_PHY_754_DATA
+ DDRSS0_PHY_755_DATA
+ DDRSS0_PHY_756_DATA
+ DDRSS0_PHY_757_DATA
+ DDRSS0_PHY_758_DATA
+ DDRSS0_PHY_759_DATA
+ DDRSS0_PHY_760_DATA
+ DDRSS0_PHY_761_DATA
+ DDRSS0_PHY_762_DATA
+ DDRSS0_PHY_763_DATA
+ DDRSS0_PHY_764_DATA
+ DDRSS0_PHY_765_DATA
+ DDRSS0_PHY_766_DATA
+ DDRSS0_PHY_767_DATA
+ DDRSS0_PHY_768_DATA
+ DDRSS0_PHY_769_DATA
+ DDRSS0_PHY_770_DATA
+ DDRSS0_PHY_771_DATA
+ DDRSS0_PHY_772_DATA
+ DDRSS0_PHY_773_DATA
+ DDRSS0_PHY_774_DATA
+ DDRSS0_PHY_775_DATA
+ DDRSS0_PHY_776_DATA
+ DDRSS0_PHY_777_DATA
+ DDRSS0_PHY_778_DATA
+ DDRSS0_PHY_779_DATA
+ DDRSS0_PHY_780_DATA
+ DDRSS0_PHY_781_DATA
+ DDRSS0_PHY_782_DATA
+ DDRSS0_PHY_783_DATA
+ DDRSS0_PHY_784_DATA
+ DDRSS0_PHY_785_DATA
+ DDRSS0_PHY_786_DATA
+ DDRSS0_PHY_787_DATA
+ DDRSS0_PHY_788_DATA
+ DDRSS0_PHY_789_DATA
+ DDRSS0_PHY_790_DATA
+ DDRSS0_PHY_791_DATA
+ DDRSS0_PHY_792_DATA
+ DDRSS0_PHY_793_DATA
+ DDRSS0_PHY_794_DATA
+ DDRSS0_PHY_795_DATA
+ DDRSS0_PHY_796_DATA
+ DDRSS0_PHY_797_DATA
+ DDRSS0_PHY_798_DATA
+ DDRSS0_PHY_799_DATA
+ DDRSS0_PHY_800_DATA
+ DDRSS0_PHY_801_DATA
+ DDRSS0_PHY_802_DATA
+ DDRSS0_PHY_803_DATA
+ DDRSS0_PHY_804_DATA
+ DDRSS0_PHY_805_DATA
+ DDRSS0_PHY_806_DATA
+ DDRSS0_PHY_807_DATA
+ DDRSS0_PHY_808_DATA
+ DDRSS0_PHY_809_DATA
+ DDRSS0_PHY_810_DATA
+ DDRSS0_PHY_811_DATA
+ DDRSS0_PHY_812_DATA
+ DDRSS0_PHY_813_DATA
+ DDRSS0_PHY_814_DATA
+ DDRSS0_PHY_815_DATA
+ DDRSS0_PHY_816_DATA
+ DDRSS0_PHY_817_DATA
+ DDRSS0_PHY_818_DATA
+ DDRSS0_PHY_819_DATA
+ DDRSS0_PHY_820_DATA
+ DDRSS0_PHY_821_DATA
+ DDRSS0_PHY_822_DATA
+ DDRSS0_PHY_823_DATA
+ DDRSS0_PHY_824_DATA
+ DDRSS0_PHY_825_DATA
+ DDRSS0_PHY_826_DATA
+ DDRSS0_PHY_827_DATA
+ DDRSS0_PHY_828_DATA
+ DDRSS0_PHY_829_DATA
+ DDRSS0_PHY_830_DATA
+ DDRSS0_PHY_831_DATA
+ DDRSS0_PHY_832_DATA
+ DDRSS0_PHY_833_DATA
+ DDRSS0_PHY_834_DATA
+ DDRSS0_PHY_835_DATA
+ DDRSS0_PHY_836_DATA
+ DDRSS0_PHY_837_DATA
+ DDRSS0_PHY_838_DATA
+ DDRSS0_PHY_839_DATA
+ DDRSS0_PHY_840_DATA
+ DDRSS0_PHY_841_DATA
+ DDRSS0_PHY_842_DATA
+ DDRSS0_PHY_843_DATA
+ DDRSS0_PHY_844_DATA
+ DDRSS0_PHY_845_DATA
+ DDRSS0_PHY_846_DATA
+ DDRSS0_PHY_847_DATA
+ DDRSS0_PHY_848_DATA
+ DDRSS0_PHY_849_DATA
+ DDRSS0_PHY_850_DATA
+ DDRSS0_PHY_851_DATA
+ DDRSS0_PHY_852_DATA
+ DDRSS0_PHY_853_DATA
+ DDRSS0_PHY_854_DATA
+ DDRSS0_PHY_855_DATA
+ DDRSS0_PHY_856_DATA
+ DDRSS0_PHY_857_DATA
+ DDRSS0_PHY_858_DATA
+ DDRSS0_PHY_859_DATA
+ DDRSS0_PHY_860_DATA
+ DDRSS0_PHY_861_DATA
+ DDRSS0_PHY_862_DATA
+ DDRSS0_PHY_863_DATA
+ DDRSS0_PHY_864_DATA
+ DDRSS0_PHY_865_DATA
+ DDRSS0_PHY_866_DATA
+ DDRSS0_PHY_867_DATA
+ DDRSS0_PHY_868_DATA
+ DDRSS0_PHY_869_DATA
+ DDRSS0_PHY_870_DATA
+ DDRSS0_PHY_871_DATA
+ DDRSS0_PHY_872_DATA
+ DDRSS0_PHY_873_DATA
+ DDRSS0_PHY_874_DATA
+ DDRSS0_PHY_875_DATA
+ DDRSS0_PHY_876_DATA
+ DDRSS0_PHY_877_DATA
+ DDRSS0_PHY_878_DATA
+ DDRSS0_PHY_879_DATA
+ DDRSS0_PHY_880_DATA
+ DDRSS0_PHY_881_DATA
+ DDRSS0_PHY_882_DATA
+ DDRSS0_PHY_883_DATA
+ DDRSS0_PHY_884_DATA
+ DDRSS0_PHY_885_DATA
+ DDRSS0_PHY_886_DATA
+ DDRSS0_PHY_887_DATA
+ DDRSS0_PHY_888_DATA
+ DDRSS0_PHY_889_DATA
+ DDRSS0_PHY_890_DATA
+ DDRSS0_PHY_891_DATA
+ DDRSS0_PHY_892_DATA
+ DDRSS0_PHY_893_DATA
+ DDRSS0_PHY_894_DATA
+ DDRSS0_PHY_895_DATA
+ DDRSS0_PHY_896_DATA
+ DDRSS0_PHY_897_DATA
+ DDRSS0_PHY_898_DATA
+ DDRSS0_PHY_899_DATA
+ DDRSS0_PHY_900_DATA
+ DDRSS0_PHY_901_DATA
+ DDRSS0_PHY_902_DATA
+ DDRSS0_PHY_903_DATA
+ DDRSS0_PHY_904_DATA
+ DDRSS0_PHY_905_DATA
+ DDRSS0_PHY_906_DATA
+ DDRSS0_PHY_907_DATA
+ DDRSS0_PHY_908_DATA
+ DDRSS0_PHY_909_DATA
+ DDRSS0_PHY_910_DATA
+ DDRSS0_PHY_911_DATA
+ DDRSS0_PHY_912_DATA
+ DDRSS0_PHY_913_DATA
+ DDRSS0_PHY_914_DATA
+ DDRSS0_PHY_915_DATA
+ DDRSS0_PHY_916_DATA
+ DDRSS0_PHY_917_DATA
+ DDRSS0_PHY_918_DATA
+ DDRSS0_PHY_919_DATA
+ DDRSS0_PHY_920_DATA
+ DDRSS0_PHY_921_DATA
+ DDRSS0_PHY_922_DATA
+ DDRSS0_PHY_923_DATA
+ DDRSS0_PHY_924_DATA
+ DDRSS0_PHY_925_DATA
+ DDRSS0_PHY_926_DATA
+ DDRSS0_PHY_927_DATA
+ DDRSS0_PHY_928_DATA
+ DDRSS0_PHY_929_DATA
+ DDRSS0_PHY_930_DATA
+ DDRSS0_PHY_931_DATA
+ DDRSS0_PHY_932_DATA
+ DDRSS0_PHY_933_DATA
+ DDRSS0_PHY_934_DATA
+ DDRSS0_PHY_935_DATA
+ DDRSS0_PHY_936_DATA
+ DDRSS0_PHY_937_DATA
+ DDRSS0_PHY_938_DATA
+ DDRSS0_PHY_939_DATA
+ DDRSS0_PHY_940_DATA
+ DDRSS0_PHY_941_DATA
+ DDRSS0_PHY_942_DATA
+ DDRSS0_PHY_943_DATA
+ DDRSS0_PHY_944_DATA
+ DDRSS0_PHY_945_DATA
+ DDRSS0_PHY_946_DATA
+ DDRSS0_PHY_947_DATA
+ DDRSS0_PHY_948_DATA
+ DDRSS0_PHY_949_DATA
+ DDRSS0_PHY_950_DATA
+ DDRSS0_PHY_951_DATA
+ DDRSS0_PHY_952_DATA
+ DDRSS0_PHY_953_DATA
+ DDRSS0_PHY_954_DATA
+ DDRSS0_PHY_955_DATA
+ DDRSS0_PHY_956_DATA
+ DDRSS0_PHY_957_DATA
+ DDRSS0_PHY_958_DATA
+ DDRSS0_PHY_959_DATA
+ DDRSS0_PHY_960_DATA
+ DDRSS0_PHY_961_DATA
+ DDRSS0_PHY_962_DATA
+ DDRSS0_PHY_963_DATA
+ DDRSS0_PHY_964_DATA
+ DDRSS0_PHY_965_DATA
+ DDRSS0_PHY_966_DATA
+ DDRSS0_PHY_967_DATA
+ DDRSS0_PHY_968_DATA
+ DDRSS0_PHY_969_DATA
+ DDRSS0_PHY_970_DATA
+ DDRSS0_PHY_971_DATA
+ DDRSS0_PHY_972_DATA
+ DDRSS0_PHY_973_DATA
+ DDRSS0_PHY_974_DATA
+ DDRSS0_PHY_975_DATA
+ DDRSS0_PHY_976_DATA
+ DDRSS0_PHY_977_DATA
+ DDRSS0_PHY_978_DATA
+ DDRSS0_PHY_979_DATA
+ DDRSS0_PHY_980_DATA
+ DDRSS0_PHY_981_DATA
+ DDRSS0_PHY_982_DATA
+ DDRSS0_PHY_983_DATA
+ DDRSS0_PHY_984_DATA
+ DDRSS0_PHY_985_DATA
+ DDRSS0_PHY_986_DATA
+ DDRSS0_PHY_987_DATA
+ DDRSS0_PHY_988_DATA
+ DDRSS0_PHY_989_DATA
+ DDRSS0_PHY_990_DATA
+ DDRSS0_PHY_991_DATA
+ DDRSS0_PHY_992_DATA
+ DDRSS0_PHY_993_DATA
+ DDRSS0_PHY_994_DATA
+ DDRSS0_PHY_995_DATA
+ DDRSS0_PHY_996_DATA
+ DDRSS0_PHY_997_DATA
+ DDRSS0_PHY_998_DATA
+ DDRSS0_PHY_999_DATA
+ DDRSS0_PHY_1000_DATA
+ DDRSS0_PHY_1001_DATA
+ DDRSS0_PHY_1002_DATA
+ DDRSS0_PHY_1003_DATA
+ DDRSS0_PHY_1004_DATA
+ DDRSS0_PHY_1005_DATA
+ DDRSS0_PHY_1006_DATA
+ DDRSS0_PHY_1007_DATA
+ DDRSS0_PHY_1008_DATA
+ DDRSS0_PHY_1009_DATA
+ DDRSS0_PHY_1010_DATA
+ DDRSS0_PHY_1011_DATA
+ DDRSS0_PHY_1012_DATA
+ DDRSS0_PHY_1013_DATA
+ DDRSS0_PHY_1014_DATA
+ DDRSS0_PHY_1015_DATA
+ DDRSS0_PHY_1016_DATA
+ DDRSS0_PHY_1017_DATA
+ DDRSS0_PHY_1018_DATA
+ DDRSS0_PHY_1019_DATA
+ DDRSS0_PHY_1020_DATA
+ DDRSS0_PHY_1021_DATA
+ DDRSS0_PHY_1022_DATA
+ DDRSS0_PHY_1023_DATA
+ DDRSS0_PHY_1024_DATA
+ DDRSS0_PHY_1025_DATA
+ DDRSS0_PHY_1026_DATA
+ DDRSS0_PHY_1027_DATA
+ DDRSS0_PHY_1028_DATA
+ DDRSS0_PHY_1029_DATA
+ DDRSS0_PHY_1030_DATA
+ DDRSS0_PHY_1031_DATA
+ DDRSS0_PHY_1032_DATA
+ DDRSS0_PHY_1033_DATA
+ DDRSS0_PHY_1034_DATA
+ DDRSS0_PHY_1035_DATA
+ DDRSS0_PHY_1036_DATA
+ DDRSS0_PHY_1037_DATA
+ DDRSS0_PHY_1038_DATA
+ DDRSS0_PHY_1039_DATA
+ DDRSS0_PHY_1040_DATA
+ DDRSS0_PHY_1041_DATA
+ DDRSS0_PHY_1042_DATA
+ DDRSS0_PHY_1043_DATA
+ DDRSS0_PHY_1044_DATA
+ DDRSS0_PHY_1045_DATA
+ DDRSS0_PHY_1046_DATA
+ DDRSS0_PHY_1047_DATA
+ DDRSS0_PHY_1048_DATA
+ DDRSS0_PHY_1049_DATA
+ DDRSS0_PHY_1050_DATA
+ DDRSS0_PHY_1051_DATA
+ DDRSS0_PHY_1052_DATA
+ DDRSS0_PHY_1053_DATA
+ DDRSS0_PHY_1054_DATA
+ DDRSS0_PHY_1055_DATA
+ DDRSS0_PHY_1056_DATA
+ DDRSS0_PHY_1057_DATA
+ DDRSS0_PHY_1058_DATA
+ DDRSS0_PHY_1059_DATA
+ DDRSS0_PHY_1060_DATA
+ DDRSS0_PHY_1061_DATA
+ DDRSS0_PHY_1062_DATA
+ DDRSS0_PHY_1063_DATA
+ DDRSS0_PHY_1064_DATA
+ DDRSS0_PHY_1065_DATA
+ DDRSS0_PHY_1066_DATA
+ DDRSS0_PHY_1067_DATA
+ DDRSS0_PHY_1068_DATA
+ DDRSS0_PHY_1069_DATA
+ DDRSS0_PHY_1070_DATA
+ DDRSS0_PHY_1071_DATA
+ DDRSS0_PHY_1072_DATA
+ DDRSS0_PHY_1073_DATA
+ DDRSS0_PHY_1074_DATA
+ DDRSS0_PHY_1075_DATA
+ DDRSS0_PHY_1076_DATA
+ DDRSS0_PHY_1077_DATA
+ DDRSS0_PHY_1078_DATA
+ DDRSS0_PHY_1079_DATA
+ DDRSS0_PHY_1080_DATA
+ DDRSS0_PHY_1081_DATA
+ DDRSS0_PHY_1082_DATA
+ DDRSS0_PHY_1083_DATA
+ DDRSS0_PHY_1084_DATA
+ DDRSS0_PHY_1085_DATA
+ DDRSS0_PHY_1086_DATA
+ DDRSS0_PHY_1087_DATA
+ DDRSS0_PHY_1088_DATA
+ DDRSS0_PHY_1089_DATA
+ DDRSS0_PHY_1090_DATA
+ DDRSS0_PHY_1091_DATA
+ DDRSS0_PHY_1092_DATA
+ DDRSS0_PHY_1093_DATA
+ DDRSS0_PHY_1094_DATA
+ DDRSS0_PHY_1095_DATA
+ DDRSS0_PHY_1096_DATA
+ DDRSS0_PHY_1097_DATA
+ DDRSS0_PHY_1098_DATA
+ DDRSS0_PHY_1099_DATA
+ DDRSS0_PHY_1100_DATA
+ DDRSS0_PHY_1101_DATA
+ DDRSS0_PHY_1102_DATA
+ DDRSS0_PHY_1103_DATA
+ DDRSS0_PHY_1104_DATA
+ DDRSS0_PHY_1105_DATA
+ DDRSS0_PHY_1106_DATA
+ DDRSS0_PHY_1107_DATA
+ DDRSS0_PHY_1108_DATA
+ DDRSS0_PHY_1109_DATA
+ DDRSS0_PHY_1110_DATA
+ DDRSS0_PHY_1111_DATA
+ DDRSS0_PHY_1112_DATA
+ DDRSS0_PHY_1113_DATA
+ DDRSS0_PHY_1114_DATA
+ DDRSS0_PHY_1115_DATA
+ DDRSS0_PHY_1116_DATA
+ DDRSS0_PHY_1117_DATA
+ DDRSS0_PHY_1118_DATA
+ DDRSS0_PHY_1119_DATA
+ DDRSS0_PHY_1120_DATA
+ DDRSS0_PHY_1121_DATA
+ DDRSS0_PHY_1122_DATA
+ DDRSS0_PHY_1123_DATA
+ DDRSS0_PHY_1124_DATA
+ DDRSS0_PHY_1125_DATA
+ DDRSS0_PHY_1126_DATA
+ DDRSS0_PHY_1127_DATA
+ DDRSS0_PHY_1128_DATA
+ DDRSS0_PHY_1129_DATA
+ DDRSS0_PHY_1130_DATA
+ DDRSS0_PHY_1131_DATA
+ DDRSS0_PHY_1132_DATA
+ DDRSS0_PHY_1133_DATA
+ DDRSS0_PHY_1134_DATA
+ DDRSS0_PHY_1135_DATA
+ DDRSS0_PHY_1136_DATA
+ DDRSS0_PHY_1137_DATA
+ DDRSS0_PHY_1138_DATA
+ DDRSS0_PHY_1139_DATA
+ DDRSS0_PHY_1140_DATA
+ DDRSS0_PHY_1141_DATA
+ DDRSS0_PHY_1142_DATA
+ DDRSS0_PHY_1143_DATA
+ DDRSS0_PHY_1144_DATA
+ DDRSS0_PHY_1145_DATA
+ DDRSS0_PHY_1146_DATA
+ DDRSS0_PHY_1147_DATA
+ DDRSS0_PHY_1148_DATA
+ DDRSS0_PHY_1149_DATA
+ DDRSS0_PHY_1150_DATA
+ DDRSS0_PHY_1151_DATA
+ DDRSS0_PHY_1152_DATA
+ DDRSS0_PHY_1153_DATA
+ DDRSS0_PHY_1154_DATA
+ DDRSS0_PHY_1155_DATA
+ DDRSS0_PHY_1156_DATA
+ DDRSS0_PHY_1157_DATA
+ DDRSS0_PHY_1158_DATA
+ DDRSS0_PHY_1159_DATA
+ DDRSS0_PHY_1160_DATA
+ DDRSS0_PHY_1161_DATA
+ DDRSS0_PHY_1162_DATA
+ DDRSS0_PHY_1163_DATA
+ DDRSS0_PHY_1164_DATA
+ DDRSS0_PHY_1165_DATA
+ DDRSS0_PHY_1166_DATA
+ DDRSS0_PHY_1167_DATA
+ DDRSS0_PHY_1168_DATA
+ DDRSS0_PHY_1169_DATA
+ DDRSS0_PHY_1170_DATA
+ DDRSS0_PHY_1171_DATA
+ DDRSS0_PHY_1172_DATA
+ DDRSS0_PHY_1173_DATA
+ DDRSS0_PHY_1174_DATA
+ DDRSS0_PHY_1175_DATA
+ DDRSS0_PHY_1176_DATA
+ DDRSS0_PHY_1177_DATA
+ DDRSS0_PHY_1178_DATA
+ DDRSS0_PHY_1179_DATA
+ DDRSS0_PHY_1180_DATA
+ DDRSS0_PHY_1181_DATA
+ DDRSS0_PHY_1182_DATA
+ DDRSS0_PHY_1183_DATA
+ DDRSS0_PHY_1184_DATA
+ DDRSS0_PHY_1185_DATA
+ DDRSS0_PHY_1186_DATA
+ DDRSS0_PHY_1187_DATA
+ DDRSS0_PHY_1188_DATA
+ DDRSS0_PHY_1189_DATA
+ DDRSS0_PHY_1190_DATA
+ DDRSS0_PHY_1191_DATA
+ DDRSS0_PHY_1192_DATA
+ DDRSS0_PHY_1193_DATA
+ DDRSS0_PHY_1194_DATA
+ DDRSS0_PHY_1195_DATA
+ DDRSS0_PHY_1196_DATA
+ DDRSS0_PHY_1197_DATA
+ DDRSS0_PHY_1198_DATA
+ DDRSS0_PHY_1199_DATA
+ DDRSS0_PHY_1200_DATA
+ DDRSS0_PHY_1201_DATA
+ DDRSS0_PHY_1202_DATA
+ DDRSS0_PHY_1203_DATA
+ DDRSS0_PHY_1204_DATA
+ DDRSS0_PHY_1205_DATA
+ DDRSS0_PHY_1206_DATA
+ DDRSS0_PHY_1207_DATA
+ DDRSS0_PHY_1208_DATA
+ DDRSS0_PHY_1209_DATA
+ DDRSS0_PHY_1210_DATA
+ DDRSS0_PHY_1211_DATA
+ DDRSS0_PHY_1212_DATA
+ DDRSS0_PHY_1213_DATA
+ DDRSS0_PHY_1214_DATA
+ DDRSS0_PHY_1215_DATA
+ DDRSS0_PHY_1216_DATA
+ DDRSS0_PHY_1217_DATA
+ DDRSS0_PHY_1218_DATA
+ DDRSS0_PHY_1219_DATA
+ DDRSS0_PHY_1220_DATA
+ DDRSS0_PHY_1221_DATA
+ DDRSS0_PHY_1222_DATA
+ DDRSS0_PHY_1223_DATA
+ DDRSS0_PHY_1224_DATA
+ DDRSS0_PHY_1225_DATA
+ DDRSS0_PHY_1226_DATA
+ DDRSS0_PHY_1227_DATA
+ DDRSS0_PHY_1228_DATA
+ DDRSS0_PHY_1229_DATA
+ DDRSS0_PHY_1230_DATA
+ DDRSS0_PHY_1231_DATA
+ DDRSS0_PHY_1232_DATA
+ DDRSS0_PHY_1233_DATA
+ DDRSS0_PHY_1234_DATA
+ DDRSS0_PHY_1235_DATA
+ DDRSS0_PHY_1236_DATA
+ DDRSS0_PHY_1237_DATA
+ DDRSS0_PHY_1238_DATA
+ DDRSS0_PHY_1239_DATA
+ DDRSS0_PHY_1240_DATA
+ DDRSS0_PHY_1241_DATA
+ DDRSS0_PHY_1242_DATA
+ DDRSS0_PHY_1243_DATA
+ DDRSS0_PHY_1244_DATA
+ DDRSS0_PHY_1245_DATA
+ DDRSS0_PHY_1246_DATA
+ DDRSS0_PHY_1247_DATA
+ DDRSS0_PHY_1248_DATA
+ DDRSS0_PHY_1249_DATA
+ DDRSS0_PHY_1250_DATA
+ DDRSS0_PHY_1251_DATA
+ DDRSS0_PHY_1252_DATA
+ DDRSS0_PHY_1253_DATA
+ DDRSS0_PHY_1254_DATA
+ DDRSS0_PHY_1255_DATA
+ DDRSS0_PHY_1256_DATA
+ DDRSS0_PHY_1257_DATA
+ DDRSS0_PHY_1258_DATA
+ DDRSS0_PHY_1259_DATA
+ DDRSS0_PHY_1260_DATA
+ DDRSS0_PHY_1261_DATA
+ DDRSS0_PHY_1262_DATA
+ DDRSS0_PHY_1263_DATA
+ DDRSS0_PHY_1264_DATA
+ DDRSS0_PHY_1265_DATA
+ DDRSS0_PHY_1266_DATA
+ DDRSS0_PHY_1267_DATA
+ DDRSS0_PHY_1268_DATA
+ DDRSS0_PHY_1269_DATA
+ DDRSS0_PHY_1270_DATA
+ DDRSS0_PHY_1271_DATA
+ DDRSS0_PHY_1272_DATA
+ DDRSS0_PHY_1273_DATA
+ DDRSS0_PHY_1274_DATA
+ DDRSS0_PHY_1275_DATA
+ DDRSS0_PHY_1276_DATA
+ DDRSS0_PHY_1277_DATA
+ DDRSS0_PHY_1278_DATA
+ DDRSS0_PHY_1279_DATA
+ DDRSS0_PHY_1280_DATA
+ DDRSS0_PHY_1281_DATA
+ DDRSS0_PHY_1282_DATA
+ DDRSS0_PHY_1283_DATA
+ DDRSS0_PHY_1284_DATA
+ DDRSS0_PHY_1285_DATA
+ DDRSS0_PHY_1286_DATA
+ DDRSS0_PHY_1287_DATA
+ DDRSS0_PHY_1288_DATA
+ DDRSS0_PHY_1289_DATA
+ DDRSS0_PHY_1290_DATA
+ DDRSS0_PHY_1291_DATA
+ DDRSS0_PHY_1292_DATA
+ DDRSS0_PHY_1293_DATA
+ DDRSS0_PHY_1294_DATA
+ DDRSS0_PHY_1295_DATA
+ DDRSS0_PHY_1296_DATA
+ DDRSS0_PHY_1297_DATA
+ DDRSS0_PHY_1298_DATA
+ DDRSS0_PHY_1299_DATA
+ DDRSS0_PHY_1300_DATA
+ DDRSS0_PHY_1301_DATA
+ DDRSS0_PHY_1302_DATA
+ DDRSS0_PHY_1303_DATA
+ DDRSS0_PHY_1304_DATA
+ DDRSS0_PHY_1305_DATA
+ DDRSS0_PHY_1306_DATA
+ DDRSS0_PHY_1307_DATA
+ DDRSS0_PHY_1308_DATA
+ DDRSS0_PHY_1309_DATA
+ DDRSS0_PHY_1310_DATA
+ DDRSS0_PHY_1311_DATA
+ DDRSS0_PHY_1312_DATA
+ DDRSS0_PHY_1313_DATA
+ DDRSS0_PHY_1314_DATA
+ DDRSS0_PHY_1315_DATA
+ DDRSS0_PHY_1316_DATA
+ DDRSS0_PHY_1317_DATA
+ DDRSS0_PHY_1318_DATA
+ DDRSS0_PHY_1319_DATA
+ DDRSS0_PHY_1320_DATA
+ DDRSS0_PHY_1321_DATA
+ DDRSS0_PHY_1322_DATA
+ DDRSS0_PHY_1323_DATA
+ DDRSS0_PHY_1324_DATA
+ DDRSS0_PHY_1325_DATA
+ DDRSS0_PHY_1326_DATA
+ DDRSS0_PHY_1327_DATA
+ DDRSS0_PHY_1328_DATA
+ DDRSS0_PHY_1329_DATA
+ DDRSS0_PHY_1330_DATA
+ DDRSS0_PHY_1331_DATA
+ DDRSS0_PHY_1332_DATA
+ DDRSS0_PHY_1333_DATA
+ DDRSS0_PHY_1334_DATA
+ DDRSS0_PHY_1335_DATA
+ DDRSS0_PHY_1336_DATA
+ DDRSS0_PHY_1337_DATA
+ DDRSS0_PHY_1338_DATA
+ DDRSS0_PHY_1339_DATA
+ DDRSS0_PHY_1340_DATA
+ DDRSS0_PHY_1341_DATA
+ DDRSS0_PHY_1342_DATA
+ DDRSS0_PHY_1343_DATA
+ DDRSS0_PHY_1344_DATA
+ DDRSS0_PHY_1345_DATA
+ DDRSS0_PHY_1346_DATA
+ DDRSS0_PHY_1347_DATA
+ DDRSS0_PHY_1348_DATA
+ DDRSS0_PHY_1349_DATA
+ DDRSS0_PHY_1350_DATA
+ DDRSS0_PHY_1351_DATA
+ DDRSS0_PHY_1352_DATA
+ DDRSS0_PHY_1353_DATA
+ DDRSS0_PHY_1354_DATA
+ DDRSS0_PHY_1355_DATA
+ DDRSS0_PHY_1356_DATA
+ DDRSS0_PHY_1357_DATA
+ DDRSS0_PHY_1358_DATA
+ DDRSS0_PHY_1359_DATA
+ DDRSS0_PHY_1360_DATA
+ DDRSS0_PHY_1361_DATA
+ DDRSS0_PHY_1362_DATA
+ DDRSS0_PHY_1363_DATA
+ DDRSS0_PHY_1364_DATA
+ DDRSS0_PHY_1365_DATA
+ DDRSS0_PHY_1366_DATA
+ DDRSS0_PHY_1367_DATA
+ DDRSS0_PHY_1368_DATA
+ DDRSS0_PHY_1369_DATA
+ DDRSS0_PHY_1370_DATA
+ DDRSS0_PHY_1371_DATA
+ DDRSS0_PHY_1372_DATA
+ DDRSS0_PHY_1373_DATA
+ DDRSS0_PHY_1374_DATA
+ DDRSS0_PHY_1375_DATA
+ DDRSS0_PHY_1376_DATA
+ DDRSS0_PHY_1377_DATA
+ DDRSS0_PHY_1378_DATA
+ DDRSS0_PHY_1379_DATA
+ DDRSS0_PHY_1380_DATA
+ DDRSS0_PHY_1381_DATA
+ DDRSS0_PHY_1382_DATA
+ DDRSS0_PHY_1383_DATA
+ DDRSS0_PHY_1384_DATA
+ DDRSS0_PHY_1385_DATA
+ DDRSS0_PHY_1386_DATA
+ DDRSS0_PHY_1387_DATA
+ DDRSS0_PHY_1388_DATA
+ DDRSS0_PHY_1389_DATA
+ DDRSS0_PHY_1390_DATA
+ DDRSS0_PHY_1391_DATA
+ DDRSS0_PHY_1392_DATA
+ DDRSS0_PHY_1393_DATA
+ DDRSS0_PHY_1394_DATA
+ DDRSS0_PHY_1395_DATA
+ DDRSS0_PHY_1396_DATA
+ DDRSS0_PHY_1397_DATA
+ DDRSS0_PHY_1398_DATA
+ DDRSS0_PHY_1399_DATA
+ DDRSS0_PHY_1400_DATA
+ DDRSS0_PHY_1401_DATA
+ DDRSS0_PHY_1402_DATA
+ DDRSS0_PHY_1403_DATA
+ DDRSS0_PHY_1404_DATA
+ DDRSS0_PHY_1405_DATA
+ DDRSS0_PHY_1406_DATA
+ DDRSS0_PHY_1407_DATA
+ DDRSS0_PHY_1408_DATA
+ DDRSS0_PHY_1409_DATA
+ DDRSS0_PHY_1410_DATA
+ DDRSS0_PHY_1411_DATA
+ DDRSS0_PHY_1412_DATA
+ DDRSS0_PHY_1413_DATA
+ DDRSS0_PHY_1414_DATA
+ DDRSS0_PHY_1415_DATA
+ DDRSS0_PHY_1416_DATA
+ DDRSS0_PHY_1417_DATA
+ DDRSS0_PHY_1418_DATA
+ DDRSS0_PHY_1419_DATA
+ DDRSS0_PHY_1420_DATA
+ DDRSS0_PHY_1421_DATA
+ DDRSS0_PHY_1422_DATA
+ >;
+ };
+
+ memorycontroller1: memorycontroller@29b0000 {
+ compatible = "ti,j721s2-ddrss";
+ reg = <0x0 0x029b0000 0x0 0x4000>,
+ <0x0 0x0114000 0x0 0x100>;
+ reg-names = "cfg", "ctrl_mmr_lp4";
+ power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
+ <&k3_pds 132 TI_SCI_PD_SHARED>;
+ clocks = <&k3_clks 192 1>, <&k3_clks 78 2>;
+ ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+ ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+ ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+ ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+ instance = <1>;
+
+ u-boot,dm-spl;
+
+ ti,ctl-data = <
+ DDRSS1_CTL_00_DATA
+ DDRSS1_CTL_01_DATA
+ DDRSS1_CTL_02_DATA
+ DDRSS1_CTL_03_DATA
+ DDRSS1_CTL_04_DATA
+ DDRSS1_CTL_05_DATA
+ DDRSS1_CTL_06_DATA
+ DDRSS1_CTL_07_DATA
+ DDRSS1_CTL_08_DATA
+ DDRSS1_CTL_09_DATA
+ DDRSS1_CTL_10_DATA
+ DDRSS1_CTL_11_DATA
+ DDRSS1_CTL_12_DATA
+ DDRSS1_CTL_13_DATA
+ DDRSS1_CTL_14_DATA
+ DDRSS1_CTL_15_DATA
+ DDRSS1_CTL_16_DATA
+ DDRSS1_CTL_17_DATA
+ DDRSS1_CTL_18_DATA
+ DDRSS1_CTL_19_DATA
+ DDRSS1_CTL_20_DATA
+ DDRSS1_CTL_21_DATA
+ DDRSS1_CTL_22_DATA
+ DDRSS1_CTL_23_DATA
+ DDRSS1_CTL_24_DATA
+ DDRSS1_CTL_25_DATA
+ DDRSS1_CTL_26_DATA
+ DDRSS1_CTL_27_DATA
+ DDRSS1_CTL_28_DATA
+ DDRSS1_CTL_29_DATA
+ DDRSS1_CTL_30_DATA
+ DDRSS1_CTL_31_DATA
+ DDRSS1_CTL_32_DATA
+ DDRSS1_CTL_33_DATA
+ DDRSS1_CTL_34_DATA
+ DDRSS1_CTL_35_DATA
+ DDRSS1_CTL_36_DATA
+ DDRSS1_CTL_37_DATA
+ DDRSS1_CTL_38_DATA
+ DDRSS1_CTL_39_DATA
+ DDRSS1_CTL_40_DATA
+ DDRSS1_CTL_41_DATA
+ DDRSS1_CTL_42_DATA
+ DDRSS1_CTL_43_DATA
+ DDRSS1_CTL_44_DATA
+ DDRSS1_CTL_45_DATA
+ DDRSS1_CTL_46_DATA
+ DDRSS1_CTL_47_DATA
+ DDRSS1_CTL_48_DATA
+ DDRSS1_CTL_49_DATA
+ DDRSS1_CTL_50_DATA
+ DDRSS1_CTL_51_DATA
+ DDRSS1_CTL_52_DATA
+ DDRSS1_CTL_53_DATA
+ DDRSS1_CTL_54_DATA
+ DDRSS1_CTL_55_DATA
+ DDRSS1_CTL_56_DATA
+ DDRSS1_CTL_57_DATA
+ DDRSS1_CTL_58_DATA
+ DDRSS1_CTL_59_DATA
+ DDRSS1_CTL_60_DATA
+ DDRSS1_CTL_61_DATA
+ DDRSS1_CTL_62_DATA
+ DDRSS1_CTL_63_DATA
+ DDRSS1_CTL_64_DATA
+ DDRSS1_CTL_65_DATA
+ DDRSS1_CTL_66_DATA
+ DDRSS1_CTL_67_DATA
+ DDRSS1_CTL_68_DATA
+ DDRSS1_CTL_69_DATA
+ DDRSS1_CTL_70_DATA
+ DDRSS1_CTL_71_DATA
+ DDRSS1_CTL_72_DATA
+ DDRSS1_CTL_73_DATA
+ DDRSS1_CTL_74_DATA
+ DDRSS1_CTL_75_DATA
+ DDRSS1_CTL_76_DATA
+ DDRSS1_CTL_77_DATA
+ DDRSS1_CTL_78_DATA
+ DDRSS1_CTL_79_DATA
+ DDRSS1_CTL_80_DATA
+ DDRSS1_CTL_81_DATA
+ DDRSS1_CTL_82_DATA
+ DDRSS1_CTL_83_DATA
+ DDRSS1_CTL_84_DATA
+ DDRSS1_CTL_85_DATA
+ DDRSS1_CTL_86_DATA
+ DDRSS1_CTL_87_DATA
+ DDRSS1_CTL_88_DATA
+ DDRSS1_CTL_89_DATA
+ DDRSS1_CTL_90_DATA
+ DDRSS1_CTL_91_DATA
+ DDRSS1_CTL_92_DATA
+ DDRSS1_CTL_93_DATA
+ DDRSS1_CTL_94_DATA
+ DDRSS1_CTL_95_DATA
+ DDRSS1_CTL_96_DATA
+ DDRSS1_CTL_97_DATA
+ DDRSS1_CTL_98_DATA
+ DDRSS1_CTL_99_DATA
+ DDRSS1_CTL_100_DATA
+ DDRSS1_CTL_101_DATA
+ DDRSS1_CTL_102_DATA
+ DDRSS1_CTL_103_DATA
+ DDRSS1_CTL_104_DATA
+ DDRSS1_CTL_105_DATA
+ DDRSS1_CTL_106_DATA
+ DDRSS1_CTL_107_DATA
+ DDRSS1_CTL_108_DATA
+ DDRSS1_CTL_109_DATA
+ DDRSS1_CTL_110_DATA
+ DDRSS1_CTL_111_DATA
+ DDRSS1_CTL_112_DATA
+ DDRSS1_CTL_113_DATA
+ DDRSS1_CTL_114_DATA
+ DDRSS1_CTL_115_DATA
+ DDRSS1_CTL_116_DATA
+ DDRSS1_CTL_117_DATA
+ DDRSS1_CTL_118_DATA
+ DDRSS1_CTL_119_DATA
+ DDRSS1_CTL_120_DATA
+ DDRSS1_CTL_121_DATA
+ DDRSS1_CTL_122_DATA
+ DDRSS1_CTL_123_DATA
+ DDRSS1_CTL_124_DATA
+ DDRSS1_CTL_125_DATA
+ DDRSS1_CTL_126_DATA
+ DDRSS1_CTL_127_DATA
+ DDRSS1_CTL_128_DATA
+ DDRSS1_CTL_129_DATA
+ DDRSS1_CTL_130_DATA
+ DDRSS1_CTL_131_DATA
+ DDRSS1_CTL_132_DATA
+ DDRSS1_CTL_133_DATA
+ DDRSS1_CTL_134_DATA
+ DDRSS1_CTL_135_DATA
+ DDRSS1_CTL_136_DATA
+ DDRSS1_CTL_137_DATA
+ DDRSS1_CTL_138_DATA
+ DDRSS1_CTL_139_DATA
+ DDRSS1_CTL_140_DATA
+ DDRSS1_CTL_141_DATA
+ DDRSS1_CTL_142_DATA
+ DDRSS1_CTL_143_DATA
+ DDRSS1_CTL_144_DATA
+ DDRSS1_CTL_145_DATA
+ DDRSS1_CTL_146_DATA
+ DDRSS1_CTL_147_DATA
+ DDRSS1_CTL_148_DATA
+ DDRSS1_CTL_149_DATA
+ DDRSS1_CTL_150_DATA
+ DDRSS1_CTL_151_DATA
+ DDRSS1_CTL_152_DATA
+ DDRSS1_CTL_153_DATA
+ DDRSS1_CTL_154_DATA
+ DDRSS1_CTL_155_DATA
+ DDRSS1_CTL_156_DATA
+ DDRSS1_CTL_157_DATA
+ DDRSS1_CTL_158_DATA
+ DDRSS1_CTL_159_DATA
+ DDRSS1_CTL_160_DATA
+ DDRSS1_CTL_161_DATA
+ DDRSS1_CTL_162_DATA
+ DDRSS1_CTL_163_DATA
+ DDRSS1_CTL_164_DATA
+ DDRSS1_CTL_165_DATA
+ DDRSS1_CTL_166_DATA
+ DDRSS1_CTL_167_DATA
+ DDRSS1_CTL_168_DATA
+ DDRSS1_CTL_169_DATA
+ DDRSS1_CTL_170_DATA
+ DDRSS1_CTL_171_DATA
+ DDRSS1_CTL_172_DATA
+ DDRSS1_CTL_173_DATA
+ DDRSS1_CTL_174_DATA
+ DDRSS1_CTL_175_DATA
+ DDRSS1_CTL_176_DATA
+ DDRSS1_CTL_177_DATA
+ DDRSS1_CTL_178_DATA
+ DDRSS1_CTL_179_DATA
+ DDRSS1_CTL_180_DATA
+ DDRSS1_CTL_181_DATA
+ DDRSS1_CTL_182_DATA
+ DDRSS1_CTL_183_DATA
+ DDRSS1_CTL_184_DATA
+ DDRSS1_CTL_185_DATA
+ DDRSS1_CTL_186_DATA
+ DDRSS1_CTL_187_DATA
+ DDRSS1_CTL_188_DATA
+ DDRSS1_CTL_189_DATA
+ DDRSS1_CTL_190_DATA
+ DDRSS1_CTL_191_DATA
+ DDRSS1_CTL_192_DATA
+ DDRSS1_CTL_193_DATA
+ DDRSS1_CTL_194_DATA
+ DDRSS1_CTL_195_DATA
+ DDRSS1_CTL_196_DATA
+ DDRSS1_CTL_197_DATA
+ DDRSS1_CTL_198_DATA
+ DDRSS1_CTL_199_DATA
+ DDRSS1_CTL_200_DATA
+ DDRSS1_CTL_201_DATA
+ DDRSS1_CTL_202_DATA
+ DDRSS1_CTL_203_DATA
+ DDRSS1_CTL_204_DATA
+ DDRSS1_CTL_205_DATA
+ DDRSS1_CTL_206_DATA
+ DDRSS1_CTL_207_DATA
+ DDRSS1_CTL_208_DATA
+ DDRSS1_CTL_209_DATA
+ DDRSS1_CTL_210_DATA
+ DDRSS1_CTL_211_DATA
+ DDRSS1_CTL_212_DATA
+ DDRSS1_CTL_213_DATA
+ DDRSS1_CTL_214_DATA
+ DDRSS1_CTL_215_DATA
+ DDRSS1_CTL_216_DATA
+ DDRSS1_CTL_217_DATA
+ DDRSS1_CTL_218_DATA
+ DDRSS1_CTL_219_DATA
+ DDRSS1_CTL_220_DATA
+ DDRSS1_CTL_221_DATA
+ DDRSS1_CTL_222_DATA
+ DDRSS1_CTL_223_DATA
+ DDRSS1_CTL_224_DATA
+ DDRSS1_CTL_225_DATA
+ DDRSS1_CTL_226_DATA
+ DDRSS1_CTL_227_DATA
+ DDRSS1_CTL_228_DATA
+ DDRSS1_CTL_229_DATA
+ DDRSS1_CTL_230_DATA
+ DDRSS1_CTL_231_DATA
+ DDRSS1_CTL_232_DATA
+ DDRSS1_CTL_233_DATA
+ DDRSS1_CTL_234_DATA
+ DDRSS1_CTL_235_DATA
+ DDRSS1_CTL_236_DATA
+ DDRSS1_CTL_237_DATA
+ DDRSS1_CTL_238_DATA
+ DDRSS1_CTL_239_DATA
+ DDRSS1_CTL_240_DATA
+ DDRSS1_CTL_241_DATA
+ DDRSS1_CTL_242_DATA
+ DDRSS1_CTL_243_DATA
+ DDRSS1_CTL_244_DATA
+ DDRSS1_CTL_245_DATA
+ DDRSS1_CTL_246_DATA
+ DDRSS1_CTL_247_DATA
+ DDRSS1_CTL_248_DATA
+ DDRSS1_CTL_249_DATA
+ DDRSS1_CTL_250_DATA
+ DDRSS1_CTL_251_DATA
+ DDRSS1_CTL_252_DATA
+ DDRSS1_CTL_253_DATA
+ DDRSS1_CTL_254_DATA
+ DDRSS1_CTL_255_DATA
+ DDRSS1_CTL_256_DATA
+ DDRSS1_CTL_257_DATA
+ DDRSS1_CTL_258_DATA
+ DDRSS1_CTL_259_DATA
+ DDRSS1_CTL_260_DATA
+ DDRSS1_CTL_261_DATA
+ DDRSS1_CTL_262_DATA
+ DDRSS1_CTL_263_DATA
+ DDRSS1_CTL_264_DATA
+ DDRSS1_CTL_265_DATA
+ DDRSS1_CTL_266_DATA
+ DDRSS1_CTL_267_DATA
+ DDRSS1_CTL_268_DATA
+ DDRSS1_CTL_269_DATA
+ DDRSS1_CTL_270_DATA
+ DDRSS1_CTL_271_DATA
+ DDRSS1_CTL_272_DATA
+ DDRSS1_CTL_273_DATA
+ DDRSS1_CTL_274_DATA
+ DDRSS1_CTL_275_DATA
+ DDRSS1_CTL_276_DATA
+ DDRSS1_CTL_277_DATA
+ DDRSS1_CTL_278_DATA
+ DDRSS1_CTL_279_DATA
+ DDRSS1_CTL_280_DATA
+ DDRSS1_CTL_281_DATA
+ DDRSS1_CTL_282_DATA
+ DDRSS1_CTL_283_DATA
+ DDRSS1_CTL_284_DATA
+ DDRSS1_CTL_285_DATA
+ DDRSS1_CTL_286_DATA
+ DDRSS1_CTL_287_DATA
+ DDRSS1_CTL_288_DATA
+ DDRSS1_CTL_289_DATA
+ DDRSS1_CTL_290_DATA
+ DDRSS1_CTL_291_DATA
+ DDRSS1_CTL_292_DATA
+ DDRSS1_CTL_293_DATA
+ DDRSS1_CTL_294_DATA
+ DDRSS1_CTL_295_DATA
+ DDRSS1_CTL_296_DATA
+ DDRSS1_CTL_297_DATA
+ DDRSS1_CTL_298_DATA
+ DDRSS1_CTL_299_DATA
+ DDRSS1_CTL_300_DATA
+ DDRSS1_CTL_301_DATA
+ DDRSS1_CTL_302_DATA
+ DDRSS1_CTL_303_DATA
+ DDRSS1_CTL_304_DATA
+ DDRSS1_CTL_305_DATA
+ DDRSS1_CTL_306_DATA
+ DDRSS1_CTL_307_DATA
+ DDRSS1_CTL_308_DATA
+ DDRSS1_CTL_309_DATA
+ DDRSS1_CTL_310_DATA
+ DDRSS1_CTL_311_DATA
+ DDRSS1_CTL_312_DATA
+ DDRSS1_CTL_313_DATA
+ DDRSS1_CTL_314_DATA
+ DDRSS1_CTL_315_DATA
+ DDRSS1_CTL_316_DATA
+ DDRSS1_CTL_317_DATA
+ DDRSS1_CTL_318_DATA
+ DDRSS1_CTL_319_DATA
+ DDRSS1_CTL_320_DATA
+ DDRSS1_CTL_321_DATA
+ DDRSS1_CTL_322_DATA
+ DDRSS1_CTL_323_DATA
+ DDRSS1_CTL_324_DATA
+ DDRSS1_CTL_325_DATA
+ DDRSS1_CTL_326_DATA
+ DDRSS1_CTL_327_DATA
+ DDRSS1_CTL_328_DATA
+ DDRSS1_CTL_329_DATA
+ DDRSS1_CTL_330_DATA
+ DDRSS1_CTL_331_DATA
+ DDRSS1_CTL_332_DATA
+ DDRSS1_CTL_333_DATA
+ DDRSS1_CTL_334_DATA
+ DDRSS1_CTL_335_DATA
+ DDRSS1_CTL_336_DATA
+ DDRSS1_CTL_337_DATA
+ DDRSS1_CTL_338_DATA
+ DDRSS1_CTL_339_DATA
+ DDRSS1_CTL_340_DATA
+ DDRSS1_CTL_341_DATA
+ DDRSS1_CTL_342_DATA
+ DDRSS1_CTL_343_DATA
+ DDRSS1_CTL_344_DATA
+ DDRSS1_CTL_345_DATA
+ DDRSS1_CTL_346_DATA
+ DDRSS1_CTL_347_DATA
+ DDRSS1_CTL_348_DATA
+ DDRSS1_CTL_349_DATA
+ DDRSS1_CTL_350_DATA
+ DDRSS1_CTL_351_DATA
+ DDRSS1_CTL_352_DATA
+ DDRSS1_CTL_353_DATA
+ DDRSS1_CTL_354_DATA
+ DDRSS1_CTL_355_DATA
+ DDRSS1_CTL_356_DATA
+ DDRSS1_CTL_357_DATA
+ DDRSS1_CTL_358_DATA
+ DDRSS1_CTL_359_DATA
+ DDRSS1_CTL_360_DATA
+ DDRSS1_CTL_361_DATA
+ DDRSS1_CTL_362_DATA
+ DDRSS1_CTL_363_DATA
+ DDRSS1_CTL_364_DATA
+ DDRSS1_CTL_365_DATA
+ DDRSS1_CTL_366_DATA
+ DDRSS1_CTL_367_DATA
+ DDRSS1_CTL_368_DATA
+ DDRSS1_CTL_369_DATA
+ DDRSS1_CTL_370_DATA
+ DDRSS1_CTL_371_DATA
+ DDRSS1_CTL_372_DATA
+ DDRSS1_CTL_373_DATA
+ DDRSS1_CTL_374_DATA
+ DDRSS1_CTL_375_DATA
+ DDRSS1_CTL_376_DATA
+ DDRSS1_CTL_377_DATA
+ DDRSS1_CTL_378_DATA
+ DDRSS1_CTL_379_DATA
+ DDRSS1_CTL_380_DATA
+ DDRSS1_CTL_381_DATA
+ DDRSS1_CTL_382_DATA
+ DDRSS1_CTL_383_DATA
+ DDRSS1_CTL_384_DATA
+ DDRSS1_CTL_385_DATA
+ DDRSS1_CTL_386_DATA
+ DDRSS1_CTL_387_DATA
+ DDRSS1_CTL_388_DATA
+ DDRSS1_CTL_389_DATA
+ DDRSS1_CTL_390_DATA
+ DDRSS1_CTL_391_DATA
+ DDRSS1_CTL_392_DATA
+ DDRSS1_CTL_393_DATA
+ DDRSS1_CTL_394_DATA
+ DDRSS1_CTL_395_DATA
+ DDRSS1_CTL_396_DATA
+ DDRSS1_CTL_397_DATA
+ DDRSS1_CTL_398_DATA
+ DDRSS1_CTL_399_DATA
+ DDRSS1_CTL_400_DATA
+ DDRSS1_CTL_401_DATA
+ DDRSS1_CTL_402_DATA
+ DDRSS1_CTL_403_DATA
+ DDRSS1_CTL_404_DATA
+ DDRSS1_CTL_405_DATA
+ DDRSS1_CTL_406_DATA
+ DDRSS1_CTL_407_DATA
+ DDRSS1_CTL_408_DATA
+ DDRSS1_CTL_409_DATA
+ DDRSS1_CTL_410_DATA
+ DDRSS1_CTL_411_DATA
+ DDRSS1_CTL_412_DATA
+ DDRSS1_CTL_413_DATA
+ DDRSS1_CTL_414_DATA
+ DDRSS1_CTL_415_DATA
+ DDRSS1_CTL_416_DATA
+ DDRSS1_CTL_417_DATA
+ DDRSS1_CTL_418_DATA
+ DDRSS1_CTL_419_DATA
+ DDRSS1_CTL_420_DATA
+ DDRSS1_CTL_421_DATA
+ DDRSS1_CTL_422_DATA
+ DDRSS1_CTL_423_DATA
+ DDRSS1_CTL_424_DATA
+ DDRSS1_CTL_425_DATA
+ DDRSS1_CTL_426_DATA
+ DDRSS1_CTL_427_DATA
+ DDRSS1_CTL_428_DATA
+ DDRSS1_CTL_429_DATA
+ DDRSS1_CTL_430_DATA
+ DDRSS1_CTL_431_DATA
+ DDRSS1_CTL_432_DATA
+ DDRSS1_CTL_433_DATA
+ DDRSS1_CTL_434_DATA
+ DDRSS1_CTL_435_DATA
+ DDRSS1_CTL_436_DATA
+ DDRSS1_CTL_437_DATA
+ DDRSS1_CTL_438_DATA
+ DDRSS1_CTL_439_DATA
+ DDRSS1_CTL_440_DATA
+ DDRSS1_CTL_441_DATA
+ DDRSS1_CTL_442_DATA
+ DDRSS1_CTL_443_DATA
+ DDRSS1_CTL_444_DATA
+ DDRSS1_CTL_445_DATA
+ DDRSS1_CTL_446_DATA
+ DDRSS1_CTL_447_DATA
+ DDRSS1_CTL_448_DATA
+ DDRSS1_CTL_449_DATA
+ DDRSS1_CTL_450_DATA
+ DDRSS1_CTL_451_DATA
+ DDRSS1_CTL_452_DATA
+ DDRSS1_CTL_453_DATA
+ DDRSS1_CTL_454_DATA
+ DDRSS1_CTL_455_DATA
+ DDRSS1_CTL_456_DATA
+ DDRSS1_CTL_457_DATA
+ DDRSS1_CTL_458_DATA
+ >;
+
+ ti,pi-data = <
+ DDRSS1_PI_00_DATA
+ DDRSS1_PI_01_DATA
+ DDRSS1_PI_02_DATA
+ DDRSS1_PI_03_DATA
+ DDRSS1_PI_04_DATA
+ DDRSS1_PI_05_DATA
+ DDRSS1_PI_06_DATA
+ DDRSS1_PI_07_DATA
+ DDRSS1_PI_08_DATA
+ DDRSS1_PI_09_DATA
+ DDRSS1_PI_10_DATA
+ DDRSS1_PI_11_DATA
+ DDRSS1_PI_12_DATA
+ DDRSS1_PI_13_DATA
+ DDRSS1_PI_14_DATA
+ DDRSS1_PI_15_DATA
+ DDRSS1_PI_16_DATA
+ DDRSS1_PI_17_DATA
+ DDRSS1_PI_18_DATA
+ DDRSS1_PI_19_DATA
+ DDRSS1_PI_20_DATA
+ DDRSS1_PI_21_DATA
+ DDRSS1_PI_22_DATA
+ DDRSS1_PI_23_DATA
+ DDRSS1_PI_24_DATA
+ DDRSS1_PI_25_DATA
+ DDRSS1_PI_26_DATA
+ DDRSS1_PI_27_DATA
+ DDRSS1_PI_28_DATA
+ DDRSS1_PI_29_DATA
+ DDRSS1_PI_30_DATA
+ DDRSS1_PI_31_DATA
+ DDRSS1_PI_32_DATA
+ DDRSS1_PI_33_DATA
+ DDRSS1_PI_34_DATA
+ DDRSS1_PI_35_DATA
+ DDRSS1_PI_36_DATA
+ DDRSS1_PI_37_DATA
+ DDRSS1_PI_38_DATA
+ DDRSS1_PI_39_DATA
+ DDRSS1_PI_40_DATA
+ DDRSS1_PI_41_DATA
+ DDRSS1_PI_42_DATA
+ DDRSS1_PI_43_DATA
+ DDRSS1_PI_44_DATA
+ DDRSS1_PI_45_DATA
+ DDRSS1_PI_46_DATA
+ DDRSS1_PI_47_DATA
+ DDRSS1_PI_48_DATA
+ DDRSS1_PI_49_DATA
+ DDRSS1_PI_50_DATA
+ DDRSS1_PI_51_DATA
+ DDRSS1_PI_52_DATA
+ DDRSS1_PI_53_DATA
+ DDRSS1_PI_54_DATA
+ DDRSS1_PI_55_DATA
+ DDRSS1_PI_56_DATA
+ DDRSS1_PI_57_DATA
+ DDRSS1_PI_58_DATA
+ DDRSS1_PI_59_DATA
+ DDRSS1_PI_60_DATA
+ DDRSS1_PI_61_DATA
+ DDRSS1_PI_62_DATA
+ DDRSS1_PI_63_DATA
+ DDRSS1_PI_64_DATA
+ DDRSS1_PI_65_DATA
+ DDRSS1_PI_66_DATA
+ DDRSS1_PI_67_DATA
+ DDRSS1_PI_68_DATA
+ DDRSS1_PI_69_DATA
+ DDRSS1_PI_70_DATA
+ DDRSS1_PI_71_DATA
+ DDRSS1_PI_72_DATA
+ DDRSS1_PI_73_DATA
+ DDRSS1_PI_74_DATA
+ DDRSS1_PI_75_DATA
+ DDRSS1_PI_76_DATA
+ DDRSS1_PI_77_DATA
+ DDRSS1_PI_78_DATA
+ DDRSS1_PI_79_DATA
+ DDRSS1_PI_80_DATA
+ DDRSS1_PI_81_DATA
+ DDRSS1_PI_82_DATA
+ DDRSS1_PI_83_DATA
+ DDRSS1_PI_84_DATA
+ DDRSS1_PI_85_DATA
+ DDRSS1_PI_86_DATA
+ DDRSS1_PI_87_DATA
+ DDRSS1_PI_88_DATA
+ DDRSS1_PI_89_DATA
+ DDRSS1_PI_90_DATA
+ DDRSS1_PI_91_DATA
+ DDRSS1_PI_92_DATA
+ DDRSS1_PI_93_DATA
+ DDRSS1_PI_94_DATA
+ DDRSS1_PI_95_DATA
+ DDRSS1_PI_96_DATA
+ DDRSS1_PI_97_DATA
+ DDRSS1_PI_98_DATA
+ DDRSS1_PI_99_DATA
+ DDRSS1_PI_100_DATA
+ DDRSS1_PI_101_DATA
+ DDRSS1_PI_102_DATA
+ DDRSS1_PI_103_DATA
+ DDRSS1_PI_104_DATA
+ DDRSS1_PI_105_DATA
+ DDRSS1_PI_106_DATA
+ DDRSS1_PI_107_DATA
+ DDRSS1_PI_108_DATA
+ DDRSS1_PI_109_DATA
+ DDRSS1_PI_110_DATA
+ DDRSS1_PI_111_DATA
+ DDRSS1_PI_112_DATA
+ DDRSS1_PI_113_DATA
+ DDRSS1_PI_114_DATA
+ DDRSS1_PI_115_DATA
+ DDRSS1_PI_116_DATA
+ DDRSS1_PI_117_DATA
+ DDRSS1_PI_118_DATA
+ DDRSS1_PI_119_DATA
+ DDRSS1_PI_120_DATA
+ DDRSS1_PI_121_DATA
+ DDRSS1_PI_122_DATA
+ DDRSS1_PI_123_DATA
+ DDRSS1_PI_124_DATA
+ DDRSS1_PI_125_DATA
+ DDRSS1_PI_126_DATA
+ DDRSS1_PI_127_DATA
+ DDRSS1_PI_128_DATA
+ DDRSS1_PI_129_DATA
+ DDRSS1_PI_130_DATA
+ DDRSS1_PI_131_DATA
+ DDRSS1_PI_132_DATA
+ DDRSS1_PI_133_DATA
+ DDRSS1_PI_134_DATA
+ DDRSS1_PI_135_DATA
+ DDRSS1_PI_136_DATA
+ DDRSS1_PI_137_DATA
+ DDRSS1_PI_138_DATA
+ DDRSS1_PI_139_DATA
+ DDRSS1_PI_140_DATA
+ DDRSS1_PI_141_DATA
+ DDRSS1_PI_142_DATA
+ DDRSS1_PI_143_DATA
+ DDRSS1_PI_144_DATA
+ DDRSS1_PI_145_DATA
+ DDRSS1_PI_146_DATA
+ DDRSS1_PI_147_DATA
+ DDRSS1_PI_148_DATA
+ DDRSS1_PI_149_DATA
+ DDRSS1_PI_150_DATA
+ DDRSS1_PI_151_DATA
+ DDRSS1_PI_152_DATA
+ DDRSS1_PI_153_DATA
+ DDRSS1_PI_154_DATA
+ DDRSS1_PI_155_DATA
+ DDRSS1_PI_156_DATA
+ DDRSS1_PI_157_DATA
+ DDRSS1_PI_158_DATA
+ DDRSS1_PI_159_DATA
+ DDRSS1_PI_160_DATA
+ DDRSS1_PI_161_DATA
+ DDRSS1_PI_162_DATA
+ DDRSS1_PI_163_DATA
+ DDRSS1_PI_164_DATA
+ DDRSS1_PI_165_DATA
+ DDRSS1_PI_166_DATA
+ DDRSS1_PI_167_DATA
+ DDRSS1_PI_168_DATA
+ DDRSS1_PI_169_DATA
+ DDRSS1_PI_170_DATA
+ DDRSS1_PI_171_DATA
+ DDRSS1_PI_172_DATA
+ DDRSS1_PI_173_DATA
+ DDRSS1_PI_174_DATA
+ DDRSS1_PI_175_DATA
+ DDRSS1_PI_176_DATA
+ DDRSS1_PI_177_DATA
+ DDRSS1_PI_178_DATA
+ DDRSS1_PI_179_DATA
+ DDRSS1_PI_180_DATA
+ DDRSS1_PI_181_DATA
+ DDRSS1_PI_182_DATA
+ DDRSS1_PI_183_DATA
+ DDRSS1_PI_184_DATA
+ DDRSS1_PI_185_DATA
+ DDRSS1_PI_186_DATA
+ DDRSS1_PI_187_DATA
+ DDRSS1_PI_188_DATA
+ DDRSS1_PI_189_DATA
+ DDRSS1_PI_190_DATA
+ DDRSS1_PI_191_DATA
+ DDRSS1_PI_192_DATA
+ DDRSS1_PI_193_DATA
+ DDRSS1_PI_194_DATA
+ DDRSS1_PI_195_DATA
+ DDRSS1_PI_196_DATA
+ DDRSS1_PI_197_DATA
+ DDRSS1_PI_198_DATA
+ DDRSS1_PI_199_DATA
+ DDRSS1_PI_200_DATA
+ DDRSS1_PI_201_DATA
+ DDRSS1_PI_202_DATA
+ DDRSS1_PI_203_DATA
+ DDRSS1_PI_204_DATA
+ DDRSS1_PI_205_DATA
+ DDRSS1_PI_206_DATA
+ DDRSS1_PI_207_DATA
+ DDRSS1_PI_208_DATA
+ DDRSS1_PI_209_DATA
+ DDRSS1_PI_210_DATA
+ DDRSS1_PI_211_DATA
+ DDRSS1_PI_212_DATA
+ DDRSS1_PI_213_DATA
+ DDRSS1_PI_214_DATA
+ DDRSS1_PI_215_DATA
+ DDRSS1_PI_216_DATA
+ DDRSS1_PI_217_DATA
+ DDRSS1_PI_218_DATA
+ DDRSS1_PI_219_DATA
+ DDRSS1_PI_220_DATA
+ DDRSS1_PI_221_DATA
+ DDRSS1_PI_222_DATA
+ DDRSS1_PI_223_DATA
+ DDRSS1_PI_224_DATA
+ DDRSS1_PI_225_DATA
+ DDRSS1_PI_226_DATA
+ DDRSS1_PI_227_DATA
+ DDRSS1_PI_228_DATA
+ DDRSS1_PI_229_DATA
+ DDRSS1_PI_230_DATA
+ DDRSS1_PI_231_DATA
+ DDRSS1_PI_232_DATA
+ DDRSS1_PI_233_DATA
+ DDRSS1_PI_234_DATA
+ DDRSS1_PI_235_DATA
+ DDRSS1_PI_236_DATA
+ DDRSS1_PI_237_DATA
+ DDRSS1_PI_238_DATA
+ DDRSS1_PI_239_DATA
+ DDRSS1_PI_240_DATA
+ DDRSS1_PI_241_DATA
+ DDRSS1_PI_242_DATA
+ DDRSS1_PI_243_DATA
+ DDRSS1_PI_244_DATA
+ DDRSS1_PI_245_DATA
+ DDRSS1_PI_246_DATA
+ DDRSS1_PI_247_DATA
+ DDRSS1_PI_248_DATA
+ DDRSS1_PI_249_DATA
+ DDRSS1_PI_250_DATA
+ DDRSS1_PI_251_DATA
+ DDRSS1_PI_252_DATA
+ DDRSS1_PI_253_DATA
+ DDRSS1_PI_254_DATA
+ DDRSS1_PI_255_DATA
+ DDRSS1_PI_256_DATA
+ DDRSS1_PI_257_DATA
+ DDRSS1_PI_258_DATA
+ DDRSS1_PI_259_DATA
+ DDRSS1_PI_260_DATA
+ DDRSS1_PI_261_DATA
+ DDRSS1_PI_262_DATA
+ DDRSS1_PI_263_DATA
+ DDRSS1_PI_264_DATA
+ DDRSS1_PI_265_DATA
+ DDRSS1_PI_266_DATA
+ DDRSS1_PI_267_DATA
+ DDRSS1_PI_268_DATA
+ DDRSS1_PI_269_DATA
+ DDRSS1_PI_270_DATA
+ DDRSS1_PI_271_DATA
+ DDRSS1_PI_272_DATA
+ DDRSS1_PI_273_DATA
+ DDRSS1_PI_274_DATA
+ DDRSS1_PI_275_DATA
+ DDRSS1_PI_276_DATA
+ DDRSS1_PI_277_DATA
+ DDRSS1_PI_278_DATA
+ DDRSS1_PI_279_DATA
+ DDRSS1_PI_280_DATA
+ DDRSS1_PI_281_DATA
+ DDRSS1_PI_282_DATA
+ DDRSS1_PI_283_DATA
+ DDRSS1_PI_284_DATA
+ DDRSS1_PI_285_DATA
+ DDRSS1_PI_286_DATA
+ DDRSS1_PI_287_DATA
+ DDRSS1_PI_288_DATA
+ DDRSS1_PI_289_DATA
+ DDRSS1_PI_290_DATA
+ DDRSS1_PI_291_DATA
+ DDRSS1_PI_292_DATA
+ DDRSS1_PI_293_DATA
+ DDRSS1_PI_294_DATA
+ DDRSS1_PI_295_DATA
+ DDRSS1_PI_296_DATA
+ DDRSS1_PI_297_DATA
+ DDRSS1_PI_298_DATA
+ DDRSS1_PI_299_DATA
+ >;
+
+ ti,phy-data = <
+ DDRSS1_PHY_00_DATA
+ DDRSS1_PHY_01_DATA
+ DDRSS1_PHY_02_DATA
+ DDRSS1_PHY_03_DATA
+ DDRSS1_PHY_04_DATA
+ DDRSS1_PHY_05_DATA
+ DDRSS1_PHY_06_DATA
+ DDRSS1_PHY_07_DATA
+ DDRSS1_PHY_08_DATA
+ DDRSS1_PHY_09_DATA
+ DDRSS1_PHY_10_DATA
+ DDRSS1_PHY_11_DATA
+ DDRSS1_PHY_12_DATA
+ DDRSS1_PHY_13_DATA
+ DDRSS1_PHY_14_DATA
+ DDRSS1_PHY_15_DATA
+ DDRSS1_PHY_16_DATA
+ DDRSS1_PHY_17_DATA
+ DDRSS1_PHY_18_DATA
+ DDRSS1_PHY_19_DATA
+ DDRSS1_PHY_20_DATA
+ DDRSS1_PHY_21_DATA
+ DDRSS1_PHY_22_DATA
+ DDRSS1_PHY_23_DATA
+ DDRSS1_PHY_24_DATA
+ DDRSS1_PHY_25_DATA
+ DDRSS1_PHY_26_DATA
+ DDRSS1_PHY_27_DATA
+ DDRSS1_PHY_28_DATA
+ DDRSS1_PHY_29_DATA
+ DDRSS1_PHY_30_DATA
+ DDRSS1_PHY_31_DATA
+ DDRSS1_PHY_32_DATA
+ DDRSS1_PHY_33_DATA
+ DDRSS1_PHY_34_DATA
+ DDRSS1_PHY_35_DATA
+ DDRSS1_PHY_36_DATA
+ DDRSS1_PHY_37_DATA
+ DDRSS1_PHY_38_DATA
+ DDRSS1_PHY_39_DATA
+ DDRSS1_PHY_40_DATA
+ DDRSS1_PHY_41_DATA
+ DDRSS1_PHY_42_DATA
+ DDRSS1_PHY_43_DATA
+ DDRSS1_PHY_44_DATA
+ DDRSS1_PHY_45_DATA
+ DDRSS1_PHY_46_DATA
+ DDRSS1_PHY_47_DATA
+ DDRSS1_PHY_48_DATA
+ DDRSS1_PHY_49_DATA
+ DDRSS1_PHY_50_DATA
+ DDRSS1_PHY_51_DATA
+ DDRSS1_PHY_52_DATA
+ DDRSS1_PHY_53_DATA
+ DDRSS1_PHY_54_DATA
+ DDRSS1_PHY_55_DATA
+ DDRSS1_PHY_56_DATA
+ DDRSS1_PHY_57_DATA
+ DDRSS1_PHY_58_DATA
+ DDRSS1_PHY_59_DATA
+ DDRSS1_PHY_60_DATA
+ DDRSS1_PHY_61_DATA
+ DDRSS1_PHY_62_DATA
+ DDRSS1_PHY_63_DATA
+ DDRSS1_PHY_64_DATA
+ DDRSS1_PHY_65_DATA
+ DDRSS1_PHY_66_DATA
+ DDRSS1_PHY_67_DATA
+ DDRSS1_PHY_68_DATA
+ DDRSS1_PHY_69_DATA
+ DDRSS1_PHY_70_DATA
+ DDRSS1_PHY_71_DATA
+ DDRSS1_PHY_72_DATA
+ DDRSS1_PHY_73_DATA
+ DDRSS1_PHY_74_DATA
+ DDRSS1_PHY_75_DATA
+ DDRSS1_PHY_76_DATA
+ DDRSS1_PHY_77_DATA
+ DDRSS1_PHY_78_DATA
+ DDRSS1_PHY_79_DATA
+ DDRSS1_PHY_80_DATA
+ DDRSS1_PHY_81_DATA
+ DDRSS1_PHY_82_DATA
+ DDRSS1_PHY_83_DATA
+ DDRSS1_PHY_84_DATA
+ DDRSS1_PHY_85_DATA
+ DDRSS1_PHY_86_DATA
+ DDRSS1_PHY_87_DATA
+ DDRSS1_PHY_88_DATA
+ DDRSS1_PHY_89_DATA
+ DDRSS1_PHY_90_DATA
+ DDRSS1_PHY_91_DATA
+ DDRSS1_PHY_92_DATA
+ DDRSS1_PHY_93_DATA
+ DDRSS1_PHY_94_DATA
+ DDRSS1_PHY_95_DATA
+ DDRSS1_PHY_96_DATA
+ DDRSS1_PHY_97_DATA
+ DDRSS1_PHY_98_DATA
+ DDRSS1_PHY_99_DATA
+ DDRSS1_PHY_100_DATA
+ DDRSS1_PHY_101_DATA
+ DDRSS1_PHY_102_DATA
+ DDRSS1_PHY_103_DATA
+ DDRSS1_PHY_104_DATA
+ DDRSS1_PHY_105_DATA
+ DDRSS1_PHY_106_DATA
+ DDRSS1_PHY_107_DATA
+ DDRSS1_PHY_108_DATA
+ DDRSS1_PHY_109_DATA
+ DDRSS1_PHY_110_DATA
+ DDRSS1_PHY_111_DATA
+ DDRSS1_PHY_112_DATA
+ DDRSS1_PHY_113_DATA
+ DDRSS1_PHY_114_DATA
+ DDRSS1_PHY_115_DATA
+ DDRSS1_PHY_116_DATA
+ DDRSS1_PHY_117_DATA
+ DDRSS1_PHY_118_DATA
+ DDRSS1_PHY_119_DATA
+ DDRSS1_PHY_120_DATA
+ DDRSS1_PHY_121_DATA
+ DDRSS1_PHY_122_DATA
+ DDRSS1_PHY_123_DATA
+ DDRSS1_PHY_124_DATA
+ DDRSS1_PHY_125_DATA
+ DDRSS1_PHY_126_DATA
+ DDRSS1_PHY_127_DATA
+ DDRSS1_PHY_128_DATA
+ DDRSS1_PHY_129_DATA
+ DDRSS1_PHY_130_DATA
+ DDRSS1_PHY_131_DATA
+ DDRSS1_PHY_132_DATA
+ DDRSS1_PHY_133_DATA
+ DDRSS1_PHY_134_DATA
+ DDRSS1_PHY_135_DATA
+ DDRSS1_PHY_136_DATA
+ DDRSS1_PHY_137_DATA
+ DDRSS1_PHY_138_DATA
+ DDRSS1_PHY_139_DATA
+ DDRSS1_PHY_140_DATA
+ DDRSS1_PHY_141_DATA
+ DDRSS1_PHY_142_DATA
+ DDRSS1_PHY_143_DATA
+ DDRSS1_PHY_144_DATA
+ DDRSS1_PHY_145_DATA
+ DDRSS1_PHY_146_DATA
+ DDRSS1_PHY_147_DATA
+ DDRSS1_PHY_148_DATA
+ DDRSS1_PHY_149_DATA
+ DDRSS1_PHY_150_DATA
+ DDRSS1_PHY_151_DATA
+ DDRSS1_PHY_152_DATA
+ DDRSS1_PHY_153_DATA
+ DDRSS1_PHY_154_DATA
+ DDRSS1_PHY_155_DATA
+ DDRSS1_PHY_156_DATA
+ DDRSS1_PHY_157_DATA
+ DDRSS1_PHY_158_DATA
+ DDRSS1_PHY_159_DATA
+ DDRSS1_PHY_160_DATA
+ DDRSS1_PHY_161_DATA
+ DDRSS1_PHY_162_DATA
+ DDRSS1_PHY_163_DATA
+ DDRSS1_PHY_164_DATA
+ DDRSS1_PHY_165_DATA
+ DDRSS1_PHY_166_DATA
+ DDRSS1_PHY_167_DATA
+ DDRSS1_PHY_168_DATA
+ DDRSS1_PHY_169_DATA
+ DDRSS1_PHY_170_DATA
+ DDRSS1_PHY_171_DATA
+ DDRSS1_PHY_172_DATA
+ DDRSS1_PHY_173_DATA
+ DDRSS1_PHY_174_DATA
+ DDRSS1_PHY_175_DATA
+ DDRSS1_PHY_176_DATA
+ DDRSS1_PHY_177_DATA
+ DDRSS1_PHY_178_DATA
+ DDRSS1_PHY_179_DATA
+ DDRSS1_PHY_180_DATA
+ DDRSS1_PHY_181_DATA
+ DDRSS1_PHY_182_DATA
+ DDRSS1_PHY_183_DATA
+ DDRSS1_PHY_184_DATA
+ DDRSS1_PHY_185_DATA
+ DDRSS1_PHY_186_DATA
+ DDRSS1_PHY_187_DATA
+ DDRSS1_PHY_188_DATA
+ DDRSS1_PHY_189_DATA
+ DDRSS1_PHY_190_DATA
+ DDRSS1_PHY_191_DATA
+ DDRSS1_PHY_192_DATA
+ DDRSS1_PHY_193_DATA
+ DDRSS1_PHY_194_DATA
+ DDRSS1_PHY_195_DATA
+ DDRSS1_PHY_196_DATA
+ DDRSS1_PHY_197_DATA
+ DDRSS1_PHY_198_DATA
+ DDRSS1_PHY_199_DATA
+ DDRSS1_PHY_200_DATA
+ DDRSS1_PHY_201_DATA
+ DDRSS1_PHY_202_DATA
+ DDRSS1_PHY_203_DATA
+ DDRSS1_PHY_204_DATA
+ DDRSS1_PHY_205_DATA
+ DDRSS1_PHY_206_DATA
+ DDRSS1_PHY_207_DATA
+ DDRSS1_PHY_208_DATA
+ DDRSS1_PHY_209_DATA
+ DDRSS1_PHY_210_DATA
+ DDRSS1_PHY_211_DATA
+ DDRSS1_PHY_212_DATA
+ DDRSS1_PHY_213_DATA
+ DDRSS1_PHY_214_DATA
+ DDRSS1_PHY_215_DATA
+ DDRSS1_PHY_216_DATA
+ DDRSS1_PHY_217_DATA
+ DDRSS1_PHY_218_DATA
+ DDRSS1_PHY_219_DATA
+ DDRSS1_PHY_220_DATA
+ DDRSS1_PHY_221_DATA
+ DDRSS1_PHY_222_DATA
+ DDRSS1_PHY_223_DATA
+ DDRSS1_PHY_224_DATA
+ DDRSS1_PHY_225_DATA
+ DDRSS1_PHY_226_DATA
+ DDRSS1_PHY_227_DATA
+ DDRSS1_PHY_228_DATA
+ DDRSS1_PHY_229_DATA
+ DDRSS1_PHY_230_DATA
+ DDRSS1_PHY_231_DATA
+ DDRSS1_PHY_232_DATA
+ DDRSS1_PHY_233_DATA
+ DDRSS1_PHY_234_DATA
+ DDRSS1_PHY_235_DATA
+ DDRSS1_PHY_236_DATA
+ DDRSS1_PHY_237_DATA
+ DDRSS1_PHY_238_DATA
+ DDRSS1_PHY_239_DATA
+ DDRSS1_PHY_240_DATA
+ DDRSS1_PHY_241_DATA
+ DDRSS1_PHY_242_DATA
+ DDRSS1_PHY_243_DATA
+ DDRSS1_PHY_244_DATA
+ DDRSS1_PHY_245_DATA
+ DDRSS1_PHY_246_DATA
+ DDRSS1_PHY_247_DATA
+ DDRSS1_PHY_248_DATA
+ DDRSS1_PHY_249_DATA
+ DDRSS1_PHY_250_DATA
+ DDRSS1_PHY_251_DATA
+ DDRSS1_PHY_252_DATA
+ DDRSS1_PHY_253_DATA
+ DDRSS1_PHY_254_DATA
+ DDRSS1_PHY_255_DATA
+ DDRSS1_PHY_256_DATA
+ DDRSS1_PHY_257_DATA
+ DDRSS1_PHY_258_DATA
+ DDRSS1_PHY_259_DATA
+ DDRSS1_PHY_260_DATA
+ DDRSS1_PHY_261_DATA
+ DDRSS1_PHY_262_DATA
+ DDRSS1_PHY_263_DATA
+ DDRSS1_PHY_264_DATA
+ DDRSS1_PHY_265_DATA
+ DDRSS1_PHY_266_DATA
+ DDRSS1_PHY_267_DATA
+ DDRSS1_PHY_268_DATA
+ DDRSS1_PHY_269_DATA
+ DDRSS1_PHY_270_DATA
+ DDRSS1_PHY_271_DATA
+ DDRSS1_PHY_272_DATA
+ DDRSS1_PHY_273_DATA
+ DDRSS1_PHY_274_DATA
+ DDRSS1_PHY_275_DATA
+ DDRSS1_PHY_276_DATA
+ DDRSS1_PHY_277_DATA
+ DDRSS1_PHY_278_DATA
+ DDRSS1_PHY_279_DATA
+ DDRSS1_PHY_280_DATA
+ DDRSS1_PHY_281_DATA
+ DDRSS1_PHY_282_DATA
+ DDRSS1_PHY_283_DATA
+ DDRSS1_PHY_284_DATA
+ DDRSS1_PHY_285_DATA
+ DDRSS1_PHY_286_DATA
+ DDRSS1_PHY_287_DATA
+ DDRSS1_PHY_288_DATA
+ DDRSS1_PHY_289_DATA
+ DDRSS1_PHY_290_DATA
+ DDRSS1_PHY_291_DATA
+ DDRSS1_PHY_292_DATA
+ DDRSS1_PHY_293_DATA
+ DDRSS1_PHY_294_DATA
+ DDRSS1_PHY_295_DATA
+ DDRSS1_PHY_296_DATA
+ DDRSS1_PHY_297_DATA
+ DDRSS1_PHY_298_DATA
+ DDRSS1_PHY_299_DATA
+ DDRSS1_PHY_300_DATA
+ DDRSS1_PHY_301_DATA
+ DDRSS1_PHY_302_DATA
+ DDRSS1_PHY_303_DATA
+ DDRSS1_PHY_304_DATA
+ DDRSS1_PHY_305_DATA
+ DDRSS1_PHY_306_DATA
+ DDRSS1_PHY_307_DATA
+ DDRSS1_PHY_308_DATA
+ DDRSS1_PHY_309_DATA
+ DDRSS1_PHY_310_DATA
+ DDRSS1_PHY_311_DATA
+ DDRSS1_PHY_312_DATA
+ DDRSS1_PHY_313_DATA
+ DDRSS1_PHY_314_DATA
+ DDRSS1_PHY_315_DATA
+ DDRSS1_PHY_316_DATA
+ DDRSS1_PHY_317_DATA
+ DDRSS1_PHY_318_DATA
+ DDRSS1_PHY_319_DATA
+ DDRSS1_PHY_320_DATA
+ DDRSS1_PHY_321_DATA
+ DDRSS1_PHY_322_DATA
+ DDRSS1_PHY_323_DATA
+ DDRSS1_PHY_324_DATA
+ DDRSS1_PHY_325_DATA
+ DDRSS1_PHY_326_DATA
+ DDRSS1_PHY_327_DATA
+ DDRSS1_PHY_328_DATA
+ DDRSS1_PHY_329_DATA
+ DDRSS1_PHY_330_DATA
+ DDRSS1_PHY_331_DATA
+ DDRSS1_PHY_332_DATA
+ DDRSS1_PHY_333_DATA
+ DDRSS1_PHY_334_DATA
+ DDRSS1_PHY_335_DATA
+ DDRSS1_PHY_336_DATA
+ DDRSS1_PHY_337_DATA
+ DDRSS1_PHY_338_DATA
+ DDRSS1_PHY_339_DATA
+ DDRSS1_PHY_340_DATA
+ DDRSS1_PHY_341_DATA
+ DDRSS1_PHY_342_DATA
+ DDRSS1_PHY_343_DATA
+ DDRSS1_PHY_344_DATA
+ DDRSS1_PHY_345_DATA
+ DDRSS1_PHY_346_DATA
+ DDRSS1_PHY_347_DATA
+ DDRSS1_PHY_348_DATA
+ DDRSS1_PHY_349_DATA
+ DDRSS1_PHY_350_DATA
+ DDRSS1_PHY_351_DATA
+ DDRSS1_PHY_352_DATA
+ DDRSS1_PHY_353_DATA
+ DDRSS1_PHY_354_DATA
+ DDRSS1_PHY_355_DATA
+ DDRSS1_PHY_356_DATA
+ DDRSS1_PHY_357_DATA
+ DDRSS1_PHY_358_DATA
+ DDRSS1_PHY_359_DATA
+ DDRSS1_PHY_360_DATA
+ DDRSS1_PHY_361_DATA
+ DDRSS1_PHY_362_DATA
+ DDRSS1_PHY_363_DATA
+ DDRSS1_PHY_364_DATA
+ DDRSS1_PHY_365_DATA
+ DDRSS1_PHY_366_DATA
+ DDRSS1_PHY_367_DATA
+ DDRSS1_PHY_368_DATA
+ DDRSS1_PHY_369_DATA
+ DDRSS1_PHY_370_DATA
+ DDRSS1_PHY_371_DATA
+ DDRSS1_PHY_372_DATA
+ DDRSS1_PHY_373_DATA
+ DDRSS1_PHY_374_DATA
+ DDRSS1_PHY_375_DATA
+ DDRSS1_PHY_376_DATA
+ DDRSS1_PHY_377_DATA
+ DDRSS1_PHY_378_DATA
+ DDRSS1_PHY_379_DATA
+ DDRSS1_PHY_380_DATA
+ DDRSS1_PHY_381_DATA
+ DDRSS1_PHY_382_DATA
+ DDRSS1_PHY_383_DATA
+ DDRSS1_PHY_384_DATA
+ DDRSS1_PHY_385_DATA
+ DDRSS1_PHY_386_DATA
+ DDRSS1_PHY_387_DATA
+ DDRSS1_PHY_388_DATA
+ DDRSS1_PHY_389_DATA
+ DDRSS1_PHY_390_DATA
+ DDRSS1_PHY_391_DATA
+ DDRSS1_PHY_392_DATA
+ DDRSS1_PHY_393_DATA
+ DDRSS1_PHY_394_DATA
+ DDRSS1_PHY_395_DATA
+ DDRSS1_PHY_396_DATA
+ DDRSS1_PHY_397_DATA
+ DDRSS1_PHY_398_DATA
+ DDRSS1_PHY_399_DATA
+ DDRSS1_PHY_400_DATA
+ DDRSS1_PHY_401_DATA
+ DDRSS1_PHY_402_DATA
+ DDRSS1_PHY_403_DATA
+ DDRSS1_PHY_404_DATA
+ DDRSS1_PHY_405_DATA
+ DDRSS1_PHY_406_DATA
+ DDRSS1_PHY_407_DATA
+ DDRSS1_PHY_408_DATA
+ DDRSS1_PHY_409_DATA
+ DDRSS1_PHY_410_DATA
+ DDRSS1_PHY_411_DATA
+ DDRSS1_PHY_412_DATA
+ DDRSS1_PHY_413_DATA
+ DDRSS1_PHY_414_DATA
+ DDRSS1_PHY_415_DATA
+ DDRSS1_PHY_416_DATA
+ DDRSS1_PHY_417_DATA
+ DDRSS1_PHY_418_DATA
+ DDRSS1_PHY_419_DATA
+ DDRSS1_PHY_420_DATA
+ DDRSS1_PHY_421_DATA
+ DDRSS1_PHY_422_DATA
+ DDRSS1_PHY_423_DATA
+ DDRSS1_PHY_424_DATA
+ DDRSS1_PHY_425_DATA
+ DDRSS1_PHY_426_DATA
+ DDRSS1_PHY_427_DATA
+ DDRSS1_PHY_428_DATA
+ DDRSS1_PHY_429_DATA
+ DDRSS1_PHY_430_DATA
+ DDRSS1_PHY_431_DATA
+ DDRSS1_PHY_432_DATA
+ DDRSS1_PHY_433_DATA
+ DDRSS1_PHY_434_DATA
+ DDRSS1_PHY_435_DATA
+ DDRSS1_PHY_436_DATA
+ DDRSS1_PHY_437_DATA
+ DDRSS1_PHY_438_DATA
+ DDRSS1_PHY_439_DATA
+ DDRSS1_PHY_440_DATA
+ DDRSS1_PHY_441_DATA
+ DDRSS1_PHY_442_DATA
+ DDRSS1_PHY_443_DATA
+ DDRSS1_PHY_444_DATA
+ DDRSS1_PHY_445_DATA
+ DDRSS1_PHY_446_DATA
+ DDRSS1_PHY_447_DATA
+ DDRSS1_PHY_448_DATA
+ DDRSS1_PHY_449_DATA
+ DDRSS1_PHY_450_DATA
+ DDRSS1_PHY_451_DATA
+ DDRSS1_PHY_452_DATA
+ DDRSS1_PHY_453_DATA
+ DDRSS1_PHY_454_DATA
+ DDRSS1_PHY_455_DATA
+ DDRSS1_PHY_456_DATA
+ DDRSS1_PHY_457_DATA
+ DDRSS1_PHY_458_DATA
+ DDRSS1_PHY_459_DATA
+ DDRSS1_PHY_460_DATA
+ DDRSS1_PHY_461_DATA
+ DDRSS1_PHY_462_DATA
+ DDRSS1_PHY_463_DATA
+ DDRSS1_PHY_464_DATA
+ DDRSS1_PHY_465_DATA
+ DDRSS1_PHY_466_DATA
+ DDRSS1_PHY_467_DATA
+ DDRSS1_PHY_468_DATA
+ DDRSS1_PHY_469_DATA
+ DDRSS1_PHY_470_DATA
+ DDRSS1_PHY_471_DATA
+ DDRSS1_PHY_472_DATA
+ DDRSS1_PHY_473_DATA
+ DDRSS1_PHY_474_DATA
+ DDRSS1_PHY_475_DATA
+ DDRSS1_PHY_476_DATA
+ DDRSS1_PHY_477_DATA
+ DDRSS1_PHY_478_DATA
+ DDRSS1_PHY_479_DATA
+ DDRSS1_PHY_480_DATA
+ DDRSS1_PHY_481_DATA
+ DDRSS1_PHY_482_DATA
+ DDRSS1_PHY_483_DATA
+ DDRSS1_PHY_484_DATA
+ DDRSS1_PHY_485_DATA
+ DDRSS1_PHY_486_DATA
+ DDRSS1_PHY_487_DATA
+ DDRSS1_PHY_488_DATA
+ DDRSS1_PHY_489_DATA
+ DDRSS1_PHY_490_DATA
+ DDRSS1_PHY_491_DATA
+ DDRSS1_PHY_492_DATA
+ DDRSS1_PHY_493_DATA
+ DDRSS1_PHY_494_DATA
+ DDRSS1_PHY_495_DATA
+ DDRSS1_PHY_496_DATA
+ DDRSS1_PHY_497_DATA
+ DDRSS1_PHY_498_DATA
+ DDRSS1_PHY_499_DATA
+ DDRSS1_PHY_500_DATA
+ DDRSS1_PHY_501_DATA
+ DDRSS1_PHY_502_DATA
+ DDRSS1_PHY_503_DATA
+ DDRSS1_PHY_504_DATA
+ DDRSS1_PHY_505_DATA
+ DDRSS1_PHY_506_DATA
+ DDRSS1_PHY_507_DATA
+ DDRSS1_PHY_508_DATA
+ DDRSS1_PHY_509_DATA
+ DDRSS1_PHY_510_DATA
+ DDRSS1_PHY_511_DATA
+ DDRSS1_PHY_512_DATA
+ DDRSS1_PHY_513_DATA
+ DDRSS1_PHY_514_DATA
+ DDRSS1_PHY_515_DATA
+ DDRSS1_PHY_516_DATA
+ DDRSS1_PHY_517_DATA
+ DDRSS1_PHY_518_DATA
+ DDRSS1_PHY_519_DATA
+ DDRSS1_PHY_520_DATA
+ DDRSS1_PHY_521_DATA
+ DDRSS1_PHY_522_DATA
+ DDRSS1_PHY_523_DATA
+ DDRSS1_PHY_524_DATA
+ DDRSS1_PHY_525_DATA
+ DDRSS1_PHY_526_DATA
+ DDRSS1_PHY_527_DATA
+ DDRSS1_PHY_528_DATA
+ DDRSS1_PHY_529_DATA
+ DDRSS1_PHY_530_DATA
+ DDRSS1_PHY_531_DATA
+ DDRSS1_PHY_532_DATA
+ DDRSS1_PHY_533_DATA
+ DDRSS1_PHY_534_DATA
+ DDRSS1_PHY_535_DATA
+ DDRSS1_PHY_536_DATA
+ DDRSS1_PHY_537_DATA
+ DDRSS1_PHY_538_DATA
+ DDRSS1_PHY_539_DATA
+ DDRSS1_PHY_540_DATA
+ DDRSS1_PHY_541_DATA
+ DDRSS1_PHY_542_DATA
+ DDRSS1_PHY_543_DATA
+ DDRSS1_PHY_544_DATA
+ DDRSS1_PHY_545_DATA
+ DDRSS1_PHY_546_DATA
+ DDRSS1_PHY_547_DATA
+ DDRSS1_PHY_548_DATA
+ DDRSS1_PHY_549_DATA
+ DDRSS1_PHY_550_DATA
+ DDRSS1_PHY_551_DATA
+ DDRSS1_PHY_552_DATA
+ DDRSS1_PHY_553_DATA
+ DDRSS1_PHY_554_DATA
+ DDRSS1_PHY_555_DATA
+ DDRSS1_PHY_556_DATA
+ DDRSS1_PHY_557_DATA
+ DDRSS1_PHY_558_DATA
+ DDRSS1_PHY_559_DATA
+ DDRSS1_PHY_560_DATA
+ DDRSS1_PHY_561_DATA
+ DDRSS1_PHY_562_DATA
+ DDRSS1_PHY_563_DATA
+ DDRSS1_PHY_564_DATA
+ DDRSS1_PHY_565_DATA
+ DDRSS1_PHY_566_DATA
+ DDRSS1_PHY_567_DATA
+ DDRSS1_PHY_568_DATA
+ DDRSS1_PHY_569_DATA
+ DDRSS1_PHY_570_DATA
+ DDRSS1_PHY_571_DATA
+ DDRSS1_PHY_572_DATA
+ DDRSS1_PHY_573_DATA
+ DDRSS1_PHY_574_DATA
+ DDRSS1_PHY_575_DATA
+ DDRSS1_PHY_576_DATA
+ DDRSS1_PHY_577_DATA
+ DDRSS1_PHY_578_DATA
+ DDRSS1_PHY_579_DATA
+ DDRSS1_PHY_580_DATA
+ DDRSS1_PHY_581_DATA
+ DDRSS1_PHY_582_DATA
+ DDRSS1_PHY_583_DATA
+ DDRSS1_PHY_584_DATA
+ DDRSS1_PHY_585_DATA
+ DDRSS1_PHY_586_DATA
+ DDRSS1_PHY_587_DATA
+ DDRSS1_PHY_588_DATA
+ DDRSS1_PHY_589_DATA
+ DDRSS1_PHY_590_DATA
+ DDRSS1_PHY_591_DATA
+ DDRSS1_PHY_592_DATA
+ DDRSS1_PHY_593_DATA
+ DDRSS1_PHY_594_DATA
+ DDRSS1_PHY_595_DATA
+ DDRSS1_PHY_596_DATA
+ DDRSS1_PHY_597_DATA
+ DDRSS1_PHY_598_DATA
+ DDRSS1_PHY_599_DATA
+ DDRSS1_PHY_600_DATA
+ DDRSS1_PHY_601_DATA
+ DDRSS1_PHY_602_DATA
+ DDRSS1_PHY_603_DATA
+ DDRSS1_PHY_604_DATA
+ DDRSS1_PHY_605_DATA
+ DDRSS1_PHY_606_DATA
+ DDRSS1_PHY_607_DATA
+ DDRSS1_PHY_608_DATA
+ DDRSS1_PHY_609_DATA
+ DDRSS1_PHY_610_DATA
+ DDRSS1_PHY_611_DATA
+ DDRSS1_PHY_612_DATA
+ DDRSS1_PHY_613_DATA
+ DDRSS1_PHY_614_DATA
+ DDRSS1_PHY_615_DATA
+ DDRSS1_PHY_616_DATA
+ DDRSS1_PHY_617_DATA
+ DDRSS1_PHY_618_DATA
+ DDRSS1_PHY_619_DATA
+ DDRSS1_PHY_620_DATA
+ DDRSS1_PHY_621_DATA
+ DDRSS1_PHY_622_DATA
+ DDRSS1_PHY_623_DATA
+ DDRSS1_PHY_624_DATA
+ DDRSS1_PHY_625_DATA
+ DDRSS1_PHY_626_DATA
+ DDRSS1_PHY_627_DATA
+ DDRSS1_PHY_628_DATA
+ DDRSS1_PHY_629_DATA
+ DDRSS1_PHY_630_DATA
+ DDRSS1_PHY_631_DATA
+ DDRSS1_PHY_632_DATA
+ DDRSS1_PHY_633_DATA
+ DDRSS1_PHY_634_DATA
+ DDRSS1_PHY_635_DATA
+ DDRSS1_PHY_636_DATA
+ DDRSS1_PHY_637_DATA
+ DDRSS1_PHY_638_DATA
+ DDRSS1_PHY_639_DATA
+ DDRSS1_PHY_640_DATA
+ DDRSS1_PHY_641_DATA
+ DDRSS1_PHY_642_DATA
+ DDRSS1_PHY_643_DATA
+ DDRSS1_PHY_644_DATA
+ DDRSS1_PHY_645_DATA
+ DDRSS1_PHY_646_DATA
+ DDRSS1_PHY_647_DATA
+ DDRSS1_PHY_648_DATA
+ DDRSS1_PHY_649_DATA
+ DDRSS1_PHY_650_DATA
+ DDRSS1_PHY_651_DATA
+ DDRSS1_PHY_652_DATA
+ DDRSS1_PHY_653_DATA
+ DDRSS1_PHY_654_DATA
+ DDRSS1_PHY_655_DATA
+ DDRSS1_PHY_656_DATA
+ DDRSS1_PHY_657_DATA
+ DDRSS1_PHY_658_DATA
+ DDRSS1_PHY_659_DATA
+ DDRSS1_PHY_660_DATA
+ DDRSS1_PHY_661_DATA
+ DDRSS1_PHY_662_DATA
+ DDRSS1_PHY_663_DATA
+ DDRSS1_PHY_664_DATA
+ DDRSS1_PHY_665_DATA
+ DDRSS1_PHY_666_DATA
+ DDRSS1_PHY_667_DATA
+ DDRSS1_PHY_668_DATA
+ DDRSS1_PHY_669_DATA
+ DDRSS1_PHY_670_DATA
+ DDRSS1_PHY_671_DATA
+ DDRSS1_PHY_672_DATA
+ DDRSS1_PHY_673_DATA
+ DDRSS1_PHY_674_DATA
+ DDRSS1_PHY_675_DATA
+ DDRSS1_PHY_676_DATA
+ DDRSS1_PHY_677_DATA
+ DDRSS1_PHY_678_DATA
+ DDRSS1_PHY_679_DATA
+ DDRSS1_PHY_680_DATA
+ DDRSS1_PHY_681_DATA
+ DDRSS1_PHY_682_DATA
+ DDRSS1_PHY_683_DATA
+ DDRSS1_PHY_684_DATA
+ DDRSS1_PHY_685_DATA
+ DDRSS1_PHY_686_DATA
+ DDRSS1_PHY_687_DATA
+ DDRSS1_PHY_688_DATA
+ DDRSS1_PHY_689_DATA
+ DDRSS1_PHY_690_DATA
+ DDRSS1_PHY_691_DATA
+ DDRSS1_PHY_692_DATA
+ DDRSS1_PHY_693_DATA
+ DDRSS1_PHY_694_DATA
+ DDRSS1_PHY_695_DATA
+ DDRSS1_PHY_696_DATA
+ DDRSS1_PHY_697_DATA
+ DDRSS1_PHY_698_DATA
+ DDRSS1_PHY_699_DATA
+ DDRSS1_PHY_700_DATA
+ DDRSS1_PHY_701_DATA
+ DDRSS1_PHY_702_DATA
+ DDRSS1_PHY_703_DATA
+ DDRSS1_PHY_704_DATA
+ DDRSS1_PHY_705_DATA
+ DDRSS1_PHY_706_DATA
+ DDRSS1_PHY_707_DATA
+ DDRSS1_PHY_708_DATA
+ DDRSS1_PHY_709_DATA
+ DDRSS1_PHY_710_DATA
+ DDRSS1_PHY_711_DATA
+ DDRSS1_PHY_712_DATA
+ DDRSS1_PHY_713_DATA
+ DDRSS1_PHY_714_DATA
+ DDRSS1_PHY_715_DATA
+ DDRSS1_PHY_716_DATA
+ DDRSS1_PHY_717_DATA
+ DDRSS1_PHY_718_DATA
+ DDRSS1_PHY_719_DATA
+ DDRSS1_PHY_720_DATA
+ DDRSS1_PHY_721_DATA
+ DDRSS1_PHY_722_DATA
+ DDRSS1_PHY_723_DATA
+ DDRSS1_PHY_724_DATA
+ DDRSS1_PHY_725_DATA
+ DDRSS1_PHY_726_DATA
+ DDRSS1_PHY_727_DATA
+ DDRSS1_PHY_728_DATA
+ DDRSS1_PHY_729_DATA
+ DDRSS1_PHY_730_DATA
+ DDRSS1_PHY_731_DATA
+ DDRSS1_PHY_732_DATA
+ DDRSS1_PHY_733_DATA
+ DDRSS1_PHY_734_DATA
+ DDRSS1_PHY_735_DATA
+ DDRSS1_PHY_736_DATA
+ DDRSS1_PHY_737_DATA
+ DDRSS1_PHY_738_DATA
+ DDRSS1_PHY_739_DATA
+ DDRSS1_PHY_740_DATA
+ DDRSS1_PHY_741_DATA
+ DDRSS1_PHY_742_DATA
+ DDRSS1_PHY_743_DATA
+ DDRSS1_PHY_744_DATA
+ DDRSS1_PHY_745_DATA
+ DDRSS1_PHY_746_DATA
+ DDRSS1_PHY_747_DATA
+ DDRSS1_PHY_748_DATA
+ DDRSS1_PHY_749_DATA
+ DDRSS1_PHY_750_DATA
+ DDRSS1_PHY_751_DATA
+ DDRSS1_PHY_752_DATA
+ DDRSS1_PHY_753_DATA
+ DDRSS1_PHY_754_DATA
+ DDRSS1_PHY_755_DATA
+ DDRSS1_PHY_756_DATA
+ DDRSS1_PHY_757_DATA
+ DDRSS1_PHY_758_DATA
+ DDRSS1_PHY_759_DATA
+ DDRSS1_PHY_760_DATA
+ DDRSS1_PHY_761_DATA
+ DDRSS1_PHY_762_DATA
+ DDRSS1_PHY_763_DATA
+ DDRSS1_PHY_764_DATA
+ DDRSS1_PHY_765_DATA
+ DDRSS1_PHY_766_DATA
+ DDRSS1_PHY_767_DATA
+ DDRSS1_PHY_768_DATA
+ DDRSS1_PHY_769_DATA
+ DDRSS1_PHY_770_DATA
+ DDRSS1_PHY_771_DATA
+ DDRSS1_PHY_772_DATA
+ DDRSS1_PHY_773_DATA
+ DDRSS1_PHY_774_DATA
+ DDRSS1_PHY_775_DATA
+ DDRSS1_PHY_776_DATA
+ DDRSS1_PHY_777_DATA
+ DDRSS1_PHY_778_DATA
+ DDRSS1_PHY_779_DATA
+ DDRSS1_PHY_780_DATA
+ DDRSS1_PHY_781_DATA
+ DDRSS1_PHY_782_DATA
+ DDRSS1_PHY_783_DATA
+ DDRSS1_PHY_784_DATA
+ DDRSS1_PHY_785_DATA
+ DDRSS1_PHY_786_DATA
+ DDRSS1_PHY_787_DATA
+ DDRSS1_PHY_788_DATA
+ DDRSS1_PHY_789_DATA
+ DDRSS1_PHY_790_DATA
+ DDRSS1_PHY_791_DATA
+ DDRSS1_PHY_792_DATA
+ DDRSS1_PHY_793_DATA
+ DDRSS1_PHY_794_DATA
+ DDRSS1_PHY_795_DATA
+ DDRSS1_PHY_796_DATA
+ DDRSS1_PHY_797_DATA
+ DDRSS1_PHY_798_DATA
+ DDRSS1_PHY_799_DATA
+ DDRSS1_PHY_800_DATA
+ DDRSS1_PHY_801_DATA
+ DDRSS1_PHY_802_DATA
+ DDRSS1_PHY_803_DATA
+ DDRSS1_PHY_804_DATA
+ DDRSS1_PHY_805_DATA
+ DDRSS1_PHY_806_DATA
+ DDRSS1_PHY_807_DATA
+ DDRSS1_PHY_808_DATA
+ DDRSS1_PHY_809_DATA
+ DDRSS1_PHY_810_DATA
+ DDRSS1_PHY_811_DATA
+ DDRSS1_PHY_812_DATA
+ DDRSS1_PHY_813_DATA
+ DDRSS1_PHY_814_DATA
+ DDRSS1_PHY_815_DATA
+ DDRSS1_PHY_816_DATA
+ DDRSS1_PHY_817_DATA
+ DDRSS1_PHY_818_DATA
+ DDRSS1_PHY_819_DATA
+ DDRSS1_PHY_820_DATA
+ DDRSS1_PHY_821_DATA
+ DDRSS1_PHY_822_DATA
+ DDRSS1_PHY_823_DATA
+ DDRSS1_PHY_824_DATA
+ DDRSS1_PHY_825_DATA
+ DDRSS1_PHY_826_DATA
+ DDRSS1_PHY_827_DATA
+ DDRSS1_PHY_828_DATA
+ DDRSS1_PHY_829_DATA
+ DDRSS1_PHY_830_DATA
+ DDRSS1_PHY_831_DATA
+ DDRSS1_PHY_832_DATA
+ DDRSS1_PHY_833_DATA
+ DDRSS1_PHY_834_DATA
+ DDRSS1_PHY_835_DATA
+ DDRSS1_PHY_836_DATA
+ DDRSS1_PHY_837_DATA
+ DDRSS1_PHY_838_DATA
+ DDRSS1_PHY_839_DATA
+ DDRSS1_PHY_840_DATA
+ DDRSS1_PHY_841_DATA
+ DDRSS1_PHY_842_DATA
+ DDRSS1_PHY_843_DATA
+ DDRSS1_PHY_844_DATA
+ DDRSS1_PHY_845_DATA
+ DDRSS1_PHY_846_DATA
+ DDRSS1_PHY_847_DATA
+ DDRSS1_PHY_848_DATA
+ DDRSS1_PHY_849_DATA
+ DDRSS1_PHY_850_DATA
+ DDRSS1_PHY_851_DATA
+ DDRSS1_PHY_852_DATA
+ DDRSS1_PHY_853_DATA
+ DDRSS1_PHY_854_DATA
+ DDRSS1_PHY_855_DATA
+ DDRSS1_PHY_856_DATA
+ DDRSS1_PHY_857_DATA
+ DDRSS1_PHY_858_DATA
+ DDRSS1_PHY_859_DATA
+ DDRSS1_PHY_860_DATA
+ DDRSS1_PHY_861_DATA
+ DDRSS1_PHY_862_DATA
+ DDRSS1_PHY_863_DATA
+ DDRSS1_PHY_864_DATA
+ DDRSS1_PHY_865_DATA
+ DDRSS1_PHY_866_DATA
+ DDRSS1_PHY_867_DATA
+ DDRSS1_PHY_868_DATA
+ DDRSS1_PHY_869_DATA
+ DDRSS1_PHY_870_DATA
+ DDRSS1_PHY_871_DATA
+ DDRSS1_PHY_872_DATA
+ DDRSS1_PHY_873_DATA
+ DDRSS1_PHY_874_DATA
+ DDRSS1_PHY_875_DATA
+ DDRSS1_PHY_876_DATA
+ DDRSS1_PHY_877_DATA
+ DDRSS1_PHY_878_DATA
+ DDRSS1_PHY_879_DATA
+ DDRSS1_PHY_880_DATA
+ DDRSS1_PHY_881_DATA
+ DDRSS1_PHY_882_DATA
+ DDRSS1_PHY_883_DATA
+ DDRSS1_PHY_884_DATA
+ DDRSS1_PHY_885_DATA
+ DDRSS1_PHY_886_DATA
+ DDRSS1_PHY_887_DATA
+ DDRSS1_PHY_888_DATA
+ DDRSS1_PHY_889_DATA
+ DDRSS1_PHY_890_DATA
+ DDRSS1_PHY_891_DATA
+ DDRSS1_PHY_892_DATA
+ DDRSS1_PHY_893_DATA
+ DDRSS1_PHY_894_DATA
+ DDRSS1_PHY_895_DATA
+ DDRSS1_PHY_896_DATA
+ DDRSS1_PHY_897_DATA
+ DDRSS1_PHY_898_DATA
+ DDRSS1_PHY_899_DATA
+ DDRSS1_PHY_900_DATA
+ DDRSS1_PHY_901_DATA
+ DDRSS1_PHY_902_DATA
+ DDRSS1_PHY_903_DATA
+ DDRSS1_PHY_904_DATA
+ DDRSS1_PHY_905_DATA
+ DDRSS1_PHY_906_DATA
+ DDRSS1_PHY_907_DATA
+ DDRSS1_PHY_908_DATA
+ DDRSS1_PHY_909_DATA
+ DDRSS1_PHY_910_DATA
+ DDRSS1_PHY_911_DATA
+ DDRSS1_PHY_912_DATA
+ DDRSS1_PHY_913_DATA
+ DDRSS1_PHY_914_DATA
+ DDRSS1_PHY_915_DATA
+ DDRSS1_PHY_916_DATA
+ DDRSS1_PHY_917_DATA
+ DDRSS1_PHY_918_DATA
+ DDRSS1_PHY_919_DATA
+ DDRSS1_PHY_920_DATA
+ DDRSS1_PHY_921_DATA
+ DDRSS1_PHY_922_DATA
+ DDRSS1_PHY_923_DATA
+ DDRSS1_PHY_924_DATA
+ DDRSS1_PHY_925_DATA
+ DDRSS1_PHY_926_DATA
+ DDRSS1_PHY_927_DATA
+ DDRSS1_PHY_928_DATA
+ DDRSS1_PHY_929_DATA
+ DDRSS1_PHY_930_DATA
+ DDRSS1_PHY_931_DATA
+ DDRSS1_PHY_932_DATA
+ DDRSS1_PHY_933_DATA
+ DDRSS1_PHY_934_DATA
+ DDRSS1_PHY_935_DATA
+ DDRSS1_PHY_936_DATA
+ DDRSS1_PHY_937_DATA
+ DDRSS1_PHY_938_DATA
+ DDRSS1_PHY_939_DATA
+ DDRSS1_PHY_940_DATA
+ DDRSS1_PHY_941_DATA
+ DDRSS1_PHY_942_DATA
+ DDRSS1_PHY_943_DATA
+ DDRSS1_PHY_944_DATA
+ DDRSS1_PHY_945_DATA
+ DDRSS1_PHY_946_DATA
+ DDRSS1_PHY_947_DATA
+ DDRSS1_PHY_948_DATA
+ DDRSS1_PHY_949_DATA
+ DDRSS1_PHY_950_DATA
+ DDRSS1_PHY_951_DATA
+ DDRSS1_PHY_952_DATA
+ DDRSS1_PHY_953_DATA
+ DDRSS1_PHY_954_DATA
+ DDRSS1_PHY_955_DATA
+ DDRSS1_PHY_956_DATA
+ DDRSS1_PHY_957_DATA
+ DDRSS1_PHY_958_DATA
+ DDRSS1_PHY_959_DATA
+ DDRSS1_PHY_960_DATA
+ DDRSS1_PHY_961_DATA
+ DDRSS1_PHY_962_DATA
+ DDRSS1_PHY_963_DATA
+ DDRSS1_PHY_964_DATA
+ DDRSS1_PHY_965_DATA
+ DDRSS1_PHY_966_DATA
+ DDRSS1_PHY_967_DATA
+ DDRSS1_PHY_968_DATA
+ DDRSS1_PHY_969_DATA
+ DDRSS1_PHY_970_DATA
+ DDRSS1_PHY_971_DATA
+ DDRSS1_PHY_972_DATA
+ DDRSS1_PHY_973_DATA
+ DDRSS1_PHY_974_DATA
+ DDRSS1_PHY_975_DATA
+ DDRSS1_PHY_976_DATA
+ DDRSS1_PHY_977_DATA
+ DDRSS1_PHY_978_DATA
+ DDRSS1_PHY_979_DATA
+ DDRSS1_PHY_980_DATA
+ DDRSS1_PHY_981_DATA
+ DDRSS1_PHY_982_DATA
+ DDRSS1_PHY_983_DATA
+ DDRSS1_PHY_984_DATA
+ DDRSS1_PHY_985_DATA
+ DDRSS1_PHY_986_DATA
+ DDRSS1_PHY_987_DATA
+ DDRSS1_PHY_988_DATA
+ DDRSS1_PHY_989_DATA
+ DDRSS1_PHY_990_DATA
+ DDRSS1_PHY_991_DATA
+ DDRSS1_PHY_992_DATA
+ DDRSS1_PHY_993_DATA
+ DDRSS1_PHY_994_DATA
+ DDRSS1_PHY_995_DATA
+ DDRSS1_PHY_996_DATA
+ DDRSS1_PHY_997_DATA
+ DDRSS1_PHY_998_DATA
+ DDRSS1_PHY_999_DATA
+ DDRSS1_PHY_1000_DATA
+ DDRSS1_PHY_1001_DATA
+ DDRSS1_PHY_1002_DATA
+ DDRSS1_PHY_1003_DATA
+ DDRSS1_PHY_1004_DATA
+ DDRSS1_PHY_1005_DATA
+ DDRSS1_PHY_1006_DATA
+ DDRSS1_PHY_1007_DATA
+ DDRSS1_PHY_1008_DATA
+ DDRSS1_PHY_1009_DATA
+ DDRSS1_PHY_1010_DATA
+ DDRSS1_PHY_1011_DATA
+ DDRSS1_PHY_1012_DATA
+ DDRSS1_PHY_1013_DATA
+ DDRSS1_PHY_1014_DATA
+ DDRSS1_PHY_1015_DATA
+ DDRSS1_PHY_1016_DATA
+ DDRSS1_PHY_1017_DATA
+ DDRSS1_PHY_1018_DATA
+ DDRSS1_PHY_1019_DATA
+ DDRSS1_PHY_1020_DATA
+ DDRSS1_PHY_1021_DATA
+ DDRSS1_PHY_1022_DATA
+ DDRSS1_PHY_1023_DATA
+ DDRSS1_PHY_1024_DATA
+ DDRSS1_PHY_1025_DATA
+ DDRSS1_PHY_1026_DATA
+ DDRSS1_PHY_1027_DATA
+ DDRSS1_PHY_1028_DATA
+ DDRSS1_PHY_1029_DATA
+ DDRSS1_PHY_1030_DATA
+ DDRSS1_PHY_1031_DATA
+ DDRSS1_PHY_1032_DATA
+ DDRSS1_PHY_1033_DATA
+ DDRSS1_PHY_1034_DATA
+ DDRSS1_PHY_1035_DATA
+ DDRSS1_PHY_1036_DATA
+ DDRSS1_PHY_1037_DATA
+ DDRSS1_PHY_1038_DATA
+ DDRSS1_PHY_1039_DATA
+ DDRSS1_PHY_1040_DATA
+ DDRSS1_PHY_1041_DATA
+ DDRSS1_PHY_1042_DATA
+ DDRSS1_PHY_1043_DATA
+ DDRSS1_PHY_1044_DATA
+ DDRSS1_PHY_1045_DATA
+ DDRSS1_PHY_1046_DATA
+ DDRSS1_PHY_1047_DATA
+ DDRSS1_PHY_1048_DATA
+ DDRSS1_PHY_1049_DATA
+ DDRSS1_PHY_1050_DATA
+ DDRSS1_PHY_1051_DATA
+ DDRSS1_PHY_1052_DATA
+ DDRSS1_PHY_1053_DATA
+ DDRSS1_PHY_1054_DATA
+ DDRSS1_PHY_1055_DATA
+ DDRSS1_PHY_1056_DATA
+ DDRSS1_PHY_1057_DATA
+ DDRSS1_PHY_1058_DATA
+ DDRSS1_PHY_1059_DATA
+ DDRSS1_PHY_1060_DATA
+ DDRSS1_PHY_1061_DATA
+ DDRSS1_PHY_1062_DATA
+ DDRSS1_PHY_1063_DATA
+ DDRSS1_PHY_1064_DATA
+ DDRSS1_PHY_1065_DATA
+ DDRSS1_PHY_1066_DATA
+ DDRSS1_PHY_1067_DATA
+ DDRSS1_PHY_1068_DATA
+ DDRSS1_PHY_1069_DATA
+ DDRSS1_PHY_1070_DATA
+ DDRSS1_PHY_1071_DATA
+ DDRSS1_PHY_1072_DATA
+ DDRSS1_PHY_1073_DATA
+ DDRSS1_PHY_1074_DATA
+ DDRSS1_PHY_1075_DATA
+ DDRSS1_PHY_1076_DATA
+ DDRSS1_PHY_1077_DATA
+ DDRSS1_PHY_1078_DATA
+ DDRSS1_PHY_1079_DATA
+ DDRSS1_PHY_1080_DATA
+ DDRSS1_PHY_1081_DATA
+ DDRSS1_PHY_1082_DATA
+ DDRSS1_PHY_1083_DATA
+ DDRSS1_PHY_1084_DATA
+ DDRSS1_PHY_1085_DATA
+ DDRSS1_PHY_1086_DATA
+ DDRSS1_PHY_1087_DATA
+ DDRSS1_PHY_1088_DATA
+ DDRSS1_PHY_1089_DATA
+ DDRSS1_PHY_1090_DATA
+ DDRSS1_PHY_1091_DATA
+ DDRSS1_PHY_1092_DATA
+ DDRSS1_PHY_1093_DATA
+ DDRSS1_PHY_1094_DATA
+ DDRSS1_PHY_1095_DATA
+ DDRSS1_PHY_1096_DATA
+ DDRSS1_PHY_1097_DATA
+ DDRSS1_PHY_1098_DATA
+ DDRSS1_PHY_1099_DATA
+ DDRSS1_PHY_1100_DATA
+ DDRSS1_PHY_1101_DATA
+ DDRSS1_PHY_1102_DATA
+ DDRSS1_PHY_1103_DATA
+ DDRSS1_PHY_1104_DATA
+ DDRSS1_PHY_1105_DATA
+ DDRSS1_PHY_1106_DATA
+ DDRSS1_PHY_1107_DATA
+ DDRSS1_PHY_1108_DATA
+ DDRSS1_PHY_1109_DATA
+ DDRSS1_PHY_1110_DATA
+ DDRSS1_PHY_1111_DATA
+ DDRSS1_PHY_1112_DATA
+ DDRSS1_PHY_1113_DATA
+ DDRSS1_PHY_1114_DATA
+ DDRSS1_PHY_1115_DATA
+ DDRSS1_PHY_1116_DATA
+ DDRSS1_PHY_1117_DATA
+ DDRSS1_PHY_1118_DATA
+ DDRSS1_PHY_1119_DATA
+ DDRSS1_PHY_1120_DATA
+ DDRSS1_PHY_1121_DATA
+ DDRSS1_PHY_1122_DATA
+ DDRSS1_PHY_1123_DATA
+ DDRSS1_PHY_1124_DATA
+ DDRSS1_PHY_1125_DATA
+ DDRSS1_PHY_1126_DATA
+ DDRSS1_PHY_1127_DATA
+ DDRSS1_PHY_1128_DATA
+ DDRSS1_PHY_1129_DATA
+ DDRSS1_PHY_1130_DATA
+ DDRSS1_PHY_1131_DATA
+ DDRSS1_PHY_1132_DATA
+ DDRSS1_PHY_1133_DATA
+ DDRSS1_PHY_1134_DATA
+ DDRSS1_PHY_1135_DATA
+ DDRSS1_PHY_1136_DATA
+ DDRSS1_PHY_1137_DATA
+ DDRSS1_PHY_1138_DATA
+ DDRSS1_PHY_1139_DATA
+ DDRSS1_PHY_1140_DATA
+ DDRSS1_PHY_1141_DATA
+ DDRSS1_PHY_1142_DATA
+ DDRSS1_PHY_1143_DATA
+ DDRSS1_PHY_1144_DATA
+ DDRSS1_PHY_1145_DATA
+ DDRSS1_PHY_1146_DATA
+ DDRSS1_PHY_1147_DATA
+ DDRSS1_PHY_1148_DATA
+ DDRSS1_PHY_1149_DATA
+ DDRSS1_PHY_1150_DATA
+ DDRSS1_PHY_1151_DATA
+ DDRSS1_PHY_1152_DATA
+ DDRSS1_PHY_1153_DATA
+ DDRSS1_PHY_1154_DATA
+ DDRSS1_PHY_1155_DATA
+ DDRSS1_PHY_1156_DATA
+ DDRSS1_PHY_1157_DATA
+ DDRSS1_PHY_1158_DATA
+ DDRSS1_PHY_1159_DATA
+ DDRSS1_PHY_1160_DATA
+ DDRSS1_PHY_1161_DATA
+ DDRSS1_PHY_1162_DATA
+ DDRSS1_PHY_1163_DATA
+ DDRSS1_PHY_1164_DATA
+ DDRSS1_PHY_1165_DATA
+ DDRSS1_PHY_1166_DATA
+ DDRSS1_PHY_1167_DATA
+ DDRSS1_PHY_1168_DATA
+ DDRSS1_PHY_1169_DATA
+ DDRSS1_PHY_1170_DATA
+ DDRSS1_PHY_1171_DATA
+ DDRSS1_PHY_1172_DATA
+ DDRSS1_PHY_1173_DATA
+ DDRSS1_PHY_1174_DATA
+ DDRSS1_PHY_1175_DATA
+ DDRSS1_PHY_1176_DATA
+ DDRSS1_PHY_1177_DATA
+ DDRSS1_PHY_1178_DATA
+ DDRSS1_PHY_1179_DATA
+ DDRSS1_PHY_1180_DATA
+ DDRSS1_PHY_1181_DATA
+ DDRSS1_PHY_1182_DATA
+ DDRSS1_PHY_1183_DATA
+ DDRSS1_PHY_1184_DATA
+ DDRSS1_PHY_1185_DATA
+ DDRSS1_PHY_1186_DATA
+ DDRSS1_PHY_1187_DATA
+ DDRSS1_PHY_1188_DATA
+ DDRSS1_PHY_1189_DATA
+ DDRSS1_PHY_1190_DATA
+ DDRSS1_PHY_1191_DATA
+ DDRSS1_PHY_1192_DATA
+ DDRSS1_PHY_1193_DATA
+ DDRSS1_PHY_1194_DATA
+ DDRSS1_PHY_1195_DATA
+ DDRSS1_PHY_1196_DATA
+ DDRSS1_PHY_1197_DATA
+ DDRSS1_PHY_1198_DATA
+ DDRSS1_PHY_1199_DATA
+ DDRSS1_PHY_1200_DATA
+ DDRSS1_PHY_1201_DATA
+ DDRSS1_PHY_1202_DATA
+ DDRSS1_PHY_1203_DATA
+ DDRSS1_PHY_1204_DATA
+ DDRSS1_PHY_1205_DATA
+ DDRSS1_PHY_1206_DATA
+ DDRSS1_PHY_1207_DATA
+ DDRSS1_PHY_1208_DATA
+ DDRSS1_PHY_1209_DATA
+ DDRSS1_PHY_1210_DATA
+ DDRSS1_PHY_1211_DATA
+ DDRSS1_PHY_1212_DATA
+ DDRSS1_PHY_1213_DATA
+ DDRSS1_PHY_1214_DATA
+ DDRSS1_PHY_1215_DATA
+ DDRSS1_PHY_1216_DATA
+ DDRSS1_PHY_1217_DATA
+ DDRSS1_PHY_1218_DATA
+ DDRSS1_PHY_1219_DATA
+ DDRSS1_PHY_1220_DATA
+ DDRSS1_PHY_1221_DATA
+ DDRSS1_PHY_1222_DATA
+ DDRSS1_PHY_1223_DATA
+ DDRSS1_PHY_1224_DATA
+ DDRSS1_PHY_1225_DATA
+ DDRSS1_PHY_1226_DATA
+ DDRSS1_PHY_1227_DATA
+ DDRSS1_PHY_1228_DATA
+ DDRSS1_PHY_1229_DATA
+ DDRSS1_PHY_1230_DATA
+ DDRSS1_PHY_1231_DATA
+ DDRSS1_PHY_1232_DATA
+ DDRSS1_PHY_1233_DATA
+ DDRSS1_PHY_1234_DATA
+ DDRSS1_PHY_1235_DATA
+ DDRSS1_PHY_1236_DATA
+ DDRSS1_PHY_1237_DATA
+ DDRSS1_PHY_1238_DATA
+ DDRSS1_PHY_1239_DATA
+ DDRSS1_PHY_1240_DATA
+ DDRSS1_PHY_1241_DATA
+ DDRSS1_PHY_1242_DATA
+ DDRSS1_PHY_1243_DATA
+ DDRSS1_PHY_1244_DATA
+ DDRSS1_PHY_1245_DATA
+ DDRSS1_PHY_1246_DATA
+ DDRSS1_PHY_1247_DATA
+ DDRSS1_PHY_1248_DATA
+ DDRSS1_PHY_1249_DATA
+ DDRSS1_PHY_1250_DATA
+ DDRSS1_PHY_1251_DATA
+ DDRSS1_PHY_1252_DATA
+ DDRSS1_PHY_1253_DATA
+ DDRSS1_PHY_1254_DATA
+ DDRSS1_PHY_1255_DATA
+ DDRSS1_PHY_1256_DATA
+ DDRSS1_PHY_1257_DATA
+ DDRSS1_PHY_1258_DATA
+ DDRSS1_PHY_1259_DATA
+ DDRSS1_PHY_1260_DATA
+ DDRSS1_PHY_1261_DATA
+ DDRSS1_PHY_1262_DATA
+ DDRSS1_PHY_1263_DATA
+ DDRSS1_PHY_1264_DATA
+ DDRSS1_PHY_1265_DATA
+ DDRSS1_PHY_1266_DATA
+ DDRSS1_PHY_1267_DATA
+ DDRSS1_PHY_1268_DATA
+ DDRSS1_PHY_1269_DATA
+ DDRSS1_PHY_1270_DATA
+ DDRSS1_PHY_1271_DATA
+ DDRSS1_PHY_1272_DATA
+ DDRSS1_PHY_1273_DATA
+ DDRSS1_PHY_1274_DATA
+ DDRSS1_PHY_1275_DATA
+ DDRSS1_PHY_1276_DATA
+ DDRSS1_PHY_1277_DATA
+ DDRSS1_PHY_1278_DATA
+ DDRSS1_PHY_1279_DATA
+ DDRSS1_PHY_1280_DATA
+ DDRSS1_PHY_1281_DATA
+ DDRSS1_PHY_1282_DATA
+ DDRSS1_PHY_1283_DATA
+ DDRSS1_PHY_1284_DATA
+ DDRSS1_PHY_1285_DATA
+ DDRSS1_PHY_1286_DATA
+ DDRSS1_PHY_1287_DATA
+ DDRSS1_PHY_1288_DATA
+ DDRSS1_PHY_1289_DATA
+ DDRSS1_PHY_1290_DATA
+ DDRSS1_PHY_1291_DATA
+ DDRSS1_PHY_1292_DATA
+ DDRSS1_PHY_1293_DATA
+ DDRSS1_PHY_1294_DATA
+ DDRSS1_PHY_1295_DATA
+ DDRSS1_PHY_1296_DATA
+ DDRSS1_PHY_1297_DATA
+ DDRSS1_PHY_1298_DATA
+ DDRSS1_PHY_1299_DATA
+ DDRSS1_PHY_1300_DATA
+ DDRSS1_PHY_1301_DATA
+ DDRSS1_PHY_1302_DATA
+ DDRSS1_PHY_1303_DATA
+ DDRSS1_PHY_1304_DATA
+ DDRSS1_PHY_1305_DATA
+ DDRSS1_PHY_1306_DATA
+ DDRSS1_PHY_1307_DATA
+ DDRSS1_PHY_1308_DATA
+ DDRSS1_PHY_1309_DATA
+ DDRSS1_PHY_1310_DATA
+ DDRSS1_PHY_1311_DATA
+ DDRSS1_PHY_1312_DATA
+ DDRSS1_PHY_1313_DATA
+ DDRSS1_PHY_1314_DATA
+ DDRSS1_PHY_1315_DATA
+ DDRSS1_PHY_1316_DATA
+ DDRSS1_PHY_1317_DATA
+ DDRSS1_PHY_1318_DATA
+ DDRSS1_PHY_1319_DATA
+ DDRSS1_PHY_1320_DATA
+ DDRSS1_PHY_1321_DATA
+ DDRSS1_PHY_1322_DATA
+ DDRSS1_PHY_1323_DATA
+ DDRSS1_PHY_1324_DATA
+ DDRSS1_PHY_1325_DATA
+ DDRSS1_PHY_1326_DATA
+ DDRSS1_PHY_1327_DATA
+ DDRSS1_PHY_1328_DATA
+ DDRSS1_PHY_1329_DATA
+ DDRSS1_PHY_1330_DATA
+ DDRSS1_PHY_1331_DATA
+ DDRSS1_PHY_1332_DATA
+ DDRSS1_PHY_1333_DATA
+ DDRSS1_PHY_1334_DATA
+ DDRSS1_PHY_1335_DATA
+ DDRSS1_PHY_1336_DATA
+ DDRSS1_PHY_1337_DATA
+ DDRSS1_PHY_1338_DATA
+ DDRSS1_PHY_1339_DATA
+ DDRSS1_PHY_1340_DATA
+ DDRSS1_PHY_1341_DATA
+ DDRSS1_PHY_1342_DATA
+ DDRSS1_PHY_1343_DATA
+ DDRSS1_PHY_1344_DATA
+ DDRSS1_PHY_1345_DATA
+ DDRSS1_PHY_1346_DATA
+ DDRSS1_PHY_1347_DATA
+ DDRSS1_PHY_1348_DATA
+ DDRSS1_PHY_1349_DATA
+ DDRSS1_PHY_1350_DATA
+ DDRSS1_PHY_1351_DATA
+ DDRSS1_PHY_1352_DATA
+ DDRSS1_PHY_1353_DATA
+ DDRSS1_PHY_1354_DATA
+ DDRSS1_PHY_1355_DATA
+ DDRSS1_PHY_1356_DATA
+ DDRSS1_PHY_1357_DATA
+ DDRSS1_PHY_1358_DATA
+ DDRSS1_PHY_1359_DATA
+ DDRSS1_PHY_1360_DATA
+ DDRSS1_PHY_1361_DATA
+ DDRSS1_PHY_1362_DATA
+ DDRSS1_PHY_1363_DATA
+ DDRSS1_PHY_1364_DATA
+ DDRSS1_PHY_1365_DATA
+ DDRSS1_PHY_1366_DATA
+ DDRSS1_PHY_1367_DATA
+ DDRSS1_PHY_1368_DATA
+ DDRSS1_PHY_1369_DATA
+ DDRSS1_PHY_1370_DATA
+ DDRSS1_PHY_1371_DATA
+ DDRSS1_PHY_1372_DATA
+ DDRSS1_PHY_1373_DATA
+ DDRSS1_PHY_1374_DATA
+ DDRSS1_PHY_1375_DATA
+ DDRSS1_PHY_1376_DATA
+ DDRSS1_PHY_1377_DATA
+ DDRSS1_PHY_1378_DATA
+ DDRSS1_PHY_1379_DATA
+ DDRSS1_PHY_1380_DATA
+ DDRSS1_PHY_1381_DATA
+ DDRSS1_PHY_1382_DATA
+ DDRSS1_PHY_1383_DATA
+ DDRSS1_PHY_1384_DATA
+ DDRSS1_PHY_1385_DATA
+ DDRSS1_PHY_1386_DATA
+ DDRSS1_PHY_1387_DATA
+ DDRSS1_PHY_1388_DATA
+ DDRSS1_PHY_1389_DATA
+ DDRSS1_PHY_1390_DATA
+ DDRSS1_PHY_1391_DATA
+ DDRSS1_PHY_1392_DATA
+ DDRSS1_PHY_1393_DATA
+ DDRSS1_PHY_1394_DATA
+ DDRSS1_PHY_1395_DATA
+ DDRSS1_PHY_1396_DATA
+ DDRSS1_PHY_1397_DATA
+ DDRSS1_PHY_1398_DATA
+ DDRSS1_PHY_1399_DATA
+ DDRSS1_PHY_1400_DATA
+ DDRSS1_PHY_1401_DATA
+ DDRSS1_PHY_1402_DATA
+ DDRSS1_PHY_1403_DATA
+ DDRSS1_PHY_1404_DATA
+ DDRSS1_PHY_1405_DATA
+ DDRSS1_PHY_1406_DATA
+ DDRSS1_PHY_1407_DATA
+ DDRSS1_PHY_1408_DATA
+ DDRSS1_PHY_1409_DATA
+ DDRSS1_PHY_1410_DATA
+ DDRSS1_PHY_1411_DATA
+ DDRSS1_PHY_1412_DATA
+ DDRSS1_PHY_1413_DATA
+ DDRSS1_PHY_1414_DATA
+ DDRSS1_PHY_1415_DATA
+ DDRSS1_PHY_1416_DATA
+ DDRSS1_PHY_1417_DATA
+ DDRSS1_PHY_1418_DATA
+ DDRSS1_PHY_1419_DATA
+ DDRSS1_PHY_1420_DATA
+ DDRSS1_PHY_1421_DATA
+ DDRSS1_PHY_1422_DATA
+ >;
+ };
+
+ memorycontroller2: memorycontroller@29d0000 {
+ compatible = "ti,j721s2-ddrss";
+ reg = <0x0 0x029d0000 0x0 0x4000>,
+ <0x0 0x0114000 0x0 0x100>;
+ reg-names = "cfg", "ctrl_mmr_lp4";
+ power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
+ <&k3_pds 133 TI_SCI_PD_SHARED>;
+ clocks = <&k3_clks 193 1>, <&k3_clks 78 2>;
+ ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+ ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+ ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+ ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+ instance = <2>;
+
+ u-boot,dm-spl;
+
+ ti,ctl-data = <
+ DDRSS2_CTL_00_DATA
+ DDRSS2_CTL_01_DATA
+ DDRSS2_CTL_02_DATA
+ DDRSS2_CTL_03_DATA
+ DDRSS2_CTL_04_DATA
+ DDRSS2_CTL_05_DATA
+ DDRSS2_CTL_06_DATA
+ DDRSS2_CTL_07_DATA
+ DDRSS2_CTL_08_DATA
+ DDRSS2_CTL_09_DATA
+ DDRSS2_CTL_10_DATA
+ DDRSS2_CTL_11_DATA
+ DDRSS2_CTL_12_DATA
+ DDRSS2_CTL_13_DATA
+ DDRSS2_CTL_14_DATA
+ DDRSS2_CTL_15_DATA
+ DDRSS2_CTL_16_DATA
+ DDRSS2_CTL_17_DATA
+ DDRSS2_CTL_18_DATA
+ DDRSS2_CTL_19_DATA
+ DDRSS2_CTL_20_DATA
+ DDRSS2_CTL_21_DATA
+ DDRSS2_CTL_22_DATA
+ DDRSS2_CTL_23_DATA
+ DDRSS2_CTL_24_DATA
+ DDRSS2_CTL_25_DATA
+ DDRSS2_CTL_26_DATA
+ DDRSS2_CTL_27_DATA
+ DDRSS2_CTL_28_DATA
+ DDRSS2_CTL_29_DATA
+ DDRSS2_CTL_30_DATA
+ DDRSS2_CTL_31_DATA
+ DDRSS2_CTL_32_DATA
+ DDRSS2_CTL_33_DATA
+ DDRSS2_CTL_34_DATA
+ DDRSS2_CTL_35_DATA
+ DDRSS2_CTL_36_DATA
+ DDRSS2_CTL_37_DATA
+ DDRSS2_CTL_38_DATA
+ DDRSS2_CTL_39_DATA
+ DDRSS2_CTL_40_DATA
+ DDRSS2_CTL_41_DATA
+ DDRSS2_CTL_42_DATA
+ DDRSS2_CTL_43_DATA
+ DDRSS2_CTL_44_DATA
+ DDRSS2_CTL_45_DATA
+ DDRSS2_CTL_46_DATA
+ DDRSS2_CTL_47_DATA
+ DDRSS2_CTL_48_DATA
+ DDRSS2_CTL_49_DATA
+ DDRSS2_CTL_50_DATA
+ DDRSS2_CTL_51_DATA
+ DDRSS2_CTL_52_DATA
+ DDRSS2_CTL_53_DATA
+ DDRSS2_CTL_54_DATA
+ DDRSS2_CTL_55_DATA
+ DDRSS2_CTL_56_DATA
+ DDRSS2_CTL_57_DATA
+ DDRSS2_CTL_58_DATA
+ DDRSS2_CTL_59_DATA
+ DDRSS2_CTL_60_DATA
+ DDRSS2_CTL_61_DATA
+ DDRSS2_CTL_62_DATA
+ DDRSS2_CTL_63_DATA
+ DDRSS2_CTL_64_DATA
+ DDRSS2_CTL_65_DATA
+ DDRSS2_CTL_66_DATA
+ DDRSS2_CTL_67_DATA
+ DDRSS2_CTL_68_DATA
+ DDRSS2_CTL_69_DATA
+ DDRSS2_CTL_70_DATA
+ DDRSS2_CTL_71_DATA
+ DDRSS2_CTL_72_DATA
+ DDRSS2_CTL_73_DATA
+ DDRSS2_CTL_74_DATA
+ DDRSS2_CTL_75_DATA
+ DDRSS2_CTL_76_DATA
+ DDRSS2_CTL_77_DATA
+ DDRSS2_CTL_78_DATA
+ DDRSS2_CTL_79_DATA
+ DDRSS2_CTL_80_DATA
+ DDRSS2_CTL_81_DATA
+ DDRSS2_CTL_82_DATA
+ DDRSS2_CTL_83_DATA
+ DDRSS2_CTL_84_DATA
+ DDRSS2_CTL_85_DATA
+ DDRSS2_CTL_86_DATA
+ DDRSS2_CTL_87_DATA
+ DDRSS2_CTL_88_DATA
+ DDRSS2_CTL_89_DATA
+ DDRSS2_CTL_90_DATA
+ DDRSS2_CTL_91_DATA
+ DDRSS2_CTL_92_DATA
+ DDRSS2_CTL_93_DATA
+ DDRSS2_CTL_94_DATA
+ DDRSS2_CTL_95_DATA
+ DDRSS2_CTL_96_DATA
+ DDRSS2_CTL_97_DATA
+ DDRSS2_CTL_98_DATA
+ DDRSS2_CTL_99_DATA
+ DDRSS2_CTL_100_DATA
+ DDRSS2_CTL_101_DATA
+ DDRSS2_CTL_102_DATA
+ DDRSS2_CTL_103_DATA
+ DDRSS2_CTL_104_DATA
+ DDRSS2_CTL_105_DATA
+ DDRSS2_CTL_106_DATA
+ DDRSS2_CTL_107_DATA
+ DDRSS2_CTL_108_DATA
+ DDRSS2_CTL_109_DATA
+ DDRSS2_CTL_110_DATA
+ DDRSS2_CTL_111_DATA
+ DDRSS2_CTL_112_DATA
+ DDRSS2_CTL_113_DATA
+ DDRSS2_CTL_114_DATA
+ DDRSS2_CTL_115_DATA
+ DDRSS2_CTL_116_DATA
+ DDRSS2_CTL_117_DATA
+ DDRSS2_CTL_118_DATA
+ DDRSS2_CTL_119_DATA
+ DDRSS2_CTL_120_DATA
+ DDRSS2_CTL_121_DATA
+ DDRSS2_CTL_122_DATA
+ DDRSS2_CTL_123_DATA
+ DDRSS2_CTL_124_DATA
+ DDRSS2_CTL_125_DATA
+ DDRSS2_CTL_126_DATA
+ DDRSS2_CTL_127_DATA
+ DDRSS2_CTL_128_DATA
+ DDRSS2_CTL_129_DATA
+ DDRSS2_CTL_130_DATA
+ DDRSS2_CTL_131_DATA
+ DDRSS2_CTL_132_DATA
+ DDRSS2_CTL_133_DATA
+ DDRSS2_CTL_134_DATA
+ DDRSS2_CTL_135_DATA
+ DDRSS2_CTL_136_DATA
+ DDRSS2_CTL_137_DATA
+ DDRSS2_CTL_138_DATA
+ DDRSS2_CTL_139_DATA
+ DDRSS2_CTL_140_DATA
+ DDRSS2_CTL_141_DATA
+ DDRSS2_CTL_142_DATA
+ DDRSS2_CTL_143_DATA
+ DDRSS2_CTL_144_DATA
+ DDRSS2_CTL_145_DATA
+ DDRSS2_CTL_146_DATA
+ DDRSS2_CTL_147_DATA
+ DDRSS2_CTL_148_DATA
+ DDRSS2_CTL_149_DATA
+ DDRSS2_CTL_150_DATA
+ DDRSS2_CTL_151_DATA
+ DDRSS2_CTL_152_DATA
+ DDRSS2_CTL_153_DATA
+ DDRSS2_CTL_154_DATA
+ DDRSS2_CTL_155_DATA
+ DDRSS2_CTL_156_DATA
+ DDRSS2_CTL_157_DATA
+ DDRSS2_CTL_158_DATA
+ DDRSS2_CTL_159_DATA
+ DDRSS2_CTL_160_DATA
+ DDRSS2_CTL_161_DATA
+ DDRSS2_CTL_162_DATA
+ DDRSS2_CTL_163_DATA
+ DDRSS2_CTL_164_DATA
+ DDRSS2_CTL_165_DATA
+ DDRSS2_CTL_166_DATA
+ DDRSS2_CTL_167_DATA
+ DDRSS2_CTL_168_DATA
+ DDRSS2_CTL_169_DATA
+ DDRSS2_CTL_170_DATA
+ DDRSS2_CTL_171_DATA
+ DDRSS2_CTL_172_DATA
+ DDRSS2_CTL_173_DATA
+ DDRSS2_CTL_174_DATA
+ DDRSS2_CTL_175_DATA
+ DDRSS2_CTL_176_DATA
+ DDRSS2_CTL_177_DATA
+ DDRSS2_CTL_178_DATA
+ DDRSS2_CTL_179_DATA
+ DDRSS2_CTL_180_DATA
+ DDRSS2_CTL_181_DATA
+ DDRSS2_CTL_182_DATA
+ DDRSS2_CTL_183_DATA
+ DDRSS2_CTL_184_DATA
+ DDRSS2_CTL_185_DATA
+ DDRSS2_CTL_186_DATA
+ DDRSS2_CTL_187_DATA
+ DDRSS2_CTL_188_DATA
+ DDRSS2_CTL_189_DATA
+ DDRSS2_CTL_190_DATA
+ DDRSS2_CTL_191_DATA
+ DDRSS2_CTL_192_DATA
+ DDRSS2_CTL_193_DATA
+ DDRSS2_CTL_194_DATA
+ DDRSS2_CTL_195_DATA
+ DDRSS2_CTL_196_DATA
+ DDRSS2_CTL_197_DATA
+ DDRSS2_CTL_198_DATA
+ DDRSS2_CTL_199_DATA
+ DDRSS2_CTL_200_DATA
+ DDRSS2_CTL_201_DATA
+ DDRSS2_CTL_202_DATA
+ DDRSS2_CTL_203_DATA
+ DDRSS2_CTL_204_DATA
+ DDRSS2_CTL_205_DATA
+ DDRSS2_CTL_206_DATA
+ DDRSS2_CTL_207_DATA
+ DDRSS2_CTL_208_DATA
+ DDRSS2_CTL_209_DATA
+ DDRSS2_CTL_210_DATA
+ DDRSS2_CTL_211_DATA
+ DDRSS2_CTL_212_DATA
+ DDRSS2_CTL_213_DATA
+ DDRSS2_CTL_214_DATA
+ DDRSS2_CTL_215_DATA
+ DDRSS2_CTL_216_DATA
+ DDRSS2_CTL_217_DATA
+ DDRSS2_CTL_218_DATA
+ DDRSS2_CTL_219_DATA
+ DDRSS2_CTL_220_DATA
+ DDRSS2_CTL_221_DATA
+ DDRSS2_CTL_222_DATA
+ DDRSS2_CTL_223_DATA
+ DDRSS2_CTL_224_DATA
+ DDRSS2_CTL_225_DATA
+ DDRSS2_CTL_226_DATA
+ DDRSS2_CTL_227_DATA
+ DDRSS2_CTL_228_DATA
+ DDRSS2_CTL_229_DATA
+ DDRSS2_CTL_230_DATA
+ DDRSS2_CTL_231_DATA
+ DDRSS2_CTL_232_DATA
+ DDRSS2_CTL_233_DATA
+ DDRSS2_CTL_234_DATA
+ DDRSS2_CTL_235_DATA
+ DDRSS2_CTL_236_DATA
+ DDRSS2_CTL_237_DATA
+ DDRSS2_CTL_238_DATA
+ DDRSS2_CTL_239_DATA
+ DDRSS2_CTL_240_DATA
+ DDRSS2_CTL_241_DATA
+ DDRSS2_CTL_242_DATA
+ DDRSS2_CTL_243_DATA
+ DDRSS2_CTL_244_DATA
+ DDRSS2_CTL_245_DATA
+ DDRSS2_CTL_246_DATA
+ DDRSS2_CTL_247_DATA
+ DDRSS2_CTL_248_DATA
+ DDRSS2_CTL_249_DATA
+ DDRSS2_CTL_250_DATA
+ DDRSS2_CTL_251_DATA
+ DDRSS2_CTL_252_DATA
+ DDRSS2_CTL_253_DATA
+ DDRSS2_CTL_254_DATA
+ DDRSS2_CTL_255_DATA
+ DDRSS2_CTL_256_DATA
+ DDRSS2_CTL_257_DATA
+ DDRSS2_CTL_258_DATA
+ DDRSS2_CTL_259_DATA
+ DDRSS2_CTL_260_DATA
+ DDRSS2_CTL_261_DATA
+ DDRSS2_CTL_262_DATA
+ DDRSS2_CTL_263_DATA
+ DDRSS2_CTL_264_DATA
+ DDRSS2_CTL_265_DATA
+ DDRSS2_CTL_266_DATA
+ DDRSS2_CTL_267_DATA
+ DDRSS2_CTL_268_DATA
+ DDRSS2_CTL_269_DATA
+ DDRSS2_CTL_270_DATA
+ DDRSS2_CTL_271_DATA
+ DDRSS2_CTL_272_DATA
+ DDRSS2_CTL_273_DATA
+ DDRSS2_CTL_274_DATA
+ DDRSS2_CTL_275_DATA
+ DDRSS2_CTL_276_DATA
+ DDRSS2_CTL_277_DATA
+ DDRSS2_CTL_278_DATA
+ DDRSS2_CTL_279_DATA
+ DDRSS2_CTL_280_DATA
+ DDRSS2_CTL_281_DATA
+ DDRSS2_CTL_282_DATA
+ DDRSS2_CTL_283_DATA
+ DDRSS2_CTL_284_DATA
+ DDRSS2_CTL_285_DATA
+ DDRSS2_CTL_286_DATA
+ DDRSS2_CTL_287_DATA
+ DDRSS2_CTL_288_DATA
+ DDRSS2_CTL_289_DATA
+ DDRSS2_CTL_290_DATA
+ DDRSS2_CTL_291_DATA
+ DDRSS2_CTL_292_DATA
+ DDRSS2_CTL_293_DATA
+ DDRSS2_CTL_294_DATA
+ DDRSS2_CTL_295_DATA
+ DDRSS2_CTL_296_DATA
+ DDRSS2_CTL_297_DATA
+ DDRSS2_CTL_298_DATA
+ DDRSS2_CTL_299_DATA
+ DDRSS2_CTL_300_DATA
+ DDRSS2_CTL_301_DATA
+ DDRSS2_CTL_302_DATA
+ DDRSS2_CTL_303_DATA
+ DDRSS2_CTL_304_DATA
+ DDRSS2_CTL_305_DATA
+ DDRSS2_CTL_306_DATA
+ DDRSS2_CTL_307_DATA
+ DDRSS2_CTL_308_DATA
+ DDRSS2_CTL_309_DATA
+ DDRSS2_CTL_310_DATA
+ DDRSS2_CTL_311_DATA
+ DDRSS2_CTL_312_DATA
+ DDRSS2_CTL_313_DATA
+ DDRSS2_CTL_314_DATA
+ DDRSS2_CTL_315_DATA
+ DDRSS2_CTL_316_DATA
+ DDRSS2_CTL_317_DATA
+ DDRSS2_CTL_318_DATA
+ DDRSS2_CTL_319_DATA
+ DDRSS2_CTL_320_DATA
+ DDRSS2_CTL_321_DATA
+ DDRSS2_CTL_322_DATA
+ DDRSS2_CTL_323_DATA
+ DDRSS2_CTL_324_DATA
+ DDRSS2_CTL_325_DATA
+ DDRSS2_CTL_326_DATA
+ DDRSS2_CTL_327_DATA
+ DDRSS2_CTL_328_DATA
+ DDRSS2_CTL_329_DATA
+ DDRSS2_CTL_330_DATA
+ DDRSS2_CTL_331_DATA
+ DDRSS2_CTL_332_DATA
+ DDRSS2_CTL_333_DATA
+ DDRSS2_CTL_334_DATA
+ DDRSS2_CTL_335_DATA
+ DDRSS2_CTL_336_DATA
+ DDRSS2_CTL_337_DATA
+ DDRSS2_CTL_338_DATA
+ DDRSS2_CTL_339_DATA
+ DDRSS2_CTL_340_DATA
+ DDRSS2_CTL_341_DATA
+ DDRSS2_CTL_342_DATA
+ DDRSS2_CTL_343_DATA
+ DDRSS2_CTL_344_DATA
+ DDRSS2_CTL_345_DATA
+ DDRSS2_CTL_346_DATA
+ DDRSS2_CTL_347_DATA
+ DDRSS2_CTL_348_DATA
+ DDRSS2_CTL_349_DATA
+ DDRSS2_CTL_350_DATA
+ DDRSS2_CTL_351_DATA
+ DDRSS2_CTL_352_DATA
+ DDRSS2_CTL_353_DATA
+ DDRSS2_CTL_354_DATA
+ DDRSS2_CTL_355_DATA
+ DDRSS2_CTL_356_DATA
+ DDRSS2_CTL_357_DATA
+ DDRSS2_CTL_358_DATA
+ DDRSS2_CTL_359_DATA
+ DDRSS2_CTL_360_DATA
+ DDRSS2_CTL_361_DATA
+ DDRSS2_CTL_362_DATA
+ DDRSS2_CTL_363_DATA
+ DDRSS2_CTL_364_DATA
+ DDRSS2_CTL_365_DATA
+ DDRSS2_CTL_366_DATA
+ DDRSS2_CTL_367_DATA
+ DDRSS2_CTL_368_DATA
+ DDRSS2_CTL_369_DATA
+ DDRSS2_CTL_370_DATA
+ DDRSS2_CTL_371_DATA
+ DDRSS2_CTL_372_DATA
+ DDRSS2_CTL_373_DATA
+ DDRSS2_CTL_374_DATA
+ DDRSS2_CTL_375_DATA
+ DDRSS2_CTL_376_DATA
+ DDRSS2_CTL_377_DATA
+ DDRSS2_CTL_378_DATA
+ DDRSS2_CTL_379_DATA
+ DDRSS2_CTL_380_DATA
+ DDRSS2_CTL_381_DATA
+ DDRSS2_CTL_382_DATA
+ DDRSS2_CTL_383_DATA
+ DDRSS2_CTL_384_DATA
+ DDRSS2_CTL_385_DATA
+ DDRSS2_CTL_386_DATA
+ DDRSS2_CTL_387_DATA
+ DDRSS2_CTL_388_DATA
+ DDRSS2_CTL_389_DATA
+ DDRSS2_CTL_390_DATA
+ DDRSS2_CTL_391_DATA
+ DDRSS2_CTL_392_DATA
+ DDRSS2_CTL_393_DATA
+ DDRSS2_CTL_394_DATA
+ DDRSS2_CTL_395_DATA
+ DDRSS2_CTL_396_DATA
+ DDRSS2_CTL_397_DATA
+ DDRSS2_CTL_398_DATA
+ DDRSS2_CTL_399_DATA
+ DDRSS2_CTL_400_DATA
+ DDRSS2_CTL_401_DATA
+ DDRSS2_CTL_402_DATA
+ DDRSS2_CTL_403_DATA
+ DDRSS2_CTL_404_DATA
+ DDRSS2_CTL_405_DATA
+ DDRSS2_CTL_406_DATA
+ DDRSS2_CTL_407_DATA
+ DDRSS2_CTL_408_DATA
+ DDRSS2_CTL_409_DATA
+ DDRSS2_CTL_410_DATA
+ DDRSS2_CTL_411_DATA
+ DDRSS2_CTL_412_DATA
+ DDRSS2_CTL_413_DATA
+ DDRSS2_CTL_414_DATA
+ DDRSS2_CTL_415_DATA
+ DDRSS2_CTL_416_DATA
+ DDRSS2_CTL_417_DATA
+ DDRSS2_CTL_418_DATA
+ DDRSS2_CTL_419_DATA
+ DDRSS2_CTL_420_DATA
+ DDRSS2_CTL_421_DATA
+ DDRSS2_CTL_422_DATA
+ DDRSS2_CTL_423_DATA
+ DDRSS2_CTL_424_DATA
+ DDRSS2_CTL_425_DATA
+ DDRSS2_CTL_426_DATA
+ DDRSS2_CTL_427_DATA
+ DDRSS2_CTL_428_DATA
+ DDRSS2_CTL_429_DATA
+ DDRSS2_CTL_430_DATA
+ DDRSS2_CTL_431_DATA
+ DDRSS2_CTL_432_DATA
+ DDRSS2_CTL_433_DATA
+ DDRSS2_CTL_434_DATA
+ DDRSS2_CTL_435_DATA
+ DDRSS2_CTL_436_DATA
+ DDRSS2_CTL_437_DATA
+ DDRSS2_CTL_438_DATA
+ DDRSS2_CTL_439_DATA
+ DDRSS2_CTL_440_DATA
+ DDRSS2_CTL_441_DATA
+ DDRSS2_CTL_442_DATA
+ DDRSS2_CTL_443_DATA
+ DDRSS2_CTL_444_DATA
+ DDRSS2_CTL_445_DATA
+ DDRSS2_CTL_446_DATA
+ DDRSS2_CTL_447_DATA
+ DDRSS2_CTL_448_DATA
+ DDRSS2_CTL_449_DATA
+ DDRSS2_CTL_450_DATA
+ DDRSS2_CTL_451_DATA
+ DDRSS2_CTL_452_DATA
+ DDRSS2_CTL_453_DATA
+ DDRSS2_CTL_454_DATA
+ DDRSS2_CTL_455_DATA
+ DDRSS2_CTL_456_DATA
+ DDRSS2_CTL_457_DATA
+ DDRSS2_CTL_458_DATA
+ >;
+
+ ti,pi-data = <
+ DDRSS2_PI_00_DATA
+ DDRSS2_PI_01_DATA
+ DDRSS2_PI_02_DATA
+ DDRSS2_PI_03_DATA
+ DDRSS2_PI_04_DATA
+ DDRSS2_PI_05_DATA
+ DDRSS2_PI_06_DATA
+ DDRSS2_PI_07_DATA
+ DDRSS2_PI_08_DATA
+ DDRSS2_PI_09_DATA
+ DDRSS2_PI_10_DATA
+ DDRSS2_PI_11_DATA
+ DDRSS2_PI_12_DATA
+ DDRSS2_PI_13_DATA
+ DDRSS2_PI_14_DATA
+ DDRSS2_PI_15_DATA
+ DDRSS2_PI_16_DATA
+ DDRSS2_PI_17_DATA
+ DDRSS2_PI_18_DATA
+ DDRSS2_PI_19_DATA
+ DDRSS2_PI_20_DATA
+ DDRSS2_PI_21_DATA
+ DDRSS2_PI_22_DATA
+ DDRSS2_PI_23_DATA
+ DDRSS2_PI_24_DATA
+ DDRSS2_PI_25_DATA
+ DDRSS2_PI_26_DATA
+ DDRSS2_PI_27_DATA
+ DDRSS2_PI_28_DATA
+ DDRSS2_PI_29_DATA
+ DDRSS2_PI_30_DATA
+ DDRSS2_PI_31_DATA
+ DDRSS2_PI_32_DATA
+ DDRSS2_PI_33_DATA
+ DDRSS2_PI_34_DATA
+ DDRSS2_PI_35_DATA
+ DDRSS2_PI_36_DATA
+ DDRSS2_PI_37_DATA
+ DDRSS2_PI_38_DATA
+ DDRSS2_PI_39_DATA
+ DDRSS2_PI_40_DATA
+ DDRSS2_PI_41_DATA
+ DDRSS2_PI_42_DATA
+ DDRSS2_PI_43_DATA
+ DDRSS2_PI_44_DATA
+ DDRSS2_PI_45_DATA
+ DDRSS2_PI_46_DATA
+ DDRSS2_PI_47_DATA
+ DDRSS2_PI_48_DATA
+ DDRSS2_PI_49_DATA
+ DDRSS2_PI_50_DATA
+ DDRSS2_PI_51_DATA
+ DDRSS2_PI_52_DATA
+ DDRSS2_PI_53_DATA
+ DDRSS2_PI_54_DATA
+ DDRSS2_PI_55_DATA
+ DDRSS2_PI_56_DATA
+ DDRSS2_PI_57_DATA
+ DDRSS2_PI_58_DATA
+ DDRSS2_PI_59_DATA
+ DDRSS2_PI_60_DATA
+ DDRSS2_PI_61_DATA
+ DDRSS2_PI_62_DATA
+ DDRSS2_PI_63_DATA
+ DDRSS2_PI_64_DATA
+ DDRSS2_PI_65_DATA
+ DDRSS2_PI_66_DATA
+ DDRSS2_PI_67_DATA
+ DDRSS2_PI_68_DATA
+ DDRSS2_PI_69_DATA
+ DDRSS2_PI_70_DATA
+ DDRSS2_PI_71_DATA
+ DDRSS2_PI_72_DATA
+ DDRSS2_PI_73_DATA
+ DDRSS2_PI_74_DATA
+ DDRSS2_PI_75_DATA
+ DDRSS2_PI_76_DATA
+ DDRSS2_PI_77_DATA
+ DDRSS2_PI_78_DATA
+ DDRSS2_PI_79_DATA
+ DDRSS2_PI_80_DATA
+ DDRSS2_PI_81_DATA
+ DDRSS2_PI_82_DATA
+ DDRSS2_PI_83_DATA
+ DDRSS2_PI_84_DATA
+ DDRSS2_PI_85_DATA
+ DDRSS2_PI_86_DATA
+ DDRSS2_PI_87_DATA
+ DDRSS2_PI_88_DATA
+ DDRSS2_PI_89_DATA
+ DDRSS2_PI_90_DATA
+ DDRSS2_PI_91_DATA
+ DDRSS2_PI_92_DATA
+ DDRSS2_PI_93_DATA
+ DDRSS2_PI_94_DATA
+ DDRSS2_PI_95_DATA
+ DDRSS2_PI_96_DATA
+ DDRSS2_PI_97_DATA
+ DDRSS2_PI_98_DATA
+ DDRSS2_PI_99_DATA
+ DDRSS2_PI_100_DATA
+ DDRSS2_PI_101_DATA
+ DDRSS2_PI_102_DATA
+ DDRSS2_PI_103_DATA
+ DDRSS2_PI_104_DATA
+ DDRSS2_PI_105_DATA
+ DDRSS2_PI_106_DATA
+ DDRSS2_PI_107_DATA
+ DDRSS2_PI_108_DATA
+ DDRSS2_PI_109_DATA
+ DDRSS2_PI_110_DATA
+ DDRSS2_PI_111_DATA
+ DDRSS2_PI_112_DATA
+ DDRSS2_PI_113_DATA
+ DDRSS2_PI_114_DATA
+ DDRSS2_PI_115_DATA
+ DDRSS2_PI_116_DATA
+ DDRSS2_PI_117_DATA
+ DDRSS2_PI_118_DATA
+ DDRSS2_PI_119_DATA
+ DDRSS2_PI_120_DATA
+ DDRSS2_PI_121_DATA
+ DDRSS2_PI_122_DATA
+ DDRSS2_PI_123_DATA
+ DDRSS2_PI_124_DATA
+ DDRSS2_PI_125_DATA
+ DDRSS2_PI_126_DATA
+ DDRSS2_PI_127_DATA
+ DDRSS2_PI_128_DATA
+ DDRSS2_PI_129_DATA
+ DDRSS2_PI_130_DATA
+ DDRSS2_PI_131_DATA
+ DDRSS2_PI_132_DATA
+ DDRSS2_PI_133_DATA
+ DDRSS2_PI_134_DATA
+ DDRSS2_PI_135_DATA
+ DDRSS2_PI_136_DATA
+ DDRSS2_PI_137_DATA
+ DDRSS2_PI_138_DATA
+ DDRSS2_PI_139_DATA
+ DDRSS2_PI_140_DATA
+ DDRSS2_PI_141_DATA
+ DDRSS2_PI_142_DATA
+ DDRSS2_PI_143_DATA
+ DDRSS2_PI_144_DATA
+ DDRSS2_PI_145_DATA
+ DDRSS2_PI_146_DATA
+ DDRSS2_PI_147_DATA
+ DDRSS2_PI_148_DATA
+ DDRSS2_PI_149_DATA
+ DDRSS2_PI_150_DATA
+ DDRSS2_PI_151_DATA
+ DDRSS2_PI_152_DATA
+ DDRSS2_PI_153_DATA
+ DDRSS2_PI_154_DATA
+ DDRSS2_PI_155_DATA
+ DDRSS2_PI_156_DATA
+ DDRSS2_PI_157_DATA
+ DDRSS2_PI_158_DATA
+ DDRSS2_PI_159_DATA
+ DDRSS2_PI_160_DATA
+ DDRSS2_PI_161_DATA
+ DDRSS2_PI_162_DATA
+ DDRSS2_PI_163_DATA
+ DDRSS2_PI_164_DATA
+ DDRSS2_PI_165_DATA
+ DDRSS2_PI_166_DATA
+ DDRSS2_PI_167_DATA
+ DDRSS2_PI_168_DATA
+ DDRSS2_PI_169_DATA
+ DDRSS2_PI_170_DATA
+ DDRSS2_PI_171_DATA
+ DDRSS2_PI_172_DATA
+ DDRSS2_PI_173_DATA
+ DDRSS2_PI_174_DATA
+ DDRSS2_PI_175_DATA
+ DDRSS2_PI_176_DATA
+ DDRSS2_PI_177_DATA
+ DDRSS2_PI_178_DATA
+ DDRSS2_PI_179_DATA
+ DDRSS2_PI_180_DATA
+ DDRSS2_PI_181_DATA
+ DDRSS2_PI_182_DATA
+ DDRSS2_PI_183_DATA
+ DDRSS2_PI_184_DATA
+ DDRSS2_PI_185_DATA
+ DDRSS2_PI_186_DATA
+ DDRSS2_PI_187_DATA
+ DDRSS2_PI_188_DATA
+ DDRSS2_PI_189_DATA
+ DDRSS2_PI_190_DATA
+ DDRSS2_PI_191_DATA
+ DDRSS2_PI_192_DATA
+ DDRSS2_PI_193_DATA
+ DDRSS2_PI_194_DATA
+ DDRSS2_PI_195_DATA
+ DDRSS2_PI_196_DATA
+ DDRSS2_PI_197_DATA
+ DDRSS2_PI_198_DATA
+ DDRSS2_PI_199_DATA
+ DDRSS2_PI_200_DATA
+ DDRSS2_PI_201_DATA
+ DDRSS2_PI_202_DATA
+ DDRSS2_PI_203_DATA
+ DDRSS2_PI_204_DATA
+ DDRSS2_PI_205_DATA
+ DDRSS2_PI_206_DATA
+ DDRSS2_PI_207_DATA
+ DDRSS2_PI_208_DATA
+ DDRSS2_PI_209_DATA
+ DDRSS2_PI_210_DATA
+ DDRSS2_PI_211_DATA
+ DDRSS2_PI_212_DATA
+ DDRSS2_PI_213_DATA
+ DDRSS2_PI_214_DATA
+ DDRSS2_PI_215_DATA
+ DDRSS2_PI_216_DATA
+ DDRSS2_PI_217_DATA
+ DDRSS2_PI_218_DATA
+ DDRSS2_PI_219_DATA
+ DDRSS2_PI_220_DATA
+ DDRSS2_PI_221_DATA
+ DDRSS2_PI_222_DATA
+ DDRSS2_PI_223_DATA
+ DDRSS2_PI_224_DATA
+ DDRSS2_PI_225_DATA
+ DDRSS2_PI_226_DATA
+ DDRSS2_PI_227_DATA
+ DDRSS2_PI_228_DATA
+ DDRSS2_PI_229_DATA
+ DDRSS2_PI_230_DATA
+ DDRSS2_PI_231_DATA
+ DDRSS2_PI_232_DATA
+ DDRSS2_PI_233_DATA
+ DDRSS2_PI_234_DATA
+ DDRSS2_PI_235_DATA
+ DDRSS2_PI_236_DATA
+ DDRSS2_PI_237_DATA
+ DDRSS2_PI_238_DATA
+ DDRSS2_PI_239_DATA
+ DDRSS2_PI_240_DATA
+ DDRSS2_PI_241_DATA
+ DDRSS2_PI_242_DATA
+ DDRSS2_PI_243_DATA
+ DDRSS2_PI_244_DATA
+ DDRSS2_PI_245_DATA
+ DDRSS2_PI_246_DATA
+ DDRSS2_PI_247_DATA
+ DDRSS2_PI_248_DATA
+ DDRSS2_PI_249_DATA
+ DDRSS2_PI_250_DATA
+ DDRSS2_PI_251_DATA
+ DDRSS2_PI_252_DATA
+ DDRSS2_PI_253_DATA
+ DDRSS2_PI_254_DATA
+ DDRSS2_PI_255_DATA
+ DDRSS2_PI_256_DATA
+ DDRSS2_PI_257_DATA
+ DDRSS2_PI_258_DATA
+ DDRSS2_PI_259_DATA
+ DDRSS2_PI_260_DATA
+ DDRSS2_PI_261_DATA
+ DDRSS2_PI_262_DATA
+ DDRSS2_PI_263_DATA
+ DDRSS2_PI_264_DATA
+ DDRSS2_PI_265_DATA
+ DDRSS2_PI_266_DATA
+ DDRSS2_PI_267_DATA
+ DDRSS2_PI_268_DATA
+ DDRSS2_PI_269_DATA
+ DDRSS2_PI_270_DATA
+ DDRSS2_PI_271_DATA
+ DDRSS2_PI_272_DATA
+ DDRSS2_PI_273_DATA
+ DDRSS2_PI_274_DATA
+ DDRSS2_PI_275_DATA
+ DDRSS2_PI_276_DATA
+ DDRSS2_PI_277_DATA
+ DDRSS2_PI_278_DATA
+ DDRSS2_PI_279_DATA
+ DDRSS2_PI_280_DATA
+ DDRSS2_PI_281_DATA
+ DDRSS2_PI_282_DATA
+ DDRSS2_PI_283_DATA
+ DDRSS2_PI_284_DATA
+ DDRSS2_PI_285_DATA
+ DDRSS2_PI_286_DATA
+ DDRSS2_PI_287_DATA
+ DDRSS2_PI_288_DATA
+ DDRSS2_PI_289_DATA
+ DDRSS2_PI_290_DATA
+ DDRSS2_PI_291_DATA
+ DDRSS2_PI_292_DATA
+ DDRSS2_PI_293_DATA
+ DDRSS2_PI_294_DATA
+ DDRSS2_PI_295_DATA
+ DDRSS2_PI_296_DATA
+ DDRSS2_PI_297_DATA
+ DDRSS2_PI_298_DATA
+ DDRSS2_PI_299_DATA
+ >;
+
+ ti,phy-data = <
+ DDRSS2_PHY_00_DATA
+ DDRSS2_PHY_01_DATA
+ DDRSS2_PHY_02_DATA
+ DDRSS2_PHY_03_DATA
+ DDRSS2_PHY_04_DATA
+ DDRSS2_PHY_05_DATA
+ DDRSS2_PHY_06_DATA
+ DDRSS2_PHY_07_DATA
+ DDRSS2_PHY_08_DATA
+ DDRSS2_PHY_09_DATA
+ DDRSS2_PHY_10_DATA
+ DDRSS2_PHY_11_DATA
+ DDRSS2_PHY_12_DATA
+ DDRSS2_PHY_13_DATA
+ DDRSS2_PHY_14_DATA
+ DDRSS2_PHY_15_DATA
+ DDRSS2_PHY_16_DATA
+ DDRSS2_PHY_17_DATA
+ DDRSS2_PHY_18_DATA
+ DDRSS2_PHY_19_DATA
+ DDRSS2_PHY_20_DATA
+ DDRSS2_PHY_21_DATA
+ DDRSS2_PHY_22_DATA
+ DDRSS2_PHY_23_DATA
+ DDRSS2_PHY_24_DATA
+ DDRSS2_PHY_25_DATA
+ DDRSS2_PHY_26_DATA
+ DDRSS2_PHY_27_DATA
+ DDRSS2_PHY_28_DATA
+ DDRSS2_PHY_29_DATA
+ DDRSS2_PHY_30_DATA
+ DDRSS2_PHY_31_DATA
+ DDRSS2_PHY_32_DATA
+ DDRSS2_PHY_33_DATA
+ DDRSS2_PHY_34_DATA
+ DDRSS2_PHY_35_DATA
+ DDRSS2_PHY_36_DATA
+ DDRSS2_PHY_37_DATA
+ DDRSS2_PHY_38_DATA
+ DDRSS2_PHY_39_DATA
+ DDRSS2_PHY_40_DATA
+ DDRSS2_PHY_41_DATA
+ DDRSS2_PHY_42_DATA
+ DDRSS2_PHY_43_DATA
+ DDRSS2_PHY_44_DATA
+ DDRSS2_PHY_45_DATA
+ DDRSS2_PHY_46_DATA
+ DDRSS2_PHY_47_DATA
+ DDRSS2_PHY_48_DATA
+ DDRSS2_PHY_49_DATA
+ DDRSS2_PHY_50_DATA
+ DDRSS2_PHY_51_DATA
+ DDRSS2_PHY_52_DATA
+ DDRSS2_PHY_53_DATA
+ DDRSS2_PHY_54_DATA
+ DDRSS2_PHY_55_DATA
+ DDRSS2_PHY_56_DATA
+ DDRSS2_PHY_57_DATA
+ DDRSS2_PHY_58_DATA
+ DDRSS2_PHY_59_DATA
+ DDRSS2_PHY_60_DATA
+ DDRSS2_PHY_61_DATA
+ DDRSS2_PHY_62_DATA
+ DDRSS2_PHY_63_DATA
+ DDRSS2_PHY_64_DATA
+ DDRSS2_PHY_65_DATA
+ DDRSS2_PHY_66_DATA
+ DDRSS2_PHY_67_DATA
+ DDRSS2_PHY_68_DATA
+ DDRSS2_PHY_69_DATA
+ DDRSS2_PHY_70_DATA
+ DDRSS2_PHY_71_DATA
+ DDRSS2_PHY_72_DATA
+ DDRSS2_PHY_73_DATA
+ DDRSS2_PHY_74_DATA
+ DDRSS2_PHY_75_DATA
+ DDRSS2_PHY_76_DATA
+ DDRSS2_PHY_77_DATA
+ DDRSS2_PHY_78_DATA
+ DDRSS2_PHY_79_DATA
+ DDRSS2_PHY_80_DATA
+ DDRSS2_PHY_81_DATA
+ DDRSS2_PHY_82_DATA
+ DDRSS2_PHY_83_DATA
+ DDRSS2_PHY_84_DATA
+ DDRSS2_PHY_85_DATA
+ DDRSS2_PHY_86_DATA
+ DDRSS2_PHY_87_DATA
+ DDRSS2_PHY_88_DATA
+ DDRSS2_PHY_89_DATA
+ DDRSS2_PHY_90_DATA
+ DDRSS2_PHY_91_DATA
+ DDRSS2_PHY_92_DATA
+ DDRSS2_PHY_93_DATA
+ DDRSS2_PHY_94_DATA
+ DDRSS2_PHY_95_DATA
+ DDRSS2_PHY_96_DATA
+ DDRSS2_PHY_97_DATA
+ DDRSS2_PHY_98_DATA
+ DDRSS2_PHY_99_DATA
+ DDRSS2_PHY_100_DATA
+ DDRSS2_PHY_101_DATA
+ DDRSS2_PHY_102_DATA
+ DDRSS2_PHY_103_DATA
+ DDRSS2_PHY_104_DATA
+ DDRSS2_PHY_105_DATA
+ DDRSS2_PHY_106_DATA
+ DDRSS2_PHY_107_DATA
+ DDRSS2_PHY_108_DATA
+ DDRSS2_PHY_109_DATA
+ DDRSS2_PHY_110_DATA
+ DDRSS2_PHY_111_DATA
+ DDRSS2_PHY_112_DATA
+ DDRSS2_PHY_113_DATA
+ DDRSS2_PHY_114_DATA
+ DDRSS2_PHY_115_DATA
+ DDRSS2_PHY_116_DATA
+ DDRSS2_PHY_117_DATA
+ DDRSS2_PHY_118_DATA
+ DDRSS2_PHY_119_DATA
+ DDRSS2_PHY_120_DATA
+ DDRSS2_PHY_121_DATA
+ DDRSS2_PHY_122_DATA
+ DDRSS2_PHY_123_DATA
+ DDRSS2_PHY_124_DATA
+ DDRSS2_PHY_125_DATA
+ DDRSS2_PHY_126_DATA
+ DDRSS2_PHY_127_DATA
+ DDRSS2_PHY_128_DATA
+ DDRSS2_PHY_129_DATA
+ DDRSS2_PHY_130_DATA
+ DDRSS2_PHY_131_DATA
+ DDRSS2_PHY_132_DATA
+ DDRSS2_PHY_133_DATA
+ DDRSS2_PHY_134_DATA
+ DDRSS2_PHY_135_DATA
+ DDRSS2_PHY_136_DATA
+ DDRSS2_PHY_137_DATA
+ DDRSS2_PHY_138_DATA
+ DDRSS2_PHY_139_DATA
+ DDRSS2_PHY_140_DATA
+ DDRSS2_PHY_141_DATA
+ DDRSS2_PHY_142_DATA
+ DDRSS2_PHY_143_DATA
+ DDRSS2_PHY_144_DATA
+ DDRSS2_PHY_145_DATA
+ DDRSS2_PHY_146_DATA
+ DDRSS2_PHY_147_DATA
+ DDRSS2_PHY_148_DATA
+ DDRSS2_PHY_149_DATA
+ DDRSS2_PHY_150_DATA
+ DDRSS2_PHY_151_DATA
+ DDRSS2_PHY_152_DATA
+ DDRSS2_PHY_153_DATA
+ DDRSS2_PHY_154_DATA
+ DDRSS2_PHY_155_DATA
+ DDRSS2_PHY_156_DATA
+ DDRSS2_PHY_157_DATA
+ DDRSS2_PHY_158_DATA
+ DDRSS2_PHY_159_DATA
+ DDRSS2_PHY_160_DATA
+ DDRSS2_PHY_161_DATA
+ DDRSS2_PHY_162_DATA
+ DDRSS2_PHY_163_DATA
+ DDRSS2_PHY_164_DATA
+ DDRSS2_PHY_165_DATA
+ DDRSS2_PHY_166_DATA
+ DDRSS2_PHY_167_DATA
+ DDRSS2_PHY_168_DATA
+ DDRSS2_PHY_169_DATA
+ DDRSS2_PHY_170_DATA
+ DDRSS2_PHY_171_DATA
+ DDRSS2_PHY_172_DATA
+ DDRSS2_PHY_173_DATA
+ DDRSS2_PHY_174_DATA
+ DDRSS2_PHY_175_DATA
+ DDRSS2_PHY_176_DATA
+ DDRSS2_PHY_177_DATA
+ DDRSS2_PHY_178_DATA
+ DDRSS2_PHY_179_DATA
+ DDRSS2_PHY_180_DATA
+ DDRSS2_PHY_181_DATA
+ DDRSS2_PHY_182_DATA
+ DDRSS2_PHY_183_DATA
+ DDRSS2_PHY_184_DATA
+ DDRSS2_PHY_185_DATA
+ DDRSS2_PHY_186_DATA
+ DDRSS2_PHY_187_DATA
+ DDRSS2_PHY_188_DATA
+ DDRSS2_PHY_189_DATA
+ DDRSS2_PHY_190_DATA
+ DDRSS2_PHY_191_DATA
+ DDRSS2_PHY_192_DATA
+ DDRSS2_PHY_193_DATA
+ DDRSS2_PHY_194_DATA
+ DDRSS2_PHY_195_DATA
+ DDRSS2_PHY_196_DATA
+ DDRSS2_PHY_197_DATA
+ DDRSS2_PHY_198_DATA
+ DDRSS2_PHY_199_DATA
+ DDRSS2_PHY_200_DATA
+ DDRSS2_PHY_201_DATA
+ DDRSS2_PHY_202_DATA
+ DDRSS2_PHY_203_DATA
+ DDRSS2_PHY_204_DATA
+ DDRSS2_PHY_205_DATA
+ DDRSS2_PHY_206_DATA
+ DDRSS2_PHY_207_DATA
+ DDRSS2_PHY_208_DATA
+ DDRSS2_PHY_209_DATA
+ DDRSS2_PHY_210_DATA
+ DDRSS2_PHY_211_DATA
+ DDRSS2_PHY_212_DATA
+ DDRSS2_PHY_213_DATA
+ DDRSS2_PHY_214_DATA
+ DDRSS2_PHY_215_DATA
+ DDRSS2_PHY_216_DATA
+ DDRSS2_PHY_217_DATA
+ DDRSS2_PHY_218_DATA
+ DDRSS2_PHY_219_DATA
+ DDRSS2_PHY_220_DATA
+ DDRSS2_PHY_221_DATA
+ DDRSS2_PHY_222_DATA
+ DDRSS2_PHY_223_DATA
+ DDRSS2_PHY_224_DATA
+ DDRSS2_PHY_225_DATA
+ DDRSS2_PHY_226_DATA
+ DDRSS2_PHY_227_DATA
+ DDRSS2_PHY_228_DATA
+ DDRSS2_PHY_229_DATA
+ DDRSS2_PHY_230_DATA
+ DDRSS2_PHY_231_DATA
+ DDRSS2_PHY_232_DATA
+ DDRSS2_PHY_233_DATA
+ DDRSS2_PHY_234_DATA
+ DDRSS2_PHY_235_DATA
+ DDRSS2_PHY_236_DATA
+ DDRSS2_PHY_237_DATA
+ DDRSS2_PHY_238_DATA
+ DDRSS2_PHY_239_DATA
+ DDRSS2_PHY_240_DATA
+ DDRSS2_PHY_241_DATA
+ DDRSS2_PHY_242_DATA
+ DDRSS2_PHY_243_DATA
+ DDRSS2_PHY_244_DATA
+ DDRSS2_PHY_245_DATA
+ DDRSS2_PHY_246_DATA
+ DDRSS2_PHY_247_DATA
+ DDRSS2_PHY_248_DATA
+ DDRSS2_PHY_249_DATA
+ DDRSS2_PHY_250_DATA
+ DDRSS2_PHY_251_DATA
+ DDRSS2_PHY_252_DATA
+ DDRSS2_PHY_253_DATA
+ DDRSS2_PHY_254_DATA
+ DDRSS2_PHY_255_DATA
+ DDRSS2_PHY_256_DATA
+ DDRSS2_PHY_257_DATA
+ DDRSS2_PHY_258_DATA
+ DDRSS2_PHY_259_DATA
+ DDRSS2_PHY_260_DATA
+ DDRSS2_PHY_261_DATA
+ DDRSS2_PHY_262_DATA
+ DDRSS2_PHY_263_DATA
+ DDRSS2_PHY_264_DATA
+ DDRSS2_PHY_265_DATA
+ DDRSS2_PHY_266_DATA
+ DDRSS2_PHY_267_DATA
+ DDRSS2_PHY_268_DATA
+ DDRSS2_PHY_269_DATA
+ DDRSS2_PHY_270_DATA
+ DDRSS2_PHY_271_DATA
+ DDRSS2_PHY_272_DATA
+ DDRSS2_PHY_273_DATA
+ DDRSS2_PHY_274_DATA
+ DDRSS2_PHY_275_DATA
+ DDRSS2_PHY_276_DATA
+ DDRSS2_PHY_277_DATA
+ DDRSS2_PHY_278_DATA
+ DDRSS2_PHY_279_DATA
+ DDRSS2_PHY_280_DATA
+ DDRSS2_PHY_281_DATA
+ DDRSS2_PHY_282_DATA
+ DDRSS2_PHY_283_DATA
+ DDRSS2_PHY_284_DATA
+ DDRSS2_PHY_285_DATA
+ DDRSS2_PHY_286_DATA
+ DDRSS2_PHY_287_DATA
+ DDRSS2_PHY_288_DATA
+ DDRSS2_PHY_289_DATA
+ DDRSS2_PHY_290_DATA
+ DDRSS2_PHY_291_DATA
+ DDRSS2_PHY_292_DATA
+ DDRSS2_PHY_293_DATA
+ DDRSS2_PHY_294_DATA
+ DDRSS2_PHY_295_DATA
+ DDRSS2_PHY_296_DATA
+ DDRSS2_PHY_297_DATA
+ DDRSS2_PHY_298_DATA
+ DDRSS2_PHY_299_DATA
+ DDRSS2_PHY_300_DATA
+ DDRSS2_PHY_301_DATA
+ DDRSS2_PHY_302_DATA
+ DDRSS2_PHY_303_DATA
+ DDRSS2_PHY_304_DATA
+ DDRSS2_PHY_305_DATA
+ DDRSS2_PHY_306_DATA
+ DDRSS2_PHY_307_DATA
+ DDRSS2_PHY_308_DATA
+ DDRSS2_PHY_309_DATA
+ DDRSS2_PHY_310_DATA
+ DDRSS2_PHY_311_DATA
+ DDRSS2_PHY_312_DATA
+ DDRSS2_PHY_313_DATA
+ DDRSS2_PHY_314_DATA
+ DDRSS2_PHY_315_DATA
+ DDRSS2_PHY_316_DATA
+ DDRSS2_PHY_317_DATA
+ DDRSS2_PHY_318_DATA
+ DDRSS2_PHY_319_DATA
+ DDRSS2_PHY_320_DATA
+ DDRSS2_PHY_321_DATA
+ DDRSS2_PHY_322_DATA
+ DDRSS2_PHY_323_DATA
+ DDRSS2_PHY_324_DATA
+ DDRSS2_PHY_325_DATA
+ DDRSS2_PHY_326_DATA
+ DDRSS2_PHY_327_DATA
+ DDRSS2_PHY_328_DATA
+ DDRSS2_PHY_329_DATA
+ DDRSS2_PHY_330_DATA
+ DDRSS2_PHY_331_DATA
+ DDRSS2_PHY_332_DATA
+ DDRSS2_PHY_333_DATA
+ DDRSS2_PHY_334_DATA
+ DDRSS2_PHY_335_DATA
+ DDRSS2_PHY_336_DATA
+ DDRSS2_PHY_337_DATA
+ DDRSS2_PHY_338_DATA
+ DDRSS2_PHY_339_DATA
+ DDRSS2_PHY_340_DATA
+ DDRSS2_PHY_341_DATA
+ DDRSS2_PHY_342_DATA
+ DDRSS2_PHY_343_DATA
+ DDRSS2_PHY_344_DATA
+ DDRSS2_PHY_345_DATA
+ DDRSS2_PHY_346_DATA
+ DDRSS2_PHY_347_DATA
+ DDRSS2_PHY_348_DATA
+ DDRSS2_PHY_349_DATA
+ DDRSS2_PHY_350_DATA
+ DDRSS2_PHY_351_DATA
+ DDRSS2_PHY_352_DATA
+ DDRSS2_PHY_353_DATA
+ DDRSS2_PHY_354_DATA
+ DDRSS2_PHY_355_DATA
+ DDRSS2_PHY_356_DATA
+ DDRSS2_PHY_357_DATA
+ DDRSS2_PHY_358_DATA
+ DDRSS2_PHY_359_DATA
+ DDRSS2_PHY_360_DATA
+ DDRSS2_PHY_361_DATA
+ DDRSS2_PHY_362_DATA
+ DDRSS2_PHY_363_DATA
+ DDRSS2_PHY_364_DATA
+ DDRSS2_PHY_365_DATA
+ DDRSS2_PHY_366_DATA
+ DDRSS2_PHY_367_DATA
+ DDRSS2_PHY_368_DATA
+ DDRSS2_PHY_369_DATA
+ DDRSS2_PHY_370_DATA
+ DDRSS2_PHY_371_DATA
+ DDRSS2_PHY_372_DATA
+ DDRSS2_PHY_373_DATA
+ DDRSS2_PHY_374_DATA
+ DDRSS2_PHY_375_DATA
+ DDRSS2_PHY_376_DATA
+ DDRSS2_PHY_377_DATA
+ DDRSS2_PHY_378_DATA
+ DDRSS2_PHY_379_DATA
+ DDRSS2_PHY_380_DATA
+ DDRSS2_PHY_381_DATA
+ DDRSS2_PHY_382_DATA
+ DDRSS2_PHY_383_DATA
+ DDRSS2_PHY_384_DATA
+ DDRSS2_PHY_385_DATA
+ DDRSS2_PHY_386_DATA
+ DDRSS2_PHY_387_DATA
+ DDRSS2_PHY_388_DATA
+ DDRSS2_PHY_389_DATA
+ DDRSS2_PHY_390_DATA
+ DDRSS2_PHY_391_DATA
+ DDRSS2_PHY_392_DATA
+ DDRSS2_PHY_393_DATA
+ DDRSS2_PHY_394_DATA
+ DDRSS2_PHY_395_DATA
+ DDRSS2_PHY_396_DATA
+ DDRSS2_PHY_397_DATA
+ DDRSS2_PHY_398_DATA
+ DDRSS2_PHY_399_DATA
+ DDRSS2_PHY_400_DATA
+ DDRSS2_PHY_401_DATA
+ DDRSS2_PHY_402_DATA
+ DDRSS2_PHY_403_DATA
+ DDRSS2_PHY_404_DATA
+ DDRSS2_PHY_405_DATA
+ DDRSS2_PHY_406_DATA
+ DDRSS2_PHY_407_DATA
+ DDRSS2_PHY_408_DATA
+ DDRSS2_PHY_409_DATA
+ DDRSS2_PHY_410_DATA
+ DDRSS2_PHY_411_DATA
+ DDRSS2_PHY_412_DATA
+ DDRSS2_PHY_413_DATA
+ DDRSS2_PHY_414_DATA
+ DDRSS2_PHY_415_DATA
+ DDRSS2_PHY_416_DATA
+ DDRSS2_PHY_417_DATA
+ DDRSS2_PHY_418_DATA
+ DDRSS2_PHY_419_DATA
+ DDRSS2_PHY_420_DATA
+ DDRSS2_PHY_421_DATA
+ DDRSS2_PHY_422_DATA
+ DDRSS2_PHY_423_DATA
+ DDRSS2_PHY_424_DATA
+ DDRSS2_PHY_425_DATA
+ DDRSS2_PHY_426_DATA
+ DDRSS2_PHY_427_DATA
+ DDRSS2_PHY_428_DATA
+ DDRSS2_PHY_429_DATA
+ DDRSS2_PHY_430_DATA
+ DDRSS2_PHY_431_DATA
+ DDRSS2_PHY_432_DATA
+ DDRSS2_PHY_433_DATA
+ DDRSS2_PHY_434_DATA
+ DDRSS2_PHY_435_DATA
+ DDRSS2_PHY_436_DATA
+ DDRSS2_PHY_437_DATA
+ DDRSS2_PHY_438_DATA
+ DDRSS2_PHY_439_DATA
+ DDRSS2_PHY_440_DATA
+ DDRSS2_PHY_441_DATA
+ DDRSS2_PHY_442_DATA
+ DDRSS2_PHY_443_DATA
+ DDRSS2_PHY_444_DATA
+ DDRSS2_PHY_445_DATA
+ DDRSS2_PHY_446_DATA
+ DDRSS2_PHY_447_DATA
+ DDRSS2_PHY_448_DATA
+ DDRSS2_PHY_449_DATA
+ DDRSS2_PHY_450_DATA
+ DDRSS2_PHY_451_DATA
+ DDRSS2_PHY_452_DATA
+ DDRSS2_PHY_453_DATA
+ DDRSS2_PHY_454_DATA
+ DDRSS2_PHY_455_DATA
+ DDRSS2_PHY_456_DATA
+ DDRSS2_PHY_457_DATA
+ DDRSS2_PHY_458_DATA
+ DDRSS2_PHY_459_DATA
+ DDRSS2_PHY_460_DATA
+ DDRSS2_PHY_461_DATA
+ DDRSS2_PHY_462_DATA
+ DDRSS2_PHY_463_DATA
+ DDRSS2_PHY_464_DATA
+ DDRSS2_PHY_465_DATA
+ DDRSS2_PHY_466_DATA
+ DDRSS2_PHY_467_DATA
+ DDRSS2_PHY_468_DATA
+ DDRSS2_PHY_469_DATA
+ DDRSS2_PHY_470_DATA
+ DDRSS2_PHY_471_DATA
+ DDRSS2_PHY_472_DATA
+ DDRSS2_PHY_473_DATA
+ DDRSS2_PHY_474_DATA
+ DDRSS2_PHY_475_DATA
+ DDRSS2_PHY_476_DATA
+ DDRSS2_PHY_477_DATA
+ DDRSS2_PHY_478_DATA
+ DDRSS2_PHY_479_DATA
+ DDRSS2_PHY_480_DATA
+ DDRSS2_PHY_481_DATA
+ DDRSS2_PHY_482_DATA
+ DDRSS2_PHY_483_DATA
+ DDRSS2_PHY_484_DATA
+ DDRSS2_PHY_485_DATA
+ DDRSS2_PHY_486_DATA
+ DDRSS2_PHY_487_DATA
+ DDRSS2_PHY_488_DATA
+ DDRSS2_PHY_489_DATA
+ DDRSS2_PHY_490_DATA
+ DDRSS2_PHY_491_DATA
+ DDRSS2_PHY_492_DATA
+ DDRSS2_PHY_493_DATA
+ DDRSS2_PHY_494_DATA
+ DDRSS2_PHY_495_DATA
+ DDRSS2_PHY_496_DATA
+ DDRSS2_PHY_497_DATA
+ DDRSS2_PHY_498_DATA
+ DDRSS2_PHY_499_DATA
+ DDRSS2_PHY_500_DATA
+ DDRSS2_PHY_501_DATA
+ DDRSS2_PHY_502_DATA
+ DDRSS2_PHY_503_DATA
+ DDRSS2_PHY_504_DATA
+ DDRSS2_PHY_505_DATA
+ DDRSS2_PHY_506_DATA
+ DDRSS2_PHY_507_DATA
+ DDRSS2_PHY_508_DATA
+ DDRSS2_PHY_509_DATA
+ DDRSS2_PHY_510_DATA
+ DDRSS2_PHY_511_DATA
+ DDRSS2_PHY_512_DATA
+ DDRSS2_PHY_513_DATA
+ DDRSS2_PHY_514_DATA
+ DDRSS2_PHY_515_DATA
+ DDRSS2_PHY_516_DATA
+ DDRSS2_PHY_517_DATA
+ DDRSS2_PHY_518_DATA
+ DDRSS2_PHY_519_DATA
+ DDRSS2_PHY_520_DATA
+ DDRSS2_PHY_521_DATA
+ DDRSS2_PHY_522_DATA
+ DDRSS2_PHY_523_DATA
+ DDRSS2_PHY_524_DATA
+ DDRSS2_PHY_525_DATA
+ DDRSS2_PHY_526_DATA
+ DDRSS2_PHY_527_DATA
+ DDRSS2_PHY_528_DATA
+ DDRSS2_PHY_529_DATA
+ DDRSS2_PHY_530_DATA
+ DDRSS2_PHY_531_DATA
+ DDRSS2_PHY_532_DATA
+ DDRSS2_PHY_533_DATA
+ DDRSS2_PHY_534_DATA
+ DDRSS2_PHY_535_DATA
+ DDRSS2_PHY_536_DATA
+ DDRSS2_PHY_537_DATA
+ DDRSS2_PHY_538_DATA
+ DDRSS2_PHY_539_DATA
+ DDRSS2_PHY_540_DATA
+ DDRSS2_PHY_541_DATA
+ DDRSS2_PHY_542_DATA
+ DDRSS2_PHY_543_DATA
+ DDRSS2_PHY_544_DATA
+ DDRSS2_PHY_545_DATA
+ DDRSS2_PHY_546_DATA
+ DDRSS2_PHY_547_DATA
+ DDRSS2_PHY_548_DATA
+ DDRSS2_PHY_549_DATA
+ DDRSS2_PHY_550_DATA
+ DDRSS2_PHY_551_DATA
+ DDRSS2_PHY_552_DATA
+ DDRSS2_PHY_553_DATA
+ DDRSS2_PHY_554_DATA
+ DDRSS2_PHY_555_DATA
+ DDRSS2_PHY_556_DATA
+ DDRSS2_PHY_557_DATA
+ DDRSS2_PHY_558_DATA
+ DDRSS2_PHY_559_DATA
+ DDRSS2_PHY_560_DATA
+ DDRSS2_PHY_561_DATA
+ DDRSS2_PHY_562_DATA
+ DDRSS2_PHY_563_DATA
+ DDRSS2_PHY_564_DATA
+ DDRSS2_PHY_565_DATA
+ DDRSS2_PHY_566_DATA
+ DDRSS2_PHY_567_DATA
+ DDRSS2_PHY_568_DATA
+ DDRSS2_PHY_569_DATA
+ DDRSS2_PHY_570_DATA
+ DDRSS2_PHY_571_DATA
+ DDRSS2_PHY_572_DATA
+ DDRSS2_PHY_573_DATA
+ DDRSS2_PHY_574_DATA
+ DDRSS2_PHY_575_DATA
+ DDRSS2_PHY_576_DATA
+ DDRSS2_PHY_577_DATA
+ DDRSS2_PHY_578_DATA
+ DDRSS2_PHY_579_DATA
+ DDRSS2_PHY_580_DATA
+ DDRSS2_PHY_581_DATA
+ DDRSS2_PHY_582_DATA
+ DDRSS2_PHY_583_DATA
+ DDRSS2_PHY_584_DATA
+ DDRSS2_PHY_585_DATA
+ DDRSS2_PHY_586_DATA
+ DDRSS2_PHY_587_DATA
+ DDRSS2_PHY_588_DATA
+ DDRSS2_PHY_589_DATA
+ DDRSS2_PHY_590_DATA
+ DDRSS2_PHY_591_DATA
+ DDRSS2_PHY_592_DATA
+ DDRSS2_PHY_593_DATA
+ DDRSS2_PHY_594_DATA
+ DDRSS2_PHY_595_DATA
+ DDRSS2_PHY_596_DATA
+ DDRSS2_PHY_597_DATA
+ DDRSS2_PHY_598_DATA
+ DDRSS2_PHY_599_DATA
+ DDRSS2_PHY_600_DATA
+ DDRSS2_PHY_601_DATA
+ DDRSS2_PHY_602_DATA
+ DDRSS2_PHY_603_DATA
+ DDRSS2_PHY_604_DATA
+ DDRSS2_PHY_605_DATA
+ DDRSS2_PHY_606_DATA
+ DDRSS2_PHY_607_DATA
+ DDRSS2_PHY_608_DATA
+ DDRSS2_PHY_609_DATA
+ DDRSS2_PHY_610_DATA
+ DDRSS2_PHY_611_DATA
+ DDRSS2_PHY_612_DATA
+ DDRSS2_PHY_613_DATA
+ DDRSS2_PHY_614_DATA
+ DDRSS2_PHY_615_DATA
+ DDRSS2_PHY_616_DATA
+ DDRSS2_PHY_617_DATA
+ DDRSS2_PHY_618_DATA
+ DDRSS2_PHY_619_DATA
+ DDRSS2_PHY_620_DATA
+ DDRSS2_PHY_621_DATA
+ DDRSS2_PHY_622_DATA
+ DDRSS2_PHY_623_DATA
+ DDRSS2_PHY_624_DATA
+ DDRSS2_PHY_625_DATA
+ DDRSS2_PHY_626_DATA
+ DDRSS2_PHY_627_DATA
+ DDRSS2_PHY_628_DATA
+ DDRSS2_PHY_629_DATA
+ DDRSS2_PHY_630_DATA
+ DDRSS2_PHY_631_DATA
+ DDRSS2_PHY_632_DATA
+ DDRSS2_PHY_633_DATA
+ DDRSS2_PHY_634_DATA
+ DDRSS2_PHY_635_DATA
+ DDRSS2_PHY_636_DATA
+ DDRSS2_PHY_637_DATA
+ DDRSS2_PHY_638_DATA
+ DDRSS2_PHY_639_DATA
+ DDRSS2_PHY_640_DATA
+ DDRSS2_PHY_641_DATA
+ DDRSS2_PHY_642_DATA
+ DDRSS2_PHY_643_DATA
+ DDRSS2_PHY_644_DATA
+ DDRSS2_PHY_645_DATA
+ DDRSS2_PHY_646_DATA
+ DDRSS2_PHY_647_DATA
+ DDRSS2_PHY_648_DATA
+ DDRSS2_PHY_649_DATA
+ DDRSS2_PHY_650_DATA
+ DDRSS2_PHY_651_DATA
+ DDRSS2_PHY_652_DATA
+ DDRSS2_PHY_653_DATA
+ DDRSS2_PHY_654_DATA
+ DDRSS2_PHY_655_DATA
+ DDRSS2_PHY_656_DATA
+ DDRSS2_PHY_657_DATA
+ DDRSS2_PHY_658_DATA
+ DDRSS2_PHY_659_DATA
+ DDRSS2_PHY_660_DATA
+ DDRSS2_PHY_661_DATA
+ DDRSS2_PHY_662_DATA
+ DDRSS2_PHY_663_DATA
+ DDRSS2_PHY_664_DATA
+ DDRSS2_PHY_665_DATA
+ DDRSS2_PHY_666_DATA
+ DDRSS2_PHY_667_DATA
+ DDRSS2_PHY_668_DATA
+ DDRSS2_PHY_669_DATA
+ DDRSS2_PHY_670_DATA
+ DDRSS2_PHY_671_DATA
+ DDRSS2_PHY_672_DATA
+ DDRSS2_PHY_673_DATA
+ DDRSS2_PHY_674_DATA
+ DDRSS2_PHY_675_DATA
+ DDRSS2_PHY_676_DATA
+ DDRSS2_PHY_677_DATA
+ DDRSS2_PHY_678_DATA
+ DDRSS2_PHY_679_DATA
+ DDRSS2_PHY_680_DATA
+ DDRSS2_PHY_681_DATA
+ DDRSS2_PHY_682_DATA
+ DDRSS2_PHY_683_DATA
+ DDRSS2_PHY_684_DATA
+ DDRSS2_PHY_685_DATA
+ DDRSS2_PHY_686_DATA
+ DDRSS2_PHY_687_DATA
+ DDRSS2_PHY_688_DATA
+ DDRSS2_PHY_689_DATA
+ DDRSS2_PHY_690_DATA
+ DDRSS2_PHY_691_DATA
+ DDRSS2_PHY_692_DATA
+ DDRSS2_PHY_693_DATA
+ DDRSS2_PHY_694_DATA
+ DDRSS2_PHY_695_DATA
+ DDRSS2_PHY_696_DATA
+ DDRSS2_PHY_697_DATA
+ DDRSS2_PHY_698_DATA
+ DDRSS2_PHY_699_DATA
+ DDRSS2_PHY_700_DATA
+ DDRSS2_PHY_701_DATA
+ DDRSS2_PHY_702_DATA
+ DDRSS2_PHY_703_DATA
+ DDRSS2_PHY_704_DATA
+ DDRSS2_PHY_705_DATA
+ DDRSS2_PHY_706_DATA
+ DDRSS2_PHY_707_DATA
+ DDRSS2_PHY_708_DATA
+ DDRSS2_PHY_709_DATA
+ DDRSS2_PHY_710_DATA
+ DDRSS2_PHY_711_DATA
+ DDRSS2_PHY_712_DATA
+ DDRSS2_PHY_713_DATA
+ DDRSS2_PHY_714_DATA
+ DDRSS2_PHY_715_DATA
+ DDRSS2_PHY_716_DATA
+ DDRSS2_PHY_717_DATA
+ DDRSS2_PHY_718_DATA
+ DDRSS2_PHY_719_DATA
+ DDRSS2_PHY_720_DATA
+ DDRSS2_PHY_721_DATA
+ DDRSS2_PHY_722_DATA
+ DDRSS2_PHY_723_DATA
+ DDRSS2_PHY_724_DATA
+ DDRSS2_PHY_725_DATA
+ DDRSS2_PHY_726_DATA
+ DDRSS2_PHY_727_DATA
+ DDRSS2_PHY_728_DATA
+ DDRSS2_PHY_729_DATA
+ DDRSS2_PHY_730_DATA
+ DDRSS2_PHY_731_DATA
+ DDRSS2_PHY_732_DATA
+ DDRSS2_PHY_733_DATA
+ DDRSS2_PHY_734_DATA
+ DDRSS2_PHY_735_DATA
+ DDRSS2_PHY_736_DATA
+ DDRSS2_PHY_737_DATA
+ DDRSS2_PHY_738_DATA
+ DDRSS2_PHY_739_DATA
+ DDRSS2_PHY_740_DATA
+ DDRSS2_PHY_741_DATA
+ DDRSS2_PHY_742_DATA
+ DDRSS2_PHY_743_DATA
+ DDRSS2_PHY_744_DATA
+ DDRSS2_PHY_745_DATA
+ DDRSS2_PHY_746_DATA
+ DDRSS2_PHY_747_DATA
+ DDRSS2_PHY_748_DATA
+ DDRSS2_PHY_749_DATA
+ DDRSS2_PHY_750_DATA
+ DDRSS2_PHY_751_DATA
+ DDRSS2_PHY_752_DATA
+ DDRSS2_PHY_753_DATA
+ DDRSS2_PHY_754_DATA
+ DDRSS2_PHY_755_DATA
+ DDRSS2_PHY_756_DATA
+ DDRSS2_PHY_757_DATA
+ DDRSS2_PHY_758_DATA
+ DDRSS2_PHY_759_DATA
+ DDRSS2_PHY_760_DATA
+ DDRSS2_PHY_761_DATA
+ DDRSS2_PHY_762_DATA
+ DDRSS2_PHY_763_DATA
+ DDRSS2_PHY_764_DATA
+ DDRSS2_PHY_765_DATA
+ DDRSS2_PHY_766_DATA
+ DDRSS2_PHY_767_DATA
+ DDRSS2_PHY_768_DATA
+ DDRSS2_PHY_769_DATA
+ DDRSS2_PHY_770_DATA
+ DDRSS2_PHY_771_DATA
+ DDRSS2_PHY_772_DATA
+ DDRSS2_PHY_773_DATA
+ DDRSS2_PHY_774_DATA
+ DDRSS2_PHY_775_DATA
+ DDRSS2_PHY_776_DATA
+ DDRSS2_PHY_777_DATA
+ DDRSS2_PHY_778_DATA
+ DDRSS2_PHY_779_DATA
+ DDRSS2_PHY_780_DATA
+ DDRSS2_PHY_781_DATA
+ DDRSS2_PHY_782_DATA
+ DDRSS2_PHY_783_DATA
+ DDRSS2_PHY_784_DATA
+ DDRSS2_PHY_785_DATA
+ DDRSS2_PHY_786_DATA
+ DDRSS2_PHY_787_DATA
+ DDRSS2_PHY_788_DATA
+ DDRSS2_PHY_789_DATA
+ DDRSS2_PHY_790_DATA
+ DDRSS2_PHY_791_DATA
+ DDRSS2_PHY_792_DATA
+ DDRSS2_PHY_793_DATA
+ DDRSS2_PHY_794_DATA
+ DDRSS2_PHY_795_DATA
+ DDRSS2_PHY_796_DATA
+ DDRSS2_PHY_797_DATA
+ DDRSS2_PHY_798_DATA
+ DDRSS2_PHY_799_DATA
+ DDRSS2_PHY_800_DATA
+ DDRSS2_PHY_801_DATA
+ DDRSS2_PHY_802_DATA
+ DDRSS2_PHY_803_DATA
+ DDRSS2_PHY_804_DATA
+ DDRSS2_PHY_805_DATA
+ DDRSS2_PHY_806_DATA
+ DDRSS2_PHY_807_DATA
+ DDRSS2_PHY_808_DATA
+ DDRSS2_PHY_809_DATA
+ DDRSS2_PHY_810_DATA
+ DDRSS2_PHY_811_DATA
+ DDRSS2_PHY_812_DATA
+ DDRSS2_PHY_813_DATA
+ DDRSS2_PHY_814_DATA
+ DDRSS2_PHY_815_DATA
+ DDRSS2_PHY_816_DATA
+ DDRSS2_PHY_817_DATA
+ DDRSS2_PHY_818_DATA
+ DDRSS2_PHY_819_DATA
+ DDRSS2_PHY_820_DATA
+ DDRSS2_PHY_821_DATA
+ DDRSS2_PHY_822_DATA
+ DDRSS2_PHY_823_DATA
+ DDRSS2_PHY_824_DATA
+ DDRSS2_PHY_825_DATA
+ DDRSS2_PHY_826_DATA
+ DDRSS2_PHY_827_DATA
+ DDRSS2_PHY_828_DATA
+ DDRSS2_PHY_829_DATA
+ DDRSS2_PHY_830_DATA
+ DDRSS2_PHY_831_DATA
+ DDRSS2_PHY_832_DATA
+ DDRSS2_PHY_833_DATA
+ DDRSS2_PHY_834_DATA
+ DDRSS2_PHY_835_DATA
+ DDRSS2_PHY_836_DATA
+ DDRSS2_PHY_837_DATA
+ DDRSS2_PHY_838_DATA
+ DDRSS2_PHY_839_DATA
+ DDRSS2_PHY_840_DATA
+ DDRSS2_PHY_841_DATA
+ DDRSS2_PHY_842_DATA
+ DDRSS2_PHY_843_DATA
+ DDRSS2_PHY_844_DATA
+ DDRSS2_PHY_845_DATA
+ DDRSS2_PHY_846_DATA
+ DDRSS2_PHY_847_DATA
+ DDRSS2_PHY_848_DATA
+ DDRSS2_PHY_849_DATA
+ DDRSS2_PHY_850_DATA
+ DDRSS2_PHY_851_DATA
+ DDRSS2_PHY_852_DATA
+ DDRSS2_PHY_853_DATA
+ DDRSS2_PHY_854_DATA
+ DDRSS2_PHY_855_DATA
+ DDRSS2_PHY_856_DATA
+ DDRSS2_PHY_857_DATA
+ DDRSS2_PHY_858_DATA
+ DDRSS2_PHY_859_DATA
+ DDRSS2_PHY_860_DATA
+ DDRSS2_PHY_861_DATA
+ DDRSS2_PHY_862_DATA
+ DDRSS2_PHY_863_DATA
+ DDRSS2_PHY_864_DATA
+ DDRSS2_PHY_865_DATA
+ DDRSS2_PHY_866_DATA
+ DDRSS2_PHY_867_DATA
+ DDRSS2_PHY_868_DATA
+ DDRSS2_PHY_869_DATA
+ DDRSS2_PHY_870_DATA
+ DDRSS2_PHY_871_DATA
+ DDRSS2_PHY_872_DATA
+ DDRSS2_PHY_873_DATA
+ DDRSS2_PHY_874_DATA
+ DDRSS2_PHY_875_DATA
+ DDRSS2_PHY_876_DATA
+ DDRSS2_PHY_877_DATA
+ DDRSS2_PHY_878_DATA
+ DDRSS2_PHY_879_DATA
+ DDRSS2_PHY_880_DATA
+ DDRSS2_PHY_881_DATA
+ DDRSS2_PHY_882_DATA
+ DDRSS2_PHY_883_DATA
+ DDRSS2_PHY_884_DATA
+ DDRSS2_PHY_885_DATA
+ DDRSS2_PHY_886_DATA
+ DDRSS2_PHY_887_DATA
+ DDRSS2_PHY_888_DATA
+ DDRSS2_PHY_889_DATA
+ DDRSS2_PHY_890_DATA
+ DDRSS2_PHY_891_DATA
+ DDRSS2_PHY_892_DATA
+ DDRSS2_PHY_893_DATA
+ DDRSS2_PHY_894_DATA
+ DDRSS2_PHY_895_DATA
+ DDRSS2_PHY_896_DATA
+ DDRSS2_PHY_897_DATA
+ DDRSS2_PHY_898_DATA
+ DDRSS2_PHY_899_DATA
+ DDRSS2_PHY_900_DATA
+ DDRSS2_PHY_901_DATA
+ DDRSS2_PHY_902_DATA
+ DDRSS2_PHY_903_DATA
+ DDRSS2_PHY_904_DATA
+ DDRSS2_PHY_905_DATA
+ DDRSS2_PHY_906_DATA
+ DDRSS2_PHY_907_DATA
+ DDRSS2_PHY_908_DATA
+ DDRSS2_PHY_909_DATA
+ DDRSS2_PHY_910_DATA
+ DDRSS2_PHY_911_DATA
+ DDRSS2_PHY_912_DATA
+ DDRSS2_PHY_913_DATA
+ DDRSS2_PHY_914_DATA
+ DDRSS2_PHY_915_DATA
+ DDRSS2_PHY_916_DATA
+ DDRSS2_PHY_917_DATA
+ DDRSS2_PHY_918_DATA
+ DDRSS2_PHY_919_DATA
+ DDRSS2_PHY_920_DATA
+ DDRSS2_PHY_921_DATA
+ DDRSS2_PHY_922_DATA
+ DDRSS2_PHY_923_DATA
+ DDRSS2_PHY_924_DATA
+ DDRSS2_PHY_925_DATA
+ DDRSS2_PHY_926_DATA
+ DDRSS2_PHY_927_DATA
+ DDRSS2_PHY_928_DATA
+ DDRSS2_PHY_929_DATA
+ DDRSS2_PHY_930_DATA
+ DDRSS2_PHY_931_DATA
+ DDRSS2_PHY_932_DATA
+ DDRSS2_PHY_933_DATA
+ DDRSS2_PHY_934_DATA
+ DDRSS2_PHY_935_DATA
+ DDRSS2_PHY_936_DATA
+ DDRSS2_PHY_937_DATA
+ DDRSS2_PHY_938_DATA
+ DDRSS2_PHY_939_DATA
+ DDRSS2_PHY_940_DATA
+ DDRSS2_PHY_941_DATA
+ DDRSS2_PHY_942_DATA
+ DDRSS2_PHY_943_DATA
+ DDRSS2_PHY_944_DATA
+ DDRSS2_PHY_945_DATA
+ DDRSS2_PHY_946_DATA
+ DDRSS2_PHY_947_DATA
+ DDRSS2_PHY_948_DATA
+ DDRSS2_PHY_949_DATA
+ DDRSS2_PHY_950_DATA
+ DDRSS2_PHY_951_DATA
+ DDRSS2_PHY_952_DATA
+ DDRSS2_PHY_953_DATA
+ DDRSS2_PHY_954_DATA
+ DDRSS2_PHY_955_DATA
+ DDRSS2_PHY_956_DATA
+ DDRSS2_PHY_957_DATA
+ DDRSS2_PHY_958_DATA
+ DDRSS2_PHY_959_DATA
+ DDRSS2_PHY_960_DATA
+ DDRSS2_PHY_961_DATA
+ DDRSS2_PHY_962_DATA
+ DDRSS2_PHY_963_DATA
+ DDRSS2_PHY_964_DATA
+ DDRSS2_PHY_965_DATA
+ DDRSS2_PHY_966_DATA
+ DDRSS2_PHY_967_DATA
+ DDRSS2_PHY_968_DATA
+ DDRSS2_PHY_969_DATA
+ DDRSS2_PHY_970_DATA
+ DDRSS2_PHY_971_DATA
+ DDRSS2_PHY_972_DATA
+ DDRSS2_PHY_973_DATA
+ DDRSS2_PHY_974_DATA
+ DDRSS2_PHY_975_DATA
+ DDRSS2_PHY_976_DATA
+ DDRSS2_PHY_977_DATA
+ DDRSS2_PHY_978_DATA
+ DDRSS2_PHY_979_DATA
+ DDRSS2_PHY_980_DATA
+ DDRSS2_PHY_981_DATA
+ DDRSS2_PHY_982_DATA
+ DDRSS2_PHY_983_DATA
+ DDRSS2_PHY_984_DATA
+ DDRSS2_PHY_985_DATA
+ DDRSS2_PHY_986_DATA
+ DDRSS2_PHY_987_DATA
+ DDRSS2_PHY_988_DATA
+ DDRSS2_PHY_989_DATA
+ DDRSS2_PHY_990_DATA
+ DDRSS2_PHY_991_DATA
+ DDRSS2_PHY_992_DATA
+ DDRSS2_PHY_993_DATA
+ DDRSS2_PHY_994_DATA
+ DDRSS2_PHY_995_DATA
+ DDRSS2_PHY_996_DATA
+ DDRSS2_PHY_997_DATA
+ DDRSS2_PHY_998_DATA
+ DDRSS2_PHY_999_DATA
+ DDRSS2_PHY_1000_DATA
+ DDRSS2_PHY_1001_DATA
+ DDRSS2_PHY_1002_DATA
+ DDRSS2_PHY_1003_DATA
+ DDRSS2_PHY_1004_DATA
+ DDRSS2_PHY_1005_DATA
+ DDRSS2_PHY_1006_DATA
+ DDRSS2_PHY_1007_DATA
+ DDRSS2_PHY_1008_DATA
+ DDRSS2_PHY_1009_DATA
+ DDRSS2_PHY_1010_DATA
+ DDRSS2_PHY_1011_DATA
+ DDRSS2_PHY_1012_DATA
+ DDRSS2_PHY_1013_DATA
+ DDRSS2_PHY_1014_DATA
+ DDRSS2_PHY_1015_DATA
+ DDRSS2_PHY_1016_DATA
+ DDRSS2_PHY_1017_DATA
+ DDRSS2_PHY_1018_DATA
+ DDRSS2_PHY_1019_DATA
+ DDRSS2_PHY_1020_DATA
+ DDRSS2_PHY_1021_DATA
+ DDRSS2_PHY_1022_DATA
+ DDRSS2_PHY_1023_DATA
+ DDRSS2_PHY_1024_DATA
+ DDRSS2_PHY_1025_DATA
+ DDRSS2_PHY_1026_DATA
+ DDRSS2_PHY_1027_DATA
+ DDRSS2_PHY_1028_DATA
+ DDRSS2_PHY_1029_DATA
+ DDRSS2_PHY_1030_DATA
+ DDRSS2_PHY_1031_DATA
+ DDRSS2_PHY_1032_DATA
+ DDRSS2_PHY_1033_DATA
+ DDRSS2_PHY_1034_DATA
+ DDRSS2_PHY_1035_DATA
+ DDRSS2_PHY_1036_DATA
+ DDRSS2_PHY_1037_DATA
+ DDRSS2_PHY_1038_DATA
+ DDRSS2_PHY_1039_DATA
+ DDRSS2_PHY_1040_DATA
+ DDRSS2_PHY_1041_DATA
+ DDRSS2_PHY_1042_DATA
+ DDRSS2_PHY_1043_DATA
+ DDRSS2_PHY_1044_DATA
+ DDRSS2_PHY_1045_DATA
+ DDRSS2_PHY_1046_DATA
+ DDRSS2_PHY_1047_DATA
+ DDRSS2_PHY_1048_DATA
+ DDRSS2_PHY_1049_DATA
+ DDRSS2_PHY_1050_DATA
+ DDRSS2_PHY_1051_DATA
+ DDRSS2_PHY_1052_DATA
+ DDRSS2_PHY_1053_DATA
+ DDRSS2_PHY_1054_DATA
+ DDRSS2_PHY_1055_DATA
+ DDRSS2_PHY_1056_DATA
+ DDRSS2_PHY_1057_DATA
+ DDRSS2_PHY_1058_DATA
+ DDRSS2_PHY_1059_DATA
+ DDRSS2_PHY_1060_DATA
+ DDRSS2_PHY_1061_DATA
+ DDRSS2_PHY_1062_DATA
+ DDRSS2_PHY_1063_DATA
+ DDRSS2_PHY_1064_DATA
+ DDRSS2_PHY_1065_DATA
+ DDRSS2_PHY_1066_DATA
+ DDRSS2_PHY_1067_DATA
+ DDRSS2_PHY_1068_DATA
+ DDRSS2_PHY_1069_DATA
+ DDRSS2_PHY_1070_DATA
+ DDRSS2_PHY_1071_DATA
+ DDRSS2_PHY_1072_DATA
+ DDRSS2_PHY_1073_DATA
+ DDRSS2_PHY_1074_DATA
+ DDRSS2_PHY_1075_DATA
+ DDRSS2_PHY_1076_DATA
+ DDRSS2_PHY_1077_DATA
+ DDRSS2_PHY_1078_DATA
+ DDRSS2_PHY_1079_DATA
+ DDRSS2_PHY_1080_DATA
+ DDRSS2_PHY_1081_DATA
+ DDRSS2_PHY_1082_DATA
+ DDRSS2_PHY_1083_DATA
+ DDRSS2_PHY_1084_DATA
+ DDRSS2_PHY_1085_DATA
+ DDRSS2_PHY_1086_DATA
+ DDRSS2_PHY_1087_DATA
+ DDRSS2_PHY_1088_DATA
+ DDRSS2_PHY_1089_DATA
+ DDRSS2_PHY_1090_DATA
+ DDRSS2_PHY_1091_DATA
+ DDRSS2_PHY_1092_DATA
+ DDRSS2_PHY_1093_DATA
+ DDRSS2_PHY_1094_DATA
+ DDRSS2_PHY_1095_DATA
+ DDRSS2_PHY_1096_DATA
+ DDRSS2_PHY_1097_DATA
+ DDRSS2_PHY_1098_DATA
+ DDRSS2_PHY_1099_DATA
+ DDRSS2_PHY_1100_DATA
+ DDRSS2_PHY_1101_DATA
+ DDRSS2_PHY_1102_DATA
+ DDRSS2_PHY_1103_DATA
+ DDRSS2_PHY_1104_DATA
+ DDRSS2_PHY_1105_DATA
+ DDRSS2_PHY_1106_DATA
+ DDRSS2_PHY_1107_DATA
+ DDRSS2_PHY_1108_DATA
+ DDRSS2_PHY_1109_DATA
+ DDRSS2_PHY_1110_DATA
+ DDRSS2_PHY_1111_DATA
+ DDRSS2_PHY_1112_DATA
+ DDRSS2_PHY_1113_DATA
+ DDRSS2_PHY_1114_DATA
+ DDRSS2_PHY_1115_DATA
+ DDRSS2_PHY_1116_DATA
+ DDRSS2_PHY_1117_DATA
+ DDRSS2_PHY_1118_DATA
+ DDRSS2_PHY_1119_DATA
+ DDRSS2_PHY_1120_DATA
+ DDRSS2_PHY_1121_DATA
+ DDRSS2_PHY_1122_DATA
+ DDRSS2_PHY_1123_DATA
+ DDRSS2_PHY_1124_DATA
+ DDRSS2_PHY_1125_DATA
+ DDRSS2_PHY_1126_DATA
+ DDRSS2_PHY_1127_DATA
+ DDRSS2_PHY_1128_DATA
+ DDRSS2_PHY_1129_DATA
+ DDRSS2_PHY_1130_DATA
+ DDRSS2_PHY_1131_DATA
+ DDRSS2_PHY_1132_DATA
+ DDRSS2_PHY_1133_DATA
+ DDRSS2_PHY_1134_DATA
+ DDRSS2_PHY_1135_DATA
+ DDRSS2_PHY_1136_DATA
+ DDRSS2_PHY_1137_DATA
+ DDRSS2_PHY_1138_DATA
+ DDRSS2_PHY_1139_DATA
+ DDRSS2_PHY_1140_DATA
+ DDRSS2_PHY_1141_DATA
+ DDRSS2_PHY_1142_DATA
+ DDRSS2_PHY_1143_DATA
+ DDRSS2_PHY_1144_DATA
+ DDRSS2_PHY_1145_DATA
+ DDRSS2_PHY_1146_DATA
+ DDRSS2_PHY_1147_DATA
+ DDRSS2_PHY_1148_DATA
+ DDRSS2_PHY_1149_DATA
+ DDRSS2_PHY_1150_DATA
+ DDRSS2_PHY_1151_DATA
+ DDRSS2_PHY_1152_DATA
+ DDRSS2_PHY_1153_DATA
+ DDRSS2_PHY_1154_DATA
+ DDRSS2_PHY_1155_DATA
+ DDRSS2_PHY_1156_DATA
+ DDRSS2_PHY_1157_DATA
+ DDRSS2_PHY_1158_DATA
+ DDRSS2_PHY_1159_DATA
+ DDRSS2_PHY_1160_DATA
+ DDRSS2_PHY_1161_DATA
+ DDRSS2_PHY_1162_DATA
+ DDRSS2_PHY_1163_DATA
+ DDRSS2_PHY_1164_DATA
+ DDRSS2_PHY_1165_DATA
+ DDRSS2_PHY_1166_DATA
+ DDRSS2_PHY_1167_DATA
+ DDRSS2_PHY_1168_DATA
+ DDRSS2_PHY_1169_DATA
+ DDRSS2_PHY_1170_DATA
+ DDRSS2_PHY_1171_DATA
+ DDRSS2_PHY_1172_DATA
+ DDRSS2_PHY_1173_DATA
+ DDRSS2_PHY_1174_DATA
+ DDRSS2_PHY_1175_DATA
+ DDRSS2_PHY_1176_DATA
+ DDRSS2_PHY_1177_DATA
+ DDRSS2_PHY_1178_DATA
+ DDRSS2_PHY_1179_DATA
+ DDRSS2_PHY_1180_DATA
+ DDRSS2_PHY_1181_DATA
+ DDRSS2_PHY_1182_DATA
+ DDRSS2_PHY_1183_DATA
+ DDRSS2_PHY_1184_DATA
+ DDRSS2_PHY_1185_DATA
+ DDRSS2_PHY_1186_DATA
+ DDRSS2_PHY_1187_DATA
+ DDRSS2_PHY_1188_DATA
+ DDRSS2_PHY_1189_DATA
+ DDRSS2_PHY_1190_DATA
+ DDRSS2_PHY_1191_DATA
+ DDRSS2_PHY_1192_DATA
+ DDRSS2_PHY_1193_DATA
+ DDRSS2_PHY_1194_DATA
+ DDRSS2_PHY_1195_DATA
+ DDRSS2_PHY_1196_DATA
+ DDRSS2_PHY_1197_DATA
+ DDRSS2_PHY_1198_DATA
+ DDRSS2_PHY_1199_DATA
+ DDRSS2_PHY_1200_DATA
+ DDRSS2_PHY_1201_DATA
+ DDRSS2_PHY_1202_DATA
+ DDRSS2_PHY_1203_DATA
+ DDRSS2_PHY_1204_DATA
+ DDRSS2_PHY_1205_DATA
+ DDRSS2_PHY_1206_DATA
+ DDRSS2_PHY_1207_DATA
+ DDRSS2_PHY_1208_DATA
+ DDRSS2_PHY_1209_DATA
+ DDRSS2_PHY_1210_DATA
+ DDRSS2_PHY_1211_DATA
+ DDRSS2_PHY_1212_DATA
+ DDRSS2_PHY_1213_DATA
+ DDRSS2_PHY_1214_DATA
+ DDRSS2_PHY_1215_DATA
+ DDRSS2_PHY_1216_DATA
+ DDRSS2_PHY_1217_DATA
+ DDRSS2_PHY_1218_DATA
+ DDRSS2_PHY_1219_DATA
+ DDRSS2_PHY_1220_DATA
+ DDRSS2_PHY_1221_DATA
+ DDRSS2_PHY_1222_DATA
+ DDRSS2_PHY_1223_DATA
+ DDRSS2_PHY_1224_DATA
+ DDRSS2_PHY_1225_DATA
+ DDRSS2_PHY_1226_DATA
+ DDRSS2_PHY_1227_DATA
+ DDRSS2_PHY_1228_DATA
+ DDRSS2_PHY_1229_DATA
+ DDRSS2_PHY_1230_DATA
+ DDRSS2_PHY_1231_DATA
+ DDRSS2_PHY_1232_DATA
+ DDRSS2_PHY_1233_DATA
+ DDRSS2_PHY_1234_DATA
+ DDRSS2_PHY_1235_DATA
+ DDRSS2_PHY_1236_DATA
+ DDRSS2_PHY_1237_DATA
+ DDRSS2_PHY_1238_DATA
+ DDRSS2_PHY_1239_DATA
+ DDRSS2_PHY_1240_DATA
+ DDRSS2_PHY_1241_DATA
+ DDRSS2_PHY_1242_DATA
+ DDRSS2_PHY_1243_DATA
+ DDRSS2_PHY_1244_DATA
+ DDRSS2_PHY_1245_DATA
+ DDRSS2_PHY_1246_DATA
+ DDRSS2_PHY_1247_DATA
+ DDRSS2_PHY_1248_DATA
+ DDRSS2_PHY_1249_DATA
+ DDRSS2_PHY_1250_DATA
+ DDRSS2_PHY_1251_DATA
+ DDRSS2_PHY_1252_DATA
+ DDRSS2_PHY_1253_DATA
+ DDRSS2_PHY_1254_DATA
+ DDRSS2_PHY_1255_DATA
+ DDRSS2_PHY_1256_DATA
+ DDRSS2_PHY_1257_DATA
+ DDRSS2_PHY_1258_DATA
+ DDRSS2_PHY_1259_DATA
+ DDRSS2_PHY_1260_DATA
+ DDRSS2_PHY_1261_DATA
+ DDRSS2_PHY_1262_DATA
+ DDRSS2_PHY_1263_DATA
+ DDRSS2_PHY_1264_DATA
+ DDRSS2_PHY_1265_DATA
+ DDRSS2_PHY_1266_DATA
+ DDRSS2_PHY_1267_DATA
+ DDRSS2_PHY_1268_DATA
+ DDRSS2_PHY_1269_DATA
+ DDRSS2_PHY_1270_DATA
+ DDRSS2_PHY_1271_DATA
+ DDRSS2_PHY_1272_DATA
+ DDRSS2_PHY_1273_DATA
+ DDRSS2_PHY_1274_DATA
+ DDRSS2_PHY_1275_DATA
+ DDRSS2_PHY_1276_DATA
+ DDRSS2_PHY_1277_DATA
+ DDRSS2_PHY_1278_DATA
+ DDRSS2_PHY_1279_DATA
+ DDRSS2_PHY_1280_DATA
+ DDRSS2_PHY_1281_DATA
+ DDRSS2_PHY_1282_DATA
+ DDRSS2_PHY_1283_DATA
+ DDRSS2_PHY_1284_DATA
+ DDRSS2_PHY_1285_DATA
+ DDRSS2_PHY_1286_DATA
+ DDRSS2_PHY_1287_DATA
+ DDRSS2_PHY_1288_DATA
+ DDRSS2_PHY_1289_DATA
+ DDRSS2_PHY_1290_DATA
+ DDRSS2_PHY_1291_DATA
+ DDRSS2_PHY_1292_DATA
+ DDRSS2_PHY_1293_DATA
+ DDRSS2_PHY_1294_DATA
+ DDRSS2_PHY_1295_DATA
+ DDRSS2_PHY_1296_DATA
+ DDRSS2_PHY_1297_DATA
+ DDRSS2_PHY_1298_DATA
+ DDRSS2_PHY_1299_DATA
+ DDRSS2_PHY_1300_DATA
+ DDRSS2_PHY_1301_DATA
+ DDRSS2_PHY_1302_DATA
+ DDRSS2_PHY_1303_DATA
+ DDRSS2_PHY_1304_DATA
+ DDRSS2_PHY_1305_DATA
+ DDRSS2_PHY_1306_DATA
+ DDRSS2_PHY_1307_DATA
+ DDRSS2_PHY_1308_DATA
+ DDRSS2_PHY_1309_DATA
+ DDRSS2_PHY_1310_DATA
+ DDRSS2_PHY_1311_DATA
+ DDRSS2_PHY_1312_DATA
+ DDRSS2_PHY_1313_DATA
+ DDRSS2_PHY_1314_DATA
+ DDRSS2_PHY_1315_DATA
+ DDRSS2_PHY_1316_DATA
+ DDRSS2_PHY_1317_DATA
+ DDRSS2_PHY_1318_DATA
+ DDRSS2_PHY_1319_DATA
+ DDRSS2_PHY_1320_DATA
+ DDRSS2_PHY_1321_DATA
+ DDRSS2_PHY_1322_DATA
+ DDRSS2_PHY_1323_DATA
+ DDRSS2_PHY_1324_DATA
+ DDRSS2_PHY_1325_DATA
+ DDRSS2_PHY_1326_DATA
+ DDRSS2_PHY_1327_DATA
+ DDRSS2_PHY_1328_DATA
+ DDRSS2_PHY_1329_DATA
+ DDRSS2_PHY_1330_DATA
+ DDRSS2_PHY_1331_DATA
+ DDRSS2_PHY_1332_DATA
+ DDRSS2_PHY_1333_DATA
+ DDRSS2_PHY_1334_DATA
+ DDRSS2_PHY_1335_DATA
+ DDRSS2_PHY_1336_DATA
+ DDRSS2_PHY_1337_DATA
+ DDRSS2_PHY_1338_DATA
+ DDRSS2_PHY_1339_DATA
+ DDRSS2_PHY_1340_DATA
+ DDRSS2_PHY_1341_DATA
+ DDRSS2_PHY_1342_DATA
+ DDRSS2_PHY_1343_DATA
+ DDRSS2_PHY_1344_DATA
+ DDRSS2_PHY_1345_DATA
+ DDRSS2_PHY_1346_DATA
+ DDRSS2_PHY_1347_DATA
+ DDRSS2_PHY_1348_DATA
+ DDRSS2_PHY_1349_DATA
+ DDRSS2_PHY_1350_DATA
+ DDRSS2_PHY_1351_DATA
+ DDRSS2_PHY_1352_DATA
+ DDRSS2_PHY_1353_DATA
+ DDRSS2_PHY_1354_DATA
+ DDRSS2_PHY_1355_DATA
+ DDRSS2_PHY_1356_DATA
+ DDRSS2_PHY_1357_DATA
+ DDRSS2_PHY_1358_DATA
+ DDRSS2_PHY_1359_DATA
+ DDRSS2_PHY_1360_DATA
+ DDRSS2_PHY_1361_DATA
+ DDRSS2_PHY_1362_DATA
+ DDRSS2_PHY_1363_DATA
+ DDRSS2_PHY_1364_DATA
+ DDRSS2_PHY_1365_DATA
+ DDRSS2_PHY_1366_DATA
+ DDRSS2_PHY_1367_DATA
+ DDRSS2_PHY_1368_DATA
+ DDRSS2_PHY_1369_DATA
+ DDRSS2_PHY_1370_DATA
+ DDRSS2_PHY_1371_DATA
+ DDRSS2_PHY_1372_DATA
+ DDRSS2_PHY_1373_DATA
+ DDRSS2_PHY_1374_DATA
+ DDRSS2_PHY_1375_DATA
+ DDRSS2_PHY_1376_DATA
+ DDRSS2_PHY_1377_DATA
+ DDRSS2_PHY_1378_DATA
+ DDRSS2_PHY_1379_DATA
+ DDRSS2_PHY_1380_DATA
+ DDRSS2_PHY_1381_DATA
+ DDRSS2_PHY_1382_DATA
+ DDRSS2_PHY_1383_DATA
+ DDRSS2_PHY_1384_DATA
+ DDRSS2_PHY_1385_DATA
+ DDRSS2_PHY_1386_DATA
+ DDRSS2_PHY_1387_DATA
+ DDRSS2_PHY_1388_DATA
+ DDRSS2_PHY_1389_DATA
+ DDRSS2_PHY_1390_DATA
+ DDRSS2_PHY_1391_DATA
+ DDRSS2_PHY_1392_DATA
+ DDRSS2_PHY_1393_DATA
+ DDRSS2_PHY_1394_DATA
+ DDRSS2_PHY_1395_DATA
+ DDRSS2_PHY_1396_DATA
+ DDRSS2_PHY_1397_DATA
+ DDRSS2_PHY_1398_DATA
+ DDRSS2_PHY_1399_DATA
+ DDRSS2_PHY_1400_DATA
+ DDRSS2_PHY_1401_DATA
+ DDRSS2_PHY_1402_DATA
+ DDRSS2_PHY_1403_DATA
+ DDRSS2_PHY_1404_DATA
+ DDRSS2_PHY_1405_DATA
+ DDRSS2_PHY_1406_DATA
+ DDRSS2_PHY_1407_DATA
+ DDRSS2_PHY_1408_DATA
+ DDRSS2_PHY_1409_DATA
+ DDRSS2_PHY_1410_DATA
+ DDRSS2_PHY_1411_DATA
+ DDRSS2_PHY_1412_DATA
+ DDRSS2_PHY_1413_DATA
+ DDRSS2_PHY_1414_DATA
+ DDRSS2_PHY_1415_DATA
+ DDRSS2_PHY_1416_DATA
+ DDRSS2_PHY_1417_DATA
+ DDRSS2_PHY_1418_DATA
+ DDRSS2_PHY_1419_DATA
+ DDRSS2_PHY_1420_DATA
+ DDRSS2_PHY_1421_DATA
+ DDRSS2_PHY_1422_DATA
+ >;
+ };
+
+ memorycontroller3: memorycontroller@29f0000 {
+ compatible = "ti,j721s2-ddrss";
+ reg = <0x0 0x029f0000 0x0 0x4000>,
+ <0x0 0x0114000 0x0 0x100>;
+ reg-names = "cfg", "ctrl_mmr_lp4";
+ power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
+ <&k3_pds 139 TI_SCI_PD_SHARED>;
+ clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;
+ ti,ddr-freq0 = <DDRSS_PLL_FREQUENCY_0>;
+ ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+ ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+ ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+ instance = <3>;
+
+ u-boot,dm-spl;
+
+ ti,ctl-data = <
+ DDRSS3_CTL_00_DATA
+ DDRSS3_CTL_01_DATA
+ DDRSS3_CTL_02_DATA
+ DDRSS3_CTL_03_DATA
+ DDRSS3_CTL_04_DATA
+ DDRSS3_CTL_05_DATA
+ DDRSS3_CTL_06_DATA
+ DDRSS3_CTL_07_DATA
+ DDRSS3_CTL_08_DATA
+ DDRSS3_CTL_09_DATA
+ DDRSS3_CTL_10_DATA
+ DDRSS3_CTL_11_DATA
+ DDRSS3_CTL_12_DATA
+ DDRSS3_CTL_13_DATA
+ DDRSS3_CTL_14_DATA
+ DDRSS3_CTL_15_DATA
+ DDRSS3_CTL_16_DATA
+ DDRSS3_CTL_17_DATA
+ DDRSS3_CTL_18_DATA
+ DDRSS3_CTL_19_DATA
+ DDRSS3_CTL_20_DATA
+ DDRSS3_CTL_21_DATA
+ DDRSS3_CTL_22_DATA
+ DDRSS3_CTL_23_DATA
+ DDRSS3_CTL_24_DATA
+ DDRSS3_CTL_25_DATA
+ DDRSS3_CTL_26_DATA
+ DDRSS3_CTL_27_DATA
+ DDRSS3_CTL_28_DATA
+ DDRSS3_CTL_29_DATA
+ DDRSS3_CTL_30_DATA
+ DDRSS3_CTL_31_DATA
+ DDRSS3_CTL_32_DATA
+ DDRSS3_CTL_33_DATA
+ DDRSS3_CTL_34_DATA
+ DDRSS3_CTL_35_DATA
+ DDRSS3_CTL_36_DATA
+ DDRSS3_CTL_37_DATA
+ DDRSS3_CTL_38_DATA
+ DDRSS3_CTL_39_DATA
+ DDRSS3_CTL_40_DATA
+ DDRSS3_CTL_41_DATA
+ DDRSS3_CTL_42_DATA
+ DDRSS3_CTL_43_DATA
+ DDRSS3_CTL_44_DATA
+ DDRSS3_CTL_45_DATA
+ DDRSS3_CTL_46_DATA
+ DDRSS3_CTL_47_DATA
+ DDRSS3_CTL_48_DATA
+ DDRSS3_CTL_49_DATA
+ DDRSS3_CTL_50_DATA
+ DDRSS3_CTL_51_DATA
+ DDRSS3_CTL_52_DATA
+ DDRSS3_CTL_53_DATA
+ DDRSS3_CTL_54_DATA
+ DDRSS3_CTL_55_DATA
+ DDRSS3_CTL_56_DATA
+ DDRSS3_CTL_57_DATA
+ DDRSS3_CTL_58_DATA
+ DDRSS3_CTL_59_DATA
+ DDRSS3_CTL_60_DATA
+ DDRSS3_CTL_61_DATA
+ DDRSS3_CTL_62_DATA
+ DDRSS3_CTL_63_DATA
+ DDRSS3_CTL_64_DATA
+ DDRSS3_CTL_65_DATA
+ DDRSS3_CTL_66_DATA
+ DDRSS3_CTL_67_DATA
+ DDRSS3_CTL_68_DATA
+ DDRSS3_CTL_69_DATA
+ DDRSS3_CTL_70_DATA
+ DDRSS3_CTL_71_DATA
+ DDRSS3_CTL_72_DATA
+ DDRSS3_CTL_73_DATA
+ DDRSS3_CTL_74_DATA
+ DDRSS3_CTL_75_DATA
+ DDRSS3_CTL_76_DATA
+ DDRSS3_CTL_77_DATA
+ DDRSS3_CTL_78_DATA
+ DDRSS3_CTL_79_DATA
+ DDRSS3_CTL_80_DATA
+ DDRSS3_CTL_81_DATA
+ DDRSS3_CTL_82_DATA
+ DDRSS3_CTL_83_DATA
+ DDRSS3_CTL_84_DATA
+ DDRSS3_CTL_85_DATA
+ DDRSS3_CTL_86_DATA
+ DDRSS3_CTL_87_DATA
+ DDRSS3_CTL_88_DATA
+ DDRSS3_CTL_89_DATA
+ DDRSS3_CTL_90_DATA
+ DDRSS3_CTL_91_DATA
+ DDRSS3_CTL_92_DATA
+ DDRSS3_CTL_93_DATA
+ DDRSS3_CTL_94_DATA
+ DDRSS3_CTL_95_DATA
+ DDRSS3_CTL_96_DATA
+ DDRSS3_CTL_97_DATA
+ DDRSS3_CTL_98_DATA
+ DDRSS3_CTL_99_DATA
+ DDRSS3_CTL_100_DATA
+ DDRSS3_CTL_101_DATA
+ DDRSS3_CTL_102_DATA
+ DDRSS3_CTL_103_DATA
+ DDRSS3_CTL_104_DATA
+ DDRSS3_CTL_105_DATA
+ DDRSS3_CTL_106_DATA
+ DDRSS3_CTL_107_DATA
+ DDRSS3_CTL_108_DATA
+ DDRSS3_CTL_109_DATA
+ DDRSS3_CTL_110_DATA
+ DDRSS3_CTL_111_DATA
+ DDRSS3_CTL_112_DATA
+ DDRSS3_CTL_113_DATA
+ DDRSS3_CTL_114_DATA
+ DDRSS3_CTL_115_DATA
+ DDRSS3_CTL_116_DATA
+ DDRSS3_CTL_117_DATA
+ DDRSS3_CTL_118_DATA
+ DDRSS3_CTL_119_DATA
+ DDRSS3_CTL_120_DATA
+ DDRSS3_CTL_121_DATA
+ DDRSS3_CTL_122_DATA
+ DDRSS3_CTL_123_DATA
+ DDRSS3_CTL_124_DATA
+ DDRSS3_CTL_125_DATA
+ DDRSS3_CTL_126_DATA
+ DDRSS3_CTL_127_DATA
+ DDRSS3_CTL_128_DATA
+ DDRSS3_CTL_129_DATA
+ DDRSS3_CTL_130_DATA
+ DDRSS3_CTL_131_DATA
+ DDRSS3_CTL_132_DATA
+ DDRSS3_CTL_133_DATA
+ DDRSS3_CTL_134_DATA
+ DDRSS3_CTL_135_DATA
+ DDRSS3_CTL_136_DATA
+ DDRSS3_CTL_137_DATA
+ DDRSS3_CTL_138_DATA
+ DDRSS3_CTL_139_DATA
+ DDRSS3_CTL_140_DATA
+ DDRSS3_CTL_141_DATA
+ DDRSS3_CTL_142_DATA
+ DDRSS3_CTL_143_DATA
+ DDRSS3_CTL_144_DATA
+ DDRSS3_CTL_145_DATA
+ DDRSS3_CTL_146_DATA
+ DDRSS3_CTL_147_DATA
+ DDRSS3_CTL_148_DATA
+ DDRSS3_CTL_149_DATA
+ DDRSS3_CTL_150_DATA
+ DDRSS3_CTL_151_DATA
+ DDRSS3_CTL_152_DATA
+ DDRSS3_CTL_153_DATA
+ DDRSS3_CTL_154_DATA
+ DDRSS3_CTL_155_DATA
+ DDRSS3_CTL_156_DATA
+ DDRSS3_CTL_157_DATA
+ DDRSS3_CTL_158_DATA
+ DDRSS3_CTL_159_DATA
+ DDRSS3_CTL_160_DATA
+ DDRSS3_CTL_161_DATA
+ DDRSS3_CTL_162_DATA
+ DDRSS3_CTL_163_DATA
+ DDRSS3_CTL_164_DATA
+ DDRSS3_CTL_165_DATA
+ DDRSS3_CTL_166_DATA
+ DDRSS3_CTL_167_DATA
+ DDRSS3_CTL_168_DATA
+ DDRSS3_CTL_169_DATA
+ DDRSS3_CTL_170_DATA
+ DDRSS3_CTL_171_DATA
+ DDRSS3_CTL_172_DATA
+ DDRSS3_CTL_173_DATA
+ DDRSS3_CTL_174_DATA
+ DDRSS3_CTL_175_DATA
+ DDRSS3_CTL_176_DATA
+ DDRSS3_CTL_177_DATA
+ DDRSS3_CTL_178_DATA
+ DDRSS3_CTL_179_DATA
+ DDRSS3_CTL_180_DATA
+ DDRSS3_CTL_181_DATA
+ DDRSS3_CTL_182_DATA
+ DDRSS3_CTL_183_DATA
+ DDRSS3_CTL_184_DATA
+ DDRSS3_CTL_185_DATA
+ DDRSS3_CTL_186_DATA
+ DDRSS3_CTL_187_DATA
+ DDRSS3_CTL_188_DATA
+ DDRSS3_CTL_189_DATA
+ DDRSS3_CTL_190_DATA
+ DDRSS3_CTL_191_DATA
+ DDRSS3_CTL_192_DATA
+ DDRSS3_CTL_193_DATA
+ DDRSS3_CTL_194_DATA
+ DDRSS3_CTL_195_DATA
+ DDRSS3_CTL_196_DATA
+ DDRSS3_CTL_197_DATA
+ DDRSS3_CTL_198_DATA
+ DDRSS3_CTL_199_DATA
+ DDRSS3_CTL_200_DATA
+ DDRSS3_CTL_201_DATA
+ DDRSS3_CTL_202_DATA
+ DDRSS3_CTL_203_DATA
+ DDRSS3_CTL_204_DATA
+ DDRSS3_CTL_205_DATA
+ DDRSS3_CTL_206_DATA
+ DDRSS3_CTL_207_DATA
+ DDRSS3_CTL_208_DATA
+ DDRSS3_CTL_209_DATA
+ DDRSS3_CTL_210_DATA
+ DDRSS3_CTL_211_DATA
+ DDRSS3_CTL_212_DATA
+ DDRSS3_CTL_213_DATA
+ DDRSS3_CTL_214_DATA
+ DDRSS3_CTL_215_DATA
+ DDRSS3_CTL_216_DATA
+ DDRSS3_CTL_217_DATA
+ DDRSS3_CTL_218_DATA
+ DDRSS3_CTL_219_DATA
+ DDRSS3_CTL_220_DATA
+ DDRSS3_CTL_221_DATA
+ DDRSS3_CTL_222_DATA
+ DDRSS3_CTL_223_DATA
+ DDRSS3_CTL_224_DATA
+ DDRSS3_CTL_225_DATA
+ DDRSS3_CTL_226_DATA
+ DDRSS3_CTL_227_DATA
+ DDRSS3_CTL_228_DATA
+ DDRSS3_CTL_229_DATA
+ DDRSS3_CTL_230_DATA
+ DDRSS3_CTL_231_DATA
+ DDRSS3_CTL_232_DATA
+ DDRSS3_CTL_233_DATA
+ DDRSS3_CTL_234_DATA
+ DDRSS3_CTL_235_DATA
+ DDRSS3_CTL_236_DATA
+ DDRSS3_CTL_237_DATA
+ DDRSS3_CTL_238_DATA
+ DDRSS3_CTL_239_DATA
+ DDRSS3_CTL_240_DATA
+ DDRSS3_CTL_241_DATA
+ DDRSS3_CTL_242_DATA
+ DDRSS3_CTL_243_DATA
+ DDRSS3_CTL_244_DATA
+ DDRSS3_CTL_245_DATA
+ DDRSS3_CTL_246_DATA
+ DDRSS3_CTL_247_DATA
+ DDRSS3_CTL_248_DATA
+ DDRSS3_CTL_249_DATA
+ DDRSS3_CTL_250_DATA
+ DDRSS3_CTL_251_DATA
+ DDRSS3_CTL_252_DATA
+ DDRSS3_CTL_253_DATA
+ DDRSS3_CTL_254_DATA
+ DDRSS3_CTL_255_DATA
+ DDRSS3_CTL_256_DATA
+ DDRSS3_CTL_257_DATA
+ DDRSS3_CTL_258_DATA
+ DDRSS3_CTL_259_DATA
+ DDRSS3_CTL_260_DATA
+ DDRSS3_CTL_261_DATA
+ DDRSS3_CTL_262_DATA
+ DDRSS3_CTL_263_DATA
+ DDRSS3_CTL_264_DATA
+ DDRSS3_CTL_265_DATA
+ DDRSS3_CTL_266_DATA
+ DDRSS3_CTL_267_DATA
+ DDRSS3_CTL_268_DATA
+ DDRSS3_CTL_269_DATA
+ DDRSS3_CTL_270_DATA
+ DDRSS3_CTL_271_DATA
+ DDRSS3_CTL_272_DATA
+ DDRSS3_CTL_273_DATA
+ DDRSS3_CTL_274_DATA
+ DDRSS3_CTL_275_DATA
+ DDRSS3_CTL_276_DATA
+ DDRSS3_CTL_277_DATA
+ DDRSS3_CTL_278_DATA
+ DDRSS3_CTL_279_DATA
+ DDRSS3_CTL_280_DATA
+ DDRSS3_CTL_281_DATA
+ DDRSS3_CTL_282_DATA
+ DDRSS3_CTL_283_DATA
+ DDRSS3_CTL_284_DATA
+ DDRSS3_CTL_285_DATA
+ DDRSS3_CTL_286_DATA
+ DDRSS3_CTL_287_DATA
+ DDRSS3_CTL_288_DATA
+ DDRSS3_CTL_289_DATA
+ DDRSS3_CTL_290_DATA
+ DDRSS3_CTL_291_DATA
+ DDRSS3_CTL_292_DATA
+ DDRSS3_CTL_293_DATA
+ DDRSS3_CTL_294_DATA
+ DDRSS3_CTL_295_DATA
+ DDRSS3_CTL_296_DATA
+ DDRSS3_CTL_297_DATA
+ DDRSS3_CTL_298_DATA
+ DDRSS3_CTL_299_DATA
+ DDRSS3_CTL_300_DATA
+ DDRSS3_CTL_301_DATA
+ DDRSS3_CTL_302_DATA
+ DDRSS3_CTL_303_DATA
+ DDRSS3_CTL_304_DATA
+ DDRSS3_CTL_305_DATA
+ DDRSS3_CTL_306_DATA
+ DDRSS3_CTL_307_DATA
+ DDRSS3_CTL_308_DATA
+ DDRSS3_CTL_309_DATA
+ DDRSS3_CTL_310_DATA
+ DDRSS3_CTL_311_DATA
+ DDRSS3_CTL_312_DATA
+ DDRSS3_CTL_313_DATA
+ DDRSS3_CTL_314_DATA
+ DDRSS3_CTL_315_DATA
+ DDRSS3_CTL_316_DATA
+ DDRSS3_CTL_317_DATA
+ DDRSS3_CTL_318_DATA
+ DDRSS3_CTL_319_DATA
+ DDRSS3_CTL_320_DATA
+ DDRSS3_CTL_321_DATA
+ DDRSS3_CTL_322_DATA
+ DDRSS3_CTL_323_DATA
+ DDRSS3_CTL_324_DATA
+ DDRSS3_CTL_325_DATA
+ DDRSS3_CTL_326_DATA
+ DDRSS3_CTL_327_DATA
+ DDRSS3_CTL_328_DATA
+ DDRSS3_CTL_329_DATA
+ DDRSS3_CTL_330_DATA
+ DDRSS3_CTL_331_DATA
+ DDRSS3_CTL_332_DATA
+ DDRSS3_CTL_333_DATA
+ DDRSS3_CTL_334_DATA
+ DDRSS3_CTL_335_DATA
+ DDRSS3_CTL_336_DATA
+ DDRSS3_CTL_337_DATA
+ DDRSS3_CTL_338_DATA
+ DDRSS3_CTL_339_DATA
+ DDRSS3_CTL_340_DATA
+ DDRSS3_CTL_341_DATA
+ DDRSS3_CTL_342_DATA
+ DDRSS3_CTL_343_DATA
+ DDRSS3_CTL_344_DATA
+ DDRSS3_CTL_345_DATA
+ DDRSS3_CTL_346_DATA
+ DDRSS3_CTL_347_DATA
+ DDRSS3_CTL_348_DATA
+ DDRSS3_CTL_349_DATA
+ DDRSS3_CTL_350_DATA
+ DDRSS3_CTL_351_DATA
+ DDRSS3_CTL_352_DATA
+ DDRSS3_CTL_353_DATA
+ DDRSS3_CTL_354_DATA
+ DDRSS3_CTL_355_DATA
+ DDRSS3_CTL_356_DATA
+ DDRSS3_CTL_357_DATA
+ DDRSS3_CTL_358_DATA
+ DDRSS3_CTL_359_DATA
+ DDRSS3_CTL_360_DATA
+ DDRSS3_CTL_361_DATA
+ DDRSS3_CTL_362_DATA
+ DDRSS3_CTL_363_DATA
+ DDRSS3_CTL_364_DATA
+ DDRSS3_CTL_365_DATA
+ DDRSS3_CTL_366_DATA
+ DDRSS3_CTL_367_DATA
+ DDRSS3_CTL_368_DATA
+ DDRSS3_CTL_369_DATA
+ DDRSS3_CTL_370_DATA
+ DDRSS3_CTL_371_DATA
+ DDRSS3_CTL_372_DATA
+ DDRSS3_CTL_373_DATA
+ DDRSS3_CTL_374_DATA
+ DDRSS3_CTL_375_DATA
+ DDRSS3_CTL_376_DATA
+ DDRSS3_CTL_377_DATA
+ DDRSS3_CTL_378_DATA
+ DDRSS3_CTL_379_DATA
+ DDRSS3_CTL_380_DATA
+ DDRSS3_CTL_381_DATA
+ DDRSS3_CTL_382_DATA
+ DDRSS3_CTL_383_DATA
+ DDRSS3_CTL_384_DATA
+ DDRSS3_CTL_385_DATA
+ DDRSS3_CTL_386_DATA
+ DDRSS3_CTL_387_DATA
+ DDRSS3_CTL_388_DATA
+ DDRSS3_CTL_389_DATA
+ DDRSS3_CTL_390_DATA
+ DDRSS3_CTL_391_DATA
+ DDRSS3_CTL_392_DATA
+ DDRSS3_CTL_393_DATA
+ DDRSS3_CTL_394_DATA
+ DDRSS3_CTL_395_DATA
+ DDRSS3_CTL_396_DATA
+ DDRSS3_CTL_397_DATA
+ DDRSS3_CTL_398_DATA
+ DDRSS3_CTL_399_DATA
+ DDRSS3_CTL_400_DATA
+ DDRSS3_CTL_401_DATA
+ DDRSS3_CTL_402_DATA
+ DDRSS3_CTL_403_DATA
+ DDRSS3_CTL_404_DATA
+ DDRSS3_CTL_405_DATA
+ DDRSS3_CTL_406_DATA
+ DDRSS3_CTL_407_DATA
+ DDRSS3_CTL_408_DATA
+ DDRSS3_CTL_409_DATA
+ DDRSS3_CTL_410_DATA
+ DDRSS3_CTL_411_DATA
+ DDRSS3_CTL_412_DATA
+ DDRSS3_CTL_413_DATA
+ DDRSS3_CTL_414_DATA
+ DDRSS3_CTL_415_DATA
+ DDRSS3_CTL_416_DATA
+ DDRSS3_CTL_417_DATA
+ DDRSS3_CTL_418_DATA
+ DDRSS3_CTL_419_DATA
+ DDRSS3_CTL_420_DATA
+ DDRSS3_CTL_421_DATA
+ DDRSS3_CTL_422_DATA
+ DDRSS3_CTL_423_DATA
+ DDRSS3_CTL_424_DATA
+ DDRSS3_CTL_425_DATA
+ DDRSS3_CTL_426_DATA
+ DDRSS3_CTL_427_DATA
+ DDRSS3_CTL_428_DATA
+ DDRSS3_CTL_429_DATA
+ DDRSS3_CTL_430_DATA
+ DDRSS3_CTL_431_DATA
+ DDRSS3_CTL_432_DATA
+ DDRSS3_CTL_433_DATA
+ DDRSS3_CTL_434_DATA
+ DDRSS3_CTL_435_DATA
+ DDRSS3_CTL_436_DATA
+ DDRSS3_CTL_437_DATA
+ DDRSS3_CTL_438_DATA
+ DDRSS3_CTL_439_DATA
+ DDRSS3_CTL_440_DATA
+ DDRSS3_CTL_441_DATA
+ DDRSS3_CTL_442_DATA
+ DDRSS3_CTL_443_DATA
+ DDRSS3_CTL_444_DATA
+ DDRSS3_CTL_445_DATA
+ DDRSS3_CTL_446_DATA
+ DDRSS3_CTL_447_DATA
+ DDRSS3_CTL_448_DATA
+ DDRSS3_CTL_449_DATA
+ DDRSS3_CTL_450_DATA
+ DDRSS3_CTL_451_DATA
+ DDRSS3_CTL_452_DATA
+ DDRSS3_CTL_453_DATA
+ DDRSS3_CTL_454_DATA
+ DDRSS3_CTL_455_DATA
+ DDRSS3_CTL_456_DATA
+ DDRSS3_CTL_457_DATA
+ DDRSS3_CTL_458_DATA
+ >;
+
+ ti,pi-data = <
+ DDRSS3_PI_00_DATA
+ DDRSS3_PI_01_DATA
+ DDRSS3_PI_02_DATA
+ DDRSS3_PI_03_DATA
+ DDRSS3_PI_04_DATA
+ DDRSS3_PI_05_DATA
+ DDRSS3_PI_06_DATA
+ DDRSS3_PI_07_DATA
+ DDRSS3_PI_08_DATA
+ DDRSS3_PI_09_DATA
+ DDRSS3_PI_10_DATA
+ DDRSS3_PI_11_DATA
+ DDRSS3_PI_12_DATA
+ DDRSS3_PI_13_DATA
+ DDRSS3_PI_14_DATA
+ DDRSS3_PI_15_DATA
+ DDRSS3_PI_16_DATA
+ DDRSS3_PI_17_DATA
+ DDRSS3_PI_18_DATA
+ DDRSS3_PI_19_DATA
+ DDRSS3_PI_20_DATA
+ DDRSS3_PI_21_DATA
+ DDRSS3_PI_22_DATA
+ DDRSS3_PI_23_DATA
+ DDRSS3_PI_24_DATA
+ DDRSS3_PI_25_DATA
+ DDRSS3_PI_26_DATA
+ DDRSS3_PI_27_DATA
+ DDRSS3_PI_28_DATA
+ DDRSS3_PI_29_DATA
+ DDRSS3_PI_30_DATA
+ DDRSS3_PI_31_DATA
+ DDRSS3_PI_32_DATA
+ DDRSS3_PI_33_DATA
+ DDRSS3_PI_34_DATA
+ DDRSS3_PI_35_DATA
+ DDRSS3_PI_36_DATA
+ DDRSS3_PI_37_DATA
+ DDRSS3_PI_38_DATA
+ DDRSS3_PI_39_DATA
+ DDRSS3_PI_40_DATA
+ DDRSS3_PI_41_DATA
+ DDRSS3_PI_42_DATA
+ DDRSS3_PI_43_DATA
+ DDRSS3_PI_44_DATA
+ DDRSS3_PI_45_DATA
+ DDRSS3_PI_46_DATA
+ DDRSS3_PI_47_DATA
+ DDRSS3_PI_48_DATA
+ DDRSS3_PI_49_DATA
+ DDRSS3_PI_50_DATA
+ DDRSS3_PI_51_DATA
+ DDRSS3_PI_52_DATA
+ DDRSS3_PI_53_DATA
+ DDRSS3_PI_54_DATA
+ DDRSS3_PI_55_DATA
+ DDRSS3_PI_56_DATA
+ DDRSS3_PI_57_DATA
+ DDRSS3_PI_58_DATA
+ DDRSS3_PI_59_DATA
+ DDRSS3_PI_60_DATA
+ DDRSS3_PI_61_DATA
+ DDRSS3_PI_62_DATA
+ DDRSS3_PI_63_DATA
+ DDRSS3_PI_64_DATA
+ DDRSS3_PI_65_DATA
+ DDRSS3_PI_66_DATA
+ DDRSS3_PI_67_DATA
+ DDRSS3_PI_68_DATA
+ DDRSS3_PI_69_DATA
+ DDRSS3_PI_70_DATA
+ DDRSS3_PI_71_DATA
+ DDRSS3_PI_72_DATA
+ DDRSS3_PI_73_DATA
+ DDRSS3_PI_74_DATA
+ DDRSS3_PI_75_DATA
+ DDRSS3_PI_76_DATA
+ DDRSS3_PI_77_DATA
+ DDRSS3_PI_78_DATA
+ DDRSS3_PI_79_DATA
+ DDRSS3_PI_80_DATA
+ DDRSS3_PI_81_DATA
+ DDRSS3_PI_82_DATA
+ DDRSS3_PI_83_DATA
+ DDRSS3_PI_84_DATA
+ DDRSS3_PI_85_DATA
+ DDRSS3_PI_86_DATA
+ DDRSS3_PI_87_DATA
+ DDRSS3_PI_88_DATA
+ DDRSS3_PI_89_DATA
+ DDRSS3_PI_90_DATA
+ DDRSS3_PI_91_DATA
+ DDRSS3_PI_92_DATA
+ DDRSS3_PI_93_DATA
+ DDRSS3_PI_94_DATA
+ DDRSS3_PI_95_DATA
+ DDRSS3_PI_96_DATA
+ DDRSS3_PI_97_DATA
+ DDRSS3_PI_98_DATA
+ DDRSS3_PI_99_DATA
+ DDRSS3_PI_100_DATA
+ DDRSS3_PI_101_DATA
+ DDRSS3_PI_102_DATA
+ DDRSS3_PI_103_DATA
+ DDRSS3_PI_104_DATA
+ DDRSS3_PI_105_DATA
+ DDRSS3_PI_106_DATA
+ DDRSS3_PI_107_DATA
+ DDRSS3_PI_108_DATA
+ DDRSS3_PI_109_DATA
+ DDRSS3_PI_110_DATA
+ DDRSS3_PI_111_DATA
+ DDRSS3_PI_112_DATA
+ DDRSS3_PI_113_DATA
+ DDRSS3_PI_114_DATA
+ DDRSS3_PI_115_DATA
+ DDRSS3_PI_116_DATA
+ DDRSS3_PI_117_DATA
+ DDRSS3_PI_118_DATA
+ DDRSS3_PI_119_DATA
+ DDRSS3_PI_120_DATA
+ DDRSS3_PI_121_DATA
+ DDRSS3_PI_122_DATA
+ DDRSS3_PI_123_DATA
+ DDRSS3_PI_124_DATA
+ DDRSS3_PI_125_DATA
+ DDRSS3_PI_126_DATA
+ DDRSS3_PI_127_DATA
+ DDRSS3_PI_128_DATA
+ DDRSS3_PI_129_DATA
+ DDRSS3_PI_130_DATA
+ DDRSS3_PI_131_DATA
+ DDRSS3_PI_132_DATA
+ DDRSS3_PI_133_DATA
+ DDRSS3_PI_134_DATA
+ DDRSS3_PI_135_DATA
+ DDRSS3_PI_136_DATA
+ DDRSS3_PI_137_DATA
+ DDRSS3_PI_138_DATA
+ DDRSS3_PI_139_DATA
+ DDRSS3_PI_140_DATA
+ DDRSS3_PI_141_DATA
+ DDRSS3_PI_142_DATA
+ DDRSS3_PI_143_DATA
+ DDRSS3_PI_144_DATA
+ DDRSS3_PI_145_DATA
+ DDRSS3_PI_146_DATA
+ DDRSS3_PI_147_DATA
+ DDRSS3_PI_148_DATA
+ DDRSS3_PI_149_DATA
+ DDRSS3_PI_150_DATA
+ DDRSS3_PI_151_DATA
+ DDRSS3_PI_152_DATA
+ DDRSS3_PI_153_DATA
+ DDRSS3_PI_154_DATA
+ DDRSS3_PI_155_DATA
+ DDRSS3_PI_156_DATA
+ DDRSS3_PI_157_DATA
+ DDRSS3_PI_158_DATA
+ DDRSS3_PI_159_DATA
+ DDRSS3_PI_160_DATA
+ DDRSS3_PI_161_DATA
+ DDRSS3_PI_162_DATA
+ DDRSS3_PI_163_DATA
+ DDRSS3_PI_164_DATA
+ DDRSS3_PI_165_DATA
+ DDRSS3_PI_166_DATA
+ DDRSS3_PI_167_DATA
+ DDRSS3_PI_168_DATA
+ DDRSS3_PI_169_DATA
+ DDRSS3_PI_170_DATA
+ DDRSS3_PI_171_DATA
+ DDRSS3_PI_172_DATA
+ DDRSS3_PI_173_DATA
+ DDRSS3_PI_174_DATA
+ DDRSS3_PI_175_DATA
+ DDRSS3_PI_176_DATA
+ DDRSS3_PI_177_DATA
+ DDRSS3_PI_178_DATA
+ DDRSS3_PI_179_DATA
+ DDRSS3_PI_180_DATA
+ DDRSS3_PI_181_DATA
+ DDRSS3_PI_182_DATA
+ DDRSS3_PI_183_DATA
+ DDRSS3_PI_184_DATA
+ DDRSS3_PI_185_DATA
+ DDRSS3_PI_186_DATA
+ DDRSS3_PI_187_DATA
+ DDRSS3_PI_188_DATA
+ DDRSS3_PI_189_DATA
+ DDRSS3_PI_190_DATA
+ DDRSS3_PI_191_DATA
+ DDRSS3_PI_192_DATA
+ DDRSS3_PI_193_DATA
+ DDRSS3_PI_194_DATA
+ DDRSS3_PI_195_DATA
+ DDRSS3_PI_196_DATA
+ DDRSS3_PI_197_DATA
+ DDRSS3_PI_198_DATA
+ DDRSS3_PI_199_DATA
+ DDRSS3_PI_200_DATA
+ DDRSS3_PI_201_DATA
+ DDRSS3_PI_202_DATA
+ DDRSS3_PI_203_DATA
+ DDRSS3_PI_204_DATA
+ DDRSS3_PI_205_DATA
+ DDRSS3_PI_206_DATA
+ DDRSS3_PI_207_DATA
+ DDRSS3_PI_208_DATA
+ DDRSS3_PI_209_DATA
+ DDRSS3_PI_210_DATA
+ DDRSS3_PI_211_DATA
+ DDRSS3_PI_212_DATA
+ DDRSS3_PI_213_DATA
+ DDRSS3_PI_214_DATA
+ DDRSS3_PI_215_DATA
+ DDRSS3_PI_216_DATA
+ DDRSS3_PI_217_DATA
+ DDRSS3_PI_218_DATA
+ DDRSS3_PI_219_DATA
+ DDRSS3_PI_220_DATA
+ DDRSS3_PI_221_DATA
+ DDRSS3_PI_222_DATA
+ DDRSS3_PI_223_DATA
+ DDRSS3_PI_224_DATA
+ DDRSS3_PI_225_DATA
+ DDRSS3_PI_226_DATA
+ DDRSS3_PI_227_DATA
+ DDRSS3_PI_228_DATA
+ DDRSS3_PI_229_DATA
+ DDRSS3_PI_230_DATA
+ DDRSS3_PI_231_DATA
+ DDRSS3_PI_232_DATA
+ DDRSS3_PI_233_DATA
+ DDRSS3_PI_234_DATA
+ DDRSS3_PI_235_DATA
+ DDRSS3_PI_236_DATA
+ DDRSS3_PI_237_DATA
+ DDRSS3_PI_238_DATA
+ DDRSS3_PI_239_DATA
+ DDRSS3_PI_240_DATA
+ DDRSS3_PI_241_DATA
+ DDRSS3_PI_242_DATA
+ DDRSS3_PI_243_DATA
+ DDRSS3_PI_244_DATA
+ DDRSS3_PI_245_DATA
+ DDRSS3_PI_246_DATA
+ DDRSS3_PI_247_DATA
+ DDRSS3_PI_248_DATA
+ DDRSS3_PI_249_DATA
+ DDRSS3_PI_250_DATA
+ DDRSS3_PI_251_DATA
+ DDRSS3_PI_252_DATA
+ DDRSS3_PI_253_DATA
+ DDRSS3_PI_254_DATA
+ DDRSS3_PI_255_DATA
+ DDRSS3_PI_256_DATA
+ DDRSS3_PI_257_DATA
+ DDRSS3_PI_258_DATA
+ DDRSS3_PI_259_DATA
+ DDRSS3_PI_260_DATA
+ DDRSS3_PI_261_DATA
+ DDRSS3_PI_262_DATA
+ DDRSS3_PI_263_DATA
+ DDRSS3_PI_264_DATA
+ DDRSS3_PI_265_DATA
+ DDRSS3_PI_266_DATA
+ DDRSS3_PI_267_DATA
+ DDRSS3_PI_268_DATA
+ DDRSS3_PI_269_DATA
+ DDRSS3_PI_270_DATA
+ DDRSS3_PI_271_DATA
+ DDRSS3_PI_272_DATA
+ DDRSS3_PI_273_DATA
+ DDRSS3_PI_274_DATA
+ DDRSS3_PI_275_DATA
+ DDRSS3_PI_276_DATA
+ DDRSS3_PI_277_DATA
+ DDRSS3_PI_278_DATA
+ DDRSS3_PI_279_DATA
+ DDRSS3_PI_280_DATA
+ DDRSS3_PI_281_DATA
+ DDRSS3_PI_282_DATA
+ DDRSS3_PI_283_DATA
+ DDRSS3_PI_284_DATA
+ DDRSS3_PI_285_DATA
+ DDRSS3_PI_286_DATA
+ DDRSS3_PI_287_DATA
+ DDRSS3_PI_288_DATA
+ DDRSS3_PI_289_DATA
+ DDRSS3_PI_290_DATA
+ DDRSS3_PI_291_DATA
+ DDRSS3_PI_292_DATA
+ DDRSS3_PI_293_DATA
+ DDRSS3_PI_294_DATA
+ DDRSS3_PI_295_DATA
+ DDRSS3_PI_296_DATA
+ DDRSS3_PI_297_DATA
+ DDRSS3_PI_298_DATA
+ DDRSS3_PI_299_DATA
+ >;
+
+ ti,phy-data = <
+ DDRSS3_PHY_00_DATA
+ DDRSS3_PHY_01_DATA
+ DDRSS3_PHY_02_DATA
+ DDRSS3_PHY_03_DATA
+ DDRSS3_PHY_04_DATA
+ DDRSS3_PHY_05_DATA
+ DDRSS3_PHY_06_DATA
+ DDRSS3_PHY_07_DATA
+ DDRSS3_PHY_08_DATA
+ DDRSS3_PHY_09_DATA
+ DDRSS3_PHY_10_DATA
+ DDRSS3_PHY_11_DATA
+ DDRSS3_PHY_12_DATA
+ DDRSS3_PHY_13_DATA
+ DDRSS3_PHY_14_DATA
+ DDRSS3_PHY_15_DATA
+ DDRSS3_PHY_16_DATA
+ DDRSS3_PHY_17_DATA
+ DDRSS3_PHY_18_DATA
+ DDRSS3_PHY_19_DATA
+ DDRSS3_PHY_20_DATA
+ DDRSS3_PHY_21_DATA
+ DDRSS3_PHY_22_DATA
+ DDRSS3_PHY_23_DATA
+ DDRSS3_PHY_24_DATA
+ DDRSS3_PHY_25_DATA
+ DDRSS3_PHY_26_DATA
+ DDRSS3_PHY_27_DATA
+ DDRSS3_PHY_28_DATA
+ DDRSS3_PHY_29_DATA
+ DDRSS3_PHY_30_DATA
+ DDRSS3_PHY_31_DATA
+ DDRSS3_PHY_32_DATA
+ DDRSS3_PHY_33_DATA
+ DDRSS3_PHY_34_DATA
+ DDRSS3_PHY_35_DATA
+ DDRSS3_PHY_36_DATA
+ DDRSS3_PHY_37_DATA
+ DDRSS3_PHY_38_DATA
+ DDRSS3_PHY_39_DATA
+ DDRSS3_PHY_40_DATA
+ DDRSS3_PHY_41_DATA
+ DDRSS3_PHY_42_DATA
+ DDRSS3_PHY_43_DATA
+ DDRSS3_PHY_44_DATA
+ DDRSS3_PHY_45_DATA
+ DDRSS3_PHY_46_DATA
+ DDRSS3_PHY_47_DATA
+ DDRSS3_PHY_48_DATA
+ DDRSS3_PHY_49_DATA
+ DDRSS3_PHY_50_DATA
+ DDRSS3_PHY_51_DATA
+ DDRSS3_PHY_52_DATA
+ DDRSS3_PHY_53_DATA
+ DDRSS3_PHY_54_DATA
+ DDRSS3_PHY_55_DATA
+ DDRSS3_PHY_56_DATA
+ DDRSS3_PHY_57_DATA
+ DDRSS3_PHY_58_DATA
+ DDRSS3_PHY_59_DATA
+ DDRSS3_PHY_60_DATA
+ DDRSS3_PHY_61_DATA
+ DDRSS3_PHY_62_DATA
+ DDRSS3_PHY_63_DATA
+ DDRSS3_PHY_64_DATA
+ DDRSS3_PHY_65_DATA
+ DDRSS3_PHY_66_DATA
+ DDRSS3_PHY_67_DATA
+ DDRSS3_PHY_68_DATA
+ DDRSS3_PHY_69_DATA
+ DDRSS3_PHY_70_DATA
+ DDRSS3_PHY_71_DATA
+ DDRSS3_PHY_72_DATA
+ DDRSS3_PHY_73_DATA
+ DDRSS3_PHY_74_DATA
+ DDRSS3_PHY_75_DATA
+ DDRSS3_PHY_76_DATA
+ DDRSS3_PHY_77_DATA
+ DDRSS3_PHY_78_DATA
+ DDRSS3_PHY_79_DATA
+ DDRSS3_PHY_80_DATA
+ DDRSS3_PHY_81_DATA
+ DDRSS3_PHY_82_DATA
+ DDRSS3_PHY_83_DATA
+ DDRSS3_PHY_84_DATA
+ DDRSS3_PHY_85_DATA
+ DDRSS3_PHY_86_DATA
+ DDRSS3_PHY_87_DATA
+ DDRSS3_PHY_88_DATA
+ DDRSS3_PHY_89_DATA
+ DDRSS3_PHY_90_DATA
+ DDRSS3_PHY_91_DATA
+ DDRSS3_PHY_92_DATA
+ DDRSS3_PHY_93_DATA
+ DDRSS3_PHY_94_DATA
+ DDRSS3_PHY_95_DATA
+ DDRSS3_PHY_96_DATA
+ DDRSS3_PHY_97_DATA
+ DDRSS3_PHY_98_DATA
+ DDRSS3_PHY_99_DATA
+ DDRSS3_PHY_100_DATA
+ DDRSS3_PHY_101_DATA
+ DDRSS3_PHY_102_DATA
+ DDRSS3_PHY_103_DATA
+ DDRSS3_PHY_104_DATA
+ DDRSS3_PHY_105_DATA
+ DDRSS3_PHY_106_DATA
+ DDRSS3_PHY_107_DATA
+ DDRSS3_PHY_108_DATA
+ DDRSS3_PHY_109_DATA
+ DDRSS3_PHY_110_DATA
+ DDRSS3_PHY_111_DATA
+ DDRSS3_PHY_112_DATA
+ DDRSS3_PHY_113_DATA
+ DDRSS3_PHY_114_DATA
+ DDRSS3_PHY_115_DATA
+ DDRSS3_PHY_116_DATA
+ DDRSS3_PHY_117_DATA
+ DDRSS3_PHY_118_DATA
+ DDRSS3_PHY_119_DATA
+ DDRSS3_PHY_120_DATA
+ DDRSS3_PHY_121_DATA
+ DDRSS3_PHY_122_DATA
+ DDRSS3_PHY_123_DATA
+ DDRSS3_PHY_124_DATA
+ DDRSS3_PHY_125_DATA
+ DDRSS3_PHY_126_DATA
+ DDRSS3_PHY_127_DATA
+ DDRSS3_PHY_128_DATA
+ DDRSS3_PHY_129_DATA
+ DDRSS3_PHY_130_DATA
+ DDRSS3_PHY_131_DATA
+ DDRSS3_PHY_132_DATA
+ DDRSS3_PHY_133_DATA
+ DDRSS3_PHY_134_DATA
+ DDRSS3_PHY_135_DATA
+ DDRSS3_PHY_136_DATA
+ DDRSS3_PHY_137_DATA
+ DDRSS3_PHY_138_DATA
+ DDRSS3_PHY_139_DATA
+ DDRSS3_PHY_140_DATA
+ DDRSS3_PHY_141_DATA
+ DDRSS3_PHY_142_DATA
+ DDRSS3_PHY_143_DATA
+ DDRSS3_PHY_144_DATA
+ DDRSS3_PHY_145_DATA
+ DDRSS3_PHY_146_DATA
+ DDRSS3_PHY_147_DATA
+ DDRSS3_PHY_148_DATA
+ DDRSS3_PHY_149_DATA
+ DDRSS3_PHY_150_DATA
+ DDRSS3_PHY_151_DATA
+ DDRSS3_PHY_152_DATA
+ DDRSS3_PHY_153_DATA
+ DDRSS3_PHY_154_DATA
+ DDRSS3_PHY_155_DATA
+ DDRSS3_PHY_156_DATA
+ DDRSS3_PHY_157_DATA
+ DDRSS3_PHY_158_DATA
+ DDRSS3_PHY_159_DATA
+ DDRSS3_PHY_160_DATA
+ DDRSS3_PHY_161_DATA
+ DDRSS3_PHY_162_DATA
+ DDRSS3_PHY_163_DATA
+ DDRSS3_PHY_164_DATA
+ DDRSS3_PHY_165_DATA
+ DDRSS3_PHY_166_DATA
+ DDRSS3_PHY_167_DATA
+ DDRSS3_PHY_168_DATA
+ DDRSS3_PHY_169_DATA
+ DDRSS3_PHY_170_DATA
+ DDRSS3_PHY_171_DATA
+ DDRSS3_PHY_172_DATA
+ DDRSS3_PHY_173_DATA
+ DDRSS3_PHY_174_DATA
+ DDRSS3_PHY_175_DATA
+ DDRSS3_PHY_176_DATA
+ DDRSS3_PHY_177_DATA
+ DDRSS3_PHY_178_DATA
+ DDRSS3_PHY_179_DATA
+ DDRSS3_PHY_180_DATA
+ DDRSS3_PHY_181_DATA
+ DDRSS3_PHY_182_DATA
+ DDRSS3_PHY_183_DATA
+ DDRSS3_PHY_184_DATA
+ DDRSS3_PHY_185_DATA
+ DDRSS3_PHY_186_DATA
+ DDRSS3_PHY_187_DATA
+ DDRSS3_PHY_188_DATA
+ DDRSS3_PHY_189_DATA
+ DDRSS3_PHY_190_DATA
+ DDRSS3_PHY_191_DATA
+ DDRSS3_PHY_192_DATA
+ DDRSS3_PHY_193_DATA
+ DDRSS3_PHY_194_DATA
+ DDRSS3_PHY_195_DATA
+ DDRSS3_PHY_196_DATA
+ DDRSS3_PHY_197_DATA
+ DDRSS3_PHY_198_DATA
+ DDRSS3_PHY_199_DATA
+ DDRSS3_PHY_200_DATA
+ DDRSS3_PHY_201_DATA
+ DDRSS3_PHY_202_DATA
+ DDRSS3_PHY_203_DATA
+ DDRSS3_PHY_204_DATA
+ DDRSS3_PHY_205_DATA
+ DDRSS3_PHY_206_DATA
+ DDRSS3_PHY_207_DATA
+ DDRSS3_PHY_208_DATA
+ DDRSS3_PHY_209_DATA
+ DDRSS3_PHY_210_DATA
+ DDRSS3_PHY_211_DATA
+ DDRSS3_PHY_212_DATA
+ DDRSS3_PHY_213_DATA
+ DDRSS3_PHY_214_DATA
+ DDRSS3_PHY_215_DATA
+ DDRSS3_PHY_216_DATA
+ DDRSS3_PHY_217_DATA
+ DDRSS3_PHY_218_DATA
+ DDRSS3_PHY_219_DATA
+ DDRSS3_PHY_220_DATA
+ DDRSS3_PHY_221_DATA
+ DDRSS3_PHY_222_DATA
+ DDRSS3_PHY_223_DATA
+ DDRSS3_PHY_224_DATA
+ DDRSS3_PHY_225_DATA
+ DDRSS3_PHY_226_DATA
+ DDRSS3_PHY_227_DATA
+ DDRSS3_PHY_228_DATA
+ DDRSS3_PHY_229_DATA
+ DDRSS3_PHY_230_DATA
+ DDRSS3_PHY_231_DATA
+ DDRSS3_PHY_232_DATA
+ DDRSS3_PHY_233_DATA
+ DDRSS3_PHY_234_DATA
+ DDRSS3_PHY_235_DATA
+ DDRSS3_PHY_236_DATA
+ DDRSS3_PHY_237_DATA
+ DDRSS3_PHY_238_DATA
+ DDRSS3_PHY_239_DATA
+ DDRSS3_PHY_240_DATA
+ DDRSS3_PHY_241_DATA
+ DDRSS3_PHY_242_DATA
+ DDRSS3_PHY_243_DATA
+ DDRSS3_PHY_244_DATA
+ DDRSS3_PHY_245_DATA
+ DDRSS3_PHY_246_DATA
+ DDRSS3_PHY_247_DATA
+ DDRSS3_PHY_248_DATA
+ DDRSS3_PHY_249_DATA
+ DDRSS3_PHY_250_DATA
+ DDRSS3_PHY_251_DATA
+ DDRSS3_PHY_252_DATA
+ DDRSS3_PHY_253_DATA
+ DDRSS3_PHY_254_DATA
+ DDRSS3_PHY_255_DATA
+ DDRSS3_PHY_256_DATA
+ DDRSS3_PHY_257_DATA
+ DDRSS3_PHY_258_DATA
+ DDRSS3_PHY_259_DATA
+ DDRSS3_PHY_260_DATA
+ DDRSS3_PHY_261_DATA
+ DDRSS3_PHY_262_DATA
+ DDRSS3_PHY_263_DATA
+ DDRSS3_PHY_264_DATA
+ DDRSS3_PHY_265_DATA
+ DDRSS3_PHY_266_DATA
+ DDRSS3_PHY_267_DATA
+ DDRSS3_PHY_268_DATA
+ DDRSS3_PHY_269_DATA
+ DDRSS3_PHY_270_DATA
+ DDRSS3_PHY_271_DATA
+ DDRSS3_PHY_272_DATA
+ DDRSS3_PHY_273_DATA
+ DDRSS3_PHY_274_DATA
+ DDRSS3_PHY_275_DATA
+ DDRSS3_PHY_276_DATA
+ DDRSS3_PHY_277_DATA
+ DDRSS3_PHY_278_DATA
+ DDRSS3_PHY_279_DATA
+ DDRSS3_PHY_280_DATA
+ DDRSS3_PHY_281_DATA
+ DDRSS3_PHY_282_DATA
+ DDRSS3_PHY_283_DATA
+ DDRSS3_PHY_284_DATA
+ DDRSS3_PHY_285_DATA
+ DDRSS3_PHY_286_DATA
+ DDRSS3_PHY_287_DATA
+ DDRSS3_PHY_288_DATA
+ DDRSS3_PHY_289_DATA
+ DDRSS3_PHY_290_DATA
+ DDRSS3_PHY_291_DATA
+ DDRSS3_PHY_292_DATA
+ DDRSS3_PHY_293_DATA
+ DDRSS3_PHY_294_DATA
+ DDRSS3_PHY_295_DATA
+ DDRSS3_PHY_296_DATA
+ DDRSS3_PHY_297_DATA
+ DDRSS3_PHY_298_DATA
+ DDRSS3_PHY_299_DATA
+ DDRSS3_PHY_300_DATA
+ DDRSS3_PHY_301_DATA
+ DDRSS3_PHY_302_DATA
+ DDRSS3_PHY_303_DATA
+ DDRSS3_PHY_304_DATA
+ DDRSS3_PHY_305_DATA
+ DDRSS3_PHY_306_DATA
+ DDRSS3_PHY_307_DATA
+ DDRSS3_PHY_308_DATA
+ DDRSS3_PHY_309_DATA
+ DDRSS3_PHY_310_DATA
+ DDRSS3_PHY_311_DATA
+ DDRSS3_PHY_312_DATA
+ DDRSS3_PHY_313_DATA
+ DDRSS3_PHY_314_DATA
+ DDRSS3_PHY_315_DATA
+ DDRSS3_PHY_316_DATA
+ DDRSS3_PHY_317_DATA
+ DDRSS3_PHY_318_DATA
+ DDRSS3_PHY_319_DATA
+ DDRSS3_PHY_320_DATA
+ DDRSS3_PHY_321_DATA
+ DDRSS3_PHY_322_DATA
+ DDRSS3_PHY_323_DATA
+ DDRSS3_PHY_324_DATA
+ DDRSS3_PHY_325_DATA
+ DDRSS3_PHY_326_DATA
+ DDRSS3_PHY_327_DATA
+ DDRSS3_PHY_328_DATA
+ DDRSS3_PHY_329_DATA
+ DDRSS3_PHY_330_DATA
+ DDRSS3_PHY_331_DATA
+ DDRSS3_PHY_332_DATA
+ DDRSS3_PHY_333_DATA
+ DDRSS3_PHY_334_DATA
+ DDRSS3_PHY_335_DATA
+ DDRSS3_PHY_336_DATA
+ DDRSS3_PHY_337_DATA
+ DDRSS3_PHY_338_DATA
+ DDRSS3_PHY_339_DATA
+ DDRSS3_PHY_340_DATA
+ DDRSS3_PHY_341_DATA
+ DDRSS3_PHY_342_DATA
+ DDRSS3_PHY_343_DATA
+ DDRSS3_PHY_344_DATA
+ DDRSS3_PHY_345_DATA
+ DDRSS3_PHY_346_DATA
+ DDRSS3_PHY_347_DATA
+ DDRSS3_PHY_348_DATA
+ DDRSS3_PHY_349_DATA
+ DDRSS3_PHY_350_DATA
+ DDRSS3_PHY_351_DATA
+ DDRSS3_PHY_352_DATA
+ DDRSS3_PHY_353_DATA
+ DDRSS3_PHY_354_DATA
+ DDRSS3_PHY_355_DATA
+ DDRSS3_PHY_356_DATA
+ DDRSS3_PHY_357_DATA
+ DDRSS3_PHY_358_DATA
+ DDRSS3_PHY_359_DATA
+ DDRSS3_PHY_360_DATA
+ DDRSS3_PHY_361_DATA
+ DDRSS3_PHY_362_DATA
+ DDRSS3_PHY_363_DATA
+ DDRSS3_PHY_364_DATA
+ DDRSS3_PHY_365_DATA
+ DDRSS3_PHY_366_DATA
+ DDRSS3_PHY_367_DATA
+ DDRSS3_PHY_368_DATA
+ DDRSS3_PHY_369_DATA
+ DDRSS3_PHY_370_DATA
+ DDRSS3_PHY_371_DATA
+ DDRSS3_PHY_372_DATA
+ DDRSS3_PHY_373_DATA
+ DDRSS3_PHY_374_DATA
+ DDRSS3_PHY_375_DATA
+ DDRSS3_PHY_376_DATA
+ DDRSS3_PHY_377_DATA
+ DDRSS3_PHY_378_DATA
+ DDRSS3_PHY_379_DATA
+ DDRSS3_PHY_380_DATA
+ DDRSS3_PHY_381_DATA
+ DDRSS3_PHY_382_DATA
+ DDRSS3_PHY_383_DATA
+ DDRSS3_PHY_384_DATA
+ DDRSS3_PHY_385_DATA
+ DDRSS3_PHY_386_DATA
+ DDRSS3_PHY_387_DATA
+ DDRSS3_PHY_388_DATA
+ DDRSS3_PHY_389_DATA
+ DDRSS3_PHY_390_DATA
+ DDRSS3_PHY_391_DATA
+ DDRSS3_PHY_392_DATA
+ DDRSS3_PHY_393_DATA
+ DDRSS3_PHY_394_DATA
+ DDRSS3_PHY_395_DATA
+ DDRSS3_PHY_396_DATA
+ DDRSS3_PHY_397_DATA
+ DDRSS3_PHY_398_DATA
+ DDRSS3_PHY_399_DATA
+ DDRSS3_PHY_400_DATA
+ DDRSS3_PHY_401_DATA
+ DDRSS3_PHY_402_DATA
+ DDRSS3_PHY_403_DATA
+ DDRSS3_PHY_404_DATA
+ DDRSS3_PHY_405_DATA
+ DDRSS3_PHY_406_DATA
+ DDRSS3_PHY_407_DATA
+ DDRSS3_PHY_408_DATA
+ DDRSS3_PHY_409_DATA
+ DDRSS3_PHY_410_DATA
+ DDRSS3_PHY_411_DATA
+ DDRSS3_PHY_412_DATA
+ DDRSS3_PHY_413_DATA
+ DDRSS3_PHY_414_DATA
+ DDRSS3_PHY_415_DATA
+ DDRSS3_PHY_416_DATA
+ DDRSS3_PHY_417_DATA
+ DDRSS3_PHY_418_DATA
+ DDRSS3_PHY_419_DATA
+ DDRSS3_PHY_420_DATA
+ DDRSS3_PHY_421_DATA
+ DDRSS3_PHY_422_DATA
+ DDRSS3_PHY_423_DATA
+ DDRSS3_PHY_424_DATA
+ DDRSS3_PHY_425_DATA
+ DDRSS3_PHY_426_DATA
+ DDRSS3_PHY_427_DATA
+ DDRSS3_PHY_428_DATA
+ DDRSS3_PHY_429_DATA
+ DDRSS3_PHY_430_DATA
+ DDRSS3_PHY_431_DATA
+ DDRSS3_PHY_432_DATA
+ DDRSS3_PHY_433_DATA
+ DDRSS3_PHY_434_DATA
+ DDRSS3_PHY_435_DATA
+ DDRSS3_PHY_436_DATA
+ DDRSS3_PHY_437_DATA
+ DDRSS3_PHY_438_DATA
+ DDRSS3_PHY_439_DATA
+ DDRSS3_PHY_440_DATA
+ DDRSS3_PHY_441_DATA
+ DDRSS3_PHY_442_DATA
+ DDRSS3_PHY_443_DATA
+ DDRSS3_PHY_444_DATA
+ DDRSS3_PHY_445_DATA
+ DDRSS3_PHY_446_DATA
+ DDRSS3_PHY_447_DATA
+ DDRSS3_PHY_448_DATA
+ DDRSS3_PHY_449_DATA
+ DDRSS3_PHY_450_DATA
+ DDRSS3_PHY_451_DATA
+ DDRSS3_PHY_452_DATA
+ DDRSS3_PHY_453_DATA
+ DDRSS3_PHY_454_DATA
+ DDRSS3_PHY_455_DATA
+ DDRSS3_PHY_456_DATA
+ DDRSS3_PHY_457_DATA
+ DDRSS3_PHY_458_DATA
+ DDRSS3_PHY_459_DATA
+ DDRSS3_PHY_460_DATA
+ DDRSS3_PHY_461_DATA
+ DDRSS3_PHY_462_DATA
+ DDRSS3_PHY_463_DATA
+ DDRSS3_PHY_464_DATA
+ DDRSS3_PHY_465_DATA
+ DDRSS3_PHY_466_DATA
+ DDRSS3_PHY_467_DATA
+ DDRSS3_PHY_468_DATA
+ DDRSS3_PHY_469_DATA
+ DDRSS3_PHY_470_DATA
+ DDRSS3_PHY_471_DATA
+ DDRSS3_PHY_472_DATA
+ DDRSS3_PHY_473_DATA
+ DDRSS3_PHY_474_DATA
+ DDRSS3_PHY_475_DATA
+ DDRSS3_PHY_476_DATA
+ DDRSS3_PHY_477_DATA
+ DDRSS3_PHY_478_DATA
+ DDRSS3_PHY_479_DATA
+ DDRSS3_PHY_480_DATA
+ DDRSS3_PHY_481_DATA
+ DDRSS3_PHY_482_DATA
+ DDRSS3_PHY_483_DATA
+ DDRSS3_PHY_484_DATA
+ DDRSS3_PHY_485_DATA
+ DDRSS3_PHY_486_DATA
+ DDRSS3_PHY_487_DATA
+ DDRSS3_PHY_488_DATA
+ DDRSS3_PHY_489_DATA
+ DDRSS3_PHY_490_DATA
+ DDRSS3_PHY_491_DATA
+ DDRSS3_PHY_492_DATA
+ DDRSS3_PHY_493_DATA
+ DDRSS3_PHY_494_DATA
+ DDRSS3_PHY_495_DATA
+ DDRSS3_PHY_496_DATA
+ DDRSS3_PHY_497_DATA
+ DDRSS3_PHY_498_DATA
+ DDRSS3_PHY_499_DATA
+ DDRSS3_PHY_500_DATA
+ DDRSS3_PHY_501_DATA
+ DDRSS3_PHY_502_DATA
+ DDRSS3_PHY_503_DATA
+ DDRSS3_PHY_504_DATA
+ DDRSS3_PHY_505_DATA
+ DDRSS3_PHY_506_DATA
+ DDRSS3_PHY_507_DATA
+ DDRSS3_PHY_508_DATA
+ DDRSS3_PHY_509_DATA
+ DDRSS3_PHY_510_DATA
+ DDRSS3_PHY_511_DATA
+ DDRSS3_PHY_512_DATA
+ DDRSS3_PHY_513_DATA
+ DDRSS3_PHY_514_DATA
+ DDRSS3_PHY_515_DATA
+ DDRSS3_PHY_516_DATA
+ DDRSS3_PHY_517_DATA
+ DDRSS3_PHY_518_DATA
+ DDRSS3_PHY_519_DATA
+ DDRSS3_PHY_520_DATA
+ DDRSS3_PHY_521_DATA
+ DDRSS3_PHY_522_DATA
+ DDRSS3_PHY_523_DATA
+ DDRSS3_PHY_524_DATA
+ DDRSS3_PHY_525_DATA
+ DDRSS3_PHY_526_DATA
+ DDRSS3_PHY_527_DATA
+ DDRSS3_PHY_528_DATA
+ DDRSS3_PHY_529_DATA
+ DDRSS3_PHY_530_DATA
+ DDRSS3_PHY_531_DATA
+ DDRSS3_PHY_532_DATA
+ DDRSS3_PHY_533_DATA
+ DDRSS3_PHY_534_DATA
+ DDRSS3_PHY_535_DATA
+ DDRSS3_PHY_536_DATA
+ DDRSS3_PHY_537_DATA
+ DDRSS3_PHY_538_DATA
+ DDRSS3_PHY_539_DATA
+ DDRSS3_PHY_540_DATA
+ DDRSS3_PHY_541_DATA
+ DDRSS3_PHY_542_DATA
+ DDRSS3_PHY_543_DATA
+ DDRSS3_PHY_544_DATA
+ DDRSS3_PHY_545_DATA
+ DDRSS3_PHY_546_DATA
+ DDRSS3_PHY_547_DATA
+ DDRSS3_PHY_548_DATA
+ DDRSS3_PHY_549_DATA
+ DDRSS3_PHY_550_DATA
+ DDRSS3_PHY_551_DATA
+ DDRSS3_PHY_552_DATA
+ DDRSS3_PHY_553_DATA
+ DDRSS3_PHY_554_DATA
+ DDRSS3_PHY_555_DATA
+ DDRSS3_PHY_556_DATA
+ DDRSS3_PHY_557_DATA
+ DDRSS3_PHY_558_DATA
+ DDRSS3_PHY_559_DATA
+ DDRSS3_PHY_560_DATA
+ DDRSS3_PHY_561_DATA
+ DDRSS3_PHY_562_DATA
+ DDRSS3_PHY_563_DATA
+ DDRSS3_PHY_564_DATA
+ DDRSS3_PHY_565_DATA
+ DDRSS3_PHY_566_DATA
+ DDRSS3_PHY_567_DATA
+ DDRSS3_PHY_568_DATA
+ DDRSS3_PHY_569_DATA
+ DDRSS3_PHY_570_DATA
+ DDRSS3_PHY_571_DATA
+ DDRSS3_PHY_572_DATA
+ DDRSS3_PHY_573_DATA
+ DDRSS3_PHY_574_DATA
+ DDRSS3_PHY_575_DATA
+ DDRSS3_PHY_576_DATA
+ DDRSS3_PHY_577_DATA
+ DDRSS3_PHY_578_DATA
+ DDRSS3_PHY_579_DATA
+ DDRSS3_PHY_580_DATA
+ DDRSS3_PHY_581_DATA
+ DDRSS3_PHY_582_DATA
+ DDRSS3_PHY_583_DATA
+ DDRSS3_PHY_584_DATA
+ DDRSS3_PHY_585_DATA
+ DDRSS3_PHY_586_DATA
+ DDRSS3_PHY_587_DATA
+ DDRSS3_PHY_588_DATA
+ DDRSS3_PHY_589_DATA
+ DDRSS3_PHY_590_DATA
+ DDRSS3_PHY_591_DATA
+ DDRSS3_PHY_592_DATA
+ DDRSS3_PHY_593_DATA
+ DDRSS3_PHY_594_DATA
+ DDRSS3_PHY_595_DATA
+ DDRSS3_PHY_596_DATA
+ DDRSS3_PHY_597_DATA
+ DDRSS3_PHY_598_DATA
+ DDRSS3_PHY_599_DATA
+ DDRSS3_PHY_600_DATA
+ DDRSS3_PHY_601_DATA
+ DDRSS3_PHY_602_DATA
+ DDRSS3_PHY_603_DATA
+ DDRSS3_PHY_604_DATA
+ DDRSS3_PHY_605_DATA
+ DDRSS3_PHY_606_DATA
+ DDRSS3_PHY_607_DATA
+ DDRSS3_PHY_608_DATA
+ DDRSS3_PHY_609_DATA
+ DDRSS3_PHY_610_DATA
+ DDRSS3_PHY_611_DATA
+ DDRSS3_PHY_612_DATA
+ DDRSS3_PHY_613_DATA
+ DDRSS3_PHY_614_DATA
+ DDRSS3_PHY_615_DATA
+ DDRSS3_PHY_616_DATA
+ DDRSS3_PHY_617_DATA
+ DDRSS3_PHY_618_DATA
+ DDRSS3_PHY_619_DATA
+ DDRSS3_PHY_620_DATA
+ DDRSS3_PHY_621_DATA
+ DDRSS3_PHY_622_DATA
+ DDRSS3_PHY_623_DATA
+ DDRSS3_PHY_624_DATA
+ DDRSS3_PHY_625_DATA
+ DDRSS3_PHY_626_DATA
+ DDRSS3_PHY_627_DATA
+ DDRSS3_PHY_628_DATA
+ DDRSS3_PHY_629_DATA
+ DDRSS3_PHY_630_DATA
+ DDRSS3_PHY_631_DATA
+ DDRSS3_PHY_632_DATA
+ DDRSS3_PHY_633_DATA
+ DDRSS3_PHY_634_DATA
+ DDRSS3_PHY_635_DATA
+ DDRSS3_PHY_636_DATA
+ DDRSS3_PHY_637_DATA
+ DDRSS3_PHY_638_DATA
+ DDRSS3_PHY_639_DATA
+ DDRSS3_PHY_640_DATA
+ DDRSS3_PHY_641_DATA
+ DDRSS3_PHY_642_DATA
+ DDRSS3_PHY_643_DATA
+ DDRSS3_PHY_644_DATA
+ DDRSS3_PHY_645_DATA
+ DDRSS3_PHY_646_DATA
+ DDRSS3_PHY_647_DATA
+ DDRSS3_PHY_648_DATA
+ DDRSS3_PHY_649_DATA
+ DDRSS3_PHY_650_DATA
+ DDRSS3_PHY_651_DATA
+ DDRSS3_PHY_652_DATA
+ DDRSS3_PHY_653_DATA
+ DDRSS3_PHY_654_DATA
+ DDRSS3_PHY_655_DATA
+ DDRSS3_PHY_656_DATA
+ DDRSS3_PHY_657_DATA
+ DDRSS3_PHY_658_DATA
+ DDRSS3_PHY_659_DATA
+ DDRSS3_PHY_660_DATA
+ DDRSS3_PHY_661_DATA
+ DDRSS3_PHY_662_DATA
+ DDRSS3_PHY_663_DATA
+ DDRSS3_PHY_664_DATA
+ DDRSS3_PHY_665_DATA
+ DDRSS3_PHY_666_DATA
+ DDRSS3_PHY_667_DATA
+ DDRSS3_PHY_668_DATA
+ DDRSS3_PHY_669_DATA
+ DDRSS3_PHY_670_DATA
+ DDRSS3_PHY_671_DATA
+ DDRSS3_PHY_672_DATA
+ DDRSS3_PHY_673_DATA
+ DDRSS3_PHY_674_DATA
+ DDRSS3_PHY_675_DATA
+ DDRSS3_PHY_676_DATA
+ DDRSS3_PHY_677_DATA
+ DDRSS3_PHY_678_DATA
+ DDRSS3_PHY_679_DATA
+ DDRSS3_PHY_680_DATA
+ DDRSS3_PHY_681_DATA
+ DDRSS3_PHY_682_DATA
+ DDRSS3_PHY_683_DATA
+ DDRSS3_PHY_684_DATA
+ DDRSS3_PHY_685_DATA
+ DDRSS3_PHY_686_DATA
+ DDRSS3_PHY_687_DATA
+ DDRSS3_PHY_688_DATA
+ DDRSS3_PHY_689_DATA
+ DDRSS3_PHY_690_DATA
+ DDRSS3_PHY_691_DATA
+ DDRSS3_PHY_692_DATA
+ DDRSS3_PHY_693_DATA
+ DDRSS3_PHY_694_DATA
+ DDRSS3_PHY_695_DATA
+ DDRSS3_PHY_696_DATA
+ DDRSS3_PHY_697_DATA
+ DDRSS3_PHY_698_DATA
+ DDRSS3_PHY_699_DATA
+ DDRSS3_PHY_700_DATA
+ DDRSS3_PHY_701_DATA
+ DDRSS3_PHY_702_DATA
+ DDRSS3_PHY_703_DATA
+ DDRSS3_PHY_704_DATA
+ DDRSS3_PHY_705_DATA
+ DDRSS3_PHY_706_DATA
+ DDRSS3_PHY_707_DATA
+ DDRSS3_PHY_708_DATA
+ DDRSS3_PHY_709_DATA
+ DDRSS3_PHY_710_DATA
+ DDRSS3_PHY_711_DATA
+ DDRSS3_PHY_712_DATA
+ DDRSS3_PHY_713_DATA
+ DDRSS3_PHY_714_DATA
+ DDRSS3_PHY_715_DATA
+ DDRSS3_PHY_716_DATA
+ DDRSS3_PHY_717_DATA
+ DDRSS3_PHY_718_DATA
+ DDRSS3_PHY_719_DATA
+ DDRSS3_PHY_720_DATA
+ DDRSS3_PHY_721_DATA
+ DDRSS3_PHY_722_DATA
+ DDRSS3_PHY_723_DATA
+ DDRSS3_PHY_724_DATA
+ DDRSS3_PHY_725_DATA
+ DDRSS3_PHY_726_DATA
+ DDRSS3_PHY_727_DATA
+ DDRSS3_PHY_728_DATA
+ DDRSS3_PHY_729_DATA
+ DDRSS3_PHY_730_DATA
+ DDRSS3_PHY_731_DATA
+ DDRSS3_PHY_732_DATA
+ DDRSS3_PHY_733_DATA
+ DDRSS3_PHY_734_DATA
+ DDRSS3_PHY_735_DATA
+ DDRSS3_PHY_736_DATA
+ DDRSS3_PHY_737_DATA
+ DDRSS3_PHY_738_DATA
+ DDRSS3_PHY_739_DATA
+ DDRSS3_PHY_740_DATA
+ DDRSS3_PHY_741_DATA
+ DDRSS3_PHY_742_DATA
+ DDRSS3_PHY_743_DATA
+ DDRSS3_PHY_744_DATA
+ DDRSS3_PHY_745_DATA
+ DDRSS3_PHY_746_DATA
+ DDRSS3_PHY_747_DATA
+ DDRSS3_PHY_748_DATA
+ DDRSS3_PHY_749_DATA
+ DDRSS3_PHY_750_DATA
+ DDRSS3_PHY_751_DATA
+ DDRSS3_PHY_752_DATA
+ DDRSS3_PHY_753_DATA
+ DDRSS3_PHY_754_DATA
+ DDRSS3_PHY_755_DATA
+ DDRSS3_PHY_756_DATA
+ DDRSS3_PHY_757_DATA
+ DDRSS3_PHY_758_DATA
+ DDRSS3_PHY_759_DATA
+ DDRSS3_PHY_760_DATA
+ DDRSS3_PHY_761_DATA
+ DDRSS3_PHY_762_DATA
+ DDRSS3_PHY_763_DATA
+ DDRSS3_PHY_764_DATA
+ DDRSS3_PHY_765_DATA
+ DDRSS3_PHY_766_DATA
+ DDRSS3_PHY_767_DATA
+ DDRSS3_PHY_768_DATA
+ DDRSS3_PHY_769_DATA
+ DDRSS3_PHY_770_DATA
+ DDRSS3_PHY_771_DATA
+ DDRSS3_PHY_772_DATA
+ DDRSS3_PHY_773_DATA
+ DDRSS3_PHY_774_DATA
+ DDRSS3_PHY_775_DATA
+ DDRSS3_PHY_776_DATA
+ DDRSS3_PHY_777_DATA
+ DDRSS3_PHY_778_DATA
+ DDRSS3_PHY_779_DATA
+ DDRSS3_PHY_780_DATA
+ DDRSS3_PHY_781_DATA
+ DDRSS3_PHY_782_DATA
+ DDRSS3_PHY_783_DATA
+ DDRSS3_PHY_784_DATA
+ DDRSS3_PHY_785_DATA
+ DDRSS3_PHY_786_DATA
+ DDRSS3_PHY_787_DATA
+ DDRSS3_PHY_788_DATA
+ DDRSS3_PHY_789_DATA
+ DDRSS3_PHY_790_DATA
+ DDRSS3_PHY_791_DATA
+ DDRSS3_PHY_792_DATA
+ DDRSS3_PHY_793_DATA
+ DDRSS3_PHY_794_DATA
+ DDRSS3_PHY_795_DATA
+ DDRSS3_PHY_796_DATA
+ DDRSS3_PHY_797_DATA
+ DDRSS3_PHY_798_DATA
+ DDRSS3_PHY_799_DATA
+ DDRSS3_PHY_800_DATA
+ DDRSS3_PHY_801_DATA
+ DDRSS3_PHY_802_DATA
+ DDRSS3_PHY_803_DATA
+ DDRSS3_PHY_804_DATA
+ DDRSS3_PHY_805_DATA
+ DDRSS3_PHY_806_DATA
+ DDRSS3_PHY_807_DATA
+ DDRSS3_PHY_808_DATA
+ DDRSS3_PHY_809_DATA
+ DDRSS3_PHY_810_DATA
+ DDRSS3_PHY_811_DATA
+ DDRSS3_PHY_812_DATA
+ DDRSS3_PHY_813_DATA
+ DDRSS3_PHY_814_DATA
+ DDRSS3_PHY_815_DATA
+ DDRSS3_PHY_816_DATA
+ DDRSS3_PHY_817_DATA
+ DDRSS3_PHY_818_DATA
+ DDRSS3_PHY_819_DATA
+ DDRSS3_PHY_820_DATA
+ DDRSS3_PHY_821_DATA
+ DDRSS3_PHY_822_DATA
+ DDRSS3_PHY_823_DATA
+ DDRSS3_PHY_824_DATA
+ DDRSS3_PHY_825_DATA
+ DDRSS3_PHY_826_DATA
+ DDRSS3_PHY_827_DATA
+ DDRSS3_PHY_828_DATA
+ DDRSS3_PHY_829_DATA
+ DDRSS3_PHY_830_DATA
+ DDRSS3_PHY_831_DATA
+ DDRSS3_PHY_832_DATA
+ DDRSS3_PHY_833_DATA
+ DDRSS3_PHY_834_DATA
+ DDRSS3_PHY_835_DATA
+ DDRSS3_PHY_836_DATA
+ DDRSS3_PHY_837_DATA
+ DDRSS3_PHY_838_DATA
+ DDRSS3_PHY_839_DATA
+ DDRSS3_PHY_840_DATA
+ DDRSS3_PHY_841_DATA
+ DDRSS3_PHY_842_DATA
+ DDRSS3_PHY_843_DATA
+ DDRSS3_PHY_844_DATA
+ DDRSS3_PHY_845_DATA
+ DDRSS3_PHY_846_DATA
+ DDRSS3_PHY_847_DATA
+ DDRSS3_PHY_848_DATA
+ DDRSS3_PHY_849_DATA
+ DDRSS3_PHY_850_DATA
+ DDRSS3_PHY_851_DATA
+ DDRSS3_PHY_852_DATA
+ DDRSS3_PHY_853_DATA
+ DDRSS3_PHY_854_DATA
+ DDRSS3_PHY_855_DATA
+ DDRSS3_PHY_856_DATA
+ DDRSS3_PHY_857_DATA
+ DDRSS3_PHY_858_DATA
+ DDRSS3_PHY_859_DATA
+ DDRSS3_PHY_860_DATA
+ DDRSS3_PHY_861_DATA
+ DDRSS3_PHY_862_DATA
+ DDRSS3_PHY_863_DATA
+ DDRSS3_PHY_864_DATA
+ DDRSS3_PHY_865_DATA
+ DDRSS3_PHY_866_DATA
+ DDRSS3_PHY_867_DATA
+ DDRSS3_PHY_868_DATA
+ DDRSS3_PHY_869_DATA
+ DDRSS3_PHY_870_DATA
+ DDRSS3_PHY_871_DATA
+ DDRSS3_PHY_872_DATA
+ DDRSS3_PHY_873_DATA
+ DDRSS3_PHY_874_DATA
+ DDRSS3_PHY_875_DATA
+ DDRSS3_PHY_876_DATA
+ DDRSS3_PHY_877_DATA
+ DDRSS3_PHY_878_DATA
+ DDRSS3_PHY_879_DATA
+ DDRSS3_PHY_880_DATA
+ DDRSS3_PHY_881_DATA
+ DDRSS3_PHY_882_DATA
+ DDRSS3_PHY_883_DATA
+ DDRSS3_PHY_884_DATA
+ DDRSS3_PHY_885_DATA
+ DDRSS3_PHY_886_DATA
+ DDRSS3_PHY_887_DATA
+ DDRSS3_PHY_888_DATA
+ DDRSS3_PHY_889_DATA
+ DDRSS3_PHY_890_DATA
+ DDRSS3_PHY_891_DATA
+ DDRSS3_PHY_892_DATA
+ DDRSS3_PHY_893_DATA
+ DDRSS3_PHY_894_DATA
+ DDRSS3_PHY_895_DATA
+ DDRSS3_PHY_896_DATA
+ DDRSS3_PHY_897_DATA
+ DDRSS3_PHY_898_DATA
+ DDRSS3_PHY_899_DATA
+ DDRSS3_PHY_900_DATA
+ DDRSS3_PHY_901_DATA
+ DDRSS3_PHY_902_DATA
+ DDRSS3_PHY_903_DATA
+ DDRSS3_PHY_904_DATA
+ DDRSS3_PHY_905_DATA
+ DDRSS3_PHY_906_DATA
+ DDRSS3_PHY_907_DATA
+ DDRSS3_PHY_908_DATA
+ DDRSS3_PHY_909_DATA
+ DDRSS3_PHY_910_DATA
+ DDRSS3_PHY_911_DATA
+ DDRSS3_PHY_912_DATA
+ DDRSS3_PHY_913_DATA
+ DDRSS3_PHY_914_DATA
+ DDRSS3_PHY_915_DATA
+ DDRSS3_PHY_916_DATA
+ DDRSS3_PHY_917_DATA
+ DDRSS3_PHY_918_DATA
+ DDRSS3_PHY_919_DATA
+ DDRSS3_PHY_920_DATA
+ DDRSS3_PHY_921_DATA
+ DDRSS3_PHY_922_DATA
+ DDRSS3_PHY_923_DATA
+ DDRSS3_PHY_924_DATA
+ DDRSS3_PHY_925_DATA
+ DDRSS3_PHY_926_DATA
+ DDRSS3_PHY_927_DATA
+ DDRSS3_PHY_928_DATA
+ DDRSS3_PHY_929_DATA
+ DDRSS3_PHY_930_DATA
+ DDRSS3_PHY_931_DATA
+ DDRSS3_PHY_932_DATA
+ DDRSS3_PHY_933_DATA
+ DDRSS3_PHY_934_DATA
+ DDRSS3_PHY_935_DATA
+ DDRSS3_PHY_936_DATA
+ DDRSS3_PHY_937_DATA
+ DDRSS3_PHY_938_DATA
+ DDRSS3_PHY_939_DATA
+ DDRSS3_PHY_940_DATA
+ DDRSS3_PHY_941_DATA
+ DDRSS3_PHY_942_DATA
+ DDRSS3_PHY_943_DATA
+ DDRSS3_PHY_944_DATA
+ DDRSS3_PHY_945_DATA
+ DDRSS3_PHY_946_DATA
+ DDRSS3_PHY_947_DATA
+ DDRSS3_PHY_948_DATA
+ DDRSS3_PHY_949_DATA
+ DDRSS3_PHY_950_DATA
+ DDRSS3_PHY_951_DATA
+ DDRSS3_PHY_952_DATA
+ DDRSS3_PHY_953_DATA
+ DDRSS3_PHY_954_DATA
+ DDRSS3_PHY_955_DATA
+ DDRSS3_PHY_956_DATA
+ DDRSS3_PHY_957_DATA
+ DDRSS3_PHY_958_DATA
+ DDRSS3_PHY_959_DATA
+ DDRSS3_PHY_960_DATA
+ DDRSS3_PHY_961_DATA
+ DDRSS3_PHY_962_DATA
+ DDRSS3_PHY_963_DATA
+ DDRSS3_PHY_964_DATA
+ DDRSS3_PHY_965_DATA
+ DDRSS3_PHY_966_DATA
+ DDRSS3_PHY_967_DATA
+ DDRSS3_PHY_968_DATA
+ DDRSS3_PHY_969_DATA
+ DDRSS3_PHY_970_DATA
+ DDRSS3_PHY_971_DATA
+ DDRSS3_PHY_972_DATA
+ DDRSS3_PHY_973_DATA
+ DDRSS3_PHY_974_DATA
+ DDRSS3_PHY_975_DATA
+ DDRSS3_PHY_976_DATA
+ DDRSS3_PHY_977_DATA
+ DDRSS3_PHY_978_DATA
+ DDRSS3_PHY_979_DATA
+ DDRSS3_PHY_980_DATA
+ DDRSS3_PHY_981_DATA
+ DDRSS3_PHY_982_DATA
+ DDRSS3_PHY_983_DATA
+ DDRSS3_PHY_984_DATA
+ DDRSS3_PHY_985_DATA
+ DDRSS3_PHY_986_DATA
+ DDRSS3_PHY_987_DATA
+ DDRSS3_PHY_988_DATA
+ DDRSS3_PHY_989_DATA
+ DDRSS3_PHY_990_DATA
+ DDRSS3_PHY_991_DATA
+ DDRSS3_PHY_992_DATA
+ DDRSS3_PHY_993_DATA
+ DDRSS3_PHY_994_DATA
+ DDRSS3_PHY_995_DATA
+ DDRSS3_PHY_996_DATA
+ DDRSS3_PHY_997_DATA
+ DDRSS3_PHY_998_DATA
+ DDRSS3_PHY_999_DATA
+ DDRSS3_PHY_1000_DATA
+ DDRSS3_PHY_1001_DATA
+ DDRSS3_PHY_1002_DATA
+ DDRSS3_PHY_1003_DATA
+ DDRSS3_PHY_1004_DATA
+ DDRSS3_PHY_1005_DATA
+ DDRSS3_PHY_1006_DATA
+ DDRSS3_PHY_1007_DATA
+ DDRSS3_PHY_1008_DATA
+ DDRSS3_PHY_1009_DATA
+ DDRSS3_PHY_1010_DATA
+ DDRSS3_PHY_1011_DATA
+ DDRSS3_PHY_1012_DATA
+ DDRSS3_PHY_1013_DATA
+ DDRSS3_PHY_1014_DATA
+ DDRSS3_PHY_1015_DATA
+ DDRSS3_PHY_1016_DATA
+ DDRSS3_PHY_1017_DATA
+ DDRSS3_PHY_1018_DATA
+ DDRSS3_PHY_1019_DATA
+ DDRSS3_PHY_1020_DATA
+ DDRSS3_PHY_1021_DATA
+ DDRSS3_PHY_1022_DATA
+ DDRSS3_PHY_1023_DATA
+ DDRSS3_PHY_1024_DATA
+ DDRSS3_PHY_1025_DATA
+ DDRSS3_PHY_1026_DATA
+ DDRSS3_PHY_1027_DATA
+ DDRSS3_PHY_1028_DATA
+ DDRSS3_PHY_1029_DATA
+ DDRSS3_PHY_1030_DATA
+ DDRSS3_PHY_1031_DATA
+ DDRSS3_PHY_1032_DATA
+ DDRSS3_PHY_1033_DATA
+ DDRSS3_PHY_1034_DATA
+ DDRSS3_PHY_1035_DATA
+ DDRSS3_PHY_1036_DATA
+ DDRSS3_PHY_1037_DATA
+ DDRSS3_PHY_1038_DATA
+ DDRSS3_PHY_1039_DATA
+ DDRSS3_PHY_1040_DATA
+ DDRSS3_PHY_1041_DATA
+ DDRSS3_PHY_1042_DATA
+ DDRSS3_PHY_1043_DATA
+ DDRSS3_PHY_1044_DATA
+ DDRSS3_PHY_1045_DATA
+ DDRSS3_PHY_1046_DATA
+ DDRSS3_PHY_1047_DATA
+ DDRSS3_PHY_1048_DATA
+ DDRSS3_PHY_1049_DATA
+ DDRSS3_PHY_1050_DATA
+ DDRSS3_PHY_1051_DATA
+ DDRSS3_PHY_1052_DATA
+ DDRSS3_PHY_1053_DATA
+ DDRSS3_PHY_1054_DATA
+ DDRSS3_PHY_1055_DATA
+ DDRSS3_PHY_1056_DATA
+ DDRSS3_PHY_1057_DATA
+ DDRSS3_PHY_1058_DATA
+ DDRSS3_PHY_1059_DATA
+ DDRSS3_PHY_1060_DATA
+ DDRSS3_PHY_1061_DATA
+ DDRSS3_PHY_1062_DATA
+ DDRSS3_PHY_1063_DATA
+ DDRSS3_PHY_1064_DATA
+ DDRSS3_PHY_1065_DATA
+ DDRSS3_PHY_1066_DATA
+ DDRSS3_PHY_1067_DATA
+ DDRSS3_PHY_1068_DATA
+ DDRSS3_PHY_1069_DATA
+ DDRSS3_PHY_1070_DATA
+ DDRSS3_PHY_1071_DATA
+ DDRSS3_PHY_1072_DATA
+ DDRSS3_PHY_1073_DATA
+ DDRSS3_PHY_1074_DATA
+ DDRSS3_PHY_1075_DATA
+ DDRSS3_PHY_1076_DATA
+ DDRSS3_PHY_1077_DATA
+ DDRSS3_PHY_1078_DATA
+ DDRSS3_PHY_1079_DATA
+ DDRSS3_PHY_1080_DATA
+ DDRSS3_PHY_1081_DATA
+ DDRSS3_PHY_1082_DATA
+ DDRSS3_PHY_1083_DATA
+ DDRSS3_PHY_1084_DATA
+ DDRSS3_PHY_1085_DATA
+ DDRSS3_PHY_1086_DATA
+ DDRSS3_PHY_1087_DATA
+ DDRSS3_PHY_1088_DATA
+ DDRSS3_PHY_1089_DATA
+ DDRSS3_PHY_1090_DATA
+ DDRSS3_PHY_1091_DATA
+ DDRSS3_PHY_1092_DATA
+ DDRSS3_PHY_1093_DATA
+ DDRSS3_PHY_1094_DATA
+ DDRSS3_PHY_1095_DATA
+ DDRSS3_PHY_1096_DATA
+ DDRSS3_PHY_1097_DATA
+ DDRSS3_PHY_1098_DATA
+ DDRSS3_PHY_1099_DATA
+ DDRSS3_PHY_1100_DATA
+ DDRSS3_PHY_1101_DATA
+ DDRSS3_PHY_1102_DATA
+ DDRSS3_PHY_1103_DATA
+ DDRSS3_PHY_1104_DATA
+ DDRSS3_PHY_1105_DATA
+ DDRSS3_PHY_1106_DATA
+ DDRSS3_PHY_1107_DATA
+ DDRSS3_PHY_1108_DATA
+ DDRSS3_PHY_1109_DATA
+ DDRSS3_PHY_1110_DATA
+ DDRSS3_PHY_1111_DATA
+ DDRSS3_PHY_1112_DATA
+ DDRSS3_PHY_1113_DATA
+ DDRSS3_PHY_1114_DATA
+ DDRSS3_PHY_1115_DATA
+ DDRSS3_PHY_1116_DATA
+ DDRSS3_PHY_1117_DATA
+ DDRSS3_PHY_1118_DATA
+ DDRSS3_PHY_1119_DATA
+ DDRSS3_PHY_1120_DATA
+ DDRSS3_PHY_1121_DATA
+ DDRSS3_PHY_1122_DATA
+ DDRSS3_PHY_1123_DATA
+ DDRSS3_PHY_1124_DATA
+ DDRSS3_PHY_1125_DATA
+ DDRSS3_PHY_1126_DATA
+ DDRSS3_PHY_1127_DATA
+ DDRSS3_PHY_1128_DATA
+ DDRSS3_PHY_1129_DATA
+ DDRSS3_PHY_1130_DATA
+ DDRSS3_PHY_1131_DATA
+ DDRSS3_PHY_1132_DATA
+ DDRSS3_PHY_1133_DATA
+ DDRSS3_PHY_1134_DATA
+ DDRSS3_PHY_1135_DATA
+ DDRSS3_PHY_1136_DATA
+ DDRSS3_PHY_1137_DATA
+ DDRSS3_PHY_1138_DATA
+ DDRSS3_PHY_1139_DATA
+ DDRSS3_PHY_1140_DATA
+ DDRSS3_PHY_1141_DATA
+ DDRSS3_PHY_1142_DATA
+ DDRSS3_PHY_1143_DATA
+ DDRSS3_PHY_1144_DATA
+ DDRSS3_PHY_1145_DATA
+ DDRSS3_PHY_1146_DATA
+ DDRSS3_PHY_1147_DATA
+ DDRSS3_PHY_1148_DATA
+ DDRSS3_PHY_1149_DATA
+ DDRSS3_PHY_1150_DATA
+ DDRSS3_PHY_1151_DATA
+ DDRSS3_PHY_1152_DATA
+ DDRSS3_PHY_1153_DATA
+ DDRSS3_PHY_1154_DATA
+ DDRSS3_PHY_1155_DATA
+ DDRSS3_PHY_1156_DATA
+ DDRSS3_PHY_1157_DATA
+ DDRSS3_PHY_1158_DATA
+ DDRSS3_PHY_1159_DATA
+ DDRSS3_PHY_1160_DATA
+ DDRSS3_PHY_1161_DATA
+ DDRSS3_PHY_1162_DATA
+ DDRSS3_PHY_1163_DATA
+ DDRSS3_PHY_1164_DATA
+ DDRSS3_PHY_1165_DATA
+ DDRSS3_PHY_1166_DATA
+ DDRSS3_PHY_1167_DATA
+ DDRSS3_PHY_1168_DATA
+ DDRSS3_PHY_1169_DATA
+ DDRSS3_PHY_1170_DATA
+ DDRSS3_PHY_1171_DATA
+ DDRSS3_PHY_1172_DATA
+ DDRSS3_PHY_1173_DATA
+ DDRSS3_PHY_1174_DATA
+ DDRSS3_PHY_1175_DATA
+ DDRSS3_PHY_1176_DATA
+ DDRSS3_PHY_1177_DATA
+ DDRSS3_PHY_1178_DATA
+ DDRSS3_PHY_1179_DATA
+ DDRSS3_PHY_1180_DATA
+ DDRSS3_PHY_1181_DATA
+ DDRSS3_PHY_1182_DATA
+ DDRSS3_PHY_1183_DATA
+ DDRSS3_PHY_1184_DATA
+ DDRSS3_PHY_1185_DATA
+ DDRSS3_PHY_1186_DATA
+ DDRSS3_PHY_1187_DATA
+ DDRSS3_PHY_1188_DATA
+ DDRSS3_PHY_1189_DATA
+ DDRSS3_PHY_1190_DATA
+ DDRSS3_PHY_1191_DATA
+ DDRSS3_PHY_1192_DATA
+ DDRSS3_PHY_1193_DATA
+ DDRSS3_PHY_1194_DATA
+ DDRSS3_PHY_1195_DATA
+ DDRSS3_PHY_1196_DATA
+ DDRSS3_PHY_1197_DATA
+ DDRSS3_PHY_1198_DATA
+ DDRSS3_PHY_1199_DATA
+ DDRSS3_PHY_1200_DATA
+ DDRSS3_PHY_1201_DATA
+ DDRSS3_PHY_1202_DATA
+ DDRSS3_PHY_1203_DATA
+ DDRSS3_PHY_1204_DATA
+ DDRSS3_PHY_1205_DATA
+ DDRSS3_PHY_1206_DATA
+ DDRSS3_PHY_1207_DATA
+ DDRSS3_PHY_1208_DATA
+ DDRSS3_PHY_1209_DATA
+ DDRSS3_PHY_1210_DATA
+ DDRSS3_PHY_1211_DATA
+ DDRSS3_PHY_1212_DATA
+ DDRSS3_PHY_1213_DATA
+ DDRSS3_PHY_1214_DATA
+ DDRSS3_PHY_1215_DATA
+ DDRSS3_PHY_1216_DATA
+ DDRSS3_PHY_1217_DATA
+ DDRSS3_PHY_1218_DATA
+ DDRSS3_PHY_1219_DATA
+ DDRSS3_PHY_1220_DATA
+ DDRSS3_PHY_1221_DATA
+ DDRSS3_PHY_1222_DATA
+ DDRSS3_PHY_1223_DATA
+ DDRSS3_PHY_1224_DATA
+ DDRSS3_PHY_1225_DATA
+ DDRSS3_PHY_1226_DATA
+ DDRSS3_PHY_1227_DATA
+ DDRSS3_PHY_1228_DATA
+ DDRSS3_PHY_1229_DATA
+ DDRSS3_PHY_1230_DATA
+ DDRSS3_PHY_1231_DATA
+ DDRSS3_PHY_1232_DATA
+ DDRSS3_PHY_1233_DATA
+ DDRSS3_PHY_1234_DATA
+ DDRSS3_PHY_1235_DATA
+ DDRSS3_PHY_1236_DATA
+ DDRSS3_PHY_1237_DATA
+ DDRSS3_PHY_1238_DATA
+ DDRSS3_PHY_1239_DATA
+ DDRSS3_PHY_1240_DATA
+ DDRSS3_PHY_1241_DATA
+ DDRSS3_PHY_1242_DATA
+ DDRSS3_PHY_1243_DATA
+ DDRSS3_PHY_1244_DATA
+ DDRSS3_PHY_1245_DATA
+ DDRSS3_PHY_1246_DATA
+ DDRSS3_PHY_1247_DATA
+ DDRSS3_PHY_1248_DATA
+ DDRSS3_PHY_1249_DATA
+ DDRSS3_PHY_1250_DATA
+ DDRSS3_PHY_1251_DATA
+ DDRSS3_PHY_1252_DATA
+ DDRSS3_PHY_1253_DATA
+ DDRSS3_PHY_1254_DATA
+ DDRSS3_PHY_1255_DATA
+ DDRSS3_PHY_1256_DATA
+ DDRSS3_PHY_1257_DATA
+ DDRSS3_PHY_1258_DATA
+ DDRSS3_PHY_1259_DATA
+ DDRSS3_PHY_1260_DATA
+ DDRSS3_PHY_1261_DATA
+ DDRSS3_PHY_1262_DATA
+ DDRSS3_PHY_1263_DATA
+ DDRSS3_PHY_1264_DATA
+ DDRSS3_PHY_1265_DATA
+ DDRSS3_PHY_1266_DATA
+ DDRSS3_PHY_1267_DATA
+ DDRSS3_PHY_1268_DATA
+ DDRSS3_PHY_1269_DATA
+ DDRSS3_PHY_1270_DATA
+ DDRSS3_PHY_1271_DATA
+ DDRSS3_PHY_1272_DATA
+ DDRSS3_PHY_1273_DATA
+ DDRSS3_PHY_1274_DATA
+ DDRSS3_PHY_1275_DATA
+ DDRSS3_PHY_1276_DATA
+ DDRSS3_PHY_1277_DATA
+ DDRSS3_PHY_1278_DATA
+ DDRSS3_PHY_1279_DATA
+ DDRSS3_PHY_1280_DATA
+ DDRSS3_PHY_1281_DATA
+ DDRSS3_PHY_1282_DATA
+ DDRSS3_PHY_1283_DATA
+ DDRSS3_PHY_1284_DATA
+ DDRSS3_PHY_1285_DATA
+ DDRSS3_PHY_1286_DATA
+ DDRSS3_PHY_1287_DATA
+ DDRSS3_PHY_1288_DATA
+ DDRSS3_PHY_1289_DATA
+ DDRSS3_PHY_1290_DATA
+ DDRSS3_PHY_1291_DATA
+ DDRSS3_PHY_1292_DATA
+ DDRSS3_PHY_1293_DATA
+ DDRSS3_PHY_1294_DATA
+ DDRSS3_PHY_1295_DATA
+ DDRSS3_PHY_1296_DATA
+ DDRSS3_PHY_1297_DATA
+ DDRSS3_PHY_1298_DATA
+ DDRSS3_PHY_1299_DATA
+ DDRSS3_PHY_1300_DATA
+ DDRSS3_PHY_1301_DATA
+ DDRSS3_PHY_1302_DATA
+ DDRSS3_PHY_1303_DATA
+ DDRSS3_PHY_1304_DATA
+ DDRSS3_PHY_1305_DATA
+ DDRSS3_PHY_1306_DATA
+ DDRSS3_PHY_1307_DATA
+ DDRSS3_PHY_1308_DATA
+ DDRSS3_PHY_1309_DATA
+ DDRSS3_PHY_1310_DATA
+ DDRSS3_PHY_1311_DATA
+ DDRSS3_PHY_1312_DATA
+ DDRSS3_PHY_1313_DATA
+ DDRSS3_PHY_1314_DATA
+ DDRSS3_PHY_1315_DATA
+ DDRSS3_PHY_1316_DATA
+ DDRSS3_PHY_1317_DATA
+ DDRSS3_PHY_1318_DATA
+ DDRSS3_PHY_1319_DATA
+ DDRSS3_PHY_1320_DATA
+ DDRSS3_PHY_1321_DATA
+ DDRSS3_PHY_1322_DATA
+ DDRSS3_PHY_1323_DATA
+ DDRSS3_PHY_1324_DATA
+ DDRSS3_PHY_1325_DATA
+ DDRSS3_PHY_1326_DATA
+ DDRSS3_PHY_1327_DATA
+ DDRSS3_PHY_1328_DATA
+ DDRSS3_PHY_1329_DATA
+ DDRSS3_PHY_1330_DATA
+ DDRSS3_PHY_1331_DATA
+ DDRSS3_PHY_1332_DATA
+ DDRSS3_PHY_1333_DATA
+ DDRSS3_PHY_1334_DATA
+ DDRSS3_PHY_1335_DATA
+ DDRSS3_PHY_1336_DATA
+ DDRSS3_PHY_1337_DATA
+ DDRSS3_PHY_1338_DATA
+ DDRSS3_PHY_1339_DATA
+ DDRSS3_PHY_1340_DATA
+ DDRSS3_PHY_1341_DATA
+ DDRSS3_PHY_1342_DATA
+ DDRSS3_PHY_1343_DATA
+ DDRSS3_PHY_1344_DATA
+ DDRSS3_PHY_1345_DATA
+ DDRSS3_PHY_1346_DATA
+ DDRSS3_PHY_1347_DATA
+ DDRSS3_PHY_1348_DATA
+ DDRSS3_PHY_1349_DATA
+ DDRSS3_PHY_1350_DATA
+ DDRSS3_PHY_1351_DATA
+ DDRSS3_PHY_1352_DATA
+ DDRSS3_PHY_1353_DATA
+ DDRSS3_PHY_1354_DATA
+ DDRSS3_PHY_1355_DATA
+ DDRSS3_PHY_1356_DATA
+ DDRSS3_PHY_1357_DATA
+ DDRSS3_PHY_1358_DATA
+ DDRSS3_PHY_1359_DATA
+ DDRSS3_PHY_1360_DATA
+ DDRSS3_PHY_1361_DATA
+ DDRSS3_PHY_1362_DATA
+ DDRSS3_PHY_1363_DATA
+ DDRSS3_PHY_1364_DATA
+ DDRSS3_PHY_1365_DATA
+ DDRSS3_PHY_1366_DATA
+ DDRSS3_PHY_1367_DATA
+ DDRSS3_PHY_1368_DATA
+ DDRSS3_PHY_1369_DATA
+ DDRSS3_PHY_1370_DATA
+ DDRSS3_PHY_1371_DATA
+ DDRSS3_PHY_1372_DATA
+ DDRSS3_PHY_1373_DATA
+ DDRSS3_PHY_1374_DATA
+ DDRSS3_PHY_1375_DATA
+ DDRSS3_PHY_1376_DATA
+ DDRSS3_PHY_1377_DATA
+ DDRSS3_PHY_1378_DATA
+ DDRSS3_PHY_1379_DATA
+ DDRSS3_PHY_1380_DATA
+ DDRSS3_PHY_1381_DATA
+ DDRSS3_PHY_1382_DATA
+ DDRSS3_PHY_1383_DATA
+ DDRSS3_PHY_1384_DATA
+ DDRSS3_PHY_1385_DATA
+ DDRSS3_PHY_1386_DATA
+ DDRSS3_PHY_1387_DATA
+ DDRSS3_PHY_1388_DATA
+ DDRSS3_PHY_1389_DATA
+ DDRSS3_PHY_1390_DATA
+ DDRSS3_PHY_1391_DATA
+ DDRSS3_PHY_1392_DATA
+ DDRSS3_PHY_1393_DATA
+ DDRSS3_PHY_1394_DATA
+ DDRSS3_PHY_1395_DATA
+ DDRSS3_PHY_1396_DATA
+ DDRSS3_PHY_1397_DATA
+ DDRSS3_PHY_1398_DATA
+ DDRSS3_PHY_1399_DATA
+ DDRSS3_PHY_1400_DATA
+ DDRSS3_PHY_1401_DATA
+ DDRSS3_PHY_1402_DATA
+ DDRSS3_PHY_1403_DATA
+ DDRSS3_PHY_1404_DATA
+ DDRSS3_PHY_1405_DATA
+ DDRSS3_PHY_1406_DATA
+ DDRSS3_PHY_1407_DATA
+ DDRSS3_PHY_1408_DATA
+ DDRSS3_PHY_1409_DATA
+ DDRSS3_PHY_1410_DATA
+ DDRSS3_PHY_1411_DATA
+ DDRSS3_PHY_1412_DATA
+ DDRSS3_PHY_1413_DATA
+ DDRSS3_PHY_1414_DATA
+ DDRSS3_PHY_1415_DATA
+ DDRSS3_PHY_1416_DATA
+ DDRSS3_PHY_1417_DATA
+ DDRSS3_PHY_1418_DATA
+ DDRSS3_PHY_1419_DATA
+ DDRSS3_PHY_1420_DATA
+ DDRSS3_PHY_1421_DATA
+ DDRSS3_PHY_1422_DATA
+ >;
+ };
+ };
+};
diff --git a/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
new file mode 100644
index 0000000000..cd2e1e1df5
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart8;
+ i2c0 = &wkup_i2c0;
+ i2c1 = &mcu_i2c0;
+ i2c2 = &mcu_i2c1;
+ i2c3 = &main_i2c0;
+ };
+};
+
+&wkup_i2c0 {
+ u-boot,dm-spl;
+};
+
+&cbass_main {
+ u-boot,dm-spl;
+};
+
+&main_navss {
+ u-boot,dm-spl;
+};
+
+&cbass_mcu_wakeup {
+ u-boot,dm-spl;
+
+ timer1: timer@40400000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x40400000 0x0 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <250000000>;
+ u-boot,dm-spl;
+ };
+
+ chipid@43000014 {
+ u-boot,dm-spl;
+ };
+};
+
+&mcu_navss {
+ u-boot,dm-spl;
+};
+
+&mcu_ringacc {
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+ u-boot,dm-spl;
+};
+
+&mcu_udmap {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ u-boot,dm-spl;
+};
+
+&secure_proxy_main {
+ u-boot,dm-spl;
+};
+
+&sms {
+ u-boot,dm-spl;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+};
+
+&main_uart8_pins_default {
+ u-boot,dm-spl;
+};
+
+&main_mmc1_pins_default {
+ u-boot,dm-spl;
+};
+
+&wkup_pmx0 {
+ u-boot,dm-spl;
+};
+
+&k3_pds {
+ u-boot,dm-spl;
+};
+
+&k3_clks {
+ u-boot,dm-spl;
+};
+
+&k3_reset {
+ u-boot,dm-spl;
+};
+
+&main_uart8 {
+ u-boot,dm-spl;
+};
+
+&mcu_uart0 {
+ u-boot,dm-spl;
+};
+
+&wkup_uart0 {
+ u-boot,dm-spl;
+};
+
+&main_sdhci0 {
+ u-boot,dm-spl;
+};
+
+&main_sdhci1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts
new file mode 100644
index 0000000000..7350a9be34
--- /dev/null
+++ b/arch/arm/dts/k3-j784s4-r5-evm.dts
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j784s4.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
+#include "k3-j784s4-ddr.dtsi"
+
+/ {
+ chosen {
+ firmware-loader = &fs_loader0;
+ stdout-path = &main_uart8;
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a72_0;
+ };
+
+ fs_loader0: fs_loader@0 {
+ compatible = "u-boot,fs-loader";
+ u-boot,dm-pre-reloc;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 202 0>;
+ clocks = <&k3_clks 61 0>;
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 202 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <2000000000>;
+ ti,sci = <&sms>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ clk_200mhz: dummy_clock_200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ u-boot,dm-spl;
+ };
+
+ clk_19_2mhz: dummy_clock_19_2mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_mcu_wakeup {
+ sa3_secproxy: secproxy@44880000 {
+ u-boot,dm-spl;
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x44880000 0x0 0x20000>,
+ <0x0 0x44860000 0x0 0x20000>,
+ <0x0 0x43600000 0x0 0x10000>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ };
+
+ mcu_secproxy: secproxy@2a380000 {
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x2a380000 0x0 0x80000>,
+ <0x0 0x2a400000 0x0 0x80000>,
+ <0x0 0x2a480000 0x0 0x80000>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ u-boot,dm-spl;
+ };
+
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>, <&sa3_secproxy 5>;
+ mbox-names = "tx", "rx", "boot_notify";
+ u-boot,dm-spl;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&mcu_secproxy 21>,
+ <&mcu_secproxy 23>;
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+
+ main_uart8_pins_default: main-uart8-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */
+ J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */
+ J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
+ J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
+ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
+ J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */
+ J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
+ J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
+ J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
+ J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
+ J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
+ >;
+ };
+};
+
+&wkup_pmx0 {
+
+ mcu_uart0_pins_default: mcu-uart0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */
+ J784S4_WKUP_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */
+ J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */
+ J784S4_WKUP_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */
+ >;
+ };
+
+ wkup_uart0_pins_default: wkup-uart0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+ J784S4_WKUP_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+ J784S4_WKUP_IOPAD(0x0b0, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */
+ J784S4_WKUP_IOPAD(0x0b4, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */
+ >;
+ };
+};
+
+&sms {
+ mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+ u-boot,dm-spl;
+};
+
+&wkup_uart0 {
+ u-boot,dm-spl;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+};
+
+&mcu_uart0 {
+ u-boot,dm-spl;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_uart0_pins_default>;
+};
+
+&main_uart8 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart8_pins_default>;
+};
+
+&main_sdhci0 {
+ /delete-property/ power-domains;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ status = "okay";
+ clock-names = "clk_xin";
+ clocks = <&clk_200mhz>;
+ ti,driver-strength-ohm = <50>;
+ non-removable;
+ bus-width = <8>;
+};
+
+&main_sdhci1 {
+ /delete-property/ power-domains;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ status = "okay";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ pinctrl-names = "default";
+ clock-names = "clk_xin";
+ clocks = <&clk_200mhz>;
+ ti,driver-strength-ohm = <50>;
+};
+
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
+
+#include "k3-j784s4-evm-u-boot.dtsi"
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 03/10] arm: K3: Add basic support for J784S4 SoC definition
2023-03-21 14:10 [PATCH v2 00/10] Introduce initial TI's J784S4 support Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 01/10] arm: dts: introduce j784s4 dtbs from linux kernel Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 02/10] arm: dts: introduce j784s4 u-boot dtbs Hari Nagalla
@ 2023-03-21 14:10 ` Hari Nagalla
2023-03-21 14:25 ` Andrew Davis
` (2 more replies)
2023-03-21 14:10 ` [PATCH v2 04/10] drivers: dma: Add support for J784S4 Hari Nagalla
` (7 subsequent siblings)
10 siblings, 3 replies; 22+ messages in thread
From: Hari Nagalla @ 2023-03-21 14:10 UTC (permalink / raw)
To: trini; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Bryan Bratloff <bb@ti.com>
Signed-off-by: Nishant Menon <nm@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
---
arch/arm/mach-k3/Kconfig | 16 +-
arch/arm/mach-k3/Makefile | 2 +
arch/arm/mach-k3/arm64-mmu.c | 41 +++
arch/arm/mach-k3/include/mach/hardware.h | 4 +
.../mach-k3/include/mach/j784s4_hardware.h | 41 +++
arch/arm/mach-k3/include/mach/j784s4_spl.h | 46 +++
arch/arm/mach-k3/include/mach/spl.h | 6 +-
arch/arm/mach-k3/j784s4/Makefile | 5 +
arch/arm/mach-k3/j784s4/dev-data.c | 97 ++++++
arch/arm/mach-k3/j784s4_init.c | 319 ++++++++++++++++++
board/ti/j784s4/j784s4.env | 108 ++++++
include/configs/j784s4_evm.h | 49 +++
12 files changed, 727 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/mach-k3/include/mach/j784s4_hardware.h
create mode 100644 arch/arm/mach-k3/include/mach/j784s4_spl.h
create mode 100644 arch/arm/mach-k3/j784s4/Makefile
create mode 100644 arch/arm/mach-k3/j784s4/dev-data.c
create mode 100644 arch/arm/mach-k3/j784s4_init.c
create mode 100644 board/ti/j784s4/j784s4.env
create mode 100644 include/configs/j784s4_evm.h
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index a8c3a593d5..3a9be0a590 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -22,6 +22,9 @@ config SOC_K3_AM625
config SOC_K3_AM62A7
bool "TI's K3 based AM62A7 SoC Family Support"
+config SOC_K3_J784S4
+ bool "TI's K3 based J784S4 SoC Family Support"
+
endchoice
config SYS_SOC
@@ -30,7 +33,7 @@ config SYS_SOC
config SYS_K3_NON_SECURE_MSRAM_SIZE
hex
default 0x80000 if SOC_K3_AM654
- default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2
+ default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
default 0x1c0000 if SOC_K3_AM642
default 0x3c000 if SOC_K3_AM625 || SOC_K3_AM62A7
help
@@ -42,7 +45,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
hex
default 0x58000 if SOC_K3_AM654
- default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2
+ default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
default 0x180000 if SOC_K3_AM642
default 0x38000 if SOC_K3_AM625 || SOC_K3_AM62A7
help
@@ -52,14 +55,14 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
config SYS_K3_MCU_SCRATCHPAD_BASE
hex
default 0x40280000 if SOC_K3_AM654
- default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2
+ default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
help
Describes the base address of MCU Scratchpad RAM.
config SYS_K3_MCU_SCRATCHPAD_SIZE
hex
default 0x200 if SOC_K3_AM654
- default 0x200 if SOC_K3_J721E || SOC_K3_J721S2
+ default 0x200 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
help
Describes the size of MCU Scratchpad RAM.
@@ -67,7 +70,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
hex
default 0x41c7fbfc if SOC_K3_AM654
default 0x41cffbfc if SOC_K3_J721E
- default 0x41cfdbfc if SOC_K3_J721S2
+ default 0x41cfdbfc if SOC_K3_J721S2 || SOC_K3_J784S4
default 0x701bebfc if SOC_K3_AM642
default 0x43c3f290 if SOC_K3_AM625
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
@@ -172,7 +175,7 @@ config K3_ATF_LOAD_ADDR
config K3_DM_FW
bool "Separate DM firmware image"
- depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
+ depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_J784S4) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
default y
help
Enabling this will indicate that the system has separate DM
@@ -194,4 +197,5 @@ source "board/ti/am62ax/Kconfig"
source "board/ti/j721e/Kconfig"
source "board/siemens/iot2050/Kconfig"
source "board/ti/j721s2/Kconfig"
+source "board/ti/j784s4/Kconfig"
endif
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index b5bc236781..14cf85ad38 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/
obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
obj-$(CONFIG_SOC_K3_AM625) += am62x/
obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_ARM64) += cache.o
@@ -17,6 +18,7 @@ obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
+obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o
obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
endif
obj-y += common.o security.o
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 88687c2d09..610ff19696 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -264,3 +264,44 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
struct mm_region *mem_map = am64_mem_map;
#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
+
+#if defined(CONFIG_SOC_K3_J784S4)
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
+
+/* ToDo: Add 64bit IO */
+struct mm_region j784s4_mem_map[NR_MMU_REGIONS] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x880000000UL,
+ .phys = 0x880000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x500000000UL,
+ .phys = 0x500000000UL,
+ .size = 0x400000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = j784s4_mem_map;
+
+#endif /* CONFIG_SOC_K3_J784S4 */
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 2c60ef8543..77f36c6707 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -30,6 +30,10 @@
#include "am62a_hardware.h"
#endif
+#ifdef CONFIG_SOC_K3_J784S4
+#include "j784s4_hardware.h"
+#endif
+
/* Assuming these addresses and definitions stay common across K3 devices */
#define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14)
#define JTAG_ID_VARIANT_SHIFT 28
diff --git a/arch/arm/mach-k3/include/mach/j784s4_hardware.h b/arch/arm/mach-k3/include/mach/j784s4_hardware.h
new file mode 100644
index 0000000000..afcf39c45d
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/j784s4_hardware.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: J784S4 SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __ASM_ARCH_J784S4_HARDWARE_H
+#define __ASM_ARCH_J784S4_HARDWARE_H
+
+#include <config.h>
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#endif
+
+#define WKUP_CTRL_MMR0_BASE 0x43000000
+#define MCU_CTRL_MMR0_BASE 0x40f00000
+#define CTRL_MMR0_BASE 0x00100000
+
+#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
+#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
+#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
+#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
+#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1
+#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6)
+#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6
+#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7)
+#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7
+
+#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
+#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
+#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
+#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
+#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
+
+/* ROM HANDOFF Structure location */
+#define ROM_EXTENDED_BOOT_DATA_INFO 0x41cfdb00
+
+/* MCU SCRATCHPAD usage */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
+
+#endif /* __ASM_ARCH_J784S4_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/j784s4_spl.h b/arch/arm/mach-k3/include/mach/j784s4_spl.h
new file mode 100644
index 0000000000..d312a57e69
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/j784s4_spl.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
+ * David Huang <d-huang@ti.com>
+ */
+#ifndef _ASM_ARCH_J784S4_SPL_H_
+#define _ASM_ARCH_J784S4_SPL_H_
+
+/* With BootMode B = 0 */
+#include <linux/bitops.h>
+#define BOOT_DEVICE_HYPERFLASH 0x00
+#define BOOT_DEVICE_OSPI 0x01
+#define BOOT_DEVICE_QSPI 0x02
+#define BOOT_DEVICE_SPI 0x03
+#define BOOT_DEVICE_ETHERNET 0x04
+#define BOOT_DEVICE_I2C 0x06
+#define BOOT_DEVICE_UART 0x07
+#define BOOT_DEVICE_NOR BOOT_DEVICE_HYPERFLASH
+
+/* With BootMode B = 1 */
+#define BOOT_DEVICE_MMC2 0x10
+#define BOOT_DEVICE_MMC1 0x11
+#define BOOT_DEVICE_DFU 0x12
+#define BOOT_DEVICE_UFS 0x13
+#define BOOT_DEVIE_GPMC 0x14
+#define BOOT_DEVICE_PCIE 0x15
+#define BOOT_DEVICE_XSPI 0x16
+#define BOOT_DEVICE_RAM 0x17
+#define BOOT_DEVICE_MMC2_2 0xFF /* Invalid value */
+
+/* Backup boot modes with MCU Only = 0 */
+#define BACKUP_BOOT_DEVICE_RAM 0x0
+#define BACKUP_BOOT_DEVICE_USB 0x1
+#define BACKUP_BOOT_DEVICE_UART 0x3
+#define BACKUP_BOOT_DEVICE_ETHERNET 0x4
+#define BACKUP_BOOT_DEVICE_MMC2 0x5
+#define BACKUP_BOOT_DEVICE_SPI 0x6
+#define BACKUP_BOOT_DEVICE_I2C 0x7
+
+#define BOOT_MODE_B_SHIFT 4
+#define BOOT_MODE_B_MASK BIT(4)
+
+#define K3_PRIMARY_BOOTMODE 0x0
+#define K3_BACKUP_BOOTMODE 0x1
+
+#endif
diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
index 356cd89210..82f57347e6 100644
--- a/arch/arm/mach-k3/include/mach/spl.h
+++ b/arch/arm/mach-k3/include/mach/spl.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
* Lokesh Vutla <lokeshvutla@ti.com>
*/
#ifndef _ASM_ARCH_SPL_H_
@@ -30,4 +30,8 @@
#include "am62a_spl.h"
#endif
+#ifdef CONFIG_SOC_K3_J784S4
+#include "j784s4_spl.h"
+#endif
+
#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/arch/arm/mach-k3/j784s4/Makefile b/arch/arm/mach-k3/j784s4/Makefile
new file mode 100644
index 0000000000..d8bb3c7719
--- /dev/null
+++ b/arch/arm/mach-k3/j784s4/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j784s4/dev-data.c b/arch/arm/mach-k3/j784s4/dev-data.c
new file mode 100644
index 0000000000..e44afad3ec
--- /dev/null
+++ b/arch/arm/mach-k3/j784s4/dev-data.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J784S4 specific device platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Bryan Brattlof <bb@ti.com>.
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-dev.h"
+
+static struct ti_psc soc_psc_list[] = {
+ [0] = PSC(0, 0x42000000),
+ [1] = PSC(1, 0x00420000),
+ [2] = PSC(2, 0x00400000),
+};
+
+static struct ti_pd soc_pd_list[] = {
+ [0] = PSC_PD(0, &soc_psc_list[0], NULL),
+ [1] = PSC_PD(3, &soc_psc_list[1], NULL),
+ [2] = PSC_PD(0, &soc_psc_list[2], NULL),
+ [3] = PSC_PD(1, &soc_psc_list[2], &soc_pd_list[2]),
+ [4] = PSC_PD(14, &soc_psc_list[2], NULL),
+ [5] = PSC_PD(15, &soc_psc_list[2], &soc_pd_list[4]),
+ [6] = PSC_PD(16, &soc_psc_list[2], &soc_pd_list[4]),
+ [7] = PSC_PD(38, &soc_psc_list[2], NULL),
+};
+
+static struct ti_lpsc soc_lpsc_list[] = {
+ [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [1] = PSC_LPSC(3, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [2] = PSC_LPSC(10, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [3] = PSC_LPSC(11, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [4] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [5] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[6]),
+ [6] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[1], NULL),
+ [7] = PSC_LPSC(0, &soc_psc_list[2], &soc_pd_list[2], NULL),
+ [8] = PSC_LPSC(9, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[2]),
+ [9] = PSC_LPSC(14, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[10]),
+ [10] = PSC_LPSC(15, &soc_psc_list[2], &soc_pd_list[2], NULL),
+ [11] = PSC_LPSC(16, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[12]),
+ [12] = PSC_LPSC(17, &soc_psc_list[2], &soc_pd_list[2], NULL),
+ [13] = PSC_LPSC(20, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]),
+ [14] = PSC_LPSC(23, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]),
+ [15] = PSC_LPSC(25, &soc_psc_list[2], &soc_pd_list[2], &soc_lpsc_list[5]),
+ [16] = PSC_LPSC(43, &soc_psc_list[2], &soc_pd_list[3], NULL),
+ [17] = PSC_LPSC(45, &soc_psc_list[2], &soc_pd_list[3], NULL),
+ [18] = PSC_LPSC(78, &soc_psc_list[2], &soc_pd_list[4], NULL),
+ [19] = PSC_LPSC(80, &soc_psc_list[2], &soc_pd_list[5], &soc_lpsc_list[18]),
+ [20] = PSC_LPSC(81, &soc_psc_list[2], &soc_pd_list[6], &soc_lpsc_list[18]),
+ [21] = PSC_LPSC(120, &soc_psc_list[2], &soc_pd_list[7], &soc_lpsc_list[22]),
+ [22] = PSC_LPSC(121, &soc_psc_list[2], &soc_pd_list[7], NULL),
+};
+
+static struct ti_dev soc_dev_list[] = {
+ PSC_DEV(160, &soc_lpsc_list[0]),
+ PSC_DEV(161, &soc_lpsc_list[0]),
+ PSC_DEV(162, &soc_lpsc_list[0]),
+ PSC_DEV(243, &soc_lpsc_list[0]),
+ PSC_DEV(149, &soc_lpsc_list[0]),
+ PSC_DEV(167, &soc_lpsc_list[1]),
+ PSC_DEV(279, &soc_lpsc_list[1]),
+ PSC_DEV(161, &soc_lpsc_list[2]),
+ PSC_DEV(162, &soc_lpsc_list[3]),
+ PSC_DEV(160, &soc_lpsc_list[4]),
+ PSC_DEV(139, &soc_lpsc_list[5]),
+ PSC_DEV(194, &soc_lpsc_list[6]),
+ PSC_DEV(78, &soc_lpsc_list[7]),
+ PSC_DEV(61, &soc_lpsc_list[8]),
+ PSC_DEV(131, &soc_lpsc_list[9]),
+ PSC_DEV(191, &soc_lpsc_list[10]),
+ PSC_DEV(132, &soc_lpsc_list[11]),
+ PSC_DEV(192, &soc_lpsc_list[12]),
+ PSC_DEV(398, &soc_lpsc_list[13]),
+ PSC_DEV(141, &soc_lpsc_list[14]),
+ PSC_DEV(140, &soc_lpsc_list[15]),
+ PSC_DEV(146, &soc_lpsc_list[16]),
+ PSC_DEV(392, &soc_lpsc_list[17]),
+ PSC_DEV(395, &soc_lpsc_list[17]),
+ PSC_DEV(198, &soc_lpsc_list[18]),
+ PSC_DEV(202, &soc_lpsc_list[19]),
+ PSC_DEV(203, &soc_lpsc_list[20]),
+ PSC_DEV(133, &soc_lpsc_list[21]),
+ PSC_DEV(193, &soc_lpsc_list[22]),
+};
+
+const struct ti_k3_pd_platdata j784s4_pd_platdata = {
+ .psc = soc_psc_list,
+ .pd = soc_pd_list,
+ .lpsc = soc_lpsc_list,
+ .devs = soc_dev_list,
+ .num_psc = 3,
+ .num_pd = 8,
+ .num_lpsc = 23,
+ .num_devs = 29,
+};
diff --git a/arch/arm/mach-k3/j784s4_init.c b/arch/arm/mach-k3/j784s4_init.c
new file mode 100644
index 0000000000..e2c7624cd6
--- /dev/null
+++ b/arch/arm/mach-k3/j784s4_init.c
@@ -0,0 +1,319 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J784S4: SoC specific initialization
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
+ * Hari Nagalla <hnagalla@ti.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/armv7_mpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sysfw-loader.h>
+#include "common.h"
+#include <asm/arch/sys_proto.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/pinctrl.h>
+#include <mmc.h>
+#include <remoteproc.h>
+
+static void ctrl_mmr_unlock(void)
+{
+ /* Unlock all WKUP_CTRL_MMR0 module registers */
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
+
+ /* Unlock all MCU_CTRL_MMR0 module registers */
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
+
+ /* Unlock all CTRL_MMR0 module registers */
+ mmr_unlock(CTRL_MMR0_BASE, 0);
+ mmr_unlock(CTRL_MMR0_BASE, 1);
+ mmr_unlock(CTRL_MMR0_BASE, 2);
+ mmr_unlock(CTRL_MMR0_BASE, 3);
+ mmr_unlock(CTRL_MMR0_BASE, 5);
+ mmr_unlock(CTRL_MMR0_BASE, 7);
+}
+
+void k3_mmc_stop_clock(void)
+{
+ if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
+ if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+ struct mmc *mmc = find_mmc_device(0);
+
+ if (!mmc)
+ return;
+
+ mmc->saved_clock = mmc->clock;
+ mmc_set_clock(mmc, 0, true);
+ }
+ }
+}
+
+void k3_mmc_restart_clock(void)
+{
+ if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
+ if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+ struct mmc *mmc = find_mmc_device(0);
+
+ if (!mmc)
+ return;
+
+ mmc_set_clock(mmc, mmc->saved_clock, false);
+ }
+ }
+}
+
+/*
+ * This uninitialized global variable would normal end up in the .bss section,
+ * but the .bss is cleared between writing and reading this variable, so move
+ * it to the .data section.
+ */
+u32 bootindex __section(".data");
+static struct rom_extended_boot_data bootdata __section(".data");
+
+static void store_boot_info_from_rom(void)
+{
+ bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+ memcpy(&bootdata, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
+ sizeof(struct rom_extended_boot_data));
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+ /*
+ * Cannot delay this further as there is a chance that
+ * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
+ */
+ store_boot_info_from_rom();
+
+ /* Make all control module registers accessible */
+ ctrl_mmr_unlock();
+
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ disable_linefill_optimization();
+ setup_k3_mpu_regions();
+ }
+
+ /* Init DM early */
+ ret = spl_early_init();
+
+ /* Prepare console output */
+ preloader_console_init();
+
+ if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
+ /*
+ * Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
+ * regardless of the result of pinctrl. Do this without probing the
+ * device, but instead by searching the device that would request the
+ * given sequence number if probed. The UART will be used by the system
+ * firmware (SYSFW) image for various purposes and SYSFW depends on us
+ * to initialize its pin settings.
+ */
+ ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
+ if (!ret)
+ pinctrl_select_state(dev, "default");
+
+ /*
+ * Load, start up, and configure system controller firmware. Provide
+ * the U-Boot console init function to the SYSFW post-PM configuration
+ * callback hook, effectively switching on (or over) the console
+ * output.
+ */
+ k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
+ k3_mmc_stop_clock, k3_mmc_restart_clock);
+
+ if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
+ /*
+ * Force probe of clk_k3 driver here to ensure basic default clock
+ * configuration is always done for enabling PM services.
+ */
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(ti_clk),
+ &dev);
+ if (ret)
+ panic("Failed to initialize clk-k3!\n");
+ }
+ }
+
+ /* Output System Firmware version info */
+ k3_sysfw_print_ver();
+
+ if (IS_ENABLED(CONFIG_TARGET_J784S4_R5_EVM)) {
+ ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev);
+ if (ret)
+ panic("Probe of msmc failed: %d\n", ret);
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret)
+ panic("DRAM 0 init failed: %d\n", ret);
+
+ ret = uclass_next_device_err(&dev);
+ if (ret)
+ panic("DRAM 1 init failed: %d\n", ret);
+
+ ret = uclass_next_device_err(&dev);
+ if (ret)
+ panic("DRAM 2 init failed: %d\n", ret);
+
+ ret = uclass_next_device_err(&dev);
+ if (ret)
+ panic("DRAM 3 init failed: %d\n", ret);
+ }
+
+ spl_enable_dcache();
+}
+
+u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
+{
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ return MMCSD_MODE_EMMCBOOT;
+ case BOOT_DEVICE_MMC2:
+ return MMCSD_MODE_FS;
+ default:
+ return MMCSD_MODE_RAW;
+ }
+}
+
+static u32 __get_backup_bootmedia(u32 main_devstat)
+{
+ u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
+
+ switch (bkup_boot) {
+ case BACKUP_BOOT_DEVICE_USB:
+ return BOOT_DEVICE_DFU;
+ case BACKUP_BOOT_DEVICE_UART:
+ return BOOT_DEVICE_UART;
+ case BACKUP_BOOT_DEVICE_ETHERNET:
+ return BOOT_DEVICE_ETHERNET;
+ case BACKUP_BOOT_DEVICE_MMC2:
+ {
+ u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
+ MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
+ if (port == 0x0)
+ return BOOT_DEVICE_MMC1;
+ return BOOT_DEVICE_MMC2;
+ }
+ case BACKUP_BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+ case BACKUP_BOOT_DEVICE_I2C:
+ return BOOT_DEVICE_I2C;
+ }
+
+ return BOOT_DEVICE_RAM;
+}
+
+static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
+{
+ u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+ WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+
+ bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
+ BOOT_MODE_B_SHIFT;
+
+ if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI ||
+ bootmode == BOOT_DEVICE_XSPI)
+ bootmode = BOOT_DEVICE_SPI;
+
+ if (bootmode == BOOT_DEVICE_MMC2) {
+ u32 port = (main_devstat &
+ MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
+ MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
+ if (port == 0x0)
+ bootmode = BOOT_DEVICE_MMC1;
+ }
+
+ return bootmode;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
+ u32 main_devstat;
+
+ if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
+ printf("ERROR: MCU only boot is not yet supported\n");
+ return BOOT_DEVICE_RAM;
+ }
+
+ /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
+ main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+
+ if (bootindex == K3_PRIMARY_BOOTMODE)
+ return __get_primary_bootmedia(main_devstat, wkup_devstat);
+ else
+ return __get_backup_bootmedia(main_devstat);
+}
+
+#define J784S4_DEV_MCU_RTI0 367
+#define J784S4_DEV_MCU_RTI1 368
+#define J784S4_DEV_MCU_ARMSS0_CPU0 346
+#define J784S4_DEV_MCU_ARMSS0_CPU1 347
+
+void release_resources_for_core_shutdown(void)
+{
+ if (IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)) {
+ struct ti_sci_handle *ti_sci;
+ struct ti_sci_dev_ops *dev_ops;
+ struct ti_sci_proc_ops *proc_ops;
+ int ret;
+ u32 i;
+
+ const u32 put_device_ids[] = {
+ J784S4_DEV_MCU_RTI0,
+ J784S4_DEV_MCU_RTI1,
+ };
+
+ ti_sci = get_ti_sci_handle();
+ dev_ops = &ti_sci->ops.dev_ops;
+ proc_ops = &ti_sci->ops.proc_ops;
+
+ /* Iterate through list of devices to put (shutdown) */
+ for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
+ u32 id = put_device_ids[i];
+
+ ret = dev_ops->put_device(ti_sci, id);
+ if (ret)
+ panic("Failed to put device %u (%d)\n", id, ret);
+ }
+
+ const u32 put_core_ids[] = {
+ J784S4_DEV_MCU_ARMSS0_CPU1,
+ J784S4_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
+ };
+
+ /* Iterate through list of cores to put (shutdown) */
+ for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
+ u32 id = put_core_ids[i];
+
+ /*
+ * Queue up the core shutdown request. Note that this call
+ * needs to be followed up by an actual invocation of an WFE
+ * or WFI CPU instruction.
+ */
+ ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
+ if (ret)
+ panic("Failed sending core %u shutdown message (%d)\n",
+ id, ret);
+ }
+ }
+}
diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env
new file mode 100644
index 0000000000..4be91ee89c
--- /dev/null
+++ b/board/ti/j784s4/j784s4.env
@@ -0,0 +1,108 @@
+loadaddr=0x82000000
+kernel_addr_r=0x82000000
+fdtaddr=0x88000000
+dtboaddr=0x89000000
+fdt_addr_r=0x88000000
+fdtoverlay_addr_r=0x89000000
+rdaddr=0x88080000
+ramdisk_addr_r=0x88080000
+scriptaddr=0x80000000
+pxefile_addr_r=0x80100000
+bootm_size=0x10000000
+boot_fdt=try
+
+mmcrootfstype=ext4 rootwait
+finduuid=part uuid ${boot} ${bootpart} uuid
+args_mmc=run finduuid;setenv bootargs console=${console}
+ ${optargs}
+ root=PARTUUID=${uuid} rw
+ rootfstype=${mmcrootfstype}
+loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr
+bootscript=echo Running bootscript from mmc${mmcdev} ...;
+ source ${loadaddr}
+bootenvfile=uEnv.txt
+importbootenv=echo Importing environment from mmc${mmcdev} ...;
+ env import -t ${loadaddr} ${filesize}
+loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}
+loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}
+loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}
+envboot=mmc dev ${mmcdev};
+ if mmc rescan; then
+ echo SD/MMC found on device ${mmcdev};
+ if run loadbootscript; then
+ run bootscript;
+ else
+ if run loadbootenv; then
+ echo Loaded env from ${bootenvfile};
+ run importbootenv;
+ fi;
+ if test -n $uenvcmd; then
+ echo Running uenvcmd ...;
+ run uenvcmd;
+ fi;
+ fi;
+ fi;
+mmcloados=
+ if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
+ if run loadfdt; then
+ bootz ${loadaddr} - ${fdtaddr};
+ else
+ if test ${boot_fdt} = try; then
+ bootz;
+ else
+ echo WARN: Cannot load the DT;
+ fi;
+ fi;
+ else
+ bootz;
+ fi;
+mmcboot=mmc dev ${mmcdev};
+ devnum=${mmcdev};
+ devtype=mmc;
+ if mmc rescan; then
+ echo SD/MMC found on device ${mmcdev};
+ if run loadimage; then
+ run args_mmc;
+ if test ${boot_fit} -eq 1; then
+ run run_fit;
+ else
+ run mmcloados;
+ fi;
+ fi;
+ fi;
+
+default_device_tree=k3-j784s4-evm.dtb
+findfdt=
+ setenv name_fdt ${default_device_tree};
+ setenv fdtfile ${name_fdt}
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02880000
+ ${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
+init_mmc=run args_all args_mmc
+get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}
+get_overlay_mmc=
+ fdt address ${fdtaddr};
+ fdt resize 0x100000;
+ for overlay in $name_overlays;
+ do;
+ load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} &&
+ fdt apply ${dtboaddr};
+ done;
+get_kern_mmc=load mmc ${bootpart} ${loadaddr}
+ ${bootdir}/${name_kern}
+get_fit_mmc=load mmc ${bootpart} ${addr_fit}
+ ${bootdir}/${name_fit}
+partitions=name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}
+
+splashfile=ti.gz
+splashimage=0x82000000
+splashpos=m,m
+splashsource=mmc
diff --git a/include/configs/j784s4_evm.h b/include/configs/j784s4_evm.h
new file mode 100644
index 0000000000..3e429fb036
--- /dev/null
+++ b/include/configs/j784s4_evm.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for K3 J784S4 EVM
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Hari Nagalla <hnagalla@ti.com>
+ */
+
+#ifndef __CONFIG_J784S4_EVM_H
+#define __CONFIG_J784S4_EVM_H
+
+#include <linux/sizes.h>
+#include <config_distro_bootcmd.h>
+#include <environment/ti/mmc.h>
+
+/* DDR Configuration */
+#define CFG_SYS_SDRAM_BASE1 0x880000000
+
+#ifdef CONFIG_CMD_MMC
+#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
+#else
+#define DISTRO_BOOT_DEV_MMC(func)
+#endif
+
+#ifdef CONFIG_CMD_PXE
+#define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na)
+#else
+#define DISTRO_BOOT_DEV_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_DHCP
+#define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na)
+#else
+#define DISTRO_BOOT_DEV_DHCP(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ DISTRO_BOOT_DEV_MMC(func) \
+ DISTRO_BOOT_DEV_PXE(func) \
+ DISTRO_BOOT_DEV_DHCP(func)
+
+/* Incorporate settings into the U-Boot environment */
+#define CFG_EXTRA_ENV_SETTINGS \
+ BOOTENV
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+#endif /* __CONFIG_J784S4_EVM_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 04/10] drivers: dma: Add support for J784S4
2023-03-21 14:10 [PATCH v2 00/10] Introduce initial TI's J784S4 support Hari Nagalla
` (2 preceding siblings ...)
2023-03-21 14:10 ` [PATCH v2 03/10] arm: K3: Add basic support for J784S4 SoC definition Hari Nagalla
@ 2023-03-21 14:10 ` Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 05/10] clk: clk-k3: Add support for J784S4 SoC Hari Nagalla
` (6 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Hari Nagalla @ 2023-03-21 14:10 UTC (permalink / raw)
To: trini; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
Add support for DMA in J784S4 SoC.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
---
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-psil-j784s4.c | 166 ++++++++++++++++++++++++++
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 2 +
drivers/firmware/ti_sci_static_data.h | 35 ++++++
5 files changed, 205 insertions(+)
create mode 100644 drivers/dma/ti/k3-psil-j784s4.c
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 6807eb8e8b..bd4ce68d9c 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -8,3 +8,4 @@ k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o
+k3-psil-data-$(CONFIG_SOC_K3_J784S4) += k3-psil-j784s4.o
diff --git a/drivers/dma/ti/k3-psil-j784s4.c b/drivers/dma/ti/k3-psil-j784s4.c
new file mode 100644
index 0000000000..d62d5e9c33
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-j784s4.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
+ */
+#include <linux/kernel.h>
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pkt_mode = 1, \
+ }, \
+ }
+
+#define PSIL_PDMA_MCASP(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pdma_acc32 = 1, \
+ .pdma_burst = 1, \
+ }, \
+ }
+
+#define PSIL_ETHERNET(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 16, \
+ }, \
+ }
+
+#define PSIL_SA2UL(x, tx) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 64, \
+ .notdpkt = tx, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep j784s4_src_ep_map[] = {
+ /* PDMA_MCASP - McASP0-4 */
+ PSIL_PDMA_MCASP(0x4400),
+ PSIL_PDMA_MCASP(0x4401),
+ PSIL_PDMA_MCASP(0x4402),
+ PSIL_PDMA_MCASP(0x4403),
+ PSIL_PDMA_MCASP(0x4404),
+ /* PDMA_SPI_G0 - SPI0-3 */
+ PSIL_PDMA_XY_PKT(0x4600),
+ PSIL_PDMA_XY_PKT(0x4601),
+ PSIL_PDMA_XY_PKT(0x4602),
+ PSIL_PDMA_XY_PKT(0x4603),
+ PSIL_PDMA_XY_PKT(0x4604),
+ PSIL_PDMA_XY_PKT(0x4605),
+ PSIL_PDMA_XY_PKT(0x4606),
+ PSIL_PDMA_XY_PKT(0x4607),
+ PSIL_PDMA_XY_PKT(0x4608),
+ PSIL_PDMA_XY_PKT(0x4609),
+ PSIL_PDMA_XY_PKT(0x460a),
+ PSIL_PDMA_XY_PKT(0x460b),
+ PSIL_PDMA_XY_PKT(0x460c),
+ PSIL_PDMA_XY_PKT(0x460d),
+ PSIL_PDMA_XY_PKT(0x460e),
+ PSIL_PDMA_XY_PKT(0x460f),
+ /* PDMA_SPI_G1 - SPI4-7 */
+ PSIL_PDMA_XY_PKT(0x4610),
+ PSIL_PDMA_XY_PKT(0x4611),
+ PSIL_PDMA_XY_PKT(0x4612),
+ PSIL_PDMA_XY_PKT(0x4613),
+ PSIL_PDMA_XY_PKT(0x4614),
+ PSIL_PDMA_XY_PKT(0x4615),
+ PSIL_PDMA_XY_PKT(0x4616),
+ PSIL_PDMA_XY_PKT(0x4617),
+ PSIL_PDMA_XY_PKT(0x4618),
+ PSIL_PDMA_XY_PKT(0x4619),
+ PSIL_PDMA_XY_PKT(0x461a),
+ PSIL_PDMA_XY_PKT(0x461b),
+ PSIL_PDMA_XY_PKT(0x461c),
+ PSIL_PDMA_XY_PKT(0x461d),
+ PSIL_PDMA_XY_PKT(0x461e),
+ PSIL_PDMA_XY_PKT(0x461f),
+ /* PDMA_USART_G0 - UART0-1 */
+ PSIL_PDMA_XY_PKT(0x4700),
+ PSIL_PDMA_XY_PKT(0x4701),
+ /* PDMA_USART_G1 - UART2-3 */
+ PSIL_PDMA_XY_PKT(0x4702),
+ PSIL_PDMA_XY_PKT(0x4703),
+ /* PDMA_USART_G2 - UART4-9 */
+ PSIL_PDMA_XY_PKT(0x4704),
+ PSIL_PDMA_XY_PKT(0x4705),
+ PSIL_PDMA_XY_PKT(0x4706),
+ PSIL_PDMA_XY_PKT(0x4707),
+ PSIL_PDMA_XY_PKT(0x4708),
+ PSIL_PDMA_XY_PKT(0x4709),
+ /* CPSW0 */
+ PSIL_ETHERNET(0x7000),
+ /* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */
+ PSIL_PDMA_XY_PKT(0x7100),
+ PSIL_PDMA_XY_PKT(0x7101),
+ PSIL_PDMA_XY_PKT(0x7102),
+ PSIL_PDMA_XY_PKT(0x7103),
+ /* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */
+ PSIL_PDMA_XY_PKT(0x7200),
+ PSIL_PDMA_XY_PKT(0x7201),
+ PSIL_PDMA_XY_PKT(0x7202),
+ PSIL_PDMA_XY_PKT(0x7203),
+ PSIL_PDMA_XY_PKT(0x7204),
+ PSIL_PDMA_XY_PKT(0x7205),
+ PSIL_PDMA_XY_PKT(0x7206),
+ PSIL_PDMA_XY_PKT(0x7207),
+ /* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */
+ PSIL_PDMA_XY_PKT(0x7300),
+ /* MCU_PDMA_ADC - ADC0-1 */
+ PSIL_PDMA_XY_TR(0x7400),
+ PSIL_PDMA_XY_TR(0x7401),
+ PSIL_PDMA_XY_TR(0x7402),
+ PSIL_PDMA_XY_TR(0x7403),
+ /* SA2UL */
+ PSIL_SA2UL(0x7500, 0),
+ PSIL_SA2UL(0x7501, 0),
+ PSIL_SA2UL(0x7502, 0),
+ PSIL_SA2UL(0x7503, 0),
+};
+
+/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
+static struct psil_ep j784s4_dst_ep_map[] = {
+ /* CPSW0 */
+ PSIL_ETHERNET(0xf000),
+ PSIL_ETHERNET(0xf001),
+ PSIL_ETHERNET(0xf002),
+ PSIL_ETHERNET(0xf003),
+ PSIL_ETHERNET(0xf004),
+ PSIL_ETHERNET(0xf005),
+ PSIL_ETHERNET(0xf006),
+ PSIL_ETHERNET(0xf007),
+ /* SA2UL */
+ PSIL_SA2UL(0xf500, 1),
+ PSIL_SA2UL(0xf501, 1),
+};
+
+struct psil_ep_map j784s4_ep_map = {
+ .name = "j784s4",
+ .src = j784s4_src_ep_map,
+ .src_count = ARRAY_SIZE(j784s4_src_ep_map),
+ .dst = j784s4_dst_ep_map,
+ .dst_count = ARRAY_SIZE(j784s4_dst_ep_map),
+};
diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h
index 28078c6bd8..634bf2ca19 100644
--- a/drivers/dma/ti/k3-psil-priv.h
+++ b/drivers/dma/ti/k3-psil-priv.h
@@ -42,5 +42,6 @@ extern struct psil_ep_map j721e_ep_map;
extern struct psil_ep_map j721s2_ep_map;
extern struct psil_ep_map am64_ep_map;
extern struct psil_ep_map am62_ep_map;
+extern struct psil_ep_map j784s4_ep_map;
#endif /* K3_PSIL_PRIV_H_ */
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c
index f23c8ca2b7..10383b4abf 100644
--- a/drivers/dma/ti/k3-psil.c
+++ b/drivers/dma/ti/k3-psil.c
@@ -26,6 +26,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
soc_ep_map = &am64_ep_map;
else if (IS_ENABLED(CONFIG_SOC_K3_AM625))
soc_ep_map = &am62_ep_map;
+ else if (IS_ENABLED(CONFIG_SOC_K3_J784S4))
+ soc_ep_map = &j784s4_ep_map;
}
if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) {
diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h
index 1a461fab61..a0a41ffcce 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -85,6 +85,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
#endif /* CONFIG_SOC_K3_J721S2 */
#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7)
+
static struct ti_sci_resource_static_data rm_static_data[] = {
/* BC channels */
{
@@ -97,6 +98,40 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
};
#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
+#if IS_ENABLED(CONFIG_SOC_K3_J784S4)
+static struct ti_sci_resource_static_data rm_static_data[] = {
+ /* Free rings */
+ {
+ .dev_id = 328,
+ .subtype = 1,
+ .range_start = 208,
+ .range_num = 32,
+ },
+ /* TX channels */
+ {
+ .dev_id = 329,
+ .subtype = 13,
+ .range_start = 40,
+ .range_num = 3,
+ },
+ /* RX channels */
+ {
+ .dev_id = 329,
+ .subtype = 10,
+ .range_start = 40,
+ .range_num = 3,
+ },
+ /* RX Free flows */
+ {
+ .dev_id = 329,
+ .subtype = 0,
+ .range_start = 84,
+ .range_num = 8,
+ },
+ { },
+};
+#endif /* CONFIG_SOC_K3_J784S4 */
+
#else
static struct ti_sci_resource_static_data rm_static_data[] = {
{ },
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 05/10] clk: clk-k3: Add support for J784S4 SoC
2023-03-21 14:10 [PATCH v2 00/10] Introduce initial TI's J784S4 support Hari Nagalla
` (3 preceding siblings ...)
2023-03-21 14:10 ` [PATCH v2 04/10] drivers: dma: Add support for J784S4 Hari Nagalla
@ 2023-03-21 14:10 ` Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 06/10] power: domain: ti: " Hari Nagalla
` (5 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Hari Nagalla @ 2023-03-21 14:10 UTC (permalink / raw)
To: trini; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
Add support for J784S4 SoC.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
---
arch/arm/mach-k3/j784s4/clk-data.c | 428 +++++++++++++++++++++++++++++
drivers/clk/ti/clk-k3.c | 6 +
include/k3-clk.h | 1 +
3 files changed, 435 insertions(+)
create mode 100644 arch/arm/mach-k3/j784s4/clk-data.c
diff --git a/arch/arm/mach-k3/j784s4/clk-data.c b/arch/arm/mach-k3/j784s4/clk-data.c
new file mode 100644
index 0000000000..1c9f0698ea
--- /dev/null
+++ b/arch/arm/mach-k3/j784s4/clk-data.c
@@ -0,0 +1,428 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J784S4 specific clock platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Bryan Brattlof <bb@ti.com>.
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <linux/clk-provider.h>
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+ "osc_19_2_mhz",
+ "osc_20_mhz",
+ "osc_24_mhz",
+ "osc_25_mhz",
+ "osc_26_mhz",
+ "osc_27_mhz",
+};
+
+static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
+ "board_0_mcu_ospi0_dqs_out",
+ "fss_mcu_0_ospi_0_ospi_oclk_clk",
+};
+
+static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
+ "board_0_mcu_ospi1_dqs_out",
+ "fss_mcu_0_ospi_1_ospi_oclk_clk",
+};
+
+static const char * const wkup_fref_clksel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
+ "wkup_fref_clksel_out0",
+ "hsdiv1_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const wkup_gpio0_clksel_out0_parents[] = {
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+ "j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+ "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const mcu_usart_clksel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "postdiv3_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out1_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out12_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out19_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out2_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out26_0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out27_0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out28_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out3_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out7_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out8_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const usb0_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const emmcsd1_lb_clksel_out0_parents[] = {
+ "board_0_mmc1_clklb_out",
+ "board_0_mmc1_clk_out",
+};
+
+static const char * const mcu_clkout_mux_out0_parents[] = {
+ "hsdiv4_16fft_mcu_2_hsdivout0_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout0_clk",
+};
+
+static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
+ "main_pll_hfosc_sel_out0",
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const dpi0_ext_clksel_out0_parents[] = {
+ "hsdiv1_16fft_main_19_hsdivout0_clk",
+ "board_0_vout0_extpclkin_out",
+};
+
+static const char * const emmcsd_refclk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout2_clk",
+ "hsdiv4_16fft_main_1_hsdivout2_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+ "hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out1_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout2_clk",
+ "hsdiv4_16fft_main_1_hsdivout2_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+ "hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const gtc_clk_mux_out0_parents[] = {
+ "hsdiv4_16fft_main_3_hsdivout1_clk",
+ "postdiv3_16fft_main_0_hsdivout6_clk",
+ "board_0_mcu_cpts0_rft_clk_out",
+ "board_0_cpts0_rft_clk_out",
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv4_16fft_mcu_2_hsdivout1_clk",
+ "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const struct clk_data clk_list[] = {
+ CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
+ CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
+ CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
+ CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
+ CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
+ CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
+ CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
+ CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
+ CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0),
+ CLK_FIXED_RATE("j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
+ CLK_FIXED_RATE("j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32000, 0),
+ CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
+ CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0),
+ CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
+ CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
+ CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
+ CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
+ CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0),
+ CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666),
+ CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
+ CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
+ CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
+ CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
+ CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
+ CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out26_0", main_pll_hfosc_sel_out26_0_parents, 2, 0x430080e8, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out27_0", main_pll_hfosc_sel_out27_0_parents, 2, 0x430080ec, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out28", main_pll_hfosc_sel_out28_parents, 2, 0x430080f0, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
+ CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
+ CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+ CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0),
+ CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0),
+ CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0, 2000000000),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_26_foutvcop_clk", "main_pll_hfosc_sel_out26_0", 0x69a000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_27_foutvcop_clk", "main_pll_hfosc_sel_out27_0", 0x69b000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_28_foutvcop_clk", "main_pll_hfosc_sel_out28", 0x69c000, 0),
+ CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0, 2000000000),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
+ CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
+ CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
+ CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
+ CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
+ CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0),
+ CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0),
+ CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
+ CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv0_16fft_main_27_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_27_foutvcop_clk", 0x69b080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv0_16fft_main_28_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_28_foutvcop_clk", 0x69c080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
+ CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
+ CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0),
+ CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0),
+ CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
+ CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0),
+ CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
+ CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
+ CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
+ CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
+ CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0),
+ CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
+};
+
+static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(198, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(198, 3, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+ DEV_CLK(198, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(61, 0, "gtc_clk_mux_out0"),
+ DEV_CLK(61, 1, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+ DEV_CLK(61, 2, "postdiv3_16fft_main_0_hsdivout6_clk"),
+ DEV_CLK(61, 3, "board_0_mcu_cpts0_rft_clk_out"),
+ DEV_CLK(61, 4, "board_0_cpts0_rft_clk_out"),
+ DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
+ DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+ DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(78, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
+ DEV_CLK(78, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(78, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
+ DEV_CLK(78, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
+ DEV_CLK(78, 4, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(78, 5, "board_0_hfosc1_clk_out"),
+ DEV_CLK(78, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(78, 8, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(78, 9, "board_0_hfosc1_clk_out"),
+ DEV_CLK(78, 10, "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+ DEV_CLK(78, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(78, 12, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(140, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(140, 2, "emmcsd_refclk_sel_out0"),
+ DEV_CLK(140, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(140, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+ DEV_CLK(140, 5, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(140, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+ DEV_CLK(141, 0, "emmcsd1_lb_clksel_out0"),
+ DEV_CLK(141, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(141, 4, "emmcsd_refclk_sel_out1"),
+ DEV_CLK(141, 5, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(141, 6, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+ DEV_CLK(141, 7, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(141, 8, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+ DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"),
+ DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(149, 0, "mcu_usart_clksel_out0"),
+ DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
+ DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"),
+ DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(157, 174, "mcu_clkout_mux_out0"),
+ DEV_CLK(157, 175, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
+ DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
+ DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 226, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 228, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+ DEV_CLK(157, 230, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+ DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 354, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(157, 359, "dpi0_ext_clksel_out0"),
+ DEV_CLK(157, 360, "mshsi2c_wkup_0_porscl"),
+ DEV_CLK(160, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(160, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(160, 4, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(160, 6, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(160, 8, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(161, 0, "board_0_mcu_ospi0_dqs_out"),
+ DEV_CLK(161, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(161, 2, "mcu_ospi0_iclk_sel_out0"),
+ DEV_CLK(161, 3, "board_0_mcu_ospi0_dqs_out"),
+ DEV_CLK(161, 4, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(161, 6, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(161, 7, "mcu_ospi_ref_clk_sel_out0"),
+ DEV_CLK(161, 8, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+ DEV_CLK(161, 9, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(162, 0, "board_0_mcu_ospi1_dqs_out"),
+ DEV_CLK(162, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(162, 2, "mcu_ospi1_iclk_sel_out0"),
+ DEV_CLK(162, 3, "board_0_mcu_ospi1_dqs_out"),
+ DEV_CLK(162, 4, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+ DEV_CLK(162, 6, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(162, 7, "mcu_ospi_ref_clk_sel_out1"),
+ DEV_CLK(162, 8, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+ DEV_CLK(162, 9, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(167, 0, "wkup_gpio0_clksel_out0"),
+ DEV_CLK(178, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(178, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(188, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(188, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(191, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(191, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+ DEV_CLK(191, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+ DEV_CLK(191, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(192, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(192, 1, "hsdiv0_16fft_main_26_hsdivout0_clk"),
+ DEV_CLK(192, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+ DEV_CLK(192, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(193, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(193, 1, "hsdiv0_16fft_main_27_hsdivout0_clk"),
+ DEV_CLK(193, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+ DEV_CLK(193, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(194, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(194, 1, "hsdiv0_16fft_main_28_hsdivout0_clk"),
+ DEV_CLK(194, 4, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+ DEV_CLK(194, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(201, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(201, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(243, 0, "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+ DEV_CLK(243, 1, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(243, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(279, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(279, 1, "board_0_wkup_i2c0_scl_out"),
+ DEV_CLK(279, 2, "wkup_i2c_mcupll_bypass_out0"),
+ DEV_CLK(279, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
+ DEV_CLK(279, 4, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(392, 0, "usart_programmable_clock_divider_out5"),
+ DEV_CLK(392, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(395, 0, "usart_programmable_clock_divider_out8"),
+ DEV_CLK(395, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(398, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(398, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(398, 2, "postdiv3_16fft_main_1_hsdivout7_clk"),
+ DEV_CLK(398, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(398, 20, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(398, 21, "usb0_refclk_sel_out0"),
+ DEV_CLK(398, 22, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(398, 23, "board_0_hfosc1_clk_out"),
+ DEV_CLK(398, 28, "board_0_tck_out"),
+};
+
+const struct ti_k3_clk_platdata j784s4_clk_platdata = {
+ .clk_list = clk_list,
+ .clk_list_cnt = 106,
+ .soc_dev_clk_data = soc_dev_clk_data,
+ .soc_dev_clk_data_cnt = 128,
+};
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index ba925fa3c4..0f0a54ecf3 100644
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@@ -85,6 +85,12 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
.family = "AM62AX",
.data = &am62ax_clk_platdata,
},
+#endif
+#ifdef CONFIG_SOC_K3_J784S4
+ {
+ .family = "J784S4",
+ .data = &j784s4_clk_platdata,
+ },
#endif
{ /* sentinel */ }
};
diff --git a/include/k3-clk.h b/include/k3-clk.h
index 49ba53d20f..dac9af6487 100644
--- a/include/k3-clk.h
+++ b/include/k3-clk.h
@@ -176,6 +176,7 @@ extern const struct ti_k3_clk_platdata j7200_clk_platdata;
extern const struct ti_k3_clk_platdata j721s2_clk_platdata;
extern const struct ti_k3_clk_platdata am62x_clk_platdata;
extern const struct ti_k3_clk_platdata am62ax_clk_platdata;
+extern const struct ti_k3_clk_platdata j784s4_clk_platdata;
struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
void __iomem *reg);
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 06/10] power: domain: ti: Add support for J784S4 SoC
2023-03-21 14:10 [PATCH v2 00/10] Introduce initial TI's J784S4 support Hari Nagalla
` (4 preceding siblings ...)
2023-03-21 14:10 ` [PATCH v2 05/10] clk: clk-k3: Add support for J784S4 SoC Hari Nagalla
@ 2023-03-21 14:10 ` Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 07/10] ram: k3-ddrss: " Hari Nagalla
` (4 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Hari Nagalla @ 2023-03-21 14:10 UTC (permalink / raw)
To: trini; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
Add support for J784S4 SoC.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
---
drivers/power/domain/ti-power-domain.c | 6 ++++++
include/k3-dev.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c
index 9e7151307c..0ff174e57e 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -98,6 +98,12 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
.family = "AM62AX",
.data = &am62ax_pd_platdata,
},
+#endif
+#ifdef CONFIG_SOC_K3_J784S4
+ {
+ .family = "J784S4",
+ .data = &j784s4_pd_platdata,
+ },
#endif
{ /* sentinel */ }
};
diff --git a/include/k3-dev.h b/include/k3-dev.h
index d288ae3be7..59970866f1 100644
--- a/include/k3-dev.h
+++ b/include/k3-dev.h
@@ -80,6 +80,7 @@ extern const struct ti_k3_pd_platdata j7200_pd_platdata;
extern const struct ti_k3_pd_platdata j721s2_pd_platdata;
extern const struct ti_k3_pd_platdata am62x_pd_platdata;
extern const struct ti_k3_pd_platdata am62ax_pd_platdata;
+extern const struct ti_k3_pd_platdata j784s4_pd_platdata;
u8 ti_pd_state(struct ti_pd *pd);
u8 lpsc_get_state(struct ti_lpsc *lpsc);
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 07/10] ram: k3-ddrss: Add support for J784S4 SoC
2023-03-21 14:10 [PATCH v2 00/10] Introduce initial TI's J784S4 support Hari Nagalla
` (5 preceding siblings ...)
2023-03-21 14:10 ` [PATCH v2 06/10] power: domain: ti: " Hari Nagalla
@ 2023-03-21 14:10 ` Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 08/10] soc: ti: k3-socinfo: Add entry " Hari Nagalla
` (3 subsequent siblings)
10 siblings, 0 replies; 22+ messages in thread
From: Hari Nagalla @ 2023-03-21 14:10 UTC (permalink / raw)
To: trini; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
Add support for DDR subsystem in J784S4 SoC.
Signed-off-by: Apurva Nandan <a-nandan@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
---
drivers/ram/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index e085119963..fac8c9314b 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -62,7 +62,7 @@ choice
depends on K3_DDRSS
prompt "K3 DDRSS Arch Support"
- default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2
+ default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
default K3_AM64_DDRSS if SOC_K3_AM642
default K3_AM64_DDRSS if SOC_K3_AM625
default K3_AM62A_DDRSS if SOC_K3_AM62A7
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 08/10] soc: ti: k3-socinfo: Add entry for J784S4 SoC
2023-03-21 14:10 [PATCH v2 00/10] Introduce initial TI's J784S4 support Hari Nagalla
` (6 preceding siblings ...)
2023-03-21 14:10 ` [PATCH v2 07/10] ram: k3-ddrss: " Hari Nagalla
@ 2023-03-21 14:10 ` Hari Nagalla
2023-05-09 4:10 ` Vignesh Raghavendra
2023-03-21 14:10 ` [PATCH v2 09/10] board: ti: j784s4: Add board support " Hari Nagalla
` (2 subsequent siblings)
10 siblings, 1 reply; 22+ messages in thread
From: Hari Nagalla @ 2023-03-21 14:10 UTC (permalink / raw)
To: trini; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
Add support for J784S4 SoC Identification.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
---
drivers/soc/soc_ti_k3.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index 8af0ac7051..caf8db9574 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -17,6 +17,7 @@
#define J721S2 0xbb75
#define AM62X 0xbb7e
#define AM62AX 0xbb8d
+#define J784S4 0xbb80
#define JTAG_ID_VARIANT_SHIFT 28
#define JTAG_ID_VARIANT_MASK (0xf << 28)
@@ -54,9 +55,14 @@ static const char *get_family_string(u32 idreg)
case AM62X:
family = "AM62X";
break;
+
case AM62AX:
family = "AM62AX";
+
+ case J784S4:
+ family = "J784S4";
break;
+
default:
family = "Unknown Silicon";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 09/10] board: ti: j784s4: Add board support for J784S4 SoC
2023-03-21 14:10 [PATCH v2 00/10] Introduce initial TI's J784S4 support Hari Nagalla
` (7 preceding siblings ...)
2023-03-21 14:10 ` [PATCH v2 08/10] soc: ti: k3-socinfo: Add entry " Hari Nagalla
@ 2023-03-21 14:10 ` Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 10/10] dt-bindings: ti-serdes-mux: Add defines " Hari Nagalla
2023-08-22 8:18 ` [PATCH v2 00/10] Introduce initial TI's J784S4 support Enric Balletbo i Serra
10 siblings, 0 replies; 22+ messages in thread
From: Hari Nagalla @ 2023-03-21 14:10 UTC (permalink / raw)
To: trini; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
Add board support for J784S4 SoC.
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
---
board/ti/j784s4/Kconfig | 61 +++++++++
board/ti/j784s4/MAINTAINERS | 7 +
board/ti/j784s4/Makefile | 8 ++
board/ti/j784s4/evm.c | 105 +++++++++++++++
configs/j784s4_evm_a72_defconfig | 213 +++++++++++++++++++++++++++++++
configs/j784s4_evm_r5_defconfig | 179 ++++++++++++++++++++++++++
6 files changed, 573 insertions(+)
create mode 100644 board/ti/j784s4/Kconfig
create mode 100644 board/ti/j784s4/MAINTAINERS
create mode 100644 board/ti/j784s4/Makefile
create mode 100644 board/ti/j784s4/evm.c
create mode 100644 configs/j784s4_evm_a72_defconfig
create mode 100644 configs/j784s4_evm_r5_defconfig
diff --git a/board/ti/j784s4/Kconfig b/board/ti/j784s4/Kconfig
new file mode 100644
index 0000000000..9b6e3bb3c4
--- /dev/null
+++ b/board/ti/j784s4/Kconfig
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+# Hari Nagalla <hnagalla@ti.com>
+
+choice
+ prompt "K3 J784S4 board"
+ optional
+
+config TARGET_J784S4_A72_EVM
+ bool "TI K3 based J784S4 EVM running on A72"
+ select ARM64
+ select SOC_K3_J784S4
+ select BOARD_LATE_INIT
+ select SYS_DISABLE_DCACHE_OPS
+
+config TARGET_J784S4_R5_EVM
+ bool "TI K3 based J784S4 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select SOC_K3_J784S4
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ imply SYS_K3_SPL_ATF
+
+endchoice
+
+if TARGET_J784S4_A72_EVM
+
+config SYS_BOARD
+ default "j784s4"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "j784s4_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J784S4_R5_EVM
+
+config SYS_BOARD
+ default "j784s4"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "j784s4_evm"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS
new file mode 100644
index 0000000000..7b45e409c6
--- /dev/null
+++ b/board/ti/j784s4/MAINTAINERS
@@ -0,0 +1,7 @@
+J784S4 BOARD
+M: Hari Nagalla <hnagalla@ti.com>
+S: Maintained
+F: board/ti/j784s4
+F: include/configs/j784s4_evm.h
+F: configs/j784s4_evm_r5_defconfig
+F: configs/j784s4_evm_a72_defconfig
diff --git a/board/ti/j784s4/Makefile b/board/ti/j784s4/Makefile
new file mode 100644
index 0000000000..fc98b24a2d
--- /dev/null
+++ b/board/ti/j784s4/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+# Hari Nagalla <hnagalla@ti.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evm.o
diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c
new file mode 100644
index 0000000000..13b6162329
--- /dev/null
+++ b/board/ti/j784s4/evm.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for J784S4 EVM
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
+ * Hari Nagalla <hnagalla@ti.com>
+ *
+ */
+
+#include <common.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <generic-phy.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <net.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <spl.h>
+#include <asm/arch/sys_proto.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+
+#include "../common/board_detect.h"
+
+#define board_is_j784s4_evm() board_ti_k3_is("J784S4-EVM")
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+#ifdef CONFIG_PHYS_64BIT
+ gd->ram_size = 0x100000000;
+#else
+ gd->ram_size = 0x80000000;
+#endif
+
+ return 0;
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+#ifdef CONFIG_PHYS_64BIT
+ /* Limit RAM used by U-Boot to the DDR low region */
+ if (gd->ram_top > 0x100000000)
+ return 0x100000000;
+#endif
+
+ return gd->ram_top;
+}
+
+int dram_init_banksize(void)
+{
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x7fffffff;
+ gd->ram_size = 0x80000000;
+
+#ifdef CONFIG_PHYS_64BIT
+ /* Bank 1 declares the memory available in the DDR high region */
+ gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].size = 0x77fffffff;
+ gd->ram_size = 0x800000000;
+#endif
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ int ret;
+
+ ret = fdt_fixup_msmc_ram(blob, "/bus@100000", "sram@70000000");
+ if (ret < 0)
+ ret = fdt_fixup_msmc_ram(blob, "/interconnect@100000",
+ "sram@70000000");
+ if (ret)
+ printf("%s: fixing up msmc ram failed %d\n", __func__, ret);
+
+ return ret;
+}
+#endif
+
+int board_late_init(void)
+{
+ if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
+ setup_board_eeprom_env();
+ setup_serial();
+ }
+
+ return 0;
+}
+
+void spl_board_init(void)
+{
+}
diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
new file mode 100644
index 0000000000..7de8925b27
--- /dev/null
+++ b/configs/j784s4_evm_a72_defconfig
@@ -0,0 +1,213 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_J784S4=y
+CONFIG_TARGET_J784S4_A72_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_OFFSET=0x680000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j784s4-evm"
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_ENV_OFFSET_REDUND=0x6A0000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern; setenv fdtfile ti/${name_fdt}; run distro_bootcmd"
+CONFIG_LOGLEVEL=7
+CONFIG_SPL_MAX_SIZE=0xc0000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80a00000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+# CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_UFS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),-@8m(hbmc.rootfs)"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_OF_LIST="k3-j784s4-evm"
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_MULTIPLEXER=y
+CONFIG_MUX_MMIO=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_FIXED=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+CONFIG_PHY_CADENCE_TORRENT=y
+CONFIG_PHY_J721E_WIZ=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_REMOTEPROC_TI_K3_DSP=y
+CONFIG_REMOTEPROC_TI_K3_R5F=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
+CONFIG_UFS=y
+CONFIG_CADENCE_UFS=y
+CONFIG_TI_J721E_UFS=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig
new file mode 100644
index 0000000000..5f9f74e3fc
--- /dev/null
+++ b/configs/j784s4_evm_r5_defconfig
@@ -0,0 +1,179 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SOC_K3_J784S4=y
+CONFIG_K3_EARLY_CONS=y
+CONFIG_TARGET_J784S4_R5_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j784s4-r5-evm"
+CONFIG_SPL_TEXT_BASE=0x41c00000
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0x80000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_USE_BOOTCOMMAND=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_MAX_SIZE=0xc0000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x41c76000
+CONFIG_SPL_BSS_MAX_SIZE=0xa000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+# CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_OF_LIST="k3-j784s4-r5-evm"
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HX_T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=133333333
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6168
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_PANIC_HANG=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 10/10] dt-bindings: ti-serdes-mux: Add defines for J784S4 SoC
2023-03-21 14:10 [PATCH v2 00/10] Introduce initial TI's J784S4 support Hari Nagalla
` (8 preceding siblings ...)
2023-03-21 14:10 ` [PATCH v2 09/10] board: ti: j784s4: Add board support " Hari Nagalla
@ 2023-03-21 14:10 ` Hari Nagalla
2023-08-22 8:18 ` [PATCH v2 00/10] Introduce initial TI's J784S4 support Enric Balletbo i Serra
10 siblings, 0 replies; 22+ messages in thread
From: Hari Nagalla @ 2023-03-21 14:10 UTC (permalink / raw)
To: trini; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
There are 4 instances of SERDES modules, with each instance supporting 4
lanes.
Signed-off-by: Matthew Ranostay <mranostay@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
---
include/dt-bindings/mux/ti-serdes.h | 62 +++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
index d3116c52ab..669ca2d6ab 100644
--- a/include/dt-bindings/mux/ti-serdes.h
+++ b/include/dt-bindings/mux/ti-serdes.h
@@ -117,4 +117,66 @@
#define J721S2_SERDES0_LANE3_USB 0x2
#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3
+/* J784S4 */
+
+#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0
+#define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1
+#define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2
+#define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3
+
+#define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0
+#define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1
+#define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2
+#define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3
+
+#define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0
+#define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1
+#define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2
+#define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3
+
+#define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0
+#define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1
+#define J784S4_SERDES0_LANE3_USB 0x2
+#define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0
+#define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1
+#define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2
+#define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0
+#define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1
+#define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2
+#define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0
+#define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1
+#define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2
+#define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3
+
+#define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0
+#define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1
+#define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2
+#define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0
+#define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1
+#define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0
+#define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1
+#define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0
+#define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1
+#define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3
+
+#define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0
+#define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1
+#define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2
+#define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3
+
#endif /* _DT_BINDINGS_MUX_TI_SERDES */
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v2 03/10] arm: K3: Add basic support for J784S4 SoC definition
2023-03-21 14:10 ` [PATCH v2 03/10] arm: K3: Add basic support for J784S4 SoC definition Hari Nagalla
@ 2023-03-21 14:25 ` Andrew Davis
2023-03-21 15:52 ` Tom Rini
2023-05-09 4:19 ` Vignesh Raghavendra
2 siblings, 0 replies; 22+ messages in thread
From: Andrew Davis @ 2023-03-21 14:25 UTC (permalink / raw)
To: Hari Nagalla, trini; +Cc: lukma, seanga2, jh80.chung, nm, a-nandan, u-boot
On 3/21/23 9:10 AM, Hari Nagalla wrote:
> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
> Signed-off-by: Bryan Bratloff <bb@ti.com>
> Signed-off-by: Nishant Menon <nm@ti.com>
> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
> ---
> arch/arm/mach-k3/Kconfig | 16 +-
> arch/arm/mach-k3/Makefile | 2 +
> arch/arm/mach-k3/arm64-mmu.c | 41 +++
> arch/arm/mach-k3/include/mach/hardware.h | 4 +
> .../mach-k3/include/mach/j784s4_hardware.h | 41 +++
> arch/arm/mach-k3/include/mach/j784s4_spl.h | 46 +++
> arch/arm/mach-k3/include/mach/spl.h | 6 +-
> arch/arm/mach-k3/j784s4/Makefile | 5 +
> arch/arm/mach-k3/j784s4/dev-data.c | 97 ++++++
> arch/arm/mach-k3/j784s4_init.c | 319 ++++++++++++++++++
> board/ti/j784s4/j784s4.env | 108 ++++++
> include/configs/j784s4_evm.h | 49 +++
> 12 files changed, 727 insertions(+), 7 deletions(-)
> create mode 100644 arch/arm/mach-k3/include/mach/j784s4_hardware.h
> create mode 100644 arch/arm/mach-k3/include/mach/j784s4_spl.h
> create mode 100644 arch/arm/mach-k3/j784s4/Makefile
> create mode 100644 arch/arm/mach-k3/j784s4/dev-data.c
> create mode 100644 arch/arm/mach-k3/j784s4_init.c
> create mode 100644 board/ti/j784s4/j784s4.env
> create mode 100644 include/configs/j784s4_evm.h
>
> diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
> index a8c3a593d5..3a9be0a590 100644
> --- a/arch/arm/mach-k3/Kconfig
> +++ b/arch/arm/mach-k3/Kconfig
> @@ -22,6 +22,9 @@ config SOC_K3_AM625
> config SOC_K3_AM62A7
> bool "TI's K3 based AM62A7 SoC Family Support"
>
> +config SOC_K3_J784S4
> + bool "TI's K3 based J784S4 SoC Family Support"
> +
> endchoice
>
> config SYS_SOC
> @@ -30,7 +33,7 @@ config SYS_SOC
> config SYS_K3_NON_SECURE_MSRAM_SIZE
> hex
> default 0x80000 if SOC_K3_AM654
> - default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2
> + default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
> default 0x1c0000 if SOC_K3_AM642
> default 0x3c000 if SOC_K3_AM625 || SOC_K3_AM62A7
> help
> @@ -42,7 +45,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
> config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
> hex
> default 0x58000 if SOC_K3_AM654
> - default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2
> + default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
> default 0x180000 if SOC_K3_AM642
> default 0x38000 if SOC_K3_AM625 || SOC_K3_AM62A7
> help
> @@ -52,14 +55,14 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
> config SYS_K3_MCU_SCRATCHPAD_BASE
> hex
> default 0x40280000 if SOC_K3_AM654
> - default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2
> + default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
> help
> Describes the base address of MCU Scratchpad RAM.
>
> config SYS_K3_MCU_SCRATCHPAD_SIZE
> hex
> default 0x200 if SOC_K3_AM654
> - default 0x200 if SOC_K3_J721E || SOC_K3_J721S2
> + default 0x200 if SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_J784S4
> help
> Describes the size of MCU Scratchpad RAM.
>
> @@ -67,7 +70,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
> hex
> default 0x41c7fbfc if SOC_K3_AM654
> default 0x41cffbfc if SOC_K3_J721E
> - default 0x41cfdbfc if SOC_K3_J721S2
> + default 0x41cfdbfc if SOC_K3_J721S2 || SOC_K3_J784S4
> default 0x701bebfc if SOC_K3_AM642
> default 0x43c3f290 if SOC_K3_AM625
> default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
> @@ -172,7 +175,7 @@ config K3_ATF_LOAD_ADDR
>
> config K3_DM_FW
> bool "Separate DM firmware image"
> - depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
> + depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_J784S4) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
> default y
> help
> Enabling this will indicate that the system has separate DM
> @@ -194,4 +197,5 @@ source "board/ti/am62ax/Kconfig"
> source "board/ti/j721e/Kconfig"
> source "board/siemens/iot2050/Kconfig"
> source "board/ti/j721s2/Kconfig"
> +source "board/ti/j784s4/Kconfig"
> endif
> diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
> index b5bc236781..14cf85ad38 100644
> --- a/arch/arm/mach-k3/Makefile
> +++ b/arch/arm/mach-k3/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/
> obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
> obj-$(CONFIG_SOC_K3_AM625) += am62x/
> obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
> +obj-$(CONFIG_SOC_K3_J784S4) += j784s4/
> obj-$(CONFIG_ARM64) += arm64-mmu.o
> obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
> obj-$(CONFIG_ARM64) += cache.o
> @@ -17,6 +18,7 @@ obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o
> obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
> obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
> obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
> +obj-$(CONFIG_SOC_K3_J784S4) += j784s4_init.o
> obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
> endif
> obj-y += common.o security.o
> diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
> index 88687c2d09..610ff19696 100644
> --- a/arch/arm/mach-k3/arm64-mmu.c
> +++ b/arch/arm/mach-k3/arm64-mmu.c
> @@ -264,3 +264,44 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
>
> struct mm_region *mem_map = am64_mem_map;
> #endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
> +
> +#if defined(CONFIG_SOC_K3_J784S4)
> +#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
> +
> +/* ToDo: Add 64bit IO */
The second block of IO mem at 0x500000000UL is the 64bit IO, this TODO is not needed.
> +struct mm_region j784s4_mem_map[NR_MMU_REGIONS] = {
> + {
> + .virt = 0x0UL,
> + .phys = 0x0UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + .virt = 0x80000000UL,
> + .phys = 0x80000000UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE
> + }, {
> + .virt = 0x880000000UL,
> + .phys = 0x880000000UL,
> + .size = 0x80000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE
> + }, {
> + .virt = 0x500000000UL,
> + .phys = 0x500000000UL,
> + .size = 0x400000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* List terminator */
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = j784s4_mem_map;
> +
> +#endif /* CONFIG_SOC_K3_J784S4 */
> diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
> index 2c60ef8543..77f36c6707 100644
> --- a/arch/arm/mach-k3/include/mach/hardware.h
> +++ b/arch/arm/mach-k3/include/mach/hardware.h
> @@ -30,6 +30,10 @@
> #include "am62a_hardware.h"
> #endif
>
> +#ifdef CONFIG_SOC_K3_J784S4
> +#include "j784s4_hardware.h"
> +#endif
> +
> /* Assuming these addresses and definitions stay common across K3 devices */
> #define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14)
> #define JTAG_ID_VARIANT_SHIFT 28
> diff --git a/arch/arm/mach-k3/include/mach/j784s4_hardware.h b/arch/arm/mach-k3/include/mach/j784s4_hardware.h
> new file mode 100644
> index 0000000000..afcf39c45d
> --- /dev/null
> +++ b/arch/arm/mach-k3/include/mach/j784s4_hardware.h
> @@ -0,0 +1,41 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * K3: J784S4 SoC definitions, structures etc.
> + *
> + * (C) Copyright (C) 2022 Texas Instruments Incorporated - http://www.ti.com/
Why two (C)? And the address should have https not http. Fix this everywhere in this series.
Andrew
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 02/10] arm: dts: introduce j784s4 u-boot dtbs
2023-03-21 14:10 ` [PATCH v2 02/10] arm: dts: introduce j784s4 u-boot dtbs Hari Nagalla
@ 2023-03-21 15:52 ` Tom Rini
2023-04-14 8:32 ` Siddharth Vadapalli
1 sibling, 0 replies; 22+ messages in thread
From: Tom Rini @ 2023-03-21 15:52 UTC (permalink / raw)
To: Hari Nagalla; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
[-- Attachment #1: Type: text/plain, Size: 1494 bytes --]
On Tue, Mar 21, 2023 at 09:10:20AM -0500, Hari Nagalla wrote:
> Introduce the base dts files needed for u-boot or to augment the linux
> dtbs for use in the u-boot-spl and u-boot binaries.
>
> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
> ---
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi | 8757 +++++++++++++++++
> arch/arm/dts/k3-j784s4-ddr.dtsi | 8858 ++++++++++++++++++
> arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 135 +
> arch/arm/dts/k3-j784s4-r5-evm.dts | 209 +
> 5 files changed, 17961 insertions(+)
> create mode 100644 arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4-ddr.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4-r5-evm.dts
Good news/bad news.
[snip]
> + msmc0: msmc {
[snip]
> + u-boot,dm-spl;
This is now "bootph-pre-ram" and gets sent upstream to Linux, as the
binding is there now. Please do that and then rework the first patch to
be a sync from -next or similar, that contains these changes.
And yes, this is the first example I found of properties that should be
bootph-* now instead, and there's some bindings you have in-progress and
so yes, will include these for now in the -u-boot.dtsi file. But others
don't, and this needs to be on top of -next and CI passing.
--
Tom
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 03/10] arm: K3: Add basic support for J784S4 SoC definition
2023-03-21 14:10 ` [PATCH v2 03/10] arm: K3: Add basic support for J784S4 SoC definition Hari Nagalla
2023-03-21 14:25 ` Andrew Davis
@ 2023-03-21 15:52 ` Tom Rini
2023-05-09 4:19 ` Vignesh Raghavendra
2 siblings, 0 replies; 22+ messages in thread
From: Tom Rini @ 2023-03-21 15:52 UTC (permalink / raw)
To: Hari Nagalla; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
[-- Attachment #1: Type: text/plain, Size: 1625 bytes --]
On Tue, Mar 21, 2023 at 09:10:21AM -0500, Hari Nagalla wrote:
Please include at least the usual one line summary here.
[snip]
> diff --git a/include/configs/j784s4_evm.h b/include/configs/j784s4_evm.h
> new file mode 100644
> index 0000000000..3e429fb036
> --- /dev/null
> +++ b/include/configs/j784s4_evm.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Configuration header file for K3 J784S4 EVM
> + *
> + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
> + * Hari Nagalla <hnagalla@ti.com>
> + */
> +
> +#ifndef __CONFIG_J784S4_EVM_H
> +#define __CONFIG_J784S4_EVM_H
> +
> +#include <linux/sizes.h>
> +#include <config_distro_bootcmd.h>
> +#include <environment/ti/mmc.h>
> +
> +/* DDR Configuration */
> +#define CFG_SYS_SDRAM_BASE1 0x880000000
> +
> +#ifdef CONFIG_CMD_MMC
> +#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
> +#else
> +#define DISTRO_BOOT_DEV_MMC(func)
> +#endif
> +
> +#ifdef CONFIG_CMD_PXE
> +#define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na)
> +#else
> +#define DISTRO_BOOT_DEV_PXE(func)
> +#endif
> +
> +#ifdef CONFIG_CMD_DHCP
> +#define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na)
> +#else
> +#define DISTRO_BOOT_DEV_DHCP(func)
> +#endif
> +
> +#define BOOT_TARGET_DEVICES(func) \
> + DISTRO_BOOT_DEV_MMC(func) \
> + DISTRO_BOOT_DEV_PXE(func) \
> + DISTRO_BOOT_DEV_DHCP(func)
I think you should look at using BOOTSTD here, to start with, rather
than the distro_bootcmd macros. Converting the rest of K3 to use this as
well can be a later task.
--
Tom
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 01/10] arm: dts: introduce j784s4 dtbs from linux kernel
2023-03-21 14:10 ` [PATCH v2 01/10] arm: dts: introduce j784s4 dtbs from linux kernel Hari Nagalla
@ 2023-03-21 15:57 ` Bryan Brattlof
2023-04-14 5:46 ` Siddharth Vadapalli
1 sibling, 0 replies; 22+ messages in thread
From: Bryan Brattlof @ 2023-03-21 15:57 UTC (permalink / raw)
To: Hari Nagalla; +Cc: trini, lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
Hi Hari!
On March 21, 2023 thus sayeth Hari Nagalla:
> Introduce the basic j784s4 SoC dtbs from the linux kernel along with
> the new j784s4 specific pinmux definitions that we will use to generate
> the dtbs for the u-boot-spl and u-boot binaries.
>
We should probably specify which kernel version this is from, just to
help our future selves happy.
> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
> ---
> arch/arm/dts/k3-j784s4-evm.dts | 196 +++++
> arch/arm/dts/k3-j784s4-main.dtsi | 1007 ++++++++++++++++++++++++
> arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi | 311 ++++++++
> arch/arm/dts/k3-j784s4.dtsi | 287 +++++++
> include/dt-bindings/pinctrl/k3.h | 3 +
> 5 files changed, 1804 insertions(+)
> create mode 100644 arch/arm/dts/k3-j784s4-evm.dts
> create mode 100644 arch/arm/dts/k3-j784s4-main.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4.dtsi
>
~Bryan
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 01/10] arm: dts: introduce j784s4 dtbs from linux kernel
2023-03-21 14:10 ` [PATCH v2 01/10] arm: dts: introduce j784s4 dtbs from linux kernel Hari Nagalla
2023-03-21 15:57 ` Bryan Brattlof
@ 2023-04-14 5:46 ` Siddharth Vadapalli
1 sibling, 0 replies; 22+ messages in thread
From: Siddharth Vadapalli @ 2023-04-14 5:46 UTC (permalink / raw)
To: Hari Nagalla, trini, a-nandan
Cc: lukma, seanga2, jh80.chung, nm, afd, u-boot, j-choudhary,
Vignesh Raghavendra, Udit Kumar, s-vadapalli
Hello Hari,
On 21/03/23 19:40, Hari Nagalla wrote:
> Introduce the basic j784s4 SoC dtbs from the linux kernel along with
> the new j784s4 specific pinmux definitions that we will use to generate
> the dtbs for the u-boot-spl and u-boot binaries.
>
> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
> ---
> arch/arm/dts/k3-j784s4-evm.dts | 196 +++++
> arch/arm/dts/k3-j784s4-main.dtsi | 1007 ++++++++++++++++++++++++
> arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi | 311 ++++++++
> arch/arm/dts/k3-j784s4.dtsi | 287 +++++++
> include/dt-bindings/pinctrl/k3.h | 3 +
> 5 files changed, 1804 insertions(+)
> create mode 100644 arch/arm/dts/k3-j784s4-evm.dts
> create mode 100644 arch/arm/dts/k3-j784s4-main.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4.dtsi
>
> diff --git a/arch/arm/dts/k3-j784s4-evm.dts b/arch/arm/dts/k3-j784s4-evm.dts
> new file mode 100644
> index 0000000000..8cd4a7ecc1
> --- /dev/null
> +++ b/arch/arm/dts/k3-j784s4-evm.dts
> @@ -0,0 +1,196 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
> + *
[...]
> +
> +&main_gpio0 {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/k3-j784s4-main.dtsi b/arch/arm/dts/k3-j784s4-main.dtsi
> new file mode 100644
> index 0000000000..7edf324ac1
> --- /dev/null
> +++ b/arch/arm/dts/k3-j784s4-main.dtsi
> @@ -0,0 +1,1007 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for J784S4 SoC Family Main Domain peripherals
> + *
> + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +&cbass_main {
> + msmc_ram: sram@70000000 {
> + compatible = "mmio-sram";
> + reg = <0x00 0x70000000 0x00 0x800000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x00 0x00 0x70000000 0x800000>;
> +
> + atf-sram@0 {
> + reg = <0x00 0x20000>;
> + };
> +
> + tifs-sram@1f0000 {
> + reg = <0x1f0000 0x10000>;
> + };
> +
> + l3cache-sram@200000 {
[...]
> +
> + main_navss: bus@30000000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
The property: ti,sci-dev-id = <280>; is missing here.
Please refer:
https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com/
> + dma-coherent;
> + dma-ranges;
> +
> + main_navss_intr: interrupt-controller@310e0000 {
> + compatible = "ti,sci-intr";
> + reg = <0x00 0x310e0000 0x00 0x4000>;
> + ti,intr-trigger-type = <4>;
> + interrupt-controller;
> + interrupt-parent = <&gic500>;
> + #interrupt-cells = <1>;
> + ti,sci = <&sms>;
> + ti,sci-dev-id = <283>;
> + ti,interrupt-ranges = <0 64 64>,
> + <64 448 64>,
> + <128 672 64>;
> + };
> +
[...]
> + interrupt-names = "int0", "int1";
> + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
> + status = "disabled";
> + };
> +};
> diff --git a/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
> new file mode 100644
> index 0000000000..93952af618
> --- /dev/null
> +++ b/arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
> @@ -0,0 +1,311 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals
> + *
> + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +&cbass_mcu_wakeup {
> + sms: system-controller@44083000 {
> + compatible = "ti,k2g-sci";
> + ti,host-id = <12>;
> +
> + mbox-names = "rx", "tx";
> +
> + mboxes = <&secure_proxy_main 11>,
> + <&secure_proxy_main 13>;
> +
> + reg-names = "debug_messages";
> + reg = <0x00 0x44083000 0x00 0x1000>;
> +
> + k3_pds: power-controller {
[...]
> + interrupt-names = "int0", "int1";
> + bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
> + status = "disabled";
> + };
> +
> + mcu_navss: bus@28380000{
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
The property ti,sci-dev-id = <323>; is missing here.
Please refer:
https://lore.kernel.org/r/20230314152611.140969-2-j-choudhary@ti.com/
> + dma-coherent;
> + dma-ranges;
> +
> + mcu_ringacc: ringacc@2b800000 {
> + compatible = "ti,am654-navss-ringacc";
> + reg = <0x00 0x2b800000 0x00 0x400000>,
[...]
--
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 02/10] arm: dts: introduce j784s4 u-boot dtbs
2023-03-21 14:10 ` [PATCH v2 02/10] arm: dts: introduce j784s4 u-boot dtbs Hari Nagalla
2023-03-21 15:52 ` Tom Rini
@ 2023-04-14 8:32 ` Siddharth Vadapalli
1 sibling, 0 replies; 22+ messages in thread
From: Siddharth Vadapalli @ 2023-04-14 8:32 UTC (permalink / raw)
To: Hari Nagalla, trini, nm
Cc: lukma, seanga2, jh80.chung, afd, a-nandan, u-boot, s-vadapalli
Hari,
On 21/03/23 19:40, Hari Nagalla wrote:
> Introduce the base dts files needed for u-boot or to augment the linux
> dtbs for use in the u-boot-spl and u-boot binaries.
>
> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
> ---
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi | 8757 +++++++++++++++++
> arch/arm/dts/k3-j784s4-ddr.dtsi | 8858 ++++++++++++++++++
> arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 135 +
> arch/arm/dts/k3-j784s4-r5-evm.dts | 209 +
> 5 files changed, 17961 insertions(+)
> create mode 100644 arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4-ddr.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4-r5-evm.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 7a577deb50..7690fd21db 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1264,6 +1264,8 @@ dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-base-board.dtb\
> k3-am68-sk-r5-base-board.dtb\
> k3-j721s2-common-proc-board.dtb\
> k3-j721s2-r5-common-proc-board.dtb
[...]
> +
> +&main_sdhci1 {
> + u-boot,dm-spl;
> +};
> diff --git a/arch/arm/dts/k3-j784s4-r5-evm.dts b/arch/arm/dts/k3-j784s4-r5-evm.dts
> new file mode 100644
> index 0000000000..7350a9be34
> --- /dev/null
> +++ b/arch/arm/dts/k3-j784s4-r5-evm.dts
> @@ -0,0 +1,209 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +
> +#include "k3-j784s4.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include "k3-j784s4-ddr-evm-lp4-4266.dtsi"
> +#include "k3-j784s4-ddr.dtsi"
Based on the patch by Nishanth at:
https://lore.kernel.org/r/20230414075726.387461-13-nm@ti.com/
It might be better for "k3-j784s4-r5-evm.dts" to inherit "k3-j784s4-evm.dts" as
it will prevent duplication.
[...]
--
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 08/10] soc: ti: k3-socinfo: Add entry for J784S4 SoC
2023-03-21 14:10 ` [PATCH v2 08/10] soc: ti: k3-socinfo: Add entry " Hari Nagalla
@ 2023-05-09 4:10 ` Vignesh Raghavendra
0 siblings, 0 replies; 22+ messages in thread
From: Vignesh Raghavendra @ 2023-05-09 4:10 UTC (permalink / raw)
To: Hari Nagalla, trini; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
On 21/03/23 19:40, Hari Nagalla wrote:
> Add support for J784S4 SoC Identification.
>
> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
> ---
> drivers/soc/soc_ti_k3.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
> index 8af0ac7051..caf8db9574 100644
> --- a/drivers/soc/soc_ti_k3.c
> +++ b/drivers/soc/soc_ti_k3.c
> @@ -17,6 +17,7 @@
> #define J721S2 0xbb75
> #define AM62X 0xbb7e
> #define AM62AX 0xbb8d
> +#define J784S4 0xbb80
>
> #define JTAG_ID_VARIANT_SHIFT 28
> #define JTAG_ID_VARIANT_MASK (0xf << 28)
> @@ -54,9 +55,14 @@ static const char *get_family_string(u32 idreg)
> case AM62X:
> family = "AM62X";
> break;
> +
> case AM62AX:
> family = "AM62AX";
> +
You are missing a break here. This will render AM62Ax unbootable as we
end up returning family as J784S4
> + case J784S4:
> + family = "J784S4";
> break;
> +
> default:
> family = "Unknown Silicon";
> };
--
Regards
Vignesh
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 03/10] arm: K3: Add basic support for J784S4 SoC definition
2023-03-21 14:10 ` [PATCH v2 03/10] arm: K3: Add basic support for J784S4 SoC definition Hari Nagalla
2023-03-21 14:25 ` Andrew Davis
2023-03-21 15:52 ` Tom Rini
@ 2023-05-09 4:19 ` Vignesh Raghavendra
2 siblings, 0 replies; 22+ messages in thread
From: Vignesh Raghavendra @ 2023-05-09 4:19 UTC (permalink / raw)
To: Hari Nagalla, trini; +Cc: lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
[...]
On 21/03/23 19:40, Hari Nagalla wrote:
> default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
> @@ -172,7 +175,7 @@ config K3_ATF_LOAD_ADDR
>
> config K3_DM_FW
> bool "Separate DM firmware image"
> - depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
> + depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7 || SOC_K3_J784S4) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
> default y
> help
> Enabling this will indicate that the system has separate DM
> @@ -194,4 +197,5 @@ source "board/ti/am62ax/Kconfig"
> source "board/ti/j721e/Kconfig"
> source "board/siemens/iot2050/Kconfig"
> source "board/ti/j721s2/Kconfig"
> +source "board/ti/j784s4/Kconfig"
You are adding file to Kconfig here, but the actual file itself is
introduced only in 9/10. This breaks git bisect. Please make sure each
individual each compile patch fine when applied in the order of posting.
> endif
[...]
--
Regards
Vignesh
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 00/10] Introduce initial TI's J784S4 support
2023-03-21 14:10 [PATCH v2 00/10] Introduce initial TI's J784S4 support Hari Nagalla
` (9 preceding siblings ...)
2023-03-21 14:10 ` [PATCH v2 10/10] dt-bindings: ti-serdes-mux: Add defines " Hari Nagalla
@ 2023-08-22 8:18 ` Enric Balletbo i Serra
2023-08-23 22:09 ` Hari Nagalla
10 siblings, 1 reply; 22+ messages in thread
From: Enric Balletbo i Serra @ 2023-08-22 8:18 UTC (permalink / raw)
To: Hari Nagalla; +Cc: trini, lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot
Hi Hari,
On Tue, Mar 21, 2023 at 3:12 PM Hari Nagalla <hnagalla@ti.com> wrote:
>
> Hello Everyone!
>
> This series will introduce basic support (SD and UART) support for Texas
> Instruments J784S4 EVM.
>
> The J784S4 SoC device tree patches are taken from kernel patch submissions
> and will be updated as they are accepted and merged to the kernel tree.
> All other patches are specific to SPL and u-boot and do not have
> dependency on other trees. Appreciate a review for acceptance to u-boot
> tree.
>
> Here are some of the salient features of the J784S4 automotive grade
> application processor:
>
> The J784S4 SoC belongs to the K3 Multicore SoC architecture
> platform, providing advanced system integration in automotive,
> ADAS and industrial applications requiring AI at the network edge.
> This SoC extends the K3 Jacinto 7 family of SoCs with focus on
> raising performance and integration while providing interfaces,
> memory architecture and compute performance for multi-sensor, high
> concurrency applications.
>
> Some highlights of this SoC are:
> * Up to 8 Cortex-A72s, four clusters of lockstep capable dual Cortex-R5F MCUs,
> 4 C7x floating point vector DSPs with Matrix Multiply Accelerator(MMA) for
> deep learning and CNN.
> * 3D GPU: Automotive grade IMG BXS-4-64
> * Vision Processing Accelerator (VPAC) with image signal processor and Depth
> and Motion Processing Accelerator (DMPAC)
> * Three CSI2.0 4L RX plus two CSI2.0 4L TX, two DSI Tx, one eDP/DP and one
> DPI interface.
> * Integrated gigabit ethernet switch, up to 8 ports (TDA4VH), two ports
> support 10Gb USXGMII; Two 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role
> device subsystems, Up to 20 MCANs, among other peripherals.
>
> See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022)
> for further details: http://www.ti.com/lit/zip/spruj52
>
> In addtion, the J784S4 EVM board is designed for TI J784S4 SoC. It
> supports the following interfaces:
> * 32 GB DDR4 RAM
> * x2 Gigabit Ethernet interfaces capable of working in Switch and MAC mode
> * x1 Input Audio Jack, x1 Output Audio Jack
> * x1 USB2.0 Hub with two Type A host and x1 USB 3.1 Type-C Port
> * x2 4L PCIe connector
> * x1 UHS-1 capable micro-SD card slot
> * 512 Mbit OSPI flash, 1 Gbit Octal NAND flash, 512 Mbit QSPI flash,
> UFS flash.
> * x6 UART through UART-USB bridge
> * XDS110 for onboard JTAG debug using USB
> * Temperature sensors, user push buttons and LEDs
> * 40-pin User Expansion Connector
> * x2 ENET Expansion Connector, x1 GESI expander, x2 Display connector
> * x1 15-pin CSI header
> * x6 MCAN instances
>
> Schematics: https://www.ti.com/lit/zip/sprr458
>
> bootlog: https://paste.sr.ht/~hnagalla/f14840abc854519f912923662f1fdc8075d92107
>
Many thanks for this patchset.
There is any plan to rebase all this patchset, fix the comments and
send it again to upstream? I'd be really interested in help on this
patchset.
Thanks,
Enric
> Changes in v2:
> - Refactored environement scripts to 'j784s4.env' and removed scripts not
> needed for basic board bootup.
> - Imported the J7874S4 basic device tree files from v6.2 linux kernel.
> - Moved j784s4 clock definitions and clock data into one patch/commit.
> - coalesce board commits into one commit.
>
> Hari Nagalla (10):
> arm: dts: introduce j784s4 dtbs from linux kernel
> arm: dts: introduce j784s4 u-boot dtbs
> arm: K3: Add basic support for J784S4 SoC definition
> drivers: dma: Add support for J784S4
> clk: clk-k3: Add support for J784S4 SoC
> power: domain: ti: Add support for J784S4 SoC
> ram: k3-ddrss: Add support for J784S4 SoC
> soc: ti: k3-socinfo: Add entry for J784S4 SoC
> board: ti: j784s4: Add board support for J784S4 SoC
> dt-bindings: ti-serdes-mux: Add defines for J784S4 SoC
>
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi | 8757 ++++++++++++++++
> arch/arm/dts/k3-j784s4-ddr.dtsi | 8858 +++++++++++++++++
> arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 135 +
> arch/arm/dts/k3-j784s4-evm.dts | 196 +
> arch/arm/dts/k3-j784s4-main.dtsi | 1007 ++
> arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi | 311 +
> arch/arm/dts/k3-j784s4-r5-evm.dts | 209 +
> arch/arm/dts/k3-j784s4.dtsi | 287 +
> arch/arm/mach-k3/Kconfig | 16 +-
> arch/arm/mach-k3/Makefile | 2 +
> arch/arm/mach-k3/arm64-mmu.c | 41 +
> arch/arm/mach-k3/include/mach/hardware.h | 4 +
> .../mach-k3/include/mach/j784s4_hardware.h | 41 +
> arch/arm/mach-k3/include/mach/j784s4_spl.h | 46 +
> arch/arm/mach-k3/include/mach/spl.h | 6 +-
> arch/arm/mach-k3/j784s4/Makefile | 5 +
> arch/arm/mach-k3/j784s4/clk-data.c | 428 +
> arch/arm/mach-k3/j784s4/dev-data.c | 97 +
> arch/arm/mach-k3/j784s4_init.c | 319 +
> board/ti/j784s4/Kconfig | 61 +
> board/ti/j784s4/MAINTAINERS | 7 +
> board/ti/j784s4/Makefile | 8 +
> board/ti/j784s4/evm.c | 105 +
> board/ti/j784s4/j784s4.env | 108 +
> configs/j784s4_evm_a72_defconfig | 213 +
> configs/j784s4_evm_r5_defconfig | 179 +
> drivers/clk/ti/clk-k3.c | 6 +
> drivers/dma/ti/Makefile | 1 +
> drivers/dma/ti/k3-psil-j784s4.c | 166 +
> drivers/dma/ti/k3-psil-priv.h | 1 +
> drivers/dma/ti/k3-psil.c | 2 +
> drivers/firmware/ti_sci_static_data.h | 35 +
> drivers/power/domain/ti-power-domain.c | 6 +
> drivers/ram/Kconfig | 2 +-
> drivers/soc/soc_ti_k3.c | 6 +
> include/configs/j784s4_evm.h | 49 +
> include/dt-bindings/mux/ti-serdes.h | 62 +
> include/dt-bindings/pinctrl/k3.h | 3 +
> include/k3-clk.h | 1 +
> include/k3-dev.h | 1 +
> 41 files changed, 21781 insertions(+), 8 deletions(-)
> create mode 100644 arch/arm/dts/k3-j784s4-ddr-evm-lp4-4266.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4-ddr.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4-evm-u-boot.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4-evm.dts
> create mode 100644 arch/arm/dts/k3-j784s4-main.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4-mcu-wakeup.dtsi
> create mode 100644 arch/arm/dts/k3-j784s4-r5-evm.dts
> create mode 100644 arch/arm/dts/k3-j784s4.dtsi
> create mode 100644 arch/arm/mach-k3/include/mach/j784s4_hardware.h
> create mode 100644 arch/arm/mach-k3/include/mach/j784s4_spl.h
> create mode 100644 arch/arm/mach-k3/j784s4/Makefile
> create mode 100644 arch/arm/mach-k3/j784s4/clk-data.c
> create mode 100644 arch/arm/mach-k3/j784s4/dev-data.c
> create mode 100644 arch/arm/mach-k3/j784s4_init.c
> create mode 100644 board/ti/j784s4/Kconfig
> create mode 100644 board/ti/j784s4/MAINTAINERS
> create mode 100644 board/ti/j784s4/Makefile
> create mode 100644 board/ti/j784s4/evm.c
> create mode 100644 board/ti/j784s4/j784s4.env
> create mode 100644 configs/j784s4_evm_a72_defconfig
> create mode 100644 configs/j784s4_evm_r5_defconfig
> create mode 100644 drivers/dma/ti/k3-psil-j784s4.c
> create mode 100644 include/configs/j784s4_evm.h
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 00/10] Introduce initial TI's J784S4 support
2023-08-22 8:18 ` [PATCH v2 00/10] Introduce initial TI's J784S4 support Enric Balletbo i Serra
@ 2023-08-23 22:09 ` Hari Nagalla
2023-08-24 0:12 ` Nishanth Menon
0 siblings, 1 reply; 22+ messages in thread
From: Hari Nagalla @ 2023-08-23 22:09 UTC (permalink / raw)
To: Enric Balletbo i Serra
Cc: trini, lukma, seanga2, jh80.chung, nm, afd, a-nandan, u-boot,
Kumar, Udit, Nandan, Apurva
On 8/22/23 03:18, Enric Balletbo i Serra wrote:
>> * Temperature sensors, user push buttons and LEDs
>> * 40-pin User Expansion Connector
>> * x2 ENET Expansion Connector, x1 GESI expander, x2 Display connector
>> * x1 15-pin CSI header
>> * x6 MCAN instances
>>
>> Schematics:https://www.ti.com/lit/zip/sprr458
>>
>> bootlog:https://paste.sr.ht/~hnagalla/f14840abc854519f912923662f1fdc8075d92107
>>
> Many thanks for this patchset.
>
> There is any plan to rebase all this patchset, fix the comments and
> send it again to upstream? I'd be really interested in help on this
> patchset.
>
> Thanks,
> Enric
>
Hi Enric,
Yes, we will rebase and send the patch set shortly.
Sorry for the delay.
Thanks
Hari
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 00/10] Introduce initial TI's J784S4 support
2023-08-23 22:09 ` Hari Nagalla
@ 2023-08-24 0:12 ` Nishanth Menon
0 siblings, 0 replies; 22+ messages in thread
From: Nishanth Menon @ 2023-08-24 0:12 UTC (permalink / raw)
To: Hari Nagalla
Cc: Enric Balletbo i Serra, trini, lukma, seanga2, jh80.chung, afd,
a-nandan, u-boot, Kumar, Udit
On 17:09-20230823, Hari Nagalla wrote:
> On 8/22/23 03:18, Enric Balletbo i Serra wrote:
> > > * Temperature sensors, user push buttons and LEDs
> > > * 40-pin User Expansion Connector
> > > * x2 ENET Expansion Connector, x1 GESI expander, x2 Display connector
> > > * x1 15-pin CSI header
> > > * x6 MCAN instances
> > >
> > > Schematics:https://www.ti.com/lit/zip/sprr458
> > >
> > > bootlog:https://paste.sr.ht/~hnagalla/f14840abc854519f912923662f1fdc8075d92107
> > >
> > Many thanks for this patchset.
> >
> > There is any plan to rebase all this patchset, fix the comments and
> > send it again to upstream? I'd be really interested in help on this
> > patchset.
> >
> > Thanks,
> > Enric
> >
> Hi Enric,
>
> Yes, we will rebase and send the patch set shortly.
>
> Sorry for the delay.
Let us ensure we have the proper cleanups done for other platforms,
documentation AND bootstd support as default.
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2023-08-24 0:12 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-21 14:10 [PATCH v2 00/10] Introduce initial TI's J784S4 support Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 01/10] arm: dts: introduce j784s4 dtbs from linux kernel Hari Nagalla
2023-03-21 15:57 ` Bryan Brattlof
2023-04-14 5:46 ` Siddharth Vadapalli
2023-03-21 14:10 ` [PATCH v2 02/10] arm: dts: introduce j784s4 u-boot dtbs Hari Nagalla
2023-03-21 15:52 ` Tom Rini
2023-04-14 8:32 ` Siddharth Vadapalli
2023-03-21 14:10 ` [PATCH v2 03/10] arm: K3: Add basic support for J784S4 SoC definition Hari Nagalla
2023-03-21 14:25 ` Andrew Davis
2023-03-21 15:52 ` Tom Rini
2023-05-09 4:19 ` Vignesh Raghavendra
2023-03-21 14:10 ` [PATCH v2 04/10] drivers: dma: Add support for J784S4 Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 05/10] clk: clk-k3: Add support for J784S4 SoC Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 06/10] power: domain: ti: " Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 07/10] ram: k3-ddrss: " Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 08/10] soc: ti: k3-socinfo: Add entry " Hari Nagalla
2023-05-09 4:10 ` Vignesh Raghavendra
2023-03-21 14:10 ` [PATCH v2 09/10] board: ti: j784s4: Add board support " Hari Nagalla
2023-03-21 14:10 ` [PATCH v2 10/10] dt-bindings: ti-serdes-mux: Add defines " Hari Nagalla
2023-08-22 8:18 ` [PATCH v2 00/10] Introduce initial TI's J784S4 support Enric Balletbo i Serra
2023-08-23 22:09 ` Hari Nagalla
2023-08-24 0:12 ` Nishanth Menon
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