* [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips
@ 2023-03-27 12:34 Mika Kahola
2023-03-27 12:34 ` [Intel-gfx] [PATCH 1/7] drm/i915/mtl: Initial DDI port setup Mika Kahola
` (15 more replies)
0 siblings, 16 replies; 37+ messages in thread
From: Mika Kahola @ 2023-03-27 12:34 UTC (permalink / raw)
To: intel-gfx
Phy programming support for C10 PICA chips. This is the first part of
the series that adds support for PICA chips. Later the support for
C20 chips are added.
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Clint Taylor (1):
drm/i915/mtl: Initial DDI port setup
Mika Kahola (3):
drm/i915/mtl: Add DP rates
drm/i915/mtl: Create separate reg file for PICA registers
drm/i915/mtl: Add support for PM DEMAND
Radhakrishna Sripada (3):
drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
drm/i915/mtl: Add C10 phy programming for HDMI
drm/i915/mtl: Add vswing programming for C10 phys
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1798 +++++++++++++++++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 46 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 178 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 26 +-
.../drm/i915/display/intel_ddi_buf_trans.c | 31 +-
.../drm/i915/display/intel_ddi_buf_trans.h | 6 +
drivers/gpu/drm/i915/display/intel_display.c | 20 +-
.../drm/i915/display/intel_display_power.c | 11 +-
.../i915/display/intel_display_power_map.c | 1 +
.../i915/display/intel_display_power_well.c | 2 +-
.../drm/i915/display/intel_display_types.h | 6 +
drivers/gpu/drm/i915/display/intel_dp.c | 15 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 20 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 5 +-
.../drm/i915/display/intel_modeset_verify.c | 2 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/i915_irq.c | 22 +-
drivers/gpu/drm/i915/i915_reg.h | 38 +-
drivers/gpu/drm/i915/i915_reg_defs.h | 57 +
drivers/gpu/drm/i915/intel_pm.c | 286 +++
drivers/gpu/drm/i915/intel_pm.h | 35 +
25 files changed, 2605 insertions(+), 15 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.c
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.h
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
--
2.34.1
^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 1/7] drm/i915/mtl: Initial DDI port setup
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
@ 2023-03-27 12:34 ` Mika Kahola
2023-03-28 11:41 ` Govindapillai, Vinod
2023-03-27 12:34 ` [Intel-gfx] [PATCH 2/7] drm/i915/mtl: Add DP rates Mika Kahola
` (14 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Mika Kahola @ 2023-03-27 12:34 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
From: Clint Taylor <clinton.a.taylor@intel.com>
Initialization sequences and C10 phy are in place to be able to enable
the first 2 ports of MTL. The other ports use C20 phy that still need
to be properly added. Enable the first ports for now, keeping a TODO
comment about the others.
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5a386c7c0bc9..9fe6e33a66d6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7796,7 +7796,11 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- if (IS_DG2(dev_priv)) {
+ if (IS_METEORLAKE(dev_priv)) {
+ /* TODO: initialize TC ports as well */
+ intel_ddi_init(dev_priv, PORT_A);
+ intel_ddi_init(dev_priv, PORT_B);
+ } else if (IS_DG2(dev_priv)) {
intel_ddi_init(dev_priv, PORT_A);
intel_ddi_init(dev_priv, PORT_B);
intel_ddi_init(dev_priv, PORT_C);
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 2/7] drm/i915/mtl: Add DP rates
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
2023-03-27 12:34 ` [Intel-gfx] [PATCH 1/7] drm/i915/mtl: Initial DDI port setup Mika Kahola
@ 2023-03-27 12:34 ` Mika Kahola
2023-03-28 12:49 ` Govindapillai, Vinod
2023-03-27 12:34 ` [Intel-gfx] [PATCH 3/7] drm/i915/mtl: Create separate reg file for PICA registers Mika Kahola
` (13 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Mika Kahola @ 2023-03-27 12:34 UTC (permalink / raw)
To: intel-gfx
Add DP rates for Meteorlake.
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index da1c00ee92fb..4927aeb64f23 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -420,6 +420,11 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
return 810000;
}
+static int mtl_max_source_rate(struct intel_dp *intel_dp)
+{
+ return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
+}
+
static int vbt_max_link_rate(struct intel_dp *intel_dp)
{
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
@@ -444,6 +449,10 @@ static void
intel_dp_set_source_rates(struct intel_dp *intel_dp)
{
/* The values must be in increasing order */
+ static const int mtl_rates[] = {
+ 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
+ 810000,
+ };
static const int icl_rates[] = {
162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
1000000, 1350000,
@@ -469,7 +478,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
drm_WARN_ON(&dev_priv->drm,
intel_dp->source_rates || intel_dp->num_source_rates);
- if (DISPLAY_VER(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ source_rates = mtl_rates;
+ size = ARRAY_SIZE(mtl_rates);
+ max_rate = mtl_max_source_rate(intel_dp);
+ } else if (DISPLAY_VER(dev_priv) >= 11) {
source_rates = icl_rates;
size = ARRAY_SIZE(icl_rates);
if (IS_DG2(dev_priv))
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 3/7] drm/i915/mtl: Create separate reg file for PICA registers
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
2023-03-27 12:34 ` [Intel-gfx] [PATCH 1/7] drm/i915/mtl: Initial DDI port setup Mika Kahola
2023-03-27 12:34 ` [Intel-gfx] [PATCH 2/7] drm/i915/mtl: Add DP rates Mika Kahola
@ 2023-03-27 12:34 ` Mika Kahola
2023-03-28 15:33 ` Govindapillai, Vinod
2023-03-27 12:34 ` [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming Mika Kahola
` (12 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Mika Kahola @ 2023-03-27 12:34 UTC (permalink / raw)
To: intel-gfx
Create a separate file to store registers for PICA chips
C10 and C20.
v2: Rename file (Jani)
v3: Use _PICK_EVEN_2RANGES() macro (Lucas)
Coding style fixed (Lucas)
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 131 ++++++++++++++++++
1 file changed, 131 insertions(+)
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
new file mode 100644
index 000000000000..d1ee8a2fc9cf
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_CX0_PHY_REGS_H__
+#define __INTEL_CX0_PHY_REGS_H__
+
+#include "i915_reg_defs.h"
+
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
+#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
+#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
+#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
+#define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
+#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
+#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
+#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
+#define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16)
+#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
+#define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
+#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
+#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
+#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
+#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
+#define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
+#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
+#define XELPDP_PORT_P2M_COMMAND_WRITE_ACK 0x5
+#define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16)
+#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
+#define XELPDP_PORT_P2M_ERROR_SET REG_BIT(15)
+
+#define XELPDP_MSGBUS_TIMEOUT_SLOW 1
+#define XELPDP_MSGBUS_TIMEOUT_FAST_US 2
+#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200
+#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20
+#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100
+#define XELPDP_PORT_RESET_START_TIMEOUT_US 5
+#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US 100
+#define XELPDP_PORT_RESET_END_TIMEOUT 15
+#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
+
+#define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
+#define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
+#define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200
+#define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400
+#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+ _XELPDP_PORT_BUF_CTL1_LN0_A, \
+ _XELPDP_PORT_BUF_CTL1_LN0_B, \
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC2))
+#define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
+#define XELPDP_PORT_REVERSAL REG_BIT(16)
+#define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6)
+#define XELPDP_TCSS_POWER_REQUEST REG_BIT(5)
+#define XELPDP_TCSS_POWER_STATE REG_BIT(4)
+#define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
+#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
+
+#define XELPDP_PORT_BUF_CTL2(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+ _XELPDP_PORT_BUF_CTL1_LN0_A, \
+ _XELPDP_PORT_BUF_CTL1_LN0_B, \
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4)
+#define XELPDP_LANE0_PIPE_RESET REG_BIT(31)
+#define XELPDP_LANE1_PIPE_RESET REG_BIT(30)
+#define XELPDP_LANE0_PHY_CURRENT_STATUS REG_BIT(29)
+#define XELPDP_LANE1_PHY_CURRENT_STATUS REG_BIT(28)
+#define XELPDP_LANE0_POWERDOWN_UPDATE REG_BIT(25)
+#define XELPDP_LANE1_POWERDOWN_UPDATE REG_BIT(24)
+#define XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK REG_GENMASK(23, 20)
+#define XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
+#define XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK REG_GENMASK(19, 16)
+#define XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val)
+#define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4)
+#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
+
+#define XELPDP_PORT_BUF_CTL3(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+ _XELPDP_PORT_BUF_CTL1_LN0_A, \
+ _XELPDP_PORT_BUF_CTL1_LN0_B, \
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8)
+#define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8)
+#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
+#define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
+#define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
+
+#define _XELPDP_PORT_CLOCK_CTL_A 0x640E0
+#define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
+#define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
+#define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460
+#define XELPDP_PORT_CLOCK_CTL(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+ _XELPDP_PORT_CLOCK_CTL_A, \
+ _XELPDP_PORT_CLOCK_CTL_B, \
+ _XELPDP_PORT_CLOCK_CTL_USBC1, \
+ _XELPDP_PORT_CLOCK_CTL_USBC2))
+#define XELPDP_LANE0_PCLK_PLL_REQUEST REG_BIT(31)
+#define XELPDP_LANE0_PCLK_PLL_ACK REG_BIT(30)
+#define XELPDP_LANE0_PCLK_REFCLK_REQUEST REG_BIT(29)
+#define XELPDP_LANE0_PCLK_REFCLK_ACK REG_BIT(28)
+#define XELPDP_LANE1_PCLK_PLL_REQUEST REG_BIT(27)
+#define XELPDP_LANE1_PCLK_PLL_ACK REG_BIT(26)
+#define XELPDP_LANE1_PCLK_REFCLK_REQUEST REG_BIT(25)
+#define XELPDP_LANE1_PCLK_REFCLK_ACK REG_BIT(24)
+#define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19)
+#define XELPDP_TBT_CLOCK_ACK REG_BIT(18)
+#define XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12)
+#define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val)
+#define XELPDP_DDI_CLOCK_SELECT_NONE 0x0
+#define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8
+#define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9
+#define XELPDP_DDI_CLOCK_SELECT_TBT_162 0xc
+#define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd
+#define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe
+#define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf
+#define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10)
+#define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8)
+#define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
+#define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
+
+#endif /* __INTEL_CX0_PHY_REGS_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
` (2 preceding siblings ...)
2023-03-27 12:34 ` [Intel-gfx] [PATCH 3/7] drm/i915/mtl: Create separate reg file for PICA registers Mika Kahola
@ 2023-03-27 12:34 ` Mika Kahola
2023-03-29 10:22 ` Govindapillai, Vinod
` (2 more replies)
2023-03-27 12:34 ` [Intel-gfx] [PATCH 5/7] drm/i915/mtl: Add C10 phy programming for HDMI Mika Kahola
` (11 subsequent siblings)
15 siblings, 3 replies; 37+ messages in thread
From: Mika Kahola @ 2023-03-27 12:34 UTC (permalink / raw)
To: intel-gfx
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
has a dedicated PIPE 5.2 Message bus for configuration. This message
bus is used to configure the phy internal registers.
XELPDP has C10 phys to drive output to the EDP and the native output
from the display engine. Add structures, programming hardware state
readout logic. Port clock calculations are similar to DG2. Use the DG2
formulae to calculate the port clock but use the relevant pll signals.
Note: PHY lane 0 is always used for PLL programming.
Add sequences for C10 phy enable/disable phy lane reset,
powerdown change sequence and phy lane programming.
Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
v2: Squash patches related to C10 phy message bus and pll
programming support (Jani)
Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
Move macro definitions (Jani)
DP rates as separate patch (Jani)
Spin out xelpdp register definitions into a separate file (Jani)
Replace macro to select registers based on phy lane with
function calls (Jani)
Fix styling issues (Jani)
Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
v3: Move clear request flag into try-loop
v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani)
use __intel_de_wait_for_register() instead of __intel_wait_for_register
and uncomment intel_uncore.h (Jani)
Add DP-alt support for PHY lane programming (Khaled)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1120 +++++++++++++++++
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 43 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 32 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 22 +-
.../drm/i915/display/intel_display_power.c | 3 +-
.../i915/display/intel_display_power_well.c | 2 +-
.../drm/i915/display/intel_display_types.h | 6 +
drivers/gpu/drm/i915/display/intel_dpll.c | 20 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
.../drm/i915/display/intel_modeset_verify.c | 2 +
drivers/gpu/drm/i915/i915_reg.h | 5 +
drivers/gpu/drm/i915/i915_reg_defs.h | 57 +
13 files changed, 1309 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.c
create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 057ef22fa9c6..57b1417792b4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -298,6 +298,7 @@ i915-y += \
display/icl_dsi.o \
display/intel_backlight.o \
display/intel_crt.o \
+ display/intel_cx0_phy.o \
display/intel_ddi.o \
display/intel_ddi_buf_trans.o \
display/intel_display_trace.o \
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
new file mode 100644
index 000000000000..ced8c8aa6c82
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -0,0 +1,1120 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "i915_reg.h"
+#include "intel_cx0_phy.h"
+#include "intel_cx0_phy_regs.h"
+#include "intel_de.h"
+#include "intel_display_types.h"
+#include "intel_dp.h"
+#include "intel_panel.h"
+#include "intel_tc.h"
+
+bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
+{
+ if (IS_METEORLAKE(dev_priv) && (phy < PHY_C))
+ return true;
+
+ return false;
+}
+
+static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, int lane)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+
+ /* Bring the phy to idle. */
+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
+ XELPDP_PORT_M2P_TRANSACTION_RESET);
+
+ /* Wait for Idle Clear. */
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
+ XELPDP_PORT_M2P_TRANSACTION_RESET,
+ XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+ drm_dbg_kms(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
+ return;
+ }
+
+ intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1), ~0);
+}
+
+static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port, int lane, u32 *val)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+
+ if (__intel_de_wait_for_register(i915,
+ XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1),
+ XELPDP_PORT_P2M_RESPONSE_READY,
+ XELPDP_PORT_P2M_RESPONSE_READY,
+ XELPDP_MSGBUS_TIMEOUT_FAST_US,
+ XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", phy_name(phy), *val);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int __intel_cx0_read(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u32 *val)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+ int ack;
+
+ /* Wait for pending transactions.*/
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
+ XELPDP_PORT_M2P_TRANSACTION_PENDING,
+ XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
+ intel_cx0_bus_reset(i915, port, lane);
+ return -ETIMEDOUT;
+ }
+
+ /* Issue the read command. */
+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
+ XELPDP_PORT_M2P_TRANSACTION_PENDING |
+ XELPDP_PORT_M2P_COMMAND_READ |
+ XELPDP_PORT_M2P_ADDRESS(addr));
+
+ /* Wait for response ready. And read response.*/
+ ack = intel_cx0_wait_for_ack(i915, port, lane, val);
+ if (ack < 0) {
+ intel_cx0_bus_reset(i915, port, lane);
+ return ack;
+ }
+
+ /* Check for error. */
+ if (*val & XELPDP_PORT_P2M_ERROR_SET) {
+ drm_dbg_kms(&i915->drm, "PHY %c Error occurred during read command. Status: 0x%x\n", phy_name(phy), *val);
+ intel_cx0_bus_reset(i915, port, lane);
+ return -EINVAL;
+ }
+
+ /* Check for Read Ack. */
+ if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) !=
+ XELPDP_PORT_P2M_COMMAND_READ_ACK) {
+ drm_dbg_kms(&i915->drm, "PHY %c Not a Read response. MSGBUS Status: 0x%x.\n", phy_name(phy), *val);
+ intel_cx0_bus_reset(i915, port, lane);
+ return -EINVAL;
+ }
+
+ /* Clear Response Ready flag.*/
+ intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1), ~0);
+
+ return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, *val);
+}
+
+static u8 intel_cx0_read(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+ int i, status = 0;
+ u32 val;
+
+ for (i = 0; i < 3; i++) {
+ status = __intel_cx0_read(i915, port, lane, addr, &val);
+
+ if (status >= 0)
+ break;
+ }
+
+ if (i == 3) {
+ drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n", phy_name(phy), addr, i);
+ return 0;
+ }
+
+ return status;
+}
+
+static int intel_cx0_wait_cwrite_ack(struct drm_i915_private *i915,
+ enum port port, int lane)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+ int ack;
+ u32 val = 0;
+
+ /* Check for write ack. */
+ ack = intel_cx0_wait_for_ack(i915, port, lane, &val);
+ if (ack < 0)
+ return ack;
+
+ if ((REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, val) !=
+ XELPDP_PORT_P2M_COMMAND_WRITE_ACK) || val & XELPDP_PORT_P2M_ERROR_SET) {
+ drm_dbg_kms(&i915->drm, "PHY %c Unexpected ACK received. MSGBUS STATUS: 0x%x.\n", phy_name(phy), val);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u8 data, bool committed)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+
+ /* Wait for pending transactions.*/
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
+ XELPDP_PORT_M2P_TRANSACTION_PENDING,
+ XELPDP_MSGBUS_TIMEOUT_SLOW)) {
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
+ intel_cx0_bus_reset(i915, port, lane);
+ return -ETIMEDOUT;
+ }
+
+ /* Issue the write command. */
+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
+ XELPDP_PORT_M2P_TRANSACTION_PENDING |
+ (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
+ XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
+ XELPDP_PORT_M2P_DATA(data) |
+ XELPDP_PORT_M2P_ADDRESS(addr));
+
+ /* Check for error. */
+ if (committed) {
+ if (intel_cx0_wait_cwrite_ack(i915, port, lane) < 0) {
+ intel_cx0_bus_reset(i915, port, lane);
+ return -EINVAL;
+ }
+ } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1)) &
+ XELPDP_PORT_P2M_ERROR_SET)) {
+ drm_dbg_kms(&i915->drm, "PHY %c Error occurred during write command.\n", phy_name(phy));
+ intel_cx0_bus_reset(i915, port, lane);
+ return -EINVAL;
+ }
+
+ intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1), ~0);
+
+ return 0;
+}
+
+static void __intel_cx0_write(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u8 data, bool committed)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+ int i, status;
+
+ for (i = 0; i < 3; i++) {
+ status = __intel_cx0_write_once(i915, port, lane, addr, data, committed);
+
+ if (status == 0)
+ break;
+ }
+
+ if (i == 3) {
+ drm_err_once(&i915->drm, "PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
+ return;
+ }
+}
+
+static void intel_cx0_write(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u8 data, bool committed)
+{
+ if (lane == INTEL_CX0_BOTH_LANES) {
+ __intel_cx0_write(i915, port, INTEL_CX0_LANE0, addr, data, committed);
+ __intel_cx0_write(i915, port, INTEL_CX0_LANE1, addr, data, committed);
+ } else {
+ __intel_cx0_write(i915, port, lane, addr, data, committed);
+ }
+}
+
+static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u8 clear, u8 set, bool committed)
+{
+ u8 old, val;
+
+ old = intel_cx0_read(i915, port, lane, addr);
+ val = (old & ~clear) | set;
+
+ if (val != old)
+ intel_cx0_write(i915, port, lane, addr, val, committed);
+}
+
+static void intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u8 clear, u8 set, bool committed)
+{
+ if (lane == INTEL_CX0_BOTH_LANES) {
+ __intel_cx0_rmw(i915, port, INTEL_CX0_LANE0, addr, clear, set, committed);
+ __intel_cx0_rmw(i915, port, INTEL_CX0_LANE1, addr, clear, set, committed);
+ } else {
+ __intel_cx0_rmw(i915, port, lane, addr, clear, set, committed);
+ }
+}
+
+/*
+ * Basic DP link rates with 38.4 MHz reference clock.
+ * Note: The tables below are with SSC. In non-ssc
+ * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
+ * programmed 0.
+ */
+
+static const struct intel_c10mpllb_state mtl_c10_dp_rbr = {
+ .clock = 162000,
+ .pll[0] = 0xB4,
+ .pll[1] = 0,
+ .pll[2] = 0x30,
+ .pll[3] = 0x1,
+ .pll[4] = 0x26,
+ .pll[5] = 0x0C,
+ .pll[6] = 0x98,
+ .pll[7] = 0x46,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xC0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x2,
+ .pll[16] = 0x84,
+ .pll[17] = 0x4F,
+ .pll[18] = 0xE5,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_edp_r216 = {
+ .clock = 216000,
+ .pll[0] = 0x4,
+ .pll[1] = 0,
+ .pll[2] = 0xA2,
+ .pll[3] = 0x1,
+ .pll[4] = 0x33,
+ .pll[5] = 0x10,
+ .pll[6] = 0x75,
+ .pll[7] = 0xB3,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x2,
+ .pll[16] = 0x85,
+ .pll[17] = 0x0F,
+ .pll[18] = 0xE6,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_edp_r243 = {
+ .clock = 243000,
+ .pll[0] = 0x34,
+ .pll[1] = 0,
+ .pll[2] = 0xDA,
+ .pll[3] = 0x1,
+ .pll[4] = 0x39,
+ .pll[5] = 0x12,
+ .pll[6] = 0xE3,
+ .pll[7] = 0xE9,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x20,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x2,
+ .pll[16] = 0x85,
+ .pll[17] = 0x8F,
+ .pll[18] = 0xE6,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_dp_hbr1 = {
+ .clock = 270000,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0xF8,
+ .pll[3] = 0x0,
+ .pll[4] = 0x20,
+ .pll[5] = 0x0A,
+ .pll[6] = 0x29,
+ .pll[7] = 0x10,
+ .pll[8] = 0x1, /* Verify */
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xA0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x1,
+ .pll[16] = 0x84,
+ .pll[17] = 0x4F,
+ .pll[18] = 0xE5,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_edp_r324 = {
+ .clock = 324000,
+ .pll[0] = 0xB4,
+ .pll[1] = 0,
+ .pll[2] = 0x30,
+ .pll[3] = 0x1,
+ .pll[4] = 0x26,
+ .pll[5] = 0x0C,
+ .pll[6] = 0x98,
+ .pll[7] = 0x46,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xC0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x1,
+ .pll[16] = 0x85,
+ .pll[17] = 0x4F,
+ .pll[18] = 0xE6,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_edp_r432 = {
+ .clock = 432000,
+ .pll[0] = 0x4,
+ .pll[1] = 0,
+ .pll[2] = 0xA2,
+ .pll[3] = 0x1,
+ .pll[4] = 0x33,
+ .pll[5] = 0x10,
+ .pll[6] = 0x75,
+ .pll[7] = 0xB3,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x1,
+ .pll[16] = 0x85,
+ .pll[17] = 0x0F,
+ .pll[18] = 0xE6,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_dp_hbr2 = {
+ .clock = 540000,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0xF8,
+ .pll[3] = 0,
+ .pll[4] = 0x20,
+ .pll[5] = 0x0A,
+ .pll[6] = 0x29,
+ .pll[7] = 0x10,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xA0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0,
+ .pll[16] = 0x84,
+ .pll[17] = 0x4F,
+ .pll[18] = 0xE5,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_edp_r675 = {
+ .clock = 675000,
+ .pll[0] = 0xB4,
+ .pll[1] = 0,
+ .pll[2] = 0x3E,
+ .pll[3] = 0x1,
+ .pll[4] = 0xA8,
+ .pll[5] = 0x0C,
+ .pll[6] = 0x33,
+ .pll[7] = 0x54,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xC8,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0,
+ .pll[16] = 0x85,
+ .pll[17] = 0x8F,
+ .pll[18] = 0xE6,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_dp_hbr3 = {
+ .clock = 810000,
+ .pll[0] = 0x34,
+ .pll[1] = 0,
+ .pll[2] = 0x84,
+ .pll[3] = 0x1,
+ .pll[4] = 0x30,
+ .pll[5] = 0x0F,
+ .pll[6] = 0x3D,
+ .pll[7] = 0x98,
+ .pll[8] = 0x1,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0xF0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0,
+ .pll[16] = 0x84,
+ .pll[17] = 0x0F,
+ .pll[18] = 0xE5,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state * const mtl_c10_dp_tables[] = {
+ &mtl_c10_dp_rbr,
+ &mtl_c10_dp_hbr1,
+ &mtl_c10_dp_hbr2,
+ &mtl_c10_dp_hbr3,
+ NULL,
+};
+
+static const struct intel_c10mpllb_state * const mtl_c10_edp_tables[] = {
+ &mtl_c10_dp_rbr,
+ &mtl_c10_edp_r216,
+ &mtl_c10_edp_r243,
+ &mtl_c10_dp_hbr1,
+ &mtl_c10_edp_r324,
+ &mtl_c10_edp_r432,
+ &mtl_c10_dp_hbr2,
+ &mtl_c10_edp_r675,
+ &mtl_c10_dp_hbr3,
+ NULL,
+};
+
+static const struct intel_c10mpllb_state * const *
+intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+ return mtl_c10_edp_tables;
+ else
+ return mtl_c10_dp_tables;
+ }
+
+ /* TODO: Add HDMI Support */
+ MISSING_CASE(encoder->type);
+ return NULL;
+}
+
+static int intel_c10mpllb_calc_state(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ const struct intel_c10mpllb_state * const *tables;
+ int i;
+
+ tables = intel_c10_mpllb_tables_get(crtc_state, encoder);
+ if (!tables)
+ return -EINVAL;
+
+ for (i = 0; tables[i]; i++) {
+ if (crtc_state->port_clock <= tables[i]->clock) {
+ crtc_state->c10mpllb_state = *tables[i];
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+int intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
+
+ return intel_c10mpllb_calc_state(crtc_state, encoder);
+}
+
+void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
+ struct intel_c10mpllb_state *pll_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
+ INTEL_CX0_LANE0;
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+ int i;
+ u8 cmn, tx0;
+
+ /*
+ * According to C10 VDR Register programming Sequence we need
+ * to do this to read PHY internal registers from MsgBus.
+ */
+ intel_cx0_rmw(i915, encoder->port, lane, PHY_C10_VDR_CONTROL(1), 0,
+ C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+
+ for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
+ pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane,
+ PHY_C10_VDR_PLL(i));
+
+ cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0));
+ tx0 = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0));
+
+ if (tx0 != C10_TX0_VAL || cmn != C10_CMN0_DP_VAL)
+ drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
+ tx0, cmn, phy_name(phy));
+}
+
+static void intel_c10_pll_program(struct drm_i915_private *i915,
+ const struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder)
+{
+ const struct intel_c10mpllb_state *pll_state = &crtc_state->c10mpllb_state;
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
+ INTEL_CX0_LANE0;
+ u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
+ INTEL_CX0_LANE1;
+
+ int i;
+ struct intel_dp *intel_dp;
+ bool use_ssc = false;
+ u8 cmn0 = 0;
+
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ intel_dp = enc_to_intel_dp(encoder);
+ use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
+ DP_MAX_DOWNSPREAD_0_5);
+
+ if (!intel_panel_use_ssc(i915))
+ use_ssc = false;
+
+ cmn0 = C10_CMN0_DP_VAL;
+ }
+
+ intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+ /* Custom width needs to be programmed to 0 for both the phy lanes */
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
+ PHY_C10_VDR_CUSTOM_WIDTH, 0x3, 0, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, follower_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MASTER_LANE, C10_VDR_CTRL_UPDATE_CFG,
+ MB_WRITE_COMMITTED);
+
+ /* Program the pll values only for the master lane */
+ for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
+ /* If not using ssc pll[4] through pll[8] must be 0*/
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_PLL(i),
+ (!use_ssc && (i > 3 && i < 9)) ? 0 : pll_state->pll[i],
+ (i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED);
+
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_TX(0), C10_TX0_VAL, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MASTER_LANE |
+ C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+}
+
+void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv,
+ const struct intel_c10mpllb_state *hw_state)
+{
+ bool fracen;
+ int i;
+ unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
+ unsigned int multiplier, tx_clk_div;
+
+ fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
+ drm_dbg_kms(&dev_priv->drm, "c10pll_hw_state: fracen: %s, ",
+ str_yes_no(fracen));
+
+ if (fracen) {
+ frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
+ frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13];
+ frac_den = hw_state->pll[10] << 8 | hw_state->pll[9];
+ drm_dbg_kms(&dev_priv->drm, "quot: %u, rem: %u, den: %u,\n",
+ frac_quot, frac_rem, frac_den);
+ }
+
+ multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |
+ hw_state->pll[2]) / 2 + 16;
+ tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);
+ drm_dbg_kms(&dev_priv->drm,
+ "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
+
+ drm_dbg_kms(&dev_priv->drm, "c10pll_rawhw_state:");
+
+ for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
+ drm_dbg_kms(&dev_priv->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
+ i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
+ i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
+}
+
+int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c10mpllb_state *pll_state)
+{
+ unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
+ unsigned int multiplier, tx_clk_div, refclk = 38400;
+
+ if (pll_state->pll[0] & C10_PLL0_FRACEN) {
+ frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
+ frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
+ frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
+ }
+
+ multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
+ pll_state->pll[2]) / 2 + 16;
+
+ tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
+
+ return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
+ DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
+ 10 << (tx_clk_div + 16));
+}
+
+static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ bool lane_reversal)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp;
+ bool ssc_enabled;
+ u32 val = 0;
+
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL,
+ lane_reversal ? XELPDP_PORT_REVERSAL : 0);
+
+ if (lane_reversal)
+ val |= XELPDP_LANE1_PHY_CLOCK_SELECT;
+
+ val |= XELPDP_FORWARD_CLOCK_UNGATE;
+ val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
+
+ if (intel_crtc_has_dp_encoder(crtc_state)) {
+ intel_dp = enc_to_intel_dp(encoder);
+ ssc_enabled = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
+ DP_MAX_DOWNSPREAD_0_5;
+
+ if (!intel_panel_use_ssc(i915))
+ ssc_enabled = false;
+
+ /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
+ val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
+ }
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_LANE1_PHY_CLOCK_SELECT |
+ XELPDP_FORWARD_CLOCK_UNGATE |
+ XELPDP_DDI_CLOCK_SELECT_MASK |
+ XELPDP_SSC_ENABLE_PLLB, val);
+}
+
+static u32 intel_cx0_get_powerdown_update(u8 lane)
+{
+ if (lane == INTEL_CX0_LANE0)
+ return XELPDP_LANE0_POWERDOWN_UPDATE;
+ else if (lane == INTEL_CX0_LANE1)
+ return XELPDP_LANE1_POWERDOWN_UPDATE;
+ else
+ return XELPDP_LANE0_POWERDOWN_UPDATE |
+ XELPDP_LANE1_POWERDOWN_UPDATE;
+}
+
+static u32 intel_cx0_get_powerdown_state(u8 lane, u8 state)
+{
+ if (lane == INTEL_CX0_LANE0)
+ return XELPDP_LANE0_POWERDOWN_NEW_STATE(state);
+ else if (lane == INTEL_CX0_LANE1)
+ return XELPDP_LANE1_POWERDOWN_NEW_STATE(state);
+ else
+ return XELPDP_LANE0_POWERDOWN_NEW_STATE(state) |
+ XELPDP_LANE1_POWERDOWN_NEW_STATE(state);
+}
+
+static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
+ enum port port,
+ u8 lane, u8 state)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK | XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK,
+ intel_cx0_get_powerdown_state(lane, state));
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_LANE0_POWERDOWN_UPDATE | XELPDP_LANE1_POWERDOWN_UPDATE,
+ intel_cx0_get_powerdown_update(lane));
+
+ /* Update Timeout Value */
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
+ intel_cx0_get_powerdown_update(lane), 0,
+ XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
+ drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
+ phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
+}
+
+static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port)
+{
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_POWER_STATE_READY_MASK,
+ XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port),
+ XELPDP_POWER_STATE_ACTIVE_MASK |
+ XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
+ XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
+ XELPDP_PLL_LANE_STAGGERING_DELAY(0));
+}
+
+static u32 intel_cx0_get_pclk_refclk_request(u8 lane)
+{
+ if (lane == INTEL_CX0_LANE0)
+ return XELPDP_LANE0_PCLK_REFCLK_REQUEST;
+ else if (lane == INTEL_CX0_LANE1)
+ return XELPDP_LANE1_PCLK_REFCLK_REQUEST;
+ else
+ return XELPDP_LANE0_PCLK_REFCLK_REQUEST |
+ XELPDP_LANE1_PCLK_REFCLK_REQUEST;
+}
+
+static u32 intel_cx0_get_pclk_refclk_ack(u8 lane)
+{
+ if (lane == INTEL_CX0_LANE0)
+ return XELPDP_LANE0_PCLK_REFCLK_ACK;
+ else if (lane == INTEL_CX0_LANE1)
+ return XELPDP_LANE1_PCLK_REFCLK_ACK;
+ else
+ return XELPDP_LANE0_PCLK_REFCLK_ACK |
+ XELPDP_LANE1_PCLK_REFCLK_ACK;
+}
+
+/* FIXME: Some Type-C cases need not reset both the lanes. Handle those cases. */
+static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, enum port port,
+ bool lane_reversal)
+{
+ enum phy phy = intel_port_to_phy(i915, port);
+ u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
+ INTEL_CX0_LANE0;
+
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
+ XELPDP_PORT_BUF_SOC_PHY_READY,
+ XELPDP_PORT_BUF_SOC_PHY_READY,
+ XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
+ drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
+ phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
+
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET,
+ XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET);
+
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_LANE0_PHY_CURRENT_STATUS | XELPDP_LANE1_PHY_CURRENT_STATUS,
+ XELPDP_LANE0_PHY_CURRENT_STATUS | XELPDP_LANE1_PHY_CURRENT_STATUS,
+ XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
+ drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
+ phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
+
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
+ intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES),
+ intel_cx0_get_pclk_refclk_request(lane));
+
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
+ intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES),
+ intel_cx0_get_pclk_refclk_ack(lane),
+ XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
+ drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
+ phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US);
+
+ intel_cx0_powerdown_change_sequence(i915, port, INTEL_CX0_BOTH_LANES,
+ CX0_P2_STATE_RESET);
+ intel_cx0_setup_powerdown(i915, port);
+
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET, 0);
+
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port),
+ XELPDP_LANE0_PHY_CURRENT_STATUS |
+ XELPDP_LANE1_PHY_CURRENT_STATUS,
+ XELPDP_PORT_RESET_END_TIMEOUT))
+ drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
+ phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
+}
+
+static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
+ struct intel_encoder *encoder, int lane_count,
+ bool lane_reversal)
+{
+ u8 l0t1, l0t2, l1t1, l1t2;
+ bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
+ enum port port = encoder->port;
+
+ intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MSGBUS_ACCESS,
+ MB_WRITE_COMMITTED);
+
+ l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
+ l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
+ l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2));
+ l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2));
+
+ if (lane_reversal) {
+ switch (lane_count) {
+ case 1:
+ /* Disable MLs 1(lane0), 2(lane0), 3(lane1) */
+ intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
+ l1t1 | CONTROL2_DISABLE_SINGLE_TX,
+ MB_WRITE_COMMITTED);
+ fallthrough;
+ case 2:
+ /* Disable MLs 1(lane0), 2(lane0) */
+ intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
+ l0t2 | CONTROL2_DISABLE_SINGLE_TX,
+ MB_WRITE_COMMITTED);
+ fallthrough;
+ case 3:
+ /* Disable MLs 1(lane0) */
+ intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
+ l0t1 | CONTROL2_DISABLE_SINGLE_TX,
+ MB_WRITE_COMMITTED);
+ break;
+ }
+ } else {
+ switch (lane_count) {
+ case 1:
+ if (dp_alt_mode) {
+ /* Disable MLs 1(lane0), 3(lane1), 4(lane1) */
+ intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
+ l0t1 | CONTROL2_DISABLE_SINGLE_TX,
+ MB_WRITE_COMMITTED);
+ } else {
+ /* Disable MLs 2(lane0), 3(lane1), 4(lane1) */
+ intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
+ l0t2 | CONTROL2_DISABLE_SINGLE_TX,
+ MB_WRITE_COMMITTED);
+ }
+ fallthrough;
+ case 2:
+ /* Disable MLs 3(lane1), 4(lane1) */
+ intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
+ l1t1 | CONTROL2_DISABLE_SINGLE_TX,
+ MB_WRITE_COMMITTED);
+ fallthrough;
+ case 3:
+ /* Disable MLs 4(lane1) */
+ intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
+ l1t2 | CONTROL2_DISABLE_SINGLE_TX,
+ MB_WRITE_COMMITTED);
+ break;
+ }
+ }
+
+ if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) {
+ intel_cx0_rmw(i915, port, INTEL_CX0_LANE1, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
+ C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+ }
+}
+
+static u32 intel_cx0_get_pclk_pll_request(u8 lane)
+{
+ if (lane == INTEL_CX0_LANE0)
+ return XELPDP_LANE0_PCLK_PLL_REQUEST;
+ else if (lane == INTEL_CX0_LANE1)
+ return XELPDP_LANE1_PCLK_PLL_REQUEST;
+ else
+ return XELPDP_LANE0_PCLK_PLL_REQUEST |
+ XELPDP_LANE1_PCLK_PLL_REQUEST;
+}
+
+static u32 intel_cx0_get_pclk_pll_ack(u8 lane)
+{
+ if (lane == INTEL_CX0_LANE0)
+ return XELPDP_LANE0_PCLK_PLL_ACK;
+ else if (lane == INTEL_CX0_LANE1)
+ return XELPDP_LANE1_PCLK_PLL_ACK;
+ else
+ return XELPDP_LANE0_PCLK_PLL_ACK |
+ XELPDP_LANE1_PCLK_PLL_ACK;
+}
+
+static void intel_c10pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
+ INTEL_CX0_LANE0;
+
+ /*
+ * 1. Program PORT_CLOCK_CTL REGISTER to configure
+ * clock muxes, gating and SSC
+ */
+ intel_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
+
+ /* 2. Bring PHY out of reset. */
+ intel_cx0_phy_lane_reset(i915, encoder->port, lane_reversal);
+
+ /*
+ * 3. Change Phy power state to Ready.
+ * TODO: For DP alt mode use only one lane.
+ */
+ intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES,
+ CX0_P2_STATE_READY);
+
+ /* 4. Program PHY internal PLL internal registers. */
+ intel_c10_pll_program(i915, crtc_state, encoder);
+
+ /*
+ * 5. Program the enabled and disabled owned PHY lane
+ * transmitters over message bus
+ */
+ intel_c10_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
+
+ /*
+ * 6. Follow the Display Voltage Frequency Switching - Sequence
+ * Before Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /*
+ * 7. Program DDI_CLK_VALFREQ to match intended DDI
+ * clock frequency.
+ */
+ intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
+ crtc_state->port_clock);
+ /*
+ * 8. Set PORT_CLOCK_CTL register PCLK PLL Request
+ * LN<Lane for maxPCLK> to "1" to enable PLL.
+ */
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
+ intel_cx0_get_pclk_pll_request(maxpclk_lane));
+
+ /* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
+ intel_cx0_get_pclk_pll_ack(maxpclk_lane),
+ XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
+ drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n",
+ phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US);
+
+ /*
+ * 10. Follow the Display Voltage Frequency Switching Sequence After
+ * Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+}
+
+void intel_cx0pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
+ intel_c10pll_enable(encoder, crtc_state);
+}
+
+static void intel_c10pll_disable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ /* 1. Change owned PHY lane power to Disable state. */
+ intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES,
+ CX0_P2PG_STATE_DISABLE);
+
+ /*
+ * 2. Follow the Display Voltage Frequency Switching Sequence Before
+ * Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /*
+ * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
+ * to "0" to disable PLL.
+ */
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
+ intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
+
+ /* 4. Program DDI_CLK_VALFREQ to 0. */
+ intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
+
+ /*
+ * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
+ */
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
+ intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
+ XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
+ drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n",
+ phy_name(phy), XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US);
+
+ /*
+ * 6. Follow the Display Voltage Frequency Switching Sequence After
+ * Frequency Change. We handle this step in bxt_set_cdclk().
+ */
+
+ /* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ XELPDP_DDI_CLOCK_SELECT_MASK |
+ XELPDP_FORWARD_CLOCK_UNGATE, 0);
+}
+
+void intel_cx0pll_disable(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
+ intel_c10pll_disable(encoder);
+}
+
+void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
+ struct intel_crtc_state *new_crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_c10mpllb_state mpllb_hw_state = { 0 };
+ struct intel_c10mpllb_state *mpllb_sw_state = &new_crtc_state->c10mpllb_state;
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ struct intel_encoder *encoder;
+ struct intel_dp *intel_dp;
+ enum phy phy;
+ int i;
+ bool use_ssc = false;
+
+ if (DISPLAY_VER(i915) < 14)
+ return;
+
+ if (!new_crtc_state->hw.active)
+ return;
+
+ encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
+ phy = intel_port_to_phy(i915, encoder->port);
+
+ if (intel_crtc_has_dp_encoder(new_crtc_state)) {
+ intel_dp = enc_to_intel_dp(encoder);
+ use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
+ DP_MAX_DOWNSPREAD_0_5);
+
+ if (!intel_panel_use_ssc(i915))
+ use_ssc = false;
+ }
+
+ if (!intel_is_c10phy(i915, phy))
+ return;
+
+ intel_c10mpllb_readout_hw_state(encoder, &mpllb_hw_state);
+
+ for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {
+ u8 expected;
+
+ if (!use_ssc && i > 3 && i < 9)
+ expected = 0;
+ else
+ expected = mpllb_sw_state->pll[i];
+
+ I915_STATE_WARN(mpllb_hw_state.pll[i] != expected,
+ "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)",
+ crtc->base.base.id, crtc->base.name,
+ i, expected, mpllb_hw_state.pll[i]);
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
new file mode 100644
index 000000000000..8cf340509097
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef __INTEL_CX0_PHY_H__
+#define __INTEL_CX0_PHY_H__
+
+#include <linux/types.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+
+#include "i915_drv.h"
+#include "intel_display_types.h"
+
+struct drm_i915_private;
+struct intel_encoder;
+struct intel_crtc_state;
+enum phy;
+
+#define INTEL_CX0_LANE0 0x1
+#define INTEL_CX0_LANE1 0x2
+#define INTEL_CX0_BOTH_LANES 0x3
+
+#define MB_WRITE_COMMITTED 1
+#define MB_WRITE_UNCOMMITTED 0
+
+bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
+void intel_cx0pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
+void intel_cx0pll_disable(struct intel_encoder *encoder);
+void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
+ struct intel_c10mpllb_state *pll_state);
+int intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state,
+ struct intel_encoder *encoder);
+void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv,
+ const struct intel_c10mpllb_state *hw_state);
+int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
+ const struct intel_c10mpllb_state *pll_state);
+void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
+ struct intel_crtc_state *new_crtc_state);
+
+#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index d1ee8a2fc9cf..15e249f46a64 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -128,4 +128,34 @@
#define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
#define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
-#endif /* __INTEL_CX0_PHY_REGS_H__ */
+/* C10 Vendor Registers */
+#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
+#define C10_PLL0_FRACEN REG_BIT8(4)
+#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
+#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
+#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
+#define C10_CMN0_DP_VAL 0x21
+#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
+#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
+#define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
+#define C10_TX0_VAL 0x10
+#define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1)
+#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2)
+#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1)
+#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
+#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
+
+#define CX0_P0_STATE_ACTIVE 0x0
+#define CX0_P2_STATE_READY 0x2
+#define CX0_P2PG_STATE_DISABLE 0x9
+#define CX0_P4PG_STATE_DISABLE 0xC
+#define CX0_P2_STATE_RESET 0x2
+
+/* PHY_C10_VDR_PLL0 */
+#define PLL_C10_MPLL_SSC_EN REG_BIT8(0)
+
+/* PIPE SPEC Defined Registers */
+#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
+#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
+
+#endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 73240cf78c8b..a433dea5b9a3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -39,6 +39,7 @@
#include "intel_combo_phy_regs.h"
#include "intel_connector.h"
#include "intel_crtc.h"
+#include "intel_cx0_phy.h"
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
@@ -3507,6 +3508,21 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
&crtc_state->dpll_hw_state);
}
+static void mtl_ddi_get_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
+
+ drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
+
+ intel_c10mpllb_readout_hw_state(encoder, &crtc_state->c10mpllb_state);
+ intel_c10mpllb_dump_hw_state(i915, &crtc_state->c10mpllb_state);
+ crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->c10mpllb_state);
+
+ intel_ddi_get_config(encoder, crtc_state);
+}
+
static void dg2_ddi_get_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
@@ -4413,7 +4429,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
- if (IS_DG2(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ encoder->enable_clock = intel_cx0pll_enable;
+ encoder->disable_clock = intel_cx0pll_disable;
+ encoder->get_config = mtl_ddi_get_config;
+ } else if (IS_DG2(dev_priv)) {
encoder->enable_clock = intel_mpllb_enable;
encoder->disable_clock = intel_mpllb_disable;
encoder->get_config = dg2_ddi_get_config;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index f86060195987..e23fecba446c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1614,7 +1614,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
return;
/* 2. Initialize all combo phys */
- intel_combo_phy_init(dev_priv);
+ if (DISPLAY_VER(dev_priv) < 14)
+ intel_combo_phy_init(dev_priv);
/*
* 3. Enable Power Well 1 (PG1).
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 1676df1dc066..a4c8cb75c0a0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -970,7 +970,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
bxt_verify_ddi_phy_power_wells(dev_priv);
- if (DISPLAY_VER(dev_priv) >= 11)
+ if (DISPLAY_VER(dev_priv) >= 11 && DISPLAY_VER(dev_priv) < 14)
/*
* DMC retains HW context only for port A, the other combo
* PHY's HW context for port B is lost after DC transitions,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ab146b5b68bd..db7c108e4d86 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -985,6 +985,11 @@ struct intel_link_m_n {
u32 link_n;
};
+struct intel_c10mpllb_state {
+ u32 clock; /* in KHz */
+ u8 pll[20];
+};
+
struct intel_crtc_state {
/*
* uapi (drm) state. This is the software state shown to userspace.
@@ -1128,6 +1133,7 @@ struct intel_crtc_state {
union {
struct intel_dpll_hw_state dpll_hw_state;
struct intel_mpllb_state mpllb_state;
+ struct intel_c10mpllb_state c10mpllb_state;
};
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 4e9c18be7e1f..da5aa050a5ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -8,6 +8,7 @@
#include "i915_reg.h"
#include "intel_crtc.h"
+#include "intel_cx0_phy.h"
#include "intel_de.h"
#include "intel_display.h"
#include "intel_display_types.h"
@@ -995,6 +996,17 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
+static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ struct intel_encoder *encoder =
+ intel_get_crtc_new_encoder(state, crtc_state);
+
+ return intel_cx0mpllb_calc_state(crtc_state, encoder);
+}
+
static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
{
return dpll->m < factor * dpll->n;
@@ -1423,6 +1435,10 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
return 0;
}
+static const struct intel_dpll_funcs mtl_dpll_funcs = {
+ .crtc_compute_clock = mtl_crtc_compute_clock,
+};
+
static const struct intel_dpll_funcs dg2_dpll_funcs = {
.crtc_compute_clock = dg2_crtc_compute_clock,
};
@@ -1517,7 +1533,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
- if (IS_DG2(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 14)
+ dev_priv->display.funcs.dpll = &mtl_dpll_funcs;
+ else if (IS_DG2(dev_priv))
dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 22fc908b7e5d..ed372d227aa7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4104,7 +4104,7 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->display.dpll.lock);
- if (IS_DG2(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv))
/* No shared DPLLs on DG2; port PLLs are part of the PHY */
dpll_mgr = NULL;
else if (IS_ALDERLAKE_P(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 842d70f0dfd2..ec504470c2f0 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -11,6 +11,7 @@
#include "intel_atomic.h"
#include "intel_crtc.h"
#include "intel_crtc_state_dump.h"
+#include "intel_cx0_phy.h"
#include "intel_display.h"
#include "intel_display_types.h"
#include "intel_fdi.h"
@@ -236,6 +237,7 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
intel_shared_dpll_state_verify(crtc, old_crtc_state, new_crtc_state);
intel_mpllb_state_verify(state, new_crtc_state);
+ intel_c10mpllb_state_verify(state, new_crtc_state);
}
void intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d22ffd7a32dc..94dd0d3a474b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2101,6 +2101,11 @@
#define TRANS_PUSH_EN REG_BIT(31)
#define TRANS_PUSH_SEND REG_BIT(30)
+/* DDI Buffer Control */
+#define _DDI_CLK_VALFREQ_A 0x64030
+#define _DDI_CLK_VALFREQ_B 0x64130
+#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
+
/*
* HSW+ eDP PSR registers
*
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index db26de6b57bc..f9d7c03e95d6 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -22,6 +22,19 @@
BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
((__n) < 0 || (__n) > 31))))
+/**
+ * REG_BIT8() - Prepare a u8 bit value
+ * @__n: 0-based bit number
+ *
+ * Local wrapper for BIT() to force u8, with compile time checks.
+ *
+ * @return: Value with bit @__n set.
+ */
+#define REG_BIT8(__n) \
+ ((u8)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 7))))
+
/**
* REG_GENMASK() - Prepare a continuous u32 bitmask
* @__high: 0-based high bit
@@ -52,6 +65,21 @@
__is_constexpr(__low) && \
((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
+/**
+ * REG_GENMASK8() - Prepare a continuous u8 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK() to force u8, with compile time checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK8(__high, __low) \
+ ((u8)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 7 || (__low) > (__high)))))
+
/*
* Local integer constant expression version of is_power_of_2().
*/
@@ -74,6 +102,23 @@
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
+/**
+ * REG_FIELD_PREP8() - Prepare a u8 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to put in the field
+ *
+ * Local copy of FIELD_PREP8() to generate an integer constant expression, force
+ * u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8().
+ *
+ * @return: @__val masked and shifted into the field defined by @__mask.
+ */
+#define REG_FIELD_PREP8(__mask, __val) \
+ ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
+
/**
* REG_FIELD_GET() - Extract a u32 bitfield value
* @__mask: shifted mask defining the field's length and position
@@ -155,6 +200,18 @@
*/
#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
+/**
+ * REG_FIELD_GET8() - Extract a u8 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to extract the bitfield value from
+ *
+ * Local wrapper for FIELD_GET() to force u8 and for consistency with
+ * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: Masked and shifted value of the field defined by @__mask in @__val.
+ */
+#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))
+
typedef struct {
u32 reg;
} i915_reg_t;
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 5/7] drm/i915/mtl: Add C10 phy programming for HDMI
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
` (3 preceding siblings ...)
2023-03-27 12:34 ` [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming Mika Kahola
@ 2023-03-27 12:34 ` Mika Kahola
2023-04-03 10:26 ` Imre Deak
2023-03-27 12:34 ` [Intel-gfx] [PATCH 6/7] drm/i915/mtl: Add vswing programming for C10 phys Mika Kahola
` (10 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Mika Kahola @ 2023-03-27 12:34 UTC (permalink / raw)
To: intel-gfx
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Like DG2, we still don't have a proper algorithm that can be used
for calculating PHY settings, but we do have tables of register
values for a handful of the more common link rates. Some support is
better than none, so let's go ahead and add/use these tables when we
can, and also add some logic to hdmi_port_clock_valid() to filter the
modelist to just the modes we can actually support with these link
rates.
Hopefully we'll have a proper / non-encumbered algorithm to calculate
these registers by the time we upstream and we'll be able to replace
this patch with something more general purpose.
Bspec: 64568
v2: Rebasing with Clint's HDMI C10 PLL tables (Mika)
v3: Add missing use_hdmi checks from Clint's HDMI implementation changes (Ankit)
Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 576 +++++++++++++++++-
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 13 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 5 +-
4 files changed, 579 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index ced8c8aa6c82..3aa8031f8373 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -485,6 +485,538 @@ static const struct intel_c10mpllb_state * const mtl_c10_edp_tables[] = {
NULL,
};
+/*
+ * HDMI link rates with 38.4 MHz reference clock.
+ */
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_25_2 = {
+ .clock = 25200,
+ .pll[0] = 0x4,
+ .pll[1] = 0,
+ .pll[2] = 0xB2,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xD,
+ .pll[16] = 0x6,
+ .pll[17] = 0x8F,
+ .pll[18] = 0x84,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_27_0 = {
+ .clock = 27000,
+ .pll[0] = 0x34,
+ .pll[1] = 0,
+ .pll[2] = 0xC0,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x80,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xD,
+ .pll[16] = 0x6,
+ .pll[17] = 0xCF,
+ .pll[18] = 0x84,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_74_25 = {
+ .clock = 74250,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xB,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_148_5 = {
+ .clock = 148500,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0xA,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_594 = {
+ .clock = 594000,
+ .pll[0] = 0xF4,
+ .pll[1] = 0,
+ .pll[2] = 0x7A,
+ .pll[3] = 0,
+ .pll[4] = 0,
+ .pll[5] = 0,
+ .pll[6] = 0,
+ .pll[7] = 0,
+ .pll[8] = 0x20,
+ .pll[9] = 0x1,
+ .pll[10] = 0,
+ .pll[11] = 0,
+ .pll[12] = 0x58,
+ .pll[13] = 0,
+ .pll[14] = 0,
+ .pll[15] = 0x8,
+ .pll[16] = 0x6,
+ .pll[17] = 0xF,
+ .pll[18] = 0x85,
+ .pll[19] = 0x23,
+};
+
+/* Precomputed C10 HDMI PLL tables */
+static const struct intel_c10mpllb_state mtl_c10_hdmi_25175 = {
+ .clock = 25175,
+ .pll[0]=0x34,
+ .pll[1]=0x00,
+ .pll[2]=0xB0,
+ .pll[3]=0x00,
+ .pll[4]=0x00,
+ .pll[5]=0x00,
+ .pll[6]=0x00,
+ .pll[7]=0x00,
+ .pll[8]=0x20,
+ .pll[9]=0xFF,
+ .pll[10]=0xFF,
+ .pll[11]=0x55,
+ .pll[12]=0xE5,
+ .pll[13]=0x55,
+ .pll[14]=0x55,
+ .pll[15]=0x0D,
+ .pll[16]=0x09,
+ .pll[17]=0x8F,
+ .pll[18]=0x84,
+ .pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_27027 = {
+ .clock = 27027,
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_28320 = {
+ .clock = 28320,
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xCC, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_30240 = {
+ .clock = 30240,
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xDC, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_31500 = {
+ .clock = 31500,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x62, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_36000 = {
+ .clock = 36000,
+ .pll[0]=0xC4, .pll[1]=0x00, .pll[2]=0x76, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_40000 = {
+ .clock = 40000,
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_49500 = {
+ .clock = 49500,
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_50000 = {
+ .clock = 50000,
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xB0, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_57284 = {
+ .clock = 57284,
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xCE, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_58000 = {
+ .clock = 58000,
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_65000 = {
+ .clock = 65000,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x66, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_71000 = {
+ .clock = 71000,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x72, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_74176 = {
+ .clock = 74176,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x44,.pll[12]=0x44,.pll[13]=0x44,.pll[14]=0x44,
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_75000 = {
+ .clock = 75000,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7C, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_78750 = {
+ .clock = 78750,
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x84, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x08,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_85500 = {
+ .clock = 85500,
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x92, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x10,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_88750 = {
+ .clock = 88750,
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0x98, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x72,.pll[13]=0xA9,.pll[14]=0xAA,
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_106500 = {
+ .clock = 106500,
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xBC, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xF0,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_108000 = {
+ .clock = 108000,
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x80,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_115500 = {
+ .clock = 115500,
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x50,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_119000 = {
+ .clock = 119000,
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD6, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_135000 = {
+ .clock = 135000,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x6C, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x50,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0A,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_138500 = {
+ .clock = 138500,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x70, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x22,.pll[13]=0xA9,.pll[14]=0xAA,
+ .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_147160 = {
+ .clock = 147160,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x78, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xA5,.pll[13]=0x55,.pll[14]=0x55,
+ .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_148352 = {
+ .clock = 148352,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x44,.pll[12]=0x44,.pll[13]=0x44,.pll[14]=0x44,
+ .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_154000 = {
+ .clock = 154000,
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x80, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x35,.pll[13]=0x55,.pll[14]=0x55,
+ .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_162000 = {
+ .clock = 162000,
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x88, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x60,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_167000 = {
+ .clock = 167000,
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x8C, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0xFA,.pll[13]=0xA9,.pll[14]=0xAA,
+ .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_197802 = {
+ .clock = 197802,
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x99,.pll[12]=0x05,.pll[13]=0x98,.pll[14]=0x99,
+ .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_198000 = {
+ .clock = 198000,
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_209800 = {
+ .clock = 209800,
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xBA, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x45,.pll[13]=0x55,.pll[14]=0x55,
+ .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_241500 = {
+ .clock = 241500,
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xDA, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xC8,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_262750 = {
+ .clock = 262750,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x68, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x6C,.pll[13]=0xA9,.pll[14]=0xAA,
+ .pll[15]=0x09,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_268500 = {
+ .clock = 268500,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x6A, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xEC,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x09,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_296703 = {
+ .clock = 296703,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x33,.pll[12]=0x44,.pll[13]=0x33,.pll[14]=0x33,
+ .pll[15]=0x09,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_297000 = {
+ .clock = 297000,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x58,.pll[13]=0x00,.pll[14]=0x00,
+ .pll[15]=0x09,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_319750 = {
+ .clock = 319750,
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x44,.pll[13]=0xA9,.pll[14]=0xAA,
+ .pll[15]=0x09,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_497750 = {
+ .clock = 497750,
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xE2, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x9F,.pll[13]=0x55,.pll[14]=0x55,
+ .pll[15]=0x09,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_592000 = {
+ .clock = 592000,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x15,.pll[13]=0x55,.pll[14]=0x55,
+ .pll[15]=0x08,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state mtl_c10_hdmi_593407 = {
+ .clock = 593407,
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
+ .pll[10]=0xFF,.pll[11]=0x3B,.pll[12]=0x44,.pll[13]=0xBA,.pll[14]=0xBB,
+ .pll[15]=0x08,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
+};
+
+static const struct intel_c10mpllb_state * const mtl_c10_hdmi_tables[] = {
+ &mtl_c10_hdmi_25175,
+ &mtl_c10_hdmi_25_2, /* Consolidated Table */
+ &mtl_c10_hdmi_27_0, /* Consolidated Table */
+ &mtl_c10_hdmi_27027,
+ &mtl_c10_hdmi_28320,
+ &mtl_c10_hdmi_30240,
+ &mtl_c10_hdmi_31500,
+ &mtl_c10_hdmi_36000,
+ &mtl_c10_hdmi_40000,
+ &mtl_c10_hdmi_49500,
+ &mtl_c10_hdmi_50000,
+ &mtl_c10_hdmi_57284,
+ &mtl_c10_hdmi_58000,
+ &mtl_c10_hdmi_65000,
+ &mtl_c10_hdmi_71000,
+ &mtl_c10_hdmi_74176,
+ &mtl_c10_hdmi_74_25, /* Consolidated Table */
+ &mtl_c10_hdmi_75000,
+ &mtl_c10_hdmi_78750,
+ &mtl_c10_hdmi_85500,
+ &mtl_c10_hdmi_88750,
+ &mtl_c10_hdmi_106500,
+ &mtl_c10_hdmi_108000,
+ &mtl_c10_hdmi_115500,
+ &mtl_c10_hdmi_119000,
+ &mtl_c10_hdmi_135000,
+ &mtl_c10_hdmi_138500,
+ &mtl_c10_hdmi_147160,
+ &mtl_c10_hdmi_148352,
+ &mtl_c10_hdmi_148_5, /* Consolidated Table */
+ &mtl_c10_hdmi_154000,
+ &mtl_c10_hdmi_162000,
+ &mtl_c10_hdmi_167000,
+ &mtl_c10_hdmi_197802,
+ &mtl_c10_hdmi_198000,
+ &mtl_c10_hdmi_209800,
+ &mtl_c10_hdmi_241500,
+ &mtl_c10_hdmi_262750,
+ &mtl_c10_hdmi_268500,
+ &mtl_c10_hdmi_296703,
+ &mtl_c10_hdmi_297000,
+ &mtl_c10_hdmi_319750,
+ &mtl_c10_hdmi_497750,
+ &mtl_c10_hdmi_592000,
+ &mtl_c10_hdmi_593407,
+ &mtl_c10_hdmi_594, /* Consolidated Table */
+ NULL,
+};
+
+int intel_c10_phy_check_hdmi_link_rate(int clock)
+{
+ const struct intel_c10mpllb_state * const *tables = mtl_c10_hdmi_tables;
+ int i;
+
+ for (i = 0; tables[i]; i++) {
+ if (clock == tables[i]->clock)
+ return MODE_OK;
+ }
+
+ return MODE_CLOCK_RANGE;
+}
+
static const struct intel_c10mpllb_state * const *
intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
@@ -494,9 +1026,10 @@ intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
return mtl_c10_edp_tables;
else
return mtl_c10_dp_tables;
+ } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+ return mtl_c10_hdmi_tables;
}
- /* TODO: Add HDMI Support */
MISSING_CASE(encoder->type);
return NULL;
}
@@ -504,9 +1037,20 @@ intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
static int intel_c10mpllb_calc_state(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_c10mpllb_state * const *tables;
+ enum phy phy = intel_port_to_phy(i915, encoder->port);
int i;
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+ if (intel_c10_phy_check_hdmi_link_rate(crtc_state->port_clock)
+ != MODE_OK) {
+ drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d on phy %c.\n",
+ crtc_state->port_clock, phy_name(phy));
+ return -EINVAL;
+ }
+ }
+
tables = intel_c10_mpllb_tables_get(crtc_state, encoder);
if (!tables)
return -EINVAL;
@@ -558,9 +1102,10 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0));
tx0 = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0));
- if (tx0 != C10_TX0_VAL || cmn != C10_CMN0_DP_VAL)
- drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
- tx0, cmn, phy_name(phy));
+ if (tx0 != C10_TX0_VAL || (cmn != C10_CMN0_DP_VAL &&
+ cmn != C10_CMN0_HDMI_VAL))
+ drm_dbg_kms(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
+ tx0, cmn, phy_name(phy));
}
static void intel_c10_pll_program(struct drm_i915_private *i915,
@@ -574,11 +1119,11 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
INTEL_CX0_LANE0;
u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
INTEL_CX0_LANE1;
-
int i;
struct intel_dp *intel_dp;
bool use_ssc = false;
- u8 cmn0 = 0;
+ bool use_hdmi = false;
+ u8 cmn0;
if (intel_crtc_has_dp_encoder(crtc_state)) {
intel_dp = enc_to_intel_dp(encoder);
@@ -589,6 +1134,9 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
use_ssc = false;
cmn0 = C10_CMN0_DP_VAL;
+ } else {
+ use_hdmi = true;
+ cmn0 = C10_CMN0_HDMI_VAL;
}
intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
@@ -604,7 +1152,7 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
/* If not using ssc pll[4] through pll[8] must be 0*/
intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_PLL(i),
- (!use_ssc && (i > 3 && i < 9)) ? 0 : pll_state->pll[i],
+ (!(use_ssc || use_hdmi) && (i > 3 && i < 9)) ? 0 : pll_state->pll[i],
(i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED);
intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
@@ -652,7 +1200,8 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
const struct intel_c10mpllb_state *pll_state)
{
unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
- unsigned int multiplier, tx_clk_div, refclk = 38400;
+ unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
+ int tmpclk = 0;
if (pll_state->pll[0] & C10_PLL0_FRACEN) {
frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
@@ -664,10 +1213,14 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
pll_state->pll[2]) / 2 + 16;
tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
+ hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
- return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
+ tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
10 << (tx_clk_div + 16));
+ tmpclk *= (hdmi_div ? 2 : 1);
+
+ return tmpclk;
}
static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
@@ -1080,6 +1633,7 @@ void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
enum phy phy;
int i;
bool use_ssc = false;
+ bool use_hdmi = false;
if (DISPLAY_VER(i915) < 14)
return;
@@ -1097,6 +1651,8 @@ void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
if (!intel_panel_use_ssc(i915))
use_ssc = false;
+ } else {
+ use_hdmi = true;
}
if (!intel_is_c10phy(i915, phy))
@@ -1107,7 +1663,7 @@ void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {
u8 expected;
- if (!use_ssc && i > 3 && i < 9)
+ if (!(use_ssc || use_hdmi) && i > 3 && i < 9)
expected = 0;
else
expected = mpllb_sw_state->pll[i];
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 8cf340509097..f8023f240727 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -39,5 +39,6 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
const struct intel_c10mpllb_state *pll_state);
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state);
+int intel_c10_phy_check_hdmi_link_rate(int clock);
#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 15e249f46a64..91e2f88f43f7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -133,8 +133,11 @@
#define C10_PLL0_FRACEN REG_BIT8(4)
#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
+#define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3)
+
#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
#define C10_CMN0_DP_VAL 0x21
+#define C10_CMN0_HDMI_VAL 0x1
#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
#define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
@@ -145,11 +148,11 @@
#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
-#define CX0_P0_STATE_ACTIVE 0x0
-#define CX0_P2_STATE_READY 0x2
-#define CX0_P2PG_STATE_DISABLE 0x9
-#define CX0_P4PG_STATE_DISABLE 0xC
-#define CX0_P2_STATE_RESET 0x2
+#define CX0_P0_STATE_ACTIVE 0x0
+#define CX0_P2_STATE_READY 0x2
+#define CX0_P2PG_STATE_DISABLE 0x9
+#define CX0_P4PG_STATE_DISABLE 0xC
+#define CX0_P2_STATE_RESET 0x2
/* PHY_C10_VDR_PLL0 */
#define PLL_C10_MPLL_SSC_EN REG_BIT8(0)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c7e9e1fbed37..baa9ef7568af 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -46,6 +46,7 @@
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"
+#include "intel_cx0_phy.h"
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_types.h"
@@ -1865,7 +1866,9 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
* FIXME: We will hopefully get an algorithmic way of programming
* the MPLLB for HDMI in the future.
*/
- if (IS_DG2(dev_priv))
+ if (IS_METEORLAKE(dev_priv))
+ return intel_c10_phy_check_hdmi_link_rate(clock);
+ else if (IS_DG2(dev_priv))
return intel_snps_phy_check_hdmi_link_rate(clock);
return MODE_OK;
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 6/7] drm/i915/mtl: Add vswing programming for C10 phys
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
` (4 preceding siblings ...)
2023-03-27 12:34 ` [Intel-gfx] [PATCH 5/7] drm/i915/mtl: Add C10 phy programming for HDMI Mika Kahola
@ 2023-03-27 12:34 ` Mika Kahola
2023-04-03 11:18 ` Imre Deak
2023-03-27 12:34 ` [Intel-gfx] [PATCH 7/7] drm/i915/mtl: Add support for PM DEMAND Mika Kahola
` (9 subsequent siblings)
15 siblings, 1 reply; 37+ messages in thread
From: Mika Kahola @ 2023-03-27 12:34 UTC (permalink / raw)
To: intel-gfx
From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
Program the levels directly to the fields in the VDR Registers.
Bspec: 65449
v2: From table "C10: Tx EQ settings for DP 1.4x" it shows level 1
and preemphasis 1 instead of two times of level 1 preemphasis 0.
Fix this in the driver code as well.
v3: VSwing update (Clint)
Cc: Imre Deak <imre.deak@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 140 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 14 ++
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
.../drm/i915/display/intel_ddi_buf_trans.c | 31 +++-
.../drm/i915/display/intel_ddi_buf_trans.h | 6 +
.../i915/display/intel_display_power_map.c | 1 +
7 files changed, 187 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 3aa8031f8373..fb54f56ac5ef 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -6,11 +6,15 @@
#include "i915_reg.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_phy_regs.h"
+#include "intel_ddi.h"
+#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_panel.h"
+#include "intel_psr.h"
#include "intel_tc.h"
+#include "intel_uncore.h"
bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
{
@@ -20,6 +24,15 @@ bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
return false;
}
+static void
+assert_dc_off(struct drm_i915_private *i915)
+{
+ bool enabled;
+
+ enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF);
+ drm_WARN_ON(&i915->drm, !enabled);
+}
+
static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, int lane)
{
enum phy phy = intel_port_to_phy(i915, port);
@@ -112,6 +125,8 @@ static u8 intel_cx0_read(struct drm_i915_private *i915, enum port port,
int i, status = 0;
u32 val;
+ assert_dc_off(i915);
+
for (i = 0; i < 3; i++) {
status = __intel_cx0_read(i915, port, lane, addr, &val);
@@ -194,6 +209,8 @@ static void __intel_cx0_write(struct drm_i915_private *i915, enum port port,
enum phy phy = intel_port_to_phy(i915, port);
int i, status;
+ assert_dc_off(i915);
+
for (i = 0; i < 3; i++) {
status = __intel_cx0_write_once(i915, port, lane, addr, data, committed);
@@ -241,6 +258,89 @@ static void intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
}
}
+/*
+ * Prepare HW for CX0 phy transactions.
+ *
+ * It is required that PSR and DC5/6 are disabled before any CX0 message
+ * bus transaction is executed.
+ */
+static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_pause(intel_dp);
+ return intel_display_power_get(i915, POWER_DOMAIN_DC_OFF);
+}
+
+static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_resume(intel_dp);
+ intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, wakeref);
+}
+
+void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
+ INTEL_CX0_LANE0;
+ u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
+ INTEL_CX0_LANE1;
+ const struct intel_ddi_buf_trans *trans;
+ intel_wakeref_t wakeref;
+ int n_entries, ln;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
+
+ trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
+ if (drm_WARN_ON_ONCE(&i915->drm, !trans))
+ return;
+
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
+ 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+
+ for (ln = 0; ln < 4; ln++) {
+ int level = intel_ddi_level(encoder, crtc_state, ln);
+ int lane, tx;
+
+ lane = ln / 2;
+ tx = ln % 2 + 1;
+
+ intel_cx0_rmw(i915, encoder->port, lane + 1, PHY_CX0_VDR_OVRD_CONTROL(lane, tx, 0),
+ C10_PHY_OVRD_LEVEL_MASK,
+ C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),
+ MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, lane + 1, PHY_CX0_VDR_OVRD_CONTROL(lane, tx, 1),
+ C10_PHY_OVRD_LEVEL_MASK,
+ C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing),
+ MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, encoder->port, lane + 1, PHY_CX0_VDR_OVRD_CONTROL(lane, tx, 2),
+ C10_PHY_OVRD_LEVEL_MASK,
+ C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor),
+ MB_WRITE_COMMITTED);
+ }
+
+ /* Write Override enables in 0xD71 */
+ intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_OVRD,
+ PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
+ PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
+ MB_WRITE_COMMITTED);
+ intel_cx0_write(i915, encoder->port, follower_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
+ MB_WRITE_COMMITTED);
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_MSGBUS_ACCESS |
+ C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
+}
+
/*
* Basic DP link rates with 38.4 MHz reference clock.
* Note: The tables below are with SSC. In non-ssc
@@ -1085,9 +1185,12 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
INTEL_CX0_LANE0;
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
int i;
u8 cmn, tx0;
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
+
/*
* According to C10 VDR Register programming Sequence we need
* to do this to read PHY internal registers from MsgBus.
@@ -1106,6 +1209,8 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
cmn != C10_CMN0_HDMI_VAL))
drm_dbg_kms(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
tx0, cmn, phy_name(phy));
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
}
static void intel_c10_pll_program(struct drm_i915_private *i915,
@@ -1243,8 +1348,11 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
if (intel_crtc_has_dp_encoder(crtc_state)) {
intel_dp = enc_to_intel_dp(encoder);
- ssc_enabled = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
- DP_MAX_DOWNSPREAD_0_5;
+ ssc_enabled = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
+ DP_MAX_DOWNSPREAD_0_5);
+
+ if (intel_dp_is_edp(intel_dp) && !intel_panel_use_ssc(i915))
+ ssc_enabled = false;
if (!intel_panel_use_ssc(i915))
ssc_enabled = false;
@@ -1252,11 +1360,11 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
/* TODO: DP2.0 10G and 20G rates enable MPLLA*/
val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
}
+
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
- XELPDP_LANE1_PHY_CLOCK_SELECT |
- XELPDP_FORWARD_CLOCK_UNGATE |
+ XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
XELPDP_DDI_CLOCK_SELECT_MASK |
- XELPDP_SSC_ENABLE_PLLB, val);
+ XELPDP_SSC_ENABLE_PLLA | XELPDP_SSC_ENABLE_PLLB, val);
}
static u32 intel_cx0_get_powerdown_update(u8 lane)
@@ -1396,9 +1504,12 @@ static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
enum port port = encoder->port;
- intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
- C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MSGBUS_ACCESS,
- MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, INTEL_CX0_LANE1, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
+ C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+ intel_cx0_rmw(i915, port, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),
+ C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
@@ -1561,9 +1672,14 @@ void intel_cx0pll_enable(struct intel_encoder *encoder,
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
intel_c10pll_enable(encoder, crtc_state);
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
}
static void intel_c10pll_disable(struct intel_encoder *encoder)
@@ -1608,7 +1724,8 @@ static void intel_c10pll_disable(struct intel_encoder *encoder)
/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
- XELPDP_DDI_CLOCK_SELECT_MASK |
+ XELPDP_DDI_CLOCK_SELECT_MASK, 0);
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
XELPDP_FORWARD_CLOCK_UNGATE, 0);
}
@@ -1616,9 +1733,14 @@ void intel_cx0pll_disable(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
+ intel_wakeref_t wakeref;
+
+ wakeref = intel_cx0_phy_transaction_begin(encoder);
drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
intel_c10pll_disable(encoder);
+
+ intel_cx0_phy_transaction_end(encoder, wakeref);
}
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index f8023f240727..952c7deeffaa 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -40,5 +40,7 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
struct intel_crtc_state *new_crtc_state);
int intel_c10_phy_check_hdmi_link_rate(int clock);
+void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#endif /* __INTEL_CX0_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 91e2f88f43f7..7a578a30ee45 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -154,6 +154,14 @@
#define CX0_P4PG_STATE_DISABLE 0xC
#define CX0_P2_STATE_RESET 0x2
+#define PHY_C10_VDR_OVRD 0xD71
+#define PHY_C10_VDR_OVRD_TX1 REG_BIT8(0)
+#define PHY_C10_VDR_OVRD_TX2 REG_BIT8(2)
+#define PHY_C10_VDR_PRE_OVRD_TX1 0xD80
+#define C10_PHY_OVRD_LEVEL_MASK REG_GENMASK8(5, 0)
+#define C10_PHY_OVRD_LEVEL(val) REG_FIELD_PREP8(C10_PHY_OVRD_LEVEL_MASK, val)
+#define PHY_CX0_VDR_OVRD_CONTROL(lane, tx, control) (PHY_C10_VDR_PRE_OVRD_TX1 + ((lane) ^ ((tx) - 1)) * 0x10 + (control))
+
/* PHY_C10_VDR_PLL0 */
#define PLL_C10_MPLL_SSC_EN REG_BIT8(0)
@@ -161,4 +169,10 @@
#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
+/* C10 Phy VSWING Masks */
+#define C10_PHY_VSWING_LEVEL_MASK REG_GENMASK8(2, 0)
+#define C10_PHY_VSWING_LEVEL(val) REG_FIELD_PREP8(C10_PHY_VSWING_LEVEL_MASK, val)
+#define C10_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(1, 0)
+#define C10_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C10_PHY_VSWING_PREEMPH_MASK, val)
+
#endif /* __INTEL_CX0_REG_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a433dea5b9a3..e8269fcc595e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4493,7 +4493,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->get_config = hsw_ddi_get_config;
}
- if (IS_DG2(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 14) {
+ encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
+ } else if (IS_DG2(dev_priv)) {
encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
} else if (DISPLAY_VER(dev_priv) >= 12) {
if (intel_phy_is_combo(dev_priv, phy))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 006a2e979000..cd4becbae098 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -1035,6 +1035,25 @@ static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
.num_entries = ARRAY_SIZE(_dg2_snps_trans_uhbr),
};
+static const union intel_ddi_buf_trans_entry _mtl_c10_trans_dp14[] = {
+ { .snps = { 26, 0, 0 } }, /* preset 0 */
+ { .snps = { 33, 0, 6 } }, /* preset 1 */
+ { .snps = { 38, 0, 11 } }, /* preset 2 */
+ { .snps = { 43, 0, 19 } }, /* preset 3 */
+ { .snps = { 39, 0, 0 } }, /* preset 4 */
+ { .snps = { 45, 0, 7 } }, /* preset 5 */
+ { .snps = { 46, 0, 13 } }, /* preset 6 */
+ { .snps = { 46, 0, 0 } }, /* preset 7 */
+ { .snps = { 55, 0, 7 } }, /* preset 8 */
+ { .snps = { 62, 0, 0 } }, /* preset 9 */
+};
+
+static const struct intel_ddi_buf_trans mtl_cx0c10_trans = {
+ .entries = _mtl_c10_trans_dp14,
+ .num_entries = ARRAY_SIZE(_mtl_c10_trans_dp14),
+ .hdmi_default_entry = ARRAY_SIZE(_mtl_c10_trans_dp14) - 1,
+};
+
bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
{
return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
@@ -1606,12 +1625,22 @@ dg2_get_snps_buf_trans(struct intel_encoder *encoder,
return intel_get_buf_trans(&dg2_snps_trans, n_entries);
}
+static const struct intel_ddi_buf_trans *
+mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ int *n_entries)
+{
+ return intel_get_buf_trans(&mtl_cx0c10_trans, n_entries);
+}
+
void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_port_to_phy(i915, encoder->port);
- if (IS_DG2(i915)) {
+ if (DISPLAY_VER(i915) >= 14) {
+ encoder->get_buf_trans = mtl_get_cx0_buf_trans;
+ } else if (IS_DG2(i915)) {
encoder->get_buf_trans = dg2_get_snps_buf_trans;
} else if (IS_ALDERLAKE_P(i915)) {
if (intel_phy_is_combo(i915, phy))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index 2133984a572b..e4a857b9829d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -51,6 +51,11 @@ struct dg2_snps_phy_buf_trans {
u8 post_cursor;
};
+struct direct_phy_buf_trans {
+ u8 level;
+ u8 preemph;
+};
+
union intel_ddi_buf_trans_entry {
struct hsw_ddi_buf_trans hsw;
struct bxt_ddi_buf_trans bxt;
@@ -58,6 +63,7 @@ union intel_ddi_buf_trans_entry {
struct icl_mg_phy_ddi_buf_trans mg;
struct tgl_dkl_phy_ddi_buf_trans dkl;
struct dg2_snps_phy_buf_trans snps;
+ struct direct_phy_buf_trans direct;
};
struct intel_ddi_buf_trans {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 6645eb1911d8..5ec2b9a109ae 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1427,6 +1427,7 @@ I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
XELPDP_PW_2_POWER_DOMAINS,
POWER_DOMAIN_AUDIO_MMIO,
POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_AUX_A,
POWER_DOMAIN_AUX_B,
POWER_DOMAIN_DC_OFF,
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH 7/7] drm/i915/mtl: Add support for PM DEMAND
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
` (5 preceding siblings ...)
2023-03-27 12:34 ` [Intel-gfx] [PATCH 6/7] drm/i915/mtl: Add vswing programming for C10 phys Mika Kahola
@ 2023-03-27 12:34 ` Mika Kahola
2023-03-27 19:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add Support for C10 chips Patchwork
` (8 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Mika Kahola @ 2023-03-27 12:34 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Matt Roper
Display14 introduces a new way to instruct the PUnit with
power and bandwidth requirements of DE. Add the functionality
to program the registers and handle waits using interrupts.
The current wait time for timeouts is programmed for 10 msecs to
factor in the worst case scenarios. Changes made to use REG_BIT
for a register that we touched(GEN8_DE_MISC_IER _MMIO).
v2:
- Removed repeated definition of dbuf, which has been moved to struct
intel_display. (Gustavo)
- s/dev_priv->dbuf/dev_priv->display.dbuf/ (Gustavo)
Bspec: 66451, 64636, 64602, 64603
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.h | 2 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +
.../drm/i915/display/intel_display_power.c | 8 +
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/i915_irq.c | 22 +-
drivers/gpu/drm/i915/i915_reg.h | 33 +-
drivers/gpu/drm/i915/intel_pm.c | 286 ++++++++++++++++++
drivers/gpu/drm/i915/intel_pm.h | 35 +++
9 files changed, 405 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 202321ffbe2a..87c20bf52123 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -746,8 +746,8 @@ static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv
return num_active_planes;
}
-static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
- const struct intel_bw_state *bw_state)
+unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
+ const struct intel_bw_state *bw_state)
{
unsigned int data_rate = 0;
enum pipe pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index f20292143745..17fc0b61db04 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -62,6 +62,8 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
+unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
+ const struct intel_bw_state *bw_state);
int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
u32 points_mask);
int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9fe6e33a66d6..3a9d71c80d5c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -959,6 +959,9 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
num_encoders++;
}
+ if (!encoder)
+ return NULL;
+
drm_WARN(encoder->base.dev, num_encoders != 1,
"%d encoders for pipe %c\n",
num_encoders, pipe_name(master_crtc->pipe));
@@ -6767,6 +6770,10 @@ int intel_atomic_check(struct drm_device *dev,
ret = intel_modeset_calc_cdclk(state);
if (ret)
return ret;
+
+ ret = intel_pmdemand_atomic_check(state);
+ if (ret)
+ goto fail;
}
ret = intel_atomic_check_crtcs(state);
@@ -7405,6 +7412,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
intel_sagv_pre_plane_update(state);
+ intel_pmdemand_pre_plane_update(state);
/* Complete the events for pipes that have now been disabled */
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
@@ -7517,6 +7525,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_verify_planes(state);
intel_sagv_post_plane_update(state);
+ intel_pmdemand_post_plane_update(state);
drm_atomic_helper_commit_hw_done(&state->base);
@@ -8248,6 +8257,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
intel_color_init_hooks(dev_priv);
intel_init_cdclk_hooks(dev_priv);
intel_audio_hooks_init(dev_priv);
+ intel_init_pmdemand(dev_priv);
intel_dpll_init_clock_hook(dev_priv);
@@ -8474,6 +8484,10 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
if (ret)
goto cleanup_vga_client_pw_domain_dmc;
+ ret = intel_pmdemand_init(i915);
+ if (ret)
+ goto cleanup_vga_client_pw_domain_dmc;
+
init_llist_head(&i915->display.atomic_helper.free_list);
INIT_WORK(&i915->display.atomic_helper.free_work,
intel_atomic_helper_free_state_worker);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e23fecba446c..77927d66cd35 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -19,6 +19,7 @@
#include "intel_mchbar_regs.h"
#include "intel_pch_refclk.h"
#include "intel_pcode.h"
+#include "intel_pm.h"
#include "intel_snps_phy.h"
#include "skl_watermark.h"
#include "vlv_sideband.h"
@@ -1082,6 +1083,10 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
dev_priv->display.dbuf.enabled_slices =
intel_enabled_dbuf_slices_mask(dev_priv);
+ if (DISPLAY_VER(dev_priv) >= 14)
+ intel_program_dbuf_pmdemand(dev_priv, BIT(DBUF_S1) |
+ dev_priv->display.dbuf.enabled_slices);
+
/*
* Just power up at least 1 slice, we will
* figure out later which slices we have and what we need.
@@ -1093,6 +1098,9 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
{
gen9_dbuf_slices_update(dev_priv, 0);
+
+ if (DISPLAY_VER(dev_priv) >= 14)
+ intel_program_dbuf_pmdemand(dev_priv, 0);
}
static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6254aa977398..df3b6742d980 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -250,6 +250,12 @@ struct drm_i915_private {
unsigned int hpll_freq;
unsigned int czclk_freq;
+ struct {
+ wait_queue_head_t waitqueue;
+ struct mutex lock;
+ struct intel_global_obj obj;
+ } pmdemand;
+
/**
* wq - Driver workqueue for GEM.
*
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 31271c30a8cf..4de7edc6c751 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1912,6 +1912,11 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
}
+static void intel_pmdemand_irq_handler(struct drm_i915_private *dev_priv)
+{
+ wake_up_all(&dev_priv->pmdemand.waitqueue);
+}
+
static void
gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
{
@@ -1948,6 +1953,18 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
}
}
+ if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR) {
+ drm_dbg(&dev_priv->drm,
+ "Error waiting for Punit PM Demand Response\n");
+ intel_pmdemand_irq_handler(dev_priv);
+ found = true;
+ }
+
+ if (iir & XELPDP_PMDEMAND_RSP) {
+ intel_pmdemand_irq_handler(dev_priv);
+ found = true;
+ }
+
if (!found)
drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
}
@@ -3314,7 +3331,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
de_port_masked |= BXT_DE_PORT_GMBUS;
- if (DISPLAY_VER(dev_priv) >= 11) {
+ if (DISPLAY_VER(dev_priv) >= 14)
+ de_misc_masked |= XELPDP_PMDEMAND_RSPTOUT_ERR |
+ XELPDP_PMDEMAND_RSP;
+ else if (DISPLAY_VER(dev_priv) >= 11) {
enum port port;
if (intel_bios_is_dsi_present(dev_priv, &port))
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 94dd0d3a474b..370b2bcb6fbf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5398,8 +5398,10 @@
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
#define GEN8_DE_MISC_IIR _MMIO(0x44468)
#define GEN8_DE_MISC_IER _MMIO(0x4446c)
-#define GEN8_DE_MISC_GSE (1 << 27)
-#define GEN8_DE_EDP_PSR (1 << 19)
+#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
+#define GEN8_DE_MISC_GSE REG_BIT(27)
+#define GEN8_DE_EDP_PSR REG_BIT(19)
+#define XELPDP_PMDEMAND_RSP REG_BIT(3)
#define GEN8_PCU_ISR _MMIO(0x444e0)
#define GEN8_PCU_IMR _MMIO(0x444e4)
@@ -5462,6 +5464,33 @@
#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
+#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
+#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
+#define XELPDP_PMDEMAND_QCLK_GV_BW(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_BW_MASK, x)
+#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
+#define XELPDP_PMDEMAND_VOLTAGE_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK, x)
+#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
+#define XELPDP_PMDEMAND_QCLK_GV_INDEX(x) REG_FIELD_PREP(XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK, x)
+#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
+#define XELPDP_PMDEMAND_PIPES(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PIPES_MASK, x)
+#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
+#define XELPDP_PMDEMAND_DBUFS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DBUFS_MASK, x)
+#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
+#define XELPDP_PMDEMAND_PHYS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PHYS_MASK, x)
+
+#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
+#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20)
+#define XELPDP_PMDEMAND_CDCLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, x)
+#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8)
+#define XELPDP_PMDEMAND_DDICLK_FREQ(x) REG_FIELD_PREP(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, x)
+#define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4)
+#define XELPDP_PMDEMAND_SCALERS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_SCALERS_MASK, x)
+#define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
+#define XELPDP_PMDEMAND_PLLS(x) REG_FIELD_PREP(XELPDP_PMDEMAND_PLLS_MASK, x)
+
+#define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
+#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
+
#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
/* Required on all Ironlake and Sandybridge according to the B-Spec. */
#define ILK_ELPIN_409_SELECT (1 << 25)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c45af0d981fd..32f562c01865 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -25,6 +25,11 @@
*
*/
+#include <linux/bitops.h>
+
+#include "display/intel_bw.h"
+#include "display/intel_cdclk.h"
+#include "display/intel_cx0_phy.h"
#include "display/intel_de.h"
#include "display/intel_display.h"
#include "display/intel_display_trace.h"
@@ -124,6 +129,287 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
PWM1_GATING_DIS | PWM2_GATING_DIS);
}
+static struct intel_global_state *intel_pmdemand_duplicate_state(struct intel_global_obj *obj)
+{
+ struct intel_pmdemand_state *pmdmnd_state;
+
+ pmdmnd_state = kmemdup(obj->state, sizeof(*pmdmnd_state), GFP_KERNEL);
+ if (!pmdmnd_state)
+ return NULL;
+
+ return &pmdmnd_state->base;
+}
+
+static void intel_pmdemand_destroy_state(struct intel_global_obj *obj,
+ struct intel_global_state *state)
+{
+ kfree(state);
+}
+
+static const struct intel_global_state_funcs intel_pmdemand_funcs = {
+ .atomic_duplicate_state = intel_pmdemand_duplicate_state,
+ .atomic_destroy_state = intel_pmdemand_destroy_state,
+};
+
+struct intel_pmdemand_state *
+intel_atomic_get_pmdemand_state(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_global_state *pmdemand_state;
+
+ pmdemand_state = intel_atomic_get_global_obj_state(state, &dev_priv->pmdemand.obj);
+ if (IS_ERR(pmdemand_state))
+ return ERR_CAST(pmdemand_state);
+
+ return to_intel_pmdemand_state(pmdemand_state);
+}
+
+int intel_pmdemand_init(struct drm_i915_private *dev_priv)
+{
+ struct intel_pmdemand_state *pmdemand_state;
+
+ pmdemand_state = kzalloc(sizeof(*pmdemand_state), GFP_KERNEL);
+ if (!pmdemand_state)
+ return -ENOMEM;
+
+ intel_atomic_global_obj_init(dev_priv, &dev_priv->pmdemand.obj,
+ &pmdemand_state->base, &intel_pmdemand_funcs);
+
+ return 0;
+}
+
+void intel_init_pmdemand(struct drm_i915_private *dev_priv)
+{
+ mutex_init(&dev_priv->pmdemand.lock);
+ init_waitqueue_head(&dev_priv->pmdemand.waitqueue);
+}
+
+int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ struct intel_pmdemand_state *new_pmdemand_state = NULL;
+ struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+ struct intel_crtc *crtc;
+ struct intel_encoder *encoder;
+ struct intel_bw_state *new_bw_state;
+ const struct intel_dbuf_state *new_dbuf_state;
+ const struct intel_cdclk_state *new_cdclk_state;
+ int port_clock = 0;
+ unsigned int data_rate;
+ enum phy phy;
+ int i, ret;
+
+ if (DISPLAY_VER(dev_priv) < 14)
+ return 0;
+
+ new_pmdemand_state = intel_atomic_get_pmdemand_state(state);
+ if (IS_ERR(new_pmdemand_state))
+ return PTR_ERR(new_pmdemand_state);
+
+ ret = intel_atomic_lock_global_state(&new_pmdemand_state->base);
+ if (ret)
+ return ret;
+
+ /* Punit figures out the voltage index based on bandwidth*/
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
+
+ /* firmware will calculate the qclck_gc_index, requirement is set to 0 */
+ new_pmdemand_state->qclk_gv_index = 0;
+
+ data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ /* To MBs then to multiples of 100MBs */
+ data_rate = DIV_ROUND_UP(data_rate, 1000);
+ data_rate = DIV_ROUND_UP(data_rate, 100);
+ new_pmdemand_state->qclk_gv_bw = data_rate;
+
+ new_dbuf_state = intel_atomic_get_dbuf_state(state);
+ if (IS_ERR(new_dbuf_state))
+ return PTR_ERR(new_dbuf_state);
+
+ i = hweight8(new_dbuf_state->active_pipes);
+ new_pmdemand_state->active_pipes = min(i, 3);
+
+ new_cdclk_state = intel_atomic_get_cdclk_state(state);
+ if (IS_ERR(new_cdclk_state))
+ return PTR_ERR(new_cdclk_state);
+
+ new_pmdemand_state->voltage_index = new_cdclk_state->logical.voltage_level;
+ /* KHz to MHz */
+ new_pmdemand_state->cdclk_freq_mhz = DIV_ROUND_UP(new_cdclk_state->logical.cdclk, 1000);
+
+ new_pmdemand_state->active_phys_plls_mask = 0;
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+ if (!new_crtc_state->hw.active)
+ continue;
+
+ encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
+ if (!encoder)
+ continue;
+
+ phy = intel_port_to_phy(dev_priv, encoder->port);
+
+ if (intel_is_c10phy(dev_priv, phy))
+ new_pmdemand_state->active_phys_plls_mask |= BIT(phy);
+
+ port_clock = max(port_clock, new_crtc_state->port_clock);
+ }
+
+ /* To MHz */
+ new_pmdemand_state->ddiclk_freq_mhz = DIV_ROUND_UP(port_clock, 1000);
+
+ /*
+ * Setting scalers to max as it can not be calculated during flips and
+ * fastsets without taking global states locks.
+ */
+ new_pmdemand_state->scalers = 7;
+
+ return 0;
+}
+
+static bool intel_pmdemand_check_prev_transaction(struct drm_i915_private *dev_priv)
+{
+ return !((intel_de_read(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) & XELPDP_PMDEMAND_REQ_ENABLE) ||
+ (intel_de_read(dev_priv, GEN12_DCPR_STATUS_1) & XELPDP_PMDEMAND_INFLIGHT_STATUS));
+}
+
+static bool intel_pmdemand_req_complete(struct drm_i915_private *dev_priv)
+{
+ return !(intel_de_read(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1)) & XELPDP_PMDEMAND_REQ_ENABLE);
+}
+
+static int intel_pmdemand_wait(struct drm_i915_private *dev_priv)
+{
+ DEFINE_WAIT(wait);
+ int ret;
+ const unsigned int timeout_ms = 10;
+
+ add_wait_queue(&dev_priv->pmdemand.waitqueue, &wait);
+
+ ret = wait_event_timeout(dev_priv->pmdemand.waitqueue,
+ intel_pmdemand_req_complete(dev_priv),
+ msecs_to_jiffies_timeout(timeout_ms));
+ if (ret < 0)
+ drm_err(&dev_priv->drm,
+ "timed out waiting for Punit PM Demand Response\n");
+
+ remove_wait_queue(&dev_priv->pmdemand.waitqueue, &wait);
+
+ return ret;
+}
+
+/* Required to be programmed during Display Init Sequences. */
+void intel_program_dbuf_pmdemand(struct drm_i915_private *dev_priv,
+ u8 dbuf_slices)
+{
+ mutex_lock(&dev_priv->pmdemand.lock);
+ if (drm_WARN_ON(&dev_priv->drm,
+ !intel_pmdemand_check_prev_transaction(dev_priv)))
+ goto unlock;
+
+ intel_de_rmw(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(0),
+ XELPDP_PMDEMAND_DBUFS_MASK,
+ XELPDP_PMDEMAND_DBUFS(hweight32(dbuf_slices)));
+ intel_de_rmw(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0,
+ XELPDP_PMDEMAND_REQ_ENABLE);
+
+ intel_pmdemand_wait(dev_priv);
+unlock:
+ mutex_unlock(&dev_priv->pmdemand.lock);
+}
+
+static void intel_program_pmdemand(struct drm_i915_private *dev_priv,
+ const struct intel_pmdemand_state *new,
+ const struct intel_pmdemand_state *old)
+{
+ u32 val, tmp;
+
+#define UPDATE_PMDEMAND_VAL(val, F, f) do { \
+ val &= (~(XELPDP_PMDEMAND_##F##_MASK)); \
+ val |= (XELPDP_PMDEMAND_##F((u32)(old ? max(old->f, new->f) : new->f))); \
+} while (0)
+
+ mutex_lock(&dev_priv->pmdemand.lock);
+ if (drm_WARN_ON(&dev_priv->drm,
+ !intel_pmdemand_check_prev_transaction(dev_priv)))
+ goto unlock;
+
+ /*
+ * TODO: Update programming PM Demand for
+ * PHYS, PLLS, DDI_CLKFREQ, SCALARS
+ */
+ val = intel_de_read(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(0));
+ UPDATE_PMDEMAND_VAL(val, QCLK_GV_INDEX, qclk_gv_index);
+ UPDATE_PMDEMAND_VAL(val, QCLK_GV_BW, qclk_gv_bw);
+ UPDATE_PMDEMAND_VAL(val, VOLTAGE_INDEX, voltage_index);
+ UPDATE_PMDEMAND_VAL(val, PIPES, active_pipes);
+ UPDATE_PMDEMAND_VAL(val, DBUFS, dbufs);
+ tmp = hweight32(new->active_phys_plls_mask);
+ if (old)
+ tmp = max(tmp, hweight32(old->active_phys_plls_mask));
+ val |= XELPDP_PMDEMAND_PHYS(tmp);
+
+ intel_de_write(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(0), val);
+
+ val = intel_de_read(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1));
+ UPDATE_PMDEMAND_VAL(val, CDCLK_FREQ, cdclk_freq_mhz);
+ UPDATE_PMDEMAND_VAL(val, DDICLK_FREQ, ddiclk_freq_mhz);
+ UPDATE_PMDEMAND_VAL(val, SCALERS, scalers);
+ /*
+ * Active_PLLs starts with 1 because of CDCLK PLL.
+ * TODO: Missing to account genlock filter when it gets used.
+ */
+ val |= XELPDP_PMDEMAND_PLLS(tmp + 1);
+
+ intel_de_write(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1), val);
+
+#undef UPDATE_PM_DEMAND_VAL
+
+ intel_de_rmw(dev_priv, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0, XELPDP_PMDEMAND_REQ_ENABLE);
+
+ intel_pmdemand_wait(dev_priv);
+unlock:
+ mutex_unlock(&dev_priv->pmdemand.lock);
+}
+
+void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_pmdemand_state *new_pmdmnd_state =
+ intel_atomic_get_new_pmdemand_state(state);
+ const struct intel_pmdemand_state *old_pmdmnd_state =
+ intel_atomic_get_old_pmdemand_state(state);
+
+ if (DISPLAY_VER(dev_priv) < 14)
+ return;
+
+ if (!new_pmdmnd_state ||
+ memcmp(new_pmdmnd_state, old_pmdmnd_state, sizeof(*new_pmdmnd_state)) == 0)
+ return;
+
+ intel_program_pmdemand(dev_priv, new_pmdmnd_state, old_pmdmnd_state);
+}
+
+void intel_pmdemand_post_plane_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_pmdemand_state *new_pmdmnd_state =
+ intel_atomic_get_new_pmdemand_state(state);
+ const struct intel_pmdemand_state *old_pmdmnd_state =
+ intel_atomic_get_old_pmdemand_state(state);
+
+ if (DISPLAY_VER(dev_priv) < 14)
+ return;
+
+ if (!new_pmdmnd_state ||
+ memcmp(new_pmdmnd_state, old_pmdmnd_state, sizeof(*new_pmdmnd_state)) == 0)
+ return;
+
+ intel_program_pmdemand(dev_priv, new_pmdmnd_state, NULL);
+}
+
static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
{
/*
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index f774bddcdca6..2663bec408c7 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -8,11 +8,46 @@
#include <linux/types.h>
+#include "display/intel_global_state.h"
+
struct drm_i915_private;
struct intel_crtc_state;
struct intel_plane_state;
void intel_init_clock_gating(struct drm_i915_private *dev_priv);
+void intel_init_pmdemand(struct drm_i915_private *dev_priv);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
+struct intel_pmdemand_state {
+ struct intel_global_state base;
+
+ u16 qclk_gv_bw;
+ u8 voltage_index;
+ u8 qclk_gv_index;
+ u8 active_pipes;
+ u8 dbufs;
+ u8 active_phys_plls_mask;
+ u16 cdclk_freq_mhz;
+ u16 ddiclk_freq_mhz;
+ u8 scalers;
+};
+
+int intel_pmdemand_init(struct drm_i915_private *dev_priv);
+
+struct intel_pmdemand_state *
+intel_atomic_get_pmdemand_state(struct intel_atomic_state *state);
+
+#define to_intel_pmdemand_state(x) container_of((x), struct intel_pmdemand_state, base)
+#define intel_atomic_get_old_pmdemand_state(state) \
+ to_intel_pmdemand_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->pmdemand.obj))
+#define intel_atomic_get_new_pmdemand_state(state) \
+ to_intel_pmdemand_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->pmdemand.obj))
+
+int intel_pmdemand_init(struct drm_i915_private *dev_priv);
+void intel_program_dbuf_pmdemand(struct drm_i915_private *dev_priv,
+ u8 dbuf_slices);
+void intel_pmdemand_pre_plane_update(struct intel_atomic_state *state);
+void intel_pmdemand_post_plane_update(struct intel_atomic_state *state);
+int intel_pmdemand_atomic_check(struct intel_atomic_state *state);
+
#endif /* __INTEL_PM_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add Support for C10 chips
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
` (6 preceding siblings ...)
2023-03-27 12:34 ` [Intel-gfx] [PATCH 7/7] drm/i915/mtl: Add support for PM DEMAND Mika Kahola
@ 2023-03-27 19:19 ` Patchwork
2023-03-27 19:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (7 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2023-03-27 19:19 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 chips
URL : https://patchwork.freedesktop.org/series/115664/
State : warning
== Summary ==
Error: dim checkpatch failed
acf3d3886bcc drm/i915/mtl: Initial DDI port setup
fa367a60b5f5 drm/i915/mtl: Add DP rates
dd49f2562c22 drm/i915/mtl: Create separate reg file for PICA registers
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:17: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#17:
new file mode 100644
-:37: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#37: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:16:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
-:38: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#38: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:17:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
-:39: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#39: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:18:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
-:40: WARNING:LONG_LINE: line length of 133 exceeds 100 columns
#40: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:19:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
-:43: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#43: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:22:
+#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
-:44: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:23:
+#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
-:45: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:24:
+#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
-:47: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#47: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:26:
+#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
-:50: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#50: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:29:
+#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
-:52: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#52: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:31:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
-:53: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#53: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:32:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
-:54: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:33:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
-:55: WARNING:LONG_LINE: line length of 137 exceeds 100 columns
#55: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:34:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
-:61: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#61: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:40:
+#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
-:79: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#79: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:58:
+ _XELPDP_PORT_BUF_CTL1_LN0_A, \
-:80: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#80: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:59:
+ _XELPDP_PORT_BUF_CTL1_LN0_B, \
-:81: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#81: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:60:
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
-:82: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#82: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:61:
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC2))
-:92: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#92: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:71:
+ _XELPDP_PORT_BUF_CTL1_LN0_A, \
-:93: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#93: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:72:
+ _XELPDP_PORT_BUF_CTL1_LN0_B, \
-:94: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#94: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:73:
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
-:95: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#95: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:74:
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4)
-:103: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#103: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:82:
+#define XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
-:105: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#105: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:84:
+#define XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val)
-:107: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#107: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:86:
+#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
-:110: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#110: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:89:
+ _XELPDP_PORT_BUF_CTL1_LN0_A, \
-:111: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#111: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:90:
+ _XELPDP_PORT_BUF_CTL1_LN0_B, \
-:112: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#112: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:91:
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
-:113: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#113: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:92:
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8)
-:115: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#115: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:94:
+#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
-:117: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#117: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:96:
+#define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
-:124: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#124: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:103:
+ _XELPDP_PORT_CLOCK_CTL_A, \
-:125: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#125: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:104:
+ _XELPDP_PORT_CLOCK_CTL_B, \
-:126: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#126: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:105:
+ _XELPDP_PORT_CLOCK_CTL_USBC1, \
-:127: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#127: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:106:
+ _XELPDP_PORT_CLOCK_CTL_USBC2))
-:139: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#139: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:118:
+#define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val)
total: 0 errors, 37 warnings, 0 checks, 131 lines checked
484ad1495ef9 drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:24: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#24:
Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
-:58: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#58:
new file mode 100644
-:79: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'phy < PHY_C'
#79: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:17:
+ if (IS_METEORLAKE(dev_priv) && (phy < PHY_C))
-:114: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#114: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:52:
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", phy_name(phy), *val);
-:122: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#122: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:60:
+static int __intel_cx0_read(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u32 *val)
-:131: WARNING:LONG_LINE: line length of 146 exceeds 100 columns
#131: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:69:
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
-:151: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#151: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:89:
+ drm_dbg_kms(&i915->drm, "PHY %c Error occurred during read command. Status: 0x%x\n", phy_name(phy), *val);
-:159: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#159: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:97:
+ drm_dbg_kms(&i915->drm, "PHY %c Not a Read response. MSGBUS Status: 0x%x.\n", phy_name(phy), *val);
-:185: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#185: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:123:
+ drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n", phy_name(phy), addr, i);
-:193: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#193: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:131:
+static int intel_cx0_wait_cwrite_ack(struct drm_i915_private *i915,
+ enum port port, int lane)
-:206: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#206: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:144:
+ drm_dbg_kms(&i915->drm, "PHY %c Unexpected ACK received. MSGBUS STATUS: 0x%x.\n", phy_name(phy), val);
-:222: WARNING:LONG_LINE: line length of 146 exceeds 100 columns
#222: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:160:
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
-:243: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#243: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:181:
+ drm_dbg_kms(&i915->drm, "PHY %c Error occurred during write command.\n", phy_name(phy));
-:267: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#267: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:205:
+ drm_err_once(&i915->drm, "PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
-:672: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#672: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:610:
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
-:673: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#673: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:611:
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_TX(0), C10_TX0_VAL, MB_WRITE_COMMITTED);
-:868: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#868: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:806:
+ XELPDP_LANE0_PHY_CURRENT_STATUS | XELPDP_LANE1_PHY_CURRENT_STATUS,
-:869: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#869: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:807:
+ XELPDP_LANE0_PHY_CURRENT_STATUS | XELPDP_LANE1_PHY_CURRENT_STATUS,
-:943: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#943: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:881:
+ intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
-:948: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#948: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:886:
+ intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
-:974: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#974: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:912:
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
-:1189: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/display/intel_cx0_phy.h', please use '/*' instead
#1189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.h:1:
+// SPDX-License-Identifier: MIT
-:1189: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#1189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.h:1:
+// SPDX-License-Identifier: MIT
-:1298: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#1298: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3521:
+ crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->c10mpllb_state);
-:1487: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__n' - possible side-effects?
#1487: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:33:
+#define REG_BIT8(__n) \
+ ((u8)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 7))))
-:1508: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__high' - possible side-effects?
#1508: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:77:
+#define REG_GENMASK8(__high, __low) \
+ ((u8)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 7 || (__low) > (__high)))))
-:1508: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__low' - possible side-effects?
#1508: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:77:
+#define REG_GENMASK8(__high, __low) \
+ ((u8)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 7 || (__low) > (__high)))))
-:1531: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__mask' - possible side-effects?
#1531: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:115:
+#define REG_FIELD_PREP8(__mask, __val) \
+ ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:1531: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__val' - possible side-effects?
#1531: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:115:
+#define REG_FIELD_PREP8(__mask, __val) \
+ ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:1536: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#1536: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:120:
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
total: 0 errors, 22 warnings, 8 checks, 1438 lines checked
5ab3ed0136b6 drm/i915/mtl: Add C10 phy programming for HDMI
-:21: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#21:
v3: Add missing use_hdmi checks from Clint's HDMI implementation changes (Ankit)
-:165: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#165: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:615:
+ .pll[0]=0x34,
^
-:166: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#166: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:616:
+ .pll[1]=0x00,
^
-:167: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#167: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:617:
+ .pll[2]=0xB0,
^
-:168: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#168: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:618:
+ .pll[3]=0x00,
^
-:169: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#169: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:619:
+ .pll[4]=0x00,
^
-:170: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#170: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:620:
+ .pll[5]=0x00,
^
-:171: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#171: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:621:
+ .pll[6]=0x00,
^
-:172: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#172: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:622:
+ .pll[7]=0x00,
^
-:173: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#173: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:623:
+ .pll[8]=0x20,
^
-:174: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#174: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:624:
+ .pll[9]=0xFF,
^
-:175: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#175: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:625:
+ .pll[10]=0xFF,
^
-:176: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#176: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:626:
+ .pll[11]=0x55,
^
-:177: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#177: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:627:
+ .pll[12]=0xE5,
^
-:178: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#178: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:628:
+ .pll[13]=0x55,
^
-:179: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#179: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:629:
+ .pll[14]=0x55,
^
-:180: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#180: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:630:
+ .pll[15]=0x0D,
^
-:181: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#181: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:631:
+ .pll[16]=0x09,
^
-:182: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#182: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:632:
+ .pll[17]=0x8F,
^
-:183: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#183: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:633:
+ .pll[18]=0x84,
^
-:184: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#184: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:634:
+ .pll[19]=0x23,
^
-:189: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:639:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
^
-:189: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:639:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
^
-:189: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:639:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
^
-:189: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:639:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
^
-:189: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:639:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
^
-:190: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:640:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:190: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:640:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:190: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:640:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:190: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:640:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:190: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:640:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:191: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: space required after that ',' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: space required after that ',' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: space required after that ',' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: space required after that ',' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:192: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: space required after that ',' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: space required after that ',' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: space required after that ',' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: space required after that ',' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:197: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#197: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:647:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xCC, .pll[3]=0x00, .pll[4]=0x00,
^
-:197: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#197: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:647:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xCC, .pll[3]=0x00, .pll[4]=0x00,
^
-:197: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#197: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:647:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xCC, .pll[3]=0x00, .pll[4]=0x00,
^
-:197: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#197: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:647:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xCC, .pll[3]=0x00, .pll[4]=0x00,
^
-:197: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#197: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:647:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xCC, .pll[3]=0x00, .pll[4]=0x00,
^
-:198: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#198: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:648:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:198: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#198: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:648:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:198: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#198: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:648:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:198: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#198: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:648:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:198: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#198: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:648:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:199: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: space required after that ',' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: space required after that ',' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: space required after that ',' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: space required after that ',' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:200: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: space required after that ',' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: space required after that ',' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: space required after that ',' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: space required after that ',' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:205: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#205: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:655:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xDC, .pll[3]=0x00, .pll[4]=0x00,
^
-:205: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#205: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:655:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xDC, .pll[3]=0x00, .pll[4]=0x00,
^
-:205: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#205: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:655:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xDC, .pll[3]=0x00, .pll[4]=0x00,
^
-:205: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#205: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:655:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xDC, .pll[3]=0x00, .pll[4]=0x00,
^
-:205: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#205: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:655:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xDC, .pll[3]=0x00, .pll[4]=0x00,
^
-:206: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#206: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:656:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:206: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#206: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:656:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:206: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#206: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:656:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:206: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#206: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:656:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:206: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#206: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:656:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:207: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: space required after that ',' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: space required after that ',' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: space required after that ',' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: space required after that ',' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:208: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: space required after that ',' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: space required after that ',' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: space required after that ',' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: space required after that ',' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:213: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#213: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:663:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x62, .pll[3]=0x00, .pll[4]=0x00,
^
-:213: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#213: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:663:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x62, .pll[3]=0x00, .pll[4]=0x00,
^
-:213: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#213: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:663:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x62, .pll[3]=0x00, .pll[4]=0x00,
^
-:213: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#213: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:663:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x62, .pll[3]=0x00, .pll[4]=0x00,
^
-:213: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#213: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:663:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x62, .pll[3]=0x00, .pll[4]=0x00,
^
-:214: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#214: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:664:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:214: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#214: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:664:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:214: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#214: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:664:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:214: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#214: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:664:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:214: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#214: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:664:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:215: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: space required after that ',' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: space required after that ',' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: space required after that ',' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: space required after that ',' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:216: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: space required after that ',' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: space required after that ',' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: space required after that ',' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: space required after that ',' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:221: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#221: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:671:
+ .pll[0]=0xC4, .pll[1]=0x00, .pll[2]=0x76, .pll[3]=0x00, .pll[4]=0x00,
^
-:221: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#221: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:671:
+ .pll[0]=0xC4, .pll[1]=0x00, .pll[2]=0x76, .pll[3]=0x00, .pll[4]=0x00,
^
-:221: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#221: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:671:
+ .pll[0]=0xC4, .pll[1]=0x00, .pll[2]=0x76, .pll[3]=0x00, .pll[4]=0x00,
^
-:221: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#221: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:671:
+ .pll[0]=0xC4, .pll[1]=0x00, .pll[2]=0x76, .pll[3]=0x00, .pll[4]=0x00,
^
-:221: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#221: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:671:
+ .pll[0]=0xC4, .pll[1]=0x00, .pll[2]=0x76, .pll[3]=0x00, .pll[4]=0x00,
^
-:222: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#222: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:672:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:222: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#222: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:672:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:222: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#222: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:672:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:222: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#222: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:672:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:222: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#222: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:672:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:223: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: space required after that ',' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: space required after that ',' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: space required after that ',' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: space required after that ',' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:224: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: space required after that ',' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: space required after that ',' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: space required after that ',' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: space required after that ',' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:229: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#229: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:679:
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
^
-:229: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#229: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:679:
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
^
-:229: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#229: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:679:
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
^
-:229: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#229: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:679:
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
^
-:229: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#229: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:679:
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
^
-:230: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#230: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:680:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:230: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#230: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:680:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:230: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#230: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:680:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:230: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#230: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:680:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:230: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#230: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:680:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:231: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: space required after that ',' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: space required after that ',' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: space required after that ',' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: space required after that ',' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:232: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: space required after that ',' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: space required after that ',' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: space required after that ',' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: space required after that ',' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:237: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#237: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:687:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
^
-:237: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#237: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:687:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
^
-:237: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#237: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:687:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
^
-:237: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#237: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:687:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
^
-:237: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#237: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:687:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
^
-:238: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#238: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:688:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:238: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#238: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:688:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:238: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#238: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:688:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:238: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#238: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:688:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:238: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#238: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:688:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:239: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: space required after that ',' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: space required after that ',' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: space required after that ',' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: space required after that ',' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:240: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: space required after that ',' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: space required after that ',' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: space required after that ',' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: space required after that ',' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:245: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#245: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:695:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xB0, .pll[3]=0x00, .pll[4]=0x00,
^
-:245: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#245: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:695:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xB0, .pll[3]=0x00, .pll[4]=0x00,
^
-:245: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#245: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:695:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xB0, .pll[3]=0x00, .pll[4]=0x00,
^
-:245: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#245: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:695:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xB0, .pll[3]=0x00, .pll[4]=0x00,
^
-:245: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#245: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:695:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xB0, .pll[3]=0x00, .pll[4]=0x00,
^
-:246: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#246: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:696:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:246: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#246: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:696:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:246: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#246: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:696:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:246: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#246: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:696:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:246: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#246: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:696:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:247: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: space required after that ',' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: space required after that ',' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: space required after that ',' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: space required after that ',' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:248: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: space required after that ',' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: space required after that ',' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: space required after that ',' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: space required after that ',' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:253: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#253: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:703:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xCE, .pll[3]=0x00, .pll[4]=0x00,
^
-:253: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#253: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:703:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xCE, .pll[3]=0x00, .pll[4]=0x00,
^
-:253: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#253: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:703:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xCE, .pll[3]=0x00, .pll[4]=0x00,
^
-:253: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#253: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:703:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xCE, .pll[3]=0x00, .pll[4]=0x00,
^
-:253: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#253: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:703:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xCE, .pll[3]=0x00, .pll[4]=0x00,
^
-:254: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#254: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:704:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:254: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#254: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:704:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:254: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#254: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:704:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:254: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#254: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:704:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:254: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#254: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:704:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:255: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: space required after that ',' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: space required after that ',' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: space required after that ',' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: space required after that ',' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:256: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: space required after that ',' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: space required after that ',' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: space required after that ',' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: space required after that ',' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:261: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#261: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:711:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
^
-:261: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#261: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:711:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
^
-:261: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#261: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:711:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
^
-:261: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#261: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:711:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
^
-:261: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#261: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:711:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
^
-:262: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#262: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:712:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:262: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#262: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:712:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:262: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#262: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:712:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:262: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#262: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:712:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:262: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#262: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:712:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:263: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: space required after that ',' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: space required after that ',' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: space required after that ',' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: space required after that ',' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:264: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: space required after that ',' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: space required after that ',' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: space required after that ',' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: space required after that ',' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:269: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#269: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:719:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x66, .pll[3]=0x00, .pll[4]=0x00,
^
-:269: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#269: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:719:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x66, .pll[3]=0x00, .pll[4]=0x00,
^
-:269: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#269: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:719:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x66, .pll[3]=0x00, .pll[4]=0x00,
^
-:269: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#269: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:719:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x66, .pll[3]=0x00, .pll[4]=0x00,
^
-:269: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#269: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:719:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x66, .pll[3]=0x00, .pll[4]=0x00,
^
-:270: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#270: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:720:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:270: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#270: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:720:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:270: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#270: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:720:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:270: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#270: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:720:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:270: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#270: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:720:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:271: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: space required after that ',' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: space required after that ',' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: space required after that ',' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: space required after that ',' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:272: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: space required after that ',' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: space required after that ',' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: space required after that ',' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: space required after that ',' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:277: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#277: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:727:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x72, .pll[3]=0x00, .pll[4]=0x00,
^
-:277: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#277: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:727:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x72, .pll[3]=0x00, .pll[4]=0x00,
^
-:277: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#277: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:727:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x72, .pll[3]=0x00, .pll[4]=0x00,
^
-:277: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#277: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:727:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x72, .pll[3]=0x00, .pll[4]=0x00,
^
-:277: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#277: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:727:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x72, .pll[3]=0x00, .pll[4]=0x00,
^
-:278: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#278: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:728:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:278: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#278: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:728:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:278: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#278: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:728:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:278: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#278: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:728:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:278: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#278: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:728:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:279: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: space required after that ',' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: space required after that ',' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: space required after that ',' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: space required after that ',' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:280: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: space required after that ',' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: space required after that ',' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: space required after that ',' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: space required after that ',' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:285: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#285: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:735:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
^
-:285: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#285: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:735:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
^
-:285: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#285: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:735:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add Support for C10 chips
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
` (7 preceding siblings ...)
2023-03-27 19:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add Support for C10 chips Patchwork
@ 2023-03-27 19:19 ` Patchwork
2023-03-27 19:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (6 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2023-03-27 19:19 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 chips
URL : https://patchwork.freedesktop.org/series/115664/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Add Support for C10 chips
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
` (8 preceding siblings ...)
2023-03-27 19:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-03-27 19:23 ` Patchwork
2023-03-28 1:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
` (5 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2023-03-27 19:23 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3646 bytes --]
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 chips
URL : https://patchwork.freedesktop.org/series/115664/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12921 -> Patchwork_115664v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/index.html
Participating hosts (37 -> 36)
------------------------------
Missing (1): fi-kbl-soraka
Known issues
------------
Here are the changes found in Patchwork_115664v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [PASS][1] -> [DMESG-WARN][2] ([i915#7699])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/bat-dg2-11/igt@i915_selftest@live@migrate.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/bat-dg2-11/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-FAIL][3] ([i915#6997] / [i915#7913])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/bat-rpls-2/igt@i915_selftest@live@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-2: NOTRUN -> [ABORT][4] ([i915#6687])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/bat-rpls-2/igt@i915_suspend@basic-s2idle-without-i915.html
#### Possible fixes ####
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][5] ([i915#4983] / [i915#7913]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/bat-rpls-2/igt@i915_selftest@live@reset.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/bat-rpls-2/igt@i915_selftest@live@reset.html
#### Warnings ####
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][7] ([i915#6367]) -> [DMESG-FAIL][8] ([i915#6367] / [i915#7996])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/bat-rpls-1/igt@i915_selftest@live@slpc.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/bat-rpls-1/igt@i915_selftest@live@slpc.html
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
Build changes
-------------
* Linux: CI_DRM_12921 -> Patchwork_115664v1
CI-20190529: 20190529
CI_DRM_12921: 3de6040ce9900a94ec626662d5c6a227b37eeb1c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7221: 4b77c6d85024d22ca521d510f8eee574128fe04f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_115664v1: 3de6040ce9900a94ec626662d5c6a227b37eeb1c @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
44fd26d03e78 drm/i915/mtl: Add support for PM DEMAND
0a81d023ecf3 drm/i915/mtl: Add vswing programming for C10 phys
8dc097cb04ea drm/i915/mtl: Add C10 phy programming for HDMI
5c7fcca442fa drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
8c2f753b154f drm/i915/mtl: Create separate reg file for PICA registers
d5b7d4eeaded drm/i915/mtl: Add DP rates
be08398ebf6f drm/i915/mtl: Initial DDI port setup
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/index.html
[-- Attachment #2: Type: text/html, Size: 4518 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mtl: Add Support for C10 chips
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
` (9 preceding siblings ...)
2023-03-27 19:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-03-28 1:44 ` Patchwork
2023-03-29 16:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add Support for C10 chips (rev2) Patchwork
` (4 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2023-03-28 1:44 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 13635 bytes --]
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 chips
URL : https://patchwork.freedesktop.org/series/115664/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12921_full -> Patchwork_115664v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_115664v1_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_vblank@pipe-b-wait-idle:
- {shard-dg1}: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-dg1-18/igt@kms_vblank@pipe-b-wait-idle.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-dg1-17/igt@kms_vblank@pipe-b-wait-idle.html
Known issues
------------
Here are the changes found in Patchwork_115664v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-glk: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-glk3/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][6] -> [ABORT][7] ([i915#5566])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-glk1/igt@gen9_exec_parse@allowed-single.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-glk4/igt@gen9_exec_parse@allowed-single.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#3886]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-apl6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2346]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
- shard-apl: [PASS][11] -> [FAIL][12] ([i915#2346])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a1:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#2122])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-glk6/igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a1.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-glk8/igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a1.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-dp-1:
- shard-apl: NOTRUN -> [SKIP][15] ([fdo#109271]) +76 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-apl2/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-c-dp-1.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#658])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-apl2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@vc4/vc4_perfmon@create-perfmon-exceed:
- shard-glk: NOTRUN -> [SKIP][17] ([fdo#109271]) +20 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-glk3/igt@vc4/vc4_perfmon@create-perfmon-exceed.html
#### Possible fixes ####
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][18] ([i915#6268]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-tglu-7/igt@gem_ctx_exec@basic-nohangcheck.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-tglu-2/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: [FAIL][20] ([i915#2846]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-apl1/igt@gem_exec_fair@basic-deadline.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-apl4/igt@gem_exec_fair@basic-deadline.html
* igt@gem_mmap_offset@clear@smem0:
- {shard-dg1}: [DMESG-WARN][22] ([i915#8304]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-dg1-17/igt@gem_mmap_offset@clear@smem0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-dg1-16/igt@gem_mmap_offset@clear@smem0.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [ABORT][24] ([i915#5566]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-apl6/igt@gen9_exec_parse@allowed-all.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-apl2/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc9-dpms:
- {shard-tglu}: [SKIP][26] ([i915#4281]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-tglu-5/igt@i915_pm_dc@dc9-dpms.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-tglu-10/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [DMESG-FAIL][28] ([i915#5334]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-apl6/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@forked-move@pipe-b:
- {shard-dg1}: [INCOMPLETE][30] ([i915#8011]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-dg1-14/igt@kms_cursor_legacy@forked-move@pipe-b.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-dg1-16/igt@kms_cursor_legacy@forked-move@pipe-b.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [ABORT][32] ([i915#180]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* {igt@perf@oa-exponents@0-rcs0}:
- shard-glk: [ABORT][34] -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12921/shard-glk3/igt@perf@oa-exponents@0-rcs0.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/shard-glk3/igt@perf@oa-exponents@0-rcs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8150]: https://gitlab.freedesktop.org/drm/intel/issues/8150
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8304]: https://gitlab.freedesktop.org/drm/intel/issues/8304
[i915#8308]: https://gitlab.freedesktop.org/drm/intel/issues/8308
Build changes
-------------
* Linux: CI_DRM_12921 -> Patchwork_115664v1
CI-20190529: 20190529
CI_DRM_12921: 3de6040ce9900a94ec626662d5c6a227b37eeb1c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7221: 4b77c6d85024d22ca521d510f8eee574128fe04f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_115664v1: 3de6040ce9900a94ec626662d5c6a227b37eeb1c @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v1/index.html
[-- Attachment #2: Type: text/html, Size: 10851 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915/mtl: Initial DDI port setup
2023-03-27 12:34 ` [Intel-gfx] [PATCH 1/7] drm/i915/mtl: Initial DDI port setup Mika Kahola
@ 2023-03-28 11:41 ` Govindapillai, Vinod
0 siblings, 0 replies; 37+ messages in thread
From: Govindapillai, Vinod @ 2023-03-28 11:41 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx; +Cc: De Marchi, Lucas
On Mon, 2023-03-27 at 15:34 +0300, Mika Kahola wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> Initialization sequences and C10 phy are in place to be able to enable
> the first 2 ports of MTL. The other ports use C20 phy that still need
> to be properly added. Enable the first ports for now, keeping a TODO
> comment about the others.
>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> ---
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> drivers/gpu/drm/i915/display/intel_display.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 5a386c7c0bc9..9fe6e33a66d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7796,7 +7796,11 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
> - if (IS_DG2(dev_priv)) {
> + if (IS_METEORLAKE(dev_priv)) {
> + /* TODO: initialize TC ports as well */
> + intel_ddi_init(dev_priv, PORT_A);
> + intel_ddi_init(dev_priv, PORT_B);
> + } else if (IS_DG2(dev_priv)) {
> intel_ddi_init(dev_priv, PORT_A);
> intel_ddi_init(dev_priv, PORT_B);
> intel_ddi_init(dev_priv, PORT_C);
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915/mtl: Add DP rates
2023-03-27 12:34 ` [Intel-gfx] [PATCH 2/7] drm/i915/mtl: Add DP rates Mika Kahola
@ 2023-03-28 12:49 ` Govindapillai, Vinod
0 siblings, 0 replies; 37+ messages in thread
From: Govindapillai, Vinod @ 2023-03-28 12:49 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx
On Mon, 2023-03-27 at 15:34 +0300, Mika Kahola wrote:
> Add DP rates for Meteorlake.
>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> drivers/gpu/drm/i915/display/intel_dp.c | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index da1c00ee92fb..4927aeb64f23 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -420,6 +420,11 @@ static int ehl_max_source_rate(struct intel_dp *intel_dp)
> return 810000;
> }
>
> +static int mtl_max_source_rate(struct intel_dp *intel_dp)
> +{
> + return intel_dp_is_edp(intel_dp) ? 675000 : 810000;
> +}
> +
> static int vbt_max_link_rate(struct intel_dp *intel_dp)
> {
> struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> @@ -444,6 +449,10 @@ static void
> intel_dp_set_source_rates(struct intel_dp *intel_dp)
> {
> /* The values must be in increasing order */
> + static const int mtl_rates[] = {
> + 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
> + 810000,
> + };
> static const int icl_rates[] = {
> 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
> 1000000, 1350000,
> @@ -469,7 +478,11 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
> drm_WARN_ON(&dev_priv->drm,
> intel_dp->source_rates || intel_dp->num_source_rates);
>
> - if (DISPLAY_VER(dev_priv) >= 11) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + source_rates = mtl_rates;
> + size = ARRAY_SIZE(mtl_rates);
> + max_rate = mtl_max_source_rate(intel_dp);
> + } else if (DISPLAY_VER(dev_priv) >= 11) {
> source_rates = icl_rates;
> size = ARRAY_SIZE(icl_rates);
> if (IS_DG2(dev_priv))
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 3/7] drm/i915/mtl: Create separate reg file for PICA registers
2023-03-27 12:34 ` [Intel-gfx] [PATCH 3/7] drm/i915/mtl: Create separate reg file for PICA registers Mika Kahola
@ 2023-03-28 15:33 ` Govindapillai, Vinod
0 siblings, 0 replies; 37+ messages in thread
From: Govindapillai, Vinod @ 2023-03-28 15:33 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx
On Mon, 2023-03-27 at 15:34 +0300, Mika Kahola wrote:
> Create a separate file to store registers for PICA chips
> C10 and C20.
>
> v2: Rename file (Jani)
> v3: Use _PICK_EVEN_2RANGES() macro (Lucas)
> Coding style fixed (Lucas)
>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
You might need to adjust some tabs before pushing I feel..
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 131 ++++++++++++++++++
> 1 file changed, 131 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> new file mode 100644
> index 000000000000..d1ee8a2fc9cf
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -0,0 +1,131 @@
> +/* SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __INTEL_CX0_PHY_REGS_H__
> +#define __INTEL_CX0_PHY_REGS_H__
> +
> +#include "i915_reg_defs.h"
> +
> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
> +#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
> +#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
> +
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
> +
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> +
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
> +#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
> +#define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
> +#define
> XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK,
> 0x1)
> +#define
> XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK,
> 0x2)
> +#define
> XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK,
> 0x3)
> +#define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16)
> +#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK,
> val)
> +#define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
> +#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
> +#define
> XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
> +#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
> +
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
> +
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
> +
> _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
> +#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
> +#define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
> +#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
> +#define XELPDP_PORT_P2M_COMMAND_WRITE_ACK 0x5
> +#define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16)
> +#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK,
> val)
> +#define XELPDP_PORT_P2M_ERROR_SET REG_BIT(15)
> +
> +#define XELPDP_MSGBUS_TIMEOUT_SLOW 1
> +#define XELPDP_MSGBUS_TIMEOUT_FAST_US 2
> +#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200
> +#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20
> +#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100
> +#define XELPDP_PORT_RESET_START_TIMEOUT_US 5
> +#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US 100
> +#define XELPDP_PORT_RESET_END_TIMEOUT 15
> +#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
> +
> +#define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
> +#define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
> +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200
> +#define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400
> +#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +
> _XELPDP_PORT_BUF_CTL1_LN0_A, \
> +
> _XELPDP_PORT_BUF_CTL1_LN0_B, \
> +
> _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> +
> _XELPDP_PORT_BUF_CTL1_LN0_USBC2))
> +#define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
> +#define XELPDP_PORT_REVERSAL REG_BIT(16)
> +#define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6)
> +#define XELPDP_TCSS_POWER_REQUEST REG_BIT(5)
> +#define XELPDP_TCSS_POWER_STATE REG_BIT(4)
> +#define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
> +#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK,
> val)
> +
> +#define XELPDP_PORT_BUF_CTL2(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +
> _XELPDP_PORT_BUF_CTL1_LN0_A, \
> +
> _XELPDP_PORT_BUF_CTL1_LN0_B, \
> +
> _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> +
> _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4)
> +#define XELPDP_LANE0_PIPE_RESET REG_BIT(31)
> +#define XELPDP_LANE1_PIPE_RESET REG_BIT(30)
> +#define XELPDP_LANE0_PHY_CURRENT_STATUS REG_BIT(29)
> +#define XELPDP_LANE1_PHY_CURRENT_STATUS REG_BIT(28)
> +#define XELPDP_LANE0_POWERDOWN_UPDATE REG_BIT(25)
> +#define XELPDP_LANE1_POWERDOWN_UPDATE REG_BIT(24)
> +#define XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK REG_GENMASK(23, 20)
> +#define
> XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE0_POWERDOWN_NEW_STA
> TE_MASK, val)
> +#define XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK REG_GENMASK(19, 16)
> +#define
> XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE1_POWERDOWN_NEW_STA
> TE_MASK, val)
> +#define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4)
> +#define
> XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK,
> val)
> +
> +#define XELPDP_PORT_BUF_CTL3(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +
> _XELPDP_PORT_BUF_CTL1_LN0_A, \
> +
> _XELPDP_PORT_BUF_CTL1_LN0_B, \
> +
> _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
> +
> _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8)
> +#define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8)
> +#define
> XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DEL
> AY_MASK, val)
> +#define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
> +#define
> XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
> +
> +#define _XELPDP_PORT_CLOCK_CTL_A 0x640E0
> +#define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
> +#define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
> +#define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460
> +#define XELPDP_PORT_CLOCK_CTL(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
> +
> _XELPDP_PORT_CLOCK_CTL_A, \
> +
> _XELPDP_PORT_CLOCK_CTL_B, \
> +
> _XELPDP_PORT_CLOCK_CTL_USBC1, \
> +
> _XELPDP_PORT_CLOCK_CTL_USBC2))
> +#define XELPDP_LANE0_PCLK_PLL_REQUEST REG_BIT(31)
> +#define XELPDP_LANE0_PCLK_PLL_ACK REG_BIT(30)
> +#define XELPDP_LANE0_PCLK_REFCLK_REQUEST REG_BIT(29)
> +#define XELPDP_LANE0_PCLK_REFCLK_ACK REG_BIT(28)
> +#define XELPDP_LANE1_PCLK_PLL_REQUEST REG_BIT(27)
> +#define XELPDP_LANE1_PCLK_PLL_ACK REG_BIT(26)
> +#define XELPDP_LANE1_PCLK_REFCLK_REQUEST REG_BIT(25)
> +#define XELPDP_LANE1_PCLK_REFCLK_ACK REG_BIT(24)
> +#define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19)
> +#define XELPDP_TBT_CLOCK_ACK REG_BIT(18)
> +#define XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12)
> +#define
> XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val)
> +#define XELPDP_DDI_CLOCK_SELECT_NONE 0x0
> +#define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8
> +#define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9
> +#define XELPDP_DDI_CLOCK_SELECT_TBT_162 0xc
> +#define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd
> +#define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe
> +#define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf
> +#define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10)
> +#define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8)
> +#define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
> +#define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
> +
> +#endif /* __INTEL_CX0_PHY_REGS_H__ */
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-03-27 12:34 ` [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming Mika Kahola
@ 2023-03-29 10:22 ` Govindapillai, Vinod
2023-03-29 15:40 ` Imre Deak
2023-04-03 10:11 ` Imre Deak
2 siblings, 0 replies; 37+ messages in thread
From: Govindapillai, Vinod @ 2023-03-29 10:22 UTC (permalink / raw)
To: Kahola, Mika, intel-gfx
Hi Mika
There were some comments from the previous version
https://patchwork.freedesktop.org/patch/517048/#comment_943150
I think you should address them?
BR
vinod
On Mon, 2023-03-27 at 15:34 +0300, Mika Kahola wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
> has a dedicated PIPE 5.2 Message bus for configuration. This message
> bus is used to configure the phy internal registers.
>
> XELPDP has C10 phys to drive output to the EDP and the native output
> from the display engine. Add structures, programming hardware state
> readout logic. Port clock calculations are similar to DG2. Use the DG2
> formulae to calculate the port clock but use the relevant pll signals.
> Note: PHY lane 0 is always used for PLL programming.
>
> Add sequences for C10 phy enable/disable phy lane reset,
> powerdown change sequence and phy lane programming.
>
> Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
>
> v2: Squash patches related to C10 phy message bus and pll
> programming support (Jani)
> Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
> Move macro definitions (Jani)
> DP rates as separate patch (Jani)
> Spin out xelpdp register definitions into a separate file (Jani)
> Replace macro to select registers based on phy lane with
> function calls (Jani)
> Fix styling issues (Jani)
> Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
> v3: Move clear request flag into try-loop
> v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani)
> use __intel_de_wait_for_register() instead of __intel_wait_for_register
> and uncomment intel_uncore.h (Jani)
> Add DP-alt support for PHY lane programming (Khaled)
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1120 +++++++++++++++++
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 43 +
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 32 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 22 +-
> .../drm/i915/display/intel_display_power.c | 3 +-
> .../i915/display/intel_display_power_well.c | 2 +-
> .../drm/i915/display/intel_display_types.h | 6 +
> drivers/gpu/drm/i915/display/intel_dpll.c | 20 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
> .../drm/i915/display/intel_modeset_verify.c | 2 +
> drivers/gpu/drm/i915/i915_reg.h | 5 +
> drivers/gpu/drm/i915/i915_reg_defs.h | 57 +
> 13 files changed, 1309 insertions(+), 6 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 057ef22fa9c6..57b1417792b4 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -298,6 +298,7 @@ i915-y += \
> display/icl_dsi.o \
> display/intel_backlight.o \
> display/intel_crt.o \
> + display/intel_cx0_phy.o \
> display/intel_ddi.o \
> display/intel_ddi_buf_trans.o \
> display/intel_display_trace.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> new file mode 100644
> index 000000000000..ced8c8aa6c82
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -0,0 +1,1120 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include "i915_reg.h"
> +#include "intel_cx0_phy.h"
> +#include "intel_cx0_phy_regs.h"
> +#include "intel_de.h"
> +#include "intel_display_types.h"
> +#include "intel_dp.h"
> +#include "intel_panel.h"
> +#include "intel_tc.h"
> +
> +bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
> +{
> + if (IS_METEORLAKE(dev_priv) && (phy < PHY_C))
> + return true;
> +
> + return false;
> +}
> +
> +static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, int lane)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> +
> + /* Bring the phy to idle. */
> + intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> + XELPDP_PORT_M2P_TRANSACTION_RESET);
> +
> + /* Wait for Idle Clear. */
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> + XELPDP_PORT_M2P_TRANSACTION_RESET,
> + XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> + drm_dbg_kms(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
> + return;
> + }
> +
> + intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1), ~0);
> +}
> +
> +static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port, int lane, u32
> *val)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> +
> + if (__intel_de_wait_for_register(i915,
> + XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1),
> + XELPDP_PORT_P2M_RESPONSE_READY,
> + XELPDP_PORT_P2M_RESPONSE_READY,
> + XELPDP_MSGBUS_TIMEOUT_FAST_US,
> + XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
> + drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
> phy_name(phy), *val);
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +static int __intel_cx0_read(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr, u32 *val)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> + int ack;
> +
> + /* Wait for pending transactions.*/
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> + XELPDP_PORT_M2P_TRANSACTION_PENDING,
> + XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> + drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to
> complete. Reset the bus and retry.\n", phy_name(phy));
> + intel_cx0_bus_reset(i915, port, lane);
> + return -ETIMEDOUT;
> + }
> +
> + /* Issue the read command. */
> + intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> + XELPDP_PORT_M2P_TRANSACTION_PENDING |
> + XELPDP_PORT_M2P_COMMAND_READ |
> + XELPDP_PORT_M2P_ADDRESS(addr));
> +
> + /* Wait for response ready. And read response.*/
> + ack = intel_cx0_wait_for_ack(i915, port, lane, val);
> + if (ack < 0) {
> + intel_cx0_bus_reset(i915, port, lane);
> + return ack;
> + }
> +
> + /* Check for error. */
> + if (*val & XELPDP_PORT_P2M_ERROR_SET) {
> + drm_dbg_kms(&i915->drm, "PHY %c Error occurred during read command. Status:
> 0x%x\n", phy_name(phy), *val);
> + intel_cx0_bus_reset(i915, port, lane);
> + return -EINVAL;
> + }
> +
> + /* Check for Read Ack. */
> + if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) !=
> + XELPDP_PORT_P2M_COMMAND_READ_ACK) {
> + drm_dbg_kms(&i915->drm, "PHY %c Not a Read response. MSGBUS Status: 0x%x.\n",
> phy_name(phy), *val);
> + intel_cx0_bus_reset(i915, port, lane);
> + return -EINVAL;
> + }
> +
> + /* Clear Response Ready flag.*/
> + intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1), ~0);
> +
> + return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, *val);
> +}
> +
> +static u8 intel_cx0_read(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> + int i, status = 0;
> + u32 val;
> +
> + for (i = 0; i < 3; i++) {
> + status = __intel_cx0_read(i915, port, lane, addr, &val);
> +
> + if (status >= 0)
> + break;
> + }
> +
> + if (i == 3) {
> + drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n",
> phy_name(phy), addr, i);
> + return 0;
> + }
> +
> + return status;
> +}
> +
> +static int intel_cx0_wait_cwrite_ack(struct drm_i915_private *i915,
> + enum port port, int lane)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> + int ack;
> + u32 val = 0;
> +
> + /* Check for write ack. */
> + ack = intel_cx0_wait_for_ack(i915, port, lane, &val);
> + if (ack < 0)
> + return ack;
> +
> + if ((REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, val) !=
> + XELPDP_PORT_P2M_COMMAND_WRITE_ACK) || val & XELPDP_PORT_P2M_ERROR_SET) {
> + drm_dbg_kms(&i915->drm, "PHY %c Unexpected ACK received. MSGBUS STATUS: 0x%x.\n",
> phy_name(phy), val);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr, u8 data, bool committed)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> +
> + /* Wait for pending transactions.*/
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> + XELPDP_PORT_M2P_TRANSACTION_PENDING,
> + XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> + drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to
> complete. Reset the bus and retry.\n", phy_name(phy));
> + intel_cx0_bus_reset(i915, port, lane);
> + return -ETIMEDOUT;
> + }
> +
> + /* Issue the write command. */
> + intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> + XELPDP_PORT_M2P_TRANSACTION_PENDING |
> + (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
> + XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
> + XELPDP_PORT_M2P_DATA(data) |
> + XELPDP_PORT_M2P_ADDRESS(addr));
> +
> + /* Check for error. */
> + if (committed) {
> + if (intel_cx0_wait_cwrite_ack(i915, port, lane) < 0) {
> + intel_cx0_bus_reset(i915, port, lane);
> + return -EINVAL;
> + }
> + } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1)) &
> + XELPDP_PORT_P2M_ERROR_SET)) {
> + drm_dbg_kms(&i915->drm, "PHY %c Error occurred during write command.\n",
> phy_name(phy));
> + intel_cx0_bus_reset(i915, port, lane);
> + return -EINVAL;
> + }
> +
> + intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1), ~0);
> +
> + return 0;
> +}
> +
> +static void __intel_cx0_write(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr, u8 data, bool committed)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> + int i, status;
> +
> + for (i = 0; i < 3; i++) {
> + status = __intel_cx0_write_once(i915, port, lane, addr, data, committed);
> +
> + if (status == 0)
> + break;
> + }
> +
> + if (i == 3) {
> + drm_err_once(&i915->drm, "PHY %c Write %04x failed after %d retries.\n",
> phy_name(phy), addr, i);
> + return;
> + }
> +}
> +
> +static void intel_cx0_write(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr, u8 data, bool committed)
> +{
> + if (lane == INTEL_CX0_BOTH_LANES) {
> + __intel_cx0_write(i915, port, INTEL_CX0_LANE0, addr, data, committed);
> + __intel_cx0_write(i915, port, INTEL_CX0_LANE1, addr, data, committed);
> + } else {
> + __intel_cx0_write(i915, port, lane, addr, data, committed);
> + }
> +}
> +
> +static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr, u8 clear, u8 set, bool committed)
> +{
> + u8 old, val;
> +
> + old = intel_cx0_read(i915, port, lane, addr);
> + val = (old & ~clear) | set;
> +
> + if (val != old)
> + intel_cx0_write(i915, port, lane, addr, val, committed);
> +}
> +
> +static void intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr, u8 clear, u8 set, bool committed)
> +{
> + if (lane == INTEL_CX0_BOTH_LANES) {
> + __intel_cx0_rmw(i915, port, INTEL_CX0_LANE0, addr, clear, set, committed);
> + __intel_cx0_rmw(i915, port, INTEL_CX0_LANE1, addr, clear, set, committed);
> + } else {
> + __intel_cx0_rmw(i915, port, lane, addr, clear, set, committed);
> + }
> +}
> +
> +/*
> + * Basic DP link rates with 38.4 MHz reference clock.
> + * Note: The tables below are with SSC. In non-ssc
> + * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
> + * programmed 0.
> + */
> +
> +static const struct intel_c10mpllb_state mtl_c10_dp_rbr = {
> + .clock = 162000,
> + .pll[0] = 0xB4,
> + .pll[1] = 0,
> + .pll[2] = 0x30,
> + .pll[3] = 0x1,
> + .pll[4] = 0x26,
> + .pll[5] = 0x0C,
> + .pll[6] = 0x98,
> + .pll[7] = 0x46,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0xC0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0x2,
> + .pll[16] = 0x84,
> + .pll[17] = 0x4F,
> + .pll[18] = 0xE5,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_edp_r216 = {
> + .clock = 216000,
> + .pll[0] = 0x4,
> + .pll[1] = 0,
> + .pll[2] = 0xA2,
> + .pll[3] = 0x1,
> + .pll[4] = 0x33,
> + .pll[5] = 0x10,
> + .pll[6] = 0x75,
> + .pll[7] = 0xB3,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0x2,
> + .pll[16] = 0x85,
> + .pll[17] = 0x0F,
> + .pll[18] = 0xE6,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_edp_r243 = {
> + .clock = 243000,
> + .pll[0] = 0x34,
> + .pll[1] = 0,
> + .pll[2] = 0xDA,
> + .pll[3] = 0x1,
> + .pll[4] = 0x39,
> + .pll[5] = 0x12,
> + .pll[6] = 0xE3,
> + .pll[7] = 0xE9,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0x20,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0x2,
> + .pll[16] = 0x85,
> + .pll[17] = 0x8F,
> + .pll[18] = 0xE6,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_dp_hbr1 = {
> + .clock = 270000,
> + .pll[0] = 0xF4,
> + .pll[1] = 0,
> + .pll[2] = 0xF8,
> + .pll[3] = 0x0,
> + .pll[4] = 0x20,
> + .pll[5] = 0x0A,
> + .pll[6] = 0x29,
> + .pll[7] = 0x10,
> + .pll[8] = 0x1, /* Verify */
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0xA0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0x1,
> + .pll[16] = 0x84,
> + .pll[17] = 0x4F,
> + .pll[18] = 0xE5,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_edp_r324 = {
> + .clock = 324000,
> + .pll[0] = 0xB4,
> + .pll[1] = 0,
> + .pll[2] = 0x30,
> + .pll[3] = 0x1,
> + .pll[4] = 0x26,
> + .pll[5] = 0x0C,
> + .pll[6] = 0x98,
> + .pll[7] = 0x46,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0xC0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0x1,
> + .pll[16] = 0x85,
> + .pll[17] = 0x4F,
> + .pll[18] = 0xE6,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_edp_r432 = {
> + .clock = 432000,
> + .pll[0] = 0x4,
> + .pll[1] = 0,
> + .pll[2] = 0xA2,
> + .pll[3] = 0x1,
> + .pll[4] = 0x33,
> + .pll[5] = 0x10,
> + .pll[6] = 0x75,
> + .pll[7] = 0xB3,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0x1,
> + .pll[16] = 0x85,
> + .pll[17] = 0x0F,
> + .pll[18] = 0xE6,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_dp_hbr2 = {
> + .clock = 540000,
> + .pll[0] = 0xF4,
> + .pll[1] = 0,
> + .pll[2] = 0xF8,
> + .pll[3] = 0,
> + .pll[4] = 0x20,
> + .pll[5] = 0x0A,
> + .pll[6] = 0x29,
> + .pll[7] = 0x10,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0xA0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0,
> + .pll[16] = 0x84,
> + .pll[17] = 0x4F,
> + .pll[18] = 0xE5,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_edp_r675 = {
> + .clock = 675000,
> + .pll[0] = 0xB4,
> + .pll[1] = 0,
> + .pll[2] = 0x3E,
> + .pll[3] = 0x1,
> + .pll[4] = 0xA8,
> + .pll[5] = 0x0C,
> + .pll[6] = 0x33,
> + .pll[7] = 0x54,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0xC8,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0,
> + .pll[16] = 0x85,
> + .pll[17] = 0x8F,
> + .pll[18] = 0xE6,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_dp_hbr3 = {
> + .clock = 810000,
> + .pll[0] = 0x34,
> + .pll[1] = 0,
> + .pll[2] = 0x84,
> + .pll[3] = 0x1,
> + .pll[4] = 0x30,
> + .pll[5] = 0x0F,
> + .pll[6] = 0x3D,
> + .pll[7] = 0x98,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0xF0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0,
> + .pll[16] = 0x84,
> + .pll[17] = 0x0F,
> + .pll[18] = 0xE5,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state * const mtl_c10_dp_tables[] = {
> + &mtl_c10_dp_rbr,
> + &mtl_c10_dp_hbr1,
> + &mtl_c10_dp_hbr2,
> + &mtl_c10_dp_hbr3,
> + NULL,
> +};
> +
> +static const struct intel_c10mpllb_state * const mtl_c10_edp_tables[] = {
> + &mtl_c10_dp_rbr,
> + &mtl_c10_edp_r216,
> + &mtl_c10_edp_r243,
> + &mtl_c10_dp_hbr1,
> + &mtl_c10_edp_r324,
> + &mtl_c10_edp_r432,
> + &mtl_c10_dp_hbr2,
> + &mtl_c10_edp_r675,
> + &mtl_c10_dp_hbr3,
> + NULL,
> +};
> +
> +static const struct intel_c10mpllb_state * const *
> +intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> + return mtl_c10_edp_tables;
> + else
> + return mtl_c10_dp_tables;
> + }
> +
> + /* TODO: Add HDMI Support */
> + MISSING_CASE(encoder->type);
> + return NULL;
> +}
> +
> +static int intel_c10mpllb_calc_state(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + const struct intel_c10mpllb_state * const *tables;
> + int i;
> +
> + tables = intel_c10_mpllb_tables_get(crtc_state, encoder);
> + if (!tables)
> + return -EINVAL;
> +
> + for (i = 0; tables[i]; i++) {
> + if (crtc_state->port_clock <= tables[i]->clock) {
> + crtc_state->c10mpllb_state = *tables[i];
> + return 0;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +
> +int intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> +
> + return intel_c10mpllb_calc_state(crtc_state, encoder);
> +}
> +
> +void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> + struct intel_c10mpllb_state *pll_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> + u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> + INTEL_CX0_LANE0;
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> + int i;
> + u8 cmn, tx0;
> +
> + /*
> + * According to C10 VDR Register programming Sequence we need
> + * to do this to read PHY internal registers from MsgBus.
> + */
> + intel_cx0_rmw(i915, encoder->port, lane, PHY_C10_VDR_CONTROL(1), 0,
> + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
> +
> + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> + pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane,
> + PHY_C10_VDR_PLL(i));
> +
> + cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0));
> + tx0 = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0));
> +
> + if (tx0 != C10_TX0_VAL || cmn != C10_CMN0_DP_VAL)
> + drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
> + tx0, cmn, phy_name(phy));
> +}
> +
> +static void intel_c10_pll_program(struct drm_i915_private *i915,
> + const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + const struct intel_c10mpllb_state *pll_state = &crtc_state->c10mpllb_state;
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> + u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
> + INTEL_CX0_LANE0;
> + u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
> + INTEL_CX0_LANE1;
> +
> + int i;
> + struct intel_dp *intel_dp;
> + bool use_ssc = false;
> + u8 cmn0 = 0;
> +
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> + intel_dp = enc_to_intel_dp(encoder);
> + use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> + DP_MAX_DOWNSPREAD_0_5);
> +
> + if (!intel_panel_use_ssc(i915))
> + use_ssc = false;
> +
> + cmn0 = C10_CMN0_DP_VAL;
> + }
> +
> + intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
> + /* Custom width needs to be programmed to 0 for both the phy lanes */
> + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> + PHY_C10_VDR_CUSTOM_WIDTH, 0x3, 0, MB_WRITE_COMMITTED);
> + intel_cx0_rmw(i915, encoder->port, follower_lane, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MASTER_LANE, C10_VDR_CTRL_UPDATE_CFG,
> + MB_WRITE_COMMITTED);
> +
> + /* Program the pll values only for the master lane */
> + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> + /* If not using ssc pll[4] through pll[8] must be 0*/
> + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_PLL(i),
> + (!use_ssc && (i > 3 && i < 9)) ? 0 : pll_state->pll[i],
> + (i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED);
> +
> + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CMN(0), cmn0,
> MB_WRITE_COMMITTED);
> + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_TX(0), C10_TX0_VAL,
> MB_WRITE_COMMITTED);
> + intel_cx0_rmw(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MASTER_LANE |
> + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> +}
> +
> +void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv,
> + const struct intel_c10mpllb_state *hw_state)
> +{
> + bool fracen;
> + int i;
> + unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> + unsigned int multiplier, tx_clk_div;
> +
> + fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
> + drm_dbg_kms(&dev_priv->drm, "c10pll_hw_state: fracen: %s, ",
> + str_yes_no(fracen));
> +
> + if (fracen) {
> + frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
> + frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13];
> + frac_den = hw_state->pll[10] << 8 | hw_state->pll[9];
> + drm_dbg_kms(&dev_priv->drm, "quot: %u, rem: %u, den: %u,\n",
> + frac_quot, frac_rem, frac_den);
> + }
> +
> + multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |
> + hw_state->pll[2]) / 2 + 16;
> + tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);
> + drm_dbg_kms(&dev_priv->drm,
> + "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
> +
> + drm_dbg_kms(&dev_priv->drm, "c10pll_rawhw_state:");
> +
> + for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
> + drm_dbg_kms(&dev_priv->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x,
> pll[%d] = 0x%x\n",
> + i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
> + i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
> +}
> +
> +int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
> + const struct intel_c10mpllb_state *pll_state)
> +{
> + unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> + unsigned int multiplier, tx_clk_div, refclk = 38400;
> +
> + if (pll_state->pll[0] & C10_PLL0_FRACEN) {
> + frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
> + frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
> + frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
> + }
> +
> + multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
> + pll_state->pll[2]) / 2 + 16;
> +
> + tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
> +
> + return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
> + DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
> + 10 << (tx_clk_div + 16));
> +}
> +
> +static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + bool lane_reversal)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_dp *intel_dp;
> + bool ssc_enabled;
> + u32 val = 0;
> +
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL,
> + lane_reversal ? XELPDP_PORT_REVERSAL : 0);
> +
> + if (lane_reversal)
> + val |= XELPDP_LANE1_PHY_CLOCK_SELECT;
> +
> + val |= XELPDP_FORWARD_CLOCK_UNGATE;
> + val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
> +
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> + intel_dp = enc_to_intel_dp(encoder);
> + ssc_enabled = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> + DP_MAX_DOWNSPREAD_0_5;
> +
> + if (!intel_panel_use_ssc(i915))
> + ssc_enabled = false;
> +
> + /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
> + val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> + }
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + XELPDP_LANE1_PHY_CLOCK_SELECT |
> + XELPDP_FORWARD_CLOCK_UNGATE |
> + XELPDP_DDI_CLOCK_SELECT_MASK |
> + XELPDP_SSC_ENABLE_PLLB, val);
> +}
> +
> +static u32 intel_cx0_get_powerdown_update(u8 lane)
> +{
> + if (lane == INTEL_CX0_LANE0)
> + return XELPDP_LANE0_POWERDOWN_UPDATE;
> + else if (lane == INTEL_CX0_LANE1)
> + return XELPDP_LANE1_POWERDOWN_UPDATE;
> + else
> + return XELPDP_LANE0_POWERDOWN_UPDATE |
> + XELPDP_LANE1_POWERDOWN_UPDATE;
> +}
> +
> +static u32 intel_cx0_get_powerdown_state(u8 lane, u8 state)
> +{
> + if (lane == INTEL_CX0_LANE0)
> + return XELPDP_LANE0_POWERDOWN_NEW_STATE(state);
> + else if (lane == INTEL_CX0_LANE1)
> + return XELPDP_LANE1_POWERDOWN_NEW_STATE(state);
> + else
> + return XELPDP_LANE0_POWERDOWN_NEW_STATE(state) |
> + XELPDP_LANE1_POWERDOWN_NEW_STATE(state);
> +}
> +
> +static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
> + enum port port,
> + u8 lane, u8 state)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> +
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK |
> XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK,
> + intel_cx0_get_powerdown_state(lane, state));
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_LANE0_POWERDOWN_UPDATE | XELPDP_LANE1_POWERDOWN_UPDATE,
> + intel_cx0_get_powerdown_update(lane));
> +
> + /* Update Timeout Value */
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> + intel_cx0_get_powerdown_update(lane), 0,
> + XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
> + drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
> + phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
> +}
> +
> +static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port)
> +{
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_POWER_STATE_READY_MASK,
> + XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port),
> + XELPDP_POWER_STATE_ACTIVE_MASK |
> + XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
> + XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
> + XELPDP_PLL_LANE_STAGGERING_DELAY(0));
> +}
> +
> +static u32 intel_cx0_get_pclk_refclk_request(u8 lane)
> +{
> + if (lane == INTEL_CX0_LANE0)
> + return XELPDP_LANE0_PCLK_REFCLK_REQUEST;
> + else if (lane == INTEL_CX0_LANE1)
> + return XELPDP_LANE1_PCLK_REFCLK_REQUEST;
> + else
> + return XELPDP_LANE0_PCLK_REFCLK_REQUEST |
> + XELPDP_LANE1_PCLK_REFCLK_REQUEST;
> +}
> +
> +static u32 intel_cx0_get_pclk_refclk_ack(u8 lane)
> +{
> + if (lane == INTEL_CX0_LANE0)
> + return XELPDP_LANE0_PCLK_REFCLK_ACK;
> + else if (lane == INTEL_CX0_LANE1)
> + return XELPDP_LANE1_PCLK_REFCLK_ACK;
> + else
> + return XELPDP_LANE0_PCLK_REFCLK_ACK |
> + XELPDP_LANE1_PCLK_REFCLK_ACK;
> +}
> +
> +/* FIXME: Some Type-C cases need not reset both the lanes. Handle those cases. */
> +static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, enum port port,
> + bool lane_reversal)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> + u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> + INTEL_CX0_LANE0;
> +
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
> + XELPDP_PORT_BUF_SOC_PHY_READY,
> + XELPDP_PORT_BUF_SOC_PHY_READY,
> + XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
> + drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
> + phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
> +
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET,
> + XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET);
> +
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_LANE0_PHY_CURRENT_STATUS |
> XELPDP_LANE1_PHY_CURRENT_STATUS,
> + XELPDP_LANE0_PHY_CURRENT_STATUS |
> XELPDP_LANE1_PHY_CURRENT_STATUS,
> + XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
> + drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
> + phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
> +
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
> + intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES),
> + intel_cx0_get_pclk_refclk_request(lane));
> +
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
> + intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES),
> + intel_cx0_get_pclk_refclk_ack(lane),
> + XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
> + drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
> + phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US);
> +
> + intel_cx0_powerdown_change_sequence(i915, port, INTEL_CX0_BOTH_LANES,
> + CX0_P2_STATE_RESET);
> + intel_cx0_setup_powerdown(i915, port);
> +
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET, 0);
> +
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_LANE0_PHY_CURRENT_STATUS |
> + XELPDP_LANE1_PHY_CURRENT_STATUS,
> + XELPDP_PORT_RESET_END_TIMEOUT))
> + drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
> + phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
> +}
> +
> +static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
> + struct intel_encoder *encoder, int lane_count,
> + bool lane_reversal)
> +{
> + u8 l0t1, l0t2, l1t1, l1t2;
> + bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
> + enum port port = encoder->port;
> +
> + intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MSGBUS_ACCESS,
> + MB_WRITE_COMMITTED);
> +
> + l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
> + l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
> + l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2));
> + l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2));
> +
> + if (lane_reversal) {
> + switch (lane_count) {
> + case 1:
> + /* Disable MLs 1(lane0), 2(lane0), 3(lane1) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
> + l1t1 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + fallthrough;
> + case 2:
> + /* Disable MLs 1(lane0), 2(lane0) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
> + l0t2 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + fallthrough;
> + case 3:
> + /* Disable MLs 1(lane0) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
> + l0t1 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + break;
> + }
> + } else {
> + switch (lane_count) {
> + case 1:
> + if (dp_alt_mode) {
> + /* Disable MLs 1(lane0), 3(lane1), 4(lane1) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1,
> 2),
> + l0t1 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + } else {
> + /* Disable MLs 2(lane0), 3(lane1), 4(lane1) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2,
> 2),
> + l0t2 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + }
> + fallthrough;
> + case 2:
> + /* Disable MLs 3(lane1), 4(lane1) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
> + l1t1 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + fallthrough;
> + case 3:
> + /* Disable MLs 4(lane1) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
> + l1t2 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + break;
> + }
> + }
> +
> + if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) {
> + intel_cx0_rmw(i915, port, INTEL_CX0_LANE1, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
> + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> + intel_cx0_rmw(i915, port, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
> + C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG,
> MB_WRITE_COMMITTED);
> + }
> +}
> +
> +static u32 intel_cx0_get_pclk_pll_request(u8 lane)
> +{
> + if (lane == INTEL_CX0_LANE0)
> + return XELPDP_LANE0_PCLK_PLL_REQUEST;
> + else if (lane == INTEL_CX0_LANE1)
> + return XELPDP_LANE1_PCLK_PLL_REQUEST;
> + else
> + return XELPDP_LANE0_PCLK_PLL_REQUEST |
> + XELPDP_LANE1_PCLK_PLL_REQUEST;
> +}
> +
> +static u32 intel_cx0_get_pclk_pll_ack(u8 lane)
> +{
> + if (lane == INTEL_CX0_LANE0)
> + return XELPDP_LANE0_PCLK_PLL_ACK;
> + else if (lane == INTEL_CX0_LANE1)
> + return XELPDP_LANE1_PCLK_PLL_ACK;
> + else
> + return XELPDP_LANE0_PCLK_PLL_ACK |
> + XELPDP_LANE1_PCLK_PLL_ACK;
> +}
> +
> +static void intel_c10pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> + u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
> + INTEL_CX0_LANE0;
> +
> + /*
> + * 1. Program PORT_CLOCK_CTL REGISTER to configure
> + * clock muxes, gating and SSC
> + */
> + intel_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
> +
> + /* 2. Bring PHY out of reset. */
> + intel_cx0_phy_lane_reset(i915, encoder->port, lane_reversal);
> +
> + /*
> + * 3. Change Phy power state to Ready.
> + * TODO: For DP alt mode use only one lane.
> + */
> + intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> + CX0_P2_STATE_READY);
> +
> + /* 4. Program PHY internal PLL internal registers. */
> + intel_c10_pll_program(i915, crtc_state, encoder);
> +
> + /*
> + * 5. Program the enabled and disabled owned PHY lane
> + * transmitters over message bus
> + */
> + intel_c10_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
> +
> + /*
> + * 6. Follow the Display Voltage Frequency Switching - Sequence
> + * Before Frequency Change. We handle this step in bxt_set_cdclk().
> + */
> +
> + /*
> + * 7. Program DDI_CLK_VALFREQ to match intended DDI
> + * clock frequency.
> + */
> + intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
> + crtc_state->port_clock);
> + /*
> + * 8. Set PORT_CLOCK_CTL register PCLK PLL Request
> + * LN<Lane for maxPCLK> to "1" to enable PLL.
> + */
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
> + intel_cx0_get_pclk_pll_request(maxpclk_lane));
> +
> + /* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
> + intel_cx0_get_pclk_pll_ack(maxpclk_lane),
> + XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
> + drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n",
> + phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US);
> +
> + /*
> + * 10. Follow the Display Voltage Frequency Switching Sequence After
> + * Frequency Change. We handle this step in bxt_set_cdclk().
> + */
> +}
> +
> +void intel_cx0pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> + intel_c10pll_enable(encoder, crtc_state);
> +}
> +
> +static void intel_c10pll_disable(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + /* 1. Change owned PHY lane power to Disable state. */
> + intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> + CX0_P2PG_STATE_DISABLE);
> +
> + /*
> + * 2. Follow the Display Voltage Frequency Switching Sequence Before
> + * Frequency Change. We handle this step in bxt_set_cdclk().
> + */
> +
> + /*
> + * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
> + * to "0" to disable PLL.
> + */
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
> + intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
> +
> + /* 4. Program DDI_CLK_VALFREQ to 0. */
> + intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
> +
> + /*
> + * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
> + */
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
> + intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
> + XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
> + drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n",
> + phy_name(phy), XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US);
> +
> + /*
> + * 6. Follow the Display Voltage Frequency Switching Sequence After
> + * Frequency Change. We handle this step in bxt_set_cdclk().
> + */
> +
> + /* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + XELPDP_DDI_CLOCK_SELECT_MASK |
> + XELPDP_FORWARD_CLOCK_UNGATE, 0);
> +}
> +
> +void intel_cx0pll_disable(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> + intel_c10pll_disable(encoder);
> +}
> +
> +void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
> + struct intel_crtc_state *new_crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_c10mpllb_state mpllb_hw_state = { 0 };
> + struct intel_c10mpllb_state *mpllb_sw_state = &new_crtc_state->c10mpllb_state;
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + struct intel_encoder *encoder;
> + struct intel_dp *intel_dp;
> + enum phy phy;
> + int i;
> + bool use_ssc = false;
> +
> + if (DISPLAY_VER(i915) < 14)
> + return;
> +
> + if (!new_crtc_state->hw.active)
> + return;
> +
> + encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> + phy = intel_port_to_phy(i915, encoder->port);
> +
> + if (intel_crtc_has_dp_encoder(new_crtc_state)) {
> + intel_dp = enc_to_intel_dp(encoder);
> + use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> + DP_MAX_DOWNSPREAD_0_5);
> +
> + if (!intel_panel_use_ssc(i915))
> + use_ssc = false;
> + }
> +
> + if (!intel_is_c10phy(i915, phy))
> + return;
> +
> + intel_c10mpllb_readout_hw_state(encoder, &mpllb_hw_state);
> +
> + for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {
> + u8 expected;
> +
> + if (!use_ssc && i > 3 && i < 9)
> + expected = 0;
> + else
> + expected = mpllb_sw_state->pll[i];
> +
> + I915_STATE_WARN(mpllb_hw_state.pll[i] != expected,
> + "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x,
> found 0x%02x)",
> + crtc->base.base.id, crtc->base.name,
> + i, expected, mpllb_hw_state.pll[i]);
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> new file mode 100644
> index 000000000000..8cf340509097
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef __INTEL_CX0_PHY_H__
> +#define __INTEL_CX0_PHY_H__
> +
> +#include <linux/types.h>
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +
> +#include "i915_drv.h"
> +#include "intel_display_types.h"
> +
> +struct drm_i915_private;
> +struct intel_encoder;
> +struct intel_crtc_state;
> +enum phy;
> +
> +#define INTEL_CX0_LANE0 0x1
> +#define INTEL_CX0_LANE1 0x2
> +#define INTEL_CX0_BOTH_LANES 0x3
> +
> +#define MB_WRITE_COMMITTED 1
> +#define MB_WRITE_UNCOMMITTED 0
> +
> +bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
> +void intel_cx0pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
> +void intel_cx0pll_disable(struct intel_encoder *encoder);
> +void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> + struct intel_c10mpllb_state *pll_state);
> +int intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder);
> +void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv,
> + const struct intel_c10mpllb_state *hw_state);
> +int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
> + const struct intel_c10mpllb_state *pll_state);
> +void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
> + struct intel_crtc_state *new_crtc_state);
> +
> +#endif /* __INTEL_CX0_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index d1ee8a2fc9cf..15e249f46a64 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -128,4 +128,34 @@
> #define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
> #define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
>
> -#endif /* __INTEL_CX0_PHY_REGS_H__ */
> +/* C10 Vendor Registers */
> +#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
> +#define C10_PLL0_FRACEN REG_BIT8(4)
> +#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
> +#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
> +#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
> +#define C10_CMN0_DP_VAL 0x21
> +#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
> +#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
> +#define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
> +#define C10_TX0_VAL 0x10
> +#define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1)
> +#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2)
> +#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1)
> +#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
> +#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
> +
> +#define CX0_P0_STATE_ACTIVE 0x0
> +#define CX0_P2_STATE_READY 0x2
> +#define CX0_P2PG_STATE_DISABLE 0x9
> +#define CX0_P4PG_STATE_DISABLE 0xC
> +#define CX0_P2_STATE_RESET 0x2
> +
> +/* PHY_C10_VDR_PLL0 */
> +#define PLL_C10_MPLL_SSC_EN REG_BIT8(0)
> +
> +/* PIPE SPEC Defined Registers */
> +#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
> +#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
> +
> +#endif /* __INTEL_CX0_REG_DEFS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 73240cf78c8b..a433dea5b9a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -39,6 +39,7 @@
> #include "intel_combo_phy_regs.h"
> #include "intel_connector.h"
> #include "intel_crtc.h"
> +#include "intel_cx0_phy.h"
> #include "intel_ddi.h"
> #include "intel_ddi_buf_trans.h"
> #include "intel_de.h"
> @@ -3507,6 +3508,21 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
> &crtc_state->dpll_hw_state);
> }
>
> +static void mtl_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> +
> + intel_c10mpllb_readout_hw_state(encoder, &crtc_state->c10mpllb_state);
> + intel_c10mpllb_dump_hw_state(i915, &crtc_state->c10mpllb_state);
> + crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state-
> >c10mpllb_state);
> +
> + intel_ddi_get_config(encoder, crtc_state);
> +}
> +
> static void dg2_ddi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -4413,7 +4429,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> encoder->cloneable = 0;
> encoder->pipe_mask = ~0;
>
> - if (IS_DG2(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + encoder->enable_clock = intel_cx0pll_enable;
> + encoder->disable_clock = intel_cx0pll_disable;
> + encoder->get_config = mtl_ddi_get_config;
> + } else if (IS_DG2(dev_priv)) {
> encoder->enable_clock = intel_mpllb_enable;
> encoder->disable_clock = intel_mpllb_disable;
> encoder->get_config = dg2_ddi_get_config;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index f86060195987..e23fecba446c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1614,7 +1614,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> return;
>
> /* 2. Initialize all combo phys */
> - intel_combo_phy_init(dev_priv);
> + if (DISPLAY_VER(dev_priv) < 14)
> + intel_combo_phy_init(dev_priv);
>
> /*
> * 3. Enable Power Well 1 (PG1).
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 1676df1dc066..a4c8cb75c0a0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -970,7 +970,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> bxt_verify_ddi_phy_power_wells(dev_priv);
>
> - if (DISPLAY_VER(dev_priv) >= 11)
> + if (DISPLAY_VER(dev_priv) >= 11 && DISPLAY_VER(dev_priv) < 14)
> /*
> * DMC retains HW context only for port A, the other combo
> * PHY's HW context for port B is lost after DC transitions,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ab146b5b68bd..db7c108e4d86 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -985,6 +985,11 @@ struct intel_link_m_n {
> u32 link_n;
> };
>
> +struct intel_c10mpllb_state {
> + u32 clock; /* in KHz */
> + u8 pll[20];
> +};
> +
> struct intel_crtc_state {
> /*
> * uapi (drm) state. This is the software state shown to userspace.
> @@ -1128,6 +1133,7 @@ struct intel_crtc_state {
> union {
> struct intel_dpll_hw_state dpll_hw_state;
> struct intel_mpllb_state mpllb_state;
> + struct intel_c10mpllb_state c10mpllb_state;
> };
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 4e9c18be7e1f..da5aa050a5ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -8,6 +8,7 @@
>
> #include "i915_reg.h"
> #include "intel_crtc.h"
> +#include "intel_cx0_phy.h"
> #include "intel_de.h"
> #include "intel_display.h"
> #include "intel_display_types.h"
> @@ -995,6 +996,17 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
> return 0;
> }
>
> +static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + struct intel_encoder *encoder =
> + intel_get_crtc_new_encoder(state, crtc_state);
> +
> + return intel_cx0mpllb_calc_state(crtc_state, encoder);
> +}
> +
> static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
> {
> return dpll->m < factor * dpll->n;
> @@ -1423,6 +1435,10 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
> return 0;
> }
>
> +static const struct intel_dpll_funcs mtl_dpll_funcs = {
> + .crtc_compute_clock = mtl_crtc_compute_clock,
> +};
> +
> static const struct intel_dpll_funcs dg2_dpll_funcs = {
> .crtc_compute_clock = dg2_crtc_compute_clock,
> };
> @@ -1517,7 +1533,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> void
> intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
> {
> - if (IS_DG2(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 14)
> + dev_priv->display.funcs.dpll = &mtl_dpll_funcs;
> + else if (IS_DG2(dev_priv))
> dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
> else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
> dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 22fc908b7e5d..ed372d227aa7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4104,7 +4104,7 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
>
> mutex_init(&dev_priv->display.dpll.lock);
>
> - if (IS_DG2(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv))
> /* No shared DPLLs on DG2; port PLLs are part of the PHY */
> dpll_mgr = NULL;
> else if (IS_ALDERLAKE_P(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> index 842d70f0dfd2..ec504470c2f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> @@ -11,6 +11,7 @@
> #include "intel_atomic.h"
> #include "intel_crtc.h"
> #include "intel_crtc_state_dump.h"
> +#include "intel_cx0_phy.h"
> #include "intel_display.h"
> #include "intel_display_types.h"
> #include "intel_fdi.h"
> @@ -236,6 +237,7 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
> verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
> intel_shared_dpll_state_verify(crtc, old_crtc_state, new_crtc_state);
> intel_mpllb_state_verify(state, new_crtc_state);
> + intel_c10mpllb_state_verify(state, new_crtc_state);
> }
>
> void intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d22ffd7a32dc..94dd0d3a474b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2101,6 +2101,11 @@
> #define TRANS_PUSH_EN REG_BIT(31)
> #define TRANS_PUSH_SEND REG_BIT(30)
>
> +/* DDI Buffer Control */
> +#define _DDI_CLK_VALFREQ_A 0x64030
> +#define _DDI_CLK_VALFREQ_B 0x64130
> +#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
> +
> /*
> * HSW+ eDP PSR registers
> *
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
> index db26de6b57bc..f9d7c03e95d6 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -22,6 +22,19 @@
> BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
> ((__n) < 0 || (__n) > 31))))
>
> +/**
> + * REG_BIT8() - Prepare a u8 bit value
> + * @__n: 0-based bit number
> + *
> + * Local wrapper for BIT() to force u8, with compile time checks.
> + *
> + * @return: Value with bit @__n set.
> + */
> +#define REG_BIT8(__n) \
> + ((u8)(BIT(__n) + \
> + BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
> + ((__n) < 0 || (__n) > 7))))
> +
> /**
> * REG_GENMASK() - Prepare a continuous u32 bitmask
> * @__high: 0-based high bit
> @@ -52,6 +65,21 @@
> __is_constexpr(__low) && \
> ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
>
> +/**
> + * REG_GENMASK8() - Prepare a continuous u8 bitmask
> + * @__high: 0-based high bit
> + * @__low: 0-based low bit
> + *
> + * Local wrapper for GENMASK() to force u8, with compile time checks.
> + *
> + * @return: Continuous bitmask from @__high to @__low, inclusive.
> + */
> +#define REG_GENMASK8(__high, __low) \
> + ((u8)(GENMASK(__high, __low) + \
> + BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
> + __is_constexpr(__low) && \
> + ((__low) < 0 || (__high) > 7 || (__low) > (__high)))))
> +
> /*
> * Local integer constant expression version of is_power_of_2().
> */
> @@ -74,6 +102,23 @@
> BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
> BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >>
> __bf_shf(__mask)) & (__val)), 0))))
>
> +/**
> + * REG_FIELD_PREP8() - Prepare a u8 bitfield value
> + * @__mask: shifted mask defining the field's length and position
> + * @__val: value to put in the field
> + *
> + * Local copy of FIELD_PREP8() to generate an integer constant expression, force
> + * u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8().
> + *
> + * @return: @__val masked and shifted into the field defined by @__mask.
> + */
> +#define REG_FIELD_PREP8(__mask, __val) \
> + ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
> + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
> + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
> + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
> + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >>
> __bf_shf(__mask)) & (__val)), 0))))
> +
> /**
> * REG_FIELD_GET() - Extract a u32 bitfield value
> * @__mask: shifted mask defining the field's length and position
> @@ -155,6 +200,18 @@
> */
> #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
>
> +/**
> + * REG_FIELD_GET8() - Extract a u8 bitfield value
> + * @__mask: shifted mask defining the field's length and position
> + * @__val: value to extract the bitfield value from
> + *
> + * Local wrapper for FIELD_GET() to force u8 and for consistency with
> + * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
> + *
> + * @return: Masked and shifted value of the field defined by @__mask in @__val.
> + */
> +#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))
> +
> typedef struct {
> u32 reg;
> } i915_reg_t;
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-03-27 12:34 ` [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming Mika Kahola
2023-03-29 10:22 ` Govindapillai, Vinod
@ 2023-03-29 15:40 ` Imre Deak
2023-03-29 15:59 ` Imre Deak
2023-04-04 10:43 ` Kahola, Mika
2023-04-03 10:11 ` Imre Deak
2 siblings, 2 replies; 37+ messages in thread
From: Imre Deak @ 2023-03-29 15:40 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
On Mon, Mar 27, 2023 at 03:34:30PM +0300, Mika Kahola wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
> has a dedicated PIPE 5.2 Message bus for configuration. This message
> bus is used to configure the phy internal registers.
>
> XELPDP has C10 phys to drive output to the EDP and the native output
> from the display engine. Add structures, programming hardware state
> readout logic. Port clock calculations are similar to DG2. Use the DG2
> formulae to calculate the port clock but use the relevant pll signals.
> Note: PHY lane 0 is always used for PLL programming.
>
> Add sequences for C10 phy enable/disable phy lane reset,
> powerdown change sequence and phy lane programming.
>
> Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
>
> v2: Squash patches related to C10 phy message bus and pll
> programming support (Jani)
> Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
> Move macro definitions (Jani)
> DP rates as separate patch (Jani)
> Spin out xelpdp register definitions into a separate file (Jani)
> Replace macro to select registers based on phy lane with
> function calls (Jani)
> Fix styling issues (Jani)
> Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
> v3: Move clear request flag into try-loop
> v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani)
> use __intel_de_wait_for_register() instead of __intel_wait_for_register
> and uncomment intel_uncore.h (Jani)
> Add DP-alt support for PHY lane programming (Khaled)
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1120 +++++++++++++++++
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 43 +
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 32 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 22 +-
> .../drm/i915/display/intel_display_power.c | 3 +-
> .../i915/display/intel_display_power_well.c | 2 +-
> .../drm/i915/display/intel_display_types.h | 6 +
> drivers/gpu/drm/i915/display/intel_dpll.c | 20 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
> .../drm/i915/display/intel_modeset_verify.c | 2 +
> drivers/gpu/drm/i915/i915_reg.h | 5 +
> drivers/gpu/drm/i915/i915_reg_defs.h | 57 +
> 13 files changed, 1309 insertions(+), 6 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 057ef22fa9c6..57b1417792b4 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -298,6 +298,7 @@ i915-y += \
> display/icl_dsi.o \
> display/intel_backlight.o \
> display/intel_crt.o \
> + display/intel_cx0_phy.o \
> display/intel_ddi.o \
> display/intel_ddi_buf_trans.o \
> display/intel_display_trace.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> new file mode 100644
> index 000000000000..ced8c8aa6c82
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -0,0 +1,1120 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#include "i915_reg.h"
> +#include "intel_cx0_phy.h"
> +#include "intel_cx0_phy_regs.h"
> +#include "intel_de.h"
> +#include "intel_display_types.h"
> +#include "intel_dp.h"
> +#include "intel_panel.h"
> +#include "intel_tc.h"
> +
> +bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
> +{
> + if (IS_METEORLAKE(dev_priv) && (phy < PHY_C))
> + return true;
> +
> + return false;
> +}
> +
> +static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, int lane)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> +
> + /* Bring the phy to idle. */
> + intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
For the above and every other place taking a lane mask parameter or
converting the lane mask to a lane:
I think the function parameter should be an 'u8 lane_mask' for clarity
and instead of open-coding the conversion should be done by a
lane_mask_to_lane() helper which also sanity checks lane_mask (that it's
either INTEL_CX0_LANE0 or INTEL_CX0_LANE1, but not both).
> + XELPDP_PORT_M2P_TRANSACTION_RESET);
> +
> + /* Wait for Idle Clear. */
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> + XELPDP_PORT_M2P_TRANSACTION_RESET,
> + XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> + drm_dbg_kms(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
> + return;
> + }
> +
> + intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1), ~0);
The above should write only the XELPDP_PORT_P2M_RESPONSE_READY and
XELPDP_PORT_P2M_ERROR_SET flags to get those cleared.
Could factor out a function for it since the same is also used later.
> +}
> +
> +static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port, int lane, u32 *val)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> +
> + if (__intel_de_wait_for_register(i915,
> + XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1),
As above this function should take the 0-based lane value.
> + XELPDP_PORT_P2M_RESPONSE_READY,
> + XELPDP_PORT_P2M_RESPONSE_READY,
> + XELPDP_MSGBUS_TIMEOUT_FAST_US,
> + XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
> + drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", phy_name(phy), *val);
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +static int __intel_cx0_read(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr, u32 *val)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> + int ack;
> +
> + /* Wait for pending transactions.*/
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> + XELPDP_PORT_M2P_TRANSACTION_PENDING,
> + XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> + drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
> + intel_cx0_bus_reset(i915, port, lane);
Does bspec describe somewhere that this reset is needed?
> + return -ETIMEDOUT;
> + }
> +
> + /* Issue the read command. */
> + intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> + XELPDP_PORT_M2P_TRANSACTION_PENDING |
> + XELPDP_PORT_M2P_COMMAND_READ |
> + XELPDP_PORT_M2P_ADDRESS(addr));
> +
> + /* Wait for response ready. And read response.*/
> + ack = intel_cx0_wait_for_ack(i915, port, lane, val);
> + if (ack < 0) {
> + intel_cx0_bus_reset(i915, port, lane);
> + return ack;
> + }
> +
> + /* Check for error. */
> + if (*val & XELPDP_PORT_P2M_ERROR_SET) {
> + drm_dbg_kms(&i915->drm, "PHY %c Error occurred during read command. Status: 0x%x\n", phy_name(phy), *val);
> + intel_cx0_bus_reset(i915, port, lane);
> + return -EINVAL;
> + }
> +
> + /* Check for Read Ack. */
> + if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) !=
> + XELPDP_PORT_P2M_COMMAND_READ_ACK) {
> + drm_dbg_kms(&i915->drm, "PHY %c Not a Read response. MSGBUS Status: 0x%x.\n", phy_name(phy), *val);
> + intel_cx0_bus_reset(i915, port, lane);
> + return -EINVAL;
> + }
> +
> + /* Clear Response Ready flag.*/
> + intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1), ~0);
Could use a helper for the above.
> +
> + return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, *val);
> +}
> +
> +static u8 intel_cx0_read(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> + int i, status = 0;
> + u32 val;
> +
> + for (i = 0; i < 3; i++) {
Please add a comment why this retries 3 times, doesn't seem to be
described by the spec.
> + status = __intel_cx0_read(i915, port, lane, addr, &val);
val could be removed as it's not used, and remove the last param from
__intel_cx0_read() accordingly.
> +
> + if (status >= 0)
> + break;
Returning status here would simplify the code below.
> + }
> +
> + if (i == 3) {
> + drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n", phy_name(phy), addr, i);
> + return 0;
> + }
> +
> + return status;
> +}
> +
> +static int intel_cx0_wait_cwrite_ack(struct drm_i915_private *i915,
> + enum port port, int lane)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> + int ack;
> + u32 val = 0;
> +
> + /* Check for write ack. */
> + ack = intel_cx0_wait_for_ack(i915, port, lane, &val);
> + if (ack < 0)
> + return ack;
> +
> + if ((REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, val) !=
> + XELPDP_PORT_P2M_COMMAND_WRITE_ACK) || val & XELPDP_PORT_P2M_ERROR_SET) {
> + drm_dbg_kms(&i915->drm, "PHY %c Unexpected ACK received. MSGBUS STATUS: 0x%x.\n", phy_name(phy), val);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr, u8 data, bool committed)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> +
> + /* Wait for pending transactions.*/
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> + XELPDP_PORT_M2P_TRANSACTION_PENDING,
> + XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> + drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
> + intel_cx0_bus_reset(i915, port, lane);
> + return -ETIMEDOUT;
> + }
> +
> + /* Issue the write command. */
> + intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> + XELPDP_PORT_M2P_TRANSACTION_PENDING |
> + (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
> + XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
Could better indent the above line for clarity.
> + XELPDP_PORT_M2P_DATA(data) |
> + XELPDP_PORT_M2P_ADDRESS(addr));
> +
The spec requires to wait here MSGBUS_CTL / XELPDP_PORT_M2P_TRANSACTION_PENDING
to clear (for both commited/uncommited writes).
> + /* Check for error. */
> + if (committed) {
> + if (intel_cx0_wait_cwrite_ack(i915, port, lane) < 0) {
> + intel_cx0_bus_reset(i915, port, lane);
> + return -EINVAL;
> + }
> + } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1)) &
> + XELPDP_PORT_P2M_ERROR_SET)) {
> + drm_dbg_kms(&i915->drm, "PHY %c Error occurred during write command.\n", phy_name(phy));
> + intel_cx0_bus_reset(i915, port, lane);
> + return -EINVAL;
> + }
> +
> + intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1), ~0);
Could use a helper for the above.
> +
> + return 0;
> +}
> +
> +static void __intel_cx0_write(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr, u8 data, bool committed)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> + int i, status;
> +
> + for (i = 0; i < 3; i++) {
> + status = __intel_cx0_write_once(i915, port, lane, addr, data, committed);
> +
> + if (status == 0)
> + break;
Could simplify by the code below by returning here.
> + }
> +
> + if (i == 3) {
> + drm_err_once(&i915->drm, "PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
> + return;
> + }
> +}
> +
> +static void intel_cx0_write(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr, u8 data, bool committed)
> +{
> + if (lane == INTEL_CX0_BOTH_LANES) {
> + __intel_cx0_write(i915, port, INTEL_CX0_LANE0, addr, data, committed);
> + __intel_cx0_write(i915, port, INTEL_CX0_LANE1, addr, data, committed);
> + } else {
> + __intel_cx0_write(i915, port, lane, addr, data, committed);
Could add a helper and simplify the above by
for_each_cx0_lane_in_mask(lane, lane_mask)
__intel_cx0_write(i915, port, lane, addr, data, committed);
> + }
> +}
> +
> +static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr, u8 clear, u8 set, bool committed)
> +{
> + u8 old, val;
> +
> + old = intel_cx0_read(i915, port, lane, addr);
> + val = (old & ~clear) | set;
> +
> + if (val != old)
> + intel_cx0_write(i915, port, lane, addr, val, committed);
> +}
> +
> +static void intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> + int lane, u16 addr, u8 clear, u8 set, bool committed)
> +{
> + if (lane == INTEL_CX0_BOTH_LANES) {
> + __intel_cx0_rmw(i915, port, INTEL_CX0_LANE0, addr, clear, set, committed);
> + __intel_cx0_rmw(i915, port, INTEL_CX0_LANE1, addr, clear, set, committed);
> + } else {
> + __intel_cx0_rmw(i915, port, lane, addr, clear, set, committed);
> + }
Could use a for_each_cx0_lane_in_mask() helper here too.
> +}
> +
> +/*
> + * Basic DP link rates with 38.4 MHz reference clock.
> + * Note: The tables below are with SSC. In non-ssc
> + * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
> + * programmed 0.
> + */
> +
> +static const struct intel_c10mpllb_state mtl_c10_dp_rbr = {
> + .clock = 162000,
> + .pll[0] = 0xB4,
> + .pll[1] = 0,
> + .pll[2] = 0x30,
> + .pll[3] = 0x1,
> + .pll[4] = 0x26,
> + .pll[5] = 0x0C,
> + .pll[6] = 0x98,
> + .pll[7] = 0x46,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0xC0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0x2,
> + .pll[16] = 0x84,
> + .pll[17] = 0x4F,
> + .pll[18] = 0xE5,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_edp_r216 = {
> + .clock = 216000,
> + .pll[0] = 0x4,
> + .pll[1] = 0,
> + .pll[2] = 0xA2,
> + .pll[3] = 0x1,
> + .pll[4] = 0x33,
> + .pll[5] = 0x10,
> + .pll[6] = 0x75,
> + .pll[7] = 0xB3,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0x2,
> + .pll[16] = 0x85,
> + .pll[17] = 0x0F,
> + .pll[18] = 0xE6,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_edp_r243 = {
> + .clock = 243000,
> + .pll[0] = 0x34,
> + .pll[1] = 0,
> + .pll[2] = 0xDA,
> + .pll[3] = 0x1,
> + .pll[4] = 0x39,
> + .pll[5] = 0x12,
> + .pll[6] = 0xE3,
> + .pll[7] = 0xE9,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0x20,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0x2,
> + .pll[16] = 0x85,
> + .pll[17] = 0x8F,
> + .pll[18] = 0xE6,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_dp_hbr1 = {
> + .clock = 270000,
> + .pll[0] = 0xF4,
> + .pll[1] = 0,
> + .pll[2] = 0xF8,
> + .pll[3] = 0x0,
> + .pll[4] = 0x20,
> + .pll[5] = 0x0A,
> + .pll[6] = 0x29,
> + .pll[7] = 0x10,
> + .pll[8] = 0x1, /* Verify */
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0xA0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0x1,
> + .pll[16] = 0x84,
> + .pll[17] = 0x4F,
> + .pll[18] = 0xE5,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_edp_r324 = {
> + .clock = 324000,
> + .pll[0] = 0xB4,
> + .pll[1] = 0,
> + .pll[2] = 0x30,
> + .pll[3] = 0x1,
> + .pll[4] = 0x26,
> + .pll[5] = 0x0C,
> + .pll[6] = 0x98,
> + .pll[7] = 0x46,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0xC0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0x1,
> + .pll[16] = 0x85,
> + .pll[17] = 0x4F,
> + .pll[18] = 0xE6,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_edp_r432 = {
> + .clock = 432000,
> + .pll[0] = 0x4,
> + .pll[1] = 0,
> + .pll[2] = 0xA2,
> + .pll[3] = 0x1,
> + .pll[4] = 0x33,
> + .pll[5] = 0x10,
> + .pll[6] = 0x75,
> + .pll[7] = 0xB3,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0x1,
> + .pll[16] = 0x85,
> + .pll[17] = 0x0F,
> + .pll[18] = 0xE6,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_dp_hbr2 = {
> + .clock = 540000,
> + .pll[0] = 0xF4,
> + .pll[1] = 0,
> + .pll[2] = 0xF8,
> + .pll[3] = 0,
> + .pll[4] = 0x20,
> + .pll[5] = 0x0A,
> + .pll[6] = 0x29,
> + .pll[7] = 0x10,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0xA0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0,
> + .pll[16] = 0x84,
> + .pll[17] = 0x4F,
> + .pll[18] = 0xE5,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_edp_r675 = {
> + .clock = 675000,
> + .pll[0] = 0xB4,
> + .pll[1] = 0,
> + .pll[2] = 0x3E,
> + .pll[3] = 0x1,
> + .pll[4] = 0xA8,
> + .pll[5] = 0x0C,
> + .pll[6] = 0x33,
> + .pll[7] = 0x54,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0xC8,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0,
> + .pll[16] = 0x85,
> + .pll[17] = 0x8F,
> + .pll[18] = 0xE6,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_dp_hbr3 = {
> + .clock = 810000,
> + .pll[0] = 0x34,
> + .pll[1] = 0,
> + .pll[2] = 0x84,
> + .pll[3] = 0x1,
> + .pll[4] = 0x30,
> + .pll[5] = 0x0F,
> + .pll[6] = 0x3D,
> + .pll[7] = 0x98,
> + .pll[8] = 0x1,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0xF0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0,
> + .pll[16] = 0x84,
> + .pll[17] = 0x0F,
> + .pll[18] = 0xE5,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state * const mtl_c10_dp_tables[] = {
> + &mtl_c10_dp_rbr,
> + &mtl_c10_dp_hbr1,
> + &mtl_c10_dp_hbr2,
> + &mtl_c10_dp_hbr3,
> + NULL,
> +};
> +
> +static const struct intel_c10mpllb_state * const mtl_c10_edp_tables[] = {
> + &mtl_c10_dp_rbr,
> + &mtl_c10_edp_r216,
> + &mtl_c10_edp_r243,
> + &mtl_c10_dp_hbr1,
> + &mtl_c10_edp_r324,
> + &mtl_c10_edp_r432,
> + &mtl_c10_dp_hbr2,
> + &mtl_c10_edp_r675,
> + &mtl_c10_dp_hbr3,
> + NULL,
> +};
> +
> +static const struct intel_c10mpllb_state * const *
> +intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> + return mtl_c10_edp_tables;
> + else
> + return mtl_c10_dp_tables;
> + }
> +
> + /* TODO: Add HDMI Support */
> + MISSING_CASE(encoder->type);
> + return NULL;
> +}
> +
> +static int intel_c10mpllb_calc_state(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + const struct intel_c10mpllb_state * const *tables;
> + int i;
> +
> + tables = intel_c10_mpllb_tables_get(crtc_state, encoder);
> + if (!tables)
> + return -EINVAL;
> +
> + for (i = 0; tables[i]; i++) {
> + if (crtc_state->port_clock <= tables[i]->clock) {
Not sure how an inaccurate PLL clock would work, shouldn't the above
accept only a matching clock?
> + crtc_state->c10mpllb_state = *tables[i];
> + return 0;
> + }
> + }
> +
> + return -EINVAL;
> +}
> +
> +int intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> +
> + return intel_c10mpllb_calc_state(crtc_state, encoder);
> +}
> +
> +void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> + struct intel_c10mpllb_state *pll_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> + u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> + INTEL_CX0_LANE0;
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> + int i;
> + u8 cmn, tx0;
> +
> + /*
> + * According to C10 VDR Register programming Sequence we need
> + * to do this to read PHY internal registers from MsgBus.
> + */
> + intel_cx0_rmw(i915, encoder->port, lane, PHY_C10_VDR_CONTROL(1), 0,
> + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
> +
> + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> + pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane,
> + PHY_C10_VDR_PLL(i));
> +
> + cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0));
> + tx0 = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0));
The driver programs these registers, so why aren't they also stored in
the intell_c20pll_state struct?
> +
> + if (tx0 != C10_TX0_VAL || cmn != C10_CMN0_DP_VAL)
> + drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
> + tx0, cmn, phy_name(phy));
Shouldn't PHY_C10_VDR_CONTROL(1)/C10_VDR_CTRL_MSGBUS_ACCESS be cleared
here?
> +}
> +
> +static void intel_c10_pll_program(struct drm_i915_private *i915,
> + const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + const struct intel_c10mpllb_state *pll_state = &crtc_state->c10mpllb_state;
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> + u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
> + INTEL_CX0_LANE0;
> + u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
> + INTEL_CX0_LANE1;
> +
> + int i;
> + struct intel_dp *intel_dp;
> + bool use_ssc = false;
> + u8 cmn0 = 0;
> +
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> + intel_dp = enc_to_intel_dp(encoder);
> + use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> + DP_MAX_DOWNSPREAD_0_5);
> +
> + if (!intel_panel_use_ssc(i915))
> + use_ssc = false;
> +
> + cmn0 = C10_CMN0_DP_VAL;
Would be clearer by stg like:
/* Using x MHz reference */
cmn0 = C10_CMN0_REF_RANGE(1) | C10_CMN0_REF_CLK_MPLLB_DIV(2);
> + }
> +
> + intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
For DP-alt MFD the PHY lane not owned by display shouldn't be
programmed, no?
> + /* Custom width needs to be programmed to 0 for both the phy lanes */
> + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> + PHY_C10_VDR_CUSTOM_WIDTH, 0x3, 0, MB_WRITE_COMMITTED);
The above hard-coded values should have a macro definiton.
> + intel_cx0_rmw(i915, encoder->port, follower_lane, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MASTER_LANE, C10_VDR_CTRL_UPDATE_CFG,
> + MB_WRITE_COMMITTED);
> +
> + /* Program the pll values only for the master lane */
> + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> + /* If not using ssc pll[4] through pll[8] must be 0*/
> + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_PLL(i),
> + (!use_ssc && (i > 3 && i < 9)) ? 0 : pll_state->pll[i],
pll_state->pll should be setup already intel_c10mpllb_calc_state()
taking into account SSC as well.
> + (i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED);
> +
> + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
> + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_TX(0), C10_TX0_VAL, MB_WRITE_COMMITTED);
Instead of C10_TX0_VAL the flags programmed should be better described
here as cmn0 above.
> + intel_cx0_rmw(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MASTER_LANE |
> + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> +}
> +
> +void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv,
> + const struct intel_c10mpllb_state *hw_state)
> +{
> + bool fracen;
> + int i;
> + unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> + unsigned int multiplier, tx_clk_div;
> +
> + fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
> + drm_dbg_kms(&dev_priv->drm, "c10pll_hw_state: fracen: %s, ",
> + str_yes_no(fracen));
> +
> + if (fracen) {
> + frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
> + frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13];
> + frac_den = hw_state->pll[10] << 8 | hw_state->pll[9];
> + drm_dbg_kms(&dev_priv->drm, "quot: %u, rem: %u, den: %u,\n",
> + frac_quot, frac_rem, frac_den);
> + }
> +
> + multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |
> + hw_state->pll[2]) / 2 + 16;
> + tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);
> + drm_dbg_kms(&dev_priv->drm,
> + "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
> +
> + drm_dbg_kms(&dev_priv->drm, "c10pll_rawhw_state:");
> +
> + for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
> + drm_dbg_kms(&dev_priv->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
> + i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
> + i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
> +}
> +
> +int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
> + const struct intel_c10mpllb_state *pll_state)
> +{
> + unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> + unsigned int multiplier, tx_clk_div, refclk = 38400;
> +
> + if (pll_state->pll[0] & C10_PLL0_FRACEN) {
> + frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
> + frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
> + frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
> + }
> +
> + multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
> + pll_state->pll[2]) / 2 + 16;
> +
> + tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
> +
> + return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
> + DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
> + 10 << (tx_clk_div + 16));
> +}
> +
> +static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + bool lane_reversal)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_dp *intel_dp;
> + bool ssc_enabled;
> + u32 val = 0;
> +
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL,
> + lane_reversal ? XELPDP_PORT_REVERSAL : 0);
> +
> + if (lane_reversal)
> + val |= XELPDP_LANE1_PHY_CLOCK_SELECT;
> +
> + val |= XELPDP_FORWARD_CLOCK_UNGATE;
> + val |= XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
TODO: HDMI FRL?
> +
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> + intel_dp = enc_to_intel_dp(encoder);
> + ssc_enabled = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> + DP_MAX_DOWNSPREAD_0_5;
> +
> + if (!intel_panel_use_ssc(i915))
> + ssc_enabled = false;
> +
> + /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
> + val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> + }
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + XELPDP_LANE1_PHY_CLOCK_SELECT |
> + XELPDP_FORWARD_CLOCK_UNGATE |
> + XELPDP_DDI_CLOCK_SELECT_MASK |
> + XELPDP_SSC_ENABLE_PLLB, val);
> +}
> +
> +static u32 intel_cx0_get_powerdown_update(u8 lane)
> +{
> + if (lane == INTEL_CX0_LANE0)
> + return XELPDP_LANE0_POWERDOWN_UPDATE;
> + else if (lane == INTEL_CX0_LANE1)
> + return XELPDP_LANE1_POWERDOWN_UPDATE;
> + else
> + return XELPDP_LANE0_POWERDOWN_UPDATE |
> + XELPDP_LANE1_POWERDOWN_UPDATE;
Could simplify by
val = 0;
for_each_cx0_lane_in_mask(lane, lane_mask)
val |= XELPDP_LANE_POWERDOWN_UPDATE(lane);
> +}
> +
> +static u32 intel_cx0_get_powerdown_state(u8 lane, u8 state)
> +{
> + if (lane == INTEL_CX0_LANE0)
> + return XELPDP_LANE0_POWERDOWN_NEW_STATE(state);
> + else if (lane == INTEL_CX0_LANE1)
> + return XELPDP_LANE1_POWERDOWN_NEW_STATE(state);
> + else
> + return XELPDP_LANE0_POWERDOWN_NEW_STATE(state) |
> + XELPDP_LANE1_POWERDOWN_NEW_STATE(state);
Could simplify similarly to the above.
> +}
> +
> +static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
> + enum port port,
> + u8 lane, u8 state)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> +
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK | XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK,
> + intel_cx0_get_powerdown_state(lane, state));
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_LANE0_POWERDOWN_UPDATE | XELPDP_LANE1_POWERDOWN_UPDATE,
> + intel_cx0_get_powerdown_update(lane));
The spec says (65451):
"Only update powerdown for one port at a time. Wait for powerdown
update to finish for one port before initiating update on another port."
both could be updated at the same time if a non-zero stagger delay was
programmed, but for C10/C20 it must be programmed as 0.
> +
> + /* Update Timeout Value */
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> + intel_cx0_get_powerdown_update(lane), 0,
> + XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
> + drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
> + phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
> +}
> +
> +static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port)
> +{
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_POWER_STATE_READY_MASK,
> + XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port),
> + XELPDP_POWER_STATE_ACTIVE_MASK |
> + XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
> + XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
> + XELPDP_PLL_LANE_STAGGERING_DELAY(0));
> +}
> +
> +static u32 intel_cx0_get_pclk_refclk_request(u8 lane)
> +{
> + if (lane == INTEL_CX0_LANE0)
> + return XELPDP_LANE0_PCLK_REFCLK_REQUEST;
> + else if (lane == INTEL_CX0_LANE1)
> + return XELPDP_LANE1_PCLK_REFCLK_REQUEST;
> + else
> + return XELPDP_LANE0_PCLK_REFCLK_REQUEST |
> + XELPDP_LANE1_PCLK_REFCLK_REQUEST;
> +}
> +
> +static u32 intel_cx0_get_pclk_refclk_ack(u8 lane)
> +{
> + if (lane == INTEL_CX0_LANE0)
> + return XELPDP_LANE0_PCLK_REFCLK_ACK;
> + else if (lane == INTEL_CX0_LANE1)
> + return XELPDP_LANE1_PCLK_REFCLK_ACK;
> + else
> + return XELPDP_LANE0_PCLK_REFCLK_ACK |
> + XELPDP_LANE1_PCLK_REFCLK_ACK;
> +}
Could simplify both of the above functions.
> +
> +/* FIXME: Some Type-C cases need not reset both the lanes. Handle those cases. */
> +static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, enum port port,
> + bool lane_reversal)
> +{
> + enum phy phy = intel_port_to_phy(i915, port);
> + u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> + INTEL_CX0_LANE0;
> +
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
> + XELPDP_PORT_BUF_SOC_PHY_READY,
> + XELPDP_PORT_BUF_SOC_PHY_READY,
> + XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
> + drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
> + phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
> +
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET,
> + XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET);
> +
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_LANE0_PHY_CURRENT_STATUS | XELPDP_LANE1_PHY_CURRENT_STATUS,
> + XELPDP_LANE0_PHY_CURRENT_STATUS | XELPDP_LANE1_PHY_CURRENT_STATUS,
> + XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
> + drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
> + phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
> +
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
> + intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES),
> + intel_cx0_get_pclk_refclk_request(lane));
> +
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
> + intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES),
> + intel_cx0_get_pclk_refclk_ack(lane),
> + XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
> + drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
> + phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US);
> +
> + intel_cx0_powerdown_change_sequence(i915, port, INTEL_CX0_BOTH_LANES,
> + CX0_P2_STATE_RESET);
> + intel_cx0_setup_powerdown(i915, port);
> +
> + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET, 0);
> +
> + if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port),
> + XELPDP_LANE0_PHY_CURRENT_STATUS |
> + XELPDP_LANE1_PHY_CURRENT_STATUS,
> + XELPDP_PORT_RESET_END_TIMEOUT))
> + drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
> + phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
> +}
> +
> +static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
> + struct intel_encoder *encoder, int lane_count,
> + bool lane_reversal)
> +{
> + u8 l0t1, l0t2, l1t1, l1t2;
> + bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
> + enum port port = encoder->port;
> +
> + intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MSGBUS_ACCESS,
> + MB_WRITE_COMMITTED);
TODO: DP-alt MFD case where only one PHY lane should be programmed.
> +
> + l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
> + l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
> + l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2));
> + l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2));
> +
Would be clearer setting here CONTROL2_DISABLE_SINGLE_TX in all of l[0/1]t[1/2], and then
> + if (lane_reversal) {
> + switch (lane_count) {
> + case 1:
l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
break;
etc. for 2,3,4 lanes and then
> + /* Disable MLs 1(lane0), 2(lane0), 3(lane1) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
> + l1t1 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + fallthrough;
> + case 2:
> + /* Disable MLs 1(lane0), 2(lane0) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
> + l0t2 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + fallthrough;
> + case 3:
> + /* Disable MLs 1(lane0) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
> + l0t1 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + break;
> + }
> + } else {
> + switch (lane_count) {
> + case 1:
> + if (dp_alt_mode) {
> + /* Disable MLs 1(lane0), 3(lane1), 4(lane1) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
> + l0t1 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + } else {
> + /* Disable MLs 2(lane0), 3(lane1), 4(lane1) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
> + l0t2 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + }
> + fallthrough;
> + case 2:
> + /* Disable MLs 3(lane1), 4(lane1) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
> + l1t1 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + fallthrough;
> + case 3:
> + /* Disable MLs 4(lane1) */
> + intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
> + l1t2 | CONTROL2_DISABLE_SINGLE_TX,
> + MB_WRITE_COMMITTED);
> + break;
> + }
> + }
write here PHY_CX0_LANE[0/1], PHY_CX0_TX_CONTROL([1/2], 2)
> +
> + if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) {
This check is not needed, as we get here only for C10 PHY.
> + intel_cx0_rmw(i915, port, INTEL_CX0_LANE1, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
Should the above clear C10_VDR_CTRL_MASTER_LANE?
> + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> + intel_cx0_rmw(i915, port, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
> + C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> + }
> +}
> +
> +static u32 intel_cx0_get_pclk_pll_request(u8 lane)
> +{
> + if (lane == INTEL_CX0_LANE0)
> + return XELPDP_LANE0_PCLK_PLL_REQUEST;
> + else if (lane == INTEL_CX0_LANE1)
> + return XELPDP_LANE1_PCLK_PLL_REQUEST;
> + else
> + return XELPDP_LANE0_PCLK_PLL_REQUEST |
> + XELPDP_LANE1_PCLK_PLL_REQUEST;
> +}
> +
> +static u32 intel_cx0_get_pclk_pll_ack(u8 lane)
> +{
> + if (lane == INTEL_CX0_LANE0)
> + return XELPDP_LANE0_PCLK_PLL_ACK;
> + else if (lane == INTEL_CX0_LANE1)
> + return XELPDP_LANE1_PCLK_PLL_ACK;
> + else
> + return XELPDP_LANE0_PCLK_PLL_ACK |
> + XELPDP_LANE1_PCLK_PLL_ACK;
> +}
Could simplify the above functions.
> +
> +static void intel_c10pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> + u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
> + INTEL_CX0_LANE0;
> +
> + /*
> + * 1. Program PORT_CLOCK_CTL REGISTER to configure
> + * clock muxes, gating and SSC
> + */
> + intel_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
> +
> + /* 2. Bring PHY out of reset. */
> + intel_cx0_phy_lane_reset(i915, encoder->port, lane_reversal);
> +
> + /*
> + * 3. Change Phy power state to Ready.
> + * TODO: For DP alt mode use only one lane.
> + */
> + intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> + CX0_P2_STATE_READY);
> +
> + /* 4. Program PHY internal PLL internal registers. */
> + intel_c10_pll_program(i915, crtc_state, encoder);
> +
> + /*
> + * 5. Program the enabled and disabled owned PHY lane
> + * transmitters over message bus
> + */
> + intel_c10_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
> +
> + /*
> + * 6. Follow the Display Voltage Frequency Switching - Sequence
> + * Before Frequency Change. We handle this step in bxt_set_cdclk().
> + */
> +
> + /*
> + * 7. Program DDI_CLK_VALFREQ to match intended DDI
> + * clock frequency.
> + */
> + intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
> + crtc_state->port_clock);
> + /*
> + * 8. Set PORT_CLOCK_CTL register PCLK PLL Request
> + * LN<Lane for maxPCLK> to "1" to enable PLL.
> + */
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
> + intel_cx0_get_pclk_pll_request(maxpclk_lane));
> +
> + /* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
> + intel_cx0_get_pclk_pll_ack(maxpclk_lane),
> + XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
> + drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n",
> + phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US);
> +
> + /*
> + * 10. Follow the Display Voltage Frequency Switching Sequence After
> + * Frequency Change. We handle this step in bxt_set_cdclk().
> + */
> +}
> +
> +void intel_cx0pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> + intel_c10pll_enable(encoder, crtc_state);
TBT-alt is not handled, so needs a TODO: comment.
> +}
> +
> +static void intel_c10pll_disable(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + /* 1. Change owned PHY lane power to Disable state. */
> + intel_cx0_powerdown_change_sequence(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> + CX0_P2PG_STATE_DISABLE);
> +
> + /*
> + * 2. Follow the Display Voltage Frequency Switching Sequence Before
> + * Frequency Change. We handle this step in bxt_set_cdclk().
> + */
> +
> + /*
> + * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
> + * to "0" to disable PLL.
> + */
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
> + intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
> +
> + /* 4. Program DDI_CLK_VALFREQ to 0. */
> + intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
> +
> + /*
> + * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
> + */
> + if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
> + intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
> + XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
> + drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n",
> + phy_name(phy), XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US);
> +
> + /*
> + * 6. Follow the Display Voltage Frequency Switching Sequence After
> + * Frequency Change. We handle this step in bxt_set_cdclk().
> + */
> +
> + /* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> + XELPDP_DDI_CLOCK_SELECT_MASK |
> + XELPDP_FORWARD_CLOCK_UNGATE, 0);
> +}
> +
> +void intel_cx0pll_disable(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> + intel_c10pll_disable(encoder);
> +}
> +
> +void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
> + struct intel_crtc_state *new_crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_c10mpllb_state mpllb_hw_state = { 0 };
> + struct intel_c10mpllb_state *mpllb_sw_state = &new_crtc_state->c10mpllb_state;
> + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + struct intel_encoder *encoder;
> + struct intel_dp *intel_dp;
> + enum phy phy;
> + int i;
> + bool use_ssc = false;
> +
> + if (DISPLAY_VER(i915) < 14)
> + return;
> +
> + if (!new_crtc_state->hw.active)
> + return;
> +
> + encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> + phy = intel_port_to_phy(i915, encoder->port);
> +
> + if (intel_crtc_has_dp_encoder(new_crtc_state)) {
> + intel_dp = enc_to_intel_dp(encoder);
> + use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> + DP_MAX_DOWNSPREAD_0_5);
> +
> + if (!intel_panel_use_ssc(i915))
> + use_ssc = false;
> + }
> +
> + if (!intel_is_c10phy(i915, phy))
> + return;
> +
> + intel_c10mpllb_readout_hw_state(encoder, &mpllb_hw_state);
> +
> + for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {
> + u8 expected;
> +
> + if (!use_ssc && i > 3 && i < 9)
> + expected = 0;
> + else
> + expected = mpllb_sw_state->pll[i];
The above isn't needed if PLL state is setup correctly in
intel_c10mpllb_calc_state(), taking into account SSC as well.
> +
> + I915_STATE_WARN(mpllb_hw_state.pll[i] != expected,
> + "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)",
> + crtc->base.base.id, crtc->base.name,
> + i, expected, mpllb_hw_state.pll[i]);
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> new file mode 100644
> index 000000000000..8cf340509097
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2021 Intel Corporation
> + */
> +
> +#ifndef __INTEL_CX0_PHY_H__
> +#define __INTEL_CX0_PHY_H__
> +
> +#include <linux/types.h>
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +
> +#include "i915_drv.h"
> +#include "intel_display_types.h"
> +
> +struct drm_i915_private;
> +struct intel_encoder;
> +struct intel_crtc_state;
> +enum phy;
> +
> +#define INTEL_CX0_LANE0 0x1
> +#define INTEL_CX0_LANE1 0x2
> +#define INTEL_CX0_BOTH_LANES 0x3
Please use INTEL_CX0_LANE0/1 instead of open-coding them.
> +
> +#define MB_WRITE_COMMITTED 1
> +#define MB_WRITE_UNCOMMITTED 0
The above should be bool values.
Could the above be moved to intel_cx0_phy.c ?
> +
> +bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
> +void intel_cx0pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
> +void intel_cx0pll_disable(struct intel_encoder *encoder);
> +void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> + struct intel_c10mpllb_state *pll_state);
> +int intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder);
> +void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv,
> + const struct intel_c10mpllb_state *hw_state);
> +int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
> + const struct intel_c10mpllb_state *pll_state);
> +void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
> + struct intel_crtc_state *new_crtc_state);
> +
> +#endif /* __INTEL_CX0_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index d1ee8a2fc9cf..15e249f46a64 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -128,4 +128,34 @@
> #define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
> #define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
>
> -#endif /* __INTEL_CX0_PHY_REGS_H__ */
> +/* C10 Vendor Registers */
> +#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
> +#define C10_PLL0_FRACEN REG_BIT8(4)
> +#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
> +#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
> +#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
> +#define C10_CMN0_DP_VAL 0x21
> +#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
> +#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
> +#define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
> +#define C10_TX0_VAL 0x10
> +#define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1)
> +#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2)
> +#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1)
> +#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
> +#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
> +
> +#define CX0_P0_STATE_ACTIVE 0x0
> +#define CX0_P2_STATE_READY 0x2
> +#define CX0_P2PG_STATE_DISABLE 0x9
> +#define CX0_P4PG_STATE_DISABLE 0xC
> +#define CX0_P2_STATE_RESET 0x2
> +
> +/* PHY_C10_VDR_PLL0 */
> +#define PLL_C10_MPLL_SSC_EN REG_BIT8(0)
> +
> +/* PIPE SPEC Defined Registers */
> +#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
> +#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
> +
> +#endif /* __INTEL_CX0_REG_DEFS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 73240cf78c8b..a433dea5b9a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -39,6 +39,7 @@
> #include "intel_combo_phy_regs.h"
> #include "intel_connector.h"
> #include "intel_crtc.h"
> +#include "intel_cx0_phy.h"
> #include "intel_ddi.h"
> #include "intel_ddi_buf_trans.h"
> #include "intel_de.h"
> @@ -3507,6 +3508,21 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
> &crtc_state->dpll_hw_state);
> }
>
> +static void mtl_ddi_get_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> +
> + drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> +
> + intel_c10mpllb_readout_hw_state(encoder, &crtc_state->c10mpllb_state);
> + intel_c10mpllb_dump_hw_state(i915, &crtc_state->c10mpllb_state);
> + crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->c10mpllb_state);
> +
> + intel_ddi_get_config(encoder, crtc_state);
> +}
> +
> static void dg2_ddi_get_config(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -4413,7 +4429,11 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> encoder->cloneable = 0;
> encoder->pipe_mask = ~0;
>
> - if (IS_DG2(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + encoder->enable_clock = intel_cx0pll_enable;
> + encoder->disable_clock = intel_cx0pll_disable;
> + encoder->get_config = mtl_ddi_get_config;
> + } else if (IS_DG2(dev_priv)) {
> encoder->enable_clock = intel_mpllb_enable;
> encoder->disable_clock = intel_mpllb_disable;
> encoder->get_config = dg2_ddi_get_config;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index f86060195987..e23fecba446c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1614,7 +1614,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> return;
>
> /* 2. Initialize all combo phys */
> - intel_combo_phy_init(dev_priv);
> + if (DISPLAY_VER(dev_priv) < 14)
> + intel_combo_phy_init(dev_priv);
This shouldn't be needed, intel_combo_phy_init() handles only combo
PHYs.
>
> /*
> * 3. Enable Power Well 1 (PG1).
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 1676df1dc066..a4c8cb75c0a0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -970,7 +970,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> bxt_verify_ddi_phy_power_wells(dev_priv);
>
> - if (DISPLAY_VER(dev_priv) >= 11)
> + if (DISPLAY_VER(dev_priv) >= 11 && DISPLAY_VER(dev_priv) < 14)
Isn't needed.
> /*
> * DMC retains HW context only for port A, the other combo
> * PHY's HW context for port B is lost after DC transitions,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ab146b5b68bd..db7c108e4d86 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -985,6 +985,11 @@ struct intel_link_m_n {
> u32 link_n;
> };
>
> +struct intel_c10mpllb_state {
> + u32 clock; /* in KHz */
> + u8 pll[20];
> +};
> +
> struct intel_crtc_state {
> /*
> * uapi (drm) state. This is the software state shown to userspace.
> @@ -1128,6 +1133,7 @@ struct intel_crtc_state {
> union {
> struct intel_dpll_hw_state dpll_hw_state;
> struct intel_mpllb_state mpllb_state;
> + struct intel_c10mpllb_state c10mpllb_state;
> };
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 4e9c18be7e1f..da5aa050a5ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -8,6 +8,7 @@
>
> #include "i915_reg.h"
> #include "intel_crtc.h"
> +#include "intel_cx0_phy.h"
> #include "intel_de.h"
> #include "intel_display.h"
> #include "intel_display_types.h"
> @@ -995,6 +996,17 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
> return 0;
> }
>
> +static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> +{
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + struct intel_encoder *encoder =
> + intel_get_crtc_new_encoder(state, crtc_state);
> +
> + return intel_cx0mpllb_calc_state(crtc_state, encoder);
> +}
> +
> static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
> {
> return dpll->m < factor * dpll->n;
> @@ -1423,6 +1435,10 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
> return 0;
> }
>
> +static const struct intel_dpll_funcs mtl_dpll_funcs = {
> + .crtc_compute_clock = mtl_crtc_compute_clock,
> +};
> +
> static const struct intel_dpll_funcs dg2_dpll_funcs = {
> .crtc_compute_clock = dg2_crtc_compute_clock,
> };
> @@ -1517,7 +1533,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
> void
> intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
> {
> - if (IS_DG2(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 14)
> + dev_priv->display.funcs.dpll = &mtl_dpll_funcs;
> + else if (IS_DG2(dev_priv))
> dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
> else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
> dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 22fc908b7e5d..ed372d227aa7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4104,7 +4104,7 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
>
> mutex_init(&dev_priv->display.dpll.lock);
>
> - if (IS_DG2(dev_priv))
> + if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv))
> /* No shared DPLLs on DG2; port PLLs are part of the PHY */
> dpll_mgr = NULL;
> else if (IS_ALDERLAKE_P(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> index 842d70f0dfd2..ec504470c2f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> @@ -11,6 +11,7 @@
> #include "intel_atomic.h"
> #include "intel_crtc.h"
> #include "intel_crtc_state_dump.h"
> +#include "intel_cx0_phy.h"
> #include "intel_display.h"
> #include "intel_display_types.h"
> #include "intel_fdi.h"
> @@ -236,6 +237,7 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
> verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
> intel_shared_dpll_state_verify(crtc, old_crtc_state, new_crtc_state);
> intel_mpllb_state_verify(state, new_crtc_state);
> + intel_c10mpllb_state_verify(state, new_crtc_state);
> }
>
> void intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d22ffd7a32dc..94dd0d3a474b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2101,6 +2101,11 @@
> #define TRANS_PUSH_EN REG_BIT(31)
> #define TRANS_PUSH_SEND REG_BIT(30)
>
> +/* DDI Buffer Control */
> +#define _DDI_CLK_VALFREQ_A 0x64030
> +#define _DDI_CLK_VALFREQ_B 0x64130
> +#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
> +
> /*
> * HSW+ eDP PSR registers
> *
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
> index db26de6b57bc..f9d7c03e95d6 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -22,6 +22,19 @@
> BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
> ((__n) < 0 || (__n) > 31))))
>
> +/**
> + * REG_BIT8() - Prepare a u8 bit value
> + * @__n: 0-based bit number
> + *
> + * Local wrapper for BIT() to force u8, with compile time checks.
> + *
> + * @return: Value with bit @__n set.
> + */
> +#define REG_BIT8(__n) \
> + ((u8)(BIT(__n) + \
> + BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
> + ((__n) < 0 || (__n) > 7))))
> +
> /**
> * REG_GENMASK() - Prepare a continuous u32 bitmask
> * @__high: 0-based high bit
> @@ -52,6 +65,21 @@
> __is_constexpr(__low) && \
> ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
>
> +/**
> + * REG_GENMASK8() - Prepare a continuous u8 bitmask
> + * @__high: 0-based high bit
> + * @__low: 0-based low bit
> + *
> + * Local wrapper for GENMASK() to force u8, with compile time checks.
> + *
> + * @return: Continuous bitmask from @__high to @__low, inclusive.
> + */
> +#define REG_GENMASK8(__high, __low) \
> + ((u8)(GENMASK(__high, __low) + \
> + BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
> + __is_constexpr(__low) && \
> + ((__low) < 0 || (__high) > 7 || (__low) > (__high)))))
> +
> /*
> * Local integer constant expression version of is_power_of_2().
> */
> @@ -74,6 +102,23 @@
> BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
> BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
>
> +/**
> + * REG_FIELD_PREP8() - Prepare a u8 bitfield value
> + * @__mask: shifted mask defining the field's length and position
> + * @__val: value to put in the field
> + *
> + * Local copy of FIELD_PREP8() to generate an integer constant expression, force
> + * u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8().
> + *
> + * @return: @__val masked and shifted into the field defined by @__mask.
> + */
> +#define REG_FIELD_PREP8(__mask, __val) \
> + ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
> + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
> + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
> + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
> + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
> +
> /**
> * REG_FIELD_GET() - Extract a u32 bitfield value
> * @__mask: shifted mask defining the field's length and position
> @@ -155,6 +200,18 @@
> */
> #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
>
> +/**
> + * REG_FIELD_GET8() - Extract a u8 bitfield value
> + * @__mask: shifted mask defining the field's length and position
> + * @__val: value to extract the bitfield value from
> + *
> + * Local wrapper for FIELD_GET() to force u8 and for consistency with
> + * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
> + *
> + * @return: Masked and shifted value of the field defined by @__mask in @__val.
> + */
> +#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))
> +
> typedef struct {
> u32 reg;
> } i915_reg_t;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-03-29 15:40 ` Imre Deak
@ 2023-03-29 15:59 ` Imre Deak
2023-04-04 10:43 ` Kahola, Mika
1 sibling, 0 replies; 37+ messages in thread
From: Imre Deak @ 2023-03-29 15:59 UTC (permalink / raw)
To: Mika Kahola, intel-gfx
On Wed, Mar 29, 2023 at 06:40:39PM +0300, Imre Deak wrote:
> On Mon, Mar 27, 2023 at 03:34:30PM +0300, Mika Kahola wrote:
> [...]
> > +}
> > +
> > +static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port, int lane, u32 *val)
> > +{
> > + enum phy phy = intel_port_to_phy(i915, port);
> > +
> > + if (__intel_de_wait_for_register(i915,
> > + XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1),
>
> As above this function should take the 0-based lane value.
Err, I meant here as earlier the function param should be
'u8 lane_mask' and use a helper to convert this mask to a lane.
--Imre
^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add Support for C10 chips (rev2)
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
` (10 preceding siblings ...)
2023-03-28 1:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-03-29 16:48 ` Patchwork
2023-03-29 16:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2023-03-29 16:48 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 chips (rev2)
URL : https://patchwork.freedesktop.org/series/115664/
State : warning
== Summary ==
Error: dim checkpatch failed
9a839bd9b6b9 drm/i915/mtl: Initial DDI port setup
febb42d9125a drm/i915/mtl: Add DP rates
7ad8892410b2 drm/i915/mtl: Create separate reg file for PICA registers
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:18: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#18:
new file mode 100644
-:38: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#38: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:16:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
-:39: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#39: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:17:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
-:40: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#40: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:18:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
-:41: WARNING:LONG_LINE: line length of 133 exceeds 100 columns
#41: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:19:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
-:44: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#44: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:22:
+#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
-:45: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:23:
+#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
-:46: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#46: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:24:
+#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
-:48: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#48: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:26:
+#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
-:51: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#51: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:29:
+#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
-:53: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#53: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:31:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
-:54: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:32:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
-:55: WARNING:LONG_LINE: line length of 121 exceeds 100 columns
#55: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:33:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
-:56: WARNING:LONG_LINE: line length of 137 exceeds 100 columns
#56: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:34:
+ _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
-:62: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#62: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:40:
+#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
-:80: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#80: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:58:
+ _XELPDP_PORT_BUF_CTL1_LN0_A, \
-:81: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#81: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:59:
+ _XELPDP_PORT_BUF_CTL1_LN0_B, \
-:82: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#82: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:60:
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
-:83: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#83: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:61:
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC2))
-:93: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#93: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:71:
+ _XELPDP_PORT_BUF_CTL1_LN0_A, \
-:94: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#94: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:72:
+ _XELPDP_PORT_BUF_CTL1_LN0_B, \
-:95: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#95: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:73:
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
-:96: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#96: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:74:
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4)
-:104: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#104: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:82:
+#define XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
-:106: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#106: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:84:
+#define XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val)
-:108: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#108: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:86:
+#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
-:111: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#111: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:89:
+ _XELPDP_PORT_BUF_CTL1_LN0_A, \
-:112: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#112: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:90:
+ _XELPDP_PORT_BUF_CTL1_LN0_B, \
-:113: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#113: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:91:
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
-:114: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#114: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:92:
+ _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8)
-:116: WARNING:LONG_LINE: line length of 114 exceeds 100 columns
#116: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:94:
+#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
-:118: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#118: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:96:
+#define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
-:125: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#125: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:103:
+ _XELPDP_PORT_CLOCK_CTL_A, \
-:126: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#126: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:104:
+ _XELPDP_PORT_CLOCK_CTL_B, \
-:127: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#127: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:105:
+ _XELPDP_PORT_CLOCK_CTL_USBC1, \
-:128: WARNING:LONG_LINE: line length of 111 exceeds 100 columns
#128: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:106:
+ _XELPDP_PORT_CLOCK_CTL_USBC2))
-:140: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#140: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:118:
+#define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val)
total: 0 errors, 37 warnings, 0 checks, 131 lines checked
4a1a74a070e6 drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:24: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#24:
Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
-:58: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#58:
new file mode 100644
-:79: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'phy < PHY_C'
#79: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:17:
+ if (IS_METEORLAKE(dev_priv) && (phy < PHY_C))
-:114: WARNING:LONG_LINE: line length of 119 exceeds 100 columns
#114: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:52:
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", phy_name(phy), *val);
-:122: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#122: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:60:
+static int __intel_cx0_read(struct drm_i915_private *i915, enum port port,
+ int lane, u16 addr, u32 *val)
-:131: WARNING:LONG_LINE: line length of 146 exceeds 100 columns
#131: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:69:
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
-:151: WARNING:LONG_LINE: line length of 122 exceeds 100 columns
#151: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:89:
+ drm_dbg_kms(&i915->drm, "PHY %c Error occurred during read command. Status: 0x%x\n", phy_name(phy), *val);
-:159: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#159: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:97:
+ drm_dbg_kms(&i915->drm, "PHY %c Not a Read response. MSGBUS Status: 0x%x.\n", phy_name(phy), *val);
-:185: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#185: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:123:
+ drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n", phy_name(phy), addr, i);
-:193: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#193: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:131:
+static int intel_cx0_wait_cwrite_ack(struct drm_i915_private *i915,
+ enum port port, int lane)
-:206: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#206: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:144:
+ drm_dbg_kms(&i915->drm, "PHY %c Unexpected ACK received. MSGBUS STATUS: 0x%x.\n", phy_name(phy), val);
-:222: WARNING:LONG_LINE: line length of 146 exceeds 100 columns
#222: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:160:
+ drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
-:243: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#243: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:181:
+ drm_dbg_kms(&i915->drm, "PHY %c Error occurred during write command.\n", phy_name(phy));
-:267: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#267: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:205:
+ drm_err_once(&i915->drm, "PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
-:672: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#672: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:610:
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
-:673: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#673: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:611:
+ intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_TX(0), C10_TX0_VAL, MB_WRITE_COMMITTED);
-:868: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#868: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:806:
+ XELPDP_LANE0_PHY_CURRENT_STATUS | XELPDP_LANE1_PHY_CURRENT_STATUS,
-:869: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#869: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:807:
+ XELPDP_LANE0_PHY_CURRENT_STATUS | XELPDP_LANE1_PHY_CURRENT_STATUS,
-:943: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#943: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:881:
+ intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
-:948: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#948: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:886:
+ intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
-:974: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#974: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:912:
+ C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
-:1189: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/display/intel_cx0_phy.h', please use '/*' instead
#1189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.h:1:
+// SPDX-License-Identifier: MIT
-:1189: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#1189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.h:1:
+// SPDX-License-Identifier: MIT
-:1298: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#1298: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:3521:
+ crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->c10mpllb_state);
-:1487: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__n' - possible side-effects?
#1487: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:33:
+#define REG_BIT8(__n) \
+ ((u8)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 7))))
-:1508: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__high' - possible side-effects?
#1508: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:77:
+#define REG_GENMASK8(__high, __low) \
+ ((u8)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 7 || (__low) > (__high)))))
-:1508: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__low' - possible side-effects?
#1508: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:77:
+#define REG_GENMASK8(__high, __low) \
+ ((u8)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 7 || (__low) > (__high)))))
-:1531: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__mask' - possible side-effects?
#1531: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:115:
+#define REG_FIELD_PREP8(__mask, __val) \
+ ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:1531: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__val' - possible side-effects?
#1531: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:115:
+#define REG_FIELD_PREP8(__mask, __val) \
+ ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:1536: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#1536: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:120:
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
total: 0 errors, 22 warnings, 8 checks, 1438 lines checked
b4fed4ea411e drm/i915/mtl: Add C10 phy programming for HDMI
-:21: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#21:
v3: Add missing use_hdmi checks from Clint's HDMI implementation changes (Ankit)
-:165: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#165: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:615:
+ .pll[0]=0x34,
^
-:166: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#166: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:616:
+ .pll[1]=0x00,
^
-:167: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#167: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:617:
+ .pll[2]=0xB0,
^
-:168: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#168: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:618:
+ .pll[3]=0x00,
^
-:169: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#169: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:619:
+ .pll[4]=0x00,
^
-:170: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#170: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:620:
+ .pll[5]=0x00,
^
-:171: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#171: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:621:
+ .pll[6]=0x00,
^
-:172: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#172: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:622:
+ .pll[7]=0x00,
^
-:173: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#173: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:623:
+ .pll[8]=0x20,
^
-:174: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#174: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:624:
+ .pll[9]=0xFF,
^
-:175: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#175: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:625:
+ .pll[10]=0xFF,
^
-:176: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#176: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:626:
+ .pll[11]=0x55,
^
-:177: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#177: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:627:
+ .pll[12]=0xE5,
^
-:178: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#178: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:628:
+ .pll[13]=0x55,
^
-:179: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#179: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:629:
+ .pll[14]=0x55,
^
-:180: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#180: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:630:
+ .pll[15]=0x0D,
^
-:181: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#181: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:631:
+ .pll[16]=0x09,
^
-:182: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#182: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:632:
+ .pll[17]=0x8F,
^
-:183: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#183: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:633:
+ .pll[18]=0x84,
^
-:184: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#184: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:634:
+ .pll[19]=0x23,
^
-:189: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:639:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
^
-:189: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:639:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
^
-:189: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:639:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
^
-:189: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:639:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
^
-:189: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#189: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:639:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
^
-:190: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:640:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:190: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:640:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:190: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:640:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:190: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:640:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:190: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#190: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:640:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:191: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: space required after that ',' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: space required after that ',' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: space required after that ',' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: space required after that ',' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:191: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#191: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:641:
+ .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
^
-:192: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: space required after that ',' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: space required after that ',' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: space required after that ',' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: space required after that ',' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:192: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#192: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:642:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:197: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#197: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:647:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xCC, .pll[3]=0x00, .pll[4]=0x00,
^
-:197: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#197: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:647:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xCC, .pll[3]=0x00, .pll[4]=0x00,
^
-:197: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#197: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:647:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xCC, .pll[3]=0x00, .pll[4]=0x00,
^
-:197: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#197: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:647:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xCC, .pll[3]=0x00, .pll[4]=0x00,
^
-:197: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#197: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:647:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xCC, .pll[3]=0x00, .pll[4]=0x00,
^
-:198: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#198: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:648:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:198: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#198: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:648:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:198: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#198: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:648:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:198: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#198: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:648:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:198: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#198: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:648:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:199: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: space required after that ',' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: space required after that ',' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: space required after that ',' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: space required after that ',' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:199: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#199: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:649:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:200: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: space required after that ',' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: space required after that ',' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: space required after that ',' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: space required after that ',' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:200: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#200: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:650:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:205: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#205: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:655:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xDC, .pll[3]=0x00, .pll[4]=0x00,
^
-:205: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#205: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:655:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xDC, .pll[3]=0x00, .pll[4]=0x00,
^
-:205: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#205: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:655:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xDC, .pll[3]=0x00, .pll[4]=0x00,
^
-:205: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#205: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:655:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xDC, .pll[3]=0x00, .pll[4]=0x00,
^
-:205: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#205: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:655:
+ .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xDC, .pll[3]=0x00, .pll[4]=0x00,
^
-:206: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#206: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:656:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:206: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#206: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:656:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:206: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#206: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:656:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:206: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#206: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:656:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:206: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#206: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:656:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:207: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: space required after that ',' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: space required after that ',' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: space required after that ',' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: space required after that ',' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:207: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#207: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:657:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:208: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: space required after that ',' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: space required after that ',' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: space required after that ',' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: space required after that ',' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:208: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#208: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:658:
+ .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:213: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#213: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:663:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x62, .pll[3]=0x00, .pll[4]=0x00,
^
-:213: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#213: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:663:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x62, .pll[3]=0x00, .pll[4]=0x00,
^
-:213: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#213: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:663:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x62, .pll[3]=0x00, .pll[4]=0x00,
^
-:213: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#213: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:663:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x62, .pll[3]=0x00, .pll[4]=0x00,
^
-:213: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#213: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:663:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x62, .pll[3]=0x00, .pll[4]=0x00,
^
-:214: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#214: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:664:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:214: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#214: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:664:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:214: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#214: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:664:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:214: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#214: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:664:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:214: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#214: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:664:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:215: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: space required after that ',' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: space required after that ',' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: space required after that ',' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: space required after that ',' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:215: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#215: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:665:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
^
-:216: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: space required after that ',' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: space required after that ',' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: space required after that ',' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: space required after that ',' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:216: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#216: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:666:
+ .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:221: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#221: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:671:
+ .pll[0]=0xC4, .pll[1]=0x00, .pll[2]=0x76, .pll[3]=0x00, .pll[4]=0x00,
^
-:221: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#221: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:671:
+ .pll[0]=0xC4, .pll[1]=0x00, .pll[2]=0x76, .pll[3]=0x00, .pll[4]=0x00,
^
-:221: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#221: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:671:
+ .pll[0]=0xC4, .pll[1]=0x00, .pll[2]=0x76, .pll[3]=0x00, .pll[4]=0x00,
^
-:221: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#221: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:671:
+ .pll[0]=0xC4, .pll[1]=0x00, .pll[2]=0x76, .pll[3]=0x00, .pll[4]=0x00,
^
-:221: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#221: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:671:
+ .pll[0]=0xC4, .pll[1]=0x00, .pll[2]=0x76, .pll[3]=0x00, .pll[4]=0x00,
^
-:222: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#222: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:672:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:222: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#222: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:672:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:222: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#222: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:672:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:222: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#222: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:672:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:222: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#222: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:672:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:223: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: space required after that ',' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: space required after that ',' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: space required after that ',' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: space required after that ',' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:223: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#223: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:673:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
^
-:224: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: space required after that ',' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: space required after that ',' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: space required after that ',' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: space required after that ',' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:224: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#224: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:674:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:229: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#229: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:679:
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
^
-:229: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#229: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:679:
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
^
-:229: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#229: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:679:
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
^
-:229: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#229: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:679:
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
^
-:229: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#229: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:679:
+ .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
^
-:230: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#230: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:680:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:230: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#230: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:680:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:230: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#230: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:680:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:230: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#230: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:680:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:230: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#230: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:680:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:231: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: space required after that ',' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: space required after that ',' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: space required after that ',' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: space required after that ',' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:231: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#231: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:681:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
^
-:232: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: space required after that ',' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: space required after that ',' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: space required after that ',' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: space required after that ',' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:232: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#232: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:682:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:237: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#237: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:687:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
^
-:237: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#237: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:687:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
^
-:237: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#237: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:687:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
^
-:237: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#237: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:687:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
^
-:237: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#237: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:687:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
^
-:238: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#238: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:688:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:238: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#238: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:688:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:238: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#238: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:688:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:238: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#238: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:688:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:238: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#238: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:688:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:239: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: space required after that ',' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: space required after that ',' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: space required after that ',' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: space required after that ',' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:239: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#239: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:689:
+ .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
^
-:240: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: space required after that ',' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: space required after that ',' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: space required after that ',' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: space required after that ',' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:240: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#240: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:690:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:245: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#245: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:695:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xB0, .pll[3]=0x00, .pll[4]=0x00,
^
-:245: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#245: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:695:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xB0, .pll[3]=0x00, .pll[4]=0x00,
^
-:245: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#245: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:695:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xB0, .pll[3]=0x00, .pll[4]=0x00,
^
-:245: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#245: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:695:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xB0, .pll[3]=0x00, .pll[4]=0x00,
^
-:245: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#245: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:695:
+ .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xB0, .pll[3]=0x00, .pll[4]=0x00,
^
-:246: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#246: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:696:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:246: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#246: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:696:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:246: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#246: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:696:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:246: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#246: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:696:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:246: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#246: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:696:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:247: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: space required after that ',' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: space required after that ',' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: space required after that ',' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: space required after that ',' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:247: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#247: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:697:
+ .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
^
-:248: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: space required after that ',' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: space required after that ',' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: space required after that ',' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: space required after that ',' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:248: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#248: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:698:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:253: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#253: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:703:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xCE, .pll[3]=0x00, .pll[4]=0x00,
^
-:253: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#253: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:703:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xCE, .pll[3]=0x00, .pll[4]=0x00,
^
-:253: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#253: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:703:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xCE, .pll[3]=0x00, .pll[4]=0x00,
^
-:253: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#253: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:703:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xCE, .pll[3]=0x00, .pll[4]=0x00,
^
-:253: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#253: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:703:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xCE, .pll[3]=0x00, .pll[4]=0x00,
^
-:254: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#254: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:704:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:254: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#254: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:704:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:254: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#254: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:704:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:254: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#254: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:704:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:254: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#254: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:704:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:255: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: space required after that ',' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: space required after that ',' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: space required after that ',' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: space required after that ',' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:255: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#255: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:705:
+ .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
^
-:256: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: space required after that ',' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: space required after that ',' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: space required after that ',' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: space required after that ',' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:256: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#256: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:706:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:261: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#261: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:711:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
^
-:261: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#261: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:711:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
^
-:261: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#261: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:711:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
^
-:261: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#261: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:711:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
^
-:261: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#261: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:711:
+ .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
^
-:262: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#262: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:712:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:262: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#262: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:712:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:262: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#262: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:712:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:262: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#262: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:712:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:262: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#262: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:712:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:263: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: space required after that ',' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: space required after that ',' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: space required after that ',' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: space required after that ',' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:263: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#263: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:713:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
^
-:264: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: space required after that ',' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: space required after that ',' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: space required after that ',' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: space required after that ',' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:264: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#264: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:714:
+ .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:269: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#269: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:719:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x66, .pll[3]=0x00, .pll[4]=0x00,
^
-:269: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#269: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:719:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x66, .pll[3]=0x00, .pll[4]=0x00,
^
-:269: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#269: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:719:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x66, .pll[3]=0x00, .pll[4]=0x00,
^
-:269: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#269: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:719:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x66, .pll[3]=0x00, .pll[4]=0x00,
^
-:269: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#269: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:719:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x66, .pll[3]=0x00, .pll[4]=0x00,
^
-:270: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#270: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:720:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:270: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#270: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:720:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:270: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#270: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:720:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:270: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#270: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:720:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:270: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#270: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:720:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:271: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: space required after that ',' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: space required after that ',' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: space required after that ',' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: space required after that ',' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:271: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#271: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:721:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
^
-:272: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: space required after that ',' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: space required after that ',' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: space required after that ',' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: space required after that ',' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:272: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#272: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:722:
+ .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
^
-:277: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#277: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:727:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x72, .pll[3]=0x00, .pll[4]=0x00,
^
-:277: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#277: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:727:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x72, .pll[3]=0x00, .pll[4]=0x00,
^
-:277: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#277: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:727:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x72, .pll[3]=0x00, .pll[4]=0x00,
^
-:277: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#277: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:727:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x72, .pll[3]=0x00, .pll[4]=0x00,
^
-:277: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#277: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:727:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x72, .pll[3]=0x00, .pll[4]=0x00,
^
-:278: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#278: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:728:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:278: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#278: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:728:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:278: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#278: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:728:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:278: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#278: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:728:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:278: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#278: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:728:
+ .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
^
-:279: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: space required after that ',' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: space required after that ',' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: space required after that ',' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: space required after that ',' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:279: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#279: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:729:
+ .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
^
-:280: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: space required after that ',' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: space required after that ',' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: space required after that ',' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: space required after that ',' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:280: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#280: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:730:
+ .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
^
-:285: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#285: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:735:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
^
-:285: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#285: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:735:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
^
-:285: ERROR:SPACING: spaces required around that '=' (ctx:VxV)
#285: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:735:
+ .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add Support for C10 chips (rev2)
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
` (11 preceding siblings ...)
2023-03-29 16:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add Support for C10 chips (rev2) Patchwork
@ 2023-03-29 16:48 ` Patchwork
2023-03-29 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
15 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2023-03-29 16:48 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 chips (rev2)
URL : https://patchwork.freedesktop.org/series/115664/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: Add Support for C10 chips (rev2)
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
` (12 preceding siblings ...)
2023-03-29 16:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-03-29 16:53 ` Patchwork
2023-03-30 8:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-04-05 8:52 ` [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Andi Shyti
15 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2023-03-29 16:53 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4708 bytes --]
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 chips (rev2)
URL : https://patchwork.freedesktop.org/series/115664/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12936 -> Patchwork_115664v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/index.html
Participating hosts (37 -> 34)
------------------------------
Missing (3): fi-kbl-soraka fi-snb-2520m fi-pnv-d510
Known issues
------------
Here are the changes found in Patchwork_115664v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][1] -> [DMESG-FAIL][2] ([i915#5334])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][3] -> [ABORT][4] ([i915#4983] / [i915#7911])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rpls-1/igt@i915_selftest@live@requests.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@workarounds:
- bat-rplp-1: [PASS][5] -> [INCOMPLETE][6] ([i915#7913])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-rplp-1/igt@i915_selftest@live@workarounds.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/bat-rplp-1/igt@i915_selftest@live@workarounds.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- fi-bsw-nick: NOTRUN -> [SKIP][7] ([fdo#109271]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/fi-bsw-nick/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
- bat-dg2-11: NOTRUN -> [SKIP][8] ([i915#5354])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc:
- bat-adlp-9: NOTRUN -> [SKIP][9] ([i915#3546]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/bat-adlp-9/igt@kms_pipe_crc_basic@read-crc.html
#### Possible fixes ####
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [ABORT][10] ([i915#7911] / [i915#7913]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@migrate:
- bat-dg2-11: [DMESG-WARN][12] ([i915#7699]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/bat-dg2-11/igt@i915_selftest@live@migrate.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/bat-dg2-11/igt@i915_selftest@live@migrate.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
Build changes
-------------
* Linux: CI_DRM_12936 -> Patchwork_115664v2
CI-20190529: 20190529
CI_DRM_12936: 906438caae695f109636f82e2d1845a258f57d8b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7226: 41be8b4ab86f9e11388c10366dfd71e5032589c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_115664v2: 906438caae695f109636f82e2d1845a258f57d8b @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
4cbd667a7a2b drm/i915/mtl: Add support for PM DEMAND
c1d07d32f2b6 drm/i915/mtl: Add vswing programming for C10 phys
c8d867cd648e drm/i915/mtl: Add C10 phy programming for HDMI
e339d2062279 drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
b8a4482714af drm/i915/mtl: Create separate reg file for PICA registers
fa6d4bc79a6c drm/i915/mtl: Add DP rates
0ad2cdd45c1d drm/i915/mtl: Initial DDI port setup
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/index.html
[-- Attachment #2: Type: text/html, Size: 5675 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mtl: Add Support for C10 chips (rev2)
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
` (13 preceding siblings ...)
2023-03-29 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-03-30 8:26 ` Patchwork
2023-04-05 8:52 ` [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Andi Shyti
15 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2023-03-30 8:26 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 12868 bytes --]
== Series Details ==
Series: drm/i915/mtl: Add Support for C10 chips (rev2)
URL : https://patchwork.freedesktop.org/series/115664/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12936_full -> Patchwork_115664v2_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_115664v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_mmap_gtt@fault-concurrent-x:
- shard-snb: [PASS][1] -> [ABORT][2] ([i915#5161])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/shard-snb4/igt@gem_mmap_gtt@fault-concurrent-x.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-snb2/igt@gem_mmap_gtt@fault-concurrent-x.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#3886])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-apl7/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][4] -> [FAIL][5] ([i915#2346]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
- shard-apl: NOTRUN -> [SKIP][6] ([fdo#109271]) +13 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-apl7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#658])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
#### Possible fixes ####
* {igt@gem_barrier_race@remote-request@rcs0}:
- shard-apl: [ABORT][8] ([i915#8211] / [i915#8234]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/shard-apl7/igt@gem_barrier_race@remote-request@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-apl7/igt@gem_barrier_race@remote-request@rcs0.html
- {shard-tglu}: [ABORT][10] ([i915#8211]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/shard-tglu-2/igt@gem_barrier_race@remote-request@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-tglu-9/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_exec_endless@dispatch@vecs0:
- {shard-tglu}: [TIMEOUT][12] ([i915#3778]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/shard-tglu-10/igt@gem_exec_endless@dispatch@vecs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-tglu-5/igt@gem_exec_endless@dispatch@vecs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: [FAIL][14] ([i915#2846]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/shard-apl1/igt@gem_exec_fair@basic-deadline.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-apl1/igt@gem_exec_fair@basic-deadline.html
- shard-glk: [FAIL][16] ([i915#2846]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/shard-glk6/igt@gem_exec_fair@basic-deadline.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-glk7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][18] ([i915#2842]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][20] ([i915#2842]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1:
- shard-apl: [ABORT][22] ([i915#180]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/shard-apl1/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-apl7/igt@kms_cursor_crc@cursor-suspend@pipe-c-dp-1.html
* {igt@kms_cursor_edge_walk@256x256-top-edge@pipe-a-hdmi-a-1}:
- shard-glk: [DMESG-FAIL][24] ([i915#118]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/shard-glk7/igt@kms_cursor_edge_walk@256x256-top-edge@pipe-a-hdmi-a-1.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-glk3/igt@kms_cursor_edge_walk@256x256-top-edge@pipe-a-hdmi-a-1.html
* {igt@kms_draw_crc@draw-method-blt@xrgb2101010-ytiled}:
- shard-glk: [DMESG-WARN][26] -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/shard-glk7/igt@kms_draw_crc@draw-method-blt@xrgb2101010-ytiled.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-glk7/igt@kms_draw_crc@draw-method-blt@xrgb2101010-ytiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- {shard-tglu}: [FAIL][28] ([i915#4767]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12936/shard-tglu-10/igt@kms_fbcon_fbt@fbc-suspend.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/shard-tglu-5/igt@kms_fbcon_fbt@fbc-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#5161]: https://gitlab.freedesktop.org/drm/intel/issues/5161
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7959]: https://gitlab.freedesktop.org/drm/intel/issues/7959
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
Build changes
-------------
* Linux: CI_DRM_12936 -> Patchwork_115664v2
CI-20190529: 20190529
CI_DRM_12936: 906438caae695f109636f82e2d1845a258f57d8b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7226: 41be8b4ab86f9e11388c10366dfd71e5032589c1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_115664v2: 906438caae695f109636f82e2d1845a258f57d8b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_115664v2/index.html
[-- Attachment #2: Type: text/html, Size: 9093 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-03-27 12:34 ` [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming Mika Kahola
2023-03-29 10:22 ` Govindapillai, Vinod
2023-03-29 15:40 ` Imre Deak
@ 2023-04-03 10:11 ` Imre Deak
2023-04-03 10:19 ` Kahola, Mika
2 siblings, 1 reply; 37+ messages in thread
From: Imre Deak @ 2023-04-03 10:11 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
On Mon, Mar 27, 2023 at 03:34:30PM +0300, Mika Kahola wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
> has a dedicated PIPE 5.2 Message bus for configuration. This message
> bus is used to configure the phy internal registers.
>
> XELPDP has C10 phys to drive output to the EDP and the native output
> from the display engine. Add structures, programming hardware state
> readout logic. Port clock calculations are similar to DG2. Use the DG2
> formulae to calculate the port clock but use the relevant pll signals.
> Note: PHY lane 0 is always used for PLL programming.
>
> Add sequences for C10 phy enable/disable phy lane reset,
> powerdown change sequence and phy lane programming.
>
> Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
Shouldn't the basic MTL DP/HDMI modeset sequences be part of this
patchset? I can't see how things would work otherwise. For DP it is the
"drm/i915/mtl/display: Implement DisplayPort sequences"
patch in the internal tree.
More things below, besides my earlier review comments.
> [...]
> +
> +static void intel_c10_pll_program(struct drm_i915_private *i915,
> + const struct intel_crtc_state *crtc_state,
> + struct intel_encoder *encoder)
> +{
> + const struct intel_c10mpllb_state *pll_state = &crtc_state->c10mpllb_state;
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> + u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
> + INTEL_CX0_LANE0;
> + u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
> + INTEL_CX0_LANE1;
> +
> + int i;
> + struct intel_dp *intel_dp;
> + bool use_ssc = false;
> + u8 cmn0 = 0;
> +
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> + intel_dp = enc_to_intel_dp(encoder);
> + use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> + DP_MAX_DOWNSPREAD_0_5);
> +
> + if (!intel_panel_use_ssc(i915))
> + use_ssc = false;
> +
> + cmn0 = C10_CMN0_DP_VAL;
> + }
> +
> + intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
> + /* Custom width needs to be programmed to 0 for both the phy lanes */
> + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> + PHY_C10_VDR_CUSTOM_WIDTH, 0x3, 0, MB_WRITE_COMMITTED);
> + intel_cx0_rmw(i915, encoder->port, follower_lane, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MASTER_LANE, C10_VDR_CTRL_UPDATE_CFG,
> + MB_WRITE_COMMITTED);
> +
> + /* Program the pll values only for the master lane */
> + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> + /* If not using ssc pll[4] through pll[8] must be 0*/
> + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_PLL(i),
This programs the PLL via the INTEL_CX0_LANE1 lane in the
lane_reversal=true case. However, I haven't found any trace of this
being correct in the spec. It just says that PLL must be programmed via
INTEL_CX0_LANE0 in all the cases, so both for lane_reversal and
!lane_reversal (see Bspec/64539 "Phy Lane and Transmitter Usage"
table/"Lane for message bus PLL programming" column).
> + (!use_ssc && (i > 3 && i < 9)) ? 0 : pll_state->pll[i],
> + (i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED);
> +
> + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
> + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_TX(0), C10_TX0_VAL, MB_WRITE_COMMITTED);
> + intel_cx0_rmw(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MASTER_LANE |
> + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
For all the above writes, programming INTEL_CX0_LANE1 looks incorrect in the
lane_reversal=true case, should program INTEL_CX0_LANE0 instead.
> +}
> +
>
> [...]
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index d1ee8a2fc9cf..15e249f46a64 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -128,4 +128,34 @@
> #define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
> #define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
>
> -#endif /* __INTEL_CX0_PHY_REGS_H__ */
> +/* C10 Vendor Registers */
> +#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
> +#define C10_PLL0_FRACEN REG_BIT8(4)
> +#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
> +#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
> +#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
> +#define C10_CMN0_DP_VAL 0x21
> +#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
> +#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
> +#define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
> +#define C10_TX0_VAL 0x10
> +#define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1)
> +#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2)
> +#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1)
> +#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
> +#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
> +
> +#define CX0_P0_STATE_ACTIVE 0x0
> +#define CX0_P2_STATE_READY 0x2
> +#define CX0_P2PG_STATE_DISABLE 0x9
> +#define CX0_P4PG_STATE_DISABLE 0xC
> +#define CX0_P2_STATE_RESET 0x2
> +
> +/* PHY_C10_VDR_PLL0 */
> +#define PLL_C10_MPLL_SSC_EN REG_BIT8(0)
These should be indented and moved to be under their register
(XELPDP_PORT_BUF_CTL3, PHY_C10_VDR_PLL).
> +
> +/* PIPE SPEC Defined Registers */
> +#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
> +#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
The flag should be indented.
> +
> +#endif /* __INTEL_CX0_REG_DEFS_H__ */
>
> [...]
>
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
> index db26de6b57bc..f9d7c03e95d6 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -22,6 +22,19 @@
> BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
> ((__n) < 0 || (__n) > 31))))
>
> +/**
> + * REG_BIT8() - Prepare a u8 bit value
> + * @__n: 0-based bit number
> + *
> + * Local wrapper for BIT() to force u8, with compile time checks.
> + *
> + * @return: Value with bit @__n set.
> + */
> +#define REG_BIT8(__n) \
> + ((u8)(BIT(__n) + \
> + BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
> + ((__n) < 0 || (__n) > 7))))
> +
> /**
> * REG_GENMASK() - Prepare a continuous u32 bitmask
> * @__high: 0-based high bit
> @@ -52,6 +65,21 @@
> __is_constexpr(__low) && \
> ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
>
> +/**
> + * REG_GENMASK8() - Prepare a continuous u8 bitmask
> + * @__high: 0-based high bit
> + * @__low: 0-based low bit
> + *
> + * Local wrapper for GENMASK() to force u8, with compile time checks.
> + *
> + * @return: Continuous bitmask from @__high to @__low, inclusive.
> + */
> +#define REG_GENMASK8(__high, __low) \
> + ((u8)(GENMASK(__high, __low) + \
> + BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
> + __is_constexpr(__low) && \
> + ((__low) < 0 || (__high) > 7 || (__low) > (__high)))))
> +
> /*
> * Local integer constant expression version of is_power_of_2().
> */
> @@ -74,6 +102,23 @@
> BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
> BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
>
> +/**
> + * REG_FIELD_PREP8() - Prepare a u8 bitfield value
> + * @__mask: shifted mask defining the field's length and position
> + * @__val: value to put in the field
> + *
> + * Local copy of FIELD_PREP8() to generate an integer constant expression, force
The above is FIELD_PREP() only.
> + * u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and REG_GENMASK8().
> + *
> + * @return: @__val masked and shifted into the field defined by @__mask.
> + */
> +#define REG_FIELD_PREP8(__mask, __val) \
> + ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
> + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
> + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) + \
> + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
> + BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
> +
> /**
> * REG_FIELD_GET() - Extract a u32 bitfield value
> * @__mask: shifted mask defining the field's length and position
> @@ -155,6 +200,18 @@
> */
> #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
>
> +/**
> + * REG_FIELD_GET8() - Extract a u8 bitfield value
> + * @__mask: shifted mask defining the field's length and position
> + * @__val: value to extract the bitfield value from
> + *
> + * Local wrapper for FIELD_GET() to force u8 and for consistency with
> + * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
> + *
> + * @return: Masked and shifted value of the field defined by @__mask in @__val.
> + */
> +#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))
> +
> typedef struct {
> u32 reg;
> } i915_reg_t;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-04-03 10:11 ` Imre Deak
@ 2023-04-03 10:19 ` Kahola, Mika
2023-04-03 10:36 ` Imre Deak
0 siblings, 1 reply; 37+ messages in thread
From: Kahola, Mika @ 2023-04-03 10:19 UTC (permalink / raw)
To: Deak, Imre; +Cc: intel-gfx
> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Monday, April 3, 2023 1:12 PM
> To: Kahola, Mika <mika.kahola@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> <radhakrishna.sripada@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Sousa, Gustavo <gustavo.sousa@intel.com>
> Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> and pll programming
>
> On Mon, Mar 27, 2023 at 03:34:30PM +0300, Mika Kahola wrote:
> > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> >
> > XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
> > has a dedicated PIPE 5.2 Message bus for configuration. This message
> > bus is used to configure the phy internal registers.
> >
> > XELPDP has C10 phys to drive output to the EDP and the native output
> > from the display engine. Add structures, programming hardware state
> > readout logic. Port clock calculations are similar to DG2. Use the DG2
> > formulae to calculate the port clock but use the relevant pll signals.
> > Note: PHY lane 0 is always used for PLL programming.
> >
> > Add sequences for C10 phy enable/disable phy lane reset, powerdown
> > change sequence and phy lane programming.
> >
> > Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
>
> Shouldn't the basic MTL DP/HDMI modeset sequences be part of this patchset? I
> can't see how things would work otherwise. For DP it is the
>
> "drm/i915/mtl/display: Implement DisplayPort sequences"
>
> patch in the internal tree.
The idea was to get the eDP supported with this C10 series. We could go back to the original form and have all C10/C20/TBT patches in one series.
>
> More things below, besides my earlier review comments.
>
> > [...]
> > +
> > +static void intel_c10_pll_program(struct drm_i915_private *i915,
> > + const struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder)
> > +{
> > + const struct intel_c10mpllb_state *pll_state = &crtc_state-
> >c10mpllb_state;
> > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > + bool lane_reversal = dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
> > + u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
> > + INTEL_CX0_LANE0;
> > + u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
> > + INTEL_CX0_LANE1;
> > +
> > + int i;
> > + struct intel_dp *intel_dp;
> > + bool use_ssc = false;
> > + u8 cmn0 = 0;
> > +
> > + if (intel_crtc_has_dp_encoder(crtc_state)) {
> > + intel_dp = enc_to_intel_dp(encoder);
> > + use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> > + DP_MAX_DOWNSPREAD_0_5);
> > +
> > + if (!intel_panel_use_ssc(i915))
> > + use_ssc = false;
> > +
> > + cmn0 = C10_CMN0_DP_VAL;
> > + }
> > +
> > + intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> > + C10_VDR_CTRL_MSGBUS_ACCESS,
> MB_WRITE_COMMITTED);
> > + /* Custom width needs to be programmed to 0 for both the phy lanes */
> > + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> > + PHY_C10_VDR_CUSTOM_WIDTH, 0x3, 0,
> MB_WRITE_COMMITTED);
> > + intel_cx0_rmw(i915, encoder->port, follower_lane,
> PHY_C10_VDR_CONTROL(1),
> > + C10_VDR_CTRL_MASTER_LANE,
> C10_VDR_CTRL_UPDATE_CFG,
> > + MB_WRITE_COMMITTED);
> > +
> > + /* Program the pll values only for the master lane */
> > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > + /* If not using ssc pll[4] through pll[8] must be 0*/
> > + intel_cx0_write(i915, encoder->port, master_lane,
> > +PHY_C10_VDR_PLL(i),
>
> This programs the PLL via the INTEL_CX0_LANE1 lane in the lane_reversal=true
> case. However, I haven't found any trace of this being correct in the spec. It just
> says that PLL must be programmed via
> INTEL_CX0_LANE0 in all the cases, so both for lane_reversal and !lane_reversal
> (see Bspec/64539 "Phy Lane and Transmitter Usage"
> table/"Lane for message bus PLL programming" column).
>
> > + (!use_ssc && (i > 3 && i < 9)) ? 0 : pll_state-
> >pll[i],
> > + (i % 4) ? MB_WRITE_UNCOMMITTED :
> MB_WRITE_COMMITTED);
> > +
> > + intel_cx0_write(i915, encoder->port, master_lane,
> PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
> > + intel_cx0_write(i915, encoder->port, master_lane,
> PHY_C10_VDR_TX(0), C10_TX0_VAL, MB_WRITE_COMMITTED);
> > + intel_cx0_rmw(i915, encoder->port, master_lane,
> PHY_C10_VDR_CONTROL(1),
> > + C10_VDR_CTRL_MSGBUS_ACCESS,
> C10_VDR_CTRL_MASTER_LANE |
> > + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
>
> For all the above writes, programming INTEL_CX0_LANE1 looks incorrect in the
> lane_reversal=true case, should program INTEL_CX0_LANE0 instead.
So in any case we should program INTEL_CX0_LANE0?
>
> > +}
> > +
> >
> > [...]
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > index d1ee8a2fc9cf..15e249f46a64 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > @@ -128,4 +128,34 @@
> > #define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
> > #define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
> >
> > -#endif /* __INTEL_CX0_PHY_REGS_H__ */
> > +/* C10 Vendor Registers */
> > +#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
> > +#define C10_PLL0_FRACEN REG_BIT8(4)
> > +#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
> > +#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
> > +#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
> > +#define C10_CMN0_DP_VAL 0x21
> > +#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
> > +#define C10_CMN3_TXVBOOST(val)
> REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
> > +#define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
> > +#define C10_TX0_VAL 0x10
> > +#define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1)
> > +#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2)
> > +#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1)
> > +#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
> > +#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
> > +
> > +#define CX0_P0_STATE_ACTIVE 0x0
> > +#define CX0_P2_STATE_READY 0x2
> > +#define CX0_P2PG_STATE_DISABLE 0x9
> > +#define CX0_P4PG_STATE_DISABLE 0xC
> > +#define CX0_P2_STATE_RESET 0x2
> > +
> > +/* PHY_C10_VDR_PLL0 */
> > +#define PLL_C10_MPLL_SSC_EN REG_BIT8(0)
>
> These should be indented and moved to be under their register
> (XELPDP_PORT_BUF_CTL3, PHY_C10_VDR_PLL).
Ok. Let's move these to correct places.
>
> > +
> > +/* PIPE SPEC Defined Registers */
> > +#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 +
> (control))
> > +#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
>
> The flag should be indented.
Ok.
>
> > +
> > +#endif /* __INTEL_CX0_REG_DEFS_H__ */
> >
> > [...]
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
> > b/drivers/gpu/drm/i915/i915_reg_defs.h
> > index db26de6b57bc..f9d7c03e95d6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> > +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> > @@ -22,6 +22,19 @@
> > BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
> > ((__n) < 0 || (__n) > 31))))
> >
> > +/**
> > + * REG_BIT8() - Prepare a u8 bit value
> > + * @__n: 0-based bit number
> > + *
> > + * Local wrapper for BIT() to force u8, with compile time checks.
> > + *
> > + * @return: Value with bit @__n set.
> > + */
> > +#define REG_BIT8(__n) \
> > + ((u8)(BIT(__n) + \
> > + BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
> > + ((__n) < 0 || (__n) > 7))))
> > +
> > /**
> > * REG_GENMASK() - Prepare a continuous u32 bitmask
> > * @__high: 0-based high bit
> > @@ -52,6 +65,21 @@
> > __is_constexpr(__low) && \
> > ((__low) < 0 || (__high) > 63 || (__low) >
> (__high)))))
> >
> > +/**
> > + * REG_GENMASK8() - Prepare a continuous u8 bitmask
> > + * @__high: 0-based high bit
> > + * @__low: 0-based low bit
> > + *
> > + * Local wrapper for GENMASK() to force u8, with compile time checks.
> > + *
> > + * @return: Continuous bitmask from @__high to @__low, inclusive.
> > + */
> > +#define REG_GENMASK8(__high, __low) \
> > + ((u8)(GENMASK(__high, __low) + \
> > + BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
> > + __is_constexpr(__low) && \
> > + ((__low) < 0 || (__high) > 7 || (__low) >
> (__high)))))
> > +
> > /*
> > * Local integer constant expression version of is_power_of_2().
> > */
> > @@ -74,6 +102,23 @@
> > BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL <<
> __bf_shf(__mask)))) + \
> >
> > BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val),
> > (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
> >
> > +/**
> > + * REG_FIELD_PREP8() - Prepare a u8 bitfield value
> > + * @__mask: shifted mask defining the field's length and position
> > + * @__val: value to put in the field
> > + *
> > + * Local copy of FIELD_PREP8() to generate an integer constant
> > +expression, force
>
> The above is FIELD_PREP() only.
So use FIELD_PREP() instead of FIELD_PREP8()?
>
> > + * u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and
> REG_GENMASK8().
> > + *
> > + * @return: @__val masked and shifted into the field defined by @__mask.
> > + */
> > +#define REG_FIELD_PREP8(__mask, __val) \
> > + ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
> > + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
> > + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) +
> \
> > + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL <<
> __bf_shf(__mask)))) + \
> > +
> > +BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val),
> > +(~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
> > +
> > /**
> > * REG_FIELD_GET() - Extract a u32 bitfield value
> > * @__mask: shifted mask defining the field's length and position @@
> > -155,6 +200,18 @@
> > */
> > #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__
> > })[__index])
> >
> > +/**
> > + * REG_FIELD_GET8() - Extract a u8 bitfield value
> > + * @__mask: shifted mask defining the field's length and position
> > + * @__val: value to extract the bitfield value from
> > + *
> > + * Local wrapper for FIELD_GET() to force u8 and for consistency with
> > + * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
> > + *
> > + * @return: Masked and shifted value of the field defined by @__mask in
> @__val.
> > + */
> > +#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))
> > +
> > typedef struct {
> > u32 reg;
> > } i915_reg_t;
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 5/7] drm/i915/mtl: Add C10 phy programming for HDMI
2023-03-27 12:34 ` [Intel-gfx] [PATCH 5/7] drm/i915/mtl: Add C10 phy programming for HDMI Mika Kahola
@ 2023-04-03 10:26 ` Imre Deak
0 siblings, 0 replies; 37+ messages in thread
From: Imre Deak @ 2023-04-03 10:26 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
On Mon, Mar 27, 2023 at 03:34:31PM +0300, Mika Kahola wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> Like DG2, we still don't have a proper algorithm that can be used
> for calculating PHY settings, but we do have tables of register
> values for a handful of the more common link rates. Some support is
> better than none, so let's go ahead and add/use these tables when we
> can, and also add some logic to hdmi_port_clock_valid() to filter the
> modelist to just the modes we can actually support with these link
> rates.
>
> Hopefully we'll have a proper / non-encumbered algorithm to calculate
> these registers by the time we upstream and we'll be able to replace
> this patch with something more general purpose.
>
> Bspec: 64568
>
> v2: Rebasing with Clint's HDMI C10 PLL tables (Mika)
> v3: Add missing use_hdmi checks from Clint's HDMI implementation changes (Ankit)
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 576 +++++++++++++++++-
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 13 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 5 +-
> 4 files changed, 579 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index ced8c8aa6c82..3aa8031f8373 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -485,6 +485,538 @@ static const struct intel_c10mpllb_state * const mtl_c10_edp_tables[] = {
> NULL,
> };
>
> +/*
> + * HDMI link rates with 38.4 MHz reference clock.
> + */
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_25_2 = {
> + .clock = 25200,
> + .pll[0] = 0x4,
> + .pll[1] = 0,
> + .pll[2] = 0xB2,
> + .pll[3] = 0,
> + .pll[4] = 0,
> + .pll[5] = 0,
> + .pll[6] = 0,
> + .pll[7] = 0,
> + .pll[8] = 0x20,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0xD,
> + .pll[16] = 0x6,
> + .pll[17] = 0x8F,
> + .pll[18] = 0x84,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_27_0 = {
> + .clock = 27000,
> + .pll[0] = 0x34,
> + .pll[1] = 0,
> + .pll[2] = 0xC0,
> + .pll[3] = 0,
> + .pll[4] = 0,
> + .pll[5] = 0,
> + .pll[6] = 0,
> + .pll[7] = 0,
> + .pll[8] = 0x20,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0x80,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0xD,
> + .pll[16] = 0x6,
> + .pll[17] = 0xCF,
> + .pll[18] = 0x84,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_74_25 = {
> + .clock = 74250,
> + .pll[0] = 0xF4,
> + .pll[1] = 0,
> + .pll[2] = 0x7A,
> + .pll[3] = 0,
> + .pll[4] = 0,
> + .pll[5] = 0,
> + .pll[6] = 0,
> + .pll[7] = 0,
> + .pll[8] = 0x20,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0x58,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0xB,
> + .pll[16] = 0x6,
> + .pll[17] = 0xF,
> + .pll[18] = 0x85,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_148_5 = {
> + .clock = 148500,
> + .pll[0] = 0xF4,
> + .pll[1] = 0,
> + .pll[2] = 0x7A,
> + .pll[3] = 0,
> + .pll[4] = 0,
> + .pll[5] = 0,
> + .pll[6] = 0,
> + .pll[7] = 0,
> + .pll[8] = 0x20,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0x58,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0xA,
> + .pll[16] = 0x6,
> + .pll[17] = 0xF,
> + .pll[18] = 0x85,
> + .pll[19] = 0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_594 = {
> + .clock = 594000,
> + .pll[0] = 0xF4,
> + .pll[1] = 0,
> + .pll[2] = 0x7A,
> + .pll[3] = 0,
> + .pll[4] = 0,
> + .pll[5] = 0,
> + .pll[6] = 0,
> + .pll[7] = 0,
> + .pll[8] = 0x20,
> + .pll[9] = 0x1,
> + .pll[10] = 0,
> + .pll[11] = 0,
> + .pll[12] = 0x58,
> + .pll[13] = 0,
> + .pll[14] = 0,
> + .pll[15] = 0x8,
> + .pll[16] = 0x6,
> + .pll[17] = 0xF,
> + .pll[18] = 0x85,
> + .pll[19] = 0x23,
> +};
> +
> +/* Precomputed C10 HDMI PLL tables */
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_25175 = {
> + .clock = 25175,
> + .pll[0]=0x34,
> + .pll[1]=0x00,
> + .pll[2]=0xB0,
> + .pll[3]=0x00,
> + .pll[4]=0x00,
> + .pll[5]=0x00,
> + .pll[6]=0x00,
> + .pll[7]=0x00,
> + .pll[8]=0x20,
> + .pll[9]=0xFF,
> + .pll[10]=0xFF,
> + .pll[11]=0x55,
> + .pll[12]=0xE5,
> + .pll[13]=0x55,
> + .pll[14]=0x55,
> + .pll[15]=0x0D,
> + .pll[16]=0x09,
> + .pll[17]=0x8F,
> + .pll[18]=0x84,
> + .pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_27027 = {
> + .clock = 27027,
> + .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0xCC,.pll[12]=0x9C,.pll[13]=0xCB,.pll[14]=0xCC,
> + .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
These tables should have the same formatting, also matching the
formatting of the C20 tables.
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_28320 = {
> + .clock = 28320,
> + .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xCC, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_30240 = {
> + .clock = 30240,
> + .pll[0]=0x04, .pll[1]=0x00, .pll[2]=0xDC, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0D,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_31500 = {
> + .clock = 31500,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x62, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xA0,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0C,.pll[16]=0x09,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_36000 = {
> + .clock = 36000,
> + .pll[0]=0xC4, .pll[1]=0x00, .pll[2]=0x76, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x00,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_40000 = {
> + .clock = 40000,
> + .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x55,.pll[13]=0x55,.pll[14]=0x55,
> + .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_49500 = {
> + .clock = 49500,
> + .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_50000 = {
> + .clock = 50000,
> + .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xB0, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x2A,.pll[13]=0xA9,.pll[14]=0xAA,
> + .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_57284 = {
> + .clock = 57284,
> + .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xCE, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x77,.pll[12]=0x57,.pll[13]=0x77,.pll[14]=0x77,
> + .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_58000 = {
> + .clock = 58000,
> + .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xD5,.pll[13]=0x55,.pll[14]=0x55,
> + .pll[15]=0x0C,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_65000 = {
> + .clock = 65000,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x66, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xB5,.pll[13]=0x55,.pll[14]=0x55,
> + .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_71000 = {
> + .clock = 71000,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x72, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
> + .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_74176 = {
> + .clock = 74176,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x44,.pll[12]=0x44,.pll[13]=0x44,.pll[14]=0x44,
> + .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_75000 = {
> + .clock = 75000,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7C, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_78750 = {
> + .clock = 78750,
> + .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x84, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x08,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_85500 = {
> + .clock = 85500,
> + .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x92, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x10,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_88750 = {
> + .clock = 88750,
> + .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0x98, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x72,.pll[13]=0xA9,.pll[14]=0xAA,
> + .pll[15]=0x0B,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_106500 = {
> + .clock = 106500,
> + .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xBC, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xF0,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_108000 = {
> + .clock = 108000,
> + .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xC0, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x80,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_115500 = {
> + .clock = 115500,
> + .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD0, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x50,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_119000 = {
> + .clock = 119000,
> + .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xD6, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xF5,.pll[13]=0x55,.pll[14]=0x55,
> + .pll[15]=0x0B,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_135000 = {
> + .clock = 135000,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x6C, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x50,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0A,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_138500 = {
> + .clock = 138500,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x70, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x22,.pll[13]=0xA9,.pll[14]=0xAA,
> + .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_147160 = {
> + .clock = 147160,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x78, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0xA5,.pll[13]=0x55,.pll[14]=0x55,
> + .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_148352 = {
> + .clock = 148352,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x44,.pll[12]=0x44,.pll[13]=0x44,.pll[14]=0x44,
> + .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_154000 = {
> + .clock = 154000,
> + .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x80, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x35,.pll[13]=0x55,.pll[14]=0x55,
> + .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_162000 = {
> + .clock = 162000,
> + .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x88, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x60,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_167000 = {
> + .clock = 167000,
> + .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x8C, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0xFA,.pll[13]=0xA9,.pll[14]=0xAA,
> + .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_197802 = {
> + .clock = 197802,
> + .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x99,.pll[12]=0x05,.pll[13]=0x98,.pll[14]=0x99,
> + .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_198000 = {
> + .clock = 198000,
> + .pll[0]=0x74, .pll[1]=0x00, .pll[2]=0xAE, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x20,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_209800 = {
> + .clock = 209800,
> + .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xBA, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x45,.pll[13]=0x55,.pll[14]=0x55,
> + .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_241500 = {
> + .clock = 241500,
> + .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xDA, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xC8,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x0A,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_262750 = {
> + .clock = 262750,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x68, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x6C,.pll[13]=0xA9,.pll[14]=0xAA,
> + .pll[15]=0x09,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_268500 = {
> + .clock = 268500,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x6A, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0xEC,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x09,.pll[16]=0x09,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_296703 = {
> + .clock = 296703,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x33,.pll[12]=0x44,.pll[13]=0x33,.pll[14]=0x33,
> + .pll[15]=0x09,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_297000 = {
> + .clock = 297000,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x00,.pll[12]=0x58,.pll[13]=0x00,.pll[14]=0x00,
> + .pll[15]=0x09,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_319750 = {
> + .clock = 319750,
> + .pll[0]=0xB4, .pll[1]=0x00, .pll[2]=0x86, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0xAA,.pll[12]=0x44,.pll[13]=0xA9,.pll[14]=0xAA,
> + .pll[15]=0x09,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_497750 = {
> + .clock = 497750,
> + .pll[0]=0x34, .pll[1]=0x00, .pll[2]=0xE2, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x9F,.pll[13]=0x55,.pll[14]=0x55,
> + .pll[15]=0x09,.pll[16]=0x08,.pll[17]=0xCF,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_592000 = {
> + .clock = 592000,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x55,.pll[12]=0x15,.pll[13]=0x55,.pll[14]=0x55,
> + .pll[15]=0x08,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state mtl_c10_hdmi_593407 = {
> + .clock = 593407,
> + .pll[0]=0xF4, .pll[1]=0x00, .pll[2]=0x7A, .pll[3]=0x00, .pll[4]=0x00,
> + .pll[5]=0x00, .pll[6]=0x00, .pll[7]=0x00, .pll[8]=0x20, .pll[9]=0xFF,
> + .pll[10]=0xFF,.pll[11]=0x3B,.pll[12]=0x44,.pll[13]=0xBA,.pll[14]=0xBB,
> + .pll[15]=0x08,.pll[16]=0x08,.pll[17]=0x8F,.pll[18]=0x84,.pll[19]=0x23,
> +};
> +
> +static const struct intel_c10mpllb_state * const mtl_c10_hdmi_tables[] = {
> + &mtl_c10_hdmi_25175,
> + &mtl_c10_hdmi_25_2, /* Consolidated Table */
> + &mtl_c10_hdmi_27_0, /* Consolidated Table */
> + &mtl_c10_hdmi_27027,
> + &mtl_c10_hdmi_28320,
> + &mtl_c10_hdmi_30240,
> + &mtl_c10_hdmi_31500,
> + &mtl_c10_hdmi_36000,
> + &mtl_c10_hdmi_40000,
> + &mtl_c10_hdmi_49500,
> + &mtl_c10_hdmi_50000,
> + &mtl_c10_hdmi_57284,
> + &mtl_c10_hdmi_58000,
> + &mtl_c10_hdmi_65000,
> + &mtl_c10_hdmi_71000,
> + &mtl_c10_hdmi_74176,
> + &mtl_c10_hdmi_74_25, /* Consolidated Table */
> + &mtl_c10_hdmi_75000,
> + &mtl_c10_hdmi_78750,
> + &mtl_c10_hdmi_85500,
> + &mtl_c10_hdmi_88750,
> + &mtl_c10_hdmi_106500,
> + &mtl_c10_hdmi_108000,
> + &mtl_c10_hdmi_115500,
> + &mtl_c10_hdmi_119000,
> + &mtl_c10_hdmi_135000,
> + &mtl_c10_hdmi_138500,
> + &mtl_c10_hdmi_147160,
> + &mtl_c10_hdmi_148352,
> + &mtl_c10_hdmi_148_5, /* Consolidated Table */
> + &mtl_c10_hdmi_154000,
> + &mtl_c10_hdmi_162000,
> + &mtl_c10_hdmi_167000,
> + &mtl_c10_hdmi_197802,
> + &mtl_c10_hdmi_198000,
> + &mtl_c10_hdmi_209800,
> + &mtl_c10_hdmi_241500,
> + &mtl_c10_hdmi_262750,
> + &mtl_c10_hdmi_268500,
> + &mtl_c10_hdmi_296703,
> + &mtl_c10_hdmi_297000,
> + &mtl_c10_hdmi_319750,
> + &mtl_c10_hdmi_497750,
> + &mtl_c10_hdmi_592000,
> + &mtl_c10_hdmi_593407,
> + &mtl_c10_hdmi_594, /* Consolidated Table */
> + NULL,
> +};
> +
> +int intel_c10_phy_check_hdmi_link_rate(int clock)
> +{
> + const struct intel_c10mpllb_state * const *tables = mtl_c10_hdmi_tables;
> + int i;
> +
> + for (i = 0; tables[i]; i++) {
> + if (clock == tables[i]->clock)
> + return MODE_OK;
> + }
> +
> + return MODE_CLOCK_RANGE;
> +}
> +
> static const struct intel_c10mpllb_state * const *
> intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder)
> @@ -494,9 +1026,10 @@ intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
> return mtl_c10_edp_tables;
> else
> return mtl_c10_dp_tables;
> + } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> + return mtl_c10_hdmi_tables;
> }
>
> - /* TODO: Add HDMI Support */
> MISSING_CASE(encoder->type);
> return NULL;
> }
> @@ -504,9 +1037,20 @@ intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
> static int intel_c10mpllb_calc_state(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder)
> {
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> const struct intel_c10mpllb_state * const *tables;
> + enum phy phy = intel_port_to_phy(i915, encoder->port);
> int i;
>
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> + if (intel_c10_phy_check_hdmi_link_rate(crtc_state->port_clock)
> + != MODE_OK) {
> + drm_dbg_kms(&i915->drm, "Can't support HDMI link rate %d on phy %c.\n",
> + crtc_state->port_clock, phy_name(phy));
> + return -EINVAL;
> + }
> + }
The above is redundant if the table selection later is fixed to check
for an exact match between crtc_state->port_clock and tables[i].clock.
> +
> tables = intel_c10_mpllb_tables_get(crtc_state, encoder);
> if (!tables)
> return -EINVAL;
> @@ -558,9 +1102,10 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0));
> tx0 = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0));
>
> - if (tx0 != C10_TX0_VAL || cmn != C10_CMN0_DP_VAL)
> - drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
> - tx0, cmn, phy_name(phy));
> + if (tx0 != C10_TX0_VAL || (cmn != C10_CMN0_DP_VAL &&
> + cmn != C10_CMN0_HDMI_VAL))
> + drm_dbg_kms(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
> + tx0, cmn, phy_name(phy));
This should just read out the cmn0 and tx0 registers and store them to
pll_state, while the check should be done in
intel_c10mpllb_state_verify().
> }
>
> static void intel_c10_pll_program(struct drm_i915_private *i915,
> @@ -574,11 +1119,11 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
> INTEL_CX0_LANE0;
> u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
> INTEL_CX0_LANE1;
> -
> int i;
> struct intel_dp *intel_dp;
> bool use_ssc = false;
> - u8 cmn0 = 0;
> + bool use_hdmi = false;
> + u8 cmn0;
>
> if (intel_crtc_has_dp_encoder(crtc_state)) {
> intel_dp = enc_to_intel_dp(encoder);
> @@ -589,6 +1134,9 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
> use_ssc = false;
>
> cmn0 = C10_CMN0_DP_VAL;
> + } else {
> + use_hdmi = true;
> + cmn0 = C10_CMN0_HDMI_VAL;
This should be set up with the rest of pll values and the tx0 value in
intel_c10mpllb_calc_state(), storing them to
crtc_state->cx0pll_state.c10mpllb_state, while this function should just
program these to their registers.
> }
>
> intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> @@ -604,7 +1152,7 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
> for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> /* If not using ssc pll[4] through pll[8] must be 0*/
> intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_PLL(i),
> - (!use_ssc && (i > 3 && i < 9)) ? 0 : pll_state->pll[i],
> + (!(use_ssc || use_hdmi) && (i > 3 && i < 9)) ? 0 : pll_state->pll[i],
Same as above.
> (i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED);
>
> intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
> @@ -652,7 +1200,8 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
> const struct intel_c10mpllb_state *pll_state)
> {
> unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> - unsigned int multiplier, tx_clk_div, refclk = 38400;
> + unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
> + int tmpclk = 0;
>
> if (pll_state->pll[0] & C10_PLL0_FRACEN) {
> frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
> @@ -664,10 +1213,14 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
> pll_state->pll[2]) / 2 + 16;
>
> tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
> + hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
>
> - return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
> + tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
> DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
> 10 << (tx_clk_div + 16));
> + tmpclk *= (hdmi_div ? 2 : 1);
> +
> + return tmpclk;
> }
>
> static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> @@ -1080,6 +1633,7 @@ void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
> enum phy phy;
> int i;
> bool use_ssc = false;
> + bool use_hdmi = false;
>
> if (DISPLAY_VER(i915) < 14)
> return;
> @@ -1097,6 +1651,8 @@ void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
>
> if (!intel_panel_use_ssc(i915))
> use_ssc = false;
> + } else {
> + use_hdmi = true;
> }
The above should rely only on the HW state, not the SW new_crtc_state.
To deduct the HDMI/DP mode C10_PLL15_HDMIDIV_MASK/pll_state->pll[15] can
be used.
>
> if (!intel_is_c10phy(i915, phy))
The above should be earlier in the function.
> @@ -1107,7 +1663,7 @@ void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
> for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {
> u8 expected;
>
> - if (!use_ssc && i > 3 && i < 9)
> + if (!(use_ssc || use_hdmi) && i > 3 && i < 9)
The above should be handled already in intel_c10mpllb_calc_state().
> expected = 0;
> else
> expected = mpllb_sw_state->pll[i];
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 8cf340509097..f8023f240727 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -39,5 +39,6 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
> const struct intel_c10mpllb_state *pll_state);
> void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
> struct intel_crtc_state *new_crtc_state);
> +int intel_c10_phy_check_hdmi_link_rate(int clock);
>
> #endif /* __INTEL_CX0_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 15e249f46a64..91e2f88f43f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -133,8 +133,11 @@
> #define C10_PLL0_FRACEN REG_BIT8(4)
> #define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
> #define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
> +#define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3)
> +
> #define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
> #define C10_CMN0_DP_VAL 0x21
> +#define C10_CMN0_HDMI_VAL 0x1
The above should be defined using the actual register field
names/values, instead of hard-coding the whole register value.
> #define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
> #define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
> #define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
> @@ -145,11 +148,11 @@
> #define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
> #define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
>
> -#define CX0_P0_STATE_ACTIVE 0x0
> -#define CX0_P2_STATE_READY 0x2
> -#define CX0_P2PG_STATE_DISABLE 0x9
> -#define CX0_P4PG_STATE_DISABLE 0xC
> -#define CX0_P2_STATE_RESET 0x2
> +#define CX0_P0_STATE_ACTIVE 0x0
> +#define CX0_P2_STATE_READY 0x2
> +#define CX0_P2PG_STATE_DISABLE 0x9
> +#define CX0_P4PG_STATE_DISABLE 0xC
> +#define CX0_P2_STATE_RESET 0x2
Looks like a w/s fixup, to be done already in the patch where the flags
were added.
>
> /* PHY_C10_VDR_PLL0 */
> #define PLL_C10_MPLL_SSC_EN REG_BIT8(0)
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index c7e9e1fbed37..baa9ef7568af 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -46,6 +46,7 @@
> #include "intel_atomic.h"
> #include "intel_audio.h"
> #include "intel_connector.h"
> +#include "intel_cx0_phy.h"
> #include "intel_ddi.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> @@ -1865,7 +1866,9 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
> * FIXME: We will hopefully get an algorithmic way of programming
> * the MPLLB for HDMI in the future.
> */
> - if (IS_DG2(dev_priv))
> + if (IS_METEORLAKE(dev_priv))
> + return intel_c10_phy_check_hdmi_link_rate(clock);
> + else if (IS_DG2(dev_priv))
> return intel_snps_phy_check_hdmi_link_rate(clock);
>
> return MODE_OK;
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-04-03 10:19 ` Kahola, Mika
@ 2023-04-03 10:36 ` Imre Deak
2023-04-03 10:43 ` Kahola, Mika
0 siblings, 1 reply; 37+ messages in thread
From: Imre Deak @ 2023-04-03 10:36 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx
On Mon, Apr 03, 2023 at 01:19:48PM +0300, Kahola, Mika wrote:
> > -----Original Message-----
> > From: Deak, Imre <imre.deak@intel.com>
> > Sent: Monday, April 3, 2023 1:12 PM
> > To: Kahola, Mika <mika.kahola@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> > <radhakrishna.sripada@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> > Sousa, Gustavo <gustavo.sousa@intel.com>
> > Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> > and pll programming
> >
> > On Mon, Mar 27, 2023 at 03:34:30PM +0300, Mika Kahola wrote:
> > > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > >
> > > XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
> > > has a dedicated PIPE 5.2 Message bus for configuration. This message
> > > bus is used to configure the phy internal registers.
> > >
> > > XELPDP has C10 phys to drive output to the EDP and the native output
> > > from the display engine. Add structures, programming hardware state
> > > readout logic. Port clock calculations are similar to DG2. Use the DG2
> > > formulae to calculate the port clock but use the relevant pll signals.
> > > Note: PHY lane 0 is always used for PLL programming.
> > >
> > > Add sequences for C10 phy enable/disable phy lane reset, powerdown
> > > change sequence and phy lane programming.
> > >
> > > Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
> >
> > Shouldn't the basic MTL DP/HDMI modeset sequences be part of this patchset? I
> > can't see how things would work otherwise. For DP it is the
> >
> > "drm/i915/mtl/display: Implement DisplayPort sequences"
> >
> > patch in the internal tree.
>
> The idea was to get the eDP supported with this C10 series. We could
> go back to the original form and have all C10/C20/TBT patches in one
> series.
As this series enables eDP and HDMI on C10, the parts that make this
working should be in this patchset imo. C20 and TBT doesn't need to be,
but I don't see how eDP or HDMI on C10 would work if the modeset
sequence used for both C10 and C20 and both DP and HDMI modes is not
updated for MTL.
> > More things below, besides my earlier review comments.
> >
> > > [...]
> > > +
> > > +static void intel_c10_pll_program(struct drm_i915_private *i915,
> > > + const struct intel_crtc_state *crtc_state,
> > > + struct intel_encoder *encoder)
> > > +{
> > > + const struct intel_c10mpllb_state *pll_state = &crtc_state->c10mpllb_state;
> > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> > > + u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
> > > + INTEL_CX0_LANE0;
> > > + u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
> > > + INTEL_CX0_LANE1;
> > > +
> > > + int i;
> > > + struct intel_dp *intel_dp;
> > > + bool use_ssc = false;
> > > + u8 cmn0 = 0;
> > > +
> > > + if (intel_crtc_has_dp_encoder(crtc_state)) {
> > > + intel_dp = enc_to_intel_dp(encoder);
> > > + use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> > > + DP_MAX_DOWNSPREAD_0_5);
> > > +
> > > + if (!intel_panel_use_ssc(i915))
> > > + use_ssc = false;
> > > +
> > > + cmn0 = C10_CMN0_DP_VAL;
> > > + }
> > > +
> > > + intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> > > + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
> > > + /* Custom width needs to be programmed to 0 for both the phy lanes */
> > > + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> > > + PHY_C10_VDR_CUSTOM_WIDTH, 0x3, 0, MB_WRITE_COMMITTED);
> > > + intel_cx0_rmw(i915, encoder->port, follower_lane, PHY_C10_VDR_CONTROL(1),
> > > + C10_VDR_CTRL_MASTER_LANE, C10_VDR_CTRL_UPDATE_CFG,
> > > + MB_WRITE_COMMITTED);
> > > +
> > > + /* Program the pll values only for the master lane */
> > > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > > + /* If not using ssc pll[4] through pll[8] must be 0*/
> > > + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_PLL(i),
> >
> > This programs the PLL via the INTEL_CX0_LANE1 lane in the lane_reversal=true
> > case. However, I haven't found any trace of this being correct in the spec. It just
> > says that PLL must be programmed via
> > INTEL_CX0_LANE0 in all the cases, so both for lane_reversal and !lane_reversal
> > (see Bspec/64539 "Phy Lane and Transmitter Usage"
> > table/"Lane for message bus PLL programming" column).
> >
> > > + (!use_ssc && (i > 3 && i < 9)) ? 0 : pll_state->pll[i],
> > > + (i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED);
> > > +
> > > + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
> > > + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_TX(0), C10_TX0_VAL, MB_WRITE_COMMITTED);
> > > + intel_cx0_rmw(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
> > > + C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MASTER_LANE |
> > > + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> >
> > For all the above writes, programming INTEL_CX0_LANE1 looks incorrect in the
> > lane_reversal=true case, should program INTEL_CX0_LANE0 instead.
>
> So in any case we should program INTEL_CX0_LANE0?
That's what the spec says at least, so I don't see a reason to not
follow that.
> [...]
> > > +
> > > /*
> > > * Local integer constant expression version of is_power_of_2().
> > > */
> > > @@ -74,6 +102,23 @@
> > > BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
> > >
> > > BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val),
> > > (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
> > >
> > > +/**
> > > + * REG_FIELD_PREP8() - Prepare a u8 bitfield value
> > > + * @__mask: shifted mask defining the field's length and position
> > > + * @__val: value to put in the field
> > > + *
> > > + * Local copy of FIELD_PREP8() to generate an integer constant expression, force
> >
> > The above is FIELD_PREP() only.
>
> So use FIELD_PREP() instead of FIELD_PREP8()?
Yes, there is no FIELD_PREP8(), so I assume the reference was about
FIELD_PREP().
--Imre
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-04-03 10:36 ` Imre Deak
@ 2023-04-03 10:43 ` Kahola, Mika
0 siblings, 0 replies; 37+ messages in thread
From: Kahola, Mika @ 2023-04-03 10:43 UTC (permalink / raw)
To: Deak, Imre; +Cc: intel-gfx
> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Monday, April 3, 2023 1:36 PM
> To: Kahola, Mika <mika.kahola@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> <radhakrishna.sripada@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Sousa, Gustavo <gustavo.sousa@intel.com>
> Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> and pll programming
>
> On Mon, Apr 03, 2023 at 01:19:48PM +0300, Kahola, Mika wrote:
> > > -----Original Message-----
> > > From: Deak, Imre <imre.deak@intel.com>
> > > Sent: Monday, April 3, 2023 1:12 PM
> > > To: Kahola, Mika <mika.kahola@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> > > <radhakrishna.sripada@intel.com>; Shankar, Uma
> > > <uma.shankar@intel.com>; Sousa, Gustavo <gustavo.sousa@intel.com>
> > > Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY
> > > message bus and pll programming
> > >
> > > On Mon, Mar 27, 2023 at 03:34:30PM +0300, Mika Kahola wrote:
> > > > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > >
> > > > XELPDP has C10 and C20 phys from Synopsys to drive displays. Each
> > > > phy has a dedicated PIPE 5.2 Message bus for configuration. This
> > > > message bus is used to configure the phy internal registers.
> > > >
> > > > XELPDP has C10 phys to drive output to the EDP and the native
> > > > output from the display engine. Add structures, programming
> > > > hardware state readout logic. Port clock calculations are similar
> > > > to DG2. Use the DG2 formulae to calculate the port clock but use the
> relevant pll signals.
> > > > Note: PHY lane 0 is always used for PLL programming.
> > > >
> > > > Add sequences for C10 phy enable/disable phy lane reset, powerdown
> > > > change sequence and phy lane programming.
> > > >
> > > > Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610,
> > > > 67636
> > >
> > > Shouldn't the basic MTL DP/HDMI modeset sequences be part of this
> > > patchset? I can't see how things would work otherwise. For DP it is
> > > the
> > >
> > > "drm/i915/mtl/display: Implement DisplayPort sequences"
> > >
> > > patch in the internal tree.
> >
> > The idea was to get the eDP supported with this C10 series. We could
> > go back to the original form and have all C10/C20/TBT patches in one
> > series.
>
> As this series enables eDP and HDMI on C10, the parts that make this working
> should be in this patchset imo. C20 and TBT doesn't need to be, but I don't see
> how eDP or HDMI on C10 would work if the modeset sequence used for both
> C10 and C20 and both DP and HDMI modes is not updated for MTL.
The whole split is a bit artificial as it was really hard to get any reviews done for the whole series. But you are right, the hdmi is not needed to eDP support. Maybe for the next round, I drop these hdmi related patches out from the C10 series so we can get only eDP support reviewed and merged at some point.
>
> > > More things below, besides my earlier review comments.
> > >
> > > > [...]
> > > > +
> > > > +static void intel_c10_pll_program(struct drm_i915_private *i915,
> > > > + const struct intel_crtc_state *crtc_state,
> > > > + struct intel_encoder *encoder) {
> > > > + const struct intel_c10mpllb_state *pll_state = &crtc_state-
> >c10mpllb_state;
> > > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > > + bool lane_reversal = dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
> > > > + u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
> > > > + INTEL_CX0_LANE0;
> > > > + u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
> > > > + INTEL_CX0_LANE1;
> > > > +
> > > > + int i;
> > > > + struct intel_dp *intel_dp;
> > > > + bool use_ssc = false;
> > > > + u8 cmn0 = 0;
> > > > +
> > > > + if (intel_crtc_has_dp_encoder(crtc_state)) {
> > > > + intel_dp = enc_to_intel_dp(encoder);
> > > > + use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> > > > + DP_MAX_DOWNSPREAD_0_5);
> > > > +
> > > > + if (!intel_panel_use_ssc(i915))
> > > > + use_ssc = false;
> > > > +
> > > > + cmn0 = C10_CMN0_DP_VAL;
> > > > + }
> > > > +
> > > > + intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> > > > + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
> > > > + /* Custom width needs to be programmed to 0 for both the phy lanes */
> > > > + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> > > > + PHY_C10_VDR_CUSTOM_WIDTH, 0x3, 0,
> MB_WRITE_COMMITTED);
> > > > + intel_cx0_rmw(i915, encoder->port, follower_lane,
> PHY_C10_VDR_CONTROL(1),
> > > > + C10_VDR_CTRL_MASTER_LANE, C10_VDR_CTRL_UPDATE_CFG,
> > > > + MB_WRITE_COMMITTED);
> > > > +
> > > > + /* Program the pll values only for the master lane */
> > > > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > > > + /* If not using ssc pll[4] through pll[8] must be 0*/
> > > > + intel_cx0_write(i915, encoder->port, master_lane,
> > > > + PHY_C10_VDR_PLL(i),
> > >
> > > This programs the PLL via the INTEL_CX0_LANE1 lane in the
> > > lane_reversal=true case. However, I haven't found any trace of this
> > > being correct in the spec. It just says that PLL must be programmed
> > > via
> > > INTEL_CX0_LANE0 in all the cases, so both for lane_reversal and
> > > !lane_reversal (see Bspec/64539 "Phy Lane and Transmitter Usage"
> > > table/"Lane for message bus PLL programming" column).
> > >
> > > > + (!use_ssc && (i > 3 && i < 9)) ? 0 : pll_state->pll[i],
> > > > + (i % 4) ? MB_WRITE_UNCOMMITTED :
> > > > + MB_WRITE_COMMITTED);
> > > > +
> > > > + intel_cx0_write(i915, encoder->port, master_lane,
> PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
> > > > + intel_cx0_write(i915, encoder->port, master_lane,
> PHY_C10_VDR_TX(0), C10_TX0_VAL, MB_WRITE_COMMITTED);
> > > > + intel_cx0_rmw(i915, encoder->port, master_lane,
> PHY_C10_VDR_CONTROL(1),
> > > > + C10_VDR_CTRL_MSGBUS_ACCESS,
> C10_VDR_CTRL_MASTER_LANE |
> > > > + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> > >
> > > For all the above writes, programming INTEL_CX0_LANE1 looks
> > > incorrect in the lane_reversal=true case, should program INTEL_CX0_LANE0
> instead.
> >
> > So in any case we should program INTEL_CX0_LANE0?
>
> That's what the spec says at least, so I don't see a reason to not follow that.
Let's go with what the spec says.
>
> > [...]
> > > > +
> > > > /*
> > > > * Local integer constant expression version of is_power_of_2().
> > > > */
> > > > @@ -74,6 +102,23 @@
> > > > BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL <<
> > > > __bf_shf(__mask)))) + \
> > > >
> > > > BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val),
> > > > (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
> > > >
> > > > +/**
> > > > + * REG_FIELD_PREP8() - Prepare a u8 bitfield value
> > > > + * @__mask: shifted mask defining the field's length and position
> > > > + * @__val: value to put in the field
> > > > + *
> > > > + * Local copy of FIELD_PREP8() to generate an integer constant
> > > > +expression, force
> > >
> > > The above is FIELD_PREP() only.
> >
> > So use FIELD_PREP() instead of FIELD_PREP8()?
>
> Yes, there is no FIELD_PREP8(), so I assume the reference was about
> FIELD_PREP().
Ok.
>
> --Imre
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 6/7] drm/i915/mtl: Add vswing programming for C10 phys
2023-03-27 12:34 ` [Intel-gfx] [PATCH 6/7] drm/i915/mtl: Add vswing programming for C10 phys Mika Kahola
@ 2023-04-03 11:18 ` Imre Deak
0 siblings, 0 replies; 37+ messages in thread
From: Imre Deak @ 2023-04-03 11:18 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
On Mon, Mar 27, 2023 at 03:34:32PM +0300, Mika Kahola wrote:
> From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>
> C10 phys uses direct mapping internally for voltage and pre-emphasis levels.
> Program the levels directly to the fields in the VDR Registers.
>
> Bspec: 65449
>
> v2: From table "C10: Tx EQ settings for DP 1.4x" it shows level 1
> and preemphasis 1 instead of two times of level 1 preemphasis 0.
> Fix this in the driver code as well.
> v3: VSwing update (Clint)
>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 140 ++++++++++++++++--
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 +
> .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 14 ++
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
> .../drm/i915/display/intel_ddi_buf_trans.c | 31 +++-
> .../drm/i915/display/intel_ddi_buf_trans.h | 6 +
> .../i915/display/intel_display_power_map.c | 1 +
> 7 files changed, 187 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 3aa8031f8373..fb54f56ac5ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -6,11 +6,15 @@
> #include "i915_reg.h"
> #include "intel_cx0_phy.h"
> #include "intel_cx0_phy_regs.h"
> +#include "intel_ddi.h"
> +#include "intel_ddi_buf_trans.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_panel.h"
> +#include "intel_psr.h"
> #include "intel_tc.h"
> +#include "intel_uncore.h"
>
> bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
> {
> @@ -20,6 +24,15 @@ bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
> return false;
> }
>
> +static void
> +assert_dc_off(struct drm_i915_private *i915)
> +{
> + bool enabled;
> +
> + enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF);
> + drm_WARN_ON(&i915->drm, !enabled);
> +}
> +
> static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, int lane)
> {
> enum phy phy = intel_port_to_phy(i915, port);
> @@ -112,6 +125,8 @@ static u8 intel_cx0_read(struct drm_i915_private *i915, enum port port,
> int i, status = 0;
> u32 val;
>
> + assert_dc_off(i915);
> +
This along with intel_cx0_phy_transaction_begin()/end() could be moved
to the patch adding intel_cx0_bus_reset().
> for (i = 0; i < 3; i++) {
> status = __intel_cx0_read(i915, port, lane, addr, &val);
>
> @@ -194,6 +209,8 @@ static void __intel_cx0_write(struct drm_i915_private *i915, enum port port,
> enum phy phy = intel_port_to_phy(i915, port);
> int i, status;
>
> + assert_dc_off(i915);
> +
> for (i = 0; i < 3; i++) {
> status = __intel_cx0_write_once(i915, port, lane, addr, data, committed);
>
> @@ -241,6 +258,89 @@ static void intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> }
> }
>
> +/*
> + * Prepare HW for CX0 phy transactions.
> + *
> + * It is required that PSR and DC5/6 are disabled before any CX0 message
> + * bus transaction is executed.
> + */
> +static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + intel_psr_pause(intel_dp);
> + return intel_display_power_get(i915, POWER_DOMAIN_DC_OFF);
> +}
> +
> +static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + intel_psr_resume(intel_dp);
> + intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, wakeref);
> +}
> +
> +void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> + u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
> + INTEL_CX0_LANE0;
> + u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
> + INTEL_CX0_LANE1;
> + const struct intel_ddi_buf_trans *trans;
> + intel_wakeref_t wakeref;
> + int n_entries, ln;
> +
> + wakeref = intel_cx0_phy_transaction_begin(encoder);
> +
> + trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
> + if (drm_WARN_ON_ONCE(&i915->drm, !trans))
> + return;
> +
> + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> + 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
The spec says to program here the
VDR common offset 12'hC31 for TX termination control
and
VDR common offset 12'hC23 for TX vboost level
see bspec/74103.
> +
> + for (ln = 0; ln < 4; ln++) {
Should program only the lanes up to crtc_state->lane_count.
> + int level = intel_ddi_level(encoder, crtc_state, ln);
> + int lane, tx;
> +
> + lane = ln / 2;
> + tx = ln % 2 + 1;
> +
> + intel_cx0_rmw(i915, encoder->port, lane + 1, PHY_CX0_VDR_OVRD_CONTROL(lane, tx, 0),
Instead of the above magic conversions, would be better to have helpers, stg like:
phy_lane = lane_to_phy_lane(ln);
tx = lane_to_phy_lane_tx(ln);
phy_lane_mask = lane_to_phy_lane_mask(ln);
lane_reversal and the DP-alt mode is not accounted for here, for
instance phy lane#0/tx#1 will be programmed instead of phy lane#1/tx#2.
Either this needs to be fixed or needs a FIXME: comment.
> + C10_PHY_OVRD_LEVEL_MASK,
> + C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),
> + MB_WRITE_COMMITTED);
> + intel_cx0_rmw(i915, encoder->port, lane + 1, PHY_CX0_VDR_OVRD_CONTROL(lane, tx, 1),
> + C10_PHY_OVRD_LEVEL_MASK,
> + C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing),
> + MB_WRITE_COMMITTED);
> + intel_cx0_rmw(i915, encoder->port, lane + 1, PHY_CX0_VDR_OVRD_CONTROL(lane, tx, 2),
> + C10_PHY_OVRD_LEVEL_MASK,
> + C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor),
> + MB_WRITE_COMMITTED);
> + }
> +
> + /* Write Override enables in 0xD71 */
> + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_OVRD,
> + PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
> + PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
> + MB_WRITE_COMMITTED);
Only the used/owned PHY lanes should be programmed.
> + intel_cx0_write(i915, encoder->port, follower_lane, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
> + MB_WRITE_COMMITTED);
> + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_MSGBUS_ACCESS |
> + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
I don't think this should change the MASTER_LANE flag, which only
controls where the PLL parameters are programmed and is already set up
during PLL enabling. Also I don't see a reason to differentiate between
"master" and "follower" PHY lanes here. I think the above two should
simply set the C10_VCR_CTRL_UPDATE_CFG flag in both PHY lanes, using
intel_cx0_rmw().
> +
> + intel_cx0_phy_transaction_end(encoder, wakeref);
> +}
> +
> /*
> * Basic DP link rates with 38.4 MHz reference clock.
> * Note: The tables below are with SSC. In non-ssc
> @@ -1085,9 +1185,12 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> INTEL_CX0_LANE0;
> enum phy phy = intel_port_to_phy(i915, encoder->port);
> + intel_wakeref_t wakeref;
> int i;
> u8 cmn, tx0;
>
> + wakeref = intel_cx0_phy_transaction_begin(encoder);
> +
This should be in the patch adding intel_c10mpllb_readout_hw_state().
> /*
> * According to C10 VDR Register programming Sequence we need
> * to do this to read PHY internal registers from MsgBus.
> @@ -1106,6 +1209,8 @@ void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> cmn != C10_CMN0_HDMI_VAL))
> drm_dbg_kms(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
> tx0, cmn, phy_name(phy));
> +
> + intel_cx0_phy_transaction_end(encoder, wakeref);
> }
>
> static void intel_c10_pll_program(struct drm_i915_private *i915,
> @@ -1243,8 +1348,11 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
>
> if (intel_crtc_has_dp_encoder(crtc_state)) {
> intel_dp = enc_to_intel_dp(encoder);
> - ssc_enabled = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> - DP_MAX_DOWNSPREAD_0_5;
> + ssc_enabled = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> + DP_MAX_DOWNSPREAD_0_5);
> +
> + if (intel_dp_is_edp(intel_dp) && !intel_panel_use_ssc(i915))
> + ssc_enabled = false;
>
> if (!intel_panel_use_ssc(i915))
> ssc_enabled = false;
> @@ -1252,11 +1360,11 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
> val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> }
> +
> intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> - XELPDP_LANE1_PHY_CLOCK_SELECT |
> - XELPDP_FORWARD_CLOCK_UNGATE |
> + XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
Stray w/s change.
> XELPDP_DDI_CLOCK_SELECT_MASK |
> - XELPDP_SSC_ENABLE_PLLB, val);
> + XELPDP_SSC_ENABLE_PLLA | XELPDP_SSC_ENABLE_PLLB, val);
I suppose this change should be in a C20 patchset, as PLLA is not used
in C10 PHYs.
> }
>
> static u32 intel_cx0_get_powerdown_update(u8 lane)
> @@ -1396,9 +1504,12 @@ static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
> bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
> enum port port = encoder->port;
>
> - intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> - C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MSGBUS_ACCESS,
> - MB_WRITE_COMMITTED);
> + intel_cx0_rmw(i915, port, INTEL_CX0_LANE1, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
> + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
> + intel_cx0_rmw(i915, port, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),
> + C10_VDR_CTRL_MSGBUS_ACCESS | C10_VDR_CTRL_UPDATE_CFG,
> + C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
As above, this shouldn't change the MASTER_LANE flag (now it contradicts
the programming during pll enabling and vswing setting for the
lane_reversal=true case). Probably the MSGBUS_ACCESS flag doesn't need
to be cleared either, at least I can't see bspec requiring it. So just set the
C10_VDR_CTRL_UPDATE_CFG flag in the programmed PHY lanes.
>
> l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
> l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
> @@ -1561,9 +1672,14 @@ void intel_cx0pll_enable(struct intel_encoder *encoder,
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum phy phy = intel_port_to_phy(i915, encoder->port);
> + intel_wakeref_t wakeref;
> +
> + wakeref = intel_cx0_phy_transaction_begin(encoder);
Should be in the patch adding intel_cx0pll_enable().
>
> drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> intel_c10pll_enable(encoder, crtc_state);
> +
> + intel_cx0_phy_transaction_end(encoder, wakeref);
> }
>
> static void intel_c10pll_disable(struct intel_encoder *encoder)
> @@ -1608,7 +1724,8 @@ static void intel_c10pll_disable(struct intel_encoder *encoder)
>
> /* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
> intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> - XELPDP_DDI_CLOCK_SELECT_MASK |
> + XELPDP_DDI_CLOCK_SELECT_MASK, 0);
> + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> XELPDP_FORWARD_CLOCK_UNGATE, 0);
This looks like a fix-up, if required should be part of the patch adding
this register programming.
> }
>
> @@ -1616,9 +1733,14 @@ void intel_cx0pll_disable(struct intel_encoder *encoder)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum phy phy = intel_port_to_phy(i915, encoder->port);
> + intel_wakeref_t wakeref;
> +
> + wakeref = intel_cx0_phy_transaction_begin(encoder);
Should be where intel_cx0pll_disable() is added.
>
> drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> intel_c10pll_disable(encoder);
> +
> + intel_cx0_phy_transaction_end(encoder, wakeref);
> }
>
> void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index f8023f240727..952c7deeffaa 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -40,5 +40,7 @@ int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
> void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
> struct intel_crtc_state *new_crtc_state);
> int intel_c10_phy_check_hdmi_link_rate(int clock);
> +void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_CX0_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 91e2f88f43f7..7a578a30ee45 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -154,6 +154,14 @@
> #define CX0_P4PG_STATE_DISABLE 0xC
> #define CX0_P2_STATE_RESET 0x2
>
> +#define PHY_C10_VDR_OVRD 0xD71
> +#define PHY_C10_VDR_OVRD_TX1 REG_BIT8(0)
> +#define PHY_C10_VDR_OVRD_TX2 REG_BIT8(2)
> +#define PHY_C10_VDR_PRE_OVRD_TX1 0xD80
> +#define C10_PHY_OVRD_LEVEL_MASK REG_GENMASK8(5, 0)
> +#define C10_PHY_OVRD_LEVEL(val) REG_FIELD_PREP8(C10_PHY_OVRD_LEVEL_MASK, val)
> +#define PHY_CX0_VDR_OVRD_CONTROL(lane, tx, control) (PHY_C10_VDR_PRE_OVRD_TX1 + ((lane) ^ ((tx) - 1)) * 0x10 + (control))
Flag indentation is missing.
Instead of open-coding there should be defines like
CX0_VDR_CONTROL_TX1 0
CX0_VDR_CONTROL_TX2 1
and use these both in lane_to_phy_lane_tx() and above replacing
((tx) - 1) with ((tx) - CX0_VDR_CONTROL_TX1).
(and in similar places like PHY_CX0_TX_CONTROL()).
> +
> /* PHY_C10_VDR_PLL0 */
> #define PLL_C10_MPLL_SSC_EN REG_BIT8(0)
>
> @@ -161,4 +169,10 @@
> #define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
> #define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
>
> +/* C10 Phy VSWING Masks */
> +#define C10_PHY_VSWING_LEVEL_MASK REG_GENMASK8(2, 0)
> +#define C10_PHY_VSWING_LEVEL(val) REG_FIELD_PREP8(C10_PHY_VSWING_LEVEL_MASK, val)
> +#define C10_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(1, 0)
> +#define C10_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C10_PHY_VSWING_PREEMPH_MASK, val)
The above seem to be unused.
> +
> #endif /* __INTEL_CX0_REG_DEFS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a433dea5b9a3..e8269fcc595e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4493,7 +4493,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> encoder->get_config = hsw_ddi_get_config;
> }
>
> - if (IS_DG2(dev_priv)) {
> + if (DISPLAY_VER(dev_priv) >= 14) {
> + encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
> + } else if (IS_DG2(dev_priv)) {
> encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
> } else if (DISPLAY_VER(dev_priv) >= 12) {
> if (intel_phy_is_combo(dev_priv, phy))
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index 006a2e979000..cd4becbae098 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -1035,6 +1035,25 @@ static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
> .num_entries = ARRAY_SIZE(_dg2_snps_trans_uhbr),
> };
>
> +static const union intel_ddi_buf_trans_entry _mtl_c10_trans_dp14[] = {
> + { .snps = { 26, 0, 0 } }, /* preset 0 */
> + { .snps = { 33, 0, 6 } }, /* preset 1 */
> + { .snps = { 38, 0, 11 } }, /* preset 2 */
> + { .snps = { 43, 0, 19 } }, /* preset 3 */
> + { .snps = { 39, 0, 0 } }, /* preset 4 */
> + { .snps = { 45, 0, 7 } }, /* preset 5 */
> + { .snps = { 46, 0, 13 } }, /* preset 6 */
> + { .snps = { 46, 0, 0 } }, /* preset 7 */
> + { .snps = { 55, 0, 7 } }, /* preset 8 */
> + { .snps = { 62, 0, 0 } }, /* preset 9 */
> +};
> +
> +static const struct intel_ddi_buf_trans mtl_cx0c10_trans = {
> + .entries = _mtl_c10_trans_dp14,
> + .num_entries = ARRAY_SIZE(_mtl_c10_trans_dp14),
> + .hdmi_default_entry = ARRAY_SIZE(_mtl_c10_trans_dp14) - 1,
> +};
> +
> bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
> {
> return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
> @@ -1606,12 +1625,22 @@ dg2_get_snps_buf_trans(struct intel_encoder *encoder,
> return intel_get_buf_trans(&dg2_snps_trans, n_entries);
> }
>
> +static const struct intel_ddi_buf_trans *
> +mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state,
> + int *n_entries)
> +{
> + return intel_get_buf_trans(&mtl_cx0c10_trans, n_entries);
> +}
> +
> void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum phy phy = intel_port_to_phy(i915, encoder->port);
>
> - if (IS_DG2(i915)) {
> + if (DISPLAY_VER(i915) >= 14) {
> + encoder->get_buf_trans = mtl_get_cx0_buf_trans;
> + } else if (IS_DG2(i915)) {
> encoder->get_buf_trans = dg2_get_snps_buf_trans;
> } else if (IS_ALDERLAKE_P(i915)) {
> if (intel_phy_is_combo(i915, phy))
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> index 2133984a572b..e4a857b9829d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> @@ -51,6 +51,11 @@ struct dg2_snps_phy_buf_trans {
> u8 post_cursor;
> };
>
> +struct direct_phy_buf_trans {
> + u8 level;
> + u8 preemph;
> +};
> +
> union intel_ddi_buf_trans_entry {
> struct hsw_ddi_buf_trans hsw;
> struct bxt_ddi_buf_trans bxt;
> @@ -58,6 +63,7 @@ union intel_ddi_buf_trans_entry {
> struct icl_mg_phy_ddi_buf_trans mg;
> struct tgl_dkl_phy_ddi_buf_trans dkl;
> struct dg2_snps_phy_buf_trans snps;
> + struct direct_phy_buf_trans direct;
> };
>
> struct intel_ddi_buf_trans {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 6645eb1911d8..5ec2b9a109ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1427,6 +1427,7 @@ I915_DECL_PW_DOMAINS(xelpdp_pwdoms_dc_off,
> XELPDP_PW_2_POWER_DOMAINS,
> POWER_DOMAIN_AUDIO_MMIO,
> POWER_DOMAIN_MODESET,
> + POWER_DOMAIN_DC_OFF,
It's added to the domain list below.
> POWER_DOMAIN_AUX_A,
> POWER_DOMAIN_AUX_B,
> POWER_DOMAIN_DC_OFF,
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-03-29 15:40 ` Imre Deak
2023-03-29 15:59 ` Imre Deak
@ 2023-04-04 10:43 ` Kahola, Mika
2023-04-04 11:47 ` Imre Deak
1 sibling, 1 reply; 37+ messages in thread
From: Kahola, Mika @ 2023-04-04 10:43 UTC (permalink / raw)
To: Deak, Imre; +Cc: intel-gfx
> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Wednesday, March 29, 2023 6:41 PM
> To: Kahola, Mika <mika.kahola@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> <radhakrishna.sripada@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Sousa, Gustavo <gustavo.sousa@intel.com>
> Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> and pll programming
>
> On Mon, Mar 27, 2023 at 03:34:30PM +0300, Mika Kahola wrote:
> > From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> >
> > XELPDP has C10 and C20 phys from Synopsys to drive displays. Each phy
> > has a dedicated PIPE 5.2 Message bus for configuration. This message
> > bus is used to configure the phy internal registers.
> >
> > XELPDP has C10 phys to drive output to the EDP and the native output
> > from the display engine. Add structures, programming hardware state
> > readout logic. Port clock calculations are similar to DG2. Use the DG2
> > formulae to calculate the port clock but use the relevant pll signals.
> > Note: PHY lane 0 is always used for PLL programming.
> >
> > Add sequences for C10 phy enable/disable phy lane reset,
> > powerdown change sequence and phy lane programming.
> >
> > Bspec: 64539, 64568, 64599, 65100, 65101, 65450, 65451, 67610, 67636
> >
> > v2: Squash patches related to C10 phy message bus and pll
> > programming support (Jani)
> > Move register definitions to a new file i.e. intel_cx0_reg_defs.h (Jani)
> > Move macro definitions (Jani)
> > DP rates as separate patch (Jani)
> > Spin out xelpdp register definitions into a separate file (Jani)
> > Replace macro to select registers based on phy lane with
> > function calls (Jani)
> > Fix styling issues (Jani)
> > Call XELPDP_PORT_P2M_MSGBUS_STATUS() with port instead of phy (Lucas)
> > v3: Move clear request flag into try-loop
> > v4: On PHY idle change drm_err_once() as drm_dbg_kms() (Jani)
> > use __intel_de_wait_for_register() instead of __intel_wait_for_register
> > and uncomment intel_uncore.h (Jani)
> > Add DP-alt support for PHY lane programming (Khaled)
> >
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Cc: Uma Shankar <uma.shankar@intel.com>
> > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> > drivers/gpu/drm/i915/Makefile | 1 +
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 1120 +++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 43 +
> > .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 32 +-
> > drivers/gpu/drm/i915/display/intel_ddi.c | 22 +-
> > .../drm/i915/display/intel_display_power.c | 3 +-
> > .../i915/display/intel_display_power_well.c | 2 +-
> > .../drm/i915/display/intel_display_types.h | 6 +
> > drivers/gpu/drm/i915/display/intel_dpll.c | 20 +-
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
> > .../drm/i915/display/intel_modeset_verify.c | 2 +
> > drivers/gpu/drm/i915/i915_reg.h | 5 +
> > drivers/gpu/drm/i915/i915_reg_defs.h | 57 +
> > 13 files changed, 1309 insertions(+), 6 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_phy.h
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> > index 057ef22fa9c6..57b1417792b4 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -298,6 +298,7 @@ i915-y += \
> > display/icl_dsi.o \
> > display/intel_backlight.o \
> > display/intel_crt.o \
> > + display/intel_cx0_phy.o \
> > display/intel_ddi.o \
> > display/intel_ddi_buf_trans.o \
> > display/intel_display_trace.o \
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > new file mode 100644
> > index 000000000000..ced8c8aa6c82
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -0,0 +1,1120 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2021 Intel Corporation
> > + */
> > +
> > +#include "i915_reg.h"
> > +#include "intel_cx0_phy.h"
> > +#include "intel_cx0_phy_regs.h"
> > +#include "intel_de.h"
> > +#include "intel_display_types.h"
> > +#include "intel_dp.h"
> > +#include "intel_panel.h"
> > +#include "intel_tc.h"
> > +
> > +bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy)
> > +{
> > + if (IS_METEORLAKE(dev_priv) && (phy < PHY_C))
> > + return true;
> > +
> > + return false;
> > +}
> > +
> > +static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port
> port, int lane)
> > +{
> > + enum phy phy = intel_port_to_phy(i915, port);
> > +
> > + /* Bring the phy to idle. */
> > + intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
>
> For the above and every other place taking a lane mask parameter or
> converting the lane mask to a lane:
>
> I think the function parameter should be an 'u8 lane_mask' for clarity
> and instead of open-coding the conversion should be done by a
> lane_mask_to_lane() helper which also sanity checks lane_mask (that it's
> either INTEL_CX0_LANE0 or INTEL_CX0_LANE1, but not both).
I will add this type of helper function for sanity check.
>
>
> > + XELPDP_PORT_M2P_TRANSACTION_RESET);
> > +
> > + /* Wait for Idle Clear. */
> > + if (intel_de_wait_for_clear(i915,
> XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> > + XELPDP_PORT_M2P_TRANSACTION_RESET,
> > + XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> > + drm_dbg_kms(&i915->drm, "Failed to bring PHY %c to idle.\n",
> phy_name(phy));
> > + return;
> > + }
> > +
> > + intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane -
> 1), ~0);
>
> The above should write only the XELPDP_PORT_P2M_RESPONSE_READY and
> XELPDP_PORT_P2M_ERROR_SET flags to get those cleared.
>
> Could factor out a function for it since the same is also used later.
Ok. There are couple of occasions where this is used.
>
> > +}
> > +
> > +static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port
> port, int lane, u32 *val)
> > +{
> > + enum phy phy = intel_port_to_phy(i915, port);
> > +
> > + if (__intel_de_wait_for_register(i915,
> > +
> XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1),
>
> As above this function should take the 0-based lane value.
Sure.
>
> > +
> XELPDP_PORT_P2M_RESPONSE_READY,
> > +
> XELPDP_PORT_P2M_RESPONSE_READY,
> > +
> XELPDP_MSGBUS_TIMEOUT_FAST_US,
> > + XELPDP_MSGBUS_TIMEOUT_SLOW,
> val)) {
> > + drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for
> message ACK. Status: 0x%x\n", phy_name(phy), *val);
> > + return -ETIMEDOUT;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int __intel_cx0_read(struct drm_i915_private *i915, enum port port,
> > + int lane, u16 addr, u32 *val)
> > +{
> > + enum phy phy = intel_port_to_phy(i915, port);
> > + int ack;
> > +
> > + /* Wait for pending transactions.*/
> > + if (intel_de_wait_for_clear(i915,
> XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> > +
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> > + XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> > + drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for
> previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
> > + intel_cx0_bus_reset(i915, port, lane);
>
> Does bspec describe somewhere that this reset is needed?
I think this plays on the safe side. If transaction is not completed withing reasonable time, we set the bus in known state. What would be the alternative? Just leave the bus state as is?
>
> > + return -ETIMEDOUT;
> > + }
> > +
> > + /* Issue the read command. */
> > + intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> > + XELPDP_PORT_M2P_TRANSACTION_PENDING |
> > + XELPDP_PORT_M2P_COMMAND_READ |
> > + XELPDP_PORT_M2P_ADDRESS(addr));
> > +
> > + /* Wait for response ready. And read response.*/
> > + ack = intel_cx0_wait_for_ack(i915, port, lane, val);
> > + if (ack < 0) {
> > + intel_cx0_bus_reset(i915, port, lane);
> > + return ack;
> > + }
> > +
> > + /* Check for error. */
> > + if (*val & XELPDP_PORT_P2M_ERROR_SET) {
> > + drm_dbg_kms(&i915->drm, "PHY %c Error occurred during read
> command. Status: 0x%x\n", phy_name(phy), *val);
> > + intel_cx0_bus_reset(i915, port, lane);
> > + return -EINVAL;
> > + }
> > +
> > + /* Check for Read Ack. */
> > + if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val)
> !=
> > + XELPDP_PORT_P2M_COMMAND_READ_ACK) {
> > + drm_dbg_kms(&i915->drm, "PHY %c Not a Read response.
> MSGBUS Status: 0x%x.\n", phy_name(phy), *val);
> > + intel_cx0_bus_reset(i915, port, lane);
> > + return -EINVAL;
> > + }
> > +
> > + /* Clear Response Ready flag.*/
> > + intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane -
> 1), ~0);
>
> Could use a helper for the above.
Yes.
>
> > +
> > + return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, *val);
> > +}
> > +
> > +static u8 intel_cx0_read(struct drm_i915_private *i915, enum port port,
> > + int lane, u16 addr)
> > +{
> > + enum phy phy = intel_port_to_phy(i915, port);
> > + int i, status = 0;
> > + u32 val;
> > +
> > + for (i = 0; i < 3; i++) {
>
> Please add a comment why this retries 3 times, doesn't seem to be
> described by the spec.
Ok, I'll add a comment for read/write tries. This hasn't been specified in spec so the number of retries could be anything.
>
> > + status = __intel_cx0_read(i915, port, lane, addr, &val);
>
> val could be removed as it's not used, and remove the last param from
> __intel_cx0_read() accordingly.
>
> > +
> > + if (status >= 0)
> > + break;
>
> Returning status here would simplify the code below.
Yes. Let's just return here.
>
> > + }
> > +
> > + if (i == 3) {
> > + drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d
> retries.\n", phy_name(phy), addr, i);
> > + return 0;
> > + }
> > +
> > + return status;
> > +}
> > +
> > +static int intel_cx0_wait_cwrite_ack(struct drm_i915_private *i915,
> > + enum port port, int lane)
> > +{
> > + enum phy phy = intel_port_to_phy(i915, port);
> > + int ack;
> > + u32 val = 0;
> > +
> > + /* Check for write ack. */
> > + ack = intel_cx0_wait_for_ack(i915, port, lane, &val);
> > + if (ack < 0)
> > + return ack;
> > +
> > + if ((REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, val)
> !=
> > + XELPDP_PORT_P2M_COMMAND_WRITE_ACK) || val &
> XELPDP_PORT_P2M_ERROR_SET) {
> > + drm_dbg_kms(&i915->drm, "PHY %c Unexpected ACK received.
> MSGBUS STATUS: 0x%x.\n", phy_name(phy), val);
> > + return -EINVAL;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port
> port,
> > + int lane, u16 addr, u8 data, bool committed)
> > +{
> > + enum phy phy = intel_port_to_phy(i915, port);
> > +
> > + /* Wait for pending transactions.*/
> > + if (intel_de_wait_for_clear(i915,
> XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> > +
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> > + XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> > + drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for
> previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
> > + intel_cx0_bus_reset(i915, port, lane);
> > + return -ETIMEDOUT;
> > + }
> > +
> > + /* Issue the write command. */
> > + intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> > + XELPDP_PORT_M2P_TRANSACTION_PENDING |
> > + (committed ?
> XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
> > + XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED)
> |
>
> Could better indent the above line for clarity.
Ah, ok.
>
> > + XELPDP_PORT_M2P_DATA(data) |
> > + XELPDP_PORT_M2P_ADDRESS(addr));
> > +
>
> The spec requires to wait here MSGBUS_CTL /
> XELPDP_PORT_M2P_TRANSACTION_PENDING
> to clear (for both commited/uncommited writes).
>
> > + /* Check for error. */
> > + if (committed) {
> > + if (intel_cx0_wait_cwrite_ack(i915, port, lane) < 0) {
> > + intel_cx0_bus_reset(i915, port, lane);
> > + return -EINVAL;
> > + }
> > + } else if ((intel_de_read(i915,
> XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane - 1)) &
> > + XELPDP_PORT_P2M_ERROR_SET)) {
> > + drm_dbg_kms(&i915->drm, "PHY %c Error occurred during write
> command.\n", phy_name(phy));
> > + intel_cx0_bus_reset(i915, port, lane);
> > + return -EINVAL;
> > + }
> > +
> > + intel_de_write(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane -
> 1), ~0);
>
> Could use a helper for the above.
Yes.
>
> > +
> > + return 0;
> > +}
> > +
> > +static void __intel_cx0_write(struct drm_i915_private *i915, enum port port,
> > + int lane, u16 addr, u8 data, bool committed)
> > +{
> > + enum phy phy = intel_port_to_phy(i915, port);
> > + int i, status;
> > +
> > + for (i = 0; i < 3; i++) {
> > + status = __intel_cx0_write_once(i915, port, lane, addr, data,
> committed);
> > +
> > + if (status == 0)
> > + break;
>
> Could simplify by the code below by returning here.
I will return here as well.
>
> > + }
> > +
> > + if (i == 3) {
> > + drm_err_once(&i915->drm, "PHY %c Write %04x failed after %d
> retries.\n", phy_name(phy), addr, i);
> > + return;
> > + }
> > +}
> > +
> > +static void intel_cx0_write(struct drm_i915_private *i915, enum port port,
> > + int lane, u16 addr, u8 data, bool committed)
> > +{
> > + if (lane == INTEL_CX0_BOTH_LANES) {
> > + __intel_cx0_write(i915, port, INTEL_CX0_LANE0, addr, data,
> committed);
> > + __intel_cx0_write(i915, port, INTEL_CX0_LANE1, addr, data,
> committed);
> > + } else {
> > + __intel_cx0_write(i915, port, lane, addr, data, committed);
>
> Could add a helper and simplify the above by
>
> for_each_cx0_lane_in_mask(lane, lane_mask)
> __intel_cx0_write(i915, port, lane, addr, data, committed);
>
Yes, let's add this kind of helper. It will help with rmw case as well.
> > + }
> > +}
> > +
> > +static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> > + int lane, u16 addr, u8 clear, u8 set, bool committed)
> > +{
> > + u8 old, val;
> > +
> > + old = intel_cx0_read(i915, port, lane, addr);
> > + val = (old & ~clear) | set;
> > +
> > + if (val != old)
> > + intel_cx0_write(i915, port, lane, addr, val, committed);
> > +}
> > +
> > +static void intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
> > + int lane, u16 addr, u8 clear, u8 set, bool committed)
> > +{
> > + if (lane == INTEL_CX0_BOTH_LANES) {
> > + __intel_cx0_rmw(i915, port, INTEL_CX0_LANE0, addr, clear,
> set, committed);
> > + __intel_cx0_rmw(i915, port, INTEL_CX0_LANE1, addr, clear,
> set, committed);
> > + } else {
> > + __intel_cx0_rmw(i915, port, lane, addr, clear, set, committed);
> > + }
>
> Could use a for_each_cx0_lane_in_mask() helper here too.
Sure.
>
> > +}
> > +
> > +/*
> > + * Basic DP link rates with 38.4 MHz reference clock.
> > + * Note: The tables below are with SSC. In non-ssc
> > + * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
> > + * programmed 0.
> > + */
> > +
> > +static const struct intel_c10mpllb_state mtl_c10_dp_rbr = {
> > + .clock = 162000,
> > + .pll[0] = 0xB4,
> > + .pll[1] = 0,
> > + .pll[2] = 0x30,
> > + .pll[3] = 0x1,
> > + .pll[4] = 0x26,
> > + .pll[5] = 0x0C,
> > + .pll[6] = 0x98,
> > + .pll[7] = 0x46,
> > + .pll[8] = 0x1,
> > + .pll[9] = 0x1,
> > + .pll[10] = 0,
> > + .pll[11] = 0,
> > + .pll[12] = 0xC0,
> > + .pll[13] = 0,
> > + .pll[14] = 0,
> > + .pll[15] = 0x2,
> > + .pll[16] = 0x84,
> > + .pll[17] = 0x4F,
> > + .pll[18] = 0xE5,
> > + .pll[19] = 0x23,
> > +};
> > +
> > +static const struct intel_c10mpllb_state mtl_c10_edp_r216 = {
> > + .clock = 216000,
> > + .pll[0] = 0x4,
> > + .pll[1] = 0,
> > + .pll[2] = 0xA2,
> > + .pll[3] = 0x1,
> > + .pll[4] = 0x33,
> > + .pll[5] = 0x10,
> > + .pll[6] = 0x75,
> > + .pll[7] = 0xB3,
> > + .pll[8] = 0x1,
> > + .pll[9] = 0x1,
> > + .pll[10] = 0,
> > + .pll[11] = 0,
> > + .pll[12] = 0,
> > + .pll[13] = 0,
> > + .pll[14] = 0,
> > + .pll[15] = 0x2,
> > + .pll[16] = 0x85,
> > + .pll[17] = 0x0F,
> > + .pll[18] = 0xE6,
> > + .pll[19] = 0x23,
> > +};
> > +
> > +static const struct intel_c10mpllb_state mtl_c10_edp_r243 = {
> > + .clock = 243000,
> > + .pll[0] = 0x34,
> > + .pll[1] = 0,
> > + .pll[2] = 0xDA,
> > + .pll[3] = 0x1,
> > + .pll[4] = 0x39,
> > + .pll[5] = 0x12,
> > + .pll[6] = 0xE3,
> > + .pll[7] = 0xE9,
> > + .pll[8] = 0x1,
> > + .pll[9] = 0x1,
> > + .pll[10] = 0,
> > + .pll[11] = 0,
> > + .pll[12] = 0x20,
> > + .pll[13] = 0,
> > + .pll[14] = 0,
> > + .pll[15] = 0x2,
> > + .pll[16] = 0x85,
> > + .pll[17] = 0x8F,
> > + .pll[18] = 0xE6,
> > + .pll[19] = 0x23,
> > +};
> > +
> > +static const struct intel_c10mpllb_state mtl_c10_dp_hbr1 = {
> > + .clock = 270000,
> > + .pll[0] = 0xF4,
> > + .pll[1] = 0,
> > + .pll[2] = 0xF8,
> > + .pll[3] = 0x0,
> > + .pll[4] = 0x20,
> > + .pll[5] = 0x0A,
> > + .pll[6] = 0x29,
> > + .pll[7] = 0x10,
> > + .pll[8] = 0x1, /* Verify */
> > + .pll[9] = 0x1,
> > + .pll[10] = 0,
> > + .pll[11] = 0,
> > + .pll[12] = 0xA0,
> > + .pll[13] = 0,
> > + .pll[14] = 0,
> > + .pll[15] = 0x1,
> > + .pll[16] = 0x84,
> > + .pll[17] = 0x4F,
> > + .pll[18] = 0xE5,
> > + .pll[19] = 0x23,
> > +};
> > +
> > +static const struct intel_c10mpllb_state mtl_c10_edp_r324 = {
> > + .clock = 324000,
> > + .pll[0] = 0xB4,
> > + .pll[1] = 0,
> > + .pll[2] = 0x30,
> > + .pll[3] = 0x1,
> > + .pll[4] = 0x26,
> > + .pll[5] = 0x0C,
> > + .pll[6] = 0x98,
> > + .pll[7] = 0x46,
> > + .pll[8] = 0x1,
> > + .pll[9] = 0x1,
> > + .pll[10] = 0,
> > + .pll[11] = 0,
> > + .pll[12] = 0xC0,
> > + .pll[13] = 0,
> > + .pll[14] = 0,
> > + .pll[15] = 0x1,
> > + .pll[16] = 0x85,
> > + .pll[17] = 0x4F,
> > + .pll[18] = 0xE6,
> > + .pll[19] = 0x23,
> > +};
> > +
> > +static const struct intel_c10mpllb_state mtl_c10_edp_r432 = {
> > + .clock = 432000,
> > + .pll[0] = 0x4,
> > + .pll[1] = 0,
> > + .pll[2] = 0xA2,
> > + .pll[3] = 0x1,
> > + .pll[4] = 0x33,
> > + .pll[5] = 0x10,
> > + .pll[6] = 0x75,
> > + .pll[7] = 0xB3,
> > + .pll[8] = 0x1,
> > + .pll[9] = 0x1,
> > + .pll[10] = 0,
> > + .pll[11] = 0,
> > + .pll[12] = 0,
> > + .pll[13] = 0,
> > + .pll[14] = 0,
> > + .pll[15] = 0x1,
> > + .pll[16] = 0x85,
> > + .pll[17] = 0x0F,
> > + .pll[18] = 0xE6,
> > + .pll[19] = 0x23,
> > +};
> > +
> > +static const struct intel_c10mpllb_state mtl_c10_dp_hbr2 = {
> > + .clock = 540000,
> > + .pll[0] = 0xF4,
> > + .pll[1] = 0,
> > + .pll[2] = 0xF8,
> > + .pll[3] = 0,
> > + .pll[4] = 0x20,
> > + .pll[5] = 0x0A,
> > + .pll[6] = 0x29,
> > + .pll[7] = 0x10,
> > + .pll[8] = 0x1,
> > + .pll[9] = 0x1,
> > + .pll[10] = 0,
> > + .pll[11] = 0,
> > + .pll[12] = 0xA0,
> > + .pll[13] = 0,
> > + .pll[14] = 0,
> > + .pll[15] = 0,
> > + .pll[16] = 0x84,
> > + .pll[17] = 0x4F,
> > + .pll[18] = 0xE5,
> > + .pll[19] = 0x23,
> > +};
> > +
> > +static const struct intel_c10mpllb_state mtl_c10_edp_r675 = {
> > + .clock = 675000,
> > + .pll[0] = 0xB4,
> > + .pll[1] = 0,
> > + .pll[2] = 0x3E,
> > + .pll[3] = 0x1,
> > + .pll[4] = 0xA8,
> > + .pll[5] = 0x0C,
> > + .pll[6] = 0x33,
> > + .pll[7] = 0x54,
> > + .pll[8] = 0x1,
> > + .pll[9] = 0x1,
> > + .pll[10] = 0,
> > + .pll[11] = 0,
> > + .pll[12] = 0xC8,
> > + .pll[13] = 0,
> > + .pll[14] = 0,
> > + .pll[15] = 0,
> > + .pll[16] = 0x85,
> > + .pll[17] = 0x8F,
> > + .pll[18] = 0xE6,
> > + .pll[19] = 0x23,
> > +};
> > +
> > +static const struct intel_c10mpllb_state mtl_c10_dp_hbr3 = {
> > + .clock = 810000,
> > + .pll[0] = 0x34,
> > + .pll[1] = 0,
> > + .pll[2] = 0x84,
> > + .pll[3] = 0x1,
> > + .pll[4] = 0x30,
> > + .pll[5] = 0x0F,
> > + .pll[6] = 0x3D,
> > + .pll[7] = 0x98,
> > + .pll[8] = 0x1,
> > + .pll[9] = 0x1,
> > + .pll[10] = 0,
> > + .pll[11] = 0,
> > + .pll[12] = 0xF0,
> > + .pll[13] = 0,
> > + .pll[14] = 0,
> > + .pll[15] = 0,
> > + .pll[16] = 0x84,
> > + .pll[17] = 0x0F,
> > + .pll[18] = 0xE5,
> > + .pll[19] = 0x23,
> > +};
> > +
> > +static const struct intel_c10mpllb_state * const mtl_c10_dp_tables[] = {
> > + &mtl_c10_dp_rbr,
> > + &mtl_c10_dp_hbr1,
> > + &mtl_c10_dp_hbr2,
> > + &mtl_c10_dp_hbr3,
> > + NULL,
> > +};
> > +
> > +static const struct intel_c10mpllb_state * const mtl_c10_edp_tables[] = {
> > + &mtl_c10_dp_rbr,
> > + &mtl_c10_edp_r216,
> > + &mtl_c10_edp_r243,
> > + &mtl_c10_dp_hbr1,
> > + &mtl_c10_edp_r324,
> > + &mtl_c10_edp_r432,
> > + &mtl_c10_dp_hbr2,
> > + &mtl_c10_edp_r675,
> > + &mtl_c10_dp_hbr3,
> > + NULL,
> > +};
> > +
> > +static const struct intel_c10mpllb_state * const *
> > +intel_c10_mpllb_tables_get(struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder)
> > +{
> > + if (intel_crtc_has_dp_encoder(crtc_state)) {
> > + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> > + return mtl_c10_edp_tables;
> > + else
> > + return mtl_c10_dp_tables;
> > + }
> > +
> > + /* TODO: Add HDMI Support */
> > + MISSING_CASE(encoder->type);
> > + return NULL;
> > +}
> > +
> > +static int intel_c10mpllb_calc_state(struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder)
> > +{
> > + const struct intel_c10mpllb_state * const *tables;
> > + int i;
> > +
> > + tables = intel_c10_mpllb_tables_get(crtc_state, encoder);
> > + if (!tables)
> > + return -EINVAL;
> > +
> > + for (i = 0; tables[i]; i++) {
> > + if (crtc_state->port_clock <= tables[i]->clock) {
>
> Not sure how an inaccurate PLL clock would work, shouldn't the above
> accept only a matching clock?
Matching clock is sufficient. It will be helpful in later cases.
>
> > + crtc_state->c10mpllb_state = *tables[i];
> > + return 0;
> > + }
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
> > +int intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > +
> > + drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> > +
> > + return intel_c10mpllb_calc_state(crtc_state, encoder);
> > +}
> > +
> > +void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> > + struct intel_c10mpllb_state *pll_state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > + bool lane_reversal = dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
> > + u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> > + INTEL_CX0_LANE0;
> > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > + int i;
> > + u8 cmn, tx0;
> > +
> > + /*
> > + * According to C10 VDR Register programming Sequence we need
> > + * to do this to read PHY internal registers from MsgBus.
> > + */
> > + intel_cx0_rmw(i915, encoder->port, lane, PHY_C10_VDR_CONTROL(1),
> 0,
> > + C10_VDR_CTRL_MSGBUS_ACCESS,
> MB_WRITE_COMMITTED);
> > +
> > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > + pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane,
> > + PHY_C10_VDR_PLL(i));
> > +
> > + cmn = intel_cx0_read(i915, encoder->port, lane,
> PHY_C10_VDR_CMN(0));
> > + tx0 = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0));
>
> The driver programs these registers, so why aren't they also stored in
> the intell_c20pll_state struct?
Maybe I'm not really following here but intel_c20pll_state has its own tx, cmn and mplla/mpllb stored.
>
> > +
> > + if (tx0 != C10_TX0_VAL || cmn != C10_CMN0_DP_VAL)
> > + drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy:
> %c.\n",
> > + tx0, cmn, phy_name(phy));
>
> Shouldn't PHY_C10_VDR_CONTROL(1)/C10_VDR_CTRL_MSGBUS_ACCESS be
> cleared
> here?
Usually this means that we are not accessing these values from the register. Was this in the spec that we would need to clear it?
>
> > +}
> > +
> > +static void intel_c10_pll_program(struct drm_i915_private *i915,
> > + const struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder)
> > +{
> > + const struct intel_c10mpllb_state *pll_state = &crtc_state-
> >c10mpllb_state;
> > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > + bool lane_reversal = dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
> > + u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
> > + INTEL_CX0_LANE0;
> > + u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
> > + INTEL_CX0_LANE1;
> > +
> > + int i;
> > + struct intel_dp *intel_dp;
> > + bool use_ssc = false;
> > + u8 cmn0 = 0;
> > +
> > + if (intel_crtc_has_dp_encoder(crtc_state)) {
> > + intel_dp = enc_to_intel_dp(encoder);
> > + use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> > + DP_MAX_DOWNSPREAD_0_5);
> > +
> > + if (!intel_panel_use_ssc(i915))
> > + use_ssc = false;
> > +
> > + cmn0 = C10_CMN0_DP_VAL;
>
> Would be clearer by stg like:
> /* Using x MHz reference */
> cmn0 = C10_CMN0_REF_RANGE(1) |
> C10_CMN0_REF_CLK_MPLLB_DIV(2);
Ok. I will do the change.
>
> > + }
> > +
> > + intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> > + C10_VDR_CTRL_MSGBUS_ACCESS,
> MB_WRITE_COMMITTED);
>
> For DP-alt MFD the PHY lane not owned by display shouldn't be
> programmed, no?
The spec says that with pin assignment D the lane 0 is owned by display. Lane 1 is owned by USB and shouldn't be programmed as the PHY will not respond.
>
> > + /* Custom width needs to be programmed to 0 for both the phy lanes */
> > + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> > + PHY_C10_VDR_CUSTOM_WIDTH, 0x3, 0,
> MB_WRITE_COMMITTED);
>
> The above hard-coded values should have a macro definiton.
Ok. I add these values as definitions
>
> > + intel_cx0_rmw(i915, encoder->port, follower_lane,
> PHY_C10_VDR_CONTROL(1),
> > + C10_VDR_CTRL_MASTER_LANE,
> C10_VDR_CTRL_UPDATE_CFG,
> > + MB_WRITE_COMMITTED);
> > +
> > + /* Program the pll values only for the master lane */
> > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > + /* If not using ssc pll[4] through pll[8] must be 0*/
> > + intel_cx0_write(i915, encoder->port, master_lane,
> PHY_C10_VDR_PLL(i),
> > + (!use_ssc && (i > 3 && i < 9)) ? 0 : pll_state-
> >pll[i],
>
> pll_state->pll should be setup already intel_c10mpllb_calc_state()
> taking into account SSC as well.
Yes, I will need this state calculation fixed.
>
> > + (i % 4) ? MB_WRITE_UNCOMMITTED :
> MB_WRITE_COMMITTED);
> > +
> > + intel_cx0_write(i915, encoder->port, master_lane,
> PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
> > + intel_cx0_write(i915, encoder->port, master_lane,
> PHY_C10_VDR_TX(0), C10_TX0_VAL, MB_WRITE_COMMITTED);
>
> Instead of C10_TX0_VAL the flags programmed should be better described
> here as cmn0 above.
Ok. I'll try to fix this.
>
> > + intel_cx0_rmw(i915, encoder->port, master_lane,
> PHY_C10_VDR_CONTROL(1),
> > + C10_VDR_CTRL_MSGBUS_ACCESS,
> C10_VDR_CTRL_MASTER_LANE |
> > + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> > +}
> > +
> > +void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv,
> > + const struct intel_c10mpllb_state *hw_state)
> > +{
> > + bool fracen;
> > + int i;
> > + unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> > + unsigned int multiplier, tx_clk_div;
> > +
> > + fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
> > + drm_dbg_kms(&dev_priv->drm, "c10pll_hw_state: fracen: %s, ",
> > + str_yes_no(fracen));
> > +
> > + if (fracen) {
> > + frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
> > + frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13];
> > + frac_den = hw_state->pll[10] << 8 | hw_state->pll[9];
> > + drm_dbg_kms(&dev_priv->drm, "quot: %u, rem: %u, den:
> %u,\n",
> > + frac_quot, frac_rem, frac_den);
> > + }
> > +
> > + multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK,
> hw_state->pll[3]) << 8 |
> > + hw_state->pll[2]) / 2 + 16;
> > + tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state-
> >pll[15]);
> > + drm_dbg_kms(&dev_priv->drm,
> > + "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
> > +
> > + drm_dbg_kms(&dev_priv->drm, "c10pll_rawhw_state:");
> > +
> > + for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
> > + drm_dbg_kms(&dev_priv->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x,
> pll[%d] = 0x%x, pll[%d] = 0x%x\n",
> > + i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
> > + i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
> > +}
> > +
> > +int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
> > + const struct intel_c10mpllb_state *pll_state)
> > +{
> > + unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> > + unsigned int multiplier, tx_clk_div, refclk = 38400;
> > +
> > + if (pll_state->pll[0] & C10_PLL0_FRACEN) {
> > + frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
> > + frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13];
> > + frac_den = pll_state->pll[10] << 8 | pll_state->pll[9];
> > + }
> > +
> > + multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK,
> pll_state->pll[3]) << 8 |
> > + pll_state->pll[2]) / 2 + 16;
> > +
> > + tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state-
> >pll[15]);
> > +
> > + return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier <<
> 16) + frac_quot) +
> > + DIV_ROUND_CLOSEST(refclk * frac_rem,
> frac_den),
> > + 10 << (tx_clk_div + 16));
> > +}
> > +
> > +static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> > + const struct intel_crtc_state
> *crtc_state,
> > + bool lane_reversal)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + struct intel_dp *intel_dp;
> > + bool ssc_enabled;
> > + u32 val = 0;
> > +
> > + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
> XELPDP_PORT_REVERSAL,
> > + lane_reversal ? XELPDP_PORT_REVERSAL : 0);
> > +
> > + if (lane_reversal)
> > + val |= XELPDP_LANE1_PHY_CLOCK_SELECT;
> > +
> > + val |= XELPDP_FORWARD_CLOCK_UNGATE;
> > + val |=
> XELPDP_DDI_CLOCK_SELECT(XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
>
> TODO: HDMI FRL?
At this point this TODO can be added.
>
> > +
> > + if (intel_crtc_has_dp_encoder(crtc_state)) {
> > + intel_dp = enc_to_intel_dp(encoder);
> > + ssc_enabled = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> > + DP_MAX_DOWNSPREAD_0_5;
> > +
> > + if (!intel_panel_use_ssc(i915))
> > + ssc_enabled = false;
> > +
> > + /* TODO: DP2.0 10G and 20G rates enable MPLLA*/
> > + val |= ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
> > + }
> > + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> > + XELPDP_LANE1_PHY_CLOCK_SELECT |
> > + XELPDP_FORWARD_CLOCK_UNGATE |
> > + XELPDP_DDI_CLOCK_SELECT_MASK |
> > + XELPDP_SSC_ENABLE_PLLB, val);
> > +}
> > +
> > +static u32 intel_cx0_get_powerdown_update(u8 lane)
> > +{
> > + if (lane == INTEL_CX0_LANE0)
> > + return XELPDP_LANE0_POWERDOWN_UPDATE;
> > + else if (lane == INTEL_CX0_LANE1)
> > + return XELPDP_LANE1_POWERDOWN_UPDATE;
> > + else
> > + return XELPDP_LANE0_POWERDOWN_UPDATE |
> > + XELPDP_LANE1_POWERDOWN_UPDATE;
>
> Could simplify by
> val = 0;
> for_each_cx0_lane_in_mask(lane, lane_mask)
> val |= XELPDP_LANE_POWERDOWN_UPDATE(lane);
Yes, now that we have this macro defined.
>
> > +}
> > +
> > +static u32 intel_cx0_get_powerdown_state(u8 lane, u8 state)
> > +{
> > + if (lane == INTEL_CX0_LANE0)
> > + return XELPDP_LANE0_POWERDOWN_NEW_STATE(state);
> > + else if (lane == INTEL_CX0_LANE1)
> > + return XELPDP_LANE1_POWERDOWN_NEW_STATE(state);
> > + else
> > + return XELPDP_LANE0_POWERDOWN_NEW_STATE(state) |
> > + XELPDP_LANE1_POWERDOWN_NEW_STATE(state);
>
> Could simplify similarly to the above.
Yes.
>
> > +}
> > +
> > +static void intel_cx0_powerdown_change_sequence(struct drm_i915_private
> *i915,
> > + enum port port,
> > + u8 lane, u8 state)
> > +{
> > + enum phy phy = intel_port_to_phy(i915, port);
> > +
> > + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> > + XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK |
> XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK,
> > + intel_cx0_get_powerdown_state(lane, state));
> > + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> > + XELPDP_LANE0_POWERDOWN_UPDATE |
> XELPDP_LANE1_POWERDOWN_UPDATE,
> > + intel_cx0_get_powerdown_update(lane));
>
> The spec says (65451):
> "Only update powerdown for one port at a time. Wait for powerdown
> update to finish for one port before initiating update on another port."
>
> both could be updated at the same time if a non-zero stagger delay was
> programmed, but for C10/C20 it must be programmed as 0.
So this needs to be updated so that we update one port and wait for transaction to complete before updating the second port.
>
> > +
> > + /* Update Timeout Value */
> > + if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> > +
> intel_cx0_get_powerdown_update(lane), 0,
> > +
> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
> > + drm_warn(&i915->drm, "PHY %c failed to bring out of Lane
> reset after %dus.\n",
> > + phy_name(phy),
> XELPDP_PORT_RESET_START_TIMEOUT_US);
> > +}
> > +
> > +static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum
> port port)
> > +{
> > + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> > + XELPDP_POWER_STATE_READY_MASK,
> > + XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
> > + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port),
> > + XELPDP_POWER_STATE_ACTIVE_MASK |
> > + XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
> > + XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
> > + XELPDP_PLL_LANE_STAGGERING_DELAY(0));
> > +}
> > +
> > +static u32 intel_cx0_get_pclk_refclk_request(u8 lane)
> > +{
> > + if (lane == INTEL_CX0_LANE0)
> > + return XELPDP_LANE0_PCLK_REFCLK_REQUEST;
> > + else if (lane == INTEL_CX0_LANE1)
> > + return XELPDP_LANE1_PCLK_REFCLK_REQUEST;
> > + else
> > + return XELPDP_LANE0_PCLK_REFCLK_REQUEST |
> > + XELPDP_LANE1_PCLK_REFCLK_REQUEST;
> > +}
> > +
> > +static u32 intel_cx0_get_pclk_refclk_ack(u8 lane)
> > +{
> > + if (lane == INTEL_CX0_LANE0)
> > + return XELPDP_LANE0_PCLK_REFCLK_ACK;
> > + else if (lane == INTEL_CX0_LANE1)
> > + return XELPDP_LANE1_PCLK_REFCLK_ACK;
> > + else
> > + return XELPDP_LANE0_PCLK_REFCLK_ACK |
> > + XELPDP_LANE1_PCLK_REFCLK_ACK;
> > +}
>
> Could simplify both of the above functions.
Yes.
>
> > +
> > +/* FIXME: Some Type-C cases need not reset both the lanes. Handle those
> cases. */
> > +static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915, enum
> port port,
> > + bool lane_reversal)
> > +{
> > + enum phy phy = intel_port_to_phy(i915, port);
> > + u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> > + INTEL_CX0_LANE0;
> > +
> > + if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
> > + XELPDP_PORT_BUF_SOC_PHY_READY,
> > + XELPDP_PORT_BUF_SOC_PHY_READY,
> > +
> XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
> > + drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset
> after %dus.\n",
> > + phy_name(phy),
> XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
> > +
> > + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> > + XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET,
> > + XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET);
> > +
> > + if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> > +
> XELPDP_LANE0_PHY_CURRENT_STATUS |
> XELPDP_LANE1_PHY_CURRENT_STATUS,
> > +
> XELPDP_LANE0_PHY_CURRENT_STATUS |
> XELPDP_LANE1_PHY_CURRENT_STATUS,
> > +
> XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
> > + drm_warn(&i915->drm, "PHY %c failed to bring out of Lane
> reset after %dus.\n",
> > + phy_name(phy),
> XELPDP_PORT_RESET_START_TIMEOUT_US);
> > +
> > + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
> > +
> intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES),
> > + intel_cx0_get_pclk_refclk_request(lane));
> > +
> > + if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
> > +
> intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES),
> > + intel_cx0_get_pclk_refclk_ack(lane),
> > +
> XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
> > + drm_warn(&i915->drm, "PHY %c failed to request refclk after
> %dus.\n",
> > + phy_name(phy),
> XELPDP_REFCLK_ENABLE_TIMEOUT_US);
> > +
> > + intel_cx0_powerdown_change_sequence(i915, port,
> INTEL_CX0_BOTH_LANES,
> > + CX0_P2_STATE_RESET);
> > + intel_cx0_setup_powerdown(i915, port);
> > +
> > + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> > + XELPDP_LANE0_PIPE_RESET | XELPDP_LANE1_PIPE_RESET,
> 0);
> > +
> > + if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port),
> > + XELPDP_LANE0_PHY_CURRENT_STATUS |
> > + XELPDP_LANE1_PHY_CURRENT_STATUS,
> > + XELPDP_PORT_RESET_END_TIMEOUT))
> > + drm_warn(&i915->drm, "PHY %c failed to bring out of Lane
> reset after %dms.\n",
> > + phy_name(phy),
> XELPDP_PORT_RESET_END_TIMEOUT);
> > +}
> > +
> > +static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
> > + struct intel_encoder *encoder, int
> lane_count,
> > + bool lane_reversal)
> > +{
> > + u8 l0t1, l0t2, l1t1, l1t2;
> > + bool dp_alt_mode =
> intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
> > + enum port port = encoder->port;
> > +
> > + intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> > + C10_VDR_CTRL_MSGBUS_ACCESS,
> C10_VDR_CTRL_MSGBUS_ACCESS,
> > + MB_WRITE_COMMITTED);
>
> TODO: DP-alt MFD case where only one PHY lane should be programmed.
TODO comment here or should I add the fix for DP-alt MFD case here?
>
> > +
> > + l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0,
> PHY_CX0_TX_CONTROL(1, 2));
> > + l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0,
> PHY_CX0_TX_CONTROL(2, 2));
> > + l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1,
> PHY_CX0_TX_CONTROL(1, 2));
> > + l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1,
> PHY_CX0_TX_CONTROL(2, 2));
> > +
>
> Would be clearer setting here CONTROL2_DISABLE_SINGLE_TX in all of
> l[0/1]t[1/2], and then
>
> > + if (lane_reversal) {
> > + switch (lane_count) {
> > + case 1:
> l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
> break;
>
> etc. for 2,3,4 lanes and then
>
> > + /* Disable MLs 1(lane0), 2(lane0), 3(lane1) */
> > + intel_cx0_write(i915, port, INTEL_CX0_LANE1,
> PHY_CX0_TX_CONTROL(1, 2),
> > + l1t1 |
> CONTROL2_DISABLE_SINGLE_TX,
> > + MB_WRITE_COMMITTED);
> > + fallthrough;
>
>
> > + case 2:
> > + /* Disable MLs 1(lane0), 2(lane0) */
> > + intel_cx0_write(i915, port, INTEL_CX0_LANE0,
> PHY_CX0_TX_CONTROL(2, 2),
> > + l0t2 |
> CONTROL2_DISABLE_SINGLE_TX,
> > + MB_WRITE_COMMITTED);
> > + fallthrough;
> > + case 3:
> > + /* Disable MLs 1(lane0) */
> > + intel_cx0_write(i915, port, INTEL_CX0_LANE0,
> PHY_CX0_TX_CONTROL(1, 2),
> > + l0t1 |
> CONTROL2_DISABLE_SINGLE_TX,
> > + MB_WRITE_COMMITTED);
> > + break;
> > + }
> > + } else {
> > + switch (lane_count) {
> > + case 1:
> > + if (dp_alt_mode) {
> > + /* Disable MLs 1(lane0), 3(lane1), 4(lane1) */
> > + intel_cx0_write(i915, port, INTEL_CX0_LANE0,
> PHY_CX0_TX_CONTROL(1, 2),
> > + l0t1 |
> CONTROL2_DISABLE_SINGLE_TX,
> > + MB_WRITE_COMMITTED);
> > + } else {
> > + /* Disable MLs 2(lane0), 3(lane1), 4(lane1) */
> > + intel_cx0_write(i915, port, INTEL_CX0_LANE0,
> PHY_CX0_TX_CONTROL(2, 2),
> > + l0t2 |
> CONTROL2_DISABLE_SINGLE_TX,
> > + MB_WRITE_COMMITTED);
> > + }
> > + fallthrough;
> > + case 2:
> > + /* Disable MLs 3(lane1), 4(lane1) */
> > + intel_cx0_write(i915, port, INTEL_CX0_LANE1,
> PHY_CX0_TX_CONTROL(1, 2),
> > + l1t1 |
> CONTROL2_DISABLE_SINGLE_TX,
> > + MB_WRITE_COMMITTED);
> > + fallthrough;
> > + case 3:
> > + /* Disable MLs 4(lane1) */
> > + intel_cx0_write(i915, port, INTEL_CX0_LANE1,
> PHY_CX0_TX_CONTROL(2, 2),
> > + l1t2 |
> CONTROL2_DISABLE_SINGLE_TX,
> > + MB_WRITE_COMMITTED);
> > + break;
> > + }
> > + }
>
> write here PHY_CX0_LANE[0/1], PHY_CX0_TX_CONTROL([1/2], 2)
Ok.
>
> > +
> > + if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) {
>
> This check is not needed, as we get here only for C10 PHY.
Right. I will remove that.
>
> > + intel_cx0_rmw(i915, port, INTEL_CX0_LANE1,
> PHY_C10_VDR_CONTROL(1),
> > + C10_VDR_CTRL_UPDATE_CFG |
> C10_VDR_CTRL_MSGBUS_ACCESS,
>
> Should the above clear C10_VDR_CTRL_MASTER_LANE?
>
> > + C10_VDR_CTRL_UPDATE_CFG,
> MB_WRITE_COMMITTED);
> > + intel_cx0_rmw(i915, port, INTEL_CX0_LANE0,
> PHY_C10_VDR_CONTROL(1),
> > + C10_VDR_CTRL_UPDATE_CFG |
> C10_VDR_CTRL_MSGBUS_ACCESS,
> > + C10_VDR_CTRL_MASTER_LANE |
> C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> > + }
> > +}
> > +
> > +static u32 intel_cx0_get_pclk_pll_request(u8 lane)
> > +{
> > + if (lane == INTEL_CX0_LANE0)
> > + return XELPDP_LANE0_PCLK_PLL_REQUEST;
> > + else if (lane == INTEL_CX0_LANE1)
> > + return XELPDP_LANE1_PCLK_PLL_REQUEST;
> > + else
> > + return XELPDP_LANE0_PCLK_PLL_REQUEST |
> > + XELPDP_LANE1_PCLK_PLL_REQUEST;
> > +}
> > +
> > +static u32 intel_cx0_get_pclk_pll_ack(u8 lane)
> > +{
> > + if (lane == INTEL_CX0_LANE0)
> > + return XELPDP_LANE0_PCLK_PLL_ACK;
> > + else if (lane == INTEL_CX0_LANE1)
> > + return XELPDP_LANE1_PCLK_PLL_ACK;
> > + else
> > + return XELPDP_LANE0_PCLK_PLL_ACK |
> > + XELPDP_LANE1_PCLK_PLL_ACK;
> > +}
>
> Could simplify the above functions.
Yes.
>
> > +
> > +static void intel_c10pll_enable(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > + bool lane_reversal = dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
> > + u8 maxpclk_lane = lane_reversal ? INTEL_CX0_LANE1 :
> > + INTEL_CX0_LANE0;
> > +
> > + /*
> > + * 1. Program PORT_CLOCK_CTL REGISTER to configure
> > + * clock muxes, gating and SSC
> > + */
> > + intel_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
> > +
> > + /* 2. Bring PHY out of reset. */
> > + intel_cx0_phy_lane_reset(i915, encoder->port, lane_reversal);
> > +
> > + /*
> > + * 3. Change Phy power state to Ready.
> > + * TODO: For DP alt mode use only one lane.
> > + */
> > + intel_cx0_powerdown_change_sequence(i915, encoder->port,
> INTEL_CX0_BOTH_LANES,
> > + CX0_P2_STATE_READY);
> > +
> > + /* 4. Program PHY internal PLL internal registers. */
> > + intel_c10_pll_program(i915, crtc_state, encoder);
> > +
> > + /*
> > + * 5. Program the enabled and disabled owned PHY lane
> > + * transmitters over message bus
> > + */
> > + intel_c10_program_phy_lane(i915, encoder, crtc_state->lane_count,
> lane_reversal);
> > +
> > + /*
> > + * 6. Follow the Display Voltage Frequency Switching - Sequence
> > + * Before Frequency Change. We handle this step in bxt_set_cdclk().
> > + */
> > +
> > + /*
> > + * 7. Program DDI_CLK_VALFREQ to match intended DDI
> > + * clock frequency.
> > + */
> > + intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
> > + crtc_state->port_clock);
> > + /*
> > + * 8. Set PORT_CLOCK_CTL register PCLK PLL Request
> > + * LN<Lane for maxPCLK> to "1" to enable PLL.
> > + */
> > + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> > + intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
> > + intel_cx0_get_pclk_pll_request(maxpclk_lane));
> > +
> > + /* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> ==
> "1". */
> > + if (__intel_de_wait_for_register(i915,
> XELPDP_PORT_CLOCK_CTL(encoder->port),
> > +
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
> > +
> intel_cx0_get_pclk_pll_ack(maxpclk_lane),
> > +
> XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
> > + drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n",
> > + phy_name(phy),
> XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US);
> > +
> > + /*
> > + * 10. Follow the Display Voltage Frequency Switching Sequence After
> > + * Frequency Change. We handle this step in bxt_set_cdclk().
> > + */
> > +}
> > +
> > +void intel_cx0pll_enable(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > +
> > + drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> > + intel_c10pll_enable(encoder, crtc_state);
>
> TBT-alt is not handled, so needs a TODO: comment.
At least this point it's not handled.
>
> > +}
> > +
> > +static void intel_c10pll_disable(struct intel_encoder *encoder)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > +
> > + /* 1. Change owned PHY lane power to Disable state. */
> > + intel_cx0_powerdown_change_sequence(i915, encoder->port,
> INTEL_CX0_BOTH_LANES,
> > + CX0_P2PG_STATE_DISABLE);
> > +
> > + /*
> > + * 2. Follow the Display Voltage Frequency Switching Sequence Before
> > + * Frequency Change. We handle this step in bxt_set_cdclk().
> > + */
> > +
> > + /*
> > + * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for
> maxPCLK>
> > + * to "0" to disable PLL.
> > + */
> > + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> > + intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
> > +
> intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
> > +
> > + /* 4. Program DDI_CLK_VALFREQ to 0. */
> > + intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
> > +
> > + /*
> > + * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**>
> == "0".
> > + */
> > + if (__intel_de_wait_for_register(i915,
> XELPDP_PORT_CLOCK_CTL(encoder->port),
> > +
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
> > +
> intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
> > +
> XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
> > + drm_warn(&i915->drm, "Port %c PLL not unlocked after
> %dus.\n",
> > + phy_name(phy),
> XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US);
> > +
> > + /*
> > + * 6. Follow the Display Voltage Frequency Switching Sequence After
> > + * Frequency Change. We handle this step in bxt_set_cdclk().
> > + */
> > +
> > + /* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
> > + intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
> > + XELPDP_DDI_CLOCK_SELECT_MASK |
> > + XELPDP_FORWARD_CLOCK_UNGATE, 0);
> > +}
> > +
> > +void intel_cx0pll_disable(struct intel_encoder *encoder)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > +
> > + drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> > + intel_c10pll_disable(encoder);
> > +}
> > +
> > +void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
> > + struct intel_crtc_state *new_crtc_state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(state->base.dev);
> > + struct intel_c10mpllb_state mpllb_hw_state = { 0 };
> > + struct intel_c10mpllb_state *mpllb_sw_state = &new_crtc_state-
> >c10mpllb_state;
> > + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> > + struct intel_encoder *encoder;
> > + struct intel_dp *intel_dp;
> > + enum phy phy;
> > + int i;
> > + bool use_ssc = false;
> > +
> > + if (DISPLAY_VER(i915) < 14)
> > + return;
> > +
> > + if (!new_crtc_state->hw.active)
> > + return;
> > +
> > + encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> > + phy = intel_port_to_phy(i915, encoder->port);
> > +
> > + if (intel_crtc_has_dp_encoder(new_crtc_state)) {
> > + intel_dp = enc_to_intel_dp(encoder);
> > + use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> > + DP_MAX_DOWNSPREAD_0_5);
> > +
> > + if (!intel_panel_use_ssc(i915))
> > + use_ssc = false;
> > + }
> > +
> > + if (!intel_is_c10phy(i915, phy))
> > + return;
> > +
> > + intel_c10mpllb_readout_hw_state(encoder, &mpllb_hw_state);
> > +
> > + for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {
> > + u8 expected;
> > +
> > + if (!use_ssc && i > 3 && i < 9)
> > + expected = 0;
> > + else
> > + expected = mpllb_sw_state->pll[i];
>
> The above isn't needed if PLL state is setup correctly in
> intel_c10mpllb_calc_state(), taking into account SSC as well.
Yes, this can be simplified with that change.
>
> > +
> > + I915_STATE_WARN(mpllb_hw_state.pll[i] != expected,
> > + "[CRTC:%d:%s] mismatch in C10MPLLB:
> Register[%d] (expected 0x%02x, found 0x%02x)",
> > + crtc->base.base.id, crtc->base.name,
> > + i, expected, mpllb_hw_state.pll[i]);
> > + }
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > new file mode 100644
> > index 000000000000..8cf340509097
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > @@ -0,0 +1,43 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2021 Intel Corporation
> > + */
> > +
> > +#ifndef __INTEL_CX0_PHY_H__
> > +#define __INTEL_CX0_PHY_H__
> > +
> > +#include <linux/types.h>
> > +#include <linux/bitfield.h>
> > +#include <linux/bits.h>
> > +
> > +#include "i915_drv.h"
> > +#include "intel_display_types.h"
> > +
> > +struct drm_i915_private;
> > +struct intel_encoder;
> > +struct intel_crtc_state;
> > +enum phy;
> > +
> > +#define INTEL_CX0_LANE0 0x1
> > +#define INTEL_CX0_LANE1 0x2
> > +#define INTEL_CX0_BOTH_LANES 0x3
>
> Please use INTEL_CX0_LANE0/1 instead of open-coding them.
>
> > +
> > +#define MB_WRITE_COMMITTED 1
> > +#define MB_WRITE_UNCOMMITTED 0
>
> The above should be bool values.
>
> Could the above be moved to intel_cx0_phy.c ?
Yes. These could be move to intel_cx0_phy.c
>
> > +
> > +bool intel_is_c10phy(struct drm_i915_private *dev_priv, enum phy phy);
> > +void intel_cx0pll_enable(struct intel_encoder *encoder,
> > + const struct intel_crtc_state *crtc_state);
> > +void intel_cx0pll_disable(struct intel_encoder *encoder);
> > +void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> > + struct intel_c10mpllb_state *pll_state);
> > +int intel_cx0mpllb_calc_state(struct intel_crtc_state *crtc_state,
> > + struct intel_encoder *encoder);
> > +void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv,
> > + const struct intel_c10mpllb_state *hw_state);
> > +int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder,
> > + const struct intel_c10mpllb_state *pll_state);
> > +void intel_c10mpllb_state_verify(struct intel_atomic_state *state,
> > + struct intel_crtc_state *new_crtc_state);
> > +
> > +#endif /* __INTEL_CX0_PHY_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > index d1ee8a2fc9cf..15e249f46a64 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> > @@ -128,4 +128,34 @@
> > #define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
> > #define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
> >
> > -#endif /* __INTEL_CX0_PHY_REGS_H__ */
> > +/* C10 Vendor Registers */
> > +#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
> > +#define C10_PLL0_FRACEN REG_BIT8(4)
> > +#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
> > +#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
> > +#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
> > +#define C10_CMN0_DP_VAL 0x21
> > +#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
> > +#define C10_CMN3_TXVBOOST(val)
> REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
> > +#define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
> > +#define C10_TX0_VAL 0x10
> > +#define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1)
> > +#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2)
> > +#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1)
> > +#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
> > +#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
> > +
> > +#define CX0_P0_STATE_ACTIVE 0x0
> > +#define CX0_P2_STATE_READY 0x2
> > +#define CX0_P2PG_STATE_DISABLE 0x9
> > +#define CX0_P4PG_STATE_DISABLE 0xC
> > +#define CX0_P2_STATE_RESET 0x2
> > +
> > +/* PHY_C10_VDR_PLL0 */
> > +#define PLL_C10_MPLL_SSC_EN REG_BIT8(0)
> > +
> > +/* PIPE SPEC Defined Registers */
> > +#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 +
> (control))
> > +#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
> > +
> > +#endif /* __INTEL_CX0_REG_DEFS_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 73240cf78c8b..a433dea5b9a3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -39,6 +39,7 @@
> > #include "intel_combo_phy_regs.h"
> > #include "intel_connector.h"
> > #include "intel_crtc.h"
> > +#include "intel_cx0_phy.h"
> > #include "intel_ddi.h"
> > #include "intel_ddi_buf_trans.h"
> > #include "intel_de.h"
> > @@ -3507,6 +3508,21 @@ void intel_ddi_get_clock(struct intel_encoder
> *encoder,
> > &crtc_state-
> >dpll_hw_state);
> > }
> >
> > +static void mtl_ddi_get_config(struct intel_encoder *encoder,
> > + struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > +
> > + drm_WARN_ON(&i915->drm, !intel_is_c10phy(i915, phy));
> > +
> > + intel_c10mpllb_readout_hw_state(encoder, &crtc_state-
> >c10mpllb_state);
> > + intel_c10mpllb_dump_hw_state(i915, &crtc_state->c10mpllb_state);
> > + crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder,
> &crtc_state->c10mpllb_state);
> > +
> > + intel_ddi_get_config(encoder, crtc_state);
> > +}
> > +
> > static void dg2_ddi_get_config(struct intel_encoder *encoder,
> > struct intel_crtc_state *crtc_state)
> > {
> > @@ -4413,7 +4429,11 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
> > encoder->cloneable = 0;
> > encoder->pipe_mask = ~0;
> >
> > - if (IS_DG2(dev_priv)) {
> > + if (DISPLAY_VER(dev_priv) >= 14) {
> > + encoder->enable_clock = intel_cx0pll_enable;
> > + encoder->disable_clock = intel_cx0pll_disable;
> > + encoder->get_config = mtl_ddi_get_config;
> > + } else if (IS_DG2(dev_priv)) {
> > encoder->enable_clock = intel_mpllb_enable;
> > encoder->disable_clock = intel_mpllb_disable;
> > encoder->get_config = dg2_ddi_get_config;
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index f86060195987..e23fecba446c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -1614,7 +1614,8 @@ static void icl_display_core_init(struct
> drm_i915_private *dev_priv,
> > return;
> >
> > /* 2. Initialize all combo phys */
> > - intel_combo_phy_init(dev_priv);
> > + if (DISPLAY_VER(dev_priv) < 14)
> > + intel_combo_phy_init(dev_priv);
>
> This shouldn't be needed, intel_combo_phy_init() handles only combo
> PHYs.
Ok. I remove this check. I think this was just added to play safe side.
>
> >
> > /*
> > * 3. Enable Power Well 1 (PG1).
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index 1676df1dc066..a4c8cb75c0a0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -970,7 +970,7 @@ void gen9_disable_dc_states(struct drm_i915_private
> *dev_priv)
> > if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> > bxt_verify_ddi_phy_power_wells(dev_priv);
> >
> > - if (DISPLAY_VER(dev_priv) >= 11)
> > + if (DISPLAY_VER(dev_priv) >= 11 && DISPLAY_VER(dev_priv) < 14)
>
> Isn't needed.
Ok.
>
> > /*
> > * DMC retains HW context only for port A, the other combo
> > * PHY's HW context for port B is lost after DC transitions,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index ab146b5b68bd..db7c108e4d86 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -985,6 +985,11 @@ struct intel_link_m_n {
> > u32 link_n;
> > };
> >
> > +struct intel_c10mpllb_state {
> > + u32 clock; /* in KHz */
> > + u8 pll[20];
> > +};
> > +
> > struct intel_crtc_state {
> > /*
> > * uapi (drm) state. This is the software state shown to userspace.
> > @@ -1128,6 +1133,7 @@ struct intel_crtc_state {
> > union {
> > struct intel_dpll_hw_state dpll_hw_state;
> > struct intel_mpllb_state mpllb_state;
> > + struct intel_c10mpllb_state c10mpllb_state;
> > };
> >
> > /*
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> > index 4e9c18be7e1f..da5aa050a5ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > @@ -8,6 +8,7 @@
> >
> > #include "i915_reg.h"
> > #include "intel_crtc.h"
> > +#include "intel_cx0_phy.h"
> > #include "intel_de.h"
> > #include "intel_display.h"
> > #include "intel_display_types.h"
> > @@ -995,6 +996,17 @@ static int dg2_crtc_compute_clock(struct
> intel_atomic_state *state,
> > return 0;
> > }
> >
> > +static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc)
> > +{
> > + struct intel_crtc_state *crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> > + struct intel_encoder *encoder =
> > + intel_get_crtc_new_encoder(state, crtc_state);
> > +
> > + return intel_cx0mpllb_calc_state(crtc_state, encoder);
> > +}
> > +
> > static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)
> > {
> > return dpll->m < factor * dpll->n;
> > @@ -1423,6 +1435,10 @@ static int i8xx_crtc_compute_clock(struct
> intel_atomic_state *state,
> > return 0;
> > }
> >
> > +static const struct intel_dpll_funcs mtl_dpll_funcs = {
> > + .crtc_compute_clock = mtl_crtc_compute_clock,
> > +};
> > +
> > static const struct intel_dpll_funcs dg2_dpll_funcs = {
> > .crtc_compute_clock = dg2_crtc_compute_clock,
> > };
> > @@ -1517,7 +1533,9 @@ int intel_dpll_crtc_get_shared_dpll(struct
> intel_atomic_state *state,
> > void
> > intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
> > {
> > - if (IS_DG2(dev_priv))
> > + if (DISPLAY_VER(dev_priv) >= 14)
> > + dev_priv->display.funcs.dpll = &mtl_dpll_funcs;
> > + else if (IS_DG2(dev_priv))
> > dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
> > else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
> > dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 22fc908b7e5d..ed372d227aa7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -4104,7 +4104,7 @@ void intel_shared_dpll_init(struct drm_i915_private
> *dev_priv)
> >
> > mutex_init(&dev_priv->display.dpll.lock);
> >
> > - if (IS_DG2(dev_priv))
> > + if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv))
> > /* No shared DPLLs on DG2; port PLLs are part of the PHY */
> > dpll_mgr = NULL;
> > else if (IS_ALDERLAKE_P(dev_priv))
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > index 842d70f0dfd2..ec504470c2f0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> > @@ -11,6 +11,7 @@
> > #include "intel_atomic.h"
> > #include "intel_crtc.h"
> > #include "intel_crtc_state_dump.h"
> > +#include "intel_cx0_phy.h"
> > #include "intel_display.h"
> > #include "intel_display_types.h"
> > #include "intel_fdi.h"
> > @@ -236,6 +237,7 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
> > verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
> > intel_shared_dpll_state_verify(crtc, old_crtc_state, new_crtc_state);
> > intel_mpllb_state_verify(state, new_crtc_state);
> > + intel_c10mpllb_state_verify(state, new_crtc_state);
> > }
> >
> > void intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> > index d22ffd7a32dc..94dd0d3a474b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2101,6 +2101,11 @@
> > #define TRANS_PUSH_EN REG_BIT(31)
> > #define TRANS_PUSH_SEND REG_BIT(30)
> >
> > +/* DDI Buffer Control */
> > +#define _DDI_CLK_VALFREQ_A 0x64030
> > +#define _DDI_CLK_VALFREQ_B 0x64130
> > +#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port,
> _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
> > +
> > /*
> > * HSW+ eDP PSR registers
> > *
> > diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h
> b/drivers/gpu/drm/i915/i915_reg_defs.h
> > index db26de6b57bc..f9d7c03e95d6 100644
> > --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> > +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> > @@ -22,6 +22,19 @@
> > BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
> > ((__n) < 0 || (__n) > 31))))
> >
> > +/**
> > + * REG_BIT8() - Prepare a u8 bit value
> > + * @__n: 0-based bit number
> > + *
> > + * Local wrapper for BIT() to force u8, with compile time checks.
> > + *
> > + * @return: Value with bit @__n set.
> > + */
> > +#define REG_BIT8(__n) \
> > + ((u8)(BIT(__n) + \
> > + BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
> > + ((__n) < 0 || (__n) > 7))))
> > +
> > /**
> > * REG_GENMASK() - Prepare a continuous u32 bitmask
> > * @__high: 0-based high bit
> > @@ -52,6 +65,21 @@
> > __is_constexpr(__low) && \
> > ((__low) < 0 || (__high) > 63 || (__low) >
> (__high)))))
> >
> > +/**
> > + * REG_GENMASK8() - Prepare a continuous u8 bitmask
> > + * @__high: 0-based high bit
> > + * @__low: 0-based low bit
> > + *
> > + * Local wrapper for GENMASK() to force u8, with compile time checks.
> > + *
> > + * @return: Continuous bitmask from @__high to @__low, inclusive.
> > + */
> > +#define REG_GENMASK8(__high, __low) \
> > + ((u8)(GENMASK(__high, __low) + \
> > + BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
> > + __is_constexpr(__low) && \
> > + ((__low) < 0 || (__high) > 7 || (__low) >
> (__high)))))
> > +
> > /*
> > * Local integer constant expression version of is_power_of_2().
> > */
> > @@ -74,6 +102,23 @@
> > BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL <<
> __bf_shf(__mask)))) + \
> >
> BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val),
> (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
> >
> > +/**
> > + * REG_FIELD_PREP8() - Prepare a u8 bitfield value
> > + * @__mask: shifted mask defining the field's length and position
> > + * @__val: value to put in the field
> > + *
> > + * Local copy of FIELD_PREP8() to generate an integer constant expression,
> force
> > + * u8 and for consistency with REG_FIELD_GET8(), REG_BIT8() and
> REG_GENMASK8().
> > + *
> > + * @return: @__val masked and shifted into the field defined by @__mask.
> > + */
> > +#define REG_FIELD_PREP8(__mask, __val) \
> > + ((u8)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
> > + BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
> > + BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U8_MAX) +
> \
> > + BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL <<
> __bf_shf(__mask)))) + \
> > +
> BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val),
> (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
> > +
> > /**
> > * REG_FIELD_GET() - Extract a u32 bitfield value
> > * @__mask: shifted mask defining the field's length and position
> > @@ -155,6 +200,18 @@
> > */
> > #define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
> >
> > +/**
> > + * REG_FIELD_GET8() - Extract a u8 bitfield value
> > + * @__mask: shifted mask defining the field's length and position
> > + * @__val: value to extract the bitfield value from
> > + *
> > + * Local wrapper for FIELD_GET() to force u8 and for consistency with
> > + * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
> > + *
> > + * @return: Masked and shifted value of the field defined by @__mask in
> @__val.
> > + */
> > +#define REG_FIELD_GET8(__mask, __val) ((u8)FIELD_GET(__mask, __val))
> > +
> > typedef struct {
> > u32 reg;
> > } i915_reg_t;
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-04-04 10:43 ` Kahola, Mika
@ 2023-04-04 11:47 ` Imre Deak
2023-04-04 13:01 ` Kahola, Mika
0 siblings, 1 reply; 37+ messages in thread
From: Imre Deak @ 2023-04-04 11:47 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx
On Tue, Apr 04, 2023 at 01:43:20PM +0300, Kahola, Mika wrote:
> [...]
> > > +static int __intel_cx0_read(struct drm_i915_private *i915, enum port port,
> > > + int lane, u16 addr, u32 *val)
> > > +{
> > > + enum phy phy = intel_port_to_phy(i915, port);
> > > + int ack;
> > > +
> > > + /* Wait for pending transactions.*/
> > > + if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> > > + XELPDP_PORT_M2P_TRANSACTION_PENDING,
> > > + XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> > > + drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
> > > + intel_cx0_bus_reset(i915, port, lane);
> >
> > Does bspec describe somewhere that this reset is needed?
>
> I think this plays on the safe side. If transaction is not completed
> withing reasonable time, we set the bus in known state. What would be
> the alternative? Just leave the bus state as is?
Not sure, since it's not specified; neither it is clear if it has
side-effects. In any case as I understand someone has actually seen this
being required after a transaction times out. If so please add a comment
both to here and to the 3-time retry loop, that neither of these are
required by the spec, but used as a workaround for these timeouts. (Also
I guess we'd need open HSD/bspec tickets for such WAs we came up with).
> > > + return -ETIMEDOUT;
> > > + }
> > > +
>
> [...]
>
> > > +void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> > > + struct intel_c10mpllb_state *pll_state)
> > > +{
> > > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> > > + u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> > > + INTEL_CX0_LANE0;
> > > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > > + int i;
> > > + u8 cmn, tx0;
> > > +
> > > + /*
> > > + * According to C10 VDR Register programming Sequence we need
> > > + * to do this to read PHY internal registers from MsgBus.
> > > + */
> > > + intel_cx0_rmw(i915, encoder->port, lane, PHY_C10_VDR_CONTROL(1), 0,
> > > + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
> > > +
> > > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > > + pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane,
> > > + PHY_C10_VDR_PLL(i));
> > > +
> > > + cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0));
> > > + tx0 = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0));
> >
> > The driver programs these registers, so why aren't they also stored in
> > the intell_c20pll_state struct?
>
> Maybe I'm not really following here but intel_c20pll_state has its own
> tx, cmn and mplla/mpllb stored.
Yes, just typoed that, I meant struct intel_c10mpllb_state which doesn't
include tx and cmn.
> > > +
> > > + if (tx0 != C10_TX0_VAL || cmn != C10_CMN0_DP_VAL)
> > > + drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
> > > + tx0, cmn, phy_name(phy));
> >
> > Shouldn't PHY_C10_VDR_CONTROL(1)/C10_VDR_CTRL_MSGBUS_ACCESS be
> > cleared here?
>
> Usually this means that we are not accessing these values from the
> register. Was this in the spec that we would need to clear it?
It does get cleared at the end of intel_c10_pll_program(), at least from
one of the PHY lanes, so was wondering why things are done differently
here. Yes, the spec doesn't require clearing it, but then it should not
be cleared at other places either (has related comments on this in
follow-up reviews).
> > > +}
> > > +
> > > +static void intel_c10_pll_program(struct drm_i915_private *i915,
> > > + const struct intel_crtc_state *crtc_state,
> > > + struct intel_encoder *encoder)
> > > +{
> > > + const struct intel_c10mpllb_state *pll_state = &crtc_state->c10mpllb_state;
> > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> > > + u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
> > > + INTEL_CX0_LANE0;
> > > + u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
> > > + INTEL_CX0_LANE1;
> > > +
> > > + int i;
> > > + struct intel_dp *intel_dp;
> > > + bool use_ssc = false;
> > > + u8 cmn0 = 0;
> > > +
> > > + if (intel_crtc_has_dp_encoder(crtc_state)) {
> > > + intel_dp = enc_to_intel_dp(encoder);
> > > + use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> > > + DP_MAX_DOWNSPREAD_0_5);
> > > +
> > > + if (!intel_panel_use_ssc(i915))
> > > + use_ssc = false;
> > > +
> > > + cmn0 = C10_CMN0_DP_VAL;
> >
> > Would be clearer by stg like:
> > /* Using x MHz reference */
> > cmn0 = C10_CMN0_REF_RANGE(1) | C10_CMN0_REF_CLK_MPLLB_DIV(2);
>
> Ok. I will do the change.
>
> >
> > > + }
> > > +
> > > + intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> > > + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
> >
> > For DP-alt MFD the PHY lane not owned by display shouldn't be
> > programmed, no?
>
> The spec says that with pin assignment D the lane 0 is owned by
> display. Lane 1 is owned by USB and shouldn't be programmed as the PHY
> will not respond.
Right, but both lanes are programmed. So would need a "FIXME: program only
lane 0 for DP-alt / MFD" comment.
> > > + /* Custom width needs to be programmed to 0 for both the phy lanes */
> > > + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> > > + PHY_C10_VDR_CUSTOM_WIDTH, 0x3, 0, MB_WRITE_COMMITTED);
> >
> > The above hard-coded values should have a macro definiton.
>
> Ok. I add these values as definitions
>
> > > + intel_cx0_rmw(i915, encoder->port, follower_lane, PHY_C10_VDR_CONTROL(1),
> > > + C10_VDR_CTRL_MASTER_LANE, C10_VDR_CTRL_UPDATE_CFG,
> > > + MB_WRITE_COMMITTED);
> > > +
> > > + /* Program the pll values only for the master lane */
> > > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > > + /* If not using ssc pll[4] through pll[8] must be 0*/
> > > + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_PLL(i),
> > > + (!use_ssc && (i > 3 && i < 9)) ? 0 : pll_state->pll[i],
> >
> > pll_state->pll should be setup already intel_c10mpllb_calc_state()
> > taking into account SSC as well.
>
> Yes, I will need this state calculation fixed.
>
> > > + (i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED);
> > > +
> > > + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
> > > + intel_cx0_write(i915, encoder->port, master_lane, PHY_C10_VDR_TX(0), C10_TX0_VAL, MB_WRITE_COMMITTED);
> >
> > Instead of C10_TX0_VAL the flags programmed should be better described
> > here as cmn0 above.
> Ok. I'll try to fix this.
>
> >
> > > + intel_cx0_rmw(i915, encoder->port, master_lane, PHY_C10_VDR_CONTROL(1),
> > > + C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MASTER_LANE |
> > > + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> > > +}
>
> [...]
>
> > > +static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
> > > + enum port port,
> > > + u8 lane, u8 state)
> > > +{
> > > + enum phy phy = intel_port_to_phy(i915, port);
> > > +
> > > + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> > > + XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK | XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK,
> > > + intel_cx0_get_powerdown_state(lane, state));
> > > + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> > > + XELPDP_LANE0_POWERDOWN_UPDATE | XELPDP_LANE1_POWERDOWN_UPDATE,
> > > + intel_cx0_get_powerdown_update(lane));
> >
> > The spec says (65451):
> > "Only update powerdown for one port at a time. Wait for powerdown
> > update to finish for one port before initiating update on another port."
> >
> > both could be updated at the same time if a non-zero stagger delay was
> > programmed, but for C10/C20 it must be programmed as 0.
>
> So this needs to be updated so that we update one port and wait for
> transaction to complete before updating the second port.
Yes.
> > > +
> > > + /* Update Timeout Value */
> > > + if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> > > + intel_cx0_get_powerdown_update(lane), 0,
> > > + XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
> > > + drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
> > > + phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
> > > +}
> > > +
>
> [...]
>
> > > +
> > > +static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
> > > + struct intel_encoder *encoder, int lane_count,
> > > + bool lane_reversal)
> > > +{
> > > + u8 l0t1, l0t2, l1t1, l1t2;
> > > + bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
> > > + enum port port = encoder->port;
> > > +
> > > + intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
> > > + C10_VDR_CTRL_MSGBUS_ACCESS, C10_VDR_CTRL_MSGBUS_ACCESS,
> > > + MB_WRITE_COMMITTED);
> >
> > TODO: DP-alt MFD case where only one PHY lane should be programmed.
>
> TODO comment here or should I add the fix for DP-alt MFD case here?
I think it could be fixed up later with all other places programming now
both PHY lanes unconditionally, adding only a TODO: comment here for now.
--Imre
>
> >
> > > +
> > > + l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));
> > > + l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));
> > > + l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2));
> > > + l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2));
> > > +
> >
> > Would be clearer setting here CONTROL2_DISABLE_SINGLE_TX in all of
> > l[0/1]t[1/2], and then
> >
> > > + if (lane_reversal) {
> > > + switch (lane_count) {
> > > + case 1:
> > l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
> > break;
> >
> > etc. for 2,3,4 lanes and then
> >
> > > + /* Disable MLs 1(lane0), 2(lane0), 3(lane1) */
> > > + intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
> > > + l1t1 | CONTROL2_DISABLE_SINGLE_TX,
> > > + MB_WRITE_COMMITTED);
> > > + fallthrough;
> >
> >
> > > + case 2:
> > > + /* Disable MLs 1(lane0), 2(lane0) */
> > > + intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
> > > + l0t2 | CONTROL2_DISABLE_SINGLE_TX,
> > > + MB_WRITE_COMMITTED);
> > > + fallthrough;
> > > + case 3:
> > > + /* Disable MLs 1(lane0) */
> > > + intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
> > > + l0t1 | CONTROL2_DISABLE_SINGLE_TX,
> > > + MB_WRITE_COMMITTED);
> > > + break;
> > > + }
> > > + } else {
> > > + switch (lane_count) {
> > > + case 1:
> > > + if (dp_alt_mode) {
> > > + /* Disable MLs 1(lane0), 3(lane1), 4(lane1) */
> > > + intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),
> > > + l0t1 | CONTROL2_DISABLE_SINGLE_TX,
> > > + MB_WRITE_COMMITTED);
> > > + } else {
> > > + /* Disable MLs 2(lane0), 3(lane1), 4(lane1) */
> > > + intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),
> > > + l0t2 | CONTROL2_DISABLE_SINGLE_TX,
> > > + MB_WRITE_COMMITTED);
> > > + }
> > > + fallthrough;
> > > + case 2:
> > > + /* Disable MLs 3(lane1), 4(lane1) */
> > > + intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(1, 2),
> > > + l1t1 | CONTROL2_DISABLE_SINGLE_TX,
> > > + MB_WRITE_COMMITTED);
> > > + fallthrough;
> > > + case 3:
> > > + /* Disable MLs 4(lane1) */
> > > + intel_cx0_write(i915, port, INTEL_CX0_LANE1, PHY_CX0_TX_CONTROL(2, 2),
> > > + l1t2 | CONTROL2_DISABLE_SINGLE_TX,
> > > + MB_WRITE_COMMITTED);
> > > + break;
> > > + }
> > > + }
> >
> > write here PHY_CX0_LANE[0/1], PHY_CX0_TX_CONTROL([1/2], 2)
> Ok.
>
> >
> > > +
> > > + if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) {
> >
> > This check is not needed, as we get here only for C10 PHY.
> Right. I will remove that.
>
> >
> > > + intel_cx0_rmw(i915, port, INTEL_CX0_LANE1, PHY_C10_VDR_CONTROL(1),
> > > + C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
> >
> > Should the above clear C10_VDR_CTRL_MASTER_LANE?
> >
> > > + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> > > + intel_cx0_rmw(i915, port, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),
> > > + C10_VDR_CTRL_UPDATE_CFG | C10_VDR_CTRL_MSGBUS_ACCESS,
> > > + C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> > > + }
> > > +}
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-04-04 11:47 ` Imre Deak
@ 2023-04-04 13:01 ` Kahola, Mika
2023-04-04 13:27 ` Imre Deak
0 siblings, 1 reply; 37+ messages in thread
From: Kahola, Mika @ 2023-04-04 13:01 UTC (permalink / raw)
To: Deak, Imre; +Cc: intel-gfx
> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Tuesday, April 4, 2023 2:47 PM
> To: Kahola, Mika <mika.kahola@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> <radhakrishna.sripada@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Sousa, Gustavo <gustavo.sousa@intel.com>
> Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> and pll programming
>
> On Tue, Apr 04, 2023 at 01:43:20PM +0300, Kahola, Mika wrote:
> > [...]
> > > > +static int __intel_cx0_read(struct drm_i915_private *i915, enum port
> port,
> > > > + int lane, u16 addr, u32 *val) {
> > > > + enum phy phy = intel_port_to_phy(i915, port);
> > > > + int ack;
> > > > +
> > > > + /* Wait for pending transactions.*/
> > > > + if (intel_de_wait_for_clear(i915,
> XELPDP_PORT_M2P_MSGBUS_CTL(port, lane - 1),
> > > > +
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> > > > + XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> > > > + drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for previous
> transaction to complete. Reset the bus and retry.\n", phy_name(phy));
> > > > + intel_cx0_bus_reset(i915, port, lane);
> > >
> > > Does bspec describe somewhere that this reset is needed?
> >
> > I think this plays on the safe side. If transaction is not completed
> > withing reasonable time, we set the bus in known state. What would be
> > the alternative? Just leave the bus state as is?
>
> Not sure, since it's not specified; neither it is clear if it has side-effects. In any
> case as I understand someone has actually seen this being required after a
> transaction times out. If so please add a comment both to here and to the 3-
> time retry loop, that neither of these are required by the spec, but used as a
> workaround for these timeouts. (Also I guess we'd need open HSD/bspec tickets
> for such WAs we came up with).
Let's play it safe. I add a comment here for the reset.
>
> > > > + return -ETIMEDOUT;
> > > > + }
> > > > +
> >
> > [...]
> >
> > > > +void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> > > > + struct intel_c10mpllb_state
> > > > +*pll_state) {
> > > > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > > + bool lane_reversal = dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
> > > > + u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> > > > + INTEL_CX0_LANE0;
> > > > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > > > + int i;
> > > > + u8 cmn, tx0;
> > > > +
> > > > + /*
> > > > + * According to C10 VDR Register programming Sequence we need
> > > > + * to do this to read PHY internal registers from MsgBus.
> > > > + */
> > > > + intel_cx0_rmw(i915, encoder->port, lane, PHY_C10_VDR_CONTROL(1),
> 0,
> > > > + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
> > > > +
> > > > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > > > + pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane,
> > > > +
> > > > + PHY_C10_VDR_PLL(i));
> > > > +
> > > > + cmn = intel_cx0_read(i915, encoder->port, lane,
> PHY_C10_VDR_CMN(0));
> > > > + tx0 = intel_cx0_read(i915, encoder->port, lane,
> > > > + PHY_C10_VDR_TX(0));
> > >
> > > The driver programs these registers, so why aren't they also stored
> > > in the intell_c20pll_state struct?
> >
> > Maybe I'm not really following here but intel_c20pll_state has its own
> > tx, cmn and mplla/mpllb stored.
>
> Yes, just typoed that, I meant struct intel_c10mpllb_state which doesn't include
> tx and cmn.
Yes, for C10 tx and cmn is missing. Maybe we could add those here as well. It seems that currently these are not necessary required but for the future use, these could be defined.
>
> > > > +
> > > > + if (tx0 != C10_TX0_VAL || cmn != C10_CMN0_DP_VAL)
> > > > + drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy:
> %c.\n",
> > > > + tx0, cmn, phy_name(phy));
> > >
> > > Shouldn't PHY_C10_VDR_CONTROL(1)/C10_VDR_CTRL_MSGBUS_ACCESS be
> > > cleared here?
> >
> > Usually this means that we are not accessing these values from the
> > register. Was this in the spec that we would need to clear it?
>
> It does get cleared at the end of intel_c10_pll_program(), at least from one of
> the PHY lanes, so was wondering why things are done differently here. Yes, the
> spec doesn't require clearing it, but then it should not be cleared at other places
> either (has related comments on this in follow-up reviews).
To be consistent maybe we can clear this here as well.
>
> > > > +}
> > > > +
> > > > +static void intel_c10_pll_program(struct drm_i915_private *i915,
> > > > + const struct intel_crtc_state *crtc_state,
> > > > + struct intel_encoder *encoder) {
> > > > + const struct intel_c10mpllb_state *pll_state = &crtc_state-
> >c10mpllb_state;
> > > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > > + bool lane_reversal = dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
> > > > + u8 master_lane = lane_reversal ? INTEL_CX0_LANE1 :
> > > > + INTEL_CX0_LANE0;
> > > > + u8 follower_lane = lane_reversal ? INTEL_CX0_LANE0 :
> > > > + INTEL_CX0_LANE1;
> > > > +
> > > > + int i;
> > > > + struct intel_dp *intel_dp;
> > > > + bool use_ssc = false;
> > > > + u8 cmn0 = 0;
> > > > +
> > > > + if (intel_crtc_has_dp_encoder(crtc_state)) {
> > > > + intel_dp = enc_to_intel_dp(encoder);
> > > > + use_ssc = (intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
> > > > + DP_MAX_DOWNSPREAD_0_5);
> > > > +
> > > > + if (!intel_panel_use_ssc(i915))
> > > > + use_ssc = false;
> > > > +
> > > > + cmn0 = C10_CMN0_DP_VAL;
> > >
> > > Would be clearer by stg like:
> > > /* Using x MHz reference */
> > > cmn0 = C10_CMN0_REF_RANGE(1) |
> > > C10_CMN0_REF_CLK_MPLLB_DIV(2);
> >
> > Ok. I will do the change.
> >
> > >
> > > > + }
> > > > +
> > > > + intel_cx0_write(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> > > > + C10_VDR_CTRL_MSGBUS_ACCESS,
> > > > + MB_WRITE_COMMITTED);
> > >
> > > For DP-alt MFD the PHY lane not owned by display shouldn't be
> > > programmed, no?
> >
> > The spec says that with pin assignment D the lane 0 is owned by
> > display. Lane 1 is owned by USB and shouldn't be programmed as the PHY
> > will not respond.
>
> Right, but both lanes are programmed. So would need a "FIXME: program only
> lane 0 for DP-alt / MFD" comment.
Yes, at least, we need this FIXME for now.
>
> > > > + /* Custom width needs to be programmed to 0 for both the phy lanes */
> > > > + intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES,
> > > > + PHY_C10_VDR_CUSTOM_WIDTH, 0x3, 0,
> > > > + MB_WRITE_COMMITTED);
> > >
> > > The above hard-coded values should have a macro definiton.
> >
> > Ok. I add these values as definitions
> >
> > > > + intel_cx0_rmw(i915, encoder->port, follower_lane,
> PHY_C10_VDR_CONTROL(1),
> > > > + C10_VDR_CTRL_MASTER_LANE, C10_VDR_CTRL_UPDATE_CFG,
> > > > + MB_WRITE_COMMITTED);
> > > > +
> > > > + /* Program the pll values only for the master lane */
> > > > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > > > + /* If not using ssc pll[4] through pll[8] must be 0*/
> > > > + intel_cx0_write(i915, encoder->port, master_lane,
> PHY_C10_VDR_PLL(i),
> > > > + (!use_ssc && (i > 3 && i < 9)) ? 0 :
> > > > + pll_state->pll[i],
> > >
> > > pll_state->pll should be setup already intel_c10mpllb_calc_state()
> > > taking into account SSC as well.
> >
> > Yes, I will need this state calculation fixed.
> >
> > > > + (i % 4) ? MB_WRITE_UNCOMMITTED :
> > > > + MB_WRITE_COMMITTED);
> > > > +
> > > > + intel_cx0_write(i915, encoder->port, master_lane,
> PHY_C10_VDR_CMN(0), cmn0, MB_WRITE_COMMITTED);
> > > > + intel_cx0_write(i915, encoder->port, master_lane,
> > > > + PHY_C10_VDR_TX(0), C10_TX0_VAL, MB_WRITE_COMMITTED);
> > >
> > > Instead of C10_TX0_VAL the flags programmed should be better
> > > described here as cmn0 above.
> > Ok. I'll try to fix this.
> >
> > >
> > > > + intel_cx0_rmw(i915, encoder->port, master_lane,
> PHY_C10_VDR_CONTROL(1),
> > > > + C10_VDR_CTRL_MSGBUS_ACCESS,
> C10_VDR_CTRL_MASTER_LANE |
> > > > + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); }
> >
> > [...]
> >
> > > > +static void intel_cx0_powerdown_change_sequence(struct
> drm_i915_private *i915,
> > > > + enum port port,
> > > > + u8 lane, u8 state) {
> > > > + enum phy phy = intel_port_to_phy(i915, port);
> > > > +
> > > > + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> > > > + XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK |
> XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK,
> > > > + intel_cx0_get_powerdown_state(lane, state));
> > > > + intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
> > > > + XELPDP_LANE0_POWERDOWN_UPDATE |
> XELPDP_LANE1_POWERDOWN_UPDATE,
> > > > + intel_cx0_get_powerdown_update(lane));
> > >
> > > The spec says (65451):
> > > "Only update powerdown for one port at a time. Wait for powerdown
> > > update to finish for one port before initiating update on another port."
> > >
> > > both could be updated at the same time if a non-zero stagger delay
> > > was programmed, but for C10/C20 it must be programmed as 0.
> >
> > So this needs to be updated so that we update one port and wait for
> > transaction to complete before updating the second port.
>
> Yes.
>
> > > > +
> > > > + /* Update Timeout Value */
> > > > + if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
> > > > +
> intel_cx0_get_powerdown_update(lane), 0,
> > > > +
> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
> > > > + drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset
> after %dus.\n",
> > > > + phy_name(phy),
> > > > +XELPDP_PORT_RESET_START_TIMEOUT_US);
> > > > +}
> > > > +
> >
> > [...]
> >
> > > > +
> > > > +static void intel_c10_program_phy_lane(struct drm_i915_private *i915,
> > > > + struct intel_encoder *encoder, int lane_count,
> > > > + bool lane_reversal) {
> > > > + u8 l0t1, l0t2, l1t1, l1t2;
> > > > + bool dp_alt_mode =
> intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
> > > > + enum port port = encoder->port;
> > > > +
> > > > + intel_cx0_rmw(i915, port, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> > > > + C10_VDR_CTRL_MSGBUS_ACCESS,
> C10_VDR_CTRL_MSGBUS_ACCESS,
> > > > + MB_WRITE_COMMITTED);
> > >
> > > TODO: DP-alt MFD case where only one PHY lane should be programmed.
> >
> > TODO comment here or should I add the fix for DP-alt MFD case here?
>
> I think it could be fixed up later with all other places programming now both PHY
> lanes unconditionally, adding only a TODO: comment here for now.
>
> --Imre
>
> >
> > >
> > > > +
> > > > + l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0,
> PHY_CX0_TX_CONTROL(1, 2));
> > > > + l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0,
> PHY_CX0_TX_CONTROL(2, 2));
> > > > + l1t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE1,
> PHY_CX0_TX_CONTROL(1, 2));
> > > > + l1t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE1,
> > > > + PHY_CX0_TX_CONTROL(2, 2));
> > > > +
> > >
> > > Would be clearer setting here CONTROL2_DISABLE_SINGLE_TX in all of
> > > l[0/1]t[1/2], and then
> > >
> > > > + if (lane_reversal) {
> > > > + switch (lane_count) {
> > > > + case 1:
> > > l1t1 &= ~CONTROL2_DISABLE_SINGLE_TX;
> > > break;
> > >
> > > etc. for 2,3,4 lanes and then
> > >
> > > > + /* Disable MLs 1(lane0), 2(lane0), 3(lane1) */
> > > > + intel_cx0_write(i915, port, INTEL_CX0_LANE1,
> PHY_CX0_TX_CONTROL(1, 2),
> > > > + l1t1 | CONTROL2_DISABLE_SINGLE_TX,
> > > > + MB_WRITE_COMMITTED);
> > > > + fallthrough;
> > >
> > >
> > > > + case 2:
> > > > + /* Disable MLs 1(lane0), 2(lane0) */
> > > > + intel_cx0_write(i915, port, INTEL_CX0_LANE0,
> PHY_CX0_TX_CONTROL(2, 2),
> > > > + l0t2 | CONTROL2_DISABLE_SINGLE_TX,
> > > > + MB_WRITE_COMMITTED);
> > > > + fallthrough;
> > > > + case 3:
> > > > + /* Disable MLs 1(lane0) */
> > > > + intel_cx0_write(i915, port, INTEL_CX0_LANE0,
> PHY_CX0_TX_CONTROL(1, 2),
> > > > + l0t1 | CONTROL2_DISABLE_SINGLE_TX,
> > > > + MB_WRITE_COMMITTED);
> > > > + break;
> > > > + }
> > > > + } else {
> > > > + switch (lane_count) {
> > > > + case 1:
> > > > + if (dp_alt_mode) {
> > > > + /* Disable MLs 1(lane0), 3(lane1), 4(lane1) */
> > > > + intel_cx0_write(i915, port, INTEL_CX0_LANE0,
> PHY_CX0_TX_CONTROL(1, 2),
> > > > + l0t1 | CONTROL2_DISABLE_SINGLE_TX,
> > > > + MB_WRITE_COMMITTED);
> > > > + } else {
> > > > + /* Disable MLs 2(lane0), 3(lane1), 4(lane1) */
> > > > + intel_cx0_write(i915, port, INTEL_CX0_LANE0,
> PHY_CX0_TX_CONTROL(2, 2),
> > > > + l0t2 | CONTROL2_DISABLE_SINGLE_TX,
> > > > + MB_WRITE_COMMITTED);
> > > > + }
> > > > + fallthrough;
> > > > + case 2:
> > > > + /* Disable MLs 3(lane1), 4(lane1) */
> > > > + intel_cx0_write(i915, port, INTEL_CX0_LANE1,
> PHY_CX0_TX_CONTROL(1, 2),
> > > > + l1t1 | CONTROL2_DISABLE_SINGLE_TX,
> > > > + MB_WRITE_COMMITTED);
> > > > + fallthrough;
> > > > + case 3:
> > > > + /* Disable MLs 4(lane1) */
> > > > + intel_cx0_write(i915, port, INTEL_CX0_LANE1,
> PHY_CX0_TX_CONTROL(2, 2),
> > > > + l1t2 | CONTROL2_DISABLE_SINGLE_TX,
> > > > + MB_WRITE_COMMITTED);
> > > > + break;
> > > > + }
> > > > + }
> > >
> > > write here PHY_CX0_LANE[0/1], PHY_CX0_TX_CONTROL([1/2], 2)
> > Ok.
> >
> > >
> > > > +
> > > > + if (intel_is_c10phy(i915, intel_port_to_phy(i915, port))) {
> > >
> > > This check is not needed, as we get here only for C10 PHY.
> > Right. I will remove that.
> >
> > >
> > > > + intel_cx0_rmw(i915, port, INTEL_CX0_LANE1,
> PHY_C10_VDR_CONTROL(1),
> > > > + C10_VDR_CTRL_UPDATE_CFG |
> > > > + C10_VDR_CTRL_MSGBUS_ACCESS,
> > >
> > > Should the above clear C10_VDR_CTRL_MASTER_LANE?
> > >
> > > > + C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> > > > + intel_cx0_rmw(i915, port, INTEL_CX0_LANE0,
> PHY_C10_VDR_CONTROL(1),
> > > > + C10_VDR_CTRL_UPDATE_CFG |
> C10_VDR_CTRL_MSGBUS_ACCESS,
> > > > + C10_VDR_CTRL_MASTER_LANE |
> C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
> > > > + }
> > > > +}
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-04-04 13:01 ` Kahola, Mika
@ 2023-04-04 13:27 ` Imre Deak
2023-04-04 16:50 ` Sripada, Radhakrishna
0 siblings, 1 reply; 37+ messages in thread
From: Imre Deak @ 2023-04-04 13:27 UTC (permalink / raw)
To: Kahola, Mika; +Cc: intel-gfx
On Tue, Apr 04, 2023 at 04:01:55PM +0300, Kahola, Mika wrote:
> [...]
> > >
> > > > > +void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> > > > > + struct intel_c10mpllb_state
> > > > > +*pll_state) {
> > > > > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > > > + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> > > > > + u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> > > > > + INTEL_CX0_LANE0;
> > > > > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > > > > + int i;
> > > > > + u8 cmn, tx0;
> > > > > +
> > > > > + /*
> > > > > + * According to C10 VDR Register programming Sequence we need
> > > > > + * to do this to read PHY internal registers from MsgBus.
> > > > > + */
> > > > > + intel_cx0_rmw(i915, encoder->port, lane, PHY_C10_VDR_CONTROL(1), 0,
> > > > > + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
> > > > > +
> > > > > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > > > > + pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_PLL(i));
> > > > > +
> > > > > + cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0));
> > > > > + tx0 = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0));
> > > >
> > > > The driver programs these registers, so why aren't they also stored
> > > > in the intell_c20pll_state struct?
> > >
> > > Maybe I'm not really following here but intel_c20pll_state has its own
> > > tx, cmn and mplla/mpllb stored.
> >
> > Yes, just typoed that, I meant struct intel_c10mpllb_state which
> > doesn't include tx and cmn.
>
> Yes, for C10 tx and cmn is missing. Maybe we could add those here as
> well. It seems that currently these are not necessary required but for
> the future use, these could be defined.
These are needed already now to make the state computation / HW readout /
state checking work for these two params the same way they do for the
rest of PLL state.
> > > > > +
> > > > > + if (tx0 != C10_TX0_VAL || cmn != C10_CMN0_DP_VAL)
> > > > > + drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy: %c.\n",
> > > > > + tx0, cmn, phy_name(phy));
> > > >
> > > > Shouldn't PHY_C10_VDR_CONTROL(1)/C10_VDR_CTRL_MSGBUS_ACCESS be
> > > > cleared here?
> > >
> > > Usually this means that we are not accessing these values from the
> > > register. Was this in the spec that we would need to clear it?
> >
> > It does get cleared at the end of intel_c10_pll_program(), at least
> > from one of the PHY lanes, so was wondering why things are done
> > differently here. Yes, the spec doesn't require clearing it, but
> > then it should not be cleared at other places either (has related
> > comments on this in follow-up reviews).
>
> To be consistent maybe we can clear this here as well.
If there is no need for it, let's follow the spec and not clear it at
any other spot either.
>
> >
> > > > > +}
> > > > > +
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-04-04 13:27 ` Imre Deak
@ 2023-04-04 16:50 ` Sripada, Radhakrishna
2023-04-04 18:03 ` Imre Deak
0 siblings, 1 reply; 37+ messages in thread
From: Sripada, Radhakrishna @ 2023-04-04 16:50 UTC (permalink / raw)
To: Deak, Imre, Kahola, Mika; +Cc: intel-gfx
> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Tuesday, April 4, 2023 6:28 AM
> To: Kahola, Mika <mika.kahola@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> <radhakrishna.sripada@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> Sousa, Gustavo <gustavo.sousa@intel.com>
> Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> and pll programming
>
> On Tue, Apr 04, 2023 at 04:01:55PM +0300, Kahola, Mika wrote:
> > [...]
> > > >
> > > > > > +void intel_c10mpllb_readout_hw_state(struct intel_encoder
> *encoder,
> > > > > > + struct intel_c10mpllb_state
> > > > > > +*pll_state) {
> > > > > > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > > > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > > > > + bool lane_reversal = dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
> > > > > > + u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> > > > > > + INTEL_CX0_LANE0;
> > > > > > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > > > > > + int i;
> > > > > > + u8 cmn, tx0;
> > > > > > +
> > > > > > + /*
> > > > > > + * According to C10 VDR Register programming Sequence we need
> > > > > > + * to do this to read PHY internal registers from MsgBus.
> > > > > > + */
> > > > > > + intel_cx0_rmw(i915, encoder->port, lane,
> PHY_C10_VDR_CONTROL(1), 0,
> > > > > > + C10_VDR_CTRL_MSGBUS_ACCESS,
> MB_WRITE_COMMITTED);
> > > > > > +
> > > > > > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > > > > > + pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane,
> PHY_C10_VDR_PLL(i));
> > > > > > +
> > > > > > + cmn = intel_cx0_read(i915, encoder->port, lane,
> PHY_C10_VDR_CMN(0));
> > > > > > + tx0 = intel_cx0_read(i915, encoder->port, lane,
> PHY_C10_VDR_TX(0));
> > > > >
> > > > > The driver programs these registers, so why aren't they also stored
> > > > > in the intell_c20pll_state struct?
> > > >
> > > > Maybe I'm not really following here but intel_c20pll_state has its own
> > > > tx, cmn and mplla/mpllb stored.
> > >
> > > Yes, just typoed that, I meant struct intel_c10mpllb_state which
> > > doesn't include tx and cmn.
> >
> > Yes, for C10 tx and cmn is missing. Maybe we could add those here as
> > well. It seems that currently these are not necessary required but for
> > the future use, these could be defined.
>
> These are needed already now to make the state computation / HW readout /
> state checking work for these two params the same way they do for the
> rest of PLL state.
I believe C10 tx and cmn values are not changing across frequencies. Cmn on ly
Changes for DP and HDMI so does it make sense to include in the pll structure?
-RK
>
> > > > > > +
> > > > > > + if (tx0 != C10_TX0_VAL || cmn != C10_CMN0_DP_VAL)
> > > > > > + drm_warn(&i915->drm, "Unexpected tx: %x or cmn: %x for phy:
> %c.\n",
> > > > > > + tx0, cmn, phy_name(phy));
> > > > >
> > > > > Shouldn't
> PHY_C10_VDR_CONTROL(1)/C10_VDR_CTRL_MSGBUS_ACCESS be
> > > > > cleared here?
> > > >
> > > > Usually this means that we are not accessing these values from the
> > > > register. Was this in the spec that we would need to clear it?
> > >
> > > It does get cleared at the end of intel_c10_pll_program(), at least
> > > from one of the PHY lanes, so was wondering why things are done
> > > differently here. Yes, the spec doesn't require clearing it, but
> > > then it should not be cleared at other places either (has related
> > > comments on this in follow-up reviews).
> >
> > To be consistent maybe we can clear this here as well.
>
> If there is no need for it, let's follow the spec and not clear it at
> any other spot either.
>
> >
> > >
> > > > > > +}
> > > > > > +
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-04-04 16:50 ` Sripada, Radhakrishna
@ 2023-04-04 18:03 ` Imre Deak
2023-04-04 19:22 ` Sripada, Radhakrishna
0 siblings, 1 reply; 37+ messages in thread
From: Imre Deak @ 2023-04-04 18:03 UTC (permalink / raw)
To: Sripada, Radhakrishna; +Cc: intel-gfx
On Tue, Apr 04, 2023 at 07:50:00PM +0300, Sripada, Radhakrishna wrote:
>
>
> > -----Original Message-----
> > From: Deak, Imre <imre.deak@intel.com>
> > Sent: Tuesday, April 4, 2023 6:28 AM
> > To: Kahola, Mika <mika.kahola@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> > <radhakrishna.sripada@intel.com>; Shankar, Uma <uma.shankar@intel.com>;
> > Sousa, Gustavo <gustavo.sousa@intel.com>
> > Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> > and pll programming
> >
> > On Tue, Apr 04, 2023 at 04:01:55PM +0300, Kahola, Mika wrote:
> > > [...]
> > > > >
> > > > > > > +void intel_c10mpllb_readout_hw_state(struct intel_encoder *encoder,
> > > > > > > + struct intel_c10mpllb_state pll_state) {
> > > > > > > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > > > > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > > > > > + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> > > > > > > + u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> > > > > > > + INTEL_CX0_LANE0;
> > > > > > > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > > > > > > + int i;
> > > > > > > + u8 cmn, tx0;
> > > > > > > +
> > > > > > > + /*
> > > > > > > + * According to C10 VDR Register programming Sequence we need
> > > > > > > + * to do this to read PHY internal registers from MsgBus.
> > > > > > > + */
> > > > > > > + intel_cx0_rmw(i915, encoder->port, lane, PHY_C10_VDR_CONTROL(1), 0,
> > > > > > > + C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
> > > > > > > +
> > > > > > > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > > > > > > + pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_PLL(i));
> > > > > > > +
> > > > > > > + cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0));
> > > > > > > + tx0 = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0));
> > > > > >
> > > > > > The driver programs these registers, so why aren't they also stored
> > > > > > in the intell_c20pll_state struct?
> > > > >
> > > > > Maybe I'm not really following here but intel_c20pll_state has its own
> > > > > tx, cmn and mplla/mpllb stored.
> > > >
> > > > Yes, just typoed that, I meant struct intel_c10mpllb_state which
> > > > doesn't include tx and cmn.
> > >
> > > Yes, for C10 tx and cmn is missing. Maybe we could add those here as
> > > well. It seems that currently these are not necessary required but for
> > > the future use, these could be defined.
> >
> > These are needed already now to make the state computation / HW readout /
> > state checking work for these two params the same way they do for the
> > rest of PLL state.
>
> I believe C10 tx and cmn values are not changing across frequencies. Cmn only
> Changes for DP and HDMI so does it make sense to include in the pll structure?
They should be part of the atomic state. To save the bytes in the
precomputed tables they could be added to intel_cx0pll_state, something
like:
struct intel_cx0pll_state {
union {
struct {
struct intel_c10mpllb_state pllb;
u8 cmn;
u8 tx;
} c10;
struct intel_c20pll_state c20pll_state;
};
};
--Imre
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-04-04 18:03 ` Imre Deak
@ 2023-04-04 19:22 ` Sripada, Radhakrishna
2023-04-04 21:28 ` Imre Deak
0 siblings, 1 reply; 37+ messages in thread
From: Sripada, Radhakrishna @ 2023-04-04 19:22 UTC (permalink / raw)
To: Deak, Imre; +Cc: intel-gfx
> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Tuesday, April 4, 2023 11:03 AM
> To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> Cc: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org;
> Shankar, Uma <uma.shankar@intel.com>; Sousa, Gustavo
> <gustavo.sousa@intel.com>
> Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> and pll programming
>
> On Tue, Apr 04, 2023 at 07:50:00PM +0300, Sripada, Radhakrishna wrote:
> >
> >
> > > -----Original Message-----
> > > From: Deak, Imre <imre.deak@intel.com>
> > > Sent: Tuesday, April 4, 2023 6:28 AM
> > > To: Kahola, Mika <mika.kahola@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> > > <radhakrishna.sripada@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>;
> > > Sousa, Gustavo <gustavo.sousa@intel.com>
> > > Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message
> bus
> > > and pll programming
> > >
> > > On Tue, Apr 04, 2023 at 04:01:55PM +0300, Kahola, Mika wrote:
> > > > [...]
> > > > > >
> > > > > > > > +void intel_c10mpllb_readout_hw_state(struct intel_encoder
> *encoder,
> > > > > > > > + struct intel_c10mpllb_state pll_state) {
> > > > > > > > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > > > > > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > > > > > > + bool lane_reversal = dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
> > > > > > > > + u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> > > > > > > > + INTEL_CX0_LANE0;
> > > > > > > > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > > > > > > > + int i;
> > > > > > > > + u8 cmn, tx0;
> > > > > > > > +
> > > > > > > > + /*
> > > > > > > > + * According to C10 VDR Register programming Sequence we
> need
> > > > > > > > + * to do this to read PHY internal registers from MsgBus.
> > > > > > > > + */
> > > > > > > > + intel_cx0_rmw(i915, encoder->port, lane,
> PHY_C10_VDR_CONTROL(1), 0,
> > > > > > > > + C10_VDR_CTRL_MSGBUS_ACCESS,
> MB_WRITE_COMMITTED);
> > > > > > > > +
> > > > > > > > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > > > > > > > + pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane,
> PHY_C10_VDR_PLL(i));
> > > > > > > > +
> > > > > > > > + cmn = intel_cx0_read(i915, encoder->port, lane,
> PHY_C10_VDR_CMN(0));
> > > > > > > > + tx0 = intel_cx0_read(i915, encoder->port, lane,
> PHY_C10_VDR_TX(0));
> > > > > > >
> > > > > > > The driver programs these registers, so why aren't they also stored
> > > > > > > in the intell_c20pll_state struct?
> > > > > >
> > > > > > Maybe I'm not really following here but intel_c20pll_state has its own
> > > > > > tx, cmn and mplla/mpllb stored.
> > > > >
> > > > > Yes, just typoed that, I meant struct intel_c10mpllb_state which
> > > > > doesn't include tx and cmn.
> > > >
> > > > Yes, for C10 tx and cmn is missing. Maybe we could add those here as
> > > > well. It seems that currently these are not necessary required but for
> > > > the future use, these could be defined.
> > >
> > > These are needed already now to make the state computation / HW readout
> /
> > > state checking work for these two params the same way they do for the
> > > rest of PLL state.
> >
> > I believe C10 tx and cmn values are not changing across frequencies. Cmn only
> > Changes for DP and HDMI so does it make sense to include in the pll structure?
>
> They should be part of the atomic state. To save the bytes in the
> precomputed tables they could be added to intel_cx0pll_state, something
> like:
>
> struct intel_cx0pll_state {
> union {
> struct {
> struct intel_c10mpllb_state pllb;
> u8 cmn;
> u8 tx;
> } c10;
> struct intel_c20pll_state c20pll_state;
> };
> };
>
I am bit concerned about the mismatch in the names for c10 and c20 states,
adding further complexity in the structure may look more ugly. Let us afford the
extra space in the tables if they need to be part of the atomic state and maintain
homogeneity across c10 and c20 structures.
Thoughts?
-RK
> --Imre
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
2023-04-04 19:22 ` Sripada, Radhakrishna
@ 2023-04-04 21:28 ` Imre Deak
0 siblings, 0 replies; 37+ messages in thread
From: Imre Deak @ 2023-04-04 21:28 UTC (permalink / raw)
To: Sripada, Radhakrishna; +Cc: intel-gfx
On Tue, Apr 04, 2023 at 10:22:53PM +0300, Sripada, Radhakrishna wrote:
>
>
> > -----Original Message-----
> > From: Deak, Imre <imre.deak@intel.com>
> > Sent: Tuesday, April 4, 2023 11:03 AM
> > To: Sripada, Radhakrishna <radhakrishna.sripada@intel.com>
> > Cc: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org;
> > Shankar, Uma <uma.shankar@intel.com>; Sousa, Gustavo
> > <gustavo.sousa@intel.com>
> > Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus
> > and pll programming
> >
> > On Tue, Apr 04, 2023 at 07:50:00PM +0300, Sripada, Radhakrishna wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Deak, Imre <imre.deak@intel.com>
> > > > Sent: Tuesday, April 4, 2023 6:28 AM
> > > > To: Kahola, Mika <mika.kahola@intel.com>
> > > > Cc: intel-gfx@lists.freedesktop.org; Sripada, Radhakrishna
> > > > <radhakrishna.sripada@intel.com>; Shankar, Uma
> > <uma.shankar@intel.com>;
> > > > Sousa, Gustavo <gustavo.sousa@intel.com>
> > > > Subject: Re: [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message
> > bus
> > > > and pll programming
> > > >
> > > > On Tue, Apr 04, 2023 at 04:01:55PM +0300, Kahola, Mika wrote:
> > > > > [...]
> > > > > > >
> > > > > > > > > +void intel_c10mpllb_readout_hw_state(struct intel_encoder
> > *encoder,
> > > > > > > > > + struct intel_c10mpllb_state pll_state) {
> > > > > > > > > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > > > > > > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > > > > > > > + bool lane_reversal = dig_port->saved_port_bits &
> > DDI_BUF_PORT_REVERSAL;
> > > > > > > > > + u8 lane = lane_reversal ? INTEL_CX0_LANE1 :
> > > > > > > > > + INTEL_CX0_LANE0;
> > > > > > > > > + enum phy phy = intel_port_to_phy(i915, encoder->port);
> > > > > > > > > + int i;
> > > > > > > > > + u8 cmn, tx0;
> > > > > > > > > +
> > > > > > > > > + /*
> > > > > > > > > + * According to C10 VDR Register programming Sequence we
> > need
> > > > > > > > > + * to do this to read PHY internal registers from MsgBus.
> > > > > > > > > + */
> > > > > > > > > + intel_cx0_rmw(i915, encoder->port, lane,
> > PHY_C10_VDR_CONTROL(1), 0,
> > > > > > > > > + C10_VDR_CTRL_MSGBUS_ACCESS,
> > MB_WRITE_COMMITTED);
> > > > > > > > > +
> > > > > > > > > + for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
> > > > > > > > > + pll_state->pll[i] = intel_cx0_read(i915, encoder->port, lane,
> > PHY_C10_VDR_PLL(i));
> > > > > > > > > +
> > > > > > > > > + cmn = intel_cx0_read(i915, encoder->port, lane,
> > PHY_C10_VDR_CMN(0));
> > > > > > > > > + tx0 = intel_cx0_read(i915, encoder->port, lane,
> > PHY_C10_VDR_TX(0));
> > > > > > > >
> > > > > > > > The driver programs these registers, so why aren't they also stored
> > > > > > > > in the intell_c20pll_state struct?
> > > > > > >
> > > > > > > Maybe I'm not really following here but intel_c20pll_state has its own
> > > > > > > tx, cmn and mplla/mpllb stored.
> > > > > >
> > > > > > Yes, just typoed that, I meant struct intel_c10mpllb_state which
> > > > > > doesn't include tx and cmn.
> > > > >
> > > > > Yes, for C10 tx and cmn is missing. Maybe we could add those here as
> > > > > well. It seems that currently these are not necessary required but for
> > > > > the future use, these could be defined.
> > > >
> > > > These are needed already now to make the state computation / HW readout
> > /
> > > > state checking work for these two params the same way they do for the
> > > > rest of PLL state.
> > >
> > > I believe C10 tx and cmn values are not changing across frequencies. Cmn only
> > > Changes for DP and HDMI so does it make sense to include in the pll structure?
> >
> > They should be part of the atomic state. To save the bytes in the
> > precomputed tables they could be added to intel_cx0pll_state, something
> > like:
> >
> > struct intel_cx0pll_state {
> > union {
> > struct {
> > struct intel_c10mpllb_state pllb;
> > u8 cmn;
> > u8 tx;
> > } c10;
> > struct intel_c20pll_state c20pll_state;
> > };
> > };
> >
> I am bit concerned about the mismatch in the names for c10 and c20 states,
> adding further complexity in the structure may look more ugly. Let us afford the
> extra space in the tables if they need to be part of the atomic state and maintain
> homogeneity across c10 and c20 structures.
Both ways are better than the current way and fine by me.
>
> Thoughts?
>
> -RK
> > --Imre
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
` (14 preceding siblings ...)
2023-03-30 8:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2023-04-05 8:52 ` Andi Shyti
15 siblings, 0 replies; 37+ messages in thread
From: Andi Shyti @ 2023-04-05 8:52 UTC (permalink / raw)
To: Mika Kahola; +Cc: intel-gfx
Hi Mika,
On Mon, Mar 27, 2023 at 03:34:26PM +0300, Mika Kahola wrote:
> Phy programming support for C10 PICA chips. This is the first part of
> the series that adds support for PICA chips. Later the support for
> C20 chips are added.
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>
> Clint Taylor (1):
> drm/i915/mtl: Initial DDI port setup
>
> Mika Kahola (3):
> drm/i915/mtl: Add DP rates
> drm/i915/mtl: Create separate reg file for PICA registers
> drm/i915/mtl: Add support for PM DEMAND
>
> Radhakrishna Sripada (3):
> drm/i915/mtl: Add Support for C10 PHY message bus and pll programming
> drm/i915/mtl: Add C10 phy programming for HDMI
> drm/i915/mtl: Add vswing programming for C10 phys
please add your SoB at the end of every patch. The last tag needs
to be the SoB of the person who is sending the patch.
Thanks,
Andi
^ permalink raw reply [flat|nested] 37+ messages in thread
end of thread, other threads:[~2023-04-05 8:53 UTC | newest]
Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-27 12:34 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Mika Kahola
2023-03-27 12:34 ` [Intel-gfx] [PATCH 1/7] drm/i915/mtl: Initial DDI port setup Mika Kahola
2023-03-28 11:41 ` Govindapillai, Vinod
2023-03-27 12:34 ` [Intel-gfx] [PATCH 2/7] drm/i915/mtl: Add DP rates Mika Kahola
2023-03-28 12:49 ` Govindapillai, Vinod
2023-03-27 12:34 ` [Intel-gfx] [PATCH 3/7] drm/i915/mtl: Create separate reg file for PICA registers Mika Kahola
2023-03-28 15:33 ` Govindapillai, Vinod
2023-03-27 12:34 ` [Intel-gfx] [PATCH 4/7] drm/i915/mtl: Add Support for C10 PHY message bus and pll programming Mika Kahola
2023-03-29 10:22 ` Govindapillai, Vinod
2023-03-29 15:40 ` Imre Deak
2023-03-29 15:59 ` Imre Deak
2023-04-04 10:43 ` Kahola, Mika
2023-04-04 11:47 ` Imre Deak
2023-04-04 13:01 ` Kahola, Mika
2023-04-04 13:27 ` Imre Deak
2023-04-04 16:50 ` Sripada, Radhakrishna
2023-04-04 18:03 ` Imre Deak
2023-04-04 19:22 ` Sripada, Radhakrishna
2023-04-04 21:28 ` Imre Deak
2023-04-03 10:11 ` Imre Deak
2023-04-03 10:19 ` Kahola, Mika
2023-04-03 10:36 ` Imre Deak
2023-04-03 10:43 ` Kahola, Mika
2023-03-27 12:34 ` [Intel-gfx] [PATCH 5/7] drm/i915/mtl: Add C10 phy programming for HDMI Mika Kahola
2023-04-03 10:26 ` Imre Deak
2023-03-27 12:34 ` [Intel-gfx] [PATCH 6/7] drm/i915/mtl: Add vswing programming for C10 phys Mika Kahola
2023-04-03 11:18 ` Imre Deak
2023-03-27 12:34 ` [Intel-gfx] [PATCH 7/7] drm/i915/mtl: Add support for PM DEMAND Mika Kahola
2023-03-27 19:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add Support for C10 chips Patchwork
2023-03-27 19:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-27 19:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-28 1:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-29 16:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Add Support for C10 chips (rev2) Patchwork
2023-03-29 16:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-29 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-30 8:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-04-05 8:52 ` [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Add Support for C10 chips Andi Shyti
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