From: Song Gao <gaosong@loongson.cn>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org
Subject: [RFC PATCH v2 17/44] target/loongarch: Implement vdiv/vmod
Date: Tue, 28 Mar 2023 11:06:04 +0800 [thread overview]
Message-ID: <20230328030631.3117129-18-gaosong@loongson.cn> (raw)
In-Reply-To: <20230328030631.3117129-1-gaosong@loongson.cn>
This patch includes:
- VDIV.{B/H/W/D}[U];
- VMOD.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/disas.c | 17 +++++++++
target/loongarch/helper.h | 17 +++++++++
target/loongarch/insn_trans/trans_lsx.c.inc | 17 +++++++++
target/loongarch/insns.decode | 17 +++++++++
target/loongarch/lsx_helper.c | 38 +++++++++++++++++++++
5 files changed, 106 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 980e6e6375..6e4f676a42 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1044,3 +1044,20 @@ INSN_LSX(vmaddwod_h_bu_b, vvv)
INSN_LSX(vmaddwod_w_hu_h, vvv)
INSN_LSX(vmaddwod_d_wu_w, vvv)
INSN_LSX(vmaddwod_q_du_d, vvv)
+
+INSN_LSX(vdiv_b, vvv)
+INSN_LSX(vdiv_h, vvv)
+INSN_LSX(vdiv_w, vvv)
+INSN_LSX(vdiv_d, vvv)
+INSN_LSX(vdiv_bu, vvv)
+INSN_LSX(vdiv_hu, vvv)
+INSN_LSX(vdiv_wu, vvv)
+INSN_LSX(vdiv_du, vvv)
+INSN_LSX(vmod_b, vvv)
+INSN_LSX(vmod_h, vvv)
+INSN_LSX(vmod_w, vvv)
+INSN_LSX(vmod_d, vvv)
+INSN_LSX(vmod_bu, vvv)
+INSN_LSX(vmod_hu, vvv)
+INSN_LSX(vmod_wu, vvv)
+INSN_LSX(vmod_du, vvv)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 6bb273fefe..e46f12cb65 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -318,3 +318,20 @@ DEF_HELPER_FLAGS_4(vmaddwod_h_bu_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmaddwod_w_hu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmaddwod_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmaddwod_q_du_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_4(vdiv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vdiv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(vdiv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(vdiv_d, void, env, i32, i32, i32)
+DEF_HELPER_4(vdiv_bu, void, env, i32, i32, i32)
+DEF_HELPER_4(vdiv_hu, void, env, i32, i32, i32)
+DEF_HELPER_4(vdiv_wu, void, env, i32, i32, i32)
+DEF_HELPER_4(vdiv_du, void, env, i32, i32, i32)
+DEF_HELPER_4(vmod_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vmod_h, void, env, i32, i32, i32)
+DEF_HELPER_4(vmod_w, void, env, i32, i32, i32)
+DEF_HELPER_4(vmod_d, void, env, i32, i32, i32)
+DEF_HELPER_4(vmod_bu, void, env, i32, i32, i32)
+DEF_HELPER_4(vmod_hu, void, env, i32, i32, i32)
+DEF_HELPER_4(vmod_wu, void, env, i32, i32, i32)
+DEF_HELPER_4(vmod_du, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc
index 29c7aca8f9..46a18da6dd 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -2365,3 +2365,20 @@ TRANS(vmaddwod_h_bu_b, gvec_vvv, MO_8, do_vmaddwod_u_s)
TRANS(vmaddwod_w_hu_h, gvec_vvv, MO_16, do_vmaddwod_u_s)
TRANS(vmaddwod_d_wu_w, gvec_vvv, MO_32, do_vmaddwod_u_s)
TRANS(vmaddwod_q_du_d, gvec_vvv, MO_64, do_vmaddwod_u_s)
+
+TRANS(vdiv_b, gen_vvv, gen_helper_vdiv_b)
+TRANS(vdiv_h, gen_vvv, gen_helper_vdiv_h)
+TRANS(vdiv_w, gen_vvv, gen_helper_vdiv_w)
+TRANS(vdiv_d, gen_vvv, gen_helper_vdiv_d)
+TRANS(vdiv_bu, gen_vvv, gen_helper_vdiv_bu)
+TRANS(vdiv_hu, gen_vvv, gen_helper_vdiv_hu)
+TRANS(vdiv_wu, gen_vvv, gen_helper_vdiv_wu)
+TRANS(vdiv_du, gen_vvv, gen_helper_vdiv_du)
+TRANS(vmod_b, gen_vvv, gen_helper_vmod_b)
+TRANS(vmod_h, gen_vvv, gen_helper_vmod_h)
+TRANS(vmod_w, gen_vvv, gen_helper_vmod_w)
+TRANS(vmod_d, gen_vvv, gen_helper_vmod_d)
+TRANS(vmod_bu, gen_vvv, gen_helper_vmod_bu)
+TRANS(vmod_hu, gen_vvv, gen_helper_vmod_hu)
+TRANS(vmod_wu, gen_vvv, gen_helper_vmod_wu)
+TRANS(vmod_du, gen_vvv, gen_helper_vmod_du)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index df23d4ee1e..67d016edb7 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -740,3 +740,20 @@ vmaddwod_h_bu_b 0111 00001011 11100 ..... ..... ..... @vvv
vmaddwod_w_hu_h 0111 00001011 11101 ..... ..... ..... @vvv
vmaddwod_d_wu_w 0111 00001011 11110 ..... ..... ..... @vvv
vmaddwod_q_du_d 0111 00001011 11111 ..... ..... ..... @vvv
+
+vdiv_b 0111 00001110 00000 ..... ..... ..... @vvv
+vdiv_h 0111 00001110 00001 ..... ..... ..... @vvv
+vdiv_w 0111 00001110 00010 ..... ..... ..... @vvv
+vdiv_d 0111 00001110 00011 ..... ..... ..... @vvv
+vdiv_bu 0111 00001110 01000 ..... ..... ..... @vvv
+vdiv_hu 0111 00001110 01001 ..... ..... ..... @vvv
+vdiv_wu 0111 00001110 01010 ..... ..... ..... @vvv
+vdiv_du 0111 00001110 01011 ..... ..... ..... @vvv
+vmod_b 0111 00001110 00100 ..... ..... ..... @vvv
+vmod_h 0111 00001110 00101 ..... ..... ..... @vvv
+vmod_w 0111 00001110 00110 ..... ..... ..... @vvv
+vmod_d 0111 00001110 00111 ..... ..... ..... @vvv
+vmod_bu 0111 00001110 01100 ..... ..... ..... @vvv
+vmod_hu 0111 00001110 01101 ..... ..... ..... @vvv
+vmod_wu 0111 00001110 01110 ..... ..... ..... @vvv
+vmod_du 0111 00001110 01111 ..... ..... ..... @vvv
diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c
index 9ae56e9fcb..03a837fa74 100644
--- a/target/loongarch/lsx_helper.c
+++ b/target/loongarch/lsx_helper.c
@@ -725,3 +725,41 @@ VMADDWOD_U_S(vmaddwod_h_bu_b, 16, uint16_t, uint8_t, int16_t, H, B, DO_MUL)
VMADDWOD_U_S(vmaddwod_w_hu_h, 32, uint32_t, uint16_t, int32_t, W, H, DO_MUL)
VMADDWOD_U_S(vmaddwod_d_wu_w, 64, uint64_t, uint32_t, int64_t, D, W, DO_MUL)
VMADD_Q(vmaddwod_q_du_d, int128_make64, int128_makes64, 1)
+
+#define DO_DIVU(N, M) (unlikely(M == 0) ? 0 : N / M)
+#define DO_REMU(N, M) (unlikely(M == 0) ? 0 : N % M)
+#define DO_DIV(N, M) (unlikely(M == 0) ? 0 :\
+ unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
+#define DO_REM(N, M) (unlikely(M == 0) ? 0 :\
+ unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
+
+#define DO_3OP(NAME, BIT, T, E, DO_OP) \
+void HELPER(NAME)(CPULoongArchState *env, \
+ uint32_t vd, uint32_t vj, uint32_t vk) \
+{ \
+ int i; \
+ VReg *Vd = &(env->fpr[vd].vreg); \
+ VReg *Vj = &(env->fpr[vj].vreg); \
+ VReg *Vk = &(env->fpr[vk].vreg); \
+ \
+ for (i = 0; i < LSX_LEN/BIT; i++) { \
+ Vd->E(i) = DO_OP((T)Vj->E(i), (T)Vk->E(i)); \
+ } \
+}
+
+DO_3OP(vdiv_b, 8, int8_t, B, DO_DIV)
+DO_3OP(vdiv_h, 16, int16_t, H, DO_DIV)
+DO_3OP(vdiv_w, 32, int32_t, W, DO_DIV)
+DO_3OP(vdiv_d, 64, int64_t, D, DO_DIV)
+DO_3OP(vdiv_bu, 8, uint8_t, B, DO_DIVU)
+DO_3OP(vdiv_hu, 16, uint16_t, H, DO_DIVU)
+DO_3OP(vdiv_wu, 32, uint32_t, W, DO_DIVU)
+DO_3OP(vdiv_du, 64, uint64_t, D, DO_DIVU)
+DO_3OP(vmod_b, 8, int8_t, B, DO_REM)
+DO_3OP(vmod_h, 16, int16_t, H, DO_REM)
+DO_3OP(vmod_w, 32, int32_t, W, DO_REM)
+DO_3OP(vmod_d, 64, int64_t, D, DO_REM)
+DO_3OP(vmod_bu, 8, uint8_t, B, DO_REMU)
+DO_3OP(vmod_hu, 16, uint16_t, H, DO_REMU)
+DO_3OP(vmod_wu, 32, uint32_t, W, DO_REMU)
+DO_3OP(vmod_du, 64, uint64_t, D, DO_REMU)
--
2.31.1
next prev parent reply other threads:[~2023-03-28 3:07 UTC|newest]
Thread overview: 114+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-28 3:05 [RFC PATCH v2 00/44] Add LoongArch LSX instructions Song Gao
2023-03-28 3:05 ` [RFC PATCH v2 01/44] target/loongarch: Add LSX data type VReg Song Gao
2023-03-28 19:56 ` Richard Henderson
2023-03-29 2:28 ` gaosong
2023-03-28 3:05 ` [RFC PATCH v2 02/44] target/loongarch: CPUCFG support LSX Song Gao
2023-03-28 19:33 ` Richard Henderson
2023-03-28 3:05 ` [RFC PATCH v2 03/44] target/loongarch: meson.build support build LSX Song Gao
2023-03-28 19:35 ` Richard Henderson
2023-03-28 3:05 ` [RFC PATCH v2 04/44] target/loongarch: Add CHECK_SXE maccro for check LSX enable Song Gao
2023-03-28 19:42 ` Richard Henderson
2023-03-29 2:28 ` gaosong
2023-03-28 3:05 ` [RFC PATCH v2 05/44] target/loongarch: Implement vadd/vsub Song Gao
2023-03-28 19:50 ` Richard Henderson
2023-03-28 19:59 ` Richard Henderson
2023-03-29 9:59 ` gaosong
2023-03-29 15:22 ` Richard Henderson
2023-03-28 3:05 ` [RFC PATCH v2 06/44] target/loongarch: Implement vaddi/vsubi Song Gao
2023-03-28 19:58 ` Richard Henderson
2023-03-28 3:05 ` [RFC PATCH v2 07/44] target/loongarch: Implement vneg Song Gao
2023-03-28 20:02 ` Richard Henderson
2023-03-28 3:05 ` [RFC PATCH v2 08/44] target/loongarch: Implement vsadd/vssub Song Gao
2023-03-28 20:03 ` Richard Henderson
2023-03-28 3:05 ` [RFC PATCH v2 09/44] target/loongarch: Implement vhaddw/vhsubw Song Gao
2023-03-28 20:17 ` Richard Henderson
2023-03-29 3:24 ` gaosong
2023-03-29 15:25 ` Richard Henderson
2023-03-28 3:05 ` [RFC PATCH v2 10/44] target/loongarch: Implement vaddw/vsubw Song Gao
2023-03-28 20:28 ` Richard Henderson
2023-03-28 3:05 ` [RFC PATCH v2 11/44] target/loongarch: Implement vavg/vavgr Song Gao
2023-03-28 20:31 ` Richard Henderson
2023-03-28 3:05 ` [RFC PATCH v2 12/44] target/loongarch: Implement vabsd Song Gao
2023-03-28 20:32 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 13/44] target/loongarch: Implement vadda Song Gao
2023-03-28 20:33 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 14/44] target/loongarch: Implement vmax/vmin Song Gao
2023-03-28 20:39 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 15/44] target/loongarch: Implement vmul/vmuh/vmulw{ev/od} Song Gao
2023-03-28 20:46 ` Richard Henderson
2023-04-06 12:09 ` gaosong
2023-04-06 16:52 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 16/44] target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od} Song Gao
2023-03-28 20:50 ` Richard Henderson
2023-03-28 3:06 ` Song Gao [this message]
2023-03-28 20:52 ` [RFC PATCH v2 17/44] target/loongarch: Implement vdiv/vmod Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 18/44] target/loongarch: Implement vsat Song Gao
2023-04-01 5:03 ` Richard Henderson
2023-04-03 12:55 ` gaosong
2023-04-03 20:13 ` Richard Henderson
2023-04-04 2:11 ` gaosong
2023-04-04 3:46 ` Richard Henderson
2023-04-19 9:31 ` Song Gao
2023-04-19 11:06 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 19/44] target/loongarch: Implement vexth Song Gao
2023-04-01 5:07 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 20/44] target/loongarch: Implement vsigncov Song Gao
2023-04-01 5:11 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 21/44] target/loongarch: Implement vmskltz/vmskgez/vmsknz Song Gao
2023-04-01 5:20 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 22/44] target/loongarch: Implement LSX logic instructions Song Gao
2023-04-01 5:31 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 23/44] target/loongarch: Implement vsll vsrl vsra vrotr Song Gao
2023-04-01 5:38 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 24/44] target/loongarch: Implement vsllwil vextl Song Gao
2023-04-01 5:40 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 25/44] target/loongarch: Implement vsrlr vsrar Song Gao
2023-04-01 5:42 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 26/44] target/loongarch: Implement vsrln vsran Song Gao
2023-04-01 5:46 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 27/44] target/loongarch: Implement vsrlrn vsrarn Song Gao
2023-04-01 5:53 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 28/44] target/loongarch: Implement vssrln vssran Song Gao
2023-04-02 3:26 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 29/44] target/loongarch: Implement vssrlrn vssrarn Song Gao
2023-04-02 3:31 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 30/44] target/loongarch: Implement vclo vclz Song Gao
2023-04-02 3:34 ` Richard Henderson
2023-04-07 7:40 ` gaosong
2023-04-07 16:46 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 31/44] target/loongarch: Implement vpcnt Song Gao
2023-04-02 3:35 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 32/44] target/loongarch: Implement vbitclr vbitset vbitrev Song Gao
2023-04-02 5:14 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 33/44] target/loongarch: Implement vfrstp Song Gao
2023-04-02 5:17 ` Richard Henderson
2023-04-03 2:27 ` gaosong
2023-03-28 3:06 ` [RFC PATCH v2 34/44] target/loongarch: Implement LSX fpu arith instructions Song Gao
2023-04-02 5:19 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 35/44] target/loongarch: Implement LSX fpu fcvt instructions Song Gao
2023-04-02 5:22 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 36/44] target/loongarch: Implement vseq vsle vslt Song Gao
2023-04-02 5:27 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 37/44] target/loongarch: Implement vfcmp Song Gao
2023-04-04 0:47 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 38/44] target/loongarch: Implement vbitsel vset Song Gao
2023-04-04 1:03 ` Richard Henderson
2023-04-11 11:37 ` gaosong
2023-04-12 6:53 ` Richard Henderson
2023-04-13 2:53 ` gaosong
2023-04-13 10:06 ` Richard Henderson
2023-04-14 3:22 ` gaosong
2023-04-14 3:47 ` gaosong
2023-03-28 3:06 ` [RFC PATCH v2 39/44] target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vr Song Gao
2023-04-04 1:09 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 40/44] target/loongarch: Implement vreplve vpack vpick Song Gao
2023-04-04 1:17 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 41/44] target/loongarch: Implement vilvl vilvh vextrins vshuf Song Gao
2023-04-04 1:31 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 42/44] target/loongarch: Implement vld vst Song Gao
2023-04-04 3:35 ` Richard Henderson
2023-03-28 3:06 ` [RFC PATCH v2 43/44] target/loongarch: Implement vldi Song Gao
2023-04-04 3:39 ` Richard Henderson
2023-04-18 9:03 ` Song Gao
2023-03-28 3:06 ` [RFC PATCH v2 44/44] target/loongarch: Use {set/get}_gpr replace to cpu_fpr Song Gao
2023-04-04 3:44 ` Richard Henderson
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