[PATCH v3 0/4] ARM: dts: at91: Set sst26vf064b SPI NOR flash at its maxumum frequency

[PATCH v3 0/4] ARM: dts: at91: Set sst26vf064b SPI NOR flash at its maxumum frequency

[Tudor Ambarus]

Changes in v3: Update S-o-b tag to match author's email.
Changes in v2: update value of spi-cs-setup-ns as it was changed to u32
since the first proposal.
v1 at: https://lore.kernel.org/linux-mtd/20221117105249.115649-1-tudor.ambarus@microchip.com/

---
SPI NOR flashes have specific cs-setup time requirements without which
they can't work at frequencies close to their maximum supported frequency,
as they miss the first bits of the instruction command. Unrecognized
commands are ignored, thus the flash will be unresponsive. Introduce the
spi-cs-setup-ns property to allow spi devices to specify their cs setup
time.


Tudor Ambarus (4):
  ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its
    maximum frequency
  ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its
    maximum frequency
  ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its
    maximum frequency
  ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its
    maximum frequency

 arch/arm/boot/dts/at91-sam9x60ek.dts        | 3 ++-
 arch/arm/boot/dts/at91-sama5d27_som1.dtsi   | 3 ++-
 arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++-
 arch/arm/boot/dts/at91-sama5d2_icp.dts      | 3 ++-
 4 files changed, 8 insertions(+), 4 deletions(-)

-- 
2.40.0.348.gf938b09366-goog

[PATCH v3 0/4] ARM: dts: at91: Set sst26vf064b SPI NOR flash at its maxumum frequency

[Tudor Ambarus]

Changes in v3: Update S-o-b tag to match author's email.
Changes in v2: update value of spi-cs-setup-ns as it was changed to u32
since the first proposal.
v1 at: https://lore.kernel.org/linux-mtd/20221117105249.115649-1-tudor.ambarus@microchip.com/

---
SPI NOR flashes have specific cs-setup time requirements without which
they can't work at frequencies close to their maximum supported frequency,
as they miss the first bits of the instruction command. Unrecognized
commands are ignored, thus the flash will be unresponsive. Introduce the
spi-cs-setup-ns property to allow spi devices to specify their cs setup
time.


Tudor Ambarus (4):
  ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its
    maximum frequency
  ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its
    maximum frequency
  ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its
    maximum frequency
  ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its
    maximum frequency

 arch/arm/boot/dts/at91-sam9x60ek.dts        | 3 ++-
 arch/arm/boot/dts/at91-sama5d27_som1.dtsi   | 3 ++-
 arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++-
 arch/arm/boot/dts/at91-sama5d2_icp.dts      | 3 ++-
 4 files changed, 8 insertions(+), 4 deletions(-)

-- 
2.40.0.348.gf938b09366-goog


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[PATCH v3 1/4] ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency

[Tudor Ambarus]

From: Tudor Ambarus <tudor.ambarus@microchip.com>

sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum
operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
at 3.3V, increase its maximum supported frequency to 104MHz. The
increasing of the spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.

The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.

With the increase of frequency the reads are now faster with ~37%.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
index 83bcf9fe0152..4617805c7748 100644
--- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
@@ -220,7 +220,8 @@ qspi1_flash: flash@0 {
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
 		reg = <0>;
-		spi-max-frequency = <80000000>;
+		spi-max-frequency = <104000000>;
+		spi-cs-setup-ns = <7>;
 		spi-rx-bus-width = <4>;
 		spi-tx-bus-width = <4>;
 		m25p,fast-read;
-- 
2.40.0.348.gf938b09366-goog

[PATCH v3 1/4] ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency

[Tudor Ambarus]

From: Tudor Ambarus <tudor.ambarus@microchip.com>

sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum
operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
at 3.3V, increase its maximum supported frequency to 104MHz. The
increasing of the spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.

The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.

With the increase of frequency the reads are now faster with ~37%.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
index 83bcf9fe0152..4617805c7748 100644
--- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
@@ -220,7 +220,8 @@ qspi1_flash: flash@0 {
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
 		reg = <0>;
-		spi-max-frequency = <80000000>;
+		spi-max-frequency = <104000000>;
+		spi-cs-setup-ns = <7>;
 		spi-rx-bus-width = <4>;
 		spi-tx-bus-width = <4>;
 		m25p,fast-read;
-- 
2.40.0.348.gf938b09366-goog


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v3 2/4] ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency

[Tudor Ambarus]

From: Tudor Ambarus <tudor.ambarus@microchip.com>

sama5d27-som1 populates an sst26vf064b SPI NOR flash. Its maximum
operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
at 3.3V, increase its maximum supported frequency to 104MHz. The
increasing of the spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.

The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.

With the increase of frequency the reads are now faster with ~37%.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
index 8aa9e8dea337..95ecb7d040a8 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
@@ -43,7 +43,8 @@ flash@0 {
 					#size-cells = <1>;
 					compatible = "jedec,spi-nor";
 					reg = <0>;
-					spi-max-frequency = <80000000>;
+					spi-max-frequency = <104000000>;
+					spi-cs-setup-ns = <7>;
 					spi-tx-bus-width = <4>;
 					spi-rx-bus-width = <4>;
 					m25p,fast-read;
-- 
2.40.0.348.gf938b09366-goog

[PATCH v3 2/4] ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its maximum frequency

[Tudor Ambarus]

From: Tudor Ambarus <tudor.ambarus@microchip.com>

sama5d27-som1 populates an sst26vf064b SPI NOR flash. Its maximum
operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
at 3.3V, increase its maximum supported frequency to 104MHz. The
increasing of the spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.

The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.

With the increase of frequency the reads are now faster with ~37%.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
index 8aa9e8dea337..95ecb7d040a8 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi
@@ -43,7 +43,8 @@ flash@0 {
 					#size-cells = <1>;
 					compatible = "jedec,spi-nor";
 					reg = <0>;
-					spi-max-frequency = <80000000>;
+					spi-max-frequency = <104000000>;
+					spi-cs-setup-ns = <7>;
 					spi-tx-bus-width = <4>;
 					spi-rx-bus-width = <4>;
 					m25p,fast-read;
-- 
2.40.0.348.gf938b09366-goog


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v3 3/4] ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency

[Tudor Ambarus]

From: Tudor Ambarus <tudor.ambarus@microchip.com>

sama5d2_icp populates an sst26vf064b SPI NOR flash. Its maximum operating
frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V,
increase its maximum supported frequency to 104MHz. The increasing of the
spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.

The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.

With the increase of frequency the reads are now faster with ~37%.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 arch/arm/boot/dts/at91-sama5d2_icp.dts | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts
index 1346b8f2b259..999adeca6f33 100644
--- a/arch/arm/boot/dts/at91-sama5d2_icp.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts
@@ -669,7 +669,8 @@ flash@0 {
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
 		reg = <0>;
-		spi-max-frequency = <80000000>;
+		spi-max-frequency = <104000000>;
+		spi-cs-setup-ns = <7>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		m25p,fast-read;
-- 
2.40.0.348.gf938b09366-goog

[PATCH v3 3/4] ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency

[Tudor Ambarus]

From: Tudor Ambarus <tudor.ambarus@microchip.com>

sama5d2_icp populates an sst26vf064b SPI NOR flash. Its maximum operating
frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V,
increase its maximum supported frequency to 104MHz. The increasing of the
spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.

The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.

With the increase of frequency the reads are now faster with ~37%.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 arch/arm/boot/dts/at91-sama5d2_icp.dts | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts
index 1346b8f2b259..999adeca6f33 100644
--- a/arch/arm/boot/dts/at91-sama5d2_icp.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts
@@ -669,7 +669,8 @@ flash@0 {
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
 		reg = <0>;
-		spi-max-frequency = <80000000>;
+		spi-max-frequency = <104000000>;
+		spi-cs-setup-ns = <7>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		m25p,fast-read;
-- 
2.40.0.348.gf938b09366-goog


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linux-arm-kernel@lists.infradead.org
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[PATCH v3 4/4] ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency

[Tudor Ambarus]

From: Tudor Ambarus <tudor.ambarus@microchip.com>

sam9x60ek populates an sst26vf064b SPI NOR flash. Its maximum operating
frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V,
increase its maximum supported frequency to 104MHz. The increasing of the
spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.

The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.

With the increase of frequency the reads are now faster with ~33%.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 arch/arm/boot/dts/at91-sam9x60ek.dts | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
index 180e4b1aa2f6..5cd593028aff 100644
--- a/arch/arm/boot/dts/at91-sam9x60ek.dts
+++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
@@ -578,7 +578,8 @@ flash@0 {
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
 		reg = <0>;
-		spi-max-frequency = <80000000>;
+		spi-max-frequency = <104000000>;
+		spi-cs-setup-ns = <7>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		m25p,fast-read;
-- 
2.40.0.348.gf938b09366-goog

[PATCH v3 4/4] ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its maximum frequency

[Tudor Ambarus]

From: Tudor Ambarus <tudor.ambarus@microchip.com>

sam9x60ek populates an sst26vf064b SPI NOR flash. Its maximum operating
frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V,
increase its maximum supported frequency to 104MHz. The increasing of the
spi-max-frequency value requires the setting of the
"CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.

The sst26vf064b datasheet specifies just a minimum value for the
"CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
maximum time specified. I determined experimentally that 5 ns for the
spi-cs-setup-ns is not enough when the flash is operated close to its
maximum frequency and tests showed that 7 ns is just fine, so set the
spi-cs-setup-ns dt property to 7.

With the increase of frequency the reads are now faster with ~33%.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
 arch/arm/boot/dts/at91-sam9x60ek.dts | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
index 180e4b1aa2f6..5cd593028aff 100644
--- a/arch/arm/boot/dts/at91-sam9x60ek.dts
+++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
@@ -578,7 +578,8 @@ flash@0 {
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
 		reg = <0>;
-		spi-max-frequency = <80000000>;
+		spi-max-frequency = <104000000>;
+		spi-cs-setup-ns = <7>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 		m25p,fast-read;
-- 
2.40.0.348.gf938b09366-goog


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Re: [PATCH v3 1/4] ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency

[Tudor Ambarus]

On 3/28/23 11:15, Tudor Ambarus wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
> 

cut

> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>

I don't understand why these differ. On my local machine I see them match:

commit e208a7b04cbde950588c561889d2f8eb8a10485f
Author: Tudor Ambarus <tudor.ambarus@linaro.org>
Date:   Thu Nov 17 12:52:46 2022 +0200

    ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its
maximum frequency

    sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum
    operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
    at 3.3V, increase its maximum supported frequency to 104MHz. The
    increasing of the spi-max-frequency value requires the setting of the
    "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value
of 7.

    The sst26vf064b datasheet specifies just a minimum value for the
    "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
    maximum time specified. I determined experimentally that 5 ns for the
    spi-cs-setup-ns is not enough when the flash is operated close to its
    maximum frequency and tests showed that 7 ns is just fine, so set the
    spi-cs-setup-ns dt property to 7.

    With the increase of frequency the reads are now faster with ~37%.

    Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>

Anyway, you can keep v2 then, looks like v2 has the same email on both
the author line and the S-o-b line. It's fine by me even if it is with
@microchip.com:
https://lore.kernel.org/all/20230328100723.1593864-2-tudor.ambarus@linaro.org/

Re: [PATCH v3 1/4] ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency

[Tudor Ambarus]

On 3/28/23 11:15, Tudor Ambarus wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
> 

cut

> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>

I don't understand why these differ. On my local machine I see them match:

commit e208a7b04cbde950588c561889d2f8eb8a10485f
Author: Tudor Ambarus <tudor.ambarus@linaro.org>
Date:   Thu Nov 17 12:52:46 2022 +0200

    ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its
maximum frequency

    sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum
    operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated
    at 3.3V, increase its maximum supported frequency to 104MHz. The
    increasing of the spi-max-frequency value requires the setting of the
    "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value
of 7.

    The sst26vf064b datasheet specifies just a minimum value for the
    "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
    maximum time specified. I determined experimentally that 5 ns for the
    spi-cs-setup-ns is not enough when the flash is operated close to its
    maximum frequency and tests showed that 7 ns is just fine, so set the
    spi-cs-setup-ns dt property to 7.

    With the increase of frequency the reads are now faster with ~37%.

    Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>

Anyway, you can keep v2 then, looks like v2 has the same email on both
the author line and the S-o-b line. It's fine by me even if it is with
@microchip.com:
https://lore.kernel.org/all/20230328100723.1593864-2-tudor.ambarus@linaro.org/

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Re: [PATCH v3 3/4] ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency

[Nicolas Ferre]

On 28/03/2023 at 12:15, Tudor Ambarus wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
> 
> sama5d2_icp populates an sst26vf064b SPI NOR flash. Its maximum operating
> frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V,
> increase its maximum supported frequency to 104MHz. The increasing of the
> spi-max-frequency value requires the setting of the
> "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
> 
> The sst26vf064b datasheet specifies just a minimum value for the
> "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
> maximum time specified. I determined experimentally that 5 ns for the
> spi-cs-setup-ns is not enough when the flash is operated close to its
> maximum frequency and tests showed that 7 ns is just fine, so set the
> spi-cs-setup-ns dt property to 7.
> 
> With the increase of frequency the reads are now faster with ~37%.
> 
> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>

Tested-by: Nicolas Ferre <nicolas.ferre@microchip.com> # on sama5d2 ICP 
board with a linux-next kernel today.

Thanks Tudor!

Best regards,
   Nicolas

> ---
>   arch/arm/boot/dts/at91-sama5d2_icp.dts | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts
> index 1346b8f2b259..999adeca6f33 100644
> --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts
> +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts
> @@ -669,7 +669,8 @@ flash@0 {
>                  #size-cells = <1>;
>                  compatible = "jedec,spi-nor";
>                  reg = <0>;
> -               spi-max-frequency = <80000000>;
> +               spi-max-frequency = <104000000>;
> +               spi-cs-setup-ns = <7>;
>                  spi-tx-bus-width = <4>;
>                  spi-rx-bus-width = <4>;
>                  m25p,fast-read;
> --
> 2.40.0.348.gf938b09366-goog
> 

-- 
Nicolas Ferre

Re: [PATCH v3 3/4] ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its maximum frequency

[Nicolas Ferre]

On 28/03/2023 at 12:15, Tudor Ambarus wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
> 
> sama5d2_icp populates an sst26vf064b SPI NOR flash. Its maximum operating
> frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V,
> increase its maximum supported frequency to 104MHz. The increasing of the
> spi-max-frequency value requires the setting of the
> "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7.
> 
> The sst26vf064b datasheet specifies just a minimum value for the
> "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no
> maximum time specified. I determined experimentally that 5 ns for the
> spi-cs-setup-ns is not enough when the flash is operated close to its
> maximum frequency and tests showed that 7 ns is just fine, so set the
> spi-cs-setup-ns dt property to 7.
> 
> With the increase of frequency the reads are now faster with ~37%.
> 
> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>

Tested-by: Nicolas Ferre <nicolas.ferre@microchip.com> # on sama5d2 ICP 
board with a linux-next kernel today.

Thanks Tudor!

Best regards,
   Nicolas

> ---
>   arch/arm/boot/dts/at91-sama5d2_icp.dts | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts
> index 1346b8f2b259..999adeca6f33 100644
> --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts
> +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts
> @@ -669,7 +669,8 @@ flash@0 {
>                  #size-cells = <1>;
>                  compatible = "jedec,spi-nor";
>                  reg = <0>;
> -               spi-max-frequency = <80000000>;
> +               spi-max-frequency = <104000000>;
> +               spi-cs-setup-ns = <7>;
>                  spi-tx-bus-width = <4>;
>                  spi-rx-bus-width = <4>;
>                  m25p,fast-read;
> --
> 2.40.0.348.gf938b09366-goog
> 

-- 
Nicolas Ferre


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Re: [PATCH v3 0/4] ARM: dts: at91: Set sst26vf064b SPI NOR flash at its maxumum frequency

[Nicolas Ferre]

On 28/03/2023 at 12:15, Tudor Ambarus wrote:
> Changes in v3: Update S-o-b tag to match author's email.
> Changes in v2: update value of spi-cs-setup-ns as it was changed to u32
> since the first proposal.
> v1 at: https://lore.kernel.org/linux-mtd/20221117105249.115649-1-tudor.ambarus@microchip.com/
> 
> ---
> SPI NOR flashes have specific cs-setup time requirements without which
> they can't work at frequencies close to their maximum supported frequency,
> as they miss the first bits of the instruction command. Unrecognized
> commands are ignored, thus the flash will be unresponsive. Introduce the
> spi-cs-setup-ns property to allow spi devices to specify their cs setup
> time.

Now that it's tested:
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
to the whole series and I'll queue them on at91-dt branch and changed 
your email address when doing so.

Thanks for your patches Tudor, it's appreciated! Best regards,
   Nicolas

> Tudor Ambarus (4):
>    ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its
>      maximum frequency
>    ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its
>      maximum frequency
>    ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its
>      maximum frequency
>    ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its
>      maximum frequency
> 
>   arch/arm/boot/dts/at91-sam9x60ek.dts        | 3 ++-
>   arch/arm/boot/dts/at91-sama5d27_som1.dtsi   | 3 ++-
>   arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++-
>   arch/arm/boot/dts/at91-sama5d2_icp.dts      | 3 ++-
>   4 files changed, 8 insertions(+), 4 deletions(-)
> 
> --
> 2.40.0.348.gf938b09366-goog
> 

-- 
Nicolas Ferre

Re: [PATCH v3 0/4] ARM: dts: at91: Set sst26vf064b SPI NOR flash at its maxumum frequency

[Nicolas Ferre]

On 28/03/2023 at 12:15, Tudor Ambarus wrote:
> Changes in v3: Update S-o-b tag to match author's email.
> Changes in v2: update value of spi-cs-setup-ns as it was changed to u32
> since the first proposal.
> v1 at: https://lore.kernel.org/linux-mtd/20221117105249.115649-1-tudor.ambarus@microchip.com/
> 
> ---
> SPI NOR flashes have specific cs-setup time requirements without which
> they can't work at frequencies close to their maximum supported frequency,
> as they miss the first bits of the instruction command. Unrecognized
> commands are ignored, thus the flash will be unresponsive. Introduce the
> spi-cs-setup-ns property to allow spi devices to specify their cs setup
> time.

Now that it's tested:
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
to the whole series and I'll queue them on at91-dt branch and changed 
your email address when doing so.

Thanks for your patches Tudor, it's appreciated! Best regards,
   Nicolas

> Tudor Ambarus (4):
>    ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its
>      maximum frequency
>    ARM: dts: at91-sama5d27_som1: Set sst26vf064b SPI NOR flash at its
>      maximum frequency
>    ARM: dts: at91: sama5d2_icp: Set sst26vf064b SPI NOR flash at its
>      maximum frequency
>    ARM: dts: at91: sam9x60ek: Set sst26vf064b SPI NOR flash at its
>      maximum frequency
> 
>   arch/arm/boot/dts/at91-sam9x60ek.dts        | 3 ++-
>   arch/arm/boot/dts/at91-sama5d27_som1.dtsi   | 3 ++-
>   arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++-
>   arch/arm/boot/dts/at91-sama5d2_icp.dts      | 3 ++-
>   4 files changed, 8 insertions(+), 4 deletions(-)
> 
> --
> 2.40.0.348.gf938b09366-goog
> 

-- 
Nicolas Ferre


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v3 0/4] ARM: dts: at91: Set sst26vf064b SPI NOR flash at its maxumum frequency

[Tudor Ambarus]

On 3/30/23 19:53, Nicolas Ferre wrote:
> On 28/03/2023 at 12:15, Tudor Ambarus wrote:
>> Changes in v3: Update S-o-b tag to match author's email.
>> Changes in v2: update value of spi-cs-setup-ns as it was changed to u32
>> since the first proposal.
>> v1 at:
>> https://lore.kernel.org/linux-mtd/20221117105249.115649-1-tudor.ambarus@microchip.com/
>>
>> ---
>> SPI NOR flashes have specific cs-setup time requirements without which
>> they can't work at frequencies close to their maximum supported
>> frequency,
>> as they miss the first bits of the instruction command. Unrecognized
>> commands are ignored, thus the flash will be unresponsive. Introduce the
>> spi-cs-setup-ns property to allow spi devices to specify their cs setup
>> time.
> 
> Now that it's tested:
> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> to the whole series and I'll queue them on at91-dt branch and changed
> your email address when doing so.
> 
> Thanks for your patches Tudor, it's appreciated! Best regards,

My pleasure, I'm happy I could help. Cheers,
ta

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
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Re: [PATCH v3 0/4] ARM: dts: at91: Set sst26vf064b SPI NOR flash at its maxumum frequency

[Tudor Ambarus]

On 3/30/23 19:53, Nicolas Ferre wrote:
> On 28/03/2023 at 12:15, Tudor Ambarus wrote:
>> Changes in v3: Update S-o-b tag to match author's email.
>> Changes in v2: update value of spi-cs-setup-ns as it was changed to u32
>> since the first proposal.
>> v1 at:
>> https://lore.kernel.org/linux-mtd/20221117105249.115649-1-tudor.ambarus@microchip.com/
>>
>> ---
>> SPI NOR flashes have specific cs-setup time requirements without which
>> they can't work at frequencies close to their maximum supported
>> frequency,
>> as they miss the first bits of the instruction command. Unrecognized
>> commands are ignored, thus the flash will be unresponsive. Introduce the
>> spi-cs-setup-ns property to allow spi devices to specify their cs setup
>> time.
> 
> Now that it's tested:
> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> to the whole series and I'll queue them on at91-dt branch and changed
> your email address when doing so.
> 
> Thanks for your patches Tudor, it's appreciated! Best regards,

My pleasure, I'm happy I could help. Cheers,
ta