From: Reiji Watanabe <reijiw@google.com> To: Marc Zyngier <maz@kernel.org>, Oliver Upton <oliver.upton@linux.dev>, kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse <james.morse@arm.com>, Alexandru Elisei <alexandru.elisei@arm.com>, Zenghui Yu <yuzenghui@huawei.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Paolo Bonzini <pbonzini@redhat.com>, Ricardo Koller <ricarkol@google.com>, Jing Zhang <jingzhangos@google.com>, Raghavendra Rao Anata <rananta@google.com>, Will Deacon <will@kernel.org>, Reiji Watanabe <reijiw@google.com> Subject: [PATCH v1 0/2] KVM: arm64: PMU: Correct the handling of PMUSERENR_EL0 Date: Tue, 28 Mar 2023 17:21:34 -0700 [thread overview] Message-ID: <20230329002136.2463442-1-reijiw@google.com> (raw) This series will fix bugs in KVM's handling of PMUSERENR_EL0. With PMU access support from EL0 [1], the perf subsystem would set CR and ER bits of PMUSERENR_EL0 as needed to allow EL0 to have a direct access to PMU counters. However, KVM appears to assume that the register value is always zero for the host EL0, and has the following two problems in handling the register. [A] The host EL0 might lose the direct access to PMU counters, as KVM always clears PMUSERENR_EL0 before returning to userspace. [B] With VHE, the guest EL0 access to PMU counters might be trapped to EL1 instead of to EL2 (even when PMUSERENR_EL0 for the guest indicates that the guest EL0 has an access to the counters). This is because, with VHE, KVM sets ER, CR, SW and EN bits of PMUSERENR_EL0 to 1 on vcpu_load() to ensure to trap PMU access from the guset EL0 to EL2, but those bits might be cleared by the perf subsystem after vcpu_load() (when PMU counters are programmed for the vPMU emulation). Patch-1 will fix [A], and Patch-2 will fix [B] respectively. The series is based on v6.3-rc4. [1] https://github.com/torvalds/linux/commit/83a7a4d643d33a8b74a42229346b7ed7139fcef9 Reiji Watanabe (2): KVM: arm64: PMU: Restore the host's PMUSERENR_EL0 KVM: arm64: PMU: Ensure to trap PMU access from EL0 to EL2 arch/arm64/include/asm/kvm_host.h | 3 +++ arch/arm64/kvm/hyp/include/hyp/switch.h | 28 +++++++++++++------------ 2 files changed, 18 insertions(+), 13 deletions(-) base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa -- 2.40.0.348.gf938b09366-goog
WARNING: multiple messages have this Message-ID (diff)
From: Reiji Watanabe <reijiw@google.com> To: Marc Zyngier <maz@kernel.org>, Oliver Upton <oliver.upton@linux.dev>, kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse <james.morse@arm.com>, Alexandru Elisei <alexandru.elisei@arm.com>, Zenghui Yu <yuzenghui@huawei.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Paolo Bonzini <pbonzini@redhat.com>, Ricardo Koller <ricarkol@google.com>, Jing Zhang <jingzhangos@google.com>, Raghavendra Rao Anata <rananta@google.com>, Will Deacon <will@kernel.org>, Reiji Watanabe <reijiw@google.com> Subject: [PATCH v1 0/2] KVM: arm64: PMU: Correct the handling of PMUSERENR_EL0 Date: Tue, 28 Mar 2023 17:21:34 -0700 [thread overview] Message-ID: <20230329002136.2463442-1-reijiw@google.com> (raw) This series will fix bugs in KVM's handling of PMUSERENR_EL0. With PMU access support from EL0 [1], the perf subsystem would set CR and ER bits of PMUSERENR_EL0 as needed to allow EL0 to have a direct access to PMU counters. However, KVM appears to assume that the register value is always zero for the host EL0, and has the following two problems in handling the register. [A] The host EL0 might lose the direct access to PMU counters, as KVM always clears PMUSERENR_EL0 before returning to userspace. [B] With VHE, the guest EL0 access to PMU counters might be trapped to EL1 instead of to EL2 (even when PMUSERENR_EL0 for the guest indicates that the guest EL0 has an access to the counters). This is because, with VHE, KVM sets ER, CR, SW and EN bits of PMUSERENR_EL0 to 1 on vcpu_load() to ensure to trap PMU access from the guset EL0 to EL2, but those bits might be cleared by the perf subsystem after vcpu_load() (when PMU counters are programmed for the vPMU emulation). Patch-1 will fix [A], and Patch-2 will fix [B] respectively. The series is based on v6.3-rc4. [1] https://github.com/torvalds/linux/commit/83a7a4d643d33a8b74a42229346b7ed7139fcef9 Reiji Watanabe (2): KVM: arm64: PMU: Restore the host's PMUSERENR_EL0 KVM: arm64: PMU: Ensure to trap PMU access from EL0 to EL2 arch/arm64/include/asm/kvm_host.h | 3 +++ arch/arm64/kvm/hyp/include/hyp/switch.h | 28 +++++++++++++------------ 2 files changed, 18 insertions(+), 13 deletions(-) base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa -- 2.40.0.348.gf938b09366-goog _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2023-03-29 0:22 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-29 0:21 Reiji Watanabe [this message] 2023-03-29 0:21 ` [PATCH v1 0/2] KVM: arm64: PMU: Correct the handling of PMUSERENR_EL0 Reiji Watanabe 2023-03-29 0:21 ` [PATCH v1 1/2] KVM: arm64: PMU: Restore the host's PMUSERENR_EL0 Reiji Watanabe 2023-03-29 0:21 ` Reiji Watanabe 2023-03-29 7:31 ` Marc Zyngier 2023-03-29 7:31 ` Marc Zyngier 2023-03-29 16:28 ` Reiji Watanabe 2023-03-29 16:28 ` Reiji Watanabe 2023-03-29 0:21 ` [PATCH v1 2/2] KVM: arm64: PMU: Ensure to trap PMU access from EL0 to EL2 Reiji Watanabe 2023-03-29 0:21 ` Reiji Watanabe 2023-03-29 12:03 ` Marc Zyngier 2023-03-29 12:03 ` Marc Zyngier 2023-03-30 3:55 ` Reiji Watanabe 2023-03-30 3:55 ` Reiji Watanabe 2023-04-04 14:25 ` Mark Rutland 2023-04-04 14:25 ` Mark Rutland 2023-04-06 2:28 ` Reiji Watanabe 2023-04-06 2:28 ` Reiji Watanabe 2023-04-04 10:05 ` [PATCH v1 0/2] KVM: arm64: PMU: Correct the handling of PMUSERENR_EL0 Marc Zyngier 2023-04-04 10:05 ` Marc Zyngier
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