[PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[Fabio Estevam]

From: Fabio Estevam <festevam@denx.de>

The Samsung DSIM IP block allows the inversion of the clock and
data lanes.

Add an optional property called 'lane-polarities' that describes the
polarities of the MIPI DSI clock and data lanes.

This is property is useful for properly describing the hardware
when the board designer decided to switch the polarities of the MIPI DSI
clock and/or data lanes.

Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 .../devicetree/bindings/display/exynos/exynos_dsim.txt      | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
index 2a5f0889ec32..65ed8ef7aed7 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
@@ -29,6 +29,12 @@ Required properties:
 
 Optional properties:
   - power-domains: a phandle to DSIM power domain node
+  - lane-polarities: Array that describes the polarities of the clock and data lanes.
+    1: inverted polarity
+    0: normal polarity
+    The first entry corresponds to the clock lanes. Subsequent entries correspond to the data lanes.
+    Example of a 4-lane system with only the clock lanes inverted:
+    lane-polarities = <1 0 0 0 0>;
 
 Child nodes:
   Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
-- 
2.34.1

[PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[Fabio Estevam]

From: Fabio Estevam <festevam@denx.de>

The Samsung DSIM IP block allows the inversion of the clock and
data lanes.

Add an optional property called 'lane-polarities' that describes the
polarities of the MIPI DSI clock and data lanes.

This is property is useful for properly describing the hardware
when the board designer decided to switch the polarities of the MIPI DSI
clock and/or data lanes.

Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 .../devicetree/bindings/display/exynos/exynos_dsim.txt      | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
index 2a5f0889ec32..65ed8ef7aed7 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
@@ -29,6 +29,12 @@ Required properties:
 
 Optional properties:
   - power-domains: a phandle to DSIM power domain node
+  - lane-polarities: Array that describes the polarities of the clock and data lanes.
+    1: inverted polarity
+    0: normal polarity
+    The first entry corresponds to the clock lanes. Subsequent entries correspond to the data lanes.
+    Example of a 4-lane system with only the clock lanes inverted:
+    lane-polarities = <1 0 0 0 0>;
 
 Child nodes:
   Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
-- 
2.34.1

[PATCH 2/2] drm/exynos: Implement support for DSI clock and data lane polarity swap

[Fabio Estevam]

From: Marek Vasut <marex@denx.de>

Implement support for DSI clock and data lane DN/DP polarity swap by
means of decoding 'lane-polarities' DT property. The controller does
support DN/DP swap of clock lane and all data lanes, the controller
does not support polarity swap of individual data lane bundles, add
a check which verifies all data lanes have the same polarity.

This has been validated on an imx8mm board that actually has the MIPI DSI
clock lanes inverted.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 27 ++++++++++++++++++++++++++-
 include/drm/bridge/samsung-dsim.h     |  2 ++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..5791148e2da2 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -183,6 +183,8 @@
 #define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
 
 /* DSIM_PLLCTRL */
+#define DSIM_PLL_DPDNSWAP_CLK		(1 << 25)
+#define DSIM_PLL_DPDNSWAP_DAT		(1 << 24)
 #define DSIM_FREQ_BAND(x)		((x) << 24)
 #define DSIM_PLL_EN			BIT(23)
 #define DSIM_PLL_P(x, offset)		((x) << (offset))
@@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
 		reg |= DSIM_FREQ_BAND(band);
 	}
 
+	if (dsi->swap_dn_dp_clk)
+		reg |= DSIM_PLL_DPDNSWAP_CLK;
+	if (dsi->swap_dn_dp_data)
+		reg |= DSIM_PLL_DPDNSWAP_DAT;
+
 	samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
 
 	timeout = 1000;
@@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
 {
 	struct device *dev = dsi->dev;
 	struct device_node *node = dev->of_node;
-	int ret;
+	u32 lane_polarities[5] = { 0 };
+	struct device_node *endpoint;
+	int i, nr_lanes, ret;
 
 	ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
 				       &dsi->pll_clk_rate);
@@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
 	if (ret < 0)
 		return ret;
 
+	endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
+	nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
+	if (nr_lanes > 0 && nr_lanes <= 4) {
+		/* Polarity 0 is clock lane, 1..4 are data lanes. */
+		of_property_read_u32_array(endpoint, "lane-polarities",
+					   lane_polarities, nr_lanes + 1);
+		for (i = 1; i <= nr_lanes; i++) {
+			if (lane_polarities[1] != lane_polarities[i])
+				DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
+		}
+		if (lane_polarities[0])
+			dsi->swap_dn_dp_clk = true;
+		if (lane_polarities[1])
+			dsi->swap_dn_dp_data = true;
+	}
+
 	return 0;
 }
 
diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h
index ba5484de2b30..6a37d1e079bf 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -95,6 +95,8 @@ struct samsung_dsim {
 	u32 mode_flags;
 	u32 format;
 
+	bool swap_dn_dp_clk;
+	bool swap_dn_dp_data;
 	int state;
 	struct drm_property *brightness;
 	struct completion completed;
-- 
2.34.1

[PATCH 2/2] drm/exynos: Implement support for DSI clock and data lane polarity swap

[Fabio Estevam]

From: Marek Vasut <marex@denx.de>

Implement support for DSI clock and data lane DN/DP polarity swap by
means of decoding 'lane-polarities' DT property. The controller does
support DN/DP swap of clock lane and all data lanes, the controller
does not support polarity swap of individual data lane bundles, add
a check which verifies all data lanes have the same polarity.

This has been validated on an imx8mm board that actually has the MIPI DSI
clock lanes inverted.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 27 ++++++++++++++++++++++++++-
 include/drm/bridge/samsung-dsim.h     |  2 ++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..5791148e2da2 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -183,6 +183,8 @@
 #define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
 
 /* DSIM_PLLCTRL */
+#define DSIM_PLL_DPDNSWAP_CLK		(1 << 25)
+#define DSIM_PLL_DPDNSWAP_DAT		(1 << 24)
 #define DSIM_FREQ_BAND(x)		((x) << 24)
 #define DSIM_PLL_EN			BIT(23)
 #define DSIM_PLL_P(x, offset)		((x) << (offset))
@@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
 		reg |= DSIM_FREQ_BAND(band);
 	}
 
+	if (dsi->swap_dn_dp_clk)
+		reg |= DSIM_PLL_DPDNSWAP_CLK;
+	if (dsi->swap_dn_dp_data)
+		reg |= DSIM_PLL_DPDNSWAP_DAT;
+
 	samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
 
 	timeout = 1000;
@@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
 {
 	struct device *dev = dsi->dev;
 	struct device_node *node = dev->of_node;
-	int ret;
+	u32 lane_polarities[5] = { 0 };
+	struct device_node *endpoint;
+	int i, nr_lanes, ret;
 
 	ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
 				       &dsi->pll_clk_rate);
@@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
 	if (ret < 0)
 		return ret;
 
+	endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
+	nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
+	if (nr_lanes > 0 && nr_lanes <= 4) {
+		/* Polarity 0 is clock lane, 1..4 are data lanes. */
+		of_property_read_u32_array(endpoint, "lane-polarities",
+					   lane_polarities, nr_lanes + 1);
+		for (i = 1; i <= nr_lanes; i++) {
+			if (lane_polarities[1] != lane_polarities[i])
+				DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
+		}
+		if (lane_polarities[0])
+			dsi->swap_dn_dp_clk = true;
+		if (lane_polarities[1])
+			dsi->swap_dn_dp_data = true;
+	}
+
 	return 0;
 }
 
diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h
index ba5484de2b30..6a37d1e079bf 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -95,6 +95,8 @@ struct samsung_dsim {
 	u32 mode_flags;
 	u32 format;
 
+	bool swap_dn_dp_clk;
+	bool swap_dn_dp_data;
 	int state;
 	struct drm_property *brightness;
 	struct completion completed;
-- 
2.34.1

Re: [PATCH 2/2] drm/exynos: Implement support for DSI clock and data lane polarity swap

[Jagan Teki]

On Wed, Mar 29, 2023 at 8:12 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> From: Marek Vasut <marex@denx.de>
>
> Implement support for DSI clock and data lane DN/DP polarity swap by
> means of decoding 'lane-polarities' DT property. The controller does
> support DN/DP swap of clock lane and all data lanes, the controller
> does not support polarity swap of individual data lane bundles, add
> a check which verifies all data lanes have the same polarity.
>
> This has been validated on an imx8mm board that actually has the MIPI DSI
> clock lanes inverted.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Fabio Estevam <festevam@denx.de>
> ---

Prefix would be "drm: bridge: samsung-dsim: "

Otherwise look good to me, I will give a test and update.

Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Re: [PATCH 2/2] drm/exynos: Implement support for DSI clock and data lane polarity swap

[Jagan Teki]

On Wed, Mar 29, 2023 at 8:12 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> From: Marek Vasut <marex@denx.de>
>
> Implement support for DSI clock and data lane DN/DP polarity swap by
> means of decoding 'lane-polarities' DT property. The controller does
> support DN/DP swap of clock lane and all data lanes, the controller
> does not support polarity swap of individual data lane bundles, add
> a check which verifies all data lanes have the same polarity.
>
> This has been validated on an imx8mm board that actually has the MIPI DSI
> clock lanes inverted.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Fabio Estevam <festevam@denx.de>
> ---

Prefix would be "drm: bridge: samsung-dsim: "

Otherwise look good to me, I will give a test and update.

Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Re: [PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[Jagan Teki]

On Wed, Mar 29, 2023 at 8:12 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> From: Fabio Estevam <festevam@denx.de>
>
> The Samsung DSIM IP block allows the inversion of the clock and
> data lanes.
>
> Add an optional property called 'lane-polarities' that describes the
> polarities of the MIPI DSI clock and data lanes.
>
> This is property is useful for properly describing the hardware
> when the board designer decided to switch the polarities of the MIPI DSI
> clock and/or data lanes.
>
> Signed-off-by: Fabio Estevam <festevam@denx.de>
> ---

Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Re: [PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[Jagan Teki]

On Wed, Mar 29, 2023 at 8:12 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> From: Fabio Estevam <festevam@denx.de>
>
> The Samsung DSIM IP block allows the inversion of the clock and
> data lanes.
>
> Add an optional property called 'lane-polarities' that describes the
> polarities of the MIPI DSI clock and data lanes.
>
> This is property is useful for properly describing the hardware
> when the board designer decided to switch the polarities of the MIPI DSI
> clock and/or data lanes.
>
> Signed-off-by: Fabio Estevam <festevam@denx.de>
> ---

Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

Re: [PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[Krzysztof Kozlowski]

On 29/03/2023 16:41, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@denx.de>
> 
> The Samsung DSIM IP block allows the inversion of the clock and
> data lanes.
> 
> Add an optional property called 'lane-polarities' that describes the
> polarities of the MIPI DSI clock and data lanes.
> 
> This is property is useful for properly describing the hardware
> when the board designer decided to switch the polarities of the MIPI DSI
> clock and/or data lanes.
> 
> Signed-off-by: Fabio Estevam <festevam@denx.de>
> ---
>  .../devicetree/bindings/display/exynos/exynos_dsim.txt      | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> index 2a5f0889ec32..65ed8ef7aed7 100644
> --- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> @@ -29,6 +29,12 @@ Required properties:
>  
>  Optional properties:
>    - power-domains: a phandle to DSIM power domain node
> +  - lane-polarities: Array that describes the polarities of the clock and data lanes.
> +    1: inverted polarity
> +    0: normal polarity
> +    The first entry corresponds to the clock lanes. Subsequent entries correspond to the data lanes.
> +    Example of a 4-lane system with only the clock lanes inverted:
> +    lane-polarities = <1 0 0 0 0>;

First, please convert to DT schema.

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[Krzysztof Kozlowski]

On 29/03/2023 16:41, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@denx.de>
> 
> The Samsung DSIM IP block allows the inversion of the clock and
> data lanes.
> 
> Add an optional property called 'lane-polarities' that describes the
> polarities of the MIPI DSI clock and data lanes.
> 
> This is property is useful for properly describing the hardware
> when the board designer decided to switch the polarities of the MIPI DSI
> clock and/or data lanes.
> 
> Signed-off-by: Fabio Estevam <festevam@denx.de>
> ---
>  .../devicetree/bindings/display/exynos/exynos_dsim.txt      | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> index 2a5f0889ec32..65ed8ef7aed7 100644
> --- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> @@ -29,6 +29,12 @@ Required properties:
>  
>  Optional properties:
>    - power-domains: a phandle to DSIM power domain node
> +  - lane-polarities: Array that describes the polarities of the clock and data lanes.
> +    1: inverted polarity
> +    0: normal polarity
> +    The first entry corresponds to the clock lanes. Subsequent entries correspond to the data lanes.
> +    Example of a 4-lane system with only the clock lanes inverted:
> +    lane-polarities = <1 0 0 0 0>;

First, please convert to DT schema.

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[Jagan Teki]

On Thu, Mar 30, 2023 at 1:08 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 29/03/2023 16:41, Fabio Estevam wrote:
> > From: Fabio Estevam <festevam@denx.de>
> >
> > The Samsung DSIM IP block allows the inversion of the clock and
> > data lanes.
> >
> > Add an optional property called 'lane-polarities' that describes the
> > polarities of the MIPI DSI clock and data lanes.
> >
> > This is property is useful for properly describing the hardware
> > when the board designer decided to switch the polarities of the MIPI DSI
> > clock and/or data lanes.
> >
> > Signed-off-by: Fabio Estevam <festevam@denx.de>
> > ---
> >  .../devicetree/bindings/display/exynos/exynos_dsim.txt      | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> > index 2a5f0889ec32..65ed8ef7aed7 100644
> > --- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> > +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> > @@ -29,6 +29,12 @@ Required properties:
> >
> >  Optional properties:
> >    - power-domains: a phandle to DSIM power domain node
> > +  - lane-polarities: Array that describes the polarities of the clock and data lanes.
> > +    1: inverted polarity
> > +    0: normal polarity
> > +    The first entry corresponds to the clock lanes. Subsequent entries correspond to the data lanes.
> > +    Example of a 4-lane system with only the clock lanes inverted:
> > +    lane-polarities = <1 0 0 0 0>;
>
> First, please convert to DT schema.

I have a previous iteration of this conversion. Can I resend it on top
of drm-misc-next?
https://lore.kernel.org/all/20210704090230.26489-9-jagan@amarulasolutions.com/

Jagan.

Re: [PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[Jagan Teki]

On Thu, Mar 30, 2023 at 1:08 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 29/03/2023 16:41, Fabio Estevam wrote:
> > From: Fabio Estevam <festevam@denx.de>
> >
> > The Samsung DSIM IP block allows the inversion of the clock and
> > data lanes.
> >
> > Add an optional property called 'lane-polarities' that describes the
> > polarities of the MIPI DSI clock and data lanes.
> >
> > This is property is useful for properly describing the hardware
> > when the board designer decided to switch the polarities of the MIPI DSI
> > clock and/or data lanes.
> >
> > Signed-off-by: Fabio Estevam <festevam@denx.de>
> > ---
> >  .../devicetree/bindings/display/exynos/exynos_dsim.txt      | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> > index 2a5f0889ec32..65ed8ef7aed7 100644
> > --- a/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> > +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dsim.txt
> > @@ -29,6 +29,12 @@ Required properties:
> >
> >  Optional properties:
> >    - power-domains: a phandle to DSIM power domain node
> > +  - lane-polarities: Array that describes the polarities of the clock and data lanes.
> > +    1: inverted polarity
> > +    0: normal polarity
> > +    The first entry corresponds to the clock lanes. Subsequent entries correspond to the data lanes.
> > +    Example of a 4-lane system with only the clock lanes inverted:
> > +    lane-polarities = <1 0 0 0 0>;
>
> First, please convert to DT schema.

I have a previous iteration of this conversion. Can I resend it on top
of drm-misc-next?
https://lore.kernel.org/all/20210704090230.26489-9-jagan@amarulasolutions.com/

Jagan.

Re: [PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[Fabio Estevam]

Hi Jagan,

On Thu, Mar 30, 2023 at 4:55 AM Jagan Teki <jagan@amarulasolutions.com> wrote:

> I have a previous iteration of this conversion. Can I resend it on top
> of drm-misc-next?
> https://lore.kernel.org/all/20210704090230.26489-9-jagan@amarulasolutions.com/

I tried applying your patch against linux-next, but I get the following error:

$ make dt_binding_check DT_SCHEMA_FILES=samsung,mipi-dsim.yaml
  LINT    Documentation/devicetree/bindings
  CHKDT   Documentation/devicetree/bindings/processed-schema.json
/home/fabio/linux-next/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml:
properties:samsung,power-domain:maxItems: False schema does not allow
1
hint: Scalar properties should not have array keywords
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
  DTEX    Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.example.dts
  DTC_CHK Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.example.dtb

Could you please take a look?

Thanks

Re: [PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[Fabio Estevam]

Hi Jagan,

On Thu, Mar 30, 2023 at 4:55 AM Jagan Teki <jagan@amarulasolutions.com> wrote:

> I have a previous iteration of this conversion. Can I resend it on top
> of drm-misc-next?
> https://lore.kernel.org/all/20210704090230.26489-9-jagan@amarulasolutions.com/

I tried applying your patch against linux-next, but I get the following error:

$ make dt_binding_check DT_SCHEMA_FILES=samsung,mipi-dsim.yaml
  LINT    Documentation/devicetree/bindings
  CHKDT   Documentation/devicetree/bindings/processed-schema.json
/home/fabio/linux-next/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml:
properties:samsung,power-domain:maxItems: False schema does not allow
1
hint: Scalar properties should not have array keywords
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
  DTEX    Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.example.dts
  DTC_CHK Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.example.dtb

Could you please take a look?

Thanks

Re: [PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[Jagan Teki]

Hi Fabio,

On Thu, Mar 30, 2023 at 4:39 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Jagan,
>
> On Thu, Mar 30, 2023 at 4:55 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> > I have a previous iteration of this conversion. Can I resend it on top
> > of drm-misc-next?
> > https://lore.kernel.org/all/20210704090230.26489-9-jagan@amarulasolutions.com/
>
> I tried applying your patch against linux-next, but I get the following error:
>
> $ make dt_binding_check DT_SCHEMA_FILES=samsung,mipi-dsim.yaml
>   LINT    Documentation/devicetree/bindings
>   CHKDT   Documentation/devicetree/bindings/processed-schema.json
> /home/fabio/linux-next/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml:
> properties:samsung,power-domain:maxItems: False schema does not allow
> 1
> hint: Scalar properties should not have array keywords
> from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
>   DTEX    Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.example.dts
>   DTC_CHK Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.example.dtb
>
> Could you please take a look?

I will rework this patch and update the next version.

Thanks,
Jagan.

Re: [PATCH 1/2] dt-bindings: display: exynos: dsim: Add 'lane-polarities'

[Jagan Teki]

Hi Fabio,

On Thu, Mar 30, 2023 at 4:39 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Jagan,
>
> On Thu, Mar 30, 2023 at 4:55 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> > I have a previous iteration of this conversion. Can I resend it on top
> > of drm-misc-next?
> > https://lore.kernel.org/all/20210704090230.26489-9-jagan@amarulasolutions.com/
>
> I tried applying your patch against linux-next, but I get the following error:
>
> $ make dt_binding_check DT_SCHEMA_FILES=samsung,mipi-dsim.yaml
>   LINT    Documentation/devicetree/bindings
>   CHKDT   Documentation/devicetree/bindings/processed-schema.json
> /home/fabio/linux-next/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml:
> properties:samsung,power-domain:maxItems: False schema does not allow
> 1
> hint: Scalar properties should not have array keywords
> from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
>   DTEX    Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.example.dts
>   DTC_CHK Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.example.dtb
>
> Could you please take a look?

I will rework this patch and update the next version.

Thanks,
Jagan.