[PATCH 00/23] Add i.MX8ULP A1 revision support

[PATCH 00/23] Add i.MX8ULP A1 revision support

[Ye Li]

The patch set is used to support i.MX8ULP A1 revision. 
It includes below changes:
a) XRDC/TRDC are enabled by default on A1 via DBD_EN fuse programmed.
   So necessary changes for XRDC setting are added. And TRDC is totally
   moved to RTD. A handshake is added to sync with RTD for the XRDC and TRDC 
   setting completion.
b) S400 API update and fuse update
c) DDR timing and driver update
d) clock setting update to match max rate restriction
e) uPower API update and code clean

Jacky Bai (2):
  ddr: imx: Update the ddr init flow on imx8ulp
  imx8ulp_evk: Update the DDR timing

Peng Fan (3):
  imx: imx8ulp: upower: replace magic number with macro
  imx: imx8ulp: upower: make code cleaner
  imx8ulp_evk: disable overflow of port0 for LPAV

Ye Li (18):
  imx: imx8ulp: Fix MU device probe failure
  imx: imx8ulp: Get chip revision from Sentinel
  imx: imx8ulp: Limit the eMMC ROM API workaround to A0.1 part
  imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APD
  imx: imx8ulp: Remove the TRDC configure from A35
  imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion
  imx: imx8ulp: configure XRDC for DRAM access from S400
  ddr: imx8ulp: Change DRAM timing save area to 0x20055000
  imx: imx8ulp: Reconfigure MRC3 for SRAM0 access
  imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers
  imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only
  imx: imx8ulp: Update clocks to meet max rate restrictions
  imx: sentinel: Update S400 API get info message structure
  misc: fuse: Update fuse mapping for 8ULP S400 API
  misc: fuse: Lock 8ULP ECC-protected fuse when programming
  imx8ulp_evk: Change to use DDR driver
  imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun
  imx8ulp_evk: Clear data at fdt_addr_r before booting kernel

 arch/arm/include/asm/arch-imx8ulp/imx-regs.h    |   1 +
 arch/arm/include/asm/arch-imx8ulp/rdc.h         |   1 +
 arch/arm/include/asm/arch-imx8ulp/sys_proto.h   |   2 +
 arch/arm/include/asm/global_data.h              |   3 +
 arch/arm/include/asm/mach-imx/s400_api.h        |   2 +
 arch/arm/mach-imx/imx8ulp/Kconfig               |   1 +
 arch/arm/mach-imx/imx8ulp/cgc.c                 |  70 ++++----
 arch/arm/mach-imx/imx8ulp/clock.c               |  50 +++---
 arch/arm/mach-imx/imx8ulp/rdc.c                 |  71 ++++++++
 arch/arm/mach-imx/imx8ulp/soc.c                 | 208 ++++++++++++++++++-----
 arch/arm/mach-imx/imx8ulp/upower/upower_hal.c   | 112 +++++++++++--
 board/freescale/imx8ulp_evk/Makefile            |   2 +-
 board/freescale/imx8ulp_evk/ddr_init.c          | 207 -----------------------
 board/freescale/imx8ulp_evk/imx8ulp_evk.c       |  16 +-
 board/freescale/imx8ulp_evk/lpddr4_timing.c     | 210 ++++++++++++------------
 board/freescale/imx8ulp_evk/lpddr4_timing_266.c |   6 +-
 board/freescale/imx8ulp_evk/spl.c               |  18 +-
 drivers/ddr/imx/imx8ulp/Kconfig                 |   2 +-
 drivers/ddr/imx/imx8ulp/ddr_init.c              |  55 +++++--
 drivers/misc/sentinel/fuse.c                    |  32 +++-
 20 files changed, 605 insertions(+), 464 deletions(-)
 delete mode 100644 board/freescale/imx8ulp_evk/ddr_init.c

-- 
2.7.4

[PATCH 01/23] imx: imx8ulp: Fix MU device probe failure

[Ye Li]

Since latest DTS has added multiple MU nodes, using compatible
string to find the device node is not proper. It finds the first
node with the compatible string matched even the node is disabled.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/soc.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 5d95fb8..3498cf9 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -673,11 +673,9 @@ int arch_cpu_init(void)
 static int imx8ulp_check_mu(void *ctx, struct event *event)
 {
 	struct udevice *devp;
-	int node, ret;
-
-	node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8ulp-mu");
+	int ret;
 
-	ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
+	ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8ulp_mu), &devp);
 	if (ret) {
 		printf("could not get S400 mu %d\n", ret);
 		return ret;
-- 
2.7.4

[PATCH 02/23] imx: imx8ulp: Get chip revision from Sentinel

[Ye Li]

In both SPL and u-boot, after probing the S400 MU, get the chip revision,
lifecycle and UID from Sentinel.
Update get_cpu_rev to use the chip revision not hard coded it for A0

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8ulp/imx-regs.h  |  1 +
 arch/arm/include/asm/arch-imx8ulp/sys_proto.h |  1 +
 arch/arm/mach-imx/imx8ulp/soc.c               | 32 ++++++++++++++++++++++++---
 board/freescale/imx8ulp_evk/spl.c             | 10 +++------
 4 files changed, 34 insertions(+), 10 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
index f5a2968..a038cc1 100644
--- a/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8ulp/imx-regs.h
@@ -10,6 +10,7 @@
 #include <linux/bitops.h>
 #include <linux/sizes.h>
 
+#define SRAM0_BASE          0x22010000
 #define PBRIDGE0_BASE		0x28000000
 
 #define CMC0_RBASE		0x28025000
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index a7869fb..ff49c62 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -15,4 +15,5 @@ void set_lpav_qos(void);
 void load_lposc_fuse(void);
 bool m33_image_booted(void);
 int m33_image_handshake(ulong timeout_ms);
+int imx8ulp_dm_post_init(void);
 #endif
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 3498cf9..9b12d3d 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -70,9 +70,18 @@ int mmc_get_env_dev(void)
 }
 #endif
 
+static void set_cpu_info(struct sentinel_get_info_data *info)
+{
+	gd->arch.soc_rev = info->soc;
+	gd->arch.lifecycle = info->lc;
+	memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32));
+}
+
 u32 get_cpu_rev(void)
 {
-	return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0;
+	u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+
+	return (MXC_CPU_IMX8ULP << 12) | (CHIP_REV_1_0 + rev);
 }
 
 enum bt_mode get_boot_mode(void)
@@ -670,10 +679,12 @@ int arch_cpu_init(void)
 	return 0;
 }
 
-static int imx8ulp_check_mu(void *ctx, struct event *event)
+int imx8ulp_dm_post_init(void)
 {
 	struct udevice *devp;
 	int ret;
+	u32 res;
+	struct sentinel_get_info_data *info = (struct sentinel_get_info_data *)SRAM0_BASE;
 
 	ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8ulp_mu), &devp);
 	if (ret) {
@@ -681,9 +692,24 @@ static int imx8ulp_check_mu(void *ctx, struct event *event)
 		return ret;
 	}
 
+	ret = ahab_get_info(info, &res);
+	if (ret) {
+		printf("ahab_get_info failed %d\n", ret);
+		/* fallback to A0.1 revision */
+		memset((void *)info, 0, sizeof(struct sentinel_get_info_data));
+		info->soc = 0xa000084d;
+	}
+
+	set_cpu_info(info);
+
 	return 0;
 }
-EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_check_mu);
+
+static int imx8ulp_evt_dm_post_init(void *ctx, struct event *event)
+{
+	return imx8ulp_dm_post_init();
+}
+EVENT_SPY(EVT_DM_POST_INIT, imx8ulp_evt_dm_post_init);
 
 #if defined(CONFIG_SPL_BUILD)
 __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index e672f6e..2a96bd0 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -77,16 +77,12 @@ void display_ele_fw_version(void)
 
 void spl_board_init(void)
 {
-	struct udevice *dev;
 	u32 res;
 	int ret;
 
-	uclass_find_first_device(UCLASS_MISC, &dev);
-
-	for (; dev; uclass_find_next_device(&dev)) {
-		if (device_probe(dev))
-			continue;
-	}
+	ret = imx8ulp_dm_post_init();
+	if (ret)
+		return;
 
 	board_early_init_f();
 
-- 
2.7.4

[PATCH 03/23] imx: imx8ulp: Limit the eMMC ROM API workaround to A0.1 part

[Ye Li]

Since A1 ROM has fixed the ROM API eMMC issue, we should only use
the workaround for A0.1 part. Add a SOC revision check.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/soc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 9b12d3d..4370399 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -761,7 +761,8 @@ int (*card_emmc_is_boot_part_en)(void) = (void *)0x67cc;
 u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev)
 {
 	/* Hard code for eMMC image_offset on 8ULP ROM, need fix by ROM, temp workaround */
-	if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC && card_emmc_is_boot_part_en())
+	if (is_soc_rev(CHIP_REV_1_0) && ((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_MMC &&
+		card_emmc_is_boot_part_en())
 		image_offset = 0;
 
 	return image_offset;
-- 
2.7.4

[PATCH 04/23] imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APD

[Ye Li]

iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set
them in SPL to allow access to DDR from A35 and APD PER masters

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/rdc.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index 6d2adcf..d664437 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -276,6 +276,16 @@ void xrdc_init_mda(void)
 
 void xrdc_init_mrc(void)
 {
+	/* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */
+	xrdc_config_mrc_w0_w1(4, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
+	xrdc_config_mrc_dx_perm(4, 0, 1, 1);
+	xrdc_config_mrc_dx_perm(4, 0, 7, 1);
+	xrdc_config_mrc_w3_w4(4, 0, 0x0, 0x80000FFF);
+
+	xrdc_config_mrc_w0_w1(5, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
+	xrdc_config_mrc_dx_perm(5, 0, 1, 1);
+	xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF);
+
 	/* The MRC8 is for SRAM1 */
 	xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000);
 	/* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */
-- 
2.7.4

[PATCH 05/23] imx: imx8ulp: Remove the TRDC configure from A35

[Ye Li]

As M33 is responsible for TRDC configuration, the settings for A35
nonsecure world access and DMA0 access are moved to M33 image.
So remove the codes to release TRDC and configure it. Just keep
the configurations for reference.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/soc.c | 63 +++++++++++++++++++++++++++++------------
 1 file changed, 45 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 4370399..0d7858a 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -556,33 +556,65 @@ static void set_core0_reset_vector(u32 entry)
 	setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26));
 }
 
-static int trdc_set_access(void)
+/* Not used now */
+int trdc_set_access(void)
 {
 	/*
 	 * TRDC mgr + 4 MBC + 2 MRC.
-	 * S400 should already configure when release RDC
-	 * A35 only map non-secure region for pbridge0 and 1, set sec_access to false
 	 */
-	trdc_mbc_set_access(2, 7, 0, 49, false);
-	trdc_mbc_set_access(2, 7, 0, 50, false);
-	trdc_mbc_set_access(2, 7, 0, 51, false);
-	trdc_mbc_set_access(2, 7, 0, 52, false);
-	trdc_mbc_set_access(2, 7, 0, 53, false);
-	trdc_mbc_set_access(2, 7, 0, 54, false);
-
-	/* CGC0: PBridge0 slot 47 */
+	trdc_mbc_set_access(2, 7, 0, 49, true);
+	trdc_mbc_set_access(2, 7, 0, 50, true);
+	trdc_mbc_set_access(2, 7, 0, 51, true);
+	trdc_mbc_set_access(2, 7, 0, 52, true);
+	trdc_mbc_set_access(2, 7, 0, 53, true);
+	trdc_mbc_set_access(2, 7, 0, 54, true);
+
+	/* 0x1fff8000 used for resource table by remoteproc */
+	trdc_mbc_set_access(0, 7, 2, 31, false);
+
+	/* CGC0: PBridge0 slot 47 and PCC0 slot 48 */
 	trdc_mbc_set_access(2, 7, 0, 47, false);
+	trdc_mbc_set_access(2, 7, 0, 48, false);
+
+	/* PCC1 */
+	trdc_mbc_set_access(2, 7, 1, 17, false);
+	trdc_mbc_set_access(2, 7, 1, 34, false);
 
 	/* Iomuxc0: : PBridge1 slot 33 */
 	trdc_mbc_set_access(2, 7, 1, 33, false);
 
 	/* flexspi0 */
+	trdc_mbc_set_access(2, 7, 0, 57, false);
 	trdc_mrc_region_set_access(0, 7, 0x04000000, 0x0c000000, false);
 
 	/* tpm0: PBridge1 slot 21 */
 	trdc_mbc_set_access(2, 7, 1, 21, false);
 	/* lpi2c0: PBridge1 slot 24 */
 	trdc_mbc_set_access(2, 7, 1, 24, false);
+
+	/* Allow M33 to access TRDC MGR */
+	trdc_mbc_set_access(2, 6, 0, 49, true);
+	trdc_mbc_set_access(2, 6, 0, 50, true);
+	trdc_mbc_set_access(2, 6, 0, 51, true);
+	trdc_mbc_set_access(2, 6, 0, 52, true);
+	trdc_mbc_set_access(2, 6, 0, 53, true);
+	trdc_mbc_set_access(2, 6, 0, 54, true);
+
+	/* Set SAI0 for eDMA 0, NS */
+	trdc_mbc_set_access(2, 0, 1, 28, false);
+
+	/* Set SSRAM for eDMA0 access */
+	trdc_mbc_set_access(0, 0, 2, 0, false);
+	trdc_mbc_set_access(0, 0, 2, 1, false);
+	trdc_mbc_set_access(0, 0, 2, 2, false);
+	trdc_mbc_set_access(0, 0, 2, 3, false);
+	trdc_mbc_set_access(0, 0, 2, 4, false);
+	trdc_mbc_set_access(0, 0, 2, 5, false);
+	trdc_mbc_set_access(0, 0, 2, 6, false);
+	trdc_mbc_set_access(0, 0, 2, 7, false);
+
+	writel(0x800000a0, 0x28031840);
+
 	return 0;
 }
 
@@ -654,15 +686,10 @@ int arch_cpu_init(void)
 		if (!ret)
 			rdc_en = !!(val & 0x4000);
 
-		if (get_boot_mode() == SINGLE_BOOT) {
-			if (rdc_en)
-				release_rdc(RDC_TRDC);
-
-			trdc_set_access();
+		if (get_boot_mode() == SINGLE_BOOT)
 			lpav_configure(false);
-		} else {
+		else
 			lpav_configure(true);
-		}
 
 		/* Release xrdc, then allow A35 to write SRAM2 */
 		if (rdc_en)
-- 
2.7.4

[PATCH 06/23] imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion

[Ye Li]

To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment.
M33 will be the TRDC owner and needs to configure TRDC. A35 is the
XRDC owner, ATF will configure XRDC.

The handshake between U-boot and M33 image is used to sync TRDC and
XRDC configuration completion. Once the handshake is done, A35 and M33
can access the allowed resources in others domain.

The handshake is needed when M33 is booted or DBD_EN fused, because both
cases will enable the TRDC. If handshake is timeout, the boot will hang.
We use SIM GPR0 to pass the info from SPL to u-boot, because before the
handshake, u-boot can't access SEC SIM and FSB.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
---
 arch/arm/include/asm/arch-imx8ulp/sys_proto.h |   1 +
 arch/arm/include/asm/global_data.h            |   3 +
 arch/arm/mach-imx/imx8ulp/soc.c               | 104 ++++++++++++++++++++++----
 board/freescale/imx8ulp_evk/imx8ulp_evk.c     |   8 +-
 4 files changed, 93 insertions(+), 23 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index ff49c62..5bbae21 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -14,6 +14,7 @@ int xrdc_config_pdac_openacc(u32 bridge, u32 index);
 void set_lpav_qos(void);
 void load_lposc_fuse(void);
 bool m33_image_booted(void);
+bool is_m33_handshake_necessary(void);
 int m33_image_handshake(ulong timeout_ms);
 int imx8ulp_dm_post_init(void);
 #endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index 9e746e3..8698783 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -97,6 +97,9 @@ struct arch_global_data {
 	u32 uid[4];
 #endif
 
+#ifdef CONFIG_ARCH_IMX8ULP
+	bool m33_handshake_done;
+#endif
 };
 
 #include <asm-generic/global_data.h>
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 0d7858a..8424332 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -104,14 +104,70 @@ enum bt_mode get_boot_mode(void)
 
 bool m33_image_booted(void)
 {
-	u32 gp6;
+	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+		u32 gp6 = 0;
+
+		/* DGO_GP6 */
+		gp6 = readl(SIM_SEC_BASE_ADDR + 0x28);
+		if (gp6 & BIT(5))
+			return true;
+
+		return false;
+	} else {
+		u32 gpr0 = readl(SIM1_BASE_ADDR);
+		if (gpr0 & BIT(0))
+			return true;
+
+		return false;
+	}
+}
+
+bool rdc_enabled_in_boot(void)
+{
+	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+		u32 val = 0;
+		int ret;
+		bool rdc_en = true; /* Default assume DBD_EN is set */
+
+		/* Read DBD_EN fuse */
+		ret = fuse_read(8, 1, &val);
+		if (!ret)
+			rdc_en = !!(val & 0x200); /* only A1 part uses DBD_EN, so check DBD_EN new place*/
+
+		return rdc_en;
+	} else {
+		u32 gpr0 = readl(SIM1_BASE_ADDR);
+		if (gpr0 & 0x2)
+			return true;
+
+		return false;
+	}
+}
+
+static void spl_pass_boot_info(void)
+{
+	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+		bool m33_booted = m33_image_booted();
+		bool rdc_en = rdc_enabled_in_boot();
+		u32 val = 0;
 
-	/* DGO_GP6 */
-	gp6 = readl(SIM_SEC_BASE_ADDR + 0x28);
-	if (gp6 & BIT(5))
-		return true;
+		if (m33_booted)
+			val |= 0x1;
 
-	return false;
+		if (rdc_en)
+			val |= 0x2;
+
+		writel(val, SIM1_BASE_ADDR);
+	}
+}
+
+bool is_m33_handshake_necessary(void)
+{
+	/* Only need handshake in u-boot */
+	if (!IS_ENABLED(CONFIG_SPL_BUILD))
+		return (m33_image_booted() || rdc_enabled_in_boot());
+	else
+		return false;
 }
 
 int m33_image_handshake(ulong timeout_ms)
@@ -661,10 +717,6 @@ void set_lpav_qos(void)
 int arch_cpu_init(void)
 {
 	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
-		u32 val = 0;
-		int ret;
-		bool rdc_en = true; /* Default assume DBD_EN is set */
-
 		/* Enable System Reset Interrupt using WDOG_AD */
 		setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13));
 		/* Clear AD_PERIPH Power switch domain out of reset interrupt flag */
@@ -681,31 +733,51 @@ int arch_cpu_init(void)
 		/* Disable wdog */
 		init_wdog();
 
-		/* Read DBD_EN fuse */
-		ret = fuse_read(8, 1, &val);
-		if (!ret)
-			rdc_en = !!(val & 0x4000);
-
 		if (get_boot_mode() == SINGLE_BOOT)
 			lpav_configure(false);
 		else
 			lpav_configure(true);
 
 		/* Release xrdc, then allow A35 to write SRAM2 */
-		if (rdc_en)
+		if (rdc_enabled_in_boot())
 			release_rdc(RDC_XRDC);
 
 		xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);
 
 		clock_init_early();
+
+		spl_pass_boot_info();
 	} else {
+		int ret;
 		/* reconfigure core0 reset vector to ROM */
 		set_core0_reset_vector(0x1000);
+
+		if (is_m33_handshake_necessary()) {
+			/* Start handshake with M33 to ensure TRDC configuration completed */
+			ret = m33_image_handshake(1000);
+			if (!ret)
+				gd->arch.m33_handshake_done = true;
+			else /* Skip and go through to panic in checkcpu as console is ready then */
+				gd->arch.m33_handshake_done = false;
+		}
 	}
 
 	return 0;
 }
 
+int checkcpu(void)
+{
+	if (is_m33_handshake_necessary()) {
+		if (!gd->arch.m33_handshake_done) {
+			puts("M33 Sync: Timeout, Boot Stop!\n");
+			hang();
+		} else {
+			puts("M33 Sync: OK\n");
+		}
+	}
+	return 0;
+}
+
 int imx8ulp_dm_post_init(void)
 {
 	struct udevice *devp;
diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
index 5aad107..b58f143 100644
--- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c
+++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
@@ -101,18 +101,12 @@ void mipi_dsi_panel_backlight(void)
 
 int board_init(void)
 {
-	int sync = -ENODEV;
 
 	if (IS_ENABLED(CONFIG_FEC_MXC))
 		setup_fec();
 
-	if (m33_image_booted()) {
-		sync = m33_image_handshake(1000);
-		printf("M33 Sync: %s\n", sync ? "Timeout" : "OK");
-	}
-
 	/* When sync with M33 is failed, use local driver to set for video */
-	if (sync != 0 && IS_ENABLED(CONFIG_VIDEO)) {
+	if (!is_m33_handshake_necessary() && IS_ENABLED(CONFIG_VIDEO)) {
 		mipi_dsi_mux_panel();
 		mipi_dsi_panel_backlight();
 	}
-- 
2.7.4

[PATCH 07/23] imx: imx8ulp: configure XRDC for DRAM access from S400

[Ye Li]

Need to add DRAM access permission for S400, as S400 needs to access
it When SPL calls image authentication

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/rdc.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index d664437..8551bf6 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -286,6 +286,11 @@ void xrdc_init_mrc(void)
 	xrdc_config_mrc_dx_perm(5, 0, 1, 1);
 	xrdc_config_mrc_w3_w4(5, 0, 0x0, 0x80000FFF);
 
+	/* Set MRC6 for DDR access from Sentinel */
+	xrdc_config_mrc_w0_w1(6, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
+	xrdc_config_mrc_dx_perm(6, 0, 4, 1);
+	xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
+
 	/* The MRC8 is for SRAM1 */
 	xrdc_config_mrc_w0_w1(8, 0, 0x21000000, 0x10000);
 	/* Allow for all domains: So domain 2/3 (HIFI DSP/LPAV) is ok to access */
-- 
2.7.4

[PATCH 08/23] ddr: imx8ulp: Change DRAM timing save area to 0x20055000

[Ye Li]

To align with ARM trusted firmware's change, adjust DRAM timing
save area to new position 0x20055000. So we can release the space
since 0x2006c000 for the NOBITS region of ARM trusted firmware

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
---
 drivers/ddr/imx/imx8ulp/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/imx/imx8ulp/Kconfig b/drivers/ddr/imx/imx8ulp/Kconfig
index 4284886..5448c33 100644
--- a/drivers/ddr/imx/imx8ulp/Kconfig
+++ b/drivers/ddr/imx/imx8ulp/Kconfig
@@ -13,6 +13,6 @@ config SAVED_DRAM_TIMING_BASE
 	help
 	  The DRAM config timing data need to be saved into sram
 	  for low power use.
-	default 0x2006c000
+	default 0x20055000
 
 endmenu
-- 
2.7.4

[PATCH 09/23] imx: imx8ulp: Reconfigure MRC3 for SRAM0 access

[Ye Li]

Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode
access only for boot purpose. Since SW will reuse the SRAM0 as SCMI
buffer and SPL container loading buffer, need to reconfigure MRC3.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/rdc.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index 8551bf6..472b13b 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -276,6 +276,21 @@ void xrdc_init_mda(void)
 
 void xrdc_init_mrc(void)
 {
+	/* Re-config MRC3 for SRAM0 in case protected by S400 */
+	xrdc_config_mrc_w0_w1(3, 0, 0x22010000, 0x10000);
+	xrdc_config_mrc_dx_perm(3, 0, 0, 1);
+	xrdc_config_mrc_dx_perm(3, 0, 1, 1);
+	xrdc_config_mrc_dx_perm(3, 0, 4, 1);
+	xrdc_config_mrc_dx_perm(3, 0, 5, 1);
+	xrdc_config_mrc_dx_perm(3, 0, 6, 1);
+	xrdc_config_mrc_dx_perm(3, 0, 7, 1);
+	xrdc_config_mrc_w3_w4(3, 0, 0x0, 0x80000FFF);
+
+	/* Clear other 3 regions of MRC3 to invalid */
+	xrdc_config_mrc_w3_w4(3, 1, 0x0, 0x0);
+	xrdc_config_mrc_w3_w4(3, 2, 0x0, 0x0);
+	xrdc_config_mrc_w3_w4(3, 3, 0x0, 0x0);
+
 	/* Set MRC4 and MRC5 for DDR access from A35 and AP NIC PER masters */
 	xrdc_config_mrc_w0_w1(4, 0, CFG_SYS_SDRAM_BASE, PHYS_SDRAM_SIZE);
 	xrdc_config_mrc_dx_perm(4, 0, 1, 1);
-- 
2.7.4

[PATCH 10/23] imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers

[Ye Li]

At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/cgc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index d240aba..104109e 100644
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
@@ -169,6 +169,9 @@ void cgc1_pll3_init(ulong freq)
 	while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30)))
 		;
 
+	clrbits_le32(&cgc1_regs->pll3div_pfd0, 0x3f3f3f3f);
+	clrbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f);
+
 	clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7));
 	clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15));
 	clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23));
-- 
2.7.4

[PATCH 11/23] imx: imx8ulp: upower: replace magic number with macro

[Ye Li]

From: Peng Fan <peng.fan@nxp.com>

The swton indicates the logic switch, magic number 0xfff80 is hard
to understand, so use macro.

Some board design may not have MIPI_CSI voltage input connected per
data sheet. In that case, the upower power on API may dead loop mu to wait
response, however there is no response. So remove MIPI_CSI here, let
linux power domain driver to runtime enable the power domain.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
index b6811d5..370685e 100644
--- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
@@ -11,6 +11,25 @@
 #include "upower_api.h"
 
 #define UPOWER_AP_MU1_ADDR	0x29280000
+
+#define PS_RTD		BIT(0)
+#define PS_DSP		BIT(1)
+#define PS_A35_0	BIT(2)
+#define PS_A35_1	BIT(3)
+#define PS_L2		BIT(4)
+#define PS_FAST_NIC	BIT(5)
+#define PS_APD_PERIPH	BIT(6)
+#define PS_GPU3D	BIT(7)
+#define PS_HIFI4	BIT(8)
+#define PS_DDR		GENMASK(12, 9)
+#define PS_PXP_EPDC	BIT(13)
+#define PS_MIPI_DSI	BIT(14)
+#define PS_MIPI_CSI	BIT(15)
+#define PS_NIC_LPAV	BIT(16)
+#define PS_FUSION_AO	BIT(17)
+#define PS_FUSE		BIT(18)
+#define PS_UPOWER	BIT(19)
+
 static struct mu_type *muptr = (struct mu_type *)UPOWER_AP_MU1_ADDR;
 
 void upower_wait_resp(void)
@@ -140,7 +159,8 @@ int upower_init(void)
 		}
 	} while (0);
 
-	swton = 0xfff80;
+	swton = PS_UPOWER | PS_FUSE | PS_FUSION_AO | PS_NIC_LPAV | PS_PXP_EPDC | PS_DDR |
+		PS_HIFI4 | PS_GPU3D | PS_MIPI_DSI;
 	ret = upwr_pwm_power_on(&swton, NULL, NULL);
 	if (ret)
 		printf("Turn on switches fail %d\n", ret);
-- 
2.7.4

[PATCH 12/23] imx: imx8ulp: upower: make code cleaner

[Ye Li]

From: Peng Fan <peng.fan@nxp.com>

To clean the upower codes by aligning codes format, check err_code
and add detail bits list for the memory magic number

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 90 +++++++++++++++++++++++----
 1 file changed, 78 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
index 370685e..fcb02ed 100644
--- a/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
+++ b/arch/arm/mach-imx/imx8ulp/upower/upower_hal.c
@@ -129,6 +129,7 @@ int upower_init(void)
 	u32 fw_major, fw_minor, fw_vfixes;
 	u32 soc_id;
 	int status;
+	enum upwr_resp err_code;
 
 	u32 swton;
 	u64 memon;
@@ -165,22 +166,86 @@ int upower_init(void)
 	if (ret)
 		printf("Turn on switches fail %d\n", ret);
 	else
-		printf("Turn on switches ok\n");
+		printf("Turning on switches...\n");
+
 	upower_wait_resp();
-	ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000);
+	ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000);
 	if (ret != UPWR_REQ_OK)
-		printf("Failure %d\n", ret);
+		printf("Turn on switches faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
+	else
+		printf("Turn on switches ok\n");
 
-	memon = 0x3FFFFFFFFFFFFCUL;
-	ret = upwr_pwm_power_on(NULL, (const u32 *)&memon, NULL);
+	/*
+	 * Ascending Order -> bit [0:54)
+	 * CA35 Core 0 L1 cache
+	 * CA35 Core 1 L1 cache
+	 * L2 Cache 0
+	 * L2 Cache 1
+	 * L2 Cache victim/tag
+	 * CAAM Secure RAM
+	 * DMA1 RAM
+	 * FlexSPI2 FIFO, Buffer
+	 * SRAM0
+	 * AD ROM
+	 * USB0 TX/RX RAM
+	 * uSDHC0 FIFO RAM
+	 * uSDHC1 FIFO RAM
+	 * uSDHC2 FIFO and USB1 TX/RX RAM
+	 * GIC RAM
+	 * ENET TX FIXO
+	 * Reserved(Brainshift)
+	 * DCNano Tile2Linear and RGB Correction
+	 * DCNano Cursor and FIFO
+	 * EPDC LUT
+	 * EPDC FIFO
+	 * DMA2 RAM
+	 * GPU2D RAM Group 1
+	 * GPU2D RAM Group 2
+	 * GPU3D RAM Group 1
+	 * GPU3D RAM Group 2
+	 * HIFI4 Caches, IRAM, DRAM
+	 * ISI Buffers
+	 * MIPI-CSI FIFO
+	 * MIPI-DSI FIFO
+	 * PXP Caches, Buffers
+	 * SRAM1
+	 * Casper RAM
+	 * DMA0 RAM
+	 * FlexCAN RAM
+	 * FlexSPI0 FIFO, Buffer
+	 * FlexSPI1 FIFO, Buffer
+	 * CM33 Cache
+	 * PowerQuad RAM
+	 * ETF RAM
+	 * Sentinel PKC, Data RAM1, Inst RAM0/1
+	 * Sentinel ROM
+	 * uPower IRAM/DRAM
+	 * uPower ROM
+	 * CM33 ROM
+	 * SSRAM Partition 0
+	 * SSRAM Partition 1
+	 * SSRAM Partition 2,3,4
+	 * SSRAM Partition 5
+	 * SSRAM Partition 6
+	 * SSRAM Partition 7_a(128KB)
+	 * SSRAM Partition 7_b(64KB)
+	 * SSRAM Partition 7_c(64KB)
+	 * Sentinel Data RAM0, Inst RAM2
+	 */
+	/* MIPI-CSI FIFO BIT28 not set */
+	memon = 0x3FFFFFEFFFFFFCUL;
+	ret = upwr_pwm_power_on(NULL, (const uint32_t *)&memon, NULL);
 	if (ret)
 		printf("Turn on memories fail %d\n", ret);
 	else
-		printf("Turn on memories ok\n");
+		printf("Turning on memories...\n");
+
 	upower_wait_resp();
-	ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, NULL, &ret_val, 1000);
+	ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000);
 	if (ret != UPWR_REQ_OK)
-		printf("Failure %d\n", ret);
+		printf("Turn on memories faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
+	else
+		printf("Turn on memories ok\n");
 
 	mdelay(1);
 
@@ -188,13 +253,14 @@ int upower_init(void)
 	if (ret)
 		printf("Clear DDR retention fail %d\n", ret);
 	else
-		printf("Clear DDR retention ok\n");
+		printf("Clearing DDR retention...\n");
 
 	upower_wait_resp();
-
-	ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, NULL, &ret_val, 1000);
+	ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000);
 	if (ret != UPWR_REQ_OK)
-		printf("Failure %d\n", ret);
+		printf("Clear DDR retention fail %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
+	else
+		printf("Clear DDR retention ok\n");
 
 	return 0;
 }
-- 
2.7.4

[PATCH 13/23] imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only

[Ye Li]

This patch is used to support DBD owner fuse changed to S400 only.
The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not
configured by S400 default setting.  So these PDAC and MSC are invalid,
only DBD owner can access the corresponding resources.

We have to configure necessary PDAC and MSC for SPL before DDR
initialization.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8ulp/rdc.h |  1 +
 arch/arm/mach-imx/imx8ulp/rdc.c         | 41 +++++++++++++++++++++++++++++++++
 board/freescale/imx8ulp_evk/spl.c       |  8 ++++---
 3 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx8ulp/rdc.h b/arch/arm/include/asm/arch-imx8ulp/rdc.h
index 9746375..5d555c4 100644
--- a/arch/arm/include/asm/arch-imx8ulp/rdc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/rdc.h
@@ -23,5 +23,6 @@ int trdc_mrc_region_set_access(u32 mrc_x, u32 dom_x, u32 addr_start, u32 addr_en
 
 void xrdc_init_mda(void);
 void xrdc_init_mrc(void);
+void xrdc_init_pdac_msc(void);
 
 #endif
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index 472b13b..50b097b 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -181,6 +181,25 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm)
 	return 0;
 }
 
+int xrdc_config_msc(u32 msc, u32 index, u32 dom, u32 perm)
+{
+	ulong w0_addr;
+	u32 val;
+
+	if (msc > 2)
+		return -EINVAL;
+
+	w0_addr = XRDC_ADDR + 0x4000 + 0x400 * msc + 0x8 * index;
+
+	val = readl(w0_addr);
+	writel((val & ~(0x7 << (dom * 3))) | (perm << (dom * 3)), w0_addr);
+
+	val = readl(w0_addr + 4);
+	writel(val | BIT(31), w0_addr + 4);
+
+	return 0;
+}
+
 int release_rdc(enum rdc_type type)
 {
 	ulong s_mu_base = 0x27020000UL;
@@ -325,6 +344,28 @@ void xrdc_init_mrc(void)
 	xrdc_config_mrc_w3_w4(6, 0, 0x0, 0x80000FFF);
 }
 
+void xrdc_init_pdac_msc(void)
+{
+	/* Init LPAV PDAC and MSC for DDR init */
+	xrdc_config_pdac(5, 36, 6, 0x7); /* CMC2*/
+	xrdc_config_pdac(5, 36, 7, 0x7);
+	xrdc_config_pdac(5, 37, 6, 0x7); /* SIM2 */
+	xrdc_config_pdac(5, 37, 7, 0x7);
+	xrdc_config_pdac(5, 38, 6, 0x7); /* CGC2 */
+	xrdc_config_pdac(5, 38, 7, 0x7);
+	xrdc_config_pdac(5, 39, 6, 0x7); /* PCC5 */
+	xrdc_config_pdac(5, 39, 7, 0x7);
+
+	xrdc_config_msc(0, 0, 6, 0x7); /* GPIOE */
+	xrdc_config_msc(0, 0, 7, 0x7);
+	xrdc_config_msc(0, 1, 6, 0x7); /* GPIOF */
+	xrdc_config_msc(0, 1, 7, 0x7);
+	xrdc_config_msc(1, 0, 6, 0x7); /* GPIOD */
+	xrdc_config_msc(1, 0, 7, 0x7);
+	xrdc_config_msc(2, 6, 6, 0x7); /* DDR controller */
+	xrdc_config_msc(2, 6, 7, 0x7);
+}
+
 int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, bool sec_access)
 {
 	struct trdc *trdc_base = (struct trdc *)0x28031000U;
diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c
index 2a96bd0..a0dad5f 100644
--- a/board/freescale/imx8ulp_evk/spl.c
+++ b/board/freescale/imx8ulp_evk/spl.c
@@ -104,9 +104,6 @@ void spl_board_init(void)
 
 	clock_init_late();
 
-	/* DDR initialization */
-	spl_dram_init();
-
 	/* This must place after upower init, so access to MDA and MRC are valid */
 	/* Init XRDC MDA  */
 	xrdc_init_mda();
@@ -114,6 +111,11 @@ void spl_board_init(void)
 	/* Init XRDC MRC for VIDEO, DSP domains */
 	xrdc_init_mrc();
 
+	xrdc_init_pdac_msc();
+
+	/* DDR initialization */
+	spl_dram_init();
+
 	/* Call it after PS16 power up */
 	set_lpav_qos();
 
-- 
2.7.4

[PATCH 14/23] imx: imx8ulp: Update clocks to meet max rate restrictions

[Ye Li]

Update PLL3/PLL4 PFD and USDHC clocks to meet maximum frequency
restrictions. Detail clock rate changes in the patch:

PLL3 PFD2: 389M -> 324M
PLL3 PFD3: 336M -> 389M
PLL3 PFD3: DIV1 336M -> 389M (OD), 194M (ND/LD)
PLL3 PFD3: DIV2 336M -> 194M (OD), 97M (ND/LD)

PLL4 PFD0: 792M -> 594M
PLL4 PFD2: 792M -> 316.8M

NIC_AP:    96M (ND) -> 192M,  48M (LD) -> 96M
NIC_LPAV:  198 (ND) -> 192M,  99M (LD) -> 96M

USDHC0:    PLL3 PFD3 DIV1, 389M (OD), 194M (ND/LD)
USDHC1:    PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD)
USDHC2:    PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD)

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/cgc.c   | 71 +++++++++++++++++++++------------------
 arch/arm/mach-imx/imx8ulp/clock.c | 50 +++++++++++----------------
 2 files changed, 57 insertions(+), 64 deletions(-)

diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c
index 104109e..d2fadb4 100644
--- a/arch/arm/mach-imx/imx8ulp/cgc.c
+++ b/arch/arm/mach-imx/imx8ulp/cgc.c
@@ -136,42 +136,34 @@ void cgc1_pll3_init(ulong freq)
 	clrbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
 
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F);
-
-	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
-		setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0);
-		clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 3 << 21); /* 195M */
-	} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
-		setbits_le32(&cgc1_regs->pll3pfdcfg, 21 << 0);
-		clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21); /* 231M */
-	} else {
-		setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* 324M */
-	}
-
+	setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* PFD0 324M */
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7));
 	while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(6)))
 		;
 
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 8);
-	setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8);
+	setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8);	/* PFD1 389M */
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15));
 	while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(14)))
 		;
 
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 16);
-	setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 16);
+	setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 16);	/* PFD2 324M */
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23));
 	while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(22)))
 		;
 
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 24);
-	setbits_le32(&cgc1_regs->pll3pfdcfg, 29 << 24);
+	setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 24);	/* PFD3 389M */
 	clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(31));
 	while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30)))
 		;
 
 	clrbits_le32(&cgc1_regs->pll3div_pfd0, 0x3f3f3f3f);
-	clrbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f);
-
+	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE))
+		clrsetbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f, 0x03010000); /* Set PFD3 DIV1 to 194M, PFD3 DIV2 to 97M */
+	else
+		clrsetbits_le32(&cgc1_regs->pll3div_pfd1, 0x3f3f3f3f, 0x01000000); /* Set PFD3 DIV1 to 389M, PFD3 DIV2 to 194M */
 	clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7));
 	clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15));
 	clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23));
@@ -182,6 +174,17 @@ void cgc1_pll3_init(ulong freq)
 	clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(23));
 	clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(31));
 
+	/* NIC_AP:
+	 * OD source PLL3 PFD0, 324M
+	 * ND source FRO192, 192M
+	 * LD source FRO192, 96M
+	*/
+	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
+		clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21);
+	} else {
+		clrbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21));
+	}
+
 	if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
 		/* nicclk select pll3 pfd0 */
 		clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(29, 28), BIT(28));
@@ -222,20 +225,9 @@ void cgc2_pll4_init(bool pll4_reset)
 
 	/* Enable all 4 PFDs */
 	setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */
-	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
-		setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8);
-		/* 99Mhz for NIC_LPAV */
-		clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 3 << 21);
-	} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
-		setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8);
-		/* 198Mhz for NIC_LPAV */
-		clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21);
-	} else {
-		setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
-		clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21));
-	}
-	setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16); /* 792 */
-	setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396 */
+	setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
+	setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 16); /* 316.8Mhz */
+	setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396Mhz */
 
 	clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) | BIT(15) | BIT(23) | BIT(31));
 
@@ -247,9 +239,22 @@ void cgc2_pll4_init(bool pll4_reset)
 	clrbits_le32(&cgc2_regs->pll4div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31));
 	clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31));
 
-	clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28));
-	while (!(readl(&cgc2_regs->niclpavclk) & BIT(27)))
-		;
+	/* NIC_LPAV:
+	 * OD source PLL4 PFD1, 316.8M
+	 * ND source FRO192, 192M
+	 * LD source FRO192, 96M
+	*/
+	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
+		clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21);
+	} else {
+		clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21));
+	}
+
+	if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+		clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28));
+		while (!(readl(&cgc2_regs->niclpavclk) & BIT(27)))
+			;
+	}
 }
 
 void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd)
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index 3e88f46..36d1294 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -182,37 +182,20 @@ void clock_init_late(void)
 	 */
 	cgc1_pll3_init(540672000);
 
-	if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
-		pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
-		pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD2_DIV2);
-		pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
-		pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
-
-		pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
-		pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV2);
-		pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
-		pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
-
-		pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
-		pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV2);
-		pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
-		pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
-	} else {
-		pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
-		pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2);
-		pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
-		pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
-
-		pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
-		pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1);
-		pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
-		pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
-
-		pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
-		pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1);
-		pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
-		pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
-	}
+	pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
+	pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD3_DIV1); /* 389M for OD, 194M for LD/ND*/
+	pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
+	pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
+
+	pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
+	pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD3_DIV2); /* 194M for OD, 97M for LD/ND */
+	pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
+	pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
+
+	pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
+	pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD3_DIV2); /* 194M for OD, 97M for LD/ND*/
+	pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
+	pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
 
 	/* enable MU0_MUB clock before access the register of MU0_MUB */
 	pcc_clock_enable(3, MU0_B_PCC3_SLOT, true);
@@ -425,6 +408,8 @@ void reset_lcdclk(void)
 	pcc_reset_peripheral(5, DCNANO_PCC5_SLOT, true);
 }
 
+/* PLL4 PFD0 max frequency */
+#define PLL4_PFD0_MAX_RATE 600000 /*khz*/
 void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz)
 {
 	u8 pcd, best_pcd = 0;
@@ -443,6 +428,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz)
 		for (div = 1; div <= 64; div++) {
 			parent_rate = pll4_rate;
 			parent_rate = parent_rate * 18 / pfd;
+			if (parent_rate > PLL4_PFD0_MAX_RATE)
+				continue;
+
 			parent_rate = parent_rate / div;
 
 			for (pcd = 0; pcd < 8; pcd++) {
-- 
2.7.4

[PATCH 15/23] imx: sentinel: Update S400 API get info message structure

[Ye Li]

From Sentinel FW v0.0.9-9df0f503, the response message of get info API
is changed to add OEM SRK and some states (IMEM, CSAL, TRNG).
With old structure, we get failure from sentinel due to the buffer
size can't fit with new response message. So update the API structure
to fix the issue.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/mach-imx/s400_api.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/mach-imx/s400_api.h b/arch/arm/include/asm/mach-imx/s400_api.h
index cb6e393..5582ff1 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -126,6 +126,8 @@ struct sentinel_get_info_data {
 	u32 uid[4];
 	u32 sha256_rom_patch[8];
 	u32 sha_fw[8];
+	u32 oem_srkh[16];
+	u32 state;
 };
 
 int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
-- 
2.7.4

[PATCH 16/23] misc: fuse: Update fuse mapping for 8ULP S400 API

[Ye Li]

Since new 8ULP A1 S400 FW (v0.0.8-e329b760) can support to read
more fuses: like PMU trim, Test flow/USB, GP1-5, GP8-10. Update
the u-boot driver for the new mapping.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
---
 drivers/misc/sentinel/fuse.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c
index e2b6875..aa691d3 100644
--- a/drivers/misc/sentinel/fuse.c
+++ b/drivers/misc/sentinel/fuse.c
@@ -67,6 +67,16 @@ struct s400_map_entry s400_api_mapping_table[] = {
 	{ 15, 8 }, /* OEM SRK HASH */
 	{ 23, 1, 4, 2 }, /* OTFAD */
 	{ 25, 8 }, /* Test config2 */
+	{ 26, 8 }, /* PMU */
+	{ 27, 8 }, /* Test flow/USB */
+	{ 32, 8 }, /* GP1 */
+	{ 33, 8 }, /* GP2 */
+	{ 34, 8 }, /* GP3 */
+	{ 35, 8 }, /* GP4 */
+	{ 36, 8 }, /* GP5 */
+	{ 49, 8 }, /* GP8 */
+	{ 50, 8 }, /* GP9 */
+	{ 51, 8 }, /* GP10 */
 };
 #elif defined(CONFIG_ARCH_IMX9)
 #define FSB_OTP_SHADOW	0x8000
-- 
2.7.4

[PATCH 17/23] misc: fuse: Lock 8ULP ECC-protected fuse when programming

[Ye Li]

The ECC fuse on 8ULP can't be written twice. If any user did it, the
ECC value would be wrong then cause accessing problem to the fuse.
The patch will lock the ECC fuse word to avoid this problem.
For iMX9, the OTP controller automatically prevents an ECC fuse word to
be written twice. So it does not need the setting.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/misc/sentinel/fuse.c | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c
index aa691d3..99342d3 100644
--- a/drivers/misc/sentinel/fuse.c
+++ b/drivers/misc/sentinel/fuse.c
@@ -60,6 +60,11 @@ struct fsb_map_entry fsb_mapping_table[] = {
 	{ 46, 8 },
 };
 
+/* None ECC banks such like Redundancy or Bit protect */
+u32 nonecc_fuse_banks[] = {
+	0, 1, 8, 12, 16, 22, 24, 25, 26, 27, 36, 41, 51, 56
+};
+
 struct s400_map_entry s400_api_mapping_table[] = {
 	{ 1, 8 },	/* LOCK */
 	{ 2, 8 },	/* ECID */
@@ -280,11 +285,26 @@ int fuse_prog(u32 bank, u32 word, u32 val)
 {
 	u32 res;
 	int ret;
+	bool lock = false;
 
 	if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
 		return -EINVAL;
 
-	ret = ahab_write_fuse((bank * 8 + word), val, false, &res);
+	/* Lock 8ULP ECC fuse word, so second programming will return failure.
+	 * iMX9 OTP can protect ECC fuse, so not need it
+	 */
+#if defined(CONFIG_IMX8ULP)
+	u32 i;
+	for (i = 0; i < ARRAY_SIZE(nonecc_fuse_banks); i++) {
+		if (nonecc_fuse_banks[i] == bank)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(nonecc_fuse_banks))
+		lock = true;
+#endif
+
+	ret = ahab_write_fuse((bank * 8 + word), val, lock, &res);
 	if (ret) {
 		printf("ahab write fuse failed %d, 0x%x\n", ret, res);
 		return ret;
-- 
2.7.4

[PATCH 18/23] ddr: imx: Update the ddr init flow on imx8ulp

[Ye Li]

From: Jacky Bai <ping.bai@nxp.com>

Update the ddr init flow to support LPDDR3 and PLL bypass mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
 drivers/ddr/imx/imx8ulp/ddr_init.c | 55 +++++++++++++++++++++++++++++---------
 1 file changed, 43 insertions(+), 12 deletions(-)

diff --git a/drivers/ddr/imx/imx8ulp/ddr_init.c b/drivers/ddr/imx/imx8ulp/ddr_init.c
index a5a9fd8..c362a2d 100644
--- a/drivers/ddr/imx/imx8ulp/ddr_init.c
+++ b/drivers/ddr/imx/imx8ulp/ddr_init.c
@@ -31,6 +31,7 @@
 #define DENALI_CTL_25		(DDR_CTL_BASE_ADDR + 4 * 25)
 
 #define DENALI_PHY_1624		(DDR_PHY_BASE_ADDR + 4 * 1624)
+#define DENALI_PHY_1625  	(DDR_PHY_BASE_ADDR + 4 * 1625)
 #define DENALI_PHY_1537		(DDR_PHY_BASE_ADDR + 4 * 1537)
 #define PHY_FREQ_SEL_MULTICAST_EN(X)	((X) << 8)
 #define PHY_FREQ_SEL_INDEX(X)		((X) << 16)
@@ -82,25 +83,39 @@ int ddr_calibration(unsigned int fsp_table[3])
 	u32 int_status_init, phy_freq_req, phy_freq_type;
 	u32 lock_0, lock_1, lock_2;
 	u32 freq_chg_pt, freq_chg_cnt;
+	u32 is_lpddr4 = 0;
 
 	if (IS_ENABLED(CONFIG_IMX8ULP_DRAM_PHY_PLL_BYPASS)) {
 		ddr_enable_pll_bypass();
 		freq_chg_cnt = 0;
 		freq_chg_pt = 0;
 	} else {
-		reg_val = readl(DENALI_CTL_250);
-		if (((reg_val >> 16) & 0x3) == 1)
-			freq_chg_cnt = 2;
-		else
-			freq_chg_cnt = 3;
-
-		reg_val = readl(DENALI_PI_12);
-		if (reg_val == 0x3) {
-			freq_chg_pt = 1;
-		} else if (reg_val == 0x7) {
-			freq_chg_pt = 2;
+		reg_val = (readl(DENALI_CTL_00)>>8)&0xf;
+		if(reg_val == 0x7) {
+			/* LPDDR3 type */
+			set_ddr_clk(fsp_table[1] >> 1);
+			freq_chg_cnt = 0;
+			freq_chg_pt = 0;
+		} else if(reg_val == 0xb) {
+			/* LPDDR4/4x type */
+			is_lpddr4 = 1;
+			reg_val = readl(DENALI_CTL_250);
+			if (((reg_val >> 16) & 0x3) == 1)
+				freq_chg_cnt = 2;
+			else
+				freq_chg_cnt = 3;
+
+			reg_val = readl(DENALI_PI_12);
+			if(reg_val == 0x3)
+				freq_chg_pt = 1;
+			else if(reg_val == 0x7)
+				freq_chg_pt = 2;
+			else {
+				printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val);
+				return -1;
+			}
 		} else {
-			printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val);
+			printf("Incorrect DDR type configured!\r\n");
 			return -1;
 		}
 	}
@@ -179,6 +194,22 @@ int ddr_calibration(unsigned int fsp_table[3])
 	}
 
 	debug("De-Skew PLL is locked and ready\n");
+
+	/* Change LPDDR4 FREQ1 to bypass mode if it is lower than 200MHz */
+	if(is_lpddr4 && fsp_table[1] < 400) {
+		/* Set FREQ1 to bypass mode */
+		reg_val = PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(0);
+		writel(reg_val, DENALI_PHY_1537);
+
+		/* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */
+		reg_val =readl(DENALI_PHY_1624) | 0x1;
+		writel(reg_val, DENALI_PHY_1624);
+
+		/* DENALI_PHY_1625: bypass mode in PHY PLL */
+		reg_val =readl(DENALI_PHY_1625) & ~0xf;
+		writel(reg_val, DENALI_PHY_1625);
+	}
+
 	return 0;
 }
 
-- 
2.7.4

[PATCH 19/23] imx8ulp_evk: Update the DDR timing

[Ye Li]

From: Jacky Bai <ping.bai@nxp.com>

Update the dram timing to support PLL bypass mode
for F1.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
---
 board/freescale/imx8ulp_evk/lpddr4_timing.c | 204 ++++++++++++++--------------
 1 file changed, 102 insertions(+), 102 deletions(-)

diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c
index 0924099..1878ca5 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c
@@ -2,7 +2,7 @@
 /*
  * Copyright 2021 NXP
  *
- * Generated code from MX8M_DDR_tool
+ * Generated code from MX8ULP_DDR_tool
  *
  */
 
@@ -16,10 +16,10 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e06002c, 0x17702 },	/* 11 */
 	{ 0x2e060030, 0x5 },	/* 12 */
 	{ 0x2e060034, 0x61 },	/* 13 */
-	{ 0x2e060038, 0xce3f },	/* 14 */
-	{ 0x2e06003c, 0x80e70 },	/* 15 */
+	{ 0x2e060038, 0x4b00 },	/* 14 */
+	{ 0x2e06003c, 0x2edfa },	/* 15 */
 	{ 0x2e060040, 0x5 },	/* 16 */
-	{ 0x2e060044, 0x210 },	/* 17 */
+	{ 0x2e060044, 0xc0 },	/* 17 */
 	{ 0x2e060048, 0x19c7d },	/* 18 */
 	{ 0x2e06004c, 0x101cdf },	/* 19 */
 	{ 0x2e060050, 0x5 },	/* 20 */
@@ -31,56 +31,56 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e060068, 0xa },	/* 26 */
 	{ 0x2e06006c, 0x19 },	/* 27 */
 	{ 0x2e060078, 0x2020200 },	/* 30 */
-	{ 0x2e06007c, 0x160b },	/* 31 */
+	{ 0x2e06007c, 0x1604 },	/* 31 */
 	{ 0x2e060090, 0x10 },	/* 36 */
 	{ 0x2e0600a4, 0x40c040c },	/* 41 */
 	{ 0x2e0600a8, 0x8040614 },	/* 42 */
 	{ 0x2e0600ac, 0x604 },	/* 43 */
 	{ 0x2e0600b0, 0x3090003 },	/* 44 */
 	{ 0x2e0600b4, 0x40002 },	/* 45 */
-	{ 0x2e0600b8, 0xc0011 },	/* 46 */
-	{ 0x2e0600bc, 0xb0509 },	/* 47 */
+	{ 0x2e0600b8, 0x50008 },	/* 46 */
+	{ 0x2e0600bc, 0x40309 },	/* 47 */
 	{ 0x2e0600c0, 0x2106 },	/* 48 */
 	{ 0x2e0600c4, 0xa090017 },	/* 49 */
 	{ 0x2e0600c8, 0x8200016 },	/* 50 */
 	{ 0x2e0600cc, 0xa0a },	/* 51 */
 	{ 0x2e0600d0, 0x4000694 },	/* 52 */
 	{ 0x2e0600d4, 0xa0a0804 },	/* 53 */
-	{ 0x2e0600d8, 0x4002432 },	/* 54 */
+	{ 0x2e0600d8, 0x4000d29 },	/* 54 */
 	{ 0x2e0600dc, 0xa0a0804 },	/* 55 */
 	{ 0x2e0600e0, 0x4004864 },	/* 56 */
 	{ 0x2e0600e4, 0x2030404 },	/* 57 */
-	{ 0x2e0600e8, 0x5040400 },	/* 58 */
-	{ 0x2e0600ec, 0x80b0a06 },	/* 59 */
+	{ 0x2e0600e8, 0x4040400 },	/* 58 */
+	{ 0x2e0600ec, 0x80b0a04 },	/* 59 */
 	{ 0x2e0600f0, 0x7010100 },	/* 60 */
-	{ 0x2e0600f4, 0x4150b },	/* 61 */
+	{ 0x2e0600f4, 0x41507 },	/* 61 */
 	{ 0x2e0600fc, 0x1010000 },	/* 63 */
 	{ 0x2e060100, 0x1000000 },	/* 64 */
 	{ 0x2e060104, 0xe0403 },	/* 65 */
 	{ 0x2e060108, 0xb3 },	/* 66 */
-	{ 0x2e06010c, 0x4a },	/* 67 */
-	{ 0x2e060110, 0x3fd },	/* 68 */
+	{ 0x2e06010c, 0x1b },	/* 67 */
+	{ 0x2e060110, 0x16e },	/* 68 */
 	{ 0x2e060114, 0x94 },	/* 69 */
 	{ 0x2e060118, 0x803 },	/* 70 */
 	{ 0x2e06011c, 0x5 },	/* 71 */
 	{ 0x2e060120, 0x70000 },	/* 72 */
-	{ 0x2e060124, 0x25000f },	/* 73 */
-	{ 0x2e060128, 0x4a0078 },	/* 74 */
+	{ 0x2e060124, 0xe000f },	/* 73 */
+	{ 0x2e060128, 0x4a0026 },	/* 74 */
 	{ 0x2e06012c, 0x4000f9 },	/* 75 */
 	{ 0x2e060130, 0x120103 },	/* 76 */
 	{ 0x2e060134, 0x50005 },	/* 77 */
-	{ 0x2e060138, 0x8070005 },	/* 78 */
+	{ 0x2e060138, 0x7070005 },	/* 78 */
 	{ 0x2e06013c, 0x505010d },	/* 79 */
 	{ 0x2e060140, 0x101030a },	/* 80 */
 	{ 0x2e060144, 0x30a0505 },	/* 81 */
 	{ 0x2e060148, 0x5050101 },	/* 82 */
 	{ 0x2e06014c, 0x1030a },	/* 83 */
 	{ 0x2e060150, 0xe000e },	/* 84 */
-	{ 0x2e060154, 0x4c004c },	/* 85 */
+	{ 0x2e060154, 0x1c001c },	/* 85 */
 	{ 0x2e060158, 0x980098 },	/* 86 */
 	{ 0x2e06015c, 0x3050505 },	/* 87 */
 	{ 0x2e060160, 0x3010403 },	/* 88 */
-	{ 0x2e060164, 0x4050505 },	/* 89 */
+	{ 0x2e060164, 0x3050505 },	/* 89 */
 	{ 0x2e060168, 0x3010403 },	/* 90 */
 	{ 0x2e06016c, 0x8050505 },	/* 91 */
 	{ 0x2e060170, 0x3010403 },	/* 92 */
@@ -101,12 +101,12 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0601b4, 0x2cc0 },	/* 109 */
 	{ 0x2e0601b8, 0x2cc0 },	/* 110 */
 	{ 0x2e0601c0, 0x4e5 },	/* 112 */
-	{ 0x2e0601c4, 0xff40 },	/* 113 */
-	{ 0x2e0601c8, 0xff40 },	/* 114 */
-	{ 0x2e0601cc, 0xff40 },	/* 115 */
-	{ 0x2e0601d0, 0xff40 },	/* 116 */
-	{ 0x2e0601d4, 0xff40 },	/* 117 */
-	{ 0x2e0601dc, 0x1beb },	/* 119 */
+	{ 0x2e0601c4, 0x5b80 },	/* 113 */
+	{ 0x2e0601c8, 0x5b80 },	/* 114 */
+	{ 0x2e0601cc, 0x5b80 },	/* 115 */
+	{ 0x2e0601d0, 0x5b80 },	/* 116 */
+	{ 0x2e0601d4, 0x5b80 },	/* 117 */
+	{ 0x2e0601dc, 0xa02 },	/* 119 */
 	{ 0x2e0601e0, 0x200c0 },	/* 120 */
 	{ 0x2e0601e4, 0x200c0 },	/* 121 */
 	{ 0x2e0601e8, 0x200c0 },	/* 122 */
@@ -138,9 +138,9 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0602a8, 0xd0005 },	/* 170 */
 	{ 0x2e0602ac, 0x404 },	/* 171 */
 	{ 0x2e0602b0, 0xd },	/* 172 */
-	{ 0x2e0602b4, 0x1b0035 },	/* 173 */
-	{ 0x2e0602b8, 0x4040042 },	/* 174 */
-	{ 0x2e0602bc, 0x42 },	/* 175 */
+	{ 0x2e0602b4, 0xa0014 },	/* 173 */
+	{ 0x2e0602b8, 0x4040018 },	/* 174 */
+	{ 0x2e0602bc, 0x18 },	/* 175 */
 	{ 0x2e0602c0, 0x35006a },	/* 176 */
 	{ 0x2e0602c4, 0x4040084 },	/* 177 */
 	{ 0x2e0602c8, 0x84 },	/* 178 */
@@ -168,13 +168,13 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e060390, 0x30000 },	/* 228 */
 	{ 0x2e060394, 0x1000200 },	/* 229 */
 	{ 0x2e060398, 0x310040 },	/* 230 */
-	{ 0x2e06039c, 0x20002 },	/* 231 */
+	{ 0x2e06039c, 0x20008 },	/* 231 */
 	{ 0x2e0603a0, 0x400100 },	/* 232 */
-	{ 0x2e0603a4, 0x80108 },	/* 233 */
+	{ 0x2e0603a4, 0x80060 },	/* 233 */
 	{ 0x2e0603a8, 0x1000200 },	/* 234 */
 	{ 0x2e0603ac, 0x2100040 },	/* 235 */
 	{ 0x2e0603b0, 0x10 },	/* 236 */
-	{ 0x2e0603b4, 0xe0003 },	/* 237 */
+	{ 0x2e0603b4, 0x50003 },	/* 237 */
 	{ 0x2e0603b8, 0x100001b },	/* 238 */
 	{ 0x2e0603d8, 0xffff0b00 },	/* 246 */
 	{ 0x2e0603dc, 0x1010001 },	/* 247 */
@@ -399,7 +399,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0608ec, 0x1320001 },	/* 571 */
 	{ 0x2e0608f0, 0x13200 },	/* 572 */
 	{ 0x2e0608f4, 0x132 },	/* 573 */
-	{ 0x2e0608fc, 0x1d1b0000 },	/* 575 */
+	{ 0x2e0608fc, 0x1b1b0000 },	/* 575 */
 	{ 0x2e060900, 0x21 },	/* 576 */
 	{ 0x2e060904, 0xa },	/* 577 */
 	{ 0x2e060908, 0x166 },	/* 578 */
@@ -410,13 +410,13 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e06091c, 0x432 },	/* 583 */
 	{ 0x2e060920, 0xdfc },	/* 584 */
 	{ 0x2e060924, 0x204 },	/* 585 */
-	{ 0x2e060928, 0x7fa },	/* 586 */
+	{ 0x2e060928, 0x2dc },	/* 586 */
 	{ 0x2e06092c, 0x200 },	/* 587 */
 	{ 0x2e060930, 0x200 },	/* 588 */
 	{ 0x2e060934, 0x200 },	/* 589 */
 	{ 0x2e060938, 0x200 },	/* 590 */
-	{ 0x2e06093c, 0x17ee },	/* 591 */
-	{ 0x2e060940, 0x4fc4 },	/* 592 */
+	{ 0x2e06093c, 0x894 },	/* 591 */
+	{ 0x2e060940, 0x1c98 },	/* 592 */
 	{ 0x2e060944, 0x204 },	/* 593 */
 	{ 0x2e060948, 0x1006 },	/* 594 */
 	{ 0x2e06094c, 0x200 },	/* 595 */
@@ -438,7 +438,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e06098c, 0x2010000 },	/* 611 */
 	{ 0x2e060990, 0x6000200 },	/* 612 */
 	{ 0x2e060994, 0x3000a06 },	/* 613 */
-	{ 0x2e060998, 0x2000c06 },	/* 614 */
+	{ 0x2e060998, 0x2000c03 },	/* 614 */
 };
 
 /** PI settings **/
@@ -518,22 +518,22 @@ struct dram_cfg_param ddr_pi_cfg[] = {
 	{ 0x2e062260, 0x10001 },	/* 152 */
 	{ 0x2e062274, 0x401 },	/* 157 */
 	{ 0x2e06227c, 0x10000 },	/* 159 */
-	{ 0x2e062284, 0x6010000 },	/* 161 */
+	{ 0x2e062284, 0x2010000 },	/* 161 */
 	{ 0x2e062288, 0xb },	/* 162 */
 	{ 0x2e06228c, 0x34 },	/* 163 */
-	{ 0x2e062290, 0x36 },	/* 164 */
+	{ 0x2e062290, 0x34 },	/* 164 */
 	{ 0x2e062294, 0x2003c },	/* 165 */
 	{ 0x2e062298, 0x2000200 },	/* 166 */
 	{ 0x2e06229c, 0xc040c04 },	/* 167 */
 	{ 0x2e0622a0, 0xe1406 },	/* 168 */
 	{ 0x2e0622a4, 0xb3 },	/* 169 */
-	{ 0x2e0622a8, 0x4a },	/* 170 */
-	{ 0x2e0622ac, 0x3fd },	/* 171 */
+	{ 0x2e0622a8, 0x1b },	/* 170 */
+	{ 0x2e0622ac, 0x16e },	/* 171 */
 	{ 0x2e0622b0, 0x94 },	/* 172 */
 	{ 0x2e0622b4, 0x4000803 },	/* 173 */
 	{ 0x2e0622b8, 0x1010404 },	/* 174 */
 	{ 0x2e0622bc, 0x1501 },	/* 175 */
-	{ 0x2e0622c0, 0x1a0018 },	/* 176 */
+	{ 0x2e0622c0, 0x1a0016 },	/* 176 */
 	{ 0x2e0622c4, 0x1000100 },	/* 177 */
 	{ 0x2e0622c8, 0x100 },	/* 178 */
 	{ 0x2e0622d0, 0x5040303 },	/* 180 */
@@ -542,15 +542,15 @@ struct dram_cfg_param ddr_pi_cfg[] = {
 	{ 0x2e0622e8, 0x2060404 },	/* 186 */
 	{ 0x2e0622ec, 0x2020402 },	/* 187 */
 	{ 0x2e0622f0, 0x3102 },	/* 188 */
-	{ 0x2e0622f4, 0x340009 },	/* 189 */
-	{ 0x2e0622f8, 0x36000c },	/* 190 */
+	{ 0x2e0622f4, 0x320009 },	/* 189 */
+	{ 0x2e0622f8, 0x36000a },	/* 190 */
 	{ 0x2e0622fc, 0x101000e },	/* 191 */
 	{ 0x2e062300, 0xd0101 },	/* 192 */
-	{ 0x2e062304, 0x1004201 },	/* 193 */
+	{ 0x2e062304, 0x1001801 },	/* 193 */
 	{ 0x2e062308, 0x1000084 },	/* 194 */
 	{ 0x2e06230c, 0xe000e },	/* 195 */
-	{ 0x2e062310, 0x430100 },	/* 196 */
-	{ 0x2e062314, 0x1000043 },	/* 197 */
+	{ 0x2e062310, 0x190100 },	/* 196 */
+	{ 0x2e062314, 0x1000019 },	/* 197 */
 	{ 0x2e062318, 0x850085 },	/* 198 */
 	{ 0x2e06231c, 0x220f220f },	/* 199 */
 	{ 0x2e062320, 0x101220f },	/* 200 */
@@ -561,8 +561,8 @@ struct dram_cfg_param ddr_pi_cfg[] = {
 	{ 0x2e062334, 0xc01000 },	/* 205 */
 	{ 0x2e062338, 0xc01000 },	/* 206 */
 	{ 0x2e06233c, 0x21000 },	/* 207 */
-	{ 0x2e062340, 0x11000d },	/* 208 */
-	{ 0x2e062344, 0x140042 },	/* 209 */
+	{ 0x2e062340, 0x2000d },	/* 208 */
+	{ 0x2e062344, 0x140018 },	/* 209 */
 	{ 0x2e062348, 0x190084 },	/* 210 */
 	{ 0x2e06234c, 0x220f0056 },	/* 211 */
 	{ 0x2e062350, 0x101 },	/* 212 */
@@ -575,40 +575,40 @@ struct dram_cfg_param ddr_pi_cfg[] = {
 	{ 0x2e06236c, 0x5eb },	/* 219 */
 	{ 0x2e062370, 0x20010003 },	/* 220 */
 	{ 0x2e062374, 0x80a0a03 },	/* 221 */
-	{ 0x2e062378, 0x6090506 },	/* 222 */
-	{ 0x2e06237c, 0x2093 },	/* 223 */
-	{ 0x2e062380, 0x2001000c },	/* 224 */
-	{ 0x2e062384, 0x80a0a04 },	/* 225 */
+	{ 0x2e062378, 0x4090403 },	/* 222 */
+	{ 0x2e06237c, 0xbd8 },	/* 223 */
+	{ 0x2e062380, 0x20010005 },	/* 224 */
+	{ 0x2e062384, 0x80a0a03 },	/* 225 */
 	{ 0x2e062388, 0xb090a0c },	/* 226 */
 	{ 0x2e06238c, 0x4126 },	/* 227 */
 	{ 0x2e062390, 0x20020017 },	/* 228 */
 	{ 0x2e062394, 0xa0a08 },	/* 229 */
 	{ 0x2e062398, 0x166 },	/* 230 */
 	{ 0x2e06239c, 0xdfc },	/* 231 */
-	{ 0x2e0623a0, 0x7fa },	/* 232 */
-	{ 0x2e0623a4, 0x4fc4 },	/* 233 */
+	{ 0x2e0623a0, 0x2dc },	/* 232 */
+	{ 0x2e0623a4, 0x1c98 },	/* 233 */
 	{ 0x2e0623a8, 0x1006 },	/* 234 */
 	{ 0x2e0623ac, 0xa03c },	/* 235 */
-	{ 0x2e0623b0, 0x4c000e },	/* 236 */
+	{ 0x2e0623b0, 0x1c000e },	/* 236 */
 	{ 0x2e0623b4, 0x3030098 },	/* 237 */
 	{ 0x2e0623b8, 0x258103 },	/* 238 */
 	{ 0x2e0623bc, 0x17702 },	/* 239 */
 	{ 0x2e0623c0, 0x5 },	/* 240 */
 	{ 0x2e0623c4, 0x61 },	/* 241 */
 	{ 0x2e0623c8, 0xe },	/* 242 */
-	{ 0x2e0623cc, 0xce3f },	/* 243 */
-	{ 0x2e0623d0, 0x80e70 },	/* 244 */
+	{ 0x2e0623cc, 0x4b00 },	/* 243 */
+	{ 0x2e0623d0, 0x17702 },	/* 244 */
 	{ 0x2e0623d4, 0x5 },	/* 245 */
-	{ 0x2e0623d8, 0x210 },	/* 246 */
-	{ 0x2e0623dc, 0x4c },	/* 247 */
+	{ 0x2e0623d8, 0xc0 },	/* 246 */
+	{ 0x2e0623dc, 0x1c },	/* 247 */
 	{ 0x2e0623e0, 0x19c7d },	/* 248 */
-	{ 0x2e0623e4, 0x101cdf },	/* 249 */
+	{ 0x2e0623e4, 0x17702 },	/* 249 */
 	{ 0x2e0623e8, 0x5 },	/* 250 */
 	{ 0x2e0623ec, 0x420 },	/* 251 */
 	{ 0x2e0623f0, 0x1000098 },	/* 252 */
 	{ 0x2e0623f4, 0x310040 },	/* 253 */
-	{ 0x2e0623f8, 0x10002 },	/* 254 */
-	{ 0x2e0623fc, 0x1080040 },	/* 255 */
+	{ 0x2e0623f8, 0x10008 },	/* 254 */
+	{ 0x2e0623fc, 0x600040 },	/* 255 */
 	{ 0x2e062400, 0x10008 },	/* 256 */
 	{ 0x2e062404, 0x2100040 },	/* 257 */
 	{ 0x2e062408, 0x310 },	/* 258 */
@@ -706,18 +706,18 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064168, 0x1000000 },	/* 90 */
 	{ 0x2e06416c, 0x10001000 },	/* 91 */
 	{ 0x2e064170, 0xc043242 },	/* 92 */
-	{ 0x2e064174, 0xf0c1201 },	/* 93 */
+	{ 0x2e064174, 0xf0c0e01 },	/* 93 */
 	{ 0x2e064178, 0x1000140 },	/* 94 */
 	{ 0x2e06417c, 0xc000120 },	/* 95 */
-	{ 0x2e064180, 0x143 },	/* 96 */
+	{ 0x2e064180, 0x118 },	/* 96 */
 	{ 0x2e064184, 0x1000203 },	/* 97 */
 	{ 0x2e064188, 0x56417032 },	/* 98 */
 	{ 0x2e06418c, 0x8 },	/* 99 */
-	{ 0x2e064190, 0x2c302c3 },	/* 100 */
-	{ 0x2e064194, 0x2c302c3 },	/* 101 */
-	{ 0x2e064198, 0x2c302c3 },	/* 102 */
-	{ 0x2e06419c, 0x2c302c3 },	/* 103 */
-	{ 0x2e0641a0, 0x2c3 },	/* 104 */
+	{ 0x2e064190, 0x2980298 },	/* 100 */
+	{ 0x2e064194, 0x2980298 },	/* 101 */
+	{ 0x2e064198, 0x2980298 },	/* 102 */
+	{ 0x2e06419c, 0x2980298 },	/* 103 */
+	{ 0x2e0641a0, 0x298 },	/* 104 */
 	{ 0x2e0641a4, 0x8000 },	/* 105 */
 	{ 0x2e0641a8, 0x800080 },	/* 106 */
 	{ 0x2e0641ac, 0x800080 },	/* 107 */
@@ -727,7 +727,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e0641bc, 0x800080 },	/* 111 */
 	{ 0x2e0641c0, 0x800080 },	/* 112 */
 	{ 0x2e0641c4, 0x800080 },	/* 113 */
-	{ 0x2e0641c8, 0x6b0080 },	/* 114 */
+	{ 0x2e0641c8, 0x1940080 },	/* 114 */
 	{ 0x2e0641cc, 0x1a00001 },	/* 115 */
 	{ 0x2e0641d4, 0x10000 },	/* 117 */
 	{ 0x2e0641d8, 0x80200 },	/* 118 */
@@ -782,18 +782,18 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064568, 0x1000000 },	/* 346 */
 	{ 0x2e06456c, 0x10001000 },	/* 347 */
 	{ 0x2e064570, 0xc043242 },	/* 348 */
-	{ 0x2e064574, 0xf0c1201 },	/* 349 */
+	{ 0x2e064574, 0xf0c0e01 },	/* 349 */
 	{ 0x2e064578, 0x1000140 },	/* 350 */
 	{ 0x2e06457c, 0xc000120 },	/* 351 */
-	{ 0x2e064580, 0x143 },	/* 352 */
+	{ 0x2e064580, 0x118 },	/* 352 */
 	{ 0x2e064584, 0x1000203 },	/* 353 */
 	{ 0x2e064588, 0x30217465 },	/* 354 */
 	{ 0x2e06458c, 0x8 },	/* 355 */
-	{ 0x2e064590, 0x2c302c3 },	/* 356 */
-	{ 0x2e064594, 0x2c302c3 },	/* 357 */
-	{ 0x2e064598, 0x2c302c3 },	/* 358 */
-	{ 0x2e06459c, 0x2c302c3 },	/* 359 */
-	{ 0x2e0645a0, 0x2c3 },	/* 360 */
+	{ 0x2e064590, 0x2980298 },	/* 356 */
+	{ 0x2e064594, 0x2980298 },	/* 357 */
+	{ 0x2e064598, 0x2980298 },	/* 358 */
+	{ 0x2e06459c, 0x2980298 },	/* 359 */
+	{ 0x2e0645a0, 0x298 },	/* 360 */
 	{ 0x2e0645a4, 0x8000 },	/* 361 */
 	{ 0x2e0645a8, 0x800080 },	/* 362 */
 	{ 0x2e0645ac, 0x800080 },	/* 363 */
@@ -803,7 +803,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e0645bc, 0x800080 },	/* 367 */
 	{ 0x2e0645c0, 0x800080 },	/* 368 */
 	{ 0x2e0645c4, 0x800080 },	/* 369 */
-	{ 0x2e0645c8, 0x6b0080 },	/* 370 */
+	{ 0x2e0645c8, 0x1940080 },	/* 370 */
 	{ 0x2e0645cc, 0x1a00001 },	/* 371 */
 	{ 0x2e0645d4, 0x10000 },	/* 373 */
 	{ 0x2e0645d8, 0x80200 },	/* 374 */
@@ -859,18 +859,18 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064968, 0x1000000 },	/* 602 */
 	{ 0x2e06496c, 0x10001000 },	/* 603 */
 	{ 0x2e064970, 0xc043242 },	/* 604 */
-	{ 0x2e064974, 0xf0c1201 },	/* 605 */
+	{ 0x2e064974, 0xf0c0e01 },	/* 605 */
 	{ 0x2e064978, 0x1000140 },	/* 606 */
 	{ 0x2e06497c, 0xc000120 },	/* 607 */
-	{ 0x2e064980, 0x143 },	/* 608 */
+	{ 0x2e064980, 0x118 },	/* 608 */
 	{ 0x2e064984, 0x1000203 },	/* 609 */
 	{ 0x2e064988, 0x75436012 },	/* 610 */
 	{ 0x2e06498c, 0x8 },	/* 611 */
-	{ 0x2e064990, 0x2c302c3 },	/* 612 */
-	{ 0x2e064994, 0x2c302c3 },	/* 613 */
-	{ 0x2e064998, 0x2c302c3 },	/* 614 */
-	{ 0x2e06499c, 0x2c302c3 },	/* 615 */
-	{ 0x2e0649a0, 0x2c3 },	/* 616 */
+	{ 0x2e064990, 0x2980298 },	/* 612 */
+	{ 0x2e064994, 0x2980298 },	/* 613 */
+	{ 0x2e064998, 0x2980298 },	/* 614 */
+	{ 0x2e06499c, 0x2980298 },	/* 615 */
+	{ 0x2e0649a0, 0x298 },	/* 616 */
 	{ 0x2e0649a4, 0x8000 },	/* 617 */
 	{ 0x2e0649a8, 0x800080 },	/* 618 */
 	{ 0x2e0649ac, 0x800080 },	/* 619 */
@@ -880,7 +880,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e0649bc, 0x800080 },	/* 623 */
 	{ 0x2e0649c0, 0x800080 },	/* 624 */
 	{ 0x2e0649c4, 0x800080 },	/* 625 */
-	{ 0x2e0649c8, 0x6b0080 },	/* 626 */
+	{ 0x2e0649c8, 0x1940080 },	/* 626 */
 	{ 0x2e0649cc, 0x1a00001 },	/* 627 */
 	{ 0x2e0649d4, 0x10000 },	/* 629 */
 	{ 0x2e0649d8, 0x80200 },	/* 630 */
@@ -935,18 +935,18 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064d68, 0x1000000 },	/* 858 */
 	{ 0x2e064d6c, 0x10001000 },	/* 859 */
 	{ 0x2e064d70, 0xc043242 },	/* 860 */
-	{ 0x2e064d74, 0xf0c1201 },	/* 861 */
+	{ 0x2e064d74, 0xf0c0e01 },	/* 861 */
 	{ 0x2e064d78, 0x1000140 },	/* 862 */
 	{ 0x2e064d7c, 0xc000120 },	/* 863 */
-	{ 0x2e064d80, 0x143 },	/* 864 */
+	{ 0x2e064d80, 0x118 },	/* 864 */
 	{ 0x2e064d84, 0x1000203 },	/* 865 */
 	{ 0x2e064d88, 0x32017465 },	/* 866 */
 	{ 0x2e064d8c, 0x8 },	/* 867 */
-	{ 0x2e064d90, 0x2c302c3 },	/* 868 */
-	{ 0x2e064d94, 0x2c302c3 },	/* 869 */
-	{ 0x2e064d98, 0x2c302c3 },	/* 870 */
-	{ 0x2e064d9c, 0x2c302c3 },	/* 871 */
-	{ 0x2e064da0, 0x2c3 },	/* 872 */
+	{ 0x2e064d90, 0x2980298 },	/* 868 */
+	{ 0x2e064d94, 0x2980298 },	/* 869 */
+	{ 0x2e064d98, 0x2980298 },	/* 870 */
+	{ 0x2e064d9c, 0x2980298 },	/* 871 */
+	{ 0x2e064da0, 0x298 },	/* 872 */
 	{ 0x2e064da4, 0x8000 },	/* 873 */
 	{ 0x2e064da8, 0x800080 },	/* 874 */
 	{ 0x2e064dac, 0x800080 },	/* 875 */
@@ -956,7 +956,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e064dbc, 0x800080 },	/* 879 */
 	{ 0x2e064dc0, 0x800080 },	/* 880 */
 	{ 0x2e064dc4, 0x800080 },	/* 881 */
-	{ 0x2e064dc8, 0x6b0080 },	/* 882 */
+	{ 0x2e064dc8, 0x1940080 },	/* 882 */
 	{ 0x2e064dcc, 0x1a00001 },	/* 883 */
 	{ 0x2e064dd4, 0x10000 },	/* 885 */
 	{ 0x2e064dd8, 0x80200 },	/* 886 */
@@ -1034,7 +1034,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e065868, 0xf0f0f },	/* 1562 */
 	{ 0x2e06586c, 0x241342 },	/* 1563 */
 	{ 0x2e065874, 0x1020000 },	/* 1565 */
-	{ 0x2e065878, 0x701 },	/* 1566 */
+	{ 0x2e065878, 0x10701 },	/* 1566 */
 	{ 0x2e06587c, 0x54 },	/* 1567 */
 	{ 0x2e065880, 0x4102000 },	/* 1568 */
 	{ 0x2e065884, 0x24410 },	/* 1569 */
@@ -1047,7 +1047,7 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e0658a0, 0x4410 },	/* 1576 */
 	{ 0x2e0658a4, 0x4410 },	/* 1577 */
 	{ 0x2e0658b0, 0x60000 },	/* 1580 */
-	{ 0x2e0658b8, 0x66 },	/* 1582 */
+	{ 0x2e0658b8, 0x64 },	/* 1582 */
 	{ 0x2e0658bc, 0x10000 },	/* 1583 */
 	{ 0x2e0658c0, 0x8 },	/* 1584 */
 	{ 0x2e0658d8, 0x3000000 },	/* 1590 */
@@ -1064,8 +1064,8 @@ struct dram_cfg_param ddr_phy_f1_cfg[] = {
 	{ 0x2e065934, 0x40700 },	/* 1613 */
 	{ 0x2e06594c, 0x2 },	/* 1619 */
 	{ 0x2e065958, 0xf3c3 },	/* 1622 */
-	{ 0x2e065964, 0x11542 },	/* 1625 */
-	{ 0x2e065968, 0x30209bf },	/* 1626 */
+	{ 0x2e065964, 0x11742 },	/* 1625 */
+	{ 0x2e065968, 0x3020600 },	/* 1626 */
 	{ 0x2e06596c, 0x30000 },	/* 1627 */
 	{ 0x2e065970, 0x3000300 },	/* 1628 */
 	{ 0x2e065974, 0x3000300 },	/* 1629 */
@@ -1098,7 +1098,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
 	{ 0x2e064170, 0xc043e42 },	/* 92 */
 	{ 0x2e064174, 0xf0c1701 },	/* 93 */
 	{ 0x2e064180, 0x187 },	/* 96 */
-	{ 0x2e064184, 0x3010203 },	/* 97 */
+	{ 0x2e064184, 0x3200203 },	/* 97 */
 	{ 0x2e064190, 0x3070307 },	/* 100 */
 	{ 0x2e064194, 0x3070307 },	/* 101 */
 	{ 0x2e064198, 0x3070307 },	/* 102 */
@@ -1109,7 +1109,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
 	{ 0x2e064570, 0xc043e42 },	/* 348 */
 	{ 0x2e064574, 0xf0c1701 },	/* 349 */
 	{ 0x2e064580, 0x187 },	/* 352 */
-	{ 0x2e064584, 0x3010203 },	/* 353 */
+	{ 0x2e064584, 0x3200203 },	/* 353 */
 	{ 0x2e064590, 0x3070307 },	/* 356 */
 	{ 0x2e064594, 0x3070307 },	/* 357 */
 	{ 0x2e064598, 0x3070307 },	/* 358 */
@@ -1120,7 +1120,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
 	{ 0x2e064970, 0xc043e42 },	/* 604 */
 	{ 0x2e064974, 0xf0c1701 },	/* 605 */
 	{ 0x2e064980, 0x187 },	/* 608 */
-	{ 0x2e064984, 0x3010203 },	/* 609 */
+	{ 0x2e064984, 0x3200203 },	/* 609 */
 	{ 0x2e064990, 0x3070307 },	/* 612 */
 	{ 0x2e064994, 0x3070307 },	/* 613 */
 	{ 0x2e064998, 0x3070307 },	/* 614 */
@@ -1131,7 +1131,7 @@ struct dram_cfg_param ddr_phy_f2_cfg[] = {
 	{ 0x2e064d70, 0xc043e42 },	/* 860 */
 	{ 0x2e064d74, 0xf0c1701 },	/* 861 */
 	{ 0x2e064d80, 0x187 },	/* 864 */
-	{ 0x2e064d84, 0x3010203 },	/* 865 */
+	{ 0x2e064d84, 0x3200203 },	/* 865 */
 	{ 0x2e064d90, 0x3070307 },	/* 868 */
 	{ 0x2e064d94, 0x3070307 },	/* 869 */
 	{ 0x2e064d98, 0x3070307 },	/* 870 */
@@ -1154,5 +1154,5 @@ struct dram_timing_info2 dram_timing = {
 	.phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg),
 	.phy_f2_cfg = ddr_phy_f2_cfg,
 	.phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg),
-	.fsp_table = { 96, 528, 1056 },
+	.fsp_table = { 96, 192, 1056 },
 };
-- 
2.7.4

[PATCH 20/23] imx8ulp_evk: Change to use DDR driver

[Ye Li]

Remove the DDR initialization codes from board and enable the iMX8ULP
DDR driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
---
 arch/arm/mach-imx/imx8ulp/Kconfig      |   1 +
 board/freescale/imx8ulp_evk/Makefile   |   2 +-
 board/freescale/imx8ulp_evk/ddr_init.c | 207 ---------------------------------
 3 files changed, 2 insertions(+), 208 deletions(-)
 delete mode 100644 board/freescale/imx8ulp_evk/ddr_init.c

diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-imx/imx8ulp/Kconfig
index bbdeaac..c1c1aa0 100644
--- a/arch/arm/mach-imx/imx8ulp/Kconfig
+++ b/arch/arm/mach-imx/imx8ulp/Kconfig
@@ -20,6 +20,7 @@ config TARGET_IMX8ULP_EVK
 	bool "imx8ulp_evk"
 	select IMX8ULP
 	select SUPPORT_SPL
+	select IMX8ULP_DRAM
 
 endchoice
 
diff --git a/board/freescale/imx8ulp_evk/Makefile b/board/freescale/imx8ulp_evk/Makefile
index b6ca238..1cf148a 100644
--- a/board/freescale/imx8ulp_evk/Makefile
+++ b/board/freescale/imx8ulp_evk/Makefile
@@ -3,7 +3,7 @@
 obj-y   += imx8ulp_evk.o
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o ddr_init.o
+obj-y += spl.o
 ifdef CONFIG_IMX8ULP_ND_MODE
 obj-y += lpddr4_timing_264.o
 else
diff --git a/board/freescale/imx8ulp_evk/ddr_init.c b/board/freescale/imx8ulp_evk/ddr_init.c
deleted file mode 100644
index f4238d2..0000000
--- a/board/freescale/imx8ulp_evk/ddr_init.c
+++ /dev/null
@@ -1,207 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Copyright 2021 NXP
- */
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/ddr.h>
-#include <asm/arch/imx-regs.h>
-
-#define DENALI_CTL_00		(DDR_CTL_BASE_ADDR)
-#define CTL_START		0x1
-
-#define DENALI_CTL_03		(DDR_CTL_BASE_ADDR + 4 * 3)
-#define DENALI_CTL_197		(DDR_CTL_BASE_ADDR + 4 * 197)
-#define DENALI_CTL_250		(DDR_CTL_BASE_ADDR + 4 * 250)
-#define DENALI_CTL_251		(DDR_CTL_BASE_ADDR + 4 * 251)
-#define DENALI_CTL_266		(DDR_CTL_BASE_ADDR + 4 * 266)
-#define DFI_INIT_COMPLETE	0x2
-
-#define DENALI_CTL_614		(DDR_CTL_BASE_ADDR + 4 * 614)
-#define DENALI_CTL_615		(DDR_CTL_BASE_ADDR + 4 * 615)
-
-#define DENALI_PI_00		(DDR_PI_BASE_ADDR)
-#define PI_START		0x1
-
-#define DENALI_PI_04		(DDR_PI_BASE_ADDR + 4 * 4)
-#define DENALI_PI_11		(DDR_PI_BASE_ADDR + 4 * 11)
-#define DENALI_PI_12		(DDR_PI_BASE_ADDR + 4 * 12)
-#define DENALI_CTL_23		(DDR_CTL_BASE_ADDR + 4 * 23)
-#define DENALI_CTL_25		(DDR_CTL_BASE_ADDR + 4 * 25)
-
-#define DENALI_PHY_1624		(DDR_PHY_BASE_ADDR + 4 * 1624)
-#define DENALI_PHY_1537		(DDR_PHY_BASE_ADDR + 4 * 1537)
-#define PHY_FREQ_SEL_MULTICAST_EN(X)	((X) << 8)
-#define PHY_FREQ_SEL_INDEX(X)		((X) << 16)
-
-#define DENALI_PHY_1547		(DDR_PHY_BASE_ADDR + 4 * 1547)
-#define DENALI_PHY_1555		(DDR_PHY_BASE_ADDR + 4 * 1555)
-#define DENALI_PHY_1564		(DDR_PHY_BASE_ADDR + 4 * 1564)
-#define DENALI_PHY_1565		(DDR_PHY_BASE_ADDR + 4 * 1565)
-
-int ddr_calibration(unsigned int fsp_table[3])
-{
-	u32 reg_val;
-	u32 int_status_init, phy_freq_req, phy_freq_type;
-	u32 lock_0, lock_1, lock_2;
-	u32 freq_chg_pt, freq_chg_cnt;
-
-	reg_val = readl(DENALI_CTL_250);
-	if (((reg_val >> 16) & 0x3) == 1)
-		freq_chg_cnt = 2;
-	else
-		freq_chg_cnt = 3;
-
-	reg_val = readl(DENALI_PI_12);
-	if (reg_val == 0x3) {
-		freq_chg_pt = 1;
-	} else if (reg_val == 0x7) {
-		freq_chg_pt = 2;
-	} else {
-		printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val);
-		return -1;
-	}
-
-	debug("%s\n", __func__);
-
-	/* Assert PI_START parameter and then assert START parameter in Controller. */
-	reg_val = readl(DENALI_PI_00) | PI_START;
-	writel(reg_val, DENALI_PI_00);
-
-	reg_val = readl(DENALI_CTL_00) | CTL_START;
-	writel(reg_val, DENALI_CTL_00);
-
-	/* Poll for init_done_bit in Controller interrupt status register (INT_STATUS_INIT) */
-	do {
-		if (!freq_chg_cnt) {
-			int_status_init = (readl(DENALI_CTL_266) >> 8) & 0xff;
-			/* DDR subsystem is ready for traffic. */
-			if (int_status_init & DFI_INIT_COMPLETE) {
-				printf("complete\n");
-				break;
-			}
-		}
-
-		/*
-		 * During leveling, PHY will request for freq change and SoC clock
-		 * logic should provide requested frequency, Polling SIM LPDDR_CTRL2
-		 * Bit phy_freq_chg_req until be 1'b1
-		 */
-		reg_val = readl(AVD_SIM_LPDDR_CTRL2);
-		phy_freq_req = (reg_val >> 7) & 0x1;
-
-		if (phy_freq_req) {
-			phy_freq_type = reg_val & 0x1F;
-			if (!phy_freq_type) {
-				printf("Poll for freq_chg_req on SIM register and change to F0 frequency.\n");
-				set_ddr_clk(fsp_table[phy_freq_type] >> 1);
-
-				/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
-				reg_val = readl(AVD_SIM_LPDDR_CTRL2);
-				writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
-			} else if (phy_freq_type == 0x01) {
-				printf("Poll for freq_chg_req on SIM register and change to F1 frequency.\n");
-				set_ddr_clk(fsp_table[phy_freq_type] >> 1);
-
-				/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
-				reg_val = readl(AVD_SIM_LPDDR_CTRL2);
-				writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
-				if (freq_chg_pt == 1)
-					freq_chg_cnt--;
-			} else if (phy_freq_type == 0x02) {
-				printf("Poll for freq_chg_req on SIM register and change to F2 frequency.\n");
-				set_ddr_clk(fsp_table[phy_freq_type] >> 1);
-
-				/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
-				reg_val = readl(AVD_SIM_LPDDR_CTRL2);
-				writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
-				if (freq_chg_pt == 2)
-					freq_chg_cnt--;
-			}
-			reg_val = readl(AVD_SIM_LPDDR_CTRL2);
-		}
-	} while (1);
-
-	/* Check PLL lock status */
-	lock_0 = readl(DENALI_PHY_1564) & 0xffff;
-	lock_1 = (readl(DENALI_PHY_1564) >> 16) & 0xffff;
-	lock_2 = readl(DENALI_PHY_1565) & 0xffff;
-
-	if ((lock_0 & 0x3) != 0x3 || (lock_1 & 0x3) != 0x3 || (lock_2 & 0x3) != 0x3) {
-		printf("De-Skew PLL failed to lock\n");
-		printf("lock_0=0x%x, lock_1=0x%x, lock_2=0x%x\n", lock_0, lock_1, lock_2);
-		return -1;
-	}
-
-	printf("De-Skew PLL is locked and ready\n");
-	return 0;
-}
-
-int ddr_init(struct dram_timing_info2 *dram_timing)
-{
-	int i;
-
-	debug("%s\n", __func__);
-
-	set_ddr_clk(dram_timing->fsp_table[0] >> 1); /* Set to boot freq */
-
-	/* Initialize CTL registers */
-	for (i = 0; i < dram_timing->ctl_cfg_num; i++)
-		writel(dram_timing->ctl_cfg[i].val, (ulong)dram_timing->ctl_cfg[i].reg);
-
-	/* Initialize PI registers */
-	for (i = 0; i < dram_timing->pi_cfg_num; i++)
-		writel(dram_timing->pi_cfg[i].val, (ulong)dram_timing->pi_cfg[i].reg);
-
-	/* Write PHY regiters for all 3 frequency points (48Mhz/384Mhz/528Mhz): f1_index=0 */
-	writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537);
-	for (i = 0; i < dram_timing->phy_f1_cfg_num; i++)
-		writel(dram_timing->phy_f1_cfg[i].val, (ulong)dram_timing->phy_f1_cfg[i].reg);
-
-	/* Write PHY regiters for freqency point 2 (528Mhz): f2_index=1 */
-	writel(PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(1), DENALI_PHY_1537);
-	for (i = 0; i < dram_timing->phy_f2_cfg_num; i++)
-		writel(dram_timing->phy_f2_cfg[i].val, (ulong)dram_timing->phy_f2_cfg[i].reg);
-
-	/* Re-enable MULTICAST mode */
-	writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537);
-
-	return ddr_calibration(dram_timing->fsp_table);
-}
-
-void enable_bypass_mode(void)
-{
-	u32 reg_val;
-
-	/* PI_INIT_LVL_EN=0x0 (DENALI_PI_04) */
-	reg_val = readl(DENALI_PI_04) & ~0x1;
-	writel(reg_val, DENALI_PI_04);
-
-	/* PI_FREQ_MAP=0x1 (DENALI_PI_12) */
-	writel(0x1, DENALI_PI_12);
-
-	/* PI_INIT_WORK_FREQ=0x0 (DENALI_PI_11) */
-	reg_val = readl(DENALI_PI_11) & ~(0x1f << 8);
-	writel(reg_val, DENALI_PI_11);
-
-	/* DFIBUS_FREQ_INIT=0x0 (DENALI_CTL_23) */
-	reg_val = readl(DENALI_CTL_23) & ~(0x3 << 24);
-	writel(reg_val, DENALI_CTL_23);
-
-	/* PHY_LP4_BOOT_DISABLE=0x0 (DENALI_PHY_1547) */
-	reg_val = readl(DENALI_PHY_1547) & ~(0x1 << 8);
-	writel(reg_val, DENALI_PHY_1547);
-
-	/* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */
-	reg_val = readl(DENALI_PHY_1624) | 0x1;
-	writel(reg_val, DENALI_PHY_1624);
-
-	/* PHY_LP4_BOOT_PLL_BYPASS to 0x1 (DENALI_PHY_1555) */
-	reg_val = readl(DENALI_PHY_1555) | 0x1;
-	writel(reg_val, DENALI_PHY_1555);
-
-	/* FREQ_CHANGE_TYPE_F0 = 0x0/FREQ_CHANGE_TYPE_F1 = 0x1/FREQ_CHANGE_TYPE_F2 = 0x2 */
-	reg_val = 0x020100;
-	writel(reg_val, DENALI_CTL_25);
-}
-- 
2.7.4

[PATCH 21/23] imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun

[Ye Li]

To resolve DCNANO underrun issue, change the DDR Port 0 arbitration
from round robin fashion to fixed priority level 1, while other ports
are not assigned any priority, so they will be serviced in round robin
fashion if there is no active request from Port 0.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8ulp_evk/lpddr4_timing.c     | 4 ++--
 board/freescale/imx8ulp_evk/lpddr4_timing_266.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c
index 1878ca5..e9edb87 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c
@@ -198,8 +198,8 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0604c8, 0x8000f00 },	/* 306 */
 	{ 0x2e0604cc, 0xa08 },	/* 307 */
 	{ 0x2e0604d0, 0x1010101 },	/* 308 */
-	{ 0x2e0604d4, 0x102 },	/* 309 */
-	{ 0x2e0604d8, 0x404 },	/* 310 */
+	{ 0x2e0604d4, 0x01000102 },	/* 309 */
+	{ 0x2e0604d8, 0x00000101 },	/* 310 */
 	{ 0x2e0604dc, 0x40400 },	/* 311 */
 	{ 0x2e0604e0, 0x4040000 },	/* 312 */
 	{ 0x2e0604e4, 0x4000000 },	/* 313 */
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
index e48cb96..9728a25 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
@@ -197,8 +197,8 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0604c8, 0x8000f00 },	/* 306 */
 	{ 0x2e0604cc, 0xa08 },	/* 307 */
 	{ 0x2e0604d0, 0x1010101 },	/* 308 */
-	{ 0x2e0604d4, 0x102 },	/* 309 */
-	{ 0x2e0604d8, 0x404 },	/* 310 */
+	{ 0x2e0604d4, 0x01000102 },	/* 309 */
+	{ 0x2e0604d8, 0x00000101 },	/* 310 */
 	{ 0x2e0604dc, 0x40400 },	/* 311 */
 	{ 0x2e0604e0, 0x4040000 },	/* 312 */
 	{ 0x2e0604e4, 0x4000000 },	/* 313 */
-- 
2.7.4

[PATCH 22/23] imx8ulp_evk: disable overflow of port0 for LPAV

[Ye Li]

From: Peng Fan <peng.fan@nxp.com>

Bit0: Port 0 behavior when bandwidth maximized. Set to 1 to allow overflow

With overflow set, we see some issue that A35 may not able to get enough
bandwidth and A35 will report hrtimer takes too much time, workqueue
lockup. With overflow cleared, the issues are gone.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8ulp_evk/lpddr4_timing.c     | 2 +-
 board/freescale/imx8ulp_evk/lpddr4_timing_266.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c
index e9edb87..6d28053 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c
@@ -396,7 +396,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0608e0, 0x30f0f },	/* 568 */
 	{ 0x2e0608e4, 0xffffffff },	/* 569 */
 	{ 0x2e0608e8, 0x32070f0f },	/* 570 */
-	{ 0x2e0608ec, 0x1320001 },	/* 571 */
+	{ 0x2e0608ec, 0x1320000 },	/* 571 */
 	{ 0x2e0608f0, 0x13200 },	/* 572 */
 	{ 0x2e0608f4, 0x132 },	/* 573 */
 	{ 0x2e0608fc, 0x1b1b0000 },	/* 575 */
diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
index 9728a25..7945760 100644
--- a/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
+++ b/board/freescale/imx8ulp_evk/lpddr4_timing_266.c
@@ -395,7 +395,7 @@ struct dram_cfg_param ddr_ctl_cfg[] = {
 	{ 0x2e0608e0, 0x30f0f },	/* 568 */
 	{ 0x2e0608e4, 0xffffffff },	/* 569 */
 	{ 0x2e0608e8, 0x32070f0f },	/* 570 */
-	{ 0x2e0608ec, 0x1320001 },	/* 571 */
+	{ 0x2e0608ec, 0x1320000 },	/* 571 */
 	{ 0x2e0608f0, 0x13200 },	/* 572 */
 	{ 0x2e0608f4, 0x132 },	/* 573 */
 	{ 0x2e0608fc, 0x1d1b0000 },	/* 575 */
-- 
2.7.4

[PATCH 23/23] imx8ulp_evk: Clear data at fdt_addr_r before booting kernel

[Ye Li]

When using dual boot mode, the DDR won't be reset when APD power off
or reboot. It has possibility that obsolete fdt data existing on
fdt_addr_r address. Then even nothing in EFI partitions, the distro boot
still continue to parse fdt and get uboot crashed.

Clear the data at fdt_addr_r, so the fdt header check in above case
will not pass.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 board/freescale/imx8ulp_evk/imx8ulp_evk.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
index b58f143..dd04d59 100644
--- a/board/freescale/imx8ulp_evk/imx8ulp_evk.c
+++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c
@@ -121,8 +121,16 @@ int board_early_init_f(void)
 
 int board_late_init(void)
 {
+	ulong addr;
+
 #if CONFIG_IS_ENABLED(ENV_IS_IN_MMC)
 	board_late_mmc_env_init();
 #endif
+
+	/* clear fdtaddr to avoid obsolete data */
+	addr = env_get_hex("fdt_addr_r", 0);
+	if (addr)
+		memset((void *)addr, 0, 0x400);
+
 	return 0;
 }
-- 
2.7.4

[PATCH 17/23] misc: fuse: Lock 8ULP ECC-protected fuse when programming

[sbabic]

> The ECC fuse on 8ULP can't be written twice. If any user did it, the
> ECC value would be wrong then cause accessing problem to the fuse.
> The patch will lock the ECC fuse word to avoid this problem.
> For iMX9, the OTP controller automatically prevents an ECC fuse word to
> be written twice. So it does not need the setting.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 16/23] misc: fuse: Update fuse mapping for 8ULP S400 API

[sbabic]

> Since new 8ULP A1 S400 FW (v0.0.8-e329b760) can support to read
> more fuses: like PMU trim, Test flow/USB, GP1-5, GP8-10. Update
> the u-boot driver for the new mapping.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Alice Guo <alice.guo@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 14/23] imx: imx8ulp: Update clocks to meet max rate restrictions

[sbabic]

> Update PLL3/PLL4 PFD and USDHC clocks to meet maximum frequency
> restrictions. Detail clock rate changes in the patch:
> PLL3 PFD2: 389M -> 324M
> PLL3 PFD3: 336M -> 389M
> PLL3 PFD3: DIV1 336M -> 389M (OD), 194M (ND/LD)
> PLL3 PFD3: DIV2 336M -> 194M (OD), 97M (ND/LD)
> PLL4 PFD0: 792M -> 594M
> PLL4 PFD2: 792M -> 316.8M
> NIC_AP:    96M (ND) -> 192M,  48M (LD) -> 96M
> NIC_LPAV:  198 (ND) -> 192M,  99M (LD) -> 96M
> USDHC0:    PLL3 PFD3 DIV1, 389M (OD), 194M (ND/LD)
> USDHC1:    PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD)
> USDHC2:    PLL3 PFD3 DIV2, 194M (OD), 97M (ND/LD)
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 05/23] imx: imx8ulp: Remove the TRDC configure from A35

[sbabic]

> As M33 is responsible for TRDC configuration, the settings for A35
> nonsecure world access and DMA0 access are moved to M33 image.
> So remove the codes to release TRDC and configure it. Just keep
> the configurations for reference.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 20/23] imx8ulp_evk: Change to use DDR driver

[sbabic]

> Remove the DDR initialization codes from board and enable the iMX8ULP
> DDR driver.
> Signed-off-by: Ye Li <ye.li@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 22/23] imx8ulp_evk: disable overflow of port0 for LPAV

[sbabic]

> From: Peng Fan <peng.fan@nxp.com>
> Bit0: Port 0 behavior when bandwidth maximized. Set to 1 to allow overflow
> With overflow set, we see some issue that A35 may not able to get enough
> bandwidth and A35 will report hrtimer takes too much time, workqueue
> lockup. With overflow cleared, the issues are gone.
> Reviewed-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 09/23] imx: imx8ulp: Reconfigure MRC3 for SRAM0 access

[sbabic]

> Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode
> access only for boot purpose. Since SW will reuse the SRAM0 as SCMI
> buffer and SPL container loading buffer, need to reconfigure MRC3.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 13/23] imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only

[sbabic]

> This patch is used to support DBD owner fuse changed to S400 only.
> The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not
> configured by S400 default setting.  So these PDAC and MSC are invalid,
> only DBD owner can access the corresponding resources.
> We have to configure necessary PDAC and MSC for SPL before DDR
> initialization.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 03/23] imx: imx8ulp: Limit the eMMC ROM API workaround to A0.1 part

[sbabic]

> Since A1 ROM has fixed the ROM API eMMC issue, we should only use
> the workaround for A0.1 part. Add a SOC revision check.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 01/23] imx: imx8ulp: Fix MU device probe failure

[sbabic]

> Since latest DTS has added multiple MU nodes, using compatible
> string to find the device node is not proper. It finds the first
> node with the compatible string matched even the node is disabled.
> Signed-off-by: Ye Li <ye.li@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 04/23] imx: imx8ulp: Set XRDC MRC4/5 for access DDR from APD

[sbabic]

> iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set
> them in SPL to allow access to DDR from A35 and APD PER masters
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 18/23] ddr: imx: Update the ddr init flow on imx8ulp

[sbabic]

> From: Jacky Bai <ping.bai@nxp.com>
> Update the ddr init flow to support LPDDR3 and PLL bypass mode.
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 21/23] imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun

[sbabic]

> To resolve DCNANO underrun issue, change the DDR Port 0 arbitration
> from round robin fashion to fixed priority level 1, while other ports
> are not assigned any priority, so they will be serviced in round robin
> fashion if there is no active request from Port 0.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Acked-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 07/23] imx: imx8ulp: configure XRDC for DRAM access from S400

[sbabic]

> Need to add DRAM access permission for S400, as S400 needs to access
> it When SPL calls image authentication
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 15/23] imx: sentinel: Update S400 API get info message structure

[sbabic]

> From Sentinel FW v0.0.9-9df0f503, the response message of get info API
> is changed to add OEM SRK and some states (IMEM, CSAL, TRNG).
> With old structure, we get failure from sentinel due to the buffer
> size can't fit with new response message. So update the API structure
> to fix the issue.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 08/23] ddr: imx8ulp: Change DRAM timing save area to 0x20055000

[sbabic]

> To align with ARM trusted firmware's change, adjust DRAM timing
> save area to new position 0x20055000. So we can release the space
> since 0x2006c000 for the NOBITS region of ARM trusted firmware
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 23/23] imx8ulp_evk: Clear data at fdt_addr_r before booting kernel

[sbabic]

> When using dual boot mode, the DDR won't be reset when APD power off
> or reboot. It has possibility that obsolete fdt data existing on
> fdt_addr_r address. Then even nothing in EFI partitions, the distro boot
> still continue to parse fdt and get uboot crashed.
> Clear the data at fdt_addr_r, so the fdt header check in above case
> will not pass.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 10/23] imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers

[sbabic]

> At present, in cgc1_pll3_init we don't set the pll3pfd div values,
> just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
> to 1 and pfd2div1 to 3.
> This finally causes some clocks' rate decreased, for example USDHC.
> So clear the PLL3DIV_PFD dividers to get correct rate.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 06/23] imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion

[sbabic]

> To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment.
> M33 will be the TRDC owner and needs to configure TRDC. A35 is the
> XRDC owner, ATF will configure XRDC.
> The handshake between U-boot and M33 image is used to sync TRDC and
> XRDC configuration completion. Once the handshake is done, A35 and M33
> can access the allowed resources in others domain.
> The handshake is needed when M33 is booted or DBD_EN fused, because both
> cases will enable the TRDC. If handshake is timeout, the boot will hang.
> We use SIM GPR0 to pass the info from SPL to u-boot, because before the
> handshake, u-boot can't access SEC SIM and FSB.
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 11/23] imx: imx8ulp: upower: replace magic number with macro

[sbabic]

> From: Peng Fan <peng.fan@nxp.com>
> The swton indicates the logic switch, magic number 0xfff80 is hard
> to understand, so use macro.
> Some board design may not have MIPI_CSI voltage input connected per
> data sheet. In that case, the upower power on API may dead loop mu to wait
> response, however there is no response. So remove MIPI_CSI here, let
> linux power domain driver to runtime enable the power domain.
> Reviewed-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 12/23] imx: imx8ulp: upower: make code cleaner

[sbabic]

> From: Peng Fan <peng.fan@nxp.com>
> To clean the upower codes by aligning codes format, check err_code
> and add detail bits list for the memory magic number
> Reviewed-by: Ye Li <ye.li@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 19/23] imx8ulp_evk: Update the DDR timing

[sbabic]

> From: Jacky Bai <ping.bai@nxp.com>
> Update the dram timing to support PLL bypass mode
> for F1.
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Reviewed-by: Ye Li <ye.li@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================

[PATCH 02/23] imx: imx8ulp: Get chip revision from Sentinel

[sbabic]

> In both SPL and u-boot, after probing the S400 MU, get the chip revision,
> lifecycle and UID from Sentinel.
> Update get_cpu_rev to use the chip revision not hard coded it for A0
> Signed-off-by: Ye Li <ye.li@nxp.com>
> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Applied to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de
=====================================================================