[PATCH v2 2/2] drm/amdgpu: Add MES KIQ clear to tell RLC that KIQ is dequeued

[PATCH v2 2/2] drm/amdgpu: Add MES KIQ clear to tell RLC that KIQ is dequeued

[Yifan Zha]

[Why]
As MES KIQ is dequeued, tell RLC that KIQ is inactive

[How]
Clear the RLC_CP_SCHEDULERS Active bit which RLC checks KIQ status
In addition, driver can halt MES under SRIOV when unloading driver

v2:
Use scheduler0 mask to clear KIQ portion of RLC_CP_SCHEDULERS

Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 4f0166a33732..67f7557d545d 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -1138,6 +1138,16 @@ static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
 	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
 }
 
+static void mes_v11_0_kiq_clear(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	/* tell RLC which is KIQ dequeue */
+	tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
+	tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK;
+	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
+}
+
 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
 {
 	int r = 0;
@@ -1182,10 +1192,10 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
 
 	if (amdgpu_sriov_vf(adev)) {
 		mes_v11_0_kiq_dequeue(&adev->gfx.kiq.ring);
+		mes_v11_0_kiq_clear(adev);
 	}
 
-	if (!amdgpu_sriov_vf(adev))
-		mes_v11_0_enable(adev, false);
+	mes_v11_0_enable(adev, false);
 
 	return 0;
 }
-- 
2.25.1

RE: [PATCH v2 2/2] drm/amdgpu: Add MES KIQ clear to tell RLC that KIQ is dequeued

[Chen, Horace]

[AMD Official Use Only - General]

Reviewed-By: Horace Chen <horace.chen@amd.com>

-----Original Message-----
From: Yifan Zha <Yifan.Zha@amd.com>
Sent: Monday, April 3, 2023 3:35 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander <Alexander.Deucher@amd.com>; Chen, Horace <Horace.Chen@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Chang, HaiJun <HaiJun.Chang@amd.com>
Cc: Zha, YiFan(Even) <Yifan.Zha@amd.com>
Subject: [PATCH v2 2/2] drm/amdgpu: Add MES KIQ clear to tell RLC that KIQ is dequeued

[Why]
As MES KIQ is dequeued, tell RLC that KIQ is inactive

[How]
Clear the RLC_CP_SCHEDULERS Active bit which RLC checks KIQ status
In addition, driver can halt MES under SRIOV when unloading driver

v2:
Use scheduler0 mask to clear KIQ portion of RLC_CP_SCHEDULERS

Signed-off-by: Yifan Zha <Yifan.Zha@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index 4f0166a33732..67f7557d545d 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -1138,6 +1138,16 @@ static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)
        WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
 }

+static void mes_v11_0_kiq_clear(struct amdgpu_device *adev)
+{
+       uint32_t tmp;
+
+       /* tell RLC which is KIQ dequeue */
+       tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
+       tmp &= ~RLC_CP_SCHEDULERS__scheduler0_MASK;
+       WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
+}
+
 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev)
 {
        int r = 0;
@@ -1182,10 +1192,10 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)

        if (amdgpu_sriov_vf(adev)) {
                mes_v11_0_kiq_dequeue(&adev->gfx.kiq.ring);
+               mes_v11_0_kiq_clear(adev);
        }

-       if (!amdgpu_sriov_vf(adev))
-               mes_v11_0_enable(adev, false);
+       mes_v11_0_enable(adev, false);

        return 0;
 }
--
2.25.1